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generic: ar8216: add chip_is_ar8{216,236,316,327} helpers
[openwrt/staging/chunkeey.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include "ar8216.h"
36
37 /* size of the vlan table */
38 #define AR8X16_MAX_VLANS 128
39 #define AR8X16_PROBE_RETRIES 10
40 #define AR8X16_MAX_PORTS 8
41
42 struct ar8216_priv;
43
44 #define AR8XXX_CAP_GIGE BIT(0)
45
46 struct ar8xxx_chip {
47 unsigned long caps;
48
49 int (*hw_init)(struct ar8216_priv *priv);
50 void (*init_globals)(struct ar8216_priv *priv);
51 void (*init_port)(struct ar8216_priv *priv, int port);
52 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
53 u32 ingress, u32 members, u32 pvid);
54 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
55 int (*atu_flush)(struct ar8216_priv *priv);
56 void (*vtu_flush)(struct ar8216_priv *priv);
57 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
58 };
59
60 struct ar8216_priv {
61 struct switch_dev dev;
62 struct phy_device *phy;
63 u32 (*read)(struct ar8216_priv *priv, int reg);
64 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
65 const struct net_device_ops *ndo_old;
66 struct net_device_ops ndo;
67 struct mutex reg_mutex;
68 int chip_type;
69 const struct ar8xxx_chip *chip;
70 bool initialized;
71 bool port4_phy;
72 char buf[80];
73
74 bool init;
75 bool mii_lo_first;
76
77 /* all fields below are cleared on reset */
78 bool vlan;
79 u16 vlan_id[AR8X16_MAX_VLANS];
80 u8 vlan_table[AR8X16_MAX_VLANS];
81 u8 vlan_tagged;
82 u16 pvid[AR8X16_MAX_PORTS];
83 };
84
85 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
86
87 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
88 {
89 return priv->chip->caps & AR8XXX_CAP_GIGE;
90 }
91
92 static inline bool chip_is_ar8216(struct ar8216_priv *priv)
93 {
94 return priv->chip_type == AR8216;
95 }
96
97 static inline bool chip_is_ar8236(struct ar8216_priv *priv)
98 {
99 return priv->chip_type == AR8236;
100 }
101
102 static inline bool chip_is_ar8316(struct ar8216_priv *priv)
103 {
104 return priv->chip_type == AR8316;
105 }
106
107 static inline bool chip_is_ar8327(struct ar8216_priv *priv)
108 {
109 return priv->chip_type == AR8327;
110 }
111
112 static inline void
113 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
114 {
115 regaddr >>= 1;
116 *r1 = regaddr & 0x1e;
117
118 regaddr >>= 5;
119 *r2 = regaddr & 0x7;
120
121 regaddr >>= 3;
122 *page = regaddr & 0x1ff;
123 }
124
125 static u32
126 ar8216_mii_read(struct ar8216_priv *priv, int reg)
127 {
128 struct phy_device *phy = priv->phy;
129 struct mii_bus *bus = phy->bus;
130 u16 r1, r2, page;
131 u16 lo, hi;
132
133 split_addr((u32) reg, &r1, &r2, &page);
134
135 mutex_lock(&bus->mdio_lock);
136
137 bus->write(bus, 0x18, 0, page);
138 usleep_range(1000, 2000); /* wait for the page switch to propagate */
139 lo = bus->read(bus, 0x10 | r2, r1);
140 hi = bus->read(bus, 0x10 | r2, r1 + 1);
141
142 mutex_unlock(&bus->mdio_lock);
143
144 return (hi << 16) | lo;
145 }
146
147 static void
148 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
149 {
150 struct phy_device *phy = priv->phy;
151 struct mii_bus *bus = phy->bus;
152 u16 r1, r2, r3;
153 u16 lo, hi;
154
155 split_addr((u32) reg, &r1, &r2, &r3);
156 lo = val & 0xffff;
157 hi = (u16) (val >> 16);
158
159 mutex_lock(&bus->mdio_lock);
160
161 bus->write(bus, 0x18, 0, r3);
162 usleep_range(1000, 2000); /* wait for the page switch to propagate */
163 if (priv->mii_lo_first) {
164 bus->write(bus, 0x10 | r2, r1, lo);
165 bus->write(bus, 0x10 | r2, r1 + 1, hi);
166 } else {
167 bus->write(bus, 0x10 | r2, r1 + 1, hi);
168 bus->write(bus, 0x10 | r2, r1, lo);
169 }
170
171 mutex_unlock(&bus->mdio_lock);
172 }
173
174 static void
175 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
176 u16 dbg_addr, u16 dbg_data)
177 {
178 struct mii_bus *bus = priv->phy->bus;
179
180 mutex_lock(&bus->mdio_lock);
181 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
182 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
183 mutex_unlock(&bus->mdio_lock);
184 }
185
186 static u32
187 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
188 {
189 u32 v;
190
191 lockdep_assert_held(&priv->reg_mutex);
192
193 v = priv->read(priv, reg);
194 v &= ~mask;
195 v |= val;
196 priv->write(priv, reg, v);
197
198 return v;
199 }
200
201 static void
202 ar8216_read_port_link(struct ar8216_priv *priv, int port,
203 struct switch_port_link *link)
204 {
205 u32 status;
206 u32 speed;
207
208 memset(link, '\0', sizeof(*link));
209
210 status = priv->chip->read_port_status(priv, port);
211
212 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
213 if (link->aneg) {
214 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
215 if (!link->link)
216 return;
217 } else {
218 link->link = true;
219 }
220
221 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
222 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
223 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
224
225 speed = (status & AR8216_PORT_STATUS_SPEED) >>
226 AR8216_PORT_STATUS_SPEED_S;
227
228 switch (speed) {
229 case AR8216_PORT_SPEED_10M:
230 link->speed = SWITCH_PORT_SPEED_10;
231 break;
232 case AR8216_PORT_SPEED_100M:
233 link->speed = SWITCH_PORT_SPEED_100;
234 break;
235 case AR8216_PORT_SPEED_1000M:
236 link->speed = SWITCH_PORT_SPEED_1000;
237 break;
238 default:
239 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
240 break;
241 }
242 }
243
244 static struct sk_buff *
245 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
246 {
247 struct ar8216_priv *priv = dev->phy_ptr;
248 unsigned char *buf;
249
250 if (unlikely(!priv))
251 goto error;
252
253 if (!priv->vlan)
254 goto send;
255
256 if (unlikely(skb_headroom(skb) < 2)) {
257 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
258 goto error;
259 }
260
261 buf = skb_push(skb, 2);
262 buf[0] = 0x10;
263 buf[1] = 0x80;
264
265 send:
266 return skb;
267
268 error:
269 dev_kfree_skb_any(skb);
270 return NULL;
271 }
272
273 static void
274 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
275 {
276 struct ar8216_priv *priv;
277 unsigned char *buf;
278 int port, vlan;
279
280 priv = dev->phy_ptr;
281 if (!priv)
282 return;
283
284 /* don't strip the header if vlan mode is disabled */
285 if (!priv->vlan)
286 return;
287
288 /* strip header, get vlan id */
289 buf = skb->data;
290 skb_pull(skb, 2);
291
292 /* check for vlan header presence */
293 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
294 return;
295
296 port = buf[0] & 0xf;
297
298 /* no need to fix up packets coming from a tagged source */
299 if (priv->vlan_tagged & (1 << port))
300 return;
301
302 /* lookup port vid from local table, the switch passes an invalid vlan id */
303 vlan = priv->vlan_id[priv->pvid[port]];
304
305 buf[14 + 2] &= 0xf0;
306 buf[14 + 2] |= vlan >> 8;
307 buf[15 + 2] = vlan & 0xff;
308 }
309
310 static int
311 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
312 {
313 int timeout = 20;
314 u32 t = 0;
315
316 while (1) {
317 t = priv->read(priv, reg);
318 if ((t & mask) == val)
319 return 0;
320
321 if (timeout-- <= 0)
322 break;
323
324 udelay(10);
325 }
326
327 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
328 (unsigned int) reg, t, mask, val);
329 return -ETIMEDOUT;
330 }
331
332 static void
333 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
334 {
335 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
336 return;
337 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
338 val &= AR8216_VTUDATA_MEMBER;
339 val |= AR8216_VTUDATA_VALID;
340 priv->write(priv, AR8216_REG_VTU_DATA, val);
341 }
342 op |= AR8216_VTU_ACTIVE;
343 priv->write(priv, AR8216_REG_VTU, op);
344 }
345
346 static void
347 ar8216_vtu_flush(struct ar8216_priv *priv)
348 {
349 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
350 }
351
352 static void
353 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
354 {
355 u32 op;
356
357 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
358 ar8216_vtu_op(priv, op, port_mask);
359 }
360
361 static int
362 ar8216_atu_flush(struct ar8216_priv *priv)
363 {
364 int ret;
365
366 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
367 if (!ret)
368 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
369
370 return ret;
371 }
372
373 static u32
374 ar8216_read_port_status(struct ar8216_priv *priv, int port)
375 {
376 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
377 }
378
379 static void
380 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
381 u32 members, u32 pvid)
382 {
383 u32 header;
384
385 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
386 header = AR8216_PORT_CTRL_HEADER;
387 else
388 header = 0;
389
390 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
391 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
392 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
393 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
394 AR8216_PORT_CTRL_LEARN | header |
395 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
396 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
397
398 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
399 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
400 AR8216_PORT_VLAN_DEFAULT_ID,
401 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
402 (ingress << AR8216_PORT_VLAN_MODE_S) |
403 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
404 }
405
406 static int
407 ar8216_hw_init(struct ar8216_priv *priv)
408 {
409 return 0;
410 }
411
412 static void
413 ar8216_init_globals(struct ar8216_priv *priv)
414 {
415 /* standard atheros magic */
416 priv->write(priv, 0x38, 0xc000050e);
417
418 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
419 AR8216_GCTRL_MTU, 1518 + 8 + 2);
420 }
421
422 static void
423 ar8216_init_port(struct ar8216_priv *priv, int port)
424 {
425 /* Enable port learning and tx */
426 priv->write(priv, AR8216_REG_PORT_CTRL(port),
427 AR8216_PORT_CTRL_LEARN |
428 (4 << AR8216_PORT_CTRL_STATE_S));
429
430 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
431
432 if (port == AR8216_PORT_CPU) {
433 priv->write(priv, AR8216_REG_PORT_STATUS(port),
434 AR8216_PORT_STATUS_LINK_UP |
435 (ar8xxx_has_gige(priv) ?
436 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
437 AR8216_PORT_STATUS_TXMAC |
438 AR8216_PORT_STATUS_RXMAC |
439 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
440 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
441 AR8216_PORT_STATUS_DUPLEX);
442 } else {
443 priv->write(priv, AR8216_REG_PORT_STATUS(port),
444 AR8216_PORT_STATUS_LINK_AUTO);
445 }
446 }
447
448 static const struct ar8xxx_chip ar8216_chip = {
449 .hw_init = ar8216_hw_init,
450 .init_globals = ar8216_init_globals,
451 .init_port = ar8216_init_port,
452 .setup_port = ar8216_setup_port,
453 .read_port_status = ar8216_read_port_status,
454 .atu_flush = ar8216_atu_flush,
455 .vtu_flush = ar8216_vtu_flush,
456 .vtu_load_vlan = ar8216_vtu_load_vlan,
457 };
458
459 static void
460 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
461 u32 members, u32 pvid)
462 {
463 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
464 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
465 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
466 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
467 AR8216_PORT_CTRL_LEARN |
468 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
469 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
470
471 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
472 AR8236_PORT_VLAN_DEFAULT_ID,
473 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
474
475 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
476 AR8236_PORT_VLAN2_VLAN_MODE |
477 AR8236_PORT_VLAN2_MEMBER,
478 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
479 (members << AR8236_PORT_VLAN2_MEMBER_S));
480 }
481
482 static int
483 ar8236_hw_init(struct ar8216_priv *priv)
484 {
485 int i;
486 struct mii_bus *bus;
487
488 if (priv->initialized)
489 return 0;
490
491 /* Initialize the PHYs */
492 bus = priv->phy->bus;
493 for (i = 0; i < 5; i++) {
494 mdiobus_write(bus, i, MII_ADVERTISE,
495 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
496 ADVERTISE_PAUSE_ASYM);
497 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
498 }
499 msleep(1000);
500
501 priv->initialized = true;
502 return 0;
503 }
504
505 static void
506 ar8236_init_globals(struct ar8216_priv *priv)
507 {
508 /* enable jumbo frames */
509 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
510 AR8316_GCTRL_MTU, 9018 + 8 + 2);
511 }
512
513 static const struct ar8xxx_chip ar8236_chip = {
514 .hw_init = ar8236_hw_init,
515 .init_globals = ar8236_init_globals,
516 .init_port = ar8216_init_port,
517 .setup_port = ar8236_setup_port,
518 .read_port_status = ar8216_read_port_status,
519 .atu_flush = ar8216_atu_flush,
520 .vtu_flush = ar8216_vtu_flush,
521 .vtu_load_vlan = ar8216_vtu_load_vlan,
522 };
523
524 static int
525 ar8316_hw_init(struct ar8216_priv *priv)
526 {
527 int i;
528 u32 val, newval;
529 struct mii_bus *bus;
530
531 val = priv->read(priv, 0x8);
532
533 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
534 if (priv->port4_phy) {
535 /* value taken from Ubiquiti RouterStation Pro */
536 newval = 0x81461bea;
537 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
538 } else {
539 newval = 0x01261be2;
540 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
541 }
542 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
543 /* value taken from AVM Fritz!Box 7390 sources */
544 newval = 0x010e5b71;
545 } else {
546 /* no known value for phy interface */
547 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
548 priv->phy->interface);
549 return -EINVAL;
550 }
551
552 if (val == newval)
553 goto out;
554
555 priv->write(priv, 0x8, newval);
556
557 /* Initialize the ports */
558 bus = priv->phy->bus;
559 for (i = 0; i < 5; i++) {
560 if ((i == 4) && priv->port4_phy &&
561 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
562 /* work around for phy4 rgmii mode */
563 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
564 /* rx delay */
565 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
566 /* tx delay */
567 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
568 msleep(1000);
569 }
570
571 /* initialize the port itself */
572 mdiobus_write(bus, i, MII_ADVERTISE,
573 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
574 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
575 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
576 msleep(1000);
577 }
578
579 out:
580 priv->initialized = true;
581 return 0;
582 }
583
584 static void
585 ar8316_init_globals(struct ar8216_priv *priv)
586 {
587 /* standard atheros magic */
588 priv->write(priv, 0x38, 0xc000050e);
589
590 /* enable cpu port to receive multicast and broadcast frames */
591 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
592
593 /* enable jumbo frames */
594 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
595 AR8316_GCTRL_MTU, 9018 + 8 + 2);
596 }
597
598 static const struct ar8xxx_chip ar8316_chip = {
599 .caps = AR8XXX_CAP_GIGE,
600 .hw_init = ar8316_hw_init,
601 .init_globals = ar8316_init_globals,
602 .init_port = ar8216_init_port,
603 .setup_port = ar8216_setup_port,
604 .read_port_status = ar8216_read_port_status,
605 .atu_flush = ar8216_atu_flush,
606 .vtu_flush = ar8216_vtu_flush,
607 .vtu_load_vlan = ar8216_vtu_load_vlan,
608 };
609
610 static u32
611 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
612 {
613 u32 t;
614
615 if (!cfg)
616 return 0;
617
618 t = 0;
619 switch (cfg->mode) {
620 case AR8327_PAD_NC:
621 break;
622
623 case AR8327_PAD_MAC2MAC_MII:
624 t = AR8327_PAD_MAC_MII_EN;
625 if (cfg->rxclk_sel)
626 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
627 if (cfg->txclk_sel)
628 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
629 break;
630
631 case AR8327_PAD_MAC2MAC_GMII:
632 t = AR8327_PAD_MAC_GMII_EN;
633 if (cfg->rxclk_sel)
634 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
635 if (cfg->txclk_sel)
636 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
637 break;
638
639 case AR8327_PAD_MAC_SGMII:
640 t = AR8327_PAD_SGMII_EN;
641 break;
642
643 case AR8327_PAD_MAC2PHY_MII:
644 t = AR8327_PAD_PHY_MII_EN;
645 if (cfg->rxclk_sel)
646 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
647 if (cfg->txclk_sel)
648 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
649 break;
650
651 case AR8327_PAD_MAC2PHY_GMII:
652 t = AR8327_PAD_PHY_GMII_EN;
653 if (cfg->pipe_rxclk_sel)
654 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
655 if (cfg->rxclk_sel)
656 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
657 if (cfg->txclk_sel)
658 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
659 break;
660
661 case AR8327_PAD_MAC_RGMII:
662 t = AR8327_PAD_RGMII_EN;
663 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
664 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
665 if (cfg->rxclk_delay_en)
666 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
667 if (cfg->txclk_delay_en)
668 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
669 break;
670
671 case AR8327_PAD_PHY_GMII:
672 t = AR8327_PAD_PHYX_GMII_EN;
673 break;
674
675 case AR8327_PAD_PHY_RGMII:
676 t = AR8327_PAD_PHYX_RGMII_EN;
677 break;
678
679 case AR8327_PAD_PHY_MII:
680 t = AR8327_PAD_PHYX_MII_EN;
681 break;
682 }
683
684 return t;
685 }
686
687 static int
688 ar8327_hw_init(struct ar8216_priv *priv)
689 {
690 struct ar8327_platform_data *pdata;
691 u32 t;
692 int i;
693
694 pdata = priv->phy->dev.platform_data;
695 if (!pdata)
696 return -EINVAL;
697
698 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
699 priv->write(priv, AR8327_REG_PAD0_MODE, t);
700 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
701 priv->write(priv, AR8327_REG_PAD5_MODE, t);
702 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
703 priv->write(priv, AR8327_REG_PAD6_MODE, t);
704
705 priv->write(priv, AR8327_REG_POWER_ON_STRIP, 0x40000000);
706
707 /* fixup PHYs */
708 for (i = 0; i < AR8327_NUM_PHYS; i++) {
709 /* For 100M waveform */
710 ar8216_phy_dbg_write(priv, i, 0, 0x02ea);
711
712 /* Turn on Gigabit clock */
713 ar8216_phy_dbg_write(priv, i, 0x3d, 0x68a0);
714 }
715
716 return 0;
717 }
718
719 static void
720 ar8327_init_globals(struct ar8216_priv *priv)
721 {
722 u32 t;
723
724 /* enable CPU port and disable mirror port */
725 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
726 AR8327_FWD_CTRL0_MIRROR_PORT;
727 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
728
729 /* forward multicast and broadcast frames to CPU */
730 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
731 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
732 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
733 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
734
735 /* setup MTU */
736 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
737 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
738 }
739
740 static void
741 ar8327_init_cpuport(struct ar8216_priv *priv)
742 {
743 struct ar8327_platform_data *pdata;
744 struct ar8327_port_cfg *cfg;
745 u32 t;
746
747 pdata = priv->phy->dev.platform_data;
748 if (!pdata)
749 return;
750
751 cfg = &pdata->cpuport_cfg;
752 if (!cfg->force_link) {
753 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
754 AR8216_PORT_STATUS_LINK_AUTO);
755 return;
756 }
757
758 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
759 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
760 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
761 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
762 switch (cfg->speed) {
763 case AR8327_PORT_SPEED_10:
764 t |= AR8216_PORT_SPEED_10M;
765 break;
766 case AR8327_PORT_SPEED_100:
767 t |= AR8216_PORT_SPEED_100M;
768 break;
769 case AR8327_PORT_SPEED_1000:
770 t |= AR8216_PORT_SPEED_1000M;
771 break;
772 }
773
774 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
775 }
776
777 static void
778 ar8327_init_port(struct ar8216_priv *priv, int port)
779 {
780 u32 t;
781
782 if (port == AR8216_PORT_CPU) {
783 ar8327_init_cpuport(priv);
784 } else {
785 t = AR8216_PORT_STATUS_LINK_AUTO;
786 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
787 }
788
789 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
790
791 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
792
793 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
794 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
795
796 t = AR8327_PORT_LOOKUP_LEARN;
797 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
798 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
799 }
800
801 static u32
802 ar8327_read_port_status(struct ar8216_priv *priv, int port)
803 {
804 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
805 }
806
807 static int
808 ar8327_atu_flush(struct ar8216_priv *priv)
809 {
810 int ret;
811
812 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
813 AR8327_ATU_FUNC_BUSY, 0);
814 if (!ret)
815 priv->write(priv, AR8327_REG_ATU_FUNC,
816 AR8327_ATU_FUNC_OP_FLUSH);
817
818 return ret;
819 }
820
821 static void
822 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
823 {
824 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
825 AR8327_VTU_FUNC1_BUSY, 0))
826 return;
827
828 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
829 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
830
831 op |= AR8327_VTU_FUNC1_BUSY;
832 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
833 }
834
835 static void
836 ar8327_vtu_flush(struct ar8216_priv *priv)
837 {
838 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
839 }
840
841 static void
842 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
843 {
844 u32 op;
845 u32 val;
846 int i;
847
848 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
849 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
850 for (i = 0; i < AR8327_NUM_PORTS; i++) {
851 u32 mode;
852
853 if ((port_mask & BIT(i)) == 0)
854 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
855 else if (priv->vlan == 0)
856 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
857 else if (priv->vlan_tagged & BIT(i))
858 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
859 else
860 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
861
862 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
863 }
864 ar8327_vtu_op(priv, op, val);
865 }
866
867 static void
868 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
869 u32 members, u32 pvid)
870 {
871 u32 t;
872 u32 mode;
873
874 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
875 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
876 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
877
878 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
879 switch (egress) {
880 case AR8216_OUT_KEEP:
881 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
882 break;
883 case AR8216_OUT_STRIP_VLAN:
884 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
885 break;
886 case AR8216_OUT_ADD_VLAN:
887 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
888 break;
889 }
890
891 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
892 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
893 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
894
895 t = members;
896 t |= AR8327_PORT_LOOKUP_LEARN;
897 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
898 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
899 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
900 }
901
902 static const struct ar8xxx_chip ar8327_chip = {
903 .caps = AR8XXX_CAP_GIGE,
904 .hw_init = ar8327_hw_init,
905 .init_globals = ar8327_init_globals,
906 .init_port = ar8327_init_port,
907 .setup_port = ar8327_setup_port,
908 .read_port_status = ar8327_read_port_status,
909 .atu_flush = ar8327_atu_flush,
910 .vtu_flush = ar8327_vtu_flush,
911 .vtu_load_vlan = ar8327_vtu_load_vlan,
912 };
913
914 static int
915 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
916 struct switch_val *val)
917 {
918 struct ar8216_priv *priv = to_ar8216(dev);
919 priv->vlan = !!val->value.i;
920 return 0;
921 }
922
923 static int
924 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
925 struct switch_val *val)
926 {
927 struct ar8216_priv *priv = to_ar8216(dev);
928 val->value.i = priv->vlan;
929 return 0;
930 }
931
932
933 static int
934 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
935 {
936 struct ar8216_priv *priv = to_ar8216(dev);
937
938 /* make sure no invalid PVIDs get set */
939
940 if (vlan >= dev->vlans)
941 return -EINVAL;
942
943 priv->pvid[port] = vlan;
944 return 0;
945 }
946
947 static int
948 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
949 {
950 struct ar8216_priv *priv = to_ar8216(dev);
951 *vlan = priv->pvid[port];
952 return 0;
953 }
954
955 static int
956 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
957 struct switch_val *val)
958 {
959 struct ar8216_priv *priv = to_ar8216(dev);
960 priv->vlan_id[val->port_vlan] = val->value.i;
961 return 0;
962 }
963
964 static int
965 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
966 struct switch_val *val)
967 {
968 struct ar8216_priv *priv = to_ar8216(dev);
969 val->value.i = priv->vlan_id[val->port_vlan];
970 return 0;
971 }
972
973 static int
974 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
975 struct switch_port_link *link)
976 {
977 struct ar8216_priv *priv = to_ar8216(dev);
978
979 ar8216_read_port_link(priv, port, link);
980 return 0;
981 }
982
983 static int
984 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
985 {
986 struct ar8216_priv *priv = to_ar8216(dev);
987 u8 ports = priv->vlan_table[val->port_vlan];
988 int i;
989
990 val->len = 0;
991 for (i = 0; i < dev->ports; i++) {
992 struct switch_port *p;
993
994 if (!(ports & (1 << i)))
995 continue;
996
997 p = &val->value.ports[val->len++];
998 p->id = i;
999 if (priv->vlan_tagged & (1 << i))
1000 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1001 else
1002 p->flags = 0;
1003 }
1004 return 0;
1005 }
1006
1007 static int
1008 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1009 {
1010 struct ar8216_priv *priv = to_ar8216(dev);
1011 u8 *vt = &priv->vlan_table[val->port_vlan];
1012 int i, j;
1013
1014 *vt = 0;
1015 for (i = 0; i < val->len; i++) {
1016 struct switch_port *p = &val->value.ports[i];
1017
1018 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1019 priv->vlan_tagged |= (1 << p->id);
1020 } else {
1021 priv->vlan_tagged &= ~(1 << p->id);
1022 priv->pvid[p->id] = val->port_vlan;
1023
1024 /* make sure that an untagged port does not
1025 * appear in other vlans */
1026 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1027 if (j == val->port_vlan)
1028 continue;
1029 priv->vlan_table[j] &= ~(1 << p->id);
1030 }
1031 }
1032
1033 *vt |= 1 << p->id;
1034 }
1035 return 0;
1036 }
1037
1038 static int
1039 ar8216_sw_hw_apply(struct switch_dev *dev)
1040 {
1041 struct ar8216_priv *priv = to_ar8216(dev);
1042 u8 portmask[AR8X16_MAX_PORTS];
1043 int i, j;
1044
1045 mutex_lock(&priv->reg_mutex);
1046 /* flush all vlan translation unit entries */
1047 priv->chip->vtu_flush(priv);
1048
1049 memset(portmask, 0, sizeof(portmask));
1050 if (!priv->init) {
1051 /* calculate the port destination masks and load vlans
1052 * into the vlan translation unit */
1053 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1054 u8 vp = priv->vlan_table[j];
1055
1056 if (!vp)
1057 continue;
1058
1059 for (i = 0; i < dev->ports; i++) {
1060 u8 mask = (1 << i);
1061 if (vp & mask)
1062 portmask[i] |= vp & ~mask;
1063 }
1064
1065 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1066 priv->vlan_table[j]);
1067 }
1068 } else {
1069 /* vlan disabled:
1070 * isolate all ports, but connect them to the cpu port */
1071 for (i = 0; i < dev->ports; i++) {
1072 if (i == AR8216_PORT_CPU)
1073 continue;
1074
1075 portmask[i] = 1 << AR8216_PORT_CPU;
1076 portmask[AR8216_PORT_CPU] |= (1 << i);
1077 }
1078 }
1079
1080 /* update the port destination mask registers and tag settings */
1081 for (i = 0; i < dev->ports; i++) {
1082 int egress, ingress;
1083 int pvid;
1084
1085 if (priv->vlan) {
1086 pvid = priv->vlan_id[priv->pvid[i]];
1087 if (priv->vlan_tagged & (1 << i))
1088 egress = AR8216_OUT_ADD_VLAN;
1089 else
1090 egress = AR8216_OUT_STRIP_VLAN;
1091 ingress = AR8216_IN_SECURE;
1092 } else {
1093 pvid = i;
1094 egress = AR8216_OUT_KEEP;
1095 ingress = AR8216_IN_PORT_ONLY;
1096 }
1097
1098 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1099 pvid);
1100 }
1101 mutex_unlock(&priv->reg_mutex);
1102 return 0;
1103 }
1104
1105 static int
1106 ar8216_sw_reset_switch(struct switch_dev *dev)
1107 {
1108 struct ar8216_priv *priv = to_ar8216(dev);
1109 int i;
1110
1111 mutex_lock(&priv->reg_mutex);
1112 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1113 offsetof(struct ar8216_priv, vlan));
1114
1115 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1116 priv->vlan_id[i] = i;
1117
1118 /* Configure all ports */
1119 for (i = 0; i < dev->ports; i++)
1120 priv->chip->init_port(priv, i);
1121
1122 priv->chip->init_globals(priv);
1123 mutex_unlock(&priv->reg_mutex);
1124
1125 return ar8216_sw_hw_apply(dev);
1126 }
1127
1128 static struct switch_attr ar8216_globals[] = {
1129 {
1130 .type = SWITCH_TYPE_INT,
1131 .name = "enable_vlan",
1132 .description = "Enable VLAN mode",
1133 .set = ar8216_sw_set_vlan,
1134 .get = ar8216_sw_get_vlan,
1135 .max = 1
1136 },
1137 };
1138
1139 static struct switch_attr ar8216_port[] = {
1140 };
1141
1142 static struct switch_attr ar8216_vlan[] = {
1143 {
1144 .type = SWITCH_TYPE_INT,
1145 .name = "vid",
1146 .description = "VLAN ID (0-4094)",
1147 .set = ar8216_sw_set_vid,
1148 .get = ar8216_sw_get_vid,
1149 .max = 4094,
1150 },
1151 };
1152
1153 static const struct switch_dev_ops ar8216_sw_ops = {
1154 .attr_global = {
1155 .attr = ar8216_globals,
1156 .n_attr = ARRAY_SIZE(ar8216_globals),
1157 },
1158 .attr_port = {
1159 .attr = ar8216_port,
1160 .n_attr = ARRAY_SIZE(ar8216_port),
1161 },
1162 .attr_vlan = {
1163 .attr = ar8216_vlan,
1164 .n_attr = ARRAY_SIZE(ar8216_vlan),
1165 },
1166 .get_port_pvid = ar8216_sw_get_pvid,
1167 .set_port_pvid = ar8216_sw_set_pvid,
1168 .get_vlan_ports = ar8216_sw_get_ports,
1169 .set_vlan_ports = ar8216_sw_set_ports,
1170 .apply_config = ar8216_sw_hw_apply,
1171 .reset_switch = ar8216_sw_reset_switch,
1172 .get_port_link = ar8216_sw_get_port_link,
1173 };
1174
1175 static int
1176 ar8216_id_chip(struct ar8216_priv *priv)
1177 {
1178 u32 val;
1179 u16 id;
1180 int i;
1181
1182 priv->chip_type = UNKNOWN;
1183
1184 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1185 if (val == ~0)
1186 return -ENODEV;
1187
1188 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1189 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1190 u16 t;
1191
1192 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1193 if (val == ~0)
1194 return -ENODEV;
1195
1196 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1197 if (t != id)
1198 return -ENODEV;
1199 }
1200
1201 switch (id) {
1202 case 0x0101:
1203 priv->chip_type = AR8216;
1204 priv->chip = &ar8216_chip;
1205 break;
1206 case 0x0301:
1207 priv->chip_type = AR8236;
1208 priv->chip = &ar8236_chip;
1209 break;
1210 case 0x1000:
1211 case 0x1001:
1212 priv->chip_type = AR8316;
1213 priv->chip = &ar8316_chip;
1214 break;
1215 case 0x1202:
1216 priv->chip_type = AR8327;
1217 priv->mii_lo_first = true;
1218 priv->chip = &ar8327_chip;
1219 break;
1220 default:
1221 printk(KERN_DEBUG
1222 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1223 (int)(id >> AR8216_CTRL_VERSION_S),
1224 (int)(id & AR8216_CTRL_REVISION),
1225 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1226 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1227
1228 return -ENODEV;
1229 }
1230
1231 return 0;
1232 }
1233
1234 static int
1235 ar8216_config_init(struct phy_device *pdev)
1236 {
1237 struct ar8216_priv *priv = pdev->priv;
1238 struct net_device *dev = pdev->attached_dev;
1239 struct switch_dev *swdev;
1240 int ret;
1241
1242 if (!priv) {
1243 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1244 if (priv == NULL)
1245 return -ENOMEM;
1246 }
1247
1248 priv->phy = pdev;
1249
1250 ret = ar8216_id_chip(priv);
1251 if (ret)
1252 goto err_free_priv;
1253
1254 if (pdev->addr != 0) {
1255 if (ar8xxx_has_gige(priv)) {
1256 pdev->supported |= SUPPORTED_1000baseT_Full;
1257 pdev->advertising |= ADVERTISED_1000baseT_Full;
1258 }
1259
1260 if (chip_is_ar8316(priv)) {
1261 /* check if we're attaching to the switch twice */
1262 pdev = pdev->bus->phy_map[0];
1263 if (!pdev) {
1264 kfree(priv);
1265 return 0;
1266 }
1267
1268 /* switch device has not been initialized, reuse priv */
1269 if (!pdev->priv) {
1270 priv->port4_phy = true;
1271 pdev->priv = priv;
1272 return 0;
1273 }
1274
1275 kfree(priv);
1276
1277 /* switch device has been initialized, reinit */
1278 priv = pdev->priv;
1279 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1280 priv->initialized = false;
1281 priv->port4_phy = true;
1282 ar8316_hw_init(priv);
1283 return 0;
1284 }
1285
1286 kfree(priv);
1287 return 0;
1288 }
1289
1290 printk(KERN_INFO "%s: AR%d switch driver attached.\n",
1291 pdev->attached_dev->name, priv->chip_type);
1292
1293 if (ar8xxx_has_gige(priv))
1294 pdev->supported = SUPPORTED_1000baseT_Full;
1295 else
1296 pdev->supported = SUPPORTED_100baseT_Full;
1297 pdev->advertising = pdev->supported;
1298
1299 mutex_init(&priv->reg_mutex);
1300 priv->read = ar8216_mii_read;
1301 priv->write = ar8216_mii_write;
1302
1303 pdev->priv = priv;
1304
1305 swdev = &priv->dev;
1306 swdev->cpu_port = AR8216_PORT_CPU;
1307 swdev->ops = &ar8216_sw_ops;
1308 swdev->ports = AR8216_NUM_PORTS;
1309
1310 if (chip_is_ar8316(priv)) {
1311 swdev->name = "Atheros AR8316";
1312 swdev->vlans = AR8X16_MAX_VLANS;
1313
1314 if (priv->port4_phy) {
1315 /* port 5 connected to the other mac, therefore unusable */
1316 swdev->ports = (AR8216_NUM_PORTS - 1);
1317 }
1318 } else if (chip_is_ar8236(priv)) {
1319 swdev->name = "Atheros AR8236";
1320 swdev->vlans = AR8216_NUM_VLANS;
1321 swdev->ports = AR8216_NUM_PORTS;
1322 } else if (chip_is_ar8327(priv)) {
1323 swdev->name = "Atheros AR8327";
1324 swdev->vlans = AR8X16_MAX_VLANS;
1325 swdev->ports = AR8327_NUM_PORTS;
1326 } else {
1327 swdev->name = "Atheros AR8216";
1328 swdev->vlans = AR8216_NUM_VLANS;
1329 }
1330
1331 ret = register_switch(&priv->dev, pdev->attached_dev);
1332 if (ret)
1333 goto err_free_priv;
1334
1335 priv->init = true;
1336
1337 ret = priv->chip->hw_init(priv);
1338 if (ret)
1339 goto err_free_priv;
1340
1341 ret = ar8216_sw_reset_switch(&priv->dev);
1342 if (ret)
1343 goto err_free_priv;
1344
1345 dev->phy_ptr = priv;
1346
1347 /* VID fixup only needed on ar8216 */
1348 if (chip_is_ar8216(priv) && pdev->addr == 0) {
1349 dev->priv_flags |= IFF_NO_IP_ALIGN;
1350 dev->eth_mangle_rx = ar8216_mangle_rx;
1351 dev->eth_mangle_tx = ar8216_mangle_tx;
1352 }
1353
1354 priv->init = false;
1355
1356 return 0;
1357
1358 err_free_priv:
1359 kfree(priv);
1360 return ret;
1361 }
1362
1363 static int
1364 ar8216_read_status(struct phy_device *phydev)
1365 {
1366 struct ar8216_priv *priv = phydev->priv;
1367 struct switch_port_link link;
1368 int ret;
1369
1370 if (phydev->addr != 0)
1371 return genphy_read_status(phydev);
1372
1373 ar8216_read_port_link(priv, phydev->addr, &link);
1374 phydev->link = !!link.link;
1375 if (!phydev->link)
1376 return 0;
1377
1378 switch (link.speed) {
1379 case SWITCH_PORT_SPEED_10:
1380 phydev->speed = SPEED_10;
1381 break;
1382 case SWITCH_PORT_SPEED_100:
1383 phydev->speed = SPEED_100;
1384 break;
1385 case SWITCH_PORT_SPEED_1000:
1386 phydev->speed = SPEED_1000;
1387 break;
1388 default:
1389 phydev->speed = 0;
1390 }
1391 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1392
1393 /* flush the address translation unit */
1394 mutex_lock(&priv->reg_mutex);
1395 ret = priv->chip->atu_flush(priv);
1396 mutex_unlock(&priv->reg_mutex);
1397
1398 phydev->state = PHY_RUNNING;
1399 netif_carrier_on(phydev->attached_dev);
1400 phydev->adjust_link(phydev->attached_dev);
1401
1402 return ret;
1403 }
1404
1405 static int
1406 ar8216_config_aneg(struct phy_device *phydev)
1407 {
1408 if (phydev->addr == 0)
1409 return 0;
1410
1411 return genphy_config_aneg(phydev);
1412 }
1413
1414 static int
1415 ar8216_probe(struct phy_device *pdev)
1416 {
1417 struct ar8216_priv priv;
1418
1419 priv.phy = pdev;
1420 return ar8216_id_chip(&priv);
1421 }
1422
1423 static void
1424 ar8216_remove(struct phy_device *pdev)
1425 {
1426 struct ar8216_priv *priv = pdev->priv;
1427 struct net_device *dev = pdev->attached_dev;
1428
1429 if (!priv)
1430 return;
1431
1432 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1433 dev->eth_mangle_rx = NULL;
1434 dev->eth_mangle_tx = NULL;
1435
1436 if (pdev->addr == 0)
1437 unregister_switch(&priv->dev);
1438 kfree(priv);
1439 }
1440
1441 static struct phy_driver ar8216_driver = {
1442 .phy_id = 0x004d0000,
1443 .name = "Atheros AR8216/AR8236/AR8316",
1444 .phy_id_mask = 0xffff0000,
1445 .features = PHY_BASIC_FEATURES,
1446 .probe = ar8216_probe,
1447 .remove = ar8216_remove,
1448 .config_init = &ar8216_config_init,
1449 .config_aneg = &ar8216_config_aneg,
1450 .read_status = &ar8216_read_status,
1451 .driver = { .owner = THIS_MODULE },
1452 };
1453
1454 int __init
1455 ar8216_init(void)
1456 {
1457 return phy_driver_register(&ar8216_driver);
1458 }
1459
1460 void __exit
1461 ar8216_exit(void)
1462 {
1463 phy_driver_unregister(&ar8216_driver);
1464 }
1465
1466 module_init(ar8216_init);
1467 module_exit(ar8216_exit);
1468 MODULE_LICENSE("GPL");
1469
Staging tree of Christian Lamparter