ar8216: Fix problem with AR8337 MAC swap handling
[openwrt/staging/chunkeey.git] / target / linux / generic / files / include / linux / ar8216_platform.h
1 /*
2 * AR8216 switch driver platform data
3 *
4 * Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef AR8216_PLATFORM_H
18 #define AR8216_PLATFORM_H
19
20 enum ar8327_pad_mode {
21 AR8327_PAD_NC = 0,
22 AR8327_PAD_MAC2MAC_MII,
23 AR8327_PAD_MAC2MAC_GMII,
24 AR8327_PAD_MAC_SGMII,
25 AR8327_PAD_MAC2PHY_MII,
26 AR8327_PAD_MAC2PHY_GMII,
27 AR8327_PAD_MAC_RGMII,
28 AR8327_PAD_PHY_GMII,
29 AR8327_PAD_PHY_RGMII,
30 AR8327_PAD_PHY_MII,
31 };
32
33 enum ar8327_clk_delay_sel {
34 AR8327_CLK_DELAY_SEL0 = 0,
35 AR8327_CLK_DELAY_SEL1,
36 AR8327_CLK_DELAY_SEL2,
37 AR8327_CLK_DELAY_SEL3,
38 };
39
40 struct ar8327_pad_cfg {
41 enum ar8327_pad_mode mode;
42 bool rxclk_sel;
43 bool txclk_sel;
44 bool pipe_rxclk_sel;
45 bool txclk_delay_en;
46 bool rxclk_delay_en;
47 bool sgmii_delay_en;
48 enum ar8327_clk_delay_sel txclk_delay_sel;
49 enum ar8327_clk_delay_sel rxclk_delay_sel;
50 bool mac06_exchange_en;
51 };
52
53 enum ar8327_port_speed {
54 AR8327_PORT_SPEED_10 = 0,
55 AR8327_PORT_SPEED_100,
56 AR8327_PORT_SPEED_1000,
57 };
58
59 struct ar8327_port_cfg {
60 int force_link:1;
61 enum ar8327_port_speed speed;
62 int txpause:1;
63 int rxpause:1;
64 int duplex:1;
65 };
66
67 struct ar8327_sgmii_cfg {
68 u32 sgmii_ctrl;
69 bool serdes_aen;
70 };
71
72 struct ar8327_led_cfg {
73 u32 led_ctrl0;
74 u32 led_ctrl1;
75 u32 led_ctrl2;
76 u32 led_ctrl3;
77 bool open_drain;
78 };
79
80 enum ar8327_led_num {
81 AR8327_LED_PHY0_0 = 0,
82 AR8327_LED_PHY0_1,
83 AR8327_LED_PHY0_2,
84 AR8327_LED_PHY1_0,
85 AR8327_LED_PHY1_1,
86 AR8327_LED_PHY1_2,
87 AR8327_LED_PHY2_0,
88 AR8327_LED_PHY2_1,
89 AR8327_LED_PHY2_2,
90 AR8327_LED_PHY3_0,
91 AR8327_LED_PHY3_1,
92 AR8327_LED_PHY3_2,
93 AR8327_LED_PHY4_0,
94 AR8327_LED_PHY4_1,
95 AR8327_LED_PHY4_2,
96 };
97
98 enum ar8327_led_mode {
99 AR8327_LED_MODE_HW = 0,
100 AR8327_LED_MODE_SW,
101 };
102
103 struct ar8327_led_info {
104 const char *name;
105 const char *default_trigger;
106 bool active_low;
107 enum ar8327_led_num led_num;
108 enum ar8327_led_mode mode;
109 };
110
111 #define AR8327_LED_INFO(_led, _mode, _name) { \
112 .name = (_name), \
113 .led_num = AR8327_LED_ ## _led, \
114 .mode = AR8327_LED_MODE_ ## _mode \
115 }
116
117 struct ar8327_platform_data {
118 struct ar8327_pad_cfg *pad0_cfg;
119 struct ar8327_pad_cfg *pad5_cfg;
120 struct ar8327_pad_cfg *pad6_cfg;
121 struct ar8327_sgmii_cfg *sgmii_cfg;
122 struct ar8327_port_cfg port0_cfg;
123 struct ar8327_port_cfg port6_cfg;
124 struct ar8327_led_cfg *led_cfg;
125
126 int (*get_port_link)(unsigned port);
127
128 unsigned num_leds;
129 const struct ar8327_led_info *leds;
130 };
131
132 #endif /* AR8216_PLATFORM_H */
133