target/linux/generic/patches-4.9/076-v4.11-0004-net-phy-bcm7xxx-Implement-EGPHY-workaround-for-7278.patch

   1 From: Florian Fainelli <f.fainelli@gmail.com>
   2 Date: Fri, 20 Jan 2017 12:36:34 -0800
   3 Subject: [PATCH] net: phy: bcm7xxx: Implement EGPHY workaround for 7278
   4
   5 Implement the HW design team recommended workaround in for 7278. Since
   6 the GPHY now returns its revision information in MII_PHYS_ID[23] we need
   7 to check whether the revision provided in flags is 0 or not.
   8
   9 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  10 Signed-off-by: David S. Miller <davem@davemloft.net>
  11 ---
  12
  13 --- a/drivers/net/phy/bcm7xxx.c
  14 +++ b/drivers/net/phy/bcm7xxx.c
  15 @@ -163,12 +163,43 @@ static int bcm7xxx_28nm_e0_plus_afe_conf
  16         return 0;
  17  }
  18
  19 +static int bcm7xxx_28nm_a0_patch_afe_config_init(struct phy_device *phydev)
  20 +{
  21 +       /* +1 RC_CAL codes for RL centering for both LT and HT conditions */
  22 +       bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0xd003);
  23 +
  24 +       /* Cut master bias current by 2% to compensate for RC_CAL offset */
  25 +       bcm_phy_write_misc(phydev, DSP_TAP10, 0x791b);
  26 +
  27 +       /* Improve hybrid leakage */
  28 +       bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x10e3);
  29 +
  30 +       /* Change rx_on_tune 8 to 0xf */
  31 +       bcm_phy_write_misc(phydev, 0x21, 0x2, 0x87f6);
  32 +
  33 +       /* Change 100Tx EEE bandwidth */
  34 +       bcm_phy_write_misc(phydev, 0x22, 0x2, 0x017d);
  35 +
  36 +       /* Enable ffe zero detection for Vitesse interoperability */
  37 +       bcm_phy_write_misc(phydev, 0x26, 0x2, 0x0015);
  38 +
  39 +       r_rc_cal_reset(phydev);
  40 +
  41 +       return 0;
  42 +}
  43 +
  44  static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
  45  {
  46         u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
  47         u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
  48         int ret = 0;
  49
  50 +       /* Newer devices have moved the revision information back into a
  51 +        * standard location in MII_PHYS_ID[23]
  52 +        */
  53 +       if (rev == 0)
  54 +               rev = phydev->phy_id & ~phydev->drv->phy_id_mask;
  55 +
  56         pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
  57                      phydev_name(phydev), phydev->drv->name, rev, patch);
  58
  59 @@ -192,6 +223,9 @@ static int bcm7xxx_28nm_config_init(stru
  60         case 0x10:
  61                 ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
  62                 break;
  63 +       case 0x01:
  64 +               ret = bcm7xxx_28nm_a0_patch_afe_config_init(phydev);
  65 +               break;
  66         default:
  67                 break;
  68         }