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[openwrt/staging/chunkeey.git] / target / linux / ipq40xx / files-4.19 / drivers / net / dsa / qca8k.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 */
8
9 #include <linux/module.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <net/dsa.h>
13 #include <linux/of_net.h>
14 #include <linux/of_platform.h>
15 #include <linux/if_bridge.h>
16 #include <linux/mdio.h>
17 #include <linux/etherdevice.h>
18 #include <linux/clk.h>
19 #include <linux/reset.h>
20 #include <linux/mdio.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/of_mdio.h>
23 #include <linux/workqueue.h>
24
25 #include "qca8k.h"
26
27 #define MIB_DESC(_s, _o, _n) \
28 { \
29 .size = (_s), \
30 .offset = (_o), \
31 .name = (_n), \
32 }
33
34 static const struct qca8k_mib_desc ar8327_mib[] = {
35 MIB_DESC(1, 0x00, "RxBroad"),
36 MIB_DESC(1, 0x04, "RxPause"),
37 MIB_DESC(1, 0x08, "RxMulti"),
38 MIB_DESC(1, 0x0c, "RxFcsErr"),
39 MIB_DESC(1, 0x10, "RxAlignErr"),
40 MIB_DESC(1, 0x14, "RxRunt"),
41 MIB_DESC(1, 0x18, "RxFragment"),
42 MIB_DESC(1, 0x1c, "Rx64Byte"),
43 MIB_DESC(1, 0x20, "Rx128Byte"),
44 MIB_DESC(1, 0x24, "Rx256Byte"),
45 MIB_DESC(1, 0x28, "Rx512Byte"),
46 MIB_DESC(1, 0x2c, "Rx1024Byte"),
47 MIB_DESC(1, 0x30, "Rx1518Byte"),
48 MIB_DESC(1, 0x34, "RxMaxByte"),
49 MIB_DESC(1, 0x38, "RxTooLong"),
50 MIB_DESC(2, 0x3c, "RxGoodByte"),
51 MIB_DESC(2, 0x44, "RxBadByte"),
52 MIB_DESC(1, 0x4c, "RxOverFlow"),
53 MIB_DESC(1, 0x50, "Filtered"),
54 MIB_DESC(1, 0x54, "TxBroad"),
55 MIB_DESC(1, 0x58, "TxPause"),
56 MIB_DESC(1, 0x5c, "TxMulti"),
57 MIB_DESC(1, 0x60, "TxUnderRun"),
58 MIB_DESC(1, 0x64, "Tx64Byte"),
59 MIB_DESC(1, 0x68, "Tx128Byte"),
60 MIB_DESC(1, 0x6c, "Tx256Byte"),
61 MIB_DESC(1, 0x70, "Tx512Byte"),
62 MIB_DESC(1, 0x74, "Tx1024Byte"),
63 MIB_DESC(1, 0x78, "Tx1518Byte"),
64 MIB_DESC(1, 0x7c, "TxMaxByte"),
65 MIB_DESC(1, 0x80, "TxOverSize"),
66 MIB_DESC(2, 0x84, "TxByte"),
67 MIB_DESC(1, 0x8c, "TxCollision"),
68 MIB_DESC(1, 0x90, "TxAbortCol"),
69 MIB_DESC(1, 0x94, "TxMultiCol"),
70 MIB_DESC(1, 0x98, "TxSingleCol"),
71 MIB_DESC(1, 0x9c, "TxExcDefer"),
72 MIB_DESC(1, 0xa0, "TxDefer"),
73 MIB_DESC(1, 0xa4, "TxLateCol"),
74 };
75
76
77 static u32
78 qca8k_read(struct qca8k_priv *priv, u32 reg)
79 {
80 unsigned int val;
81
82 regmap_read(priv->base, reg, &val);
83 return val;
84 }
85
86 static void
87 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
88 {
89 regmap_write(priv->base, reg, val);
90 }
91
92 static u32
93 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
94 {
95 u32 ret;
96
97 ret = qca8k_read(priv, reg);
98 ret &= ~mask;
99 ret |= val;
100 qca8k_write(priv, reg, ret);
101
102 return ret;
103 }
104
105 static void
106 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
107 {
108 qca8k_rmw(priv, reg, 0, val);
109 }
110
111 static void
112 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
113 {
114 qca8k_rmw(priv, reg, val, 0);
115 }
116
117 static int
118 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
119 {
120 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
121
122 *val = qca8k_read(priv, reg);
123
124 return 0;
125 }
126
127 static int
128 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
129 {
130 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
131
132 qca8k_write(priv, reg, val);
133
134 return 0;
135 }
136
137 static const struct regmap_range qca8k_readable_ranges[] = {
138 regmap_reg_range(0x0000, 0x00e4), /* Global control */
139 regmap_reg_range(0x0100, 0x0168), /* EEE control */
140 regmap_reg_range(0x0200, 0x0270), /* Parser control */
141 regmap_reg_range(0x0400, 0x0454), /* ACL */
142 regmap_reg_range(0x0600, 0x0718), /* Lookup */
143 regmap_reg_range(0x0800, 0x0b70), /* QM */
144 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
145 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
146 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
147 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
148 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
149 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
150 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
151 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
152 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
153
154 };
155
156 static const struct regmap_access_table qca8k_readable_table = {
157 .yes_ranges = qca8k_readable_ranges,
158 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
159 };
160
161 static struct regmap_config qca8k_regmap_config = {
162 .reg_bits = 16,
163 .val_bits = 32,
164 .reg_stride = 4,
165 .max_register = 0x16ac, /* end MIB - Port6 range */
166 .reg_read = qca8k_regmap_read,
167 .reg_write = qca8k_regmap_write,
168 .rd_table = &qca8k_readable_table,
169 };
170
171 static int
172 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
173 {
174 unsigned long timeout;
175
176 timeout = jiffies + msecs_to_jiffies(20);
177
178 /* loop until the busy flag has cleared */
179 do {
180 u32 val = qca8k_read(priv, reg);
181 int busy = val & mask;
182
183 if (!busy)
184 break;
185 cond_resched();
186 } while (!time_after_eq(jiffies, timeout));
187
188 return time_after_eq(jiffies, timeout);
189 }
190
191 static void
192 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
193 {
194 u32 reg[4];
195 int i;
196
197 /* load the ARL table into an array */
198 for (i = 0; i < 4; i++)
199 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
200
201 /* vid - 83:72 */
202 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
203 /* aging - 67:64 */
204 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
205 /* portmask - 54:48 */
206 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
207 /* mac - 47:0 */
208 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
209 fdb->mac[1] = reg[1] & 0xff;
210 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
211 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
212 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
213 fdb->mac[5] = reg[0] & 0xff;
214 }
215
216 static void
217 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
218 u8 aging)
219 {
220 u32 reg[3] = { 0 };
221 int i;
222
223 /* vid - 83:72 */
224 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
225 /* aging - 67:64 */
226 reg[2] |= aging & QCA8K_ATU_STATUS_M;
227 /* portmask - 54:48 */
228 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
229 /* mac - 47:0 */
230 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
231 reg[1] |= mac[1];
232 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
233 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
234 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
235 reg[0] |= mac[5];
236
237 /* load the array into the ARL table */
238 for (i = 0; i < 3; i++)
239 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
240 }
241
242 static int
243 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
244 {
245 u32 reg;
246
247 /* Set the command and FDB index */
248 reg = QCA8K_ATU_FUNC_BUSY;
249 reg |= cmd;
250 if (port >= 0) {
251 reg |= QCA8K_ATU_FUNC_PORT_EN;
252 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
253 }
254
255 /* Write the function register triggering the table access */
256 qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
257
258 /* wait for completion */
259 if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
260 return -1;
261
262 /* Check for table full violation when adding an entry */
263 if (cmd == QCA8K_FDB_LOAD) {
264 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
265 if (reg & QCA8K_ATU_FUNC_FULL)
266 return -1;
267 }
268
269 return 0;
270 }
271
272 static int
273 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
274 {
275 int ret;
276
277 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
278 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
279 if (ret >= 0)
280 qca8k_fdb_read(priv, fdb);
281
282 return ret;
283 }
284
285 static int
286 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
287 u16 vid, u8 aging)
288 {
289 int ret;
290
291 mutex_lock(&priv->reg_mutex);
292 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
293 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
294 mutex_unlock(&priv->reg_mutex);
295
296 return ret;
297 }
298
299 static int
300 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
301 {
302 int ret;
303
304 mutex_lock(&priv->reg_mutex);
305 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
306 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
307 mutex_unlock(&priv->reg_mutex);
308
309 return ret;
310 }
311
312 static void
313 qca8k_fdb_flush(struct qca8k_priv *priv)
314 {
315 mutex_lock(&priv->reg_mutex);
316 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
317 mutex_unlock(&priv->reg_mutex);
318 }
319
320 static void
321 qca8k_mib_init(struct qca8k_priv *priv)
322 {
323 mutex_lock(&priv->reg_mutex);
324 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
325 qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
326 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
327 qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
328 mutex_unlock(&priv->reg_mutex);
329 }
330
331 static int
332 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
333 {
334 u32 reg;
335
336 switch (port) {
337 case 0:
338 reg = QCA8K_REG_PORT0_PAD_CTRL;
339 break;
340 case 6:
341 reg = QCA8K_REG_PORT6_PAD_CTRL;
342 break;
343 default:
344 pr_err("Can't set PAD_CTRL on port %d\n", port);
345 return -EINVAL;
346 }
347
348 /* Configure a port to be directly connected to an external
349 * PHY or MAC.
350 */
351 switch (mode) {
352 case PHY_INTERFACE_MODE_RGMII:
353 qca8k_write(priv, reg,
354 QCA8K_PORT_PAD_RGMII_EN |
355 QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
356 QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
357
358 /* According to the datasheet, RGMII delay is enabled through
359 * PORT5_PAD_CTRL for all ports, rather than individual port
360 * registers
361 */
362 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
363 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
364 break;
365 case PHY_INTERFACE_MODE_SGMII:
366 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
367 break;
368 case PHY_INTERFACE_MODE_INTERNAL:
369 break;
370 default:
371 pr_err("xMII mode %d not supported\n", mode);
372 return -EINVAL;
373 }
374
375 return 0;
376 }
377
378 static void
379 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
380 {
381 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
382
383 /* Port 0 and 6 have no internal PHY */
384 if (port > 0 && port < 6 && priv->mac_mode != 3)
385 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
386
387 if (enable)
388 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
389 else
390 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
391 }
392
393 static int
394 qca8k_setup(struct dsa_switch *ds)
395 {
396 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
397 int ret, i, phy_mode = -1;
398 u32 mask;
399
400 /* Make sure that port 0 is the cpu port */
401 if (!dsa_is_cpu_port(ds, 0)) {
402 pr_err("port 0 is not the CPU port\n");
403 return -EINVAL;
404 }
405
406 mutex_init(&priv->reg_mutex);
407
408 /* Start by setting up the register mapping */
409 priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
410 &qca8k_regmap_config);
411 if (IS_ERR(priv->regmap))
412 pr_warn("regmap initialization failed");
413
414 /* Initialize CPU port pad mode (xMII type, delays...) */
415 phy_mode = of_get_phy_mode(ds->ports[QCA8K_CPU_PORT].dn);
416 if (phy_mode < 0) {
417 pr_err("Can't find phy-mode for master device\n");
418 return phy_mode;
419 }
420 ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
421 if (ret < 0)
422 return ret;
423
424 /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
425 mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW | QCA8K_PORT_TXHALF_FLOW |
426 QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
427 qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
428 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
429 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
430 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
431 priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
432
433 /* Enable MIB counters */
434 qca8k_mib_init(priv);
435
436 /* Disable buggy AZ */
437 qca8k_write(priv, QCA8K_REG_EEE_CTRL, 0);
438
439 /* enable jumbo frames */
440 qca8k_rmw(priv, QCA8K_REG_MAX_FRAME_SIZE,
441 QCA8K_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
442
443 qca8k_write(priv, QCA8K_REG_PORT_FLOWCTRL_THRESH(0),
444 (QCA8K_PORT0_FC_THRESH_ON_DFLT << 16) |
445 QCA8K_PORT0_FC_THRESH_OFF_DFLT);
446
447 /* Enable QCA header mode on the cpu port */
448 qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT), 0);
449 /*
450 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
451 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);*/
452
453 /* Disable forwarding by default on all ports */
454 for (i = 0; i < QCA8K_NUM_PORTS; i++)
455 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
456 QCA8K_PORT_LOOKUP_MEMBER, 0);
457
458 /* Disable MAC by default on all user ports */
459 for (i = 1; i < QCA8K_NUM_PORTS; i++)
460 if (dsa_is_user_port(ds, i))
461 qca8k_port_set_status(priv, i, 0);
462
463 /* Forward all unknown frames to CPU port for Linux processing */
464 qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
465 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
466 GENMASK(5, 0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
467 GENMASK(5, 0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
468 GENMASK(5, 0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
469
470 /* Setup connection between CPU port & user ports */
471 for (i = 0; i < DSA_MAX_PORTS; i++) {
472 /* CPU port gets connected to all user ports of the switch */
473 if (dsa_is_cpu_port(ds, i)) {
474 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
475 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
476 }
477
478 /* Invividual user ports get connected to CPU port only */
479 if (dsa_is_user_port(ds, i)) {
480 int shift = 16 * (i % 2);
481
482 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
483 QCA8K_PORT_LOOKUP_MEMBER,
484 BIT(QCA8K_CPU_PORT));
485
486 /* Enable ARP Auto-learning by default */
487 qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
488 QCA8K_PORT_LOOKUP_LEARN);
489
490 /* For port based vlans to work we need to set the
491 * default egress vid
492 */
493 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
494 0xffff << shift, 1 << shift);
495 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
496 QCA8K_PORT_VLAN_CVID(1) |
497 QCA8K_PORT_VLAN_SVID(1));
498 }
499 }
500
501 /* Flush the FDB table */
502 qca8k_fdb_flush(priv);
503
504 return 0;
505 }
506
507 static void
508 qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
509 {
510 struct qca8k_priv *priv = ds->priv;
511 u32 reg;
512
513 /* Force fixed-link setting for CPU port, skip others. */
514 if (!phy_is_pseudo_fixed_link(phy) && priv->mac_mode != 3)
515 return;
516
517 /* Set port speed */
518 switch (phy->speed) {
519 case 10:
520 reg = QCA8K_PORT_STATUS_SPEED_10;
521 break;
522 case 100:
523 reg = QCA8K_PORT_STATUS_SPEED_100;
524 break;
525 case 1000:
526 reg = QCA8K_PORT_STATUS_SPEED_1000;
527 break;
528 default:
529 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
530 port, phy->speed);
531 return;
532 }
533
534 /* Set duplex mode */
535 if (phy->duplex == DUPLEX_FULL)
536 reg |= QCA8K_PORT_STATUS_DUPLEX;
537
538 /* Force flow control */
539 if (dsa_is_cpu_port(ds, port) || priv->mac_mode == 3)
540 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW |
541 QCA8K_PORT_TXHALF_FLOW;
542
543 /* Force link down before changing MAC options */
544 qca8k_port_set_status(priv, port, 0);
545 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
546 qca8k_port_set_status(priv, port, 1);
547 }
548
549 static void
550 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
551 {
552 int i;
553
554 if (stringset != ETH_SS_STATS)
555 return;
556
557 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
558 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
559 ETH_GSTRING_LEN);
560 }
561
562 static void
563 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
564 uint64_t *data)
565 {
566 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
567 const struct qca8k_mib_desc *mib;
568 u32 reg, i;
569 u64 hi;
570
571 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
572 mib = &ar8327_mib[i];
573 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
574
575 data[i] = qca8k_read(priv, reg);
576 if (mib->size == 2) {
577 hi = qca8k_read(priv, reg + 4);
578 data[i] |= hi << 32;
579 }
580 }
581 }
582
583 static int
584 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
585 {
586 if (sset != ETH_SS_STATS)
587 return 0;
588
589 return ARRAY_SIZE(ar8327_mib);
590 }
591
592 static int
593 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
594 {
595 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
596 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
597 u32 reg;
598
599 mutex_lock(&priv->reg_mutex);
600 reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
601 if (eee->eee_enabled)
602 reg |= lpi_en;
603 else
604 reg &= ~lpi_en;
605 qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
606 mutex_unlock(&priv->reg_mutex);
607
608 return 0;
609 }
610
611 static int
612 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
613 {
614 /* Nothing to do on the port's MAC */
615 return 0;
616 }
617
618 static void
619 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
620 {
621 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
622 u32 stp_state;
623
624 switch (state) {
625 case BR_STATE_DISABLED:
626 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
627 break;
628 case BR_STATE_BLOCKING:
629 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
630 break;
631 case BR_STATE_LISTENING:
632 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
633 break;
634 case BR_STATE_LEARNING:
635 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
636 break;
637 case BR_STATE_FORWARDING:
638 default:
639 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
640 break;
641 }
642
643 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
644 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
645 }
646
647 static int
648 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
649 {
650 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
651 int port_mask = BIT(QCA8K_CPU_PORT);
652 int i;
653
654 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
655 if (dsa_to_port(ds, i)->bridge_dev != br)
656 continue;
657 /* Add this port to the portvlan mask of the other ports
658 * in the bridge
659 */
660 qca8k_reg_set(priv,
661 QCA8K_PORT_LOOKUP_CTRL(i),
662 BIT(port));
663 if (i != port)
664 port_mask |= BIT(i);
665 }
666 /* Add all other ports to this ports portvlan mask */
667 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
668 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
669
670 return 0;
671 }
672
673 static void
674 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
675 {
676 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
677 int i;
678
679 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
680 if (dsa_to_port(ds, i)->bridge_dev != br)
681 continue;
682 /* Remove this port to the portvlan mask of the other ports
683 * in the bridge
684 */
685 qca8k_reg_clear(priv,
686 QCA8K_PORT_LOOKUP_CTRL(i),
687 BIT(port));
688 }
689
690 /* Set the cpu port to be the only one in the portvlan mask of
691 * this port
692 */
693 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
694 QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
695 }
696
697 static int
698 qca8k_port_enable(struct dsa_switch *ds, int port,
699 struct phy_device *phy)
700 {
701 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
702
703 qca8k_port_set_status(priv, port, 1);
704 priv->port_sts[port].enabled = 1;
705
706 return 0;
707 }
708
709 static void
710 qca8k_port_disable(struct dsa_switch *ds, int port,
711 struct phy_device *phy)
712 {
713 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
714
715 qca8k_port_set_status(priv, port, 0);
716 priv->port_sts[port].enabled = 0;
717 }
718
719 static int
720 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
721 u16 port_mask, u16 vid)
722 {
723 /* Set the vid to the port vlan id if no vid is set */
724 if (!vid)
725 vid = 1;
726
727 return qca8k_fdb_add(priv, addr, port_mask, vid,
728 QCA8K_ATU_STATUS_STATIC);
729 }
730
731 static int
732 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
733 const unsigned char *addr, u16 vid)
734 {
735 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
736 u16 port_mask = BIT(port);
737
738 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
739 }
740
741 static int
742 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
743 const unsigned char *addr, u16 vid)
744 {
745 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
746 u16 port_mask = BIT(port);
747
748 if (!vid)
749 vid = 1;
750
751 return qca8k_fdb_del(priv, addr, port_mask, vid);
752 }
753
754 static int
755 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
756 dsa_fdb_dump_cb_t *cb, void *data)
757 {
758 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
759 struct qca8k_fdb _fdb = { 0 };
760 int cnt = QCA8K_NUM_FDB_RECORDS;
761 bool is_static;
762 int ret = 0;
763
764 mutex_lock(&priv->reg_mutex);
765 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
766 if (!_fdb.aging)
767 break;
768 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
769 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
770 if (ret)
771 break;
772 }
773 mutex_unlock(&priv->reg_mutex);
774
775 return 0;
776 }
777
778 static enum dsa_tag_protocol
779 qca8k_get_tag_protocol(struct dsa_switch *ds, int port)
780 {
781 return DSA_TAG_PROTO_QCA;
782 }
783
784 static const struct dsa_switch_ops qca8k_switch_ops = {
785 .get_tag_protocol = qca8k_get_tag_protocol,
786 .setup = qca8k_setup,
787 .adjust_link = qca8k_adjust_link,
788 .port_enable = qca8k_port_enable,
789 .port_disable = qca8k_port_disable,
790 .get_strings = qca8k_get_strings,
791 .get_ethtool_stats = qca8k_get_ethtool_stats,
792 .get_sset_count = qca8k_get_sset_count,
793 .get_mac_eee = qca8k_get_mac_eee,
794 .set_mac_eee = qca8k_set_mac_eee,
795 .port_stp_state_set = qca8k_port_stp_state_set,
796 .port_bridge_join = qca8k_port_bridge_join,
797 .port_bridge_leave = qca8k_port_bridge_leave,
798 .port_fdb_add = qca8k_port_fdb_add,
799 .port_fdb_del = qca8k_port_fdb_del,
800 .port_fdb_dump = qca8k_port_fdb_dump,
801 };
802
803 #define AR40XX_NUM_PORTS 6
804
805 enum ar40xx_port_wrapper_cfg {
806 PORT_WRAPPER_PSGMII = 0,
807 PORT_WRAPPER_RGMII = 3,
808 };
809
810 #define AR40XX_PSGMII_MODE_CONTROL 0x1b4
811 #define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
812
813 #define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
814
815 #define AR40XX_REG_RGMII_CTRL 0x0004
816 #define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
817 #define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
818
819 #define AR40XX_PHY_SPEC_STATUS 0x11
820 #define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
821 #define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
822 #define AR40XX_PHY_SPEC_STATUS_SPEED GENMASK(16, 14)
823
824 #define AR40XX_PSGMII_ID 5
825 #define AR40XX_PSGMII_CALB_NUM 100
826 #define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
827 #define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
828 #define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
829 #define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
830 #define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
831 #define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
832 #define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
833 #define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
834 #define AR40XX_MALIBU_PHY_LAST_ADDR 4
835
836 static u32
837 psgmii_read(struct qca8k_priv *priv, int reg)
838 {
839 u32 val;
840
841 regmap_read(priv->psgmii, reg, &val);
842 return val;
843 }
844
845 static void
846 psgmii_write(struct qca8k_priv *priv, int reg, u32 val)
847 {
848 regmap_write(priv->psgmii, reg, val);
849 }
850
851 static void
852 qca8k_phy_mmd_write(struct qca8k_priv *priv, u32 phy_id,
853 u16 mmd_num, u16 reg_id, u16 reg_val)
854 {
855 struct mii_bus *bus = priv->bus;
856
857 mutex_lock(&bus->mdio_lock);
858 __mdiobus_write(bus, phy_id, MII_MMD_CTRL, mmd_num);
859 __mdiobus_write(bus, phy_id, MII_MMD_DATA, reg_id);
860 __mdiobus_write(bus, phy_id, MII_MMD_CTRL, MII_MMD_CTRL_NOINCR | mmd_num);
861 __mdiobus_write(bus, phy_id, MII_MMD_DATA, reg_val);
862 mutex_unlock(&bus->mdio_lock);
863 }
864
865 static u16
866 qca8k_phy_mmd_read(struct qca8k_priv *priv, u32 phy_id,
867 u16 mmd_num, u16 reg_id)
868 {
869 struct mii_bus *bus = priv->bus;
870 u16 value;
871
872 mutex_lock(&bus->mdio_lock);
873 __mdiobus_write(bus, phy_id, MII_MMD_CTRL, mmd_num);
874 __mdiobus_write(bus, phy_id, MII_MMD_DATA, reg_id);
875 __mdiobus_write(bus, phy_id, MII_MMD_CTRL, MII_MMD_CTRL_NOINCR | mmd_num);
876 value = __mdiobus_read(bus, phy_id, MII_MMD_DATA);
877 mutex_unlock(&bus->mdio_lock);
878
879 return value;
880 }
881
882 static void
883 ess_reset(struct qca8k_priv *priv)
884 {
885 reset_control_assert(priv->ess_rst);
886
887 mdelay(10);
888
889 reset_control_deassert(priv->ess_rst);
890
891 /* Waiting for all inner tables to be flushed and reinitialized.
892 * This takes between 5 and 10ms.
893 */
894 mdelay(10);
895 }
896
897 static void
898 ar40xx_malibu_psgmii_ess_reset(struct qca8k_priv *priv)
899 {
900 struct mii_bus *bus = priv->bus;
901 u32 n;
902
903 /* Reset phy psgmii */
904 /* fix phy psgmii RX 20bit */
905 mdiobus_write(bus, AR40XX_PSGMII_ID, 0x0, 0x005b);
906 /* reset phy psgmii */
907 mdiobus_write(bus, AR40XX_PSGMII_ID, 0x0, 0x001b);
908 /* release reset phy psgmii */
909 mdiobus_write(bus, AR40XX_PSGMII_ID, 0x0, 0x005b);
910
911 for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
912 u16 status;
913
914 status = qca8k_phy_mmd_read(priv, AR40XX_PSGMII_ID,
915 MDIO_MMD_PMAPMD, 0x28);
916 if (status & BIT(0))
917 break;
918
919 /* Polling interval to check PSGMII PLL in malibu is ready
920 * the worst time is 8.67ms
921 * for 25MHz reference clock
922 * [512+(128+2048)*49]*80ns+100us
923 */
924 mdelay(2);
925 }
926
927 /* check malibu psgmii calibration done end... */
928
929 /* freeze phy psgmii RX CDR */
930 mdiobus_write(bus, AR40XX_PSGMII_ID, 0x1a, 0x2230);
931
932 ess_reset(priv);
933
934 /* wait for the psgmii calibration to complete */
935 for (n = 0; n < AR40XX_PSGMII_CALB_NUM; n++) {
936 u32 status;
937
938 status = psgmii_read(priv, 0xa0);
939 if (status & BIT(0))
940 break;
941
942 /* Polling interval to check PSGMII PLL in ESS is ready */
943 mdelay(2);
944 }
945
946 /* release phy psgmii RX CDR */
947 mdiobus_write(bus, AR40XX_PSGMII_ID, 0x1a, 0x3230);
948 /* release phy psgmii RX 20bit */
949 mdiobus_write(bus, AR40XX_PSGMII_ID, 0x0, 0x005f);
950 }
951
952 static void
953 ar40xx_psgmii_single_phy_testing(struct qca8k_priv *priv, int phy)
954 {
955 struct mii_bus *bus = priv->bus;
956 u32 tx_ok, tx_error;
957 u32 rx_ok, rx_error;
958 u32 tx_ok_high16;
959 u32 rx_ok_high16;
960 u32 tx_all_ok, rx_all_ok;
961 int j;
962
963 mdiobus_write(bus, phy, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
964 mdiobus_write(bus, phy, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
965 BMCR_SPEED1000);
966
967 for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
968 u16 status;
969
970 status = mdiobus_read(bus, phy, AR40XX_PHY_SPEC_STATUS);
971 if (status & AR40XX_PHY_SPEC_STATUS_LINK)
972 break;
973
974 /* the polling interval to check if the PHY link up or not
975 * maxwait_timer: 750 ms +/-10 ms
976 * minwait_timer : 1 us +/- 0.1us
977 * time resides in minwait_timer ~ maxwait_timer
978 * see IEEE 802.3 section 40.4.5.2
979 */
980 mdelay(8);
981 }
982
983 /* enable check */
984 qca8k_phy_mmd_write(priv, phy, 7, 0x8029, 0x0000);
985 qca8k_phy_mmd_write(priv, phy, 7, 0x8029, 0x0003);
986
987 /* start traffic */
988 qca8k_phy_mmd_write(priv, phy, 7, 0x8020, 0xa000);
989
990 /* wait precisely for all traffic end
991 * 4096(pkt num) * 1524(size) * 8ns (125MHz) = 49.9ms
992 */
993 mdelay(50);
994
995 /* check counter */
996 tx_ok = qca8k_phy_mmd_read(priv, phy, 7, 0x802e);
997 tx_ok_high16 = qca8k_phy_mmd_read(priv, phy, 7, 0x802d);
998 tx_error = qca8k_phy_mmd_read(priv, phy, 7, 0x802f);
999 rx_ok = qca8k_phy_mmd_read(priv, phy, 7, 0x802b);
1000 rx_ok_high16 = qca8k_phy_mmd_read(priv, phy, 7, 0x802a);
1001 rx_error = qca8k_phy_mmd_read(priv, phy, 7, 0x802c);
1002 tx_all_ok = tx_ok + (tx_ok_high16 << 16);
1003 rx_all_ok = rx_ok + (rx_ok_high16 << 16);
1004
1005 if (tx_all_ok == 0x1000 && tx_error == 0) {
1006 /* success */
1007 priv->phy_t_status &= (~BIT(phy));
1008 } else {
1009 pr_info("PHY %d single test PSGMII issue happen!\n", phy);
1010 priv->phy_t_status |= BIT(phy);
1011 }
1012
1013 mdiobus_write(bus, phy, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN |
1014 BMCR_SPEED1000);
1015 }
1016
1017 static void
1018 ar40xx_psgmii_all_phy_testing(struct qca8k_priv *priv)
1019 {
1020 struct mii_bus *bus = priv->bus;
1021 int phy, j;
1022
1023 mdiobus_write(bus, 0x1f, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1024 mdiobus_write(bus, 0x1f, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1025 BMCR_SPEED1000);
1026
1027 for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
1028 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1029 u16 status;
1030
1031 status = mdiobus_read(bus, phy, AR40XX_PHY_SPEC_STATUS);
1032 if (!(status & AR40XX_PHY_SPEC_STATUS_LINK))
1033 break;
1034 }
1035
1036 if (phy >= (AR40XX_NUM_PORTS - 1))
1037 break;
1038 /* The polling interva to check if the PHY link up or not */
1039 mdelay(8);
1040 }
1041 /* enable package accounting */
1042 qca8k_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0000);
1043 qca8k_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0003);
1044
1045 /* start traffic generator */
1046 qca8k_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0xa000);
1047
1048 /* wait for the traffic to die down.
1049 * 4096 Packets * 1524 Bytes/Packet * 8 ns/Byte (125MHz) = 49.9ms
1050 */
1051 mdelay(50);
1052
1053 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1054 u32 tx_ok, tx_error;
1055 u32 rx_ok, rx_error;
1056 u32 tx_ok_high16;
1057 u32 rx_ok_high16;
1058 u32 tx_all_ok, rx_all_ok;
1059
1060 /* check counter */
1061 tx_ok = qca8k_phy_mmd_read(priv, phy, 7, 0x802e);
1062 tx_ok_high16 = qca8k_phy_mmd_read(priv, phy, 7, 0x802d);
1063 tx_error = qca8k_phy_mmd_read(priv, phy, 7, 0x802f);
1064 rx_ok = qca8k_phy_mmd_read(priv, phy, 7, 0x802b);
1065 rx_ok_high16 = qca8k_phy_mmd_read(priv, phy, 7, 0x802a);
1066 rx_error = qca8k_phy_mmd_read(priv, phy, 7, 0x802c);
1067 tx_all_ok = tx_ok + (tx_ok_high16 << 16);
1068 rx_all_ok = rx_ok + (rx_ok_high16 << 16);
1069
1070 if (tx_all_ok == 4096 && tx_error == 0) {
1071 /* success */
1072 priv->phy_t_status &= ~BIT(phy + 8);
1073 } else {
1074 pr_info("PHY%d test see issue!\n", phy);
1075 priv->phy_t_status |= BIT(phy + 8);
1076 }
1077 }
1078
1079 pr_debug("PHY all test 0x%x \r\n", priv->phy_t_status);
1080 }
1081
1082 static void
1083 ar40xx_psgmii_self_test(struct qca8k_priv *priv)
1084 {
1085 struct mii_bus *bus = priv->bus;
1086 u32 i, phy;
1087
1088 ar40xx_malibu_psgmii_ess_reset(priv);
1089
1090 /* switch to access MII reg for copper */
1091 mdiobus_write(bus, 4, 0x1f, 0x8500);
1092
1093 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1094 /*enable phy mdio broadcast write*/
1095 qca8k_phy_mmd_write(priv, phy, 7, 0x8028, 0x801f);
1096 }
1097
1098 /* force no link by power down */
1099 mdiobus_write(bus, 0x1f, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN |
1100 BMCR_SPEED1000);
1101
1102 /* Setup packet generator for loopback calibration */
1103 qca8k_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x1000); /* 4096 Packets */
1104 qca8k_phy_mmd_write(priv, 0x1f, 7, 0x8062, 0x05e0); /* 1524 Bytes */
1105
1106 /* fix mdi status */
1107 mdiobus_write(bus, 0x1f, 0x10, 0x6800);
1108 for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
1109 priv->phy_t_status = 0;
1110
1111 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1112 qca8k_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
1113 AR40XX_PORT_LOOKUP_LOOPBACK,
1114 AR40XX_PORT_LOOKUP_LOOPBACK);
1115 }
1116
1117 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)
1118 ar40xx_psgmii_single_phy_testing(priv, phy);
1119
1120 ar40xx_psgmii_all_phy_testing(priv);
1121
1122 if (priv->phy_t_status)
1123 ar40xx_malibu_psgmii_ess_reset(priv);
1124 else
1125 break;
1126 }
1127
1128 if (i >= AR40XX_PSGMII_CALB_NUM)
1129 pr_info("PSGMII cannot recover\n");
1130 else
1131 pr_debug("PSGMII recovered after %d times reset\n", i);
1132
1133 /* configuration recover */
1134 /* packet number */
1135 qca8k_phy_mmd_write(priv, 0x1f, 7, 0x8021, 0x0);
1136 /* disable check */
1137 qca8k_phy_mmd_write(priv, 0x1f, 7, 0x8029, 0x0);
1138 /* disable traffic */
1139 qca8k_phy_mmd_write(priv, 0x1f, 7, 0x8020, 0x0);
1140 }
1141
1142 static void
1143 ar40xx_psgmii_self_test_clean(struct qca8k_priv *priv)
1144 {
1145 struct mii_bus *bus = priv->bus;
1146 int phy;
1147
1148 /* disable phy internal loopback */
1149 mdiobus_write(bus, 0x1f, 0x10, 0x6860);
1150 mdiobus_write(bus, 0x1f, MII_BMCR, BMCR_ANENABLE | BMCR_RESET |
1151 BMCR_SPEED1000);
1152
1153 for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
1154 /* disable mac loop back */
1155 qca8k_rmw(priv, AR40XX_REG_PORT_LOOKUP(phy + 1),
1156 AR40XX_PORT_LOOKUP_LOOPBACK, 0);
1157
1158 /* disable phy mdio broadcast write */
1159 qca8k_phy_mmd_write(priv, phy, 7, 0x8028, 0x001f);
1160 }
1161 }
1162
1163 static void
1164 ar40xx_malibu_init(struct qca8k_priv *priv)
1165 {
1166 int i;
1167 u16 val;
1168
1169 /* war to enable AZ transmitting ability */
1170 qca8k_phy_mmd_write(priv, AR40XX_PSGMII_ID, 1,
1171 AR40XX_MALIBU_PSGMII_MODE_CTRL,
1172 AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL);
1173
1174 for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
1175
1176 /* change malibu control_dac */
1177 val = qca8k_phy_mmd_read(priv, i, 7, AR40XX_MALIBU_PHY_MMD7_DAC_CTRL);
1178 val &= ~AR40XX_MALIBU_DAC_CTRL_MASK;
1179 val |= AR40XX_MALIBU_DAC_CTRL_VALUE;
1180 qca8k_phy_mmd_write(priv, i, 7, AR40XX_MALIBU_PHY_MMD7_DAC_CTRL, val);
1181
1182 if (i == AR40XX_MALIBU_PHY_LAST_ADDR) {
1183 /* avoid PHY to get into hibernation */
1184 val = qca8k_phy_mmd_read(priv, i, 3,
1185 AR40XX_MALIBU_PHY_RLP_CTRL);
1186 val &= (~(1<<1));
1187 qca8k_phy_mmd_write(priv, i, 3,
1188 AR40XX_MALIBU_PHY_RLP_CTRL, val);
1189 }
1190 }
1191
1192 /* adjust psgmii serdes tx amp */
1193 mdiobus_write(priv->bus, AR40XX_PSGMII_ID,
1194 AR40XX_PSGMII_TX_DRIVER_1_CTRL,
1195 AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
1196 }
1197
1198 static void
1199 ar40xx_mac_mode_init(struct qca8k_priv *priv)
1200 {
1201 switch (priv->mac_mode) {
1202 case PORT_WRAPPER_PSGMII:
1203 ar40xx_malibu_init(priv);
1204 ar40xx_psgmii_self_test(priv);
1205 ar40xx_psgmii_self_test_clean(priv);
1206
1207 psgmii_write(priv, AR40XX_PSGMII_MODE_CONTROL, 0x2200);
1208 psgmii_write(priv, AR40XX_PSGMIIPHY_TX_CONTROL, 0x8380);
1209 break;
1210 case PORT_WRAPPER_RGMII:
1211 qca8k_write(priv, AR40XX_REG_RGMII_CTRL, BIT(10));
1212 break;
1213 }
1214 }
1215
1216 #ifdef QM_ERROR_WAR
1217 /* Start of qm error WAR */
1218
1219 #define AR40XX_PORT_LINK_UP 1
1220 #define AR40XX_PORT_LINK_DOWN 0
1221 #define AR40XX_QM_NOT_EMPTY 1
1222 #define AR40XX_QM_EMPTY 0
1223
1224 static
1225 int ar40xx_force_1g_full(struct qca8k_priv *priv, u32 port_id)
1226 {
1227 u32 reg;
1228
1229 if (port_id < 0 || port_id > 6)
1230 return -1;
1231
1232 reg = QCA8K_REG_PORT_STATUS(port_id);
1233 return qca8k_rmw(priv, reg, QCA8K_PORT_STATUS_SPEED,
1234 (QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_DUPLEX));
1235 }
1236
1237 static
1238 int ar40xx_get_qm_status(struct qca8k_priv *priv,
1239 u32 port_id, u32 *qm_buffer_err)
1240 {
1241 u32 reg;
1242 u32 qm_val;
1243
1244 if (port_id < 1 || port_id > 5) {
1245 *qm_buffer_err = 0;
1246 return -1;
1247 }
1248
1249 if (port_id < 4) {
1250 reg = AR40XX_REG_QM_PORT0_3_QNUM;
1251 qca8k_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
1252 qm_val = qca8k_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
1253 /* every 8 bits for each port */
1254 *qm_buffer_err = (qm_val >> (port_id * 8)) & 0xFF;
1255 } else {
1256 reg = AR40XX_REG_QM_PORT4_6_QNUM;
1257 qca8k_write(priv, AR40XX_REG_QM_DEBUG_ADDR, reg);
1258 qm_val = qca8k_read(priv, AR40XX_REG_QM_DEBUG_VALUE);
1259 /* every 8 bits for each port */
1260 *qm_buffer_err = (qm_val >> ((port_id-4) * 8)) & 0xFF;
1261 }
1262
1263 return 0;
1264 }
1265
1266 static void
1267 ar40xx_sw_mac_polling_task(struct qca8k_priv *priv)
1268 {
1269 static int task_count;
1270 u32 i;
1271 u32 reg, value;
1272 u32 link, speed, duplex;
1273 u32 qm_buffer_err;
1274 u16 port_phy_status[AR40XX_NUM_PORTS];
1275 static u32 qm_err_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
1276 static u32 link_cnt[AR40XX_NUM_PORTS] = {0, 0, 0, 0, 0, 0};
1277 struct mii_bus *bus = NULL;
1278
1279 if (!priv || !priv->bus)
1280 return;
1281
1282 bus = priv->bus;
1283
1284 ++task_count;
1285
1286 for (i = 1; i < AR40XX_NUM_PORTS; ++i) {
1287 port_phy_status[i] =
1288 mdiobus_read(bus, i-1, AR40XX_PHY_SPEC_STATUS);
1289 speed = link = duplex = port_phy_status[i];
1290 speed &= AR40XX_PHY_SPEC_STATUS_SPEED;
1291 speed >>= 14;
1292 link &= AR40XX_PHY_SPEC_STATUS_LINK;
1293 link >>= 10;
1294 duplex &= AR40XX_PHY_SPEC_STATUS_DUPLEX;
1295 duplex >>= 13;
1296
1297 if (link != priv->ar40xx_port_old_link[i]) {
1298 ++link_cnt[i];
1299 /* Up --> Down */
1300 if ((priv->ar40xx_port_old_link[i] ==
1301 AR40XX_PORT_LINK_UP) &&
1302 (link == AR40XX_PORT_LINK_DOWN)) {
1303 /* LINK_EN disable(MAC force mode)*/
1304 reg = QCA8K_REG_PORT_STATUS(i);
1305 qca8k_rmw(priv, reg,
1306 QCA8K_PORT_STATUS_LINK_AUTO, 0);
1307
1308 /* Check queue buffer */
1309 qm_err_cnt[i] = 0;
1310 ar40xx_get_qm_status(priv, i, &qm_buffer_err);
1311 if (qm_buffer_err) {
1312 priv->ar40xx_port_qm_buf[i] =
1313 AR40XX_QM_NOT_EMPTY;
1314 } else {
1315 u16 phy_val = 0;
1316
1317 priv->ar40xx_port_qm_buf[i] =
1318 AR40XX_QM_EMPTY;
1319 ar40xx_force_1g_full(priv, i);
1320 /* Ref:QCA8337 Datasheet,Clearing
1321 * MENU_CTRL_EN prevents phy to
1322 * stuck in 100BT mode when
1323 * bringing up the link
1324 */
1325 ar40xx_phy_dbg_read(priv, i-1,
1326 AR40XX_PHY_DEBUG_0,
1327 &phy_val);
1328 phy_val &= (~AR40XX_PHY_MANU_CTRL_EN);
1329 ar40xx_phy_dbg_write(priv, i-1,
1330 AR40XX_PHY_DEBUG_0,
1331 phy_val);
1332 }
1333 priv->ar40xx_port_old_link[i] = link;
1334 } else if ((priv->ar40xx_port_old_link[i] ==
1335 AR40XX_PORT_LINK_DOWN) &&
1336 (link == AR40XX_PORT_LINK_UP)) {
1337 /* Down --> Up */
1338 if (priv->port_link_up[i] < 1) {
1339 ++priv->port_link_up[i];
1340 } else {
1341 /* Change port status */
1342 reg = QCA8K_REG_PORT_STATUS(i);
1343 value = qca8k_read(priv, reg);
1344 priv->port_link_up[i] = 0;
1345
1346 value &= ~(QCA8K_PORT_STATUS_DUPLEX |
1347 QCA8K_PORT_STATUS_SPEED);
1348 value |= speed | (duplex ? BIT(6) : 0);
1349 /**/qca8k_write(priv, reg, value);
1350 /* clock switch need such time
1351 * to avoid glitch
1352 */
1353 usleep_range(100, 200);
1354
1355 value |= QCA8K_PORT_STATUS_LINK_AUTO;
1356 qca8k_write(priv, reg, value);
1357 /* HW need such time to make sure link
1358 * stable before enable MAC
1359 */
1360 usleep_range(100, 200);
1361
1362 if (speed == QCA8K_PORT_STATUS_SPEED_100) {
1363 u16 phy_val = 0;
1364 /* Enable @100M, if down to 10M
1365 * clock will change smoothly
1366 */
1367 ar40xx_phy_dbg_read(priv, i-1,
1368 0,
1369 &phy_val);
1370 phy_val |=
1371 AR40XX_PHY_MANU_CTRL_EN;
1372 ar40xx_phy_dbg_write(priv, i-1,
1373 0,
1374 phy_val);
1375 }
1376 priv->ar40xx_port_old_link[i] = link;
1377 }
1378 }
1379 }
1380
1381 if (priv->ar40xx_port_qm_buf[i] == AR40XX_QM_NOT_EMPTY) {
1382 /* Check QM */
1383 ar40xx_get_qm_status(priv, i, &qm_buffer_err);
1384 if (qm_buffer_err) {
1385 ++qm_err_cnt[i];
1386 } else {
1387 priv->ar40xx_port_qm_buf[i] =
1388 AR40XX_QM_EMPTY;
1389 qm_err_cnt[i] = 0;
1390 ar40xx_force_1g_full(priv, i);
1391 }
1392 }
1393 }
1394 }
1395
1396 #define AR40XX_QM_WORK_DELAY 100
1397
1398 static void
1399 ar40xx_qm_err_check_work_task(struct work_struct *work)
1400 {
1401 struct qca8k_priv *priv = container_of(work, struct qca8k_priv,
1402 qm_dwork.work);
1403
1404 mutex_lock(&priv->qm_lock);
1405
1406 ar40xx_sw_mac_polling_task(priv);
1407
1408 mutex_unlock(&priv->qm_lock);
1409
1410 schedule_delayed_work(&priv->qm_dwork,
1411 msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
1412 }
1413
1414 static int
1415 ar40xx_qm_err_check_work_start(struct qca8k_priv *priv)
1416 {
1417 mutex_init(&priv->qm_lock);
1418
1419 INIT_DELAYED_WORK(&priv->qm_dwork, ar40xx_qm_err_check_work_task);
1420
1421 schedule_delayed_work(&priv->qm_dwork,
1422 msecs_to_jiffies(AR40XX_QM_WORK_DELAY));
1423
1424 return 0;
1425 }
1426 #else
1427 static int
1428 ar40xx_qm_err_check_work_start(struct qca8k_priv *priv)
1429 {
1430 return 0;
1431 }
1432 #endif
1433
1434
1435 static void
1436 qca8k_dsa_init_work(struct work_struct *work)
1437 {
1438 struct qca8k_priv *priv = container_of(work, struct qca8k_priv, dsa_init.work);
1439 struct device *parent = priv->pdev->dev.parent;
1440 int ret;
1441
1442 ret = dsa_register_switch(priv->ds);
1443
1444 switch (ret) {
1445 case 0:
1446 return;
1447
1448 case -EPROBE_DEFER:
1449 dev_dbg(&priv->pdev->dev, "dsa_register_switch defered.\n");
1450 schedule_delayed_work(&priv->dsa_init, msecs_to_jiffies(200));
1451 return;
1452
1453 default:
1454 dev_err(&priv->pdev->dev, "dsa_register_switch failed with (%d).\n", ret);
1455 /* unbind anything failed */
1456 if (parent)
1457 device_lock(parent);
1458
1459 device_release_driver(&priv->pdev->dev);
1460 if (parent)
1461 device_unlock(parent);
1462 return;
1463 }
1464 }
1465
1466 static int __init
1467 qca8k_mmio_probe(struct platform_device *pdev)
1468 {
1469 struct qca8k_priv *priv;
1470 struct device_node *np = pdev->dev.of_node, *mii_np;
1471 int ret;
1472
1473 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1474
1475 priv->pdev = pdev;
1476 mutex_init(&priv->reg_mutex);
1477
1478 priv->ess_clk = of_clk_get_by_name(np, "ess_clk");
1479 if (IS_ERR(priv->ess_clk)) {
1480 dev_err(&pdev->dev, "Failed to get ess_clk\n");
1481 return PTR_ERR(priv->ess_clk);
1482 }
1483
1484 priv->ess_rst = devm_reset_control_get(&pdev->dev, "ess_rst");
1485 if (IS_ERR(priv->ess_rst)) {
1486 dev_err(&pdev->dev, "Failed to get ess_rst control!\n");
1487 return PTR_ERR(priv->ess_rst);
1488 }
1489
1490 ret = of_property_read_u32(np, "mac-mode", &priv->mac_mode);
1491 if (ret < 0)
1492 return -EINVAL;
1493
1494 priv->base = syscon_node_to_regmap(np);
1495 if (IS_ERR_OR_NULL(priv->base))
1496 return -EINVAL;
1497
1498 priv->psgmii = syscon_regmap_lookup_by_phandle(np, "psgmii-phy");
1499 if (IS_ERR_OR_NULL(priv->psgmii))
1500 return -EINVAL;
1501
1502 mii_np = of_parse_phandle(np, "mii", 0);
1503 if (!mii_np)
1504 return -EINVAL;
1505
1506 priv->bus = of_mdio_find_bus(mii_np);
1507 of_node_put(mii_np);
1508 if (!priv->bus)
1509 return -EPROBE_DEFER;
1510
1511 priv->ds = dsa_switch_alloc(&pdev->dev, DSA_MAX_PORTS);
1512 if (!priv->ds)
1513 return -ENOMEM;
1514
1515 priv->ds->priv = priv;
1516 priv->ds->ops = &qca8k_switch_ops;
1517
1518 clk_prepare_enable(priv->ess_clk);
1519
1520 platform_set_drvdata(pdev, priv);
1521
1522 ar40xx_qm_err_check_work_start(priv);
1523
1524 ess_reset(priv);
1525
1526 ar40xx_mac_mode_init(priv);
1527
1528 reset_control_put(priv->ess_rst);
1529
1530 /* Ok. What's going on with the delayed dsa_switch_register?!
1531 *
1532 * On Bootup, this switch driver loads before the ethernet
1533 * driver. This causes a problem in dsa_register_switch when
1534 * it parses the tree and encounters the not-yet-ready
1535 * "ethernet = <&gmac>;" property.
1536 *
1537 * Which will err with -EPROBE_DEFER. Normally this should be
1538 * OK and the driver will just get loaded at a later time.
1539 * However, the EthernetSubSystem (ESS for short) really doesn't
1540 * like being resetted more than once in this fashion and will
1541 * "lock it up for good"... like "real good".
1542 *
1543 * So far, only a reboot can "unwedge" it, which is not what
1544 * we want.
1545 *
1546 * So this workaround (running dsa_register_switch in a
1547 * workqueue task) is employed to fix this unknown issue within
1548 * the SoC for now.
1549 */
1550
1551 INIT_DELAYED_WORK(&priv->dsa_init, qca8k_dsa_init_work);
1552 schedule_delayed_work(&priv->dsa_init, msecs_to_jiffies(1000));
1553
1554 return 0;
1555 }
1556
1557 static const struct of_device_id qca8k_of_match[] = {
1558 { .compatible = "qca,qca8337-mmio" },
1559 { /* sentinel */ },
1560 };
1561
1562 static struct platform_driver qca8kmmio_driver = {
1563 .driver = {
1564 .name = "qca8k",
1565 .of_match_table = qca8k_of_match,
1566 },
1567 };
1568
1569 module_platform_driver_probe(qca8kmmio_driver, qca8k_mmio_probe);
1570
1571 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
1572 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1573 MODULE_LICENSE("GPL v2");
1574 MODULE_ALIAS("platform:qca8k");
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