ipq40xx: dynamically build board-2.bin for Mikrotik
[openwrt/staging/chunkeey.git] / target / linux / ipq40xx / files / arch / arm / boot / dts / qcom-ipq4019-cm520-79f.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qcom-ipq4019.dtsi"
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/soc/qcom,tcsr.h>
7
8 / {
9 model = "MobiPromo CM520-79F";
10 compatible = "mobipromo,cm520-79f";
11
12 aliases {
13 led-boot = &led_sys;
14 led-failsafe = &led_sys;
15 led-running = &led_sys;
16 led-upgrade = &led_sys;
17 };
18
19 soc {
20 rng@22000 {
21 status = "okay";
22 };
23
24 mdio@90000 {
25 status = "okay";
26 pinctrl-0 = <&mdio_pins>;
27 pinctrl-names = "default";
28 reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
29 reset-delay-us = <1000>;
30 };
31
32 ess-psgmii@98000 {
33 status = "okay";
34 };
35
36 tcsr@1949000 {
37 compatible = "qcom,tcsr";
38 reg = <0x1949000 0x100>;
39 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
40 };
41
42 tcsr@194b000 {
43 compatible = "qcom,tcsr";
44 reg = <0x194b000 0x100>;
45 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
46 };
47
48 ess_tcsr@1953000 {
49 compatible = "qcom,tcsr";
50 reg = <0x1953000 0x1000>;
51 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
52 };
53
54 tcsr@1957000 {
55 compatible = "qcom,tcsr";
56 reg = <0x1957000 0x100>;
57 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
58 };
59
60 usb2@60f8800 {
61 status = "okay";
62
63 dwc3@6000000 {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 usb2_port1: port@1 {
68 reg = <1>;
69 #trigger-source-cells = <0>;
70 };
71 };
72 };
73
74 usb3@8af8800 {
75 status = "okay";
76
77 dwc3@8a00000 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 usb3_port1: port@1 {
82 reg = <1>;
83 #trigger-source-cells = <0>;
84 };
85
86 usb3_port2: port@2 {
87 reg = <2>;
88 #trigger-source-cells = <0>;
89 };
90 };
91 };
92
93 crypto@8e3a000 {
94 status = "okay";
95 };
96
97 watchdog@b017000 {
98 status = "okay";
99 };
100
101 ess-switch@c000000 {
102 status = "okay";
103 };
104
105 edma@c080000 {
106 status = "okay";
107 };
108 };
109
110 led_spi {
111 compatible = "spi-gpio";
112 #address-cells = <1>;
113 #size-cells = <0>;
114
115 sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
116 mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
117 num-chipselects = <0>;
118
119 led_gpio: led_gpio@0 {
120 compatible = "fairchild,74hc595";
121 reg = <0>;
122 gpio-controller;
123 #gpio-cells = <2>;
124 registers-number = <1>;
125 spi-max-frequency = <1000000>;
126 };
127 };
128
129 leds {
130 compatible = "gpio-leds";
131
132 usb {
133 label = "blue:usb";
134 gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
135 linux,default-trigger = "usbport";
136 trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
137 };
138
139 led_sys: can {
140 label = "blue:can";
141 gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
142 };
143
144 wan {
145 label = "blue:wan";
146 gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
147 };
148
149 lan1 {
150 label = "blue:lan1";
151 gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
152 };
153
154 lan2 {
155 label = "blue:lan2";
156 gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
157 };
158
159 wlan2g {
160 label = "blue:wlan2g";
161 gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
162 linux,default-trigger = "phy0tpt";
163 };
164
165 wlan5g {
166 label = "blue:wlan5g";
167 gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
168 linux,default-trigger = "phy1tpt";
169 };
170 };
171
172 keys {
173 compatible = "gpio-keys";
174
175 reset {
176 label = "reset";
177 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
178 linux,code = <KEY_RESTART>;
179 };
180 };
181 };
182
183 &blsp_dma {
184 status = "okay";
185 };
186
187 &blsp1_uart1 {
188 status = "okay";
189 };
190
191 &blsp1_uart2 {
192 status = "okay";
193 };
194
195 &cryptobam {
196 status = "okay";
197 };
198
199 &gmac0 {
200 nvmem-cells = <&macaddr_art_1006>;
201 nvmem-cell-names = "mac-address";
202 };
203
204 &gmac1 {
205 nvmem-cells = <&macaddr_art_5006>;
206 nvmem-cell-names = "mac-address";
207 };
208
209 &nand {
210 pinctrl-0 = <&nand_pins>;
211 pinctrl-names = "default";
212 status = "okay";
213
214 nand@0 {
215 partitions {
216 compatible = "fixed-partitions";
217 #address-cells = <1>;
218 #size-cells = <1>;
219
220 partition@0 {
221 label = "SBL1";
222 reg = <0x0 0x100000>;
223 read-only;
224 };
225
226 partition@100000 {
227 label = "MIBIB";
228 reg = <0x100000 0x100000>;
229 read-only;
230 };
231
232 partition@200000 {
233 label = "BOOTCONFIG";
234 reg = <0x200000 0x100000>;
235 };
236
237 partition@300000 {
238 label = "QSEE";
239 reg = <0x300000 0x100000>;
240 read-only;
241 };
242
243 partition@400000 {
244 label = "QSEE_1";
245 reg = <0x400000 0x100000>;
246 read-only;
247 };
248
249 partition@500000 {
250 label = "CDT";
251 reg = <0x500000 0x80000>;
252 read-only;
253 };
254
255 partition@580000 {
256 label = "CDT_1";
257 reg = <0x580000 0x80000>;
258 read-only;
259 };
260
261 partition@600000 {
262 label = "BOOTCONFIG1";
263 reg = <0x600000 0x80000>;
264 };
265
266 partition@680000 {
267 label = "APPSBLENV";
268 reg = <0x680000 0x80000>;
269 };
270
271 partition@700000 {
272 label = "APPSBL";
273 reg = <0x700000 0x200000>;
274 read-only;
275 };
276
277 partition@900000 {
278 label = "APPSBL_1";
279 reg = <0x900000 0x200000>;
280 read-only;
281 };
282
283 art: partition@b00000 {
284 label = "ART";
285 reg = <0xb00000 0x80000>;
286 read-only;
287 compatible = "nvmem-cells";
288 #address-cells = <1>;
289 #size-cells = <1>;
290
291 precal_art_1000: precal@1000 {
292 reg = <0x1000 0x2f20>;
293 };
294
295 macaddr_art_1006: macaddr@1006 {
296 reg = <0x1006 0x6>;
297 };
298
299 precal_art_5000: precal@5000 {
300 reg = <0x5000 0x2f20>;
301 };
302
303 macaddr_art_5006: macaddr@5006 {
304 reg = <0x5006 0x6>;
305 };
306 };
307
308 partition@b80000 {
309 label = "ubi";
310 reg = <0xb80000 0x7480000>;
311 };
312 };
313 };
314 };
315
316 &qpic_bam {
317 status = "okay";
318 };
319
320 &tlmm {
321 mdio_pins: mdio_pinmux {
322 mux_1 {
323 pins = "gpio6";
324 function = "mdio";
325 bias-pull-up;
326 };
327
328 mux_2 {
329 pins = "gpio7";
330 function = "mdc";
331 bias-pull-up;
332 };
333 };
334
335 nand_pins: nand_pins {
336 pullups {
337 pins = "gpio52", "gpio53", "gpio58",
338 "gpio59";
339 function = "qpic";
340 bias-pull-up;
341 };
342
343 pulldowns {
344 pins = "gpio54", "gpio55", "gpio56",
345 "gpio57", "gpio60", "gpio61",
346 "gpio62", "gpio63", "gpio64",
347 "gpio65", "gpio66", "gpio67",
348 "gpio68", "gpio69";
349 function = "qpic";
350 bias-pull-down;
351 };
352 };
353 };
354
355 &usb3_ss_phy {
356 status = "okay";
357 };
358
359 &usb3_hs_phy {
360 status = "okay";
361 };
362
363 &usb2_hs_phy {
364 status = "okay";
365 };
366
367 &wifi0 {
368 status = "okay";
369 nvmem-cell-names = "pre-calibration";
370 nvmem-cells = <&precal_art_1000>;
371 qcom,ath10k-calibration-variant = "CM520-79F";
372 };
373
374 &wifi1 {
375 status = "okay";
376 nvmem-cell-names = "pre-calibration";
377 nvmem-cells = <&precal_art_5000>;
378 qcom,ath10k-calibration-variant = "CM520-79F";
379 };