target/linux/lantiq/patches-3.10/0206-lantiq-nand-lock.patch

   1 From patchwork Wed Apr  2 19:38:52 2014
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   5 Subject: [OpenWrt-Devel,
   6         4/7] lantiq: BT Home Hub 2B support - nand pci interference
   7 Date: Wed, 02 Apr 2014 18:38:52 -0000
   8 From: Ben Mulvihill <ben.mulvihill@gmail.com>
   9 X-Patchwork-Id: 5113
  10 Message-Id: <1396467532.31327.42.camel@merveille.lan>
  11 To: openwrt-devel@lists.openwrt.org
  12
  13 Prevents interference between the xway nand driver and pci.
  14
  15 (Based on work by Simon Hayes first published on www.psidoc.com and
  16 http://sourceforge.net/projects/hh2b4ever/)
  17
  18 Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
  19
  20 ---
  21
  22
  23 --- a/drivers/mtd/nand/xway_nand.c
  24 +++ b/drivers/mtd/nand/xway_nand.c
  25 @@ -54,8 +54,27 @@
  26  #define NAND_CON_CSMUX         (1 << 1)
  27  #define NAND_CON_NANDM         1
  28
  29 +#define DANUBE_PCI_REG32( addr )    (*(volatile u32 *)(addr))
  30 +#define PCI_CR_PR_OFFSET           (KSEG1+0x1E105400)
  31 +#define PCI_CR_PC_ARB              (PCI_CR_PR_OFFSET + 0x0080)
  32 +
  33  static u32 xway_latchcmd;
  34
  35 +/*
  36 + * req_mask provides a mechanism to prevent interference between
  37 + * nand and pci (probably only relevant for the BT Home Hub 2B).
  38 + * Setting it causes the corresponding pci req pins to be masked
  39 + * during nand access, and also moves ebu locking from the read/write
  40 + * functions to the chip select function to ensure that the whole
  41 + * operation runs with interrupts disabled.
  42 + * In addition it switches on some extra waiting in xway_cmd_ctrl().
  43 + * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
  44 + * which in turn seems to be necessary for the nor chip to be recognised
  45 + * reliably, on a board (Home Hub 2B again) which has both nor and nand.
  46 + */
  47 +
  48 +static __be32 req_mask = 0;
  49 +
  50  static void xway_reset_chip(struct nand_chip *chip)
  51  {
  52         unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
  53 @@ -86,12 +105,24 @@ static void xway_select_chip(struct mtd_
  54         case -1:
  55                 ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
  56                 ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
  57 +
  58 +               if (req_mask) {
  59 +                       /* Unmask all external PCI request */
  60 +                       DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
  61 +               }
  62                 spin_unlock_irqrestore(&ebu_lock, csflags);
  63 +
  64                 break;
  65         case 0:
  66                 spin_lock_irqsave(&ebu_lock, csflags);
  67 +               if (req_mask) {
  68 +                       /* Mask all external PCI request */
  69 +                       DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
  70 +               }
  71 +
  72                 ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
  73                 ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
  74 +
  75                 break;
  76         default:
  77                 BUG();
  78 @@ -103,6 +134,12 @@ static void xway_cmd_ctrl(struct mtd_inf
  79         struct nand_chip *this = mtd->priv;
  80         unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
  81
  82 +       if (req_mask) {
  83 +               if (cmd != NAND_CMD_STATUS)
  84 +                       ltq_ebu_w32(EBU_NAND_WAIT, 0); /* Clear nand ready */
  85 +       }
  86 +
  87 +
  88         if (ctrl & NAND_CTRL_CHANGE) {
  89                 if (ctrl & NAND_CLE)
  90                         xway_latchcmd = NAND_WRITE_CMD;
  91 @@ -115,6 +152,24 @@ static void xway_cmd_ctrl(struct mtd_inf
  92                 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
  93                         ;
  94         }
  95 +
  96 +       if (req_mask) {
  97 +              /*
  98 +               * program and erase have their own busy handlers
  99 +               * status and sequential in needs no delay
 100 +               */
 101 +               switch (cmd) {
 102 +                       case NAND_CMD_ERASE1:
 103 +                       case NAND_CMD_SEQIN:
 104 +                       case NAND_CMD_STATUS:
 105 +                       case NAND_CMD_READID:
 106 +                       return;
 107 +               }
 108 +
 109 +               /* wait until command is processed */
 110 +               while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
 111 +                       ;
 112 +       }
 113  }
 114
 115  static int xway_dev_ready(struct mtd_info *mtd)
 116 @@ -157,6 +212,8 @@ static int xway_nand_probe(struct platfo
 117  {
 118         struct nand_chip *this = platform_get_drvdata(pdev);
 119         unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
 120 +       const __be32 *req_mask_ptr = of_get_property(pdev->dev.of_node,
 121 +                                       "req-mask", NULL);
 122         const __be32 *cs = of_get_property(pdev->dev.of_node,
 123                                         "lantiq,cs", NULL);
 124         u32 cs_flag = 0;
 125 @@ -165,6 +222,12 @@ static int xway_nand_probe(struct platfo
 126         if (cs && (*cs == 1))
 127                 cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
 128
 129 +       /*
 130 +        * Load the PCI req lines to mask from the device tree. If the
 131 +        * property is not present, setting req_mask to 0 disables masking.
 132 +        */
 133 +       req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
 134 +
 135         /* setup the EBU to run in NAND mode on our base addr */
 136         ltq_ebu_w32(CPHYSADDR(nandaddr)
 137                 | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);