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lantiq: Add support for linux 4.4
[openwrt/staging/chunkeey.git] / target / linux / lantiq / patches-4.4 / 0044-pinctrl-lantiq-introduce-new-dedicated-devicetree-bi.patch
1 From be14811c03cf20c793fd176a347625335110b0e6 Mon Sep 17 00:00:00 2001
2 From: Martin Schiller <mschiller@tdt.de>
3 Date: Thu, 26 Nov 2015 11:00:07 +0100
4 Subject: [PATCH] pinctrl/lantiq: introduce new dedicated devicetree bindings
5
6 This patch introduces new dedicated "lantiq,<chip>-pinctrl" devicetree
7 bindings, where <chip> is one of "ase", "danube", "xrx100", "xrx200" or
8 "xrx300" and marks the "lantiq,pinctrl-xway", "lantiq,pinctrl-ase" and
9 "lantiq,pinctrl-xr9" bindings as DEPRECATED.
10
11 Based on the newest Lantiq Hardware Description it turend out, that there are
12 some differences in the GPIO alternative functions of the Danube, xRX100 and
13 xRX200 families, which makes it impossible to use only one xway_mfp table.
14
15 This patch also adds support for the xRX300 family.
16
17 Signed-off-by: Martin Schiller <mschiller@tdt.de>
18 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
19 ---
20 drivers/pinctrl/pinctrl-lantiq.h | 8 +
21 drivers/pinctrl/pinctrl-xway.c | 1181 +++++++++++++++++++++++++++++++++-----
22 2 files changed, 1059 insertions(+), 130 deletions(-)
23
24 --- a/drivers/pinctrl/pinctrl-lantiq.h
25 +++ b/drivers/pinctrl/pinctrl-lantiq.h
26 @@ -162,6 +162,14 @@ enum ltq_pin {
27 GPIO53,
28 GPIO54,
29 GPIO55,
30 + GPIO56,
31 + GPIO57,
32 + GPIO58,
33 + GPIO59,
34 + GPIO60, /* 60 */
35 + GPIO61,
36 + GPIO62,
37 + GPIO63,
38
39 GPIO64,
40 GPIO65,
41 --- a/drivers/pinctrl/pinctrl-xway.c
42 +++ b/drivers/pinctrl/pinctrl-xway.c
43 @@ -7,6 +7,7 @@
44 * publishhed by the Free Software Foundation.
45 *
46 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
47 + * Copyright (C) 2015 Martin Schiller <mschiller@tdt.de>
48 */
49
50 #include <linux/err.h>
51 @@ -24,7 +25,7 @@
52
53 #include <lantiq_soc.h>
54
55 -/* we have 3 1/2 banks of 16 bit each */
56 +/* we have up to 4 banks of 16 bit each */
57 #define PINS 16
58 #define PORT3 3
59 #define PORT(x) (x / PINS)
60 @@ -35,7 +36,7 @@
61 #define MUX_ALT1 0x2
62
63 /*
64 - * each bank has this offset apart from the 1/2 bank that is mixed into the
65 + * each bank has this offset apart from the 4th bank that is mixed into the
66 * other 3 ranges
67 */
68 #define REG_OFF 0x30
69 @@ -51,7 +52,7 @@
70 #define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
71 #define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
72
73 -/* the 1/2 port needs special offsets for some registers */
74 +/* the 4th port needs special offsets for some registers */
75 #define GPIO3_OD (GPIO_BASE(0) + 0x24)
76 #define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
77 #define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
78 @@ -80,17 +81,18 @@
79 #define FUNC_MUX(f, m) \
80 { .func = f, .mux = XWAY_MUX_##m, }
81
82 -#define XWAY_MAX_PIN 32
83 -#define XR9_MAX_PIN 56
84 -
85 enum xway_mux {
86 XWAY_MUX_GPIO = 0,
87 XWAY_MUX_SPI,
88 XWAY_MUX_ASC,
89 + XWAY_MUX_USIF,
90 XWAY_MUX_PCI,
91 + XWAY_MUX_CBUS,
92 XWAY_MUX_CGU,
93 XWAY_MUX_EBU,
94 + XWAY_MUX_EBU2,
95 XWAY_MUX_JTAG,
96 + XWAY_MUX_MCD,
97 XWAY_MUX_EXIN,
98 XWAY_MUX_TDM,
99 XWAY_MUX_STP,
100 @@ -103,9 +105,15 @@ enum xway_mux {
101 XWAY_MUX_DFE,
102 XWAY_MUX_SDIO,
103 XWAY_MUX_GPHY,
104 + XWAY_MUX_SSI,
105 + XWAY_MUX_WIFI,
106 XWAY_MUX_NONE = 0xffff,
107 };
108
109 +/* --------- DEPRECATED: xr9 related code --------- */
110 +/* ---------- use xrx100/xrx200 instead ---------- */
111 +#define XR9_MAX_PIN 56
112 +
113 static const struct ltq_mfp_pin xway_mfp[] = {
114 /* pin f0 f1 f2 f3 */
115 MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
116 @@ -113,7 +121,7 @@ static const struct ltq_mfp_pin xway_mfp
117 MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
118 MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
119 MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
120 - MFP_XWAY(GPIO5, GPIO, STP, NONE, GPHY),
121 + MFP_XWAY(GPIO5, GPIO, STP, GPHY, NONE),
122 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
123 MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY),
124 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
125 @@ -152,7 +160,7 @@ static const struct ltq_mfp_pin xway_mfp
126 MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
127 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
128 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
129 - MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN),
130 + MFP_XWAY(GPIO44, GPIO, NONE, SIN, GPHY),
131 MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN),
132 MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
133 MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN),
134 @@ -166,42 +174,6 @@ static const struct ltq_mfp_pin xway_mfp
135 MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
136 };
137
138 -static const struct ltq_mfp_pin ase_mfp[] = {
139 - /* pin f0 f1 f2 f3 */
140 - MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
141 - MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
142 - MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
143 - MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
144 - MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
145 - MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
146 - MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
147 - MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
148 - MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
149 - MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
150 - MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
151 - MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
152 - MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
153 - MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
154 - MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
155 - MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
156 - MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
157 - MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
158 - MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
159 - MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
160 - MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
161 - MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO),
162 - MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
163 - MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
164 - MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII),
165 - MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
166 - MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
167 - MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII),
168 - MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
169 - MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
170 - MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
171 - MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
172 -};
173 -
174 static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
175 static const unsigned pins_asc0[] = {GPIO11, GPIO12};
176 static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
177 @@ -231,6 +203,8 @@ static const unsigned pins_nand_cle[] =
178 static const unsigned pins_nand_rdy[] = {GPIO48};
179 static const unsigned pins_nand_rd[] = {GPIO49};
180
181 +static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
182 +
183 static const unsigned pins_exin0[] = {GPIO0};
184 static const unsigned pins_exin1[] = {GPIO1};
185 static const unsigned pins_exin2[] = {GPIO2};
186 @@ -240,7 +214,7 @@ static const unsigned pins_exin5[] = {GP
187
188 static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
189 static const unsigned pins_spi_cs1[] = {GPIO15};
190 -static const unsigned pins_spi_cs2[] = {GPIO21};
191 +static const unsigned pins_spi_cs2[] = {GPIO22};
192 static const unsigned pins_spi_cs3[] = {GPIO13};
193 static const unsigned pins_spi_cs4[] = {GPIO10};
194 static const unsigned pins_spi_cs5[] = {GPIO9};
195 @@ -264,25 +238,6 @@ static const unsigned pins_pci_req2[] =
196 static const unsigned pins_pci_req3[] = {GPIO3};
197 static const unsigned pins_pci_req4[] = {GPIO37};
198
199 -static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
200 -static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
201 -static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
202 -static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4};
203 -static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2};
204 -
205 -static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10};
206 -static const unsigned ase_pins_spi_cs1[] = {GPIO7};
207 -static const unsigned ase_pins_spi_cs2[] = {GPIO15};
208 -static const unsigned ase_pins_spi_cs3[] = {GPIO14};
209 -
210 -static const unsigned ase_pins_exin0[] = {GPIO6};
211 -static const unsigned ase_pins_exin1[] = {GPIO29};
212 -static const unsigned ase_pins_exin2[] = {GPIO0};
213 -
214 -static const unsigned ase_pins_gpt1[] = {GPIO5};
215 -static const unsigned ase_pins_gpt2[] = {GPIO4};
216 -static const unsigned ase_pins_gpt3[] = {GPIO25};
217 -
218 static const struct ltq_pin_group xway_grps[] = {
219 GRP_MUX("exin0", EXIN, pins_exin0),
220 GRP_MUX("exin1", EXIN, pins_exin1),
221 @@ -338,24 +293,6 @@ static const struct ltq_pin_group xway_g
222 GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2),
223 };
224
225 -static const struct ltq_pin_group ase_grps[] = {
226 - GRP_MUX("exin0", EXIN, ase_pins_exin0),
227 - GRP_MUX("exin1", EXIN, ase_pins_exin1),
228 - GRP_MUX("exin2", EXIN, ase_pins_exin2),
229 - GRP_MUX("jtag", JTAG, ase_pins_jtag),
230 - GRP_MUX("stp", STP, ase_pins_stp),
231 - GRP_MUX("asc", ASC, ase_pins_asc),
232 - GRP_MUX("gpt1", GPT, ase_pins_gpt1),
233 - GRP_MUX("gpt2", GPT, ase_pins_gpt2),
234 - GRP_MUX("gpt3", GPT, ase_pins_gpt3),
235 - GRP_MUX("ephy", EPHY, ase_pins_ephy),
236 - GRP_MUX("dfe", DFE, ase_pins_dfe),
237 - GRP_MUX("spi", SPI, ase_pins_spi),
238 - GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
239 - GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
240 - GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
241 -};
242 -
243 static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
244 "gnt3", "req1",
245 "req2", "req3"};
246 @@ -395,30 +332,6 @@ static const char * const xrx_pci_grps[]
247 "req1", "req2",
248 "req3", "req4"};
249
250 -/* ase */
251 -static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
252 -static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
253 -static const char * const ase_dfe_grps[] = {"dfe"};
254 -static const char * const ase_ephy_grps[] = {"ephy"};
255 -static const char * const ase_asc_grps[] = {"asc"};
256 -static const char * const ase_jtag_grps[] = {"jtag"};
257 -static const char * const ase_stp_grps[] = {"stp"};
258 -static const char * const ase_spi_grps[] = {"spi", "spi_cs1",
259 - "spi_cs2", "spi_cs3"};
260 -
261 -static const struct ltq_pmx_func danube_funcs[] = {
262 - {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
263 - {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
264 - {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
265 - {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
266 - {"exin", ARRAY_AND_SIZE(xway_exin_grps)},
267 - {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
268 - {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
269 - {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
270 - {"pci", ARRAY_AND_SIZE(xway_pci_grps)},
271 - {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)},
272 -};
273 -
274 static const struct ltq_pmx_func xrx_funcs[] = {
275 {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
276 {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
277 @@ -434,17 +347,991 @@ static const struct ltq_pmx_func xrx_fun
278 {"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)},
279 };
280
281 +/* --------- ase related code --------- */
282 +#define ASE_MAX_PIN 32
283 +
284 +static const struct ltq_mfp_pin ase_mfp[] = {
285 + /* pin f0 f1 f2 f3 */
286 + MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
287 + MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
288 + MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
289 + MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
290 + MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
291 + MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
292 + MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
293 + MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
294 + MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
295 + MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
296 + MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
297 + MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
298 + MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
299 + MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
300 + MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
301 + MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
302 + MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
303 + MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
304 + MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
305 + MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
306 + MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
307 + MFP_XWAY(GPIO21, GPIO, EBU, MII, EBU2),
308 + MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
309 + MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
310 + MFP_XWAY(GPIO24, GPIO, EBU, EBU2, MDIO),
311 + MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
312 + MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
313 + MFP_XWAY(GPIO27, GPIO, EBU, NONE, MDIO),
314 + MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
315 + MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
316 + MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
317 + MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
318 +};
319 +
320 +static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0};
321 +
322 +static const unsigned ase_pins_exin0[] = {GPIO6};
323 +static const unsigned ase_pins_exin1[] = {GPIO29};
324 +static const unsigned ase_pins_exin2[] = {GPIO0};
325 +
326 +static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
327 +static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
328 +static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
329 +static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27};
330 +static const unsigned ase_pins_ephy_led0[] = {GPIO2};
331 +static const unsigned ase_pins_ephy_led1[] = {GPIO3};
332 +static const unsigned ase_pins_ephy_led2[] = {GPIO4};
333 +static const unsigned ase_pins_dfe_led0[] = {GPIO1};
334 +static const unsigned ase_pins_dfe_led1[] = {GPIO2};
335 +
336 +static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */
337 +static const unsigned ase_pins_spi_di[] = {GPIO8};
338 +static const unsigned ase_pins_spi_do[] = {GPIO9};
339 +static const unsigned ase_pins_spi_clk[] = {GPIO10};
340 +static const unsigned ase_pins_spi_cs1[] = {GPIO7};
341 +static const unsigned ase_pins_spi_cs2[] = {GPIO15};
342 +static const unsigned ase_pins_spi_cs3[] = {GPIO14};
343 +
344 +static const unsigned ase_pins_gpt1[] = {GPIO5};
345 +static const unsigned ase_pins_gpt2[] = {GPIO4};
346 +static const unsigned ase_pins_gpt3[] = {GPIO25};
347 +
348 +static const unsigned ase_pins_clkout0[] = {GPIO23};
349 +static const unsigned ase_pins_clkout1[] = {GPIO22};
350 +static const unsigned ase_pins_clkout2[] = {GPIO14};
351 +
352 +static const struct ltq_pin_group ase_grps[] = {
353 + GRP_MUX("exin0", EXIN, ase_pins_exin0),
354 + GRP_MUX("exin1", EXIN, ase_pins_exin1),
355 + GRP_MUX("exin2", EXIN, ase_pins_exin2),
356 + GRP_MUX("jtag", JTAG, ase_pins_jtag),
357 + GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
358 + GRP_MUX("spi_di", SPI, ase_pins_spi_di),
359 + GRP_MUX("spi_do", SPI, ase_pins_spi_do),
360 + GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
361 + GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
362 + GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
363 + GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
364 + GRP_MUX("asc", ASC, ase_pins_asc),
365 + GRP_MUX("stp", STP, ase_pins_stp),
366 + GRP_MUX("gpt1", GPT, ase_pins_gpt1),
367 + GRP_MUX("gpt2", GPT, ase_pins_gpt2),
368 + GRP_MUX("gpt3", GPT, ase_pins_gpt3),
369 + GRP_MUX("clkout0", CGU, ase_pins_clkout0),
370 + GRP_MUX("clkout1", CGU, ase_pins_clkout1),
371 + GRP_MUX("clkout2", CGU, ase_pins_clkout2),
372 + GRP_MUX("mdio", MDIO, ase_pins_mdio),
373 + GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0),
374 + GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1),
375 + GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0),
376 + GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1),
377 + GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2),
378 +};
379 +
380 +static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
381 +static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
382 +static const char * const ase_cgu_grps[] = {"clkout0", "clkout1",
383 + "clkout2"};
384 +static const char * const ase_mdio_grps[] = {"mdio"};
385 +static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"};
386 +static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1",
387 + "ephy led2"};
388 +static const char * const ase_asc_grps[] = {"asc"};
389 +static const char * const ase_jtag_grps[] = {"jtag"};
390 +static const char * const ase_stp_grps[] = {"stp"};
391 +static const char * const ase_spi_grps[] = {"spi", /* DEPRECATED */
392 + "spi_di", "spi_do",
393 + "spi_clk", "spi_cs1",
394 + "spi_cs2", "spi_cs3"};
395 +
396 static const struct ltq_pmx_func ase_funcs[] = {
397 {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
398 {"asc", ARRAY_AND_SIZE(ase_asc_grps)},
399 + {"cgu", ARRAY_AND_SIZE(ase_cgu_grps)},
400 {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)},
401 {"exin", ARRAY_AND_SIZE(ase_exin_grps)},
402 {"stp", ARRAY_AND_SIZE(ase_stp_grps)},
403 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
404 + {"mdio", ARRAY_AND_SIZE(ase_mdio_grps)},
405 {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
406 {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)},
407 };
408
409 +/* --------- danube related code --------- */
410 +#define DANUBE_MAX_PIN 32
411 +
412 +static const struct ltq_mfp_pin danube_mfp[] = {
413 + /* pin f0 f1 f2 f3 */
414 + MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
415 + MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, MII),
416 + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, MII),
417 + MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
418 + MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC),
419 + MFP_XWAY(GPIO5, GPIO, STP, MII, DFE),
420 + MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
421 + MFP_XWAY(GPIO7, GPIO, CGU, CBUS, MII),
422 + MFP_XWAY(GPIO8, GPIO, CGU, NMI, MII),
423 + MFP_XWAY(GPIO9, GPIO, ASC, SPI, MII),
424 + MFP_XWAY(GPIO10, GPIO, ASC, SPI, MII),
425 + MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
426 + MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD),
427 + MFP_XWAY(GPIO13, GPIO, EBU, SPI, MII),
428 + MFP_XWAY(GPIO14, GPIO, CGU, CBUS, MII),
429 + MFP_XWAY(GPIO15, GPIO, SPI, SDIO, JTAG),
430 + MFP_XWAY(GPIO16, GPIO, SPI, SDIO, JTAG),
431 + MFP_XWAY(GPIO17, GPIO, SPI, SDIO, JTAG),
432 + MFP_XWAY(GPIO18, GPIO, SPI, SDIO, JTAG),
433 + MFP_XWAY(GPIO19, GPIO, PCI, SDIO, MII),
434 + MFP_XWAY(GPIO20, GPIO, JTAG, SDIO, MII),
435 + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
436 + MFP_XWAY(GPIO22, GPIO, SPI, MCD, MII),
437 + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
438 + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
439 + MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC),
440 + MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
441 + MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC),
442 + MFP_XWAY(GPIO28, GPIO, GPT, MII, SDIO),
443 + MFP_XWAY(GPIO29, GPIO, PCI, CBUS, MII),
444 + MFP_XWAY(GPIO30, GPIO, PCI, CBUS, MII),
445 + MFP_XWAY(GPIO31, GPIO, EBU, PCI, MII),
446 +};
447 +
448 +static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2};
449 +
450 +static const unsigned danube_pins_exin0[] = {GPIO0};
451 +static const unsigned danube_pins_exin1[] = {GPIO1};
452 +static const unsigned danube_pins_exin2[] = {GPIO2};
453 +
454 +static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20};
455 +static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12};
456 +static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
457 +static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6};
458 +static const unsigned danube_pins_nmi[] = {GPIO8};
459 +
460 +static const unsigned danube_pins_dfe_led0[] = {GPIO4};
461 +static const unsigned danube_pins_dfe_led1[] = {GPIO5};
462 +
463 +static const unsigned danube_pins_ebu_a24[] = {GPIO13};
464 +static const unsigned danube_pins_ebu_clk[] = {GPIO21};
465 +static const unsigned danube_pins_ebu_cs1[] = {GPIO23};
466 +static const unsigned danube_pins_ebu_a23[] = {GPIO24};
467 +static const unsigned danube_pins_ebu_wait[] = {GPIO26};
468 +static const unsigned danube_pins_ebu_a25[] = {GPIO31};
469 +
470 +static const unsigned danube_pins_nand_ale[] = {GPIO13};
471 +static const unsigned danube_pins_nand_cs1[] = {GPIO23};
472 +static const unsigned danube_pins_nand_cle[] = {GPIO24};
473 +
474 +static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */
475 +static const unsigned danube_pins_spi_di[] = {GPIO16};
476 +static const unsigned danube_pins_spi_do[] = {GPIO17};
477 +static const unsigned danube_pins_spi_clk[] = {GPIO18};
478 +static const unsigned danube_pins_spi_cs1[] = {GPIO15};
479 +static const unsigned danube_pins_spi_cs2[] = {GPIO21};
480 +static const unsigned danube_pins_spi_cs3[] = {GPIO13};
481 +static const unsigned danube_pins_spi_cs4[] = {GPIO10};
482 +static const unsigned danube_pins_spi_cs5[] = {GPIO9};
483 +static const unsigned danube_pins_spi_cs6[] = {GPIO11};
484 +
485 +static const unsigned danube_pins_gpt1[] = {GPIO28};
486 +static const unsigned danube_pins_gpt2[] = {GPIO21};
487 +static const unsigned danube_pins_gpt3[] = {GPIO6};
488 +
489 +static const unsigned danube_pins_clkout0[] = {GPIO8};
490 +static const unsigned danube_pins_clkout1[] = {GPIO7};
491 +static const unsigned danube_pins_clkout2[] = {GPIO3};
492 +static const unsigned danube_pins_clkout3[] = {GPIO2};
493 +
494 +static const unsigned danube_pins_pci_gnt1[] = {GPIO30};
495 +static const unsigned danube_pins_pci_gnt2[] = {GPIO23};
496 +static const unsigned danube_pins_pci_gnt3[] = {GPIO19};
497 +static const unsigned danube_pins_pci_req1[] = {GPIO29};
498 +static const unsigned danube_pins_pci_req2[] = {GPIO31};
499 +static const unsigned danube_pins_pci_req3[] = {GPIO3};
500 +
501 +static const struct ltq_pin_group danube_grps[] = {
502 + GRP_MUX("exin0", EXIN, danube_pins_exin0),
503 + GRP_MUX("exin1", EXIN, danube_pins_exin1),
504 + GRP_MUX("exin2", EXIN, danube_pins_exin2),
505 + GRP_MUX("jtag", JTAG, danube_pins_jtag),
506 + GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23),
507 + GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24),
508 + GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25),
509 + GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk),
510 + GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1),
511 + GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait),
512 + GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
513 + GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
514 + GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
515 + GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
516 + GRP_MUX("spi_di", SPI, danube_pins_spi_di),
517 + GRP_MUX("spi_do", SPI, danube_pins_spi_do),
518 + GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
519 + GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
520 + GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
521 + GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
522 + GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
523 + GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
524 + GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
525 + GRP_MUX("asc0", ASC, danube_pins_asc0),
526 + GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts),
527 + GRP_MUX("stp", STP, danube_pins_stp),
528 + GRP_MUX("nmi", NMI, danube_pins_nmi),
529 + GRP_MUX("gpt1", GPT, danube_pins_gpt1),
530 + GRP_MUX("gpt2", GPT, danube_pins_gpt2),
531 + GRP_MUX("gpt3", GPT, danube_pins_gpt3),
532 + GRP_MUX("clkout0", CGU, danube_pins_clkout0),
533 + GRP_MUX("clkout1", CGU, danube_pins_clkout1),
534 + GRP_MUX("clkout2", CGU, danube_pins_clkout2),
535 + GRP_MUX("clkout3", CGU, danube_pins_clkout3),
536 + GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1),
537 + GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2),
538 + GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3),
539 + GRP_MUX("req1", PCI, danube_pins_pci_req1),
540 + GRP_MUX("req2", PCI, danube_pins_pci_req2),
541 + GRP_MUX("req3", PCI, danube_pins_pci_req3),
542 + GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0),
543 + GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1),
544 +};
545 +
546 +static const char * const danube_pci_grps[] = {"gnt1", "gnt2",
547 + "gnt3", "req1",
548 + "req2", "req3"};
549 +static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
550 + "spi_di", "spi_do",
551 + "spi_clk", "spi_cs1",
552 + "spi_cs2", "spi_cs3",
553 + "spi_cs4", "spi_cs5",
554 + "spi_cs6"};
555 +static const char * const danube_cgu_grps[] = {"clkout0", "clkout1",
556 + "clkout2", "clkout3"};
557 +static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24",
558 + "ebu a25", "ebu cs1",
559 + "ebu wait", "ebu clk",
560 + "nand ale", "nand cs1",
561 + "nand cle"};
562 +static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"};
563 +static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"};
564 +static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
565 +static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"};
566 +static const char * const danube_jtag_grps[] = {"jtag"};
567 +static const char * const danube_stp_grps[] = {"stp"};
568 +static const char * const danube_nmi_grps[] = {"nmi"};
569 +
570 +static const struct ltq_pmx_func danube_funcs[] = {
571 + {"spi", ARRAY_AND_SIZE(danube_spi_grps)},
572 + {"asc", ARRAY_AND_SIZE(danube_asc_grps)},
573 + {"cgu", ARRAY_AND_SIZE(danube_cgu_grps)},
574 + {"jtag", ARRAY_AND_SIZE(danube_jtag_grps)},
575 + {"exin", ARRAY_AND_SIZE(danube_exin_grps)},
576 + {"stp", ARRAY_AND_SIZE(danube_stp_grps)},
577 + {"gpt", ARRAY_AND_SIZE(danube_gpt_grps)},
578 + {"nmi", ARRAY_AND_SIZE(danube_nmi_grps)},
579 + {"pci", ARRAY_AND_SIZE(danube_pci_grps)},
580 + {"ebu", ARRAY_AND_SIZE(danube_ebu_grps)},
581 + {"dfe", ARRAY_AND_SIZE(danube_dfe_grps)},
582 +};
583 +
584 +/* --------- xrx100 related code --------- */
585 +#define XRX100_MAX_PIN 56
586 +
587 +static const struct ltq_mfp_pin xrx100_mfp[] = {
588 + /* pin f0 f1 f2 f3 */
589 + MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
590 + MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN),
591 + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
592 + MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
593 + MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC),
594 + MFP_XWAY(GPIO5, GPIO, STP, NONE, DFE),
595 + MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
596 + MFP_XWAY(GPIO7, GPIO, CGU, CBUS, NONE),
597 + MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
598 + MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
599 + MFP_XWAY(GPIO10, GPIO, ASC, SPI, EXIN),
600 + MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
601 + MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD),
602 + MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
603 + MFP_XWAY(GPIO14, GPIO, CGU, NONE, NONE),
604 + MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
605 + MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
606 + MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
607 + MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
608 + MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU),
609 + MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU),
610 + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
611 + MFP_XWAY(GPIO22, GPIO, SPI, NONE, EBU),
612 + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
613 + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
614 + MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC),
615 + MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
616 + MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC),
617 + MFP_XWAY(GPIO28, GPIO, GPT, NONE, SDIO),
618 + MFP_XWAY(GPIO29, GPIO, PCI, CBUS, NONE),
619 + MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE),
620 + MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
621 + MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU),
622 + MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU),
623 + MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE),
624 + MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE),
625 + MFP_XWAY(GPIO36, GPIO, SIN, SSI, NONE),
626 + MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
627 + MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
628 + MFP_XWAY(GPIO39, GPIO, NONE, EXIN, NONE),
629 + MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE),
630 + MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE),
631 + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
632 + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
633 + MFP_XWAY(GPIO44, GPIO, MII, SIN, NONE),
634 + MFP_XWAY(GPIO45, GPIO, MII, NONE, SIN),
635 + MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN),
636 + MFP_XWAY(GPIO47, GPIO, MII, NONE, SIN),
637 + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
638 + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
639 + MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
640 + MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
641 + MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
642 + MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
643 + MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
644 + MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
645 +};
646 +
647 +static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
648 +
649 +static const unsigned xrx100_pins_exin0[] = {GPIO0};
650 +static const unsigned xrx100_pins_exin1[] = {GPIO1};
651 +static const unsigned xrx100_pins_exin2[] = {GPIO2};
652 +static const unsigned xrx100_pins_exin3[] = {GPIO39};
653 +static const unsigned xrx100_pins_exin4[] = {GPIO10};
654 +static const unsigned xrx100_pins_exin5[] = {GPIO9};
655 +
656 +static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12};
657 +static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
658 +static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6};
659 +static const unsigned xrx100_pins_nmi[] = {GPIO8};
660 +static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43};
661 +
662 +static const unsigned xrx100_pins_dfe_led0[] = {GPIO4};
663 +static const unsigned xrx100_pins_dfe_led1[] = {GPIO5};
664 +
665 +static const unsigned xrx100_pins_ebu_a24[] = {GPIO13};
666 +static const unsigned xrx100_pins_ebu_clk[] = {GPIO21};
667 +static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23};
668 +static const unsigned xrx100_pins_ebu_a23[] = {GPIO24};
669 +static const unsigned xrx100_pins_ebu_wait[] = {GPIO26};
670 +static const unsigned xrx100_pins_ebu_a25[] = {GPIO31};
671 +
672 +static const unsigned xrx100_pins_nand_ale[] = {GPIO13};
673 +static const unsigned xrx100_pins_nand_cs1[] = {GPIO23};
674 +static const unsigned xrx100_pins_nand_cle[] = {GPIO24};
675 +static const unsigned xrx100_pins_nand_rdy[] = {GPIO48};
676 +static const unsigned xrx100_pins_nand_rd[] = {GPIO49};
677 +
678 +static const unsigned xrx100_pins_spi_di[] = {GPIO16};
679 +static const unsigned xrx100_pins_spi_do[] = {GPIO17};
680 +static const unsigned xrx100_pins_spi_clk[] = {GPIO18};
681 +static const unsigned xrx100_pins_spi_cs1[] = {GPIO15};
682 +static const unsigned xrx100_pins_spi_cs2[] = {GPIO22};
683 +static const unsigned xrx100_pins_spi_cs3[] = {GPIO13};
684 +static const unsigned xrx100_pins_spi_cs4[] = {GPIO10};
685 +static const unsigned xrx100_pins_spi_cs5[] = {GPIO9};
686 +static const unsigned xrx100_pins_spi_cs6[] = {GPIO11};
687 +
688 +static const unsigned xrx100_pins_gpt1[] = {GPIO28};
689 +static const unsigned xrx100_pins_gpt2[] = {GPIO21};
690 +static const unsigned xrx100_pins_gpt3[] = {GPIO6};
691 +
692 +static const unsigned xrx100_pins_clkout0[] = {GPIO8};
693 +static const unsigned xrx100_pins_clkout1[] = {GPIO7};
694 +static const unsigned xrx100_pins_clkout2[] = {GPIO3};
695 +static const unsigned xrx100_pins_clkout3[] = {GPIO2};
696 +
697 +static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30};
698 +static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23};
699 +static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19};
700 +static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38};
701 +static const unsigned xrx100_pins_pci_req1[] = {GPIO29};
702 +static const unsigned xrx100_pins_pci_req2[] = {GPIO31};
703 +static const unsigned xrx100_pins_pci_req3[] = {GPIO3};
704 +static const unsigned xrx100_pins_pci_req4[] = {GPIO37};
705 +
706 +static const struct ltq_pin_group xrx100_grps[] = {
707 + GRP_MUX("exin0", EXIN, xrx100_pins_exin0),
708 + GRP_MUX("exin1", EXIN, xrx100_pins_exin1),
709 + GRP_MUX("exin2", EXIN, xrx100_pins_exin2),
710 + GRP_MUX("exin3", EXIN, xrx100_pins_exin3),
711 + GRP_MUX("exin4", EXIN, xrx100_pins_exin4),
712 + GRP_MUX("exin5", EXIN, xrx100_pins_exin5),
713 + GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23),
714 + GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24),
715 + GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25),
716 + GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk),
717 + GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1),
718 + GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait),
719 + GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
720 + GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
721 + GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
722 + GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
723 + GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
724 + GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
725 + GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
726 + GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
727 + GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
728 + GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
729 + GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
730 + GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
731 + GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
732 + GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
733 + GRP_MUX("asc0", ASC, xrx100_pins_asc0),
734 + GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts),
735 + GRP_MUX("stp", STP, xrx100_pins_stp),
736 + GRP_MUX("nmi", NMI, xrx100_pins_nmi),
737 + GRP_MUX("gpt1", GPT, xrx100_pins_gpt1),
738 + GRP_MUX("gpt2", GPT, xrx100_pins_gpt2),
739 + GRP_MUX("gpt3", GPT, xrx100_pins_gpt3),
740 + GRP_MUX("clkout0", CGU, xrx100_pins_clkout0),
741 + GRP_MUX("clkout1", CGU, xrx100_pins_clkout1),
742 + GRP_MUX("clkout2", CGU, xrx100_pins_clkout2),
743 + GRP_MUX("clkout3", CGU, xrx100_pins_clkout3),
744 + GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1),
745 + GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2),
746 + GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3),
747 + GRP_MUX("gnt4", PCI, xrx100_pins_pci_gnt4),
748 + GRP_MUX("req1", PCI, xrx100_pins_pci_req1),
749 + GRP_MUX("req2", PCI, xrx100_pins_pci_req2),
750 + GRP_MUX("req3", PCI, xrx100_pins_pci_req3),
751 + GRP_MUX("req4", PCI, xrx100_pins_pci_req4),
752 + GRP_MUX("mdio", MDIO, xrx100_pins_mdio),
753 + GRP_MUX("dfe led0", DFE, xrx100_pins_dfe_led0),
754 + GRP_MUX("dfe led1", DFE, xrx100_pins_dfe_led1),
755 +};
756 +
757 +static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2",
758 + "gnt3", "gnt4",
759 + "req1", "req2",
760 + "req3", "req4"};
761 +static const char * const xrx100_spi_grps[] = {"spi_di", "spi_do",
762 + "spi_clk", "spi_cs1",
763 + "spi_cs2", "spi_cs3",
764 + "spi_cs4", "spi_cs5",
765 + "spi_cs6"};
766 +static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1",
767 + "clkout2", "clkout3"};
768 +static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24",
769 + "ebu a25", "ebu cs1",
770 + "ebu wait", "ebu clk",
771 + "nand ale", "nand cs1",
772 + "nand cle", "nand rdy",
773 + "nand rd"};
774 +static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2",
775 + "exin3", "exin4", "exin5"};
776 +static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
777 +static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"};
778 +static const char * const xrx100_stp_grps[] = {"stp"};
779 +static const char * const xrx100_nmi_grps[] = {"nmi"};
780 +static const char * const xrx100_mdio_grps[] = {"mdio"};
781 +static const char * const xrx100_dfe_grps[] = {"dfe led0", "dfe led1"};
782 +
783 +static const struct ltq_pmx_func xrx100_funcs[] = {
784 + {"spi", ARRAY_AND_SIZE(xrx100_spi_grps)},
785 + {"asc", ARRAY_AND_SIZE(xrx100_asc_grps)},
786 + {"cgu", ARRAY_AND_SIZE(xrx100_cgu_grps)},
787 + {"exin", ARRAY_AND_SIZE(xrx100_exin_grps)},
788 + {"stp", ARRAY_AND_SIZE(xrx100_stp_grps)},
789 + {"gpt", ARRAY_AND_SIZE(xrx100_gpt_grps)},
790 + {"nmi", ARRAY_AND_SIZE(xrx100_nmi_grps)},
791 + {"pci", ARRAY_AND_SIZE(xrx100_pci_grps)},
792 + {"ebu", ARRAY_AND_SIZE(xrx100_ebu_grps)},
793 + {"mdio", ARRAY_AND_SIZE(xrx100_mdio_grps)},
794 + {"dfe", ARRAY_AND_SIZE(xrx100_dfe_grps)},
795 +};
796 +
797 +/* --------- xrx200 related code --------- */
798 +#define XRX200_MAX_PIN 50
799 +
800 +static const struct ltq_mfp_pin xrx200_mfp[] = {
801 + /* pin f0 f1 f2 f3 */
802 + MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
803 + MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN),
804 + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
805 + MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
806 + MFP_XWAY(GPIO4, GPIO, STP, DFE, USIF),
807 + MFP_XWAY(GPIO5, GPIO, STP, GPHY, DFE),
808 + MFP_XWAY(GPIO6, GPIO, STP, GPT, USIF),
809 + MFP_XWAY(GPIO7, GPIO, CGU, CBUS, GPHY),
810 + MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
811 + MFP_XWAY(GPIO9, GPIO, USIF, SPI, EXIN),
812 + MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
813 + MFP_XWAY(GPIO11, GPIO, USIF, CBUS, SPI),
814 + MFP_XWAY(GPIO12, GPIO, USIF, CBUS, MCD),
815 + MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
816 + MFP_XWAY(GPIO14, GPIO, CGU, CBUS, USIF),
817 + MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
818 + MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
819 + MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
820 + MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
821 + MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU),
822 + MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU),
823 + MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
824 + MFP_XWAY(GPIO22, GPIO, SPI, CGU, EBU),
825 + MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
826 + MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
827 + MFP_XWAY(GPIO25, GPIO, TDM, SDIO, USIF),
828 + MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
829 + MFP_XWAY(GPIO27, GPIO, TDM, SDIO, USIF),
830 + MFP_XWAY(GPIO28, GPIO, GPT, PCI, SDIO),
831 + MFP_XWAY(GPIO29, GPIO, PCI, CBUS, EXIN),
832 + MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE),
833 + MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
834 + MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU),
835 + MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU),
836 + MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE),
837 + MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE),
838 + MFP_XWAY(GPIO36, GPIO, SIN, SSI, EXIN),
839 + MFP_XWAY(GPIO37, GPIO, USIF, NONE, PCI),
840 + MFP_XWAY(GPIO38, GPIO, PCI, USIF, NONE),
841 + MFP_XWAY(GPIO39, GPIO, USIF, EXIN, NONE),
842 + MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE),
843 + MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE),
844 + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
845 + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
846 + MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY),
847 + MFP_XWAY(GPIO45, GPIO, MII, GPHY, SIN),
848 + MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN),
849 + MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN),
850 + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
851 + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
852 +};
853 +
854 +static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
855 +
856 +static const unsigned xrx200_pins_exin0[] = {GPIO0};
857 +static const unsigned xrx200_pins_exin1[] = {GPIO1};
858 +static const unsigned xrx200_pins_exin2[] = {GPIO2};
859 +static const unsigned xrx200_pins_exin3[] = {GPIO39};
860 +static const unsigned xrx200_pins_exin4[] = {GPIO10};
861 +static const unsigned xrx200_pins_exin5[] = {GPIO9};
862 +
863 +static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11};
864 +static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12};
865 +static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9};
866 +static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10};
867 +static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4};
868 +static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6};
869 +static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25};
870 +static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27};
871 +
872 +static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};
873 +static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};
874 +static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};
875 +static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};
876 +static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};
877 +static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};
878 +
879 +static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6};
880 +static const unsigned xrx200_pins_nmi[] = {GPIO8};
881 +static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43};
882 +
883 +static const unsigned xrx200_pins_dfe_led0[] = {GPIO4};
884 +static const unsigned xrx200_pins_dfe_led1[] = {GPIO5};
885 +
886 +static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5};
887 +static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7};
888 +static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2};
889 +static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44};
890 +static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45};
891 +static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47};
892 +
893 +static const unsigned xrx200_pins_ebu_a24[] = {GPIO13};
894 +static const unsigned xrx200_pins_ebu_clk[] = {GPIO21};
895 +static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23};
896 +static const unsigned xrx200_pins_ebu_a23[] = {GPIO24};
897 +static const unsigned xrx200_pins_ebu_wait[] = {GPIO26};
898 +static const unsigned xrx200_pins_ebu_a25[] = {GPIO31};
899 +
900 +static const unsigned xrx200_pins_nand_ale[] = {GPIO13};
901 +static const unsigned xrx200_pins_nand_cs1[] = {GPIO23};
902 +static const unsigned xrx200_pins_nand_cle[] = {GPIO24};
903 +static const unsigned xrx200_pins_nand_rdy[] = {GPIO48};
904 +static const unsigned xrx200_pins_nand_rd[] = {GPIO49};
905 +
906 +static const unsigned xrx200_pins_spi_di[] = {GPIO16};
907 +static const unsigned xrx200_pins_spi_do[] = {GPIO17};
908 +static const unsigned xrx200_pins_spi_clk[] = {GPIO18};
909 +static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};
910 +static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};
911 +static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};
912 +static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};
913 +static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};
914 +static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};
915 +
916 +static const unsigned xrx200_pins_gpt1[] = {GPIO28};
917 +static const unsigned xrx200_pins_gpt2[] = {GPIO21};
918 +static const unsigned xrx200_pins_gpt3[] = {GPIO6};
919 +
920 +static const unsigned xrx200_pins_clkout0[] = {GPIO8};
921 +static const unsigned xrx200_pins_clkout1[] = {GPIO7};
922 +static const unsigned xrx200_pins_clkout2[] = {GPIO3};
923 +static const unsigned xrx200_pins_clkout3[] = {GPIO2};
924 +
925 +static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28};
926 +static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23};
927 +static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19};
928 +static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38};
929 +static const unsigned xrx200_pins_pci_req1[] = {GPIO29};
930 +static const unsigned xrx200_pins_pci_req2[] = {GPIO31};
931 +static const unsigned xrx200_pins_pci_req3[] = {GPIO3};
932 +static const unsigned xrx200_pins_pci_req4[] = {GPIO37};
933 +
934 +static const struct ltq_pin_group xrx200_grps[] = {
935 + GRP_MUX("exin0", EXIN, xrx200_pins_exin0),
936 + GRP_MUX("exin1", EXIN, xrx200_pins_exin1),
937 + GRP_MUX("exin2", EXIN, xrx200_pins_exin2),
938 + GRP_MUX("exin3", EXIN, xrx200_pins_exin3),
939 + GRP_MUX("exin4", EXIN, xrx200_pins_exin4),
940 + GRP_MUX("exin5", EXIN, xrx200_pins_exin5),
941 + GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23),
942 + GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24),
943 + GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25),
944 + GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk),
945 + GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1),
946 + GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait),
947 + GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
948 + GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
949 + GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
950 + GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
951 + GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
952 + GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
953 + GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
954 + GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
955 + GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
956 + GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
957 + GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
958 + GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
959 + GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
960 + GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
961 + GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx),
962 + GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_tx),
963 + GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts),
964 + GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts),
965 + GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr),
966 + GRP_MUX("usif uart_dsr", USIF, xrx200_pins_usif_uart_dsr),
967 + GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd),
968 + GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri),
969 + GRP_MUX("usif spi_di", USIF, xrx200_pins_usif_spi_di),
970 + GRP_MUX("usif spi_do", USIF, xrx200_pins_usif_spi_do),
971 + GRP_MUX("usif spi_clk", USIF, xrx200_pins_usif_spi_clk),
972 + GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0),
973 + GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1),
974 + GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2),
975 + GRP_MUX("stp", STP, xrx200_pins_stp),
976 + GRP_MUX("nmi", NMI, xrx200_pins_nmi),
977 + GRP_MUX("gpt1", GPT, xrx200_pins_gpt1),
978 + GRP_MUX("gpt2", GPT, xrx200_pins_gpt2),
979 + GRP_MUX("gpt3", GPT, xrx200_pins_gpt3),
980 + GRP_MUX("clkout0", CGU, xrx200_pins_clkout0),
981 + GRP_MUX("clkout1", CGU, xrx200_pins_clkout1),
982 + GRP_MUX("clkout2", CGU, xrx200_pins_clkout2),
983 + GRP_MUX("clkout3", CGU, xrx200_pins_clkout3),
984 + GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1),
985 + GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2),
986 + GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3),
987 + GRP_MUX("gnt4", PCI, xrx200_pins_pci_gnt4),
988 + GRP_MUX("req1", PCI, xrx200_pins_pci_req1),
989 + GRP_MUX("req2", PCI, xrx200_pins_pci_req2),
990 + GRP_MUX("req3", PCI, xrx200_pins_pci_req3),
991 + GRP_MUX("req4", PCI, xrx200_pins_pci_req4),
992 + GRP_MUX("mdio", MDIO, xrx200_pins_mdio),
993 + GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0),
994 + GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1),
995 + GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0),
996 + GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1),
997 + GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2),
998 + GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0),
999 + GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1),
1000 + GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2),
1001 +};
1002 +
1003 +static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2",
1004 + "gnt3", "gnt4",
1005 + "req1", "req2",
1006 + "req3", "req4"};
1007 +static const char * const xrx200_spi_grps[] = {"spi_di", "spi_do",
1008 + "spi_clk", "spi_cs1",
1009 + "spi_cs2", "spi_cs3",
1010 + "spi_cs4", "spi_cs5",
1011 + "spi_cs6"};
1012 +static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1",
1013 + "clkout2", "clkout3"};
1014 +static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24",
1015 + "ebu a25", "ebu cs1",
1016 + "ebu wait", "ebu clk",
1017 + "nand ale", "nand cs1",
1018 + "nand cle", "nand rdy",
1019 + "nand rd"};
1020 +static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2",
1021 + "exin3", "exin4", "exin5"};
1022 +static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
1023 +static const char * const xrx200_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1024 + "usif uart_rts", "usif uart_cts",
1025 + "usif uart_dtr", "usif uart_dsr",
1026 + "usif uart_dcd", "usif uart_ri",
1027 + "usif spi_di", "usif spi_do",
1028 + "usif spi_clk", "usif spi_cs0",
1029 + "usif spi_cs1", "usif spi_cs2"};
1030 +static const char * const xrx200_stp_grps[] = {"stp"};
1031 +static const char * const xrx200_nmi_grps[] = {"nmi"};
1032 +static const char * const xrx200_mdio_grps[] = {"mdio"};
1033 +static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"};
1034 +static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
1035 + "gphy0 led2", "gphy1 led0",
1036 + "gphy1 led1", "gphy1 led2"};
1037 +
1038 +static const struct ltq_pmx_func xrx200_funcs[] = {
1039 + {"spi", ARRAY_AND_SIZE(xrx200_spi_grps)},
1040 + {"usif", ARRAY_AND_SIZE(xrx200_usif_grps)},
1041 + {"cgu", ARRAY_AND_SIZE(xrx200_cgu_grps)},
1042 + {"exin", ARRAY_AND_SIZE(xrx200_exin_grps)},
1043 + {"stp", ARRAY_AND_SIZE(xrx200_stp_grps)},
1044 + {"gpt", ARRAY_AND_SIZE(xrx200_gpt_grps)},
1045 + {"nmi", ARRAY_AND_SIZE(xrx200_nmi_grps)},
1046 + {"pci", ARRAY_AND_SIZE(xrx200_pci_grps)},
1047 + {"ebu", ARRAY_AND_SIZE(xrx200_ebu_grps)},
1048 + {"mdio", ARRAY_AND_SIZE(xrx200_mdio_grps)},
1049 + {"dfe", ARRAY_AND_SIZE(xrx200_dfe_grps)},
1050 + {"gphy", ARRAY_AND_SIZE(xrx200_gphy_grps)},
1051 +};
1052 +
1053 +/* --------- xrx300 related code --------- */
1054 +#define XRX300_MAX_PIN 64
1055 +
1056 +static const struct ltq_mfp_pin xrx300_mfp[] = {
1057 + /* pin f0 f1 f2 f3 */
1058 + MFP_XWAY(GPIO0, GPIO, EXIN, EPHY, NONE),
1059 + MFP_XWAY(GPIO1, GPIO, NONE, EXIN, NONE),
1060 + MFP_XWAY(GPIO2, NONE, NONE, NONE, NONE),
1061 + MFP_XWAY(GPIO3, GPIO, CGU, NONE, NONE),
1062 + MFP_XWAY(GPIO4, GPIO, STP, DFE, NONE),
1063 + MFP_XWAY(GPIO5, GPIO, STP, EPHY, DFE),
1064 + MFP_XWAY(GPIO6, GPIO, STP, NONE, NONE),
1065 + MFP_XWAY(GPIO7, NONE, NONE, NONE, NONE),
1066 + MFP_XWAY(GPIO8, GPIO, CGU, GPHY, EPHY),
1067 + MFP_XWAY(GPIO9, GPIO, WIFI, NONE, EXIN),
1068 + MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
1069 + MFP_XWAY(GPIO11, GPIO, USIF, WIFI, SPI),
1070 + MFP_XWAY(GPIO12, NONE, NONE, NONE, NONE),
1071 + MFP_XWAY(GPIO13, GPIO, EBU, NONE, NONE),
1072 + MFP_XWAY(GPIO14, GPIO, CGU, USIF, EPHY),
1073 + MFP_XWAY(GPIO15, GPIO, SPI, NONE, MCD),
1074 + MFP_XWAY(GPIO16, GPIO, SPI, EXIN, NONE),
1075 + MFP_XWAY(GPIO17, GPIO, SPI, NONE, NONE),
1076 + MFP_XWAY(GPIO18, GPIO, SPI, NONE, NONE),
1077 + MFP_XWAY(GPIO19, GPIO, USIF, NONE, EPHY),
1078 + MFP_XWAY(GPIO20, NONE, NONE, NONE, NONE),
1079 + MFP_XWAY(GPIO21, NONE, NONE, NONE, NONE),
1080 + MFP_XWAY(GPIO22, NONE, NONE, NONE, NONE),
1081 + MFP_XWAY(GPIO23, GPIO, EBU, NONE, NONE),
1082 + MFP_XWAY(GPIO24, GPIO, EBU, NONE, NONE),
1083 + MFP_XWAY(GPIO25, GPIO, TDM, NONE, NONE),
1084 + MFP_XWAY(GPIO26, GPIO, TDM, NONE, NONE),
1085 + MFP_XWAY(GPIO27, GPIO, TDM, NONE, NONE),
1086 + MFP_XWAY(GPIO28, NONE, NONE, NONE, NONE),
1087 + MFP_XWAY(GPIO29, NONE, NONE, NONE, NONE),
1088 + MFP_XWAY(GPIO30, NONE, NONE, NONE, NONE),
1089 + MFP_XWAY(GPIO31, NONE, NONE, NONE, NONE),
1090 + MFP_XWAY(GPIO32, NONE, NONE, NONE, NONE),
1091 + MFP_XWAY(GPIO33, NONE, NONE, NONE, NONE),
1092 + MFP_XWAY(GPIO34, GPIO, NONE, SSI, NONE),
1093 + MFP_XWAY(GPIO35, GPIO, NONE, SSI, NONE),
1094 + MFP_XWAY(GPIO36, GPIO, NONE, SSI, NONE),
1095 + MFP_XWAY(GPIO37, NONE, NONE, NONE, NONE),
1096 + MFP_XWAY(GPIO38, NONE, NONE, NONE, NONE),
1097 + MFP_XWAY(GPIO39, NONE, NONE, NONE, NONE),
1098 + MFP_XWAY(GPIO40, NONE, NONE, NONE, NONE),
1099 + MFP_XWAY(GPIO41, NONE, NONE, NONE, NONE),
1100 + MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
1101 + MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
1102 + MFP_XWAY(GPIO44, NONE, NONE, NONE, NONE),
1103 + MFP_XWAY(GPIO45, NONE, NONE, NONE, NONE),
1104 + MFP_XWAY(GPIO46, NONE, NONE, NONE, NONE),
1105 + MFP_XWAY(GPIO47, NONE, NONE, NONE, NONE),
1106 + MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
1107 + MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
1108 + MFP_XWAY(GPIO50, GPIO, EBU, NONE, NONE),
1109 + MFP_XWAY(GPIO51, GPIO, EBU, NONE, NONE),
1110 + MFP_XWAY(GPIO52, GPIO, EBU, NONE, NONE),
1111 + MFP_XWAY(GPIO53, GPIO, EBU, NONE, NONE),
1112 + MFP_XWAY(GPIO54, GPIO, EBU, NONE, NONE),
1113 + MFP_XWAY(GPIO55, GPIO, EBU, NONE, NONE),
1114 + MFP_XWAY(GPIO56, GPIO, EBU, NONE, NONE),
1115 + MFP_XWAY(GPIO57, GPIO, EBU, NONE, NONE),
1116 + MFP_XWAY(GPIO58, GPIO, EBU, TDM, NONE),
1117 + MFP_XWAY(GPIO59, GPIO, EBU, NONE, NONE),
1118 + MFP_XWAY(GPIO60, GPIO, EBU, NONE, NONE),
1119 + MFP_XWAY(GPIO61, GPIO, EBU, NONE, NONE),
1120 + MFP_XWAY(GPIO62, NONE, NONE, NONE, NONE),
1121 + MFP_XWAY(GPIO63, NONE, NONE, NONE, NONE),
1122 +};
1123 +
1124 +static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9};
1125 +
1126 +static const unsigned xrx300_pins_exin0[] = {GPIO0};
1127 +static const unsigned xrx300_pins_exin1[] = {GPIO1};
1128 +static const unsigned xrx300_pins_exin2[] = {GPIO16};
1129 +/* EXIN3 is not available on xrX300 */
1130 +static const unsigned xrx300_pins_exin4[] = {GPIO10};
1131 +static const unsigned xrx300_pins_exin5[] = {GPIO9};
1132 +
1133 +static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11};
1134 +static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10};
1135 +
1136 +static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11};
1137 +static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10};
1138 +static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19};
1139 +static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14};
1140 +
1141 +static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6};
1142 +static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43};
1143 +
1144 +static const unsigned xrx300_pins_dfe_led0[] = {GPIO4};
1145 +static const unsigned xrx300_pins_dfe_led1[] = {GPIO5};
1146 +
1147 +static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5};
1148 +static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8};
1149 +static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14};
1150 +static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19};
1151 +
1152 +static const unsigned xrx300_pins_nand_ale[] = {GPIO13};
1153 +static const unsigned xrx300_pins_nand_cs1[] = {GPIO23};
1154 +static const unsigned xrx300_pins_nand_cle[] = {GPIO24};
1155 +static const unsigned xrx300_pins_nand_rdy[] = {GPIO48};
1156 +static const unsigned xrx300_pins_nand_rd[] = {GPIO49};
1157 +static const unsigned xrx300_pins_nand_d1[] = {GPIO50};
1158 +static const unsigned xrx300_pins_nand_d0[] = {GPIO51};
1159 +static const unsigned xrx300_pins_nand_d2[] = {GPIO52};
1160 +static const unsigned xrx300_pins_nand_d7[] = {GPIO53};
1161 +static const unsigned xrx300_pins_nand_d6[] = {GPIO54};
1162 +static const unsigned xrx300_pins_nand_d5[] = {GPIO55};
1163 +static const unsigned xrx300_pins_nand_d4[] = {GPIO56};
1164 +static const unsigned xrx300_pins_nand_d3[] = {GPIO57};
1165 +static const unsigned xrx300_pins_nand_cs0[] = {GPIO58};
1166 +static const unsigned xrx300_pins_nand_wr[] = {GPIO59};
1167 +static const unsigned xrx300_pins_nand_wp[] = {GPIO60};
1168 +static const unsigned xrx300_pins_nand_se[] = {GPIO61};
1169 +
1170 +static const unsigned xrx300_pins_spi_di[] = {GPIO16};
1171 +static const unsigned xrx300_pins_spi_do[] = {GPIO17};
1172 +static const unsigned xrx300_pins_spi_clk[] = {GPIO18};
1173 +static const unsigned xrx300_pins_spi_cs1[] = {GPIO15};
1174 +/* SPI_CS2 is not available on xrX300 */
1175 +/* SPI_CS3 is not available on xrX300 */
1176 +static const unsigned xrx300_pins_spi_cs4[] = {GPIO10};
1177 +/* SPI_CS5 is not available on xrX300 */
1178 +static const unsigned xrx300_pins_spi_cs6[] = {GPIO11};
1179 +
1180 +/* CLKOUT0 is not available on xrX300 */
1181 +/* CLKOUT1 is not available on xrX300 */
1182 +static const unsigned xrx300_pins_clkout2[] = {GPIO3};
1183 +
1184 +static const struct ltq_pin_group xrx300_grps[] = {
1185 + GRP_MUX("exin0", EXIN, xrx300_pins_exin0),
1186 + GRP_MUX("exin1", EXIN, xrx300_pins_exin1),
1187 + GRP_MUX("exin2", EXIN, xrx300_pins_exin2),
1188 + GRP_MUX("exin4", EXIN, xrx300_pins_exin4),
1189 + GRP_MUX("exin5", EXIN, xrx300_pins_exin5),
1190 + GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
1191 + GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
1192 + GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
1193 + GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
1194 + GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
1195 + GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
1196 + GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
1197 + GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
1198 + GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
1199 + GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
1200 + GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
1201 + GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
1202 + GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
1203 + GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
1204 + GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
1205 + GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
1206 + GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
1207 + GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
1208 + GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
1209 + GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
1210 + GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
1211 + GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
1212 + GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
1213 + GRP_MUX("usif uart_rx", USIF, xrx300_pins_usif_uart_rx),
1214 + GRP_MUX("usif uart_tx", USIF, xrx300_pins_usif_uart_tx),
1215 + GRP_MUX("usif spi_di", USIF, xrx300_pins_usif_spi_di),
1216 + GRP_MUX("usif spi_do", USIF, xrx300_pins_usif_spi_do),
1217 + GRP_MUX("usif spi_clk", USIF, xrx300_pins_usif_spi_clk),
1218 + GRP_MUX("usif spi_cs0", USIF, xrx300_pins_usif_spi_cs0),
1219 + GRP_MUX("stp", STP, xrx300_pins_stp),
1220 + GRP_MUX("clkout2", CGU, xrx300_pins_clkout2),
1221 + GRP_MUX("mdio", MDIO, xrx300_pins_mdio),
1222 + GRP_MUX("dfe led0", DFE, xrx300_pins_dfe_led0),
1223 + GRP_MUX("dfe led1", DFE, xrx300_pins_dfe_led1),
1224 + GRP_MUX("ephy0 led0", GPHY, xrx300_pins_ephy0_led0),
1225 + GRP_MUX("ephy0 led1", GPHY, xrx300_pins_ephy0_led1),
1226 + GRP_MUX("ephy1 led0", GPHY, xrx300_pins_ephy1_led0),
1227 + GRP_MUX("ephy1 led1", GPHY, xrx300_pins_ephy1_led1),
1228 +};
1229 +
1230 +static const char * const xrx300_spi_grps[] = {"spi_di", "spi_do",
1231 + "spi_clk", "spi_cs1",
1232 + "spi_cs4", "spi_cs6"};
1233 +static const char * const xrx300_cgu_grps[] = {"clkout2"};
1234 +static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
1235 + "nand cle", "nand rdy",
1236 + "nand rd", "nand d1",
1237 + "nand d0", "nand d2",
1238 + "nand d7", "nand d6",
1239 + "nand d5", "nand d4",
1240 + "nand d3", "nand cs0",
1241 + "nand wr", "nand wp",
1242 + "nand se"};
1243 +static const char * const xrx300_exin_grps[] = {"exin0", "exin1", "exin2",
1244 + "exin4", "exin5"};
1245 +static const char * const xrx300_usif_grps[] = {"usif uart_rx", "usif uart_tx",
1246 + "usif spi_di", "usif spi_do",
1247 + "usif spi_clk", "usif spi_cs0"};
1248 +static const char * const xrx300_stp_grps[] = {"stp"};
1249 +static const char * const xrx300_mdio_grps[] = {"mdio"};
1250 +static const char * const xrx300_dfe_grps[] = {"dfe led0", "dfe led1"};
1251 +static const char * const xrx300_gphy_grps[] = {"ephy0 led0", "ephy0 led1",
1252 + "ephy1 led0", "ephy1 led1"};
1253 +
1254 +static const struct ltq_pmx_func xrx300_funcs[] = {
1255 + {"spi", ARRAY_AND_SIZE(xrx300_spi_grps)},
1256 + {"usif", ARRAY_AND_SIZE(xrx300_usif_grps)},
1257 + {"cgu", ARRAY_AND_SIZE(xrx300_cgu_grps)},
1258 + {"exin", ARRAY_AND_SIZE(xrx300_exin_grps)},
1259 + {"stp", ARRAY_AND_SIZE(xrx300_stp_grps)},
1260 + {"ebu", ARRAY_AND_SIZE(xrx300_ebu_grps)},
1261 + {"mdio", ARRAY_AND_SIZE(xrx300_mdio_grps)},
1262 + {"dfe", ARRAY_AND_SIZE(xrx300_dfe_grps)},
1263 + {"ephy", ARRAY_AND_SIZE(xrx300_gphy_grps)},
1264 +};
1265 +
1266 /* --------- pinconf related code --------- */
1267 static int xway_pinconf_get(struct pinctrl_dev *pctldev,
1268 unsigned pin,
1269 @@ -714,10 +1601,7 @@ static struct gpio_chip xway_chip = {
1270
1271
1272 /* --------- register the pinctrl layer --------- */
1273 -static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
1274 -static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0};
1275 -
1276 -static struct pinctrl_xway_soc {
1277 +struct pinctrl_xway_soc {
1278 int pin_count;
1279 const struct ltq_mfp_pin *mfp;
1280 const struct ltq_pin_group *grps;
1281 @@ -726,22 +1610,54 @@ static struct pinctrl_xway_soc {
1282 unsigned int num_funcs;
1283 const unsigned *exin;
1284 unsigned int num_exin;
1285 -} soc_cfg[] = {
1286 - /* legacy xway */
1287 - {XWAY_MAX_PIN, xway_mfp,
1288 - xway_grps, ARRAY_SIZE(xway_grps),
1289 - danube_funcs, ARRAY_SIZE(danube_funcs),
1290 - xway_exin_pin_map, 3},
1291 - /* xway xr9 series */
1292 - {XR9_MAX_PIN, xway_mfp,
1293 - xway_grps, ARRAY_SIZE(xway_grps),
1294 - xrx_funcs, ARRAY_SIZE(xrx_funcs),
1295 - xway_exin_pin_map, 6},
1296 - /* xway ase series */
1297 - {XWAY_MAX_PIN, ase_mfp,
1298 - ase_grps, ARRAY_SIZE(ase_grps),
1299 - ase_funcs, ARRAY_SIZE(ase_funcs),
1300 - ase_exin_pins_map, 3},
1301 +};
1302 +
1303 +/* xway xr9 series (DEPRECATED: Use XWAY xRX100/xRX200 Family) */
1304 +static struct pinctrl_xway_soc xr9_pinctrl = {
1305 + XR9_MAX_PIN, xway_mfp,
1306 + xway_grps, ARRAY_SIZE(xway_grps),
1307 + xrx_funcs, ARRAY_SIZE(xrx_funcs),
1308 + xway_exin_pin_map, 6
1309 +};
1310 +
1311 +/* XWAY AMAZON Family */
1312 +static struct pinctrl_xway_soc ase_pinctrl = {
1313 + ASE_MAX_PIN, ase_mfp,
1314 + ase_grps, ARRAY_SIZE(ase_grps),
1315 + ase_funcs, ARRAY_SIZE(ase_funcs),
1316 + ase_exin_pin_map, 3
1317 +};
1318 +
1319 +/* XWAY DANUBE Family */
1320 +static struct pinctrl_xway_soc danube_pinctrl = {
1321 + DANUBE_MAX_PIN, danube_mfp,
1322 + danube_grps, ARRAY_SIZE(danube_grps),
1323 + danube_funcs, ARRAY_SIZE(danube_funcs),
1324 + danube_exin_pin_map, 3
1325 +};
1326 +
1327 +/* XWAY xRX100 Family */
1328 +static struct pinctrl_xway_soc xrx100_pinctrl = {
1329 + XRX100_MAX_PIN, xrx100_mfp,
1330 + xrx100_grps, ARRAY_SIZE(xrx100_grps),
1331 + xrx100_funcs, ARRAY_SIZE(xrx100_funcs),
1332 + xrx100_exin_pin_map, 6
1333 +};
1334 +
1335 +/* XWAY xRX200 Family */
1336 +static struct pinctrl_xway_soc xrx200_pinctrl = {
1337 + XRX200_MAX_PIN, xrx200_mfp,
1338 + xrx200_grps, ARRAY_SIZE(xrx200_grps),
1339 + xrx200_funcs, ARRAY_SIZE(xrx200_funcs),
1340 + xrx200_exin_pin_map, 6
1341 +};
1342 +
1343 +/* XWAY xRX300 Family */
1344 +static struct pinctrl_xway_soc xrx300_pinctrl = {
1345 + XRX300_MAX_PIN, xrx300_mfp,
1346 + xrx300_grps, ARRAY_SIZE(xrx300_grps),
1347 + xrx300_funcs, ARRAY_SIZE(xrx300_funcs),
1348 + xrx300_exin_pin_map, 5
1349 };
1350
1351 static struct pinctrl_gpio_range xway_gpio_range = {
1352 @@ -750,9 +1666,14 @@ static struct pinctrl_gpio_range xway_gp
1353 };
1354
1355 static const struct of_device_id xway_match[] = {
1356 - { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]},
1357 - { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]},
1358 - { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]},
1359 + { .compatible = "lantiq,pinctrl-xway", .data = &danube_pinctrl}, /*DEPRECATED*/
1360 + { .compatible = "lantiq,pinctrl-xr9", .data = &xr9_pinctrl}, /*DEPRECATED*/
1361 + { .compatible = "lantiq,pinctrl-ase", .data = &ase_pinctrl}, /*DEPRECATED*/
1362 + { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
1363 + { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
1364 + { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
1365 + { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
1366 + { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
1367 {},
1368 };
1369 MODULE_DEVICE_TABLE(of, xway_match);
1370 @@ -774,7 +1695,7 @@ static int pinmux_xway_probe(struct plat
1371 if (match)
1372 xway_soc = (const struct pinctrl_xway_soc *) match->data;
1373 else
1374 - xway_soc = &soc_cfg[0];
1375 + xway_soc = &danube_pinctrl;
1376
1377 /* find out how many pads we have */
1378 xway_chip.ngpio = xway_soc->pin_count;
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