projects / openwrt / staging / chunkeey.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
layerscape: refresh patches
[openwrt/staging/chunkeey.git] / target / linux / layerscape / patches-4.9 / 702-pci-support-layerscape.patch
1 From c4813da334b0c31e9c55eea015f1e898e84ff45b Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 11:04:10 +0800
4 Subject: [PATCH] pci: support layerscape
5
6 This is a integrated patch for layerscape pcie support.
7
8 Signed-off-by: Po Liu <po.liu@nxp.com>
9 Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
10 Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
11 Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
12 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
13 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
14 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
15 Signed-off-by: Christoph Hellwig <hch@lst.de>
16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
17 ---
18 drivers/irqchip/irq-ls-scfg-msi.c | 256 +++++++--
19 drivers/pci/host/Makefile | 2 +-
20 drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++++++++++
21 drivers/pci/host/pci-layerscape-ep.c | 309 +++++++++++
22 drivers/pci/host/pci-layerscape-ep.h | 115 ++++
23 drivers/pci/host/pci-layerscape.c | 37 +-
24 drivers/pci/host/pcie-designware.c | 6 +
25 drivers/pci/host/pcie-designware.h | 1 +
26 drivers/pci/pcie/portdrv_core.c | 181 +++----
27 include/linux/pci.h | 1 +
28 10 files changed, 1518 insertions(+), 148 deletions(-)
29 create mode 100644 drivers/pci/host/pci-layerscape-ep-debugfs.c
30 create mode 100644 drivers/pci/host/pci-layerscape-ep.c
31 create mode 100644 drivers/pci/host/pci-layerscape-ep.h
32
33 --- a/drivers/irqchip/irq-ls-scfg-msi.c
34 +++ b/drivers/irqchip/irq-ls-scfg-msi.c
35 @@ -17,13 +17,32 @@
36 #include <linux/irq.h>
37 #include <linux/irqchip/chained_irq.h>
38 #include <linux/irqdomain.h>
39 +#include <linux/of_irq.h>
40 #include <linux/of_pci.h>
41 #include <linux/of_platform.h>
42 #include <linux/spinlock.h>
43
44 -#define MSI_MAX_IRQS 32
45 -#define MSI_IBS_SHIFT 3
46 -#define MSIR 4
47 +#define MSI_IRQS_PER_MSIR 32
48 +#define MSI_MSIR_OFFSET 4
49 +
50 +#define MSI_LS1043V1_1_IRQS_PER_MSIR 8
51 +#define MSI_LS1043V1_1_MSIR_OFFSET 0x10
52 +
53 +struct ls_scfg_msi_cfg {
54 + u32 ibs_shift; /* Shift of interrupt bit select */
55 + u32 msir_irqs; /* The irq number per MSIR */
56 + u32 msir_base; /* The base address of MSIR */
57 +};
58 +
59 +struct ls_scfg_msir {
60 + struct ls_scfg_msi *msi_data;
61 + unsigned int index;
62 + unsigned int gic_irq;
63 + unsigned int bit_start;
64 + unsigned int bit_end;
65 + unsigned int srs; /* Shared interrupt register select */
66 + void __iomem *reg;
67 +};
68
69 struct ls_scfg_msi {
70 spinlock_t lock;
71 @@ -32,8 +51,11 @@ struct ls_scfg_msi {
72 struct irq_domain *msi_domain;
73 void __iomem *regs;
74 phys_addr_t msiir_addr;
75 - int irq;
76 - DECLARE_BITMAP(used, MSI_MAX_IRQS);
77 + struct ls_scfg_msi_cfg *cfg;
78 + u32 msir_num;
79 + struct ls_scfg_msir *msir;
80 + u32 irqs_num;
81 + unsigned long *used;
82 };
83
84 static struct irq_chip ls_scfg_msi_irq_chip = {
85 @@ -49,19 +71,56 @@ static struct msi_domain_info ls_scfg_ms
86 .chip = &ls_scfg_msi_irq_chip,
87 };
88
89 +static int msi_affinity_flag = 1;
90 +
91 +static int __init early_parse_ls_scfg_msi(char *p)
92 +{
93 + if (p && strncmp(p, "no-affinity", 11) == 0)
94 + msi_affinity_flag = 0;
95 + else
96 + msi_affinity_flag = 1;
97 +
98 + return 0;
99 +}
100 +early_param("lsmsi", early_parse_ls_scfg_msi);
101 +
102 static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
103 {
104 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
105
106 msg->address_hi = upper_32_bits(msi_data->msiir_addr);
107 msg->address_lo = lower_32_bits(msi_data->msiir_addr);
108 - msg->data = data->hwirq << MSI_IBS_SHIFT;
109 + msg->data = data->hwirq;
110 +
111 + if (msi_affinity_flag)
112 + msg->data |= cpumask_first(data->common->affinity);
113 }
114
115 static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
116 const struct cpumask *mask, bool force)
117 {
118 - return -EINVAL;
119 + struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
120 + u32 cpu;
121 +
122 + if (!msi_affinity_flag)
123 + return -EINVAL;
124 +
125 + if (!force)
126 + cpu = cpumask_any_and(mask, cpu_online_mask);
127 + else
128 + cpu = cpumask_first(mask);
129 +
130 + if (cpu >= msi_data->msir_num)
131 + return -EINVAL;
132 +
133 + if (msi_data->msir[cpu].gic_irq <= 0) {
134 + pr_warn("cannot bind the irq to cpu%d\n", cpu);
135 + return -EINVAL;
136 + }
137 +
138 + cpumask_copy(irq_data->common->affinity, mask);
139 +
140 + return IRQ_SET_MASK_OK;
141 }
142
143 static struct irq_chip ls_scfg_msi_parent_chip = {
144 @@ -81,8 +140,8 @@ static int ls_scfg_msi_domain_irq_alloc(
145 WARN_ON(nr_irqs != 1);
146
147 spin_lock(&msi_data->lock);
148 - pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
149 - if (pos < MSI_MAX_IRQS)
150 + pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
151 + if (pos < msi_data->irqs_num)
152 __set_bit(pos, msi_data->used);
153 else
154 err = -ENOSPC;
155 @@ -106,7 +165,7 @@ static void ls_scfg_msi_domain_irq_free(
156 int pos;
157
158 pos = d->hwirq;
159 - if (pos < 0 || pos >= MSI_MAX_IRQS) {
160 + if (pos < 0 || pos >= msi_data->irqs_num) {
161 pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
162 return;
163 }
164 @@ -123,15 +182,22 @@ static const struct irq_domain_ops ls_sc
165
166 static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
167 {
168 - struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
169 + struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
170 + struct ls_scfg_msi *msi_data = msir->msi_data;
171 unsigned long val;
172 - int pos, virq;
173 + int pos, size, virq, hwirq;
174
175 chained_irq_enter(irq_desc_get_chip(desc), desc);
176
177 - val = ioread32be(msi_data->regs + MSIR);
178 - for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
179 - virq = irq_find_mapping(msi_data->parent, (31 - pos));
180 + val = ioread32be(msir->reg);
181 +
182 + pos = msir->bit_start;
183 + size = msir->bit_end + 1;
184 +
185 + for_each_set_bit_from(pos, &val, size) {
186 + hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
187 + msir->srs;
188 + virq = irq_find_mapping(msi_data->parent, hwirq);
189 if (virq)
190 generic_handle_irq(virq);
191 }
192 @@ -143,7 +209,7 @@ static int ls_scfg_msi_domains_init(stru
193 {
194 /* Initialize MSI domain parent */
195 msi_data->parent = irq_domain_add_linear(NULL,
196 - MSI_MAX_IRQS,
197 + msi_data->irqs_num,
198 &ls_scfg_msi_domain_ops,
199 msi_data);
200 if (!msi_data->parent) {
201 @@ -164,16 +230,117 @@ static int ls_scfg_msi_domains_init(stru
202 return 0;
203 }
204
205 +static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
206 +{
207 + struct ls_scfg_msir *msir;
208 + int virq, i, hwirq;
209 +
210 + virq = platform_get_irq(msi_data->pdev, index);
211 + if (virq <= 0)
212 + return -ENODEV;
213 +
214 + msir = &msi_data->msir[index];
215 + msir->index = index;
216 + msir->msi_data = msi_data;
217 + msir->gic_irq = virq;
218 + msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
219 +
220 + if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
221 + msir->bit_start = 32 - ((msir->index + 1) *
222 + MSI_LS1043V1_1_IRQS_PER_MSIR);
223 + msir->bit_end = msir->bit_start +
224 + MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
225 + } else {
226 + msir->bit_start = 0;
227 + msir->bit_end = msi_data->cfg->msir_irqs - 1;
228 + }
229 +
230 + irq_set_chained_handler_and_data(msir->gic_irq,
231 + ls_scfg_msi_irq_handler,
232 + msir);
233 +
234 + if (msi_affinity_flag) {
235 + /* Associate MSIR interrupt to the cpu */
236 + irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
237 + msir->srs = 0; /* This value is determined by the CPU */
238 + } else
239 + msir->srs = index;
240 +
241 + /* Release the hwirqs corresponding to this MSIR */
242 + if (!msi_affinity_flag || msir->index == 0) {
243 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
244 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
245 + bitmap_clear(msi_data->used, hwirq, 1);
246 + }
247 + }
248 +
249 + return 0;
250 +}
251 +
252 +static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
253 +{
254 + struct ls_scfg_msi *msi_data = msir->msi_data;
255 + int i, hwirq;
256 +
257 + if (msir->gic_irq > 0)
258 + irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
259 +
260 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
261 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
262 + bitmap_set(msi_data->used, hwirq, 1);
263 + }
264 +
265 + return 0;
266 +}
267 +
268 +static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
269 + .ibs_shift = 3,
270 + .msir_irqs = MSI_IRQS_PER_MSIR,
271 + .msir_base = MSI_MSIR_OFFSET,
272 +};
273 +
274 +static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
275 + .ibs_shift = 2,
276 + .msir_irqs = MSI_IRQS_PER_MSIR,
277 + .msir_base = MSI_MSIR_OFFSET,
278 +};
279 +
280 +static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
281 + .ibs_shift = 2,
282 + .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
283 + .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
284 +};
285 +
286 +static const struct of_device_id ls_scfg_msi_id[] = {
287 + /* The following two misspelled compatibles are obsolete */
288 + { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
289 + { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
290 +
291 + { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
292 + { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
293 + { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
294 + { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
295 + {},
296 +};
297 +MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
298 +
299 static int ls_scfg_msi_probe(struct platform_device *pdev)
300 {
301 + const struct of_device_id *match;
302 struct ls_scfg_msi *msi_data;
303 struct resource *res;
304 - int ret;
305 + int i, ret;
306 +
307 + match = of_match_device(ls_scfg_msi_id, &pdev->dev);
308 + if (!match)
309 + return -ENODEV;
310
311 msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
312 if (!msi_data)
313 return -ENOMEM;
314
315 + msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
316 +
317 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
318 msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
319 if (IS_ERR(msi_data->regs)) {
320 @@ -182,23 +349,48 @@ static int ls_scfg_msi_probe(struct plat
321 }
322 msi_data->msiir_addr = res->start;
323
324 - msi_data->irq = platform_get_irq(pdev, 0);
325 - if (msi_data->irq <= 0) {
326 - dev_err(&pdev->dev, "failed to get MSI irq\n");
327 - return -ENODEV;
328 - }
329 -
330 msi_data->pdev = pdev;
331 spin_lock_init(&msi_data->lock);
332
333 + msi_data->irqs_num = MSI_IRQS_PER_MSIR *
334 + (1 << msi_data->cfg->ibs_shift);
335 + msi_data->used = devm_kcalloc(&pdev->dev,
336 + BITS_TO_LONGS(msi_data->irqs_num),
337 + sizeof(*msi_data->used),
338 + GFP_KERNEL);
339 + if (!msi_data->used)
340 + return -ENOMEM;
341 + /*
342 + * Reserve all the hwirqs
343 + * The available hwirqs will be released in ls1_msi_setup_hwirq()
344 + */
345 + bitmap_set(msi_data->used, 0, msi_data->irqs_num);
346 +
347 + msi_data->msir_num = of_irq_count(pdev->dev.of_node);
348 +
349 + if (msi_affinity_flag) {
350 + u32 cpu_num;
351 +
352 + cpu_num = num_possible_cpus();
353 + if (msi_data->msir_num >= cpu_num)
354 + msi_data->msir_num = cpu_num;
355 + else
356 + msi_affinity_flag = 0;
357 + }
358 +
359 + msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
360 + sizeof(*msi_data->msir),
361 + GFP_KERNEL);
362 + if (!msi_data->msir)
363 + return -ENOMEM;
364 +
365 + for (i = 0; i < msi_data->msir_num; i++)
366 + ls_scfg_msi_setup_hwirq(msi_data, i);
367 +
368 ret = ls_scfg_msi_domains_init(msi_data);
369 if (ret)
370 return ret;
371
372 - irq_set_chained_handler_and_data(msi_data->irq,
373 - ls_scfg_msi_irq_handler,
374 - msi_data);
375 -
376 platform_set_drvdata(pdev, msi_data);
377
378 return 0;
379 @@ -207,8 +399,10 @@ static int ls_scfg_msi_probe(struct plat
380 static int ls_scfg_msi_remove(struct platform_device *pdev)
381 {
382 struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
383 + int i;
384
385 - irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
386 + for (i = 0; i < msi_data->msir_num; i++)
387 + ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
388
389 irq_domain_remove(msi_data->msi_domain);
390 irq_domain_remove(msi_data->parent);
391 @@ -218,12 +412,6 @@ static int ls_scfg_msi_remove(struct pla
392 return 0;
393 }
394
395 -static const struct of_device_id ls_scfg_msi_id[] = {
396 - { .compatible = "fsl,1s1021a-msi", },
397 - { .compatible = "fsl,1s1043a-msi", },
398 - {},
399 -};
400 -
401 static struct platform_driver ls_scfg_msi_driver = {
402 .driver = {
403 .name = "ls-scfg-msi",
404 --- a/drivers/pci/host/Makefile
405 +++ b/drivers/pci/host/Makefile
406 @@ -17,7 +17,7 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx
407 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
408 obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
409 obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
410 -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
411 +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o pci-layerscape-ep-debugfs.o
412 obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
413 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
414 obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
415 --- /dev/null
416 +++ b/drivers/pci/host/pci-layerscape-ep-debugfs.c
417 @@ -0,0 +1,758 @@
418 +/*
419 + * PCIe Endpoint driver for Freescale Layerscape SoCs
420 + *
421 + * Copyright (C) 2015 Freescale Semiconductor.
422 + *
423 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
424 + *
425 + * This program is free software; you can redistribute it and/or modify
426 + * it under the terms of the GNU General Public License version 2 as
427 + * published by the Free Software Foundation.
428 + */
429 +
430 +#include <linux/kernel.h>
431 +#include <linux/module.h>
432 +#include <linux/debugfs.h>
433 +#include <linux/time.h>
434 +#include <linux/uaccess.h>
435 +#include <linux/kthread.h>
436 +#include <linux/slab.h>
437 +#include <linux/dmaengine.h>
438 +#include <linux/dma-mapping.h>
439 +#include <linux/freezer.h>
440 +
441 +#include <linux/completion.h>
442 +
443 +#include "pci-layerscape-ep.h"
444 +
445 +#define PCIE_ATU_INDEX3 (0x3 << 0)
446 +#define PCIE_ATU_INDEX2 (0x2 << 0)
447 +#define PCIE_ATU_INDEX1 (0x1 << 0)
448 +#define PCIE_ATU_INDEX0 (0x0 << 0)
449 +
450 +#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
451 +#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
452 +#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
453 +#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
454 +#define PCIE_MSI_OB_SIZE (4 * 1024) /* 4K */
455 +
456 +#define PCIE_MSI_MSG_ADDR_OFF 0x54
457 +#define PCIE_MSI_MSG_DATA_OFF 0x5c
458 +
459 +enum test_type {
460 + TEST_TYPE_DMA,
461 + TEST_TYPE_MEMCPY
462 +};
463 +
464 +enum test_dirt {
465 + TEST_DIRT_READ,
466 + TEST_DIRT_WRITE
467 +};
468 +
469 +enum test_status {
470 + TEST_IDLE,
471 + TEST_BUSY
472 +};
473 +
474 +struct ls_ep_test {
475 + struct ls_ep_dev *ep;
476 + void __iomem *cfg;
477 + void __iomem *buf;
478 + void __iomem *out;
479 + void __iomem *msi;
480 + dma_addr_t cfg_addr;
481 + dma_addr_t buf_addr;
482 + dma_addr_t out_addr;
483 + dma_addr_t bus_addr;
484 + dma_addr_t msi_addr;
485 + u64 msi_msg_addr;
486 + u16 msi_msg_data;
487 + struct task_struct *thread;
488 + spinlock_t lock;
489 + struct completion done;
490 + u32 len;
491 + int loop;
492 + char data;
493 + enum test_dirt dirt;
494 + enum test_type type;
495 + enum test_status status;
496 + u64 result; /* Mbps */
497 + char cmd[256];
498 +};
499 +
500 +static int ls_pcie_ep_trigger_msi(struct ls_ep_test *test)
501 +{
502 + if (!test->msi)
503 + return -EINVAL;
504 +
505 + iowrite32(test->msi_msg_data, test->msi);
506 +
507 + return 0;
508 +}
509 +
510 +static int ls_pcie_ep_test_try_run(struct ls_ep_test *test)
511 +{
512 + int ret;
513 +
514 + spin_lock(&test->lock);
515 + if (test->status == TEST_IDLE) {
516 + test->status = TEST_BUSY;
517 + ret = 0;
518 + } else
519 + ret = -EBUSY;
520 + spin_unlock(&test->lock);
521 +
522 + return ret;
523 +}
524 +
525 +static void ls_pcie_ep_test_done(struct ls_ep_test *test)
526 +{
527 + spin_lock(&test->lock);
528 + test->status = TEST_IDLE;
529 + spin_unlock(&test->lock);
530 +}
531 +
532 +static void ls_pcie_ep_test_dma_cb(void *arg)
533 +{
534 + struct ls_ep_test *test = arg;
535 +
536 + complete(&test->done);
537 +}
538 +
539 +static int ls_pcie_ep_test_dma(struct ls_ep_test *test)
540 +{
541 + dma_cap_mask_t mask;
542 + struct dma_chan *chan;
543 + struct dma_device *dma_dev;
544 + dma_addr_t src, dst;
545 + enum dma_data_direction direction;
546 + enum dma_ctrl_flags dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
547 + struct timespec start, end, period;
548 + int i = 0;
549 +
550 + dma_cap_zero(mask);
551 + dma_cap_set(DMA_MEMCPY, mask);
552 +
553 + chan = dma_request_channel(mask, NULL, test);
554 + if (!chan) {
555 + pr_err("failed to request dma channel\n");
556 + return -EINVAL;
557 + }
558 +
559 + memset(test->buf, test->data, test->len);
560 +
561 + if (test->dirt == TEST_DIRT_WRITE) {
562 + src = test->buf_addr;
563 + dst = test->out_addr;
564 + direction = DMA_TO_DEVICE;
565 + } else {
566 + src = test->out_addr;
567 + dst = test->buf_addr;
568 + direction = DMA_FROM_DEVICE;
569 + }
570 +
571 + dma_dev = chan->device;
572 + dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
573 +
574 + dma_sync_single_for_device(&test->ep->dev, test->buf_addr,
575 + test->len, direction);
576 +
577 + set_freezable();
578 +
579 + getrawmonotonic(&start);
580 + while (!kthread_should_stop() && (i < test->loop)) {
581 + struct dma_async_tx_descriptor *dma_desc;
582 + dma_cookie_t dma_cookie = {0};
583 + unsigned long tmo;
584 + int status;
585 +
586 + init_completion(&test->done);
587 +
588 + dma_desc = dma_dev->device_prep_dma_memcpy(chan,
589 + dst, src,
590 + test->len,
591 + dma_flags);
592 + if (!dma_desc) {
593 + pr_err("DMA desc constr failed...\n");
594 + goto _err;
595 + }
596 +
597 + dma_desc->callback = ls_pcie_ep_test_dma_cb;
598 + dma_desc->callback_param = test;
599 + dma_cookie = dmaengine_submit(dma_desc);
600 +
601 + if (dma_submit_error(dma_cookie)) {
602 + pr_err("DMA submit error....\n");
603 + goto _err;
604 + }
605 +
606 + /* Trigger the transaction */
607 + dma_async_issue_pending(chan);
608 +
609 + tmo = wait_for_completion_timeout(&test->done,
610 + msecs_to_jiffies(5 * test->len));
611 + if (tmo == 0) {
612 + pr_err("Self-test copy timed out, disabling\n");
613 + goto _err;
614 + }
615 +
616 + status = dma_async_is_tx_complete(chan, dma_cookie,
617 + NULL, NULL);
618 + if (status != DMA_COMPLETE) {
619 + pr_err("got completion callback, but status is %s\n",
620 + status == DMA_ERROR ? "error" : "in progress");
621 + goto _err;
622 + }
623 +
624 + i++;
625 + }
626 +
627 + getrawmonotonic(&end);
628 + period = timespec_sub(end, start);
629 + test->result = test->len * 8ULL * i * 1000;
630 + do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
631 + dma_release_channel(chan);
632 +
633 + return 0;
634 +
635 +_err:
636 + dma_release_channel(chan);
637 + test->result = 0;
638 + return -EINVAL;
639 +}
640 +
641 +static int ls_pcie_ep_test_cpy(struct ls_ep_test *test)
642 +{
643 + void *dst, *src;
644 + struct timespec start, end, period;
645 + int i = 0;
646 +
647 + memset(test->buf, test->data, test->len);
648 +
649 + if (test->dirt == TEST_DIRT_WRITE) {
650 + dst = test->out;
651 + src = test->buf;
652 + } else {
653 + dst = test->buf;
654 + src = test->out;
655 + }
656 +
657 + getrawmonotonic(&start);
658 + while (!kthread_should_stop() && i < test->loop) {
659 + memcpy(dst, src, test->len);
660 + i++;
661 + }
662 + getrawmonotonic(&end);
663 +
664 + period = timespec_sub(end, start);
665 + test->result = test->len * 8ULL * i * 1000;
666 + do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
667 +
668 + return 0;
669 +}
670 +
671 +int ls_pcie_ep_test_thread(void *arg)
672 +{
673 + int ret;
674 +
675 + struct ls_ep_test *test = arg;
676 +
677 + if (test->type == TEST_TYPE_DMA)
678 + ret = ls_pcie_ep_test_dma(test);
679 + else
680 + ret = ls_pcie_ep_test_cpy(test);
681 +
682 + if (ret) {
683 + pr_err("\n%s \ttest failed\n",
684 + test->cmd);
685 + test->result = 0;
686 + } else
687 + pr_err("\n%s \tthroughput:%lluMbps\n",
688 + test->cmd, test->result);
689 +
690 + ls_pcie_ep_test_done(test);
691 +
692 + ls_pcie_ep_trigger_msi(test);
693 +
694 + do_exit(0);
695 +}
696 +
697 +static int ls_pcie_ep_free_test(struct ls_ep_dev *ep)
698 +{
699 + struct ls_ep_test *test = ep->driver_data;
700 +
701 + if (!test)
702 + return 0;
703 +
704 + if (test->status == TEST_BUSY) {
705 + kthread_stop(test->thread);
706 + dev_info(&ep->dev,
707 + "test is running please wait and run again\n");
708 + return -EBUSY;
709 + }
710 +
711 + if (test->buf)
712 + free_pages((unsigned long)test->buf,
713 + get_order(PCIE_BAR4_SIZE));
714 +
715 + if (test->cfg)
716 + free_pages((unsigned long)test->cfg,
717 + get_order(PCIE_BAR2_SIZE));
718 +
719 + if (test->out)
720 + iounmap(test->out);
721 +
722 + kfree(test);
723 + ep->driver_data = NULL;
724 +
725 + return 0;
726 +}
727 +
728 +static int ls_pcie_ep_init_test(struct ls_ep_dev *ep, u64 bus_addr)
729 +{
730 + struct ls_pcie *pcie = ep->pcie;
731 + struct ls_ep_test *test = ep->driver_data;
732 + int err;
733 +
734 + if (test) {
735 + dev_info(&ep->dev,
736 + "Please use 'free' to remove the exiting test\n");
737 + return -EBUSY;
738 + }
739 +
740 + test = kzalloc(sizeof(*test), GFP_KERNEL);
741 + if (!test)
742 + return -ENOMEM;
743 + ep->driver_data = test;
744 + test->ep = ep;
745 + spin_lock_init(&test->lock);
746 + test->status = TEST_IDLE;
747 +
748 + test->buf = dma_alloc_coherent(pcie->dev, get_order(PCIE_BAR4_SIZE),
749 + &test->buf_addr,
750 + GFP_KERNEL);
751 + if (!test->buf) {
752 + dev_info(&ep->dev, "failed to get mem for bar4\n");
753 + err = -ENOMEM;
754 + goto _err;
755 + }
756 +
757 + test->cfg = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
758 + get_order(PCIE_BAR2_SIZE));
759 + if (!test->cfg) {
760 + dev_info(&ep->dev, "failed to get mem for bar4\n");
761 + err = -ENOMEM;
762 + goto _err;
763 + }
764 + test->cfg_addr = virt_to_phys(test->cfg);
765 +
766 + test->out_addr = pcie->out_base;
767 + test->out = ioremap(test->out_addr, PCIE_BAR4_SIZE);
768 + if (!test->out) {
769 + dev_info(&ep->dev, "failed to map out\n");
770 + err = -ENOMEM;
771 + goto _err;
772 + }
773 +
774 + test->bus_addr = bus_addr;
775 +
776 + test->msi_addr = test->out_addr + PCIE_BAR4_SIZE;
777 + test->msi = ioremap(test->msi_addr, PCIE_MSI_OB_SIZE);
778 + if (!test->msi)
779 + dev_info(&ep->dev, "failed to map MSI outbound region\n");
780 +
781 + test->msi_msg_addr = ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF) |
782 + (((u64)ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF + 4)) << 32);
783 + test->msi_msg_data = ioread16(pcie->dbi + PCIE_MSI_MSG_DATA_OFF);
784 +
785 + ls_pcie_ep_dev_cfg_enable(ep);
786 +
787 + /* outbound iATU for memory */
788 + ls_pcie_iatu_outbound_set(pcie, 0, PCIE_ATU_TYPE_MEM,
789 + test->out_addr, bus_addr, PCIE_BAR4_SIZE);
790 + /* outbound iATU for MSI */
791 + ls_pcie_iatu_outbound_set(pcie, 1, PCIE_ATU_TYPE_MEM,
792 + test->msi_addr, test->msi_msg_addr,
793 + PCIE_MSI_OB_SIZE);
794 +
795 + /* ATU 0 : INBOUND : map BAR0 */
796 + ls_pcie_iatu_inbound_set(pcie, 0, 0, test->cfg_addr);
797 + /* ATU 2 : INBOUND : map BAR2 */
798 + ls_pcie_iatu_inbound_set(pcie, 2, 2, test->cfg_addr);
799 + /* ATU 3 : INBOUND : map BAR4 */
800 + ls_pcie_iatu_inbound_set(pcie, 3, 4, test->buf_addr);
801 +
802 + return 0;
803 +
804 +_err:
805 + ls_pcie_ep_free_test(ep);
806 + return err;
807 +}
808 +
809 +static int ls_pcie_ep_start_test(struct ls_ep_dev *ep, char *cmd)
810 +{
811 + struct ls_ep_test *test = ep->driver_data;
812 + enum test_type type;
813 + enum test_dirt dirt;
814 + u32 cnt, len, loop;
815 + unsigned int data;
816 + char dirt_str[2];
817 + int ret;
818 +
819 + if (strncmp(cmd, "dma", 3) == 0)
820 + type = TEST_TYPE_DMA;
821 + else
822 + type = TEST_TYPE_MEMCPY;
823 +
824 + cnt = sscanf(&cmd[4], "%1s %u %u %x", dirt_str, &len, &loop, &data);
825 + if (cnt != 4) {
826 + dev_info(&ep->dev, "format error %s", cmd);
827 + dev_info(&ep->dev, "dma/cpy <r/w> <packet_size> <loop> <data>\n");
828 + return -EINVAL;
829 + }
830 +
831 + if (strncmp(dirt_str, "r", 1) == 0)
832 + dirt = TEST_DIRT_READ;
833 + else
834 + dirt = TEST_DIRT_WRITE;
835 +
836 + if (len > PCIE_BAR4_SIZE) {
837 + dev_err(&ep->dev, "max len is %d", PCIE_BAR4_SIZE);
838 + return -EINVAL;
839 + }
840 +
841 + if (!test) {
842 + dev_err(&ep->dev, "Please first run init command\n");
843 + return -EINVAL;
844 + }
845 +
846 + if (ls_pcie_ep_test_try_run(test)) {
847 + dev_err(&ep->dev, "There is already a test running\n");
848 + return -EINVAL;
849 + }
850 +
851 + test->len = len;
852 + test->loop = loop;
853 + test->type = type;
854 + test->data = (char)data;
855 + test->dirt = dirt;
856 + strcpy(test->cmd, cmd);
857 + test->thread = kthread_run(ls_pcie_ep_test_thread, test,
858 + "pcie ep test");
859 + if (IS_ERR(test->thread)) {
860 + dev_err(&ep->dev, "fork failed for pcie ep test\n");
861 + ls_pcie_ep_test_done(test);
862 + ret = PTR_ERR(test->thread);
863 + }
864 +
865 + return ret;
866 +}
867 +
868 +
869 +/**
870 + * ls_pcie_reg_ops_read - read for regs data
871 + * @filp: the opened file
872 + * @buffer: where to write the data for the user to read
873 + * @count: the size of the user's buffer
874 + * @ppos: file position offset
875 + **/
876 +static ssize_t ls_pcie_ep_dbg_regs_read(struct file *filp, char __user *buffer,
877 + size_t count, loff_t *ppos)
878 +{
879 + struct ls_ep_dev *ep = filp->private_data;
880 + struct ls_pcie *pcie = ep->pcie;
881 + char *buf;
882 + int desc = 0, i, len;
883 +
884 + buf = kmalloc(4 * 1024, GFP_KERNEL);
885 + if (!buf)
886 + return -ENOMEM;
887 +
888 + ls_pcie_ep_dev_cfg_enable(ep);
889 +
890 + desc += sprintf(buf + desc, "%s", "reg info:");
891 + for (i = 0; i < 0x200; i += 4) {
892 + if (i % 16 == 0)
893 + desc += sprintf(buf + desc, "\n%08x:", i);
894 + desc += sprintf(buf + desc, " %08x", readl(pcie->dbi + i));
895 + }
896 +
897 + desc += sprintf(buf + desc, "\n%s", "outbound iATU info:\n");
898 + for (i = 0; i < 6; i++) {
899 + writel(PCIE_ATU_REGION_OUTBOUND | i,
900 + pcie->dbi + PCIE_ATU_VIEWPORT);
901 + desc += sprintf(buf + desc, "iATU%d", i);
902 + desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
903 + readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
904 + desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
905 + readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
906 + desc += sprintf(buf + desc, "\tLOWER BUS 0x%08x\n",
907 + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
908 + desc += sprintf(buf + desc, "\tUPPER BUS 0x%08x\n",
909 + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
910 + desc += sprintf(buf + desc, "\tLIMIT 0x%08x\n",
911 + readl(pcie->dbi + PCIE_ATU_LIMIT));
912 + desc += sprintf(buf + desc, "\tCR1 0x%08x\n",
913 + readl(pcie->dbi + PCIE_ATU_CR1));
914 + desc += sprintf(buf + desc, "\tCR2 0x%08x\n",
915 + readl(pcie->dbi + PCIE_ATU_CR2));
916 + }
917 +
918 + desc += sprintf(buf + desc, "\n%s", "inbound iATU info:\n");
919 + for (i = 0; i < 6; i++) {
920 + writel(PCIE_ATU_REGION_INBOUND | i,
921 + pcie->dbi + PCIE_ATU_VIEWPORT);
922 + desc += sprintf(buf + desc, "iATU%d", i);
923 + desc += sprintf(buf + desc, "\tLOWER BUS 0x%08x\n",
924 + readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
925 + desc += sprintf(buf + desc, "\tUPPER BUSs 0x%08x\n",
926 + readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
927 + desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
928 + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
929 + desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
930 + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
931 + desc += sprintf(buf + desc, "\tLIMIT 0x%08x\n",
932 + readl(pcie->dbi + PCIE_ATU_LIMIT));
933 + desc += sprintf(buf + desc, "\tCR1 0x%08x\n",
934 + readl(pcie->dbi + PCIE_ATU_CR1));
935 + desc += sprintf(buf + desc, "\tCR2 0x%08x\n",
936 + readl(pcie->dbi + PCIE_ATU_CR2));
937 + }
938 +
939 + len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
940 + kfree(buf);
941 +
942 + return len;
943 +}
944 +
945 +/**
946 + * ls_pcie_ep_dbg_regs_write - write into regs datum
947 + * @filp: the opened file
948 + * @buffer: where to find the user's data
949 + * @count: the length of the user's data
950 + * @ppos: file position offset
951 + **/
952 +static ssize_t ls_pcie_ep_dbg_regs_write(struct file *filp,
953 + const char __user *buffer,
954 + size_t count, loff_t *ppos)
955 +{
956 + struct ls_ep_dev *ep = filp->private_data;
957 + struct ls_pcie *pcie = ep->pcie;
958 + char buf[256];
959 +
960 + if (count >= sizeof(buf))
961 + return -ENOSPC;
962 +
963 + memset(buf, 0, sizeof(buf));
964 +
965 + if (copy_from_user(buf, buffer, count))
966 + return -EFAULT;
967 +
968 + ls_pcie_ep_dev_cfg_enable(ep);
969 +
970 + if (strncmp(buf, "reg", 3) == 0) {
971 + u32 reg, value;
972 + int cnt;
973 +
974 + cnt = sscanf(&buf[3], "%x %x", &reg, &value);
975 + if (cnt == 2) {
976 + writel(value, pcie->dbi + reg);
977 + value = readl(pcie->dbi + reg);
978 + dev_info(&ep->dev, "reg 0x%08x: 0x%08x\n",
979 + reg, value);
980 + } else {
981 + dev_info(&ep->dev, "reg <reg> <value>\n");
982 + }
983 + } else if (strncmp(buf, "atu", 3) == 0) {
984 + /* to do */
985 + dev_info(&ep->dev, " Not support atu command\n");
986 + } else {
987 + dev_info(&ep->dev, "Unknown command %s\n", buf);
988 + dev_info(&ep->dev, "Available commands:\n");
989 + dev_info(&ep->dev, " reg <reg> <value>\n");
990 + }
991 +
992 + return count;
993 +}
994 +
995 +static const struct file_operations ls_pcie_ep_dbg_regs_fops = {
996 + .owner = THIS_MODULE,
997 + .open = simple_open,
998 + .read = ls_pcie_ep_dbg_regs_read,
999 + .write = ls_pcie_ep_dbg_regs_write,
1000 +};
1001 +
1002 +static ssize_t ls_pcie_ep_dbg_test_read(struct file *filp,
1003 + char __user *buffer,
1004 + size_t count, loff_t *ppos)
1005 +{
1006 + struct ls_ep_dev *ep = filp->private_data;
1007 + struct ls_ep_test *test = ep->driver_data;
1008 + char buf[512];
1009 + int desc = 0, len;
1010 +
1011 + if (!test) {
1012 + dev_info(&ep->dev, " there is NO test\n");
1013 + return 0;
1014 + }
1015 +
1016 + if (test->status != TEST_IDLE) {
1017 + dev_info(&ep->dev, "test %s is running\n", test->cmd);
1018 + return 0;
1019 + }
1020 +
1021 + desc = sprintf(buf, "MSI ADDR:0x%llx MSI DATA:0x%x\n",
1022 + test->msi_msg_addr, test->msi_msg_data);
1023 +
1024 + desc += sprintf(buf + desc, "%s throughput:%lluMbps\n",
1025 + test->cmd, test->result);
1026 +
1027 + len = simple_read_from_buffer(buffer, count, ppos,
1028 + buf, desc);
1029 +
1030 + return len;
1031 +}
1032 +
1033 +static ssize_t ls_pcie_ep_dbg_test_write(struct file *filp,
1034 + const char __user *buffer,
1035 + size_t count, loff_t *ppos)
1036 +{
1037 + struct ls_ep_dev *ep = filp->private_data;
1038 + char buf[256];
1039 +
1040 + if (count >= sizeof(buf))
1041 + return -ENOSPC;
1042 +
1043 + memset(buf, 0, sizeof(buf));
1044 +
1045 + if (copy_from_user(buf, buffer, count))
1046 + return -EFAULT;
1047 +
1048 + if (strncmp(buf, "init", 4) == 0) {
1049 + int i = 4;
1050 + u64 bus_addr;
1051 +
1052 + while (buf[i] == ' ')
1053 + i++;
1054 +
1055 + if (kstrtou64(&buf[i], 0, &bus_addr))
1056 + dev_info(&ep->dev, "command: init <bus_addr>\n");
1057 + else {
1058 + if (ls_pcie_ep_init_test(ep, bus_addr))
1059 + dev_info(&ep->dev, "failed to init test\n");
1060 + }
1061 + } else if (strncmp(buf, "free", 4) == 0)
1062 + ls_pcie_ep_free_test(ep);
1063 + else if (strncmp(buf, "dma", 3) == 0 ||
1064 + strncmp(buf, "cpy", 3) == 0)
1065 + ls_pcie_ep_start_test(ep, buf);
1066 + else {
1067 + dev_info(&ep->dev, "Unknown command: %s\n", buf);
1068 + dev_info(&ep->dev, "Available commands:\n");
1069 + dev_info(&ep->dev, "\tinit <bus_addr>\n");
1070 + dev_info(&ep->dev, "\t<dma/cpy> <r/w> <packet_size> <loop>\n");
1071 + dev_info(&ep->dev, "\tfree\n");
1072 + }
1073 +
1074 + return count;
1075 +}
1076 +
1077 +static const struct file_operations ls_pcie_ep_dbg_test_fops = {
1078 + .owner = THIS_MODULE,
1079 + .open = simple_open,
1080 + .read = ls_pcie_ep_dbg_test_read,
1081 + .write = ls_pcie_ep_dbg_test_write,
1082 +};
1083 +
1084 +static ssize_t ls_pcie_ep_dbg_dump_read(struct file *filp,
1085 + char __user *buffer,
1086 + size_t count, loff_t *ppos)
1087 +{
1088 + struct ls_ep_dev *ep = filp->private_data;
1089 + struct ls_ep_test *test = ep->driver_data;
1090 + char *buf;
1091 + int desc = 0, i, len;
1092 +
1093 + buf = kmalloc(4 * 1024, GFP_KERNEL);
1094 + if (!buf)
1095 + return -ENOMEM;
1096 +
1097 + if (!test) {
1098 + dev_info(&ep->dev, " there is NO test\n");
1099 + kfree(buf);
1100 + return 0;
1101 + }
1102 +
1103 + desc += sprintf(buf + desc, "%s", "dump info:");
1104 + for (i = 0; i < 256; i += 4) {
1105 + if (i % 16 == 0)
1106 + desc += sprintf(buf + desc, "\n%08x:", i);
1107 + desc += sprintf(buf + desc, " %08x", readl(test->buf + i));
1108 + }
1109 +
1110 + desc += sprintf(buf + desc, "\n");
1111 + len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
1112 +
1113 + kfree(buf);
1114 +
1115 + return len;
1116 +}
1117 +
1118 +static const struct file_operations ls_pcie_ep_dbg_dump_fops = {
1119 + .owner = THIS_MODULE,
1120 + .open = simple_open,
1121 + .read = ls_pcie_ep_dbg_dump_read,
1122 +};
1123 +
1124 +static int ls_pcie_ep_dev_dbgfs_init(struct ls_ep_dev *ep)
1125 +{
1126 + struct ls_pcie *pcie = ep->pcie;
1127 + struct dentry *pfile;
1128 +
1129 + ls_pcie_ep_dev_cfg_enable(ep);
1130 +
1131 + ep->dir = debugfs_create_dir(dev_name(&ep->dev), pcie->dir);
1132 + if (!ep->dir)
1133 + return -ENOMEM;
1134 +
1135 + pfile = debugfs_create_file("regs", 0600, ep->dir, ep,
1136 + &ls_pcie_ep_dbg_regs_fops);
1137 + if (!pfile)
1138 + dev_info(&ep->dev, "debugfs regs for failed\n");
1139 +
1140 + pfile = debugfs_create_file("test", 0600, ep->dir, ep,
1141 + &ls_pcie_ep_dbg_test_fops);
1142 + if (!pfile)
1143 + dev_info(&ep->dev, "debugfs test for failed\n");
1144 +
1145 + pfile = debugfs_create_file("dump", 0600, ep->dir, ep,
1146 + &ls_pcie_ep_dbg_dump_fops);
1147 + if (!pfile)
1148 + dev_info(&ep->dev, "debugfs dump for failed\n");
1149 +
1150 + return 0;
1151 +}
1152 +
1153 +int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie)
1154 +{
1155 + struct ls_ep_dev *ep;
1156 +
1157 + pcie->dir = debugfs_create_dir(dev_name(pcie->dev), NULL);
1158 + if (!pcie->dir)
1159 + return -ENOMEM;
1160 +
1161 + list_for_each_entry(ep, &pcie->ep_list, node)
1162 + ls_pcie_ep_dev_dbgfs_init(ep);
1163 +
1164 + return 0;
1165 +}
1166 +
1167 +int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie)
1168 +{
1169 + debugfs_remove_recursive(pcie->dir);
1170 + return 0;
1171 +}
1172 +
1173 +MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
1174 +MODULE_DESCRIPTION("Freescale Layerscape PCIe EP controller driver");
1175 +MODULE_LICENSE("GPL v2");
1176 --- /dev/null
1177 +++ b/drivers/pci/host/pci-layerscape-ep.c
1178 @@ -0,0 +1,309 @@
1179 +/*
1180 + * PCIe Endpoint driver for Freescale Layerscape SoCs
1181 + *
1182 + * Copyright (C) 2015 Freescale Semiconductor.
1183 + *
1184 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
1185 + *
1186 + * This program is free software; you can redistribute it and/or modify
1187 + * it under the terms of the GNU General Public License version 2 as
1188 + * published by the Free Software Foundation.
1189 + */
1190 +
1191 +#include <linux/kernel.h>
1192 +#include <linux/delay.h>
1193 +#include <linux/interrupt.h>
1194 +#include <linux/module.h>
1195 +#include <linux/of_pci.h>
1196 +#include <linux/of_platform.h>
1197 +#include <linux/of_irq.h>
1198 +#include <linux/of_address.h>
1199 +#include <linux/pci.h>
1200 +#include <linux/platform_device.h>
1201 +#include <linux/resource.h>
1202 +#include <linux/debugfs.h>
1203 +#include <linux/time.h>
1204 +#include <linux/uaccess.h>
1205 +
1206 +#include "pci-layerscape-ep.h"
1207 +
1208 +struct ls_ep_dev *
1209 +ls_pci_ep_find(struct ls_pcie *pcie, int dev_id)
1210 +{
1211 + struct ls_ep_dev *ep;
1212 +
1213 + list_for_each_entry(ep, &pcie->ep_list, node) {
1214 + if (ep->dev_id == dev_id)
1215 + return ep;
1216 + }
1217 +
1218 + return NULL;
1219 +}
1220 +
1221 +static void ls_pcie_try_cfg2(struct ls_pcie *pcie, int pf, int vf)
1222 +{
1223 + if (pcie->sriov)
1224 + writel(PCIE_LCTRL0_VAL(pf, vf),
1225 + pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
1226 +}
1227 +
1228 +static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
1229 +{
1230 + u32 header_type = 0;
1231 +
1232 + header_type = readl(pcie->dbi + (PCI_HEADER_TYPE & ~0x3));
1233 + header_type = (header_type >> 16) & 0x7f;
1234 +
1235 + return header_type == PCI_HEADER_TYPE_BRIDGE;
1236 +}
1237 +
1238 +void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
1239 + u64 cpu_addr, u64 pci_addr, u32 size)
1240 +{
1241 + writel(PCIE_ATU_REGION_OUTBOUND | idx,
1242 + pcie->dbi + PCIE_ATU_VIEWPORT);
1243 + writel(lower_32_bits(cpu_addr),
1244 + pcie->dbi + PCIE_ATU_LOWER_BASE);
1245 + writel(upper_32_bits(cpu_addr),
1246 + pcie->dbi + PCIE_ATU_UPPER_BASE);
1247 + writel(lower_32_bits(cpu_addr + size - 1),
1248 + pcie->dbi + PCIE_ATU_LIMIT);
1249 + writel(lower_32_bits(pci_addr),
1250 + pcie->dbi + PCIE_ATU_LOWER_TARGET);
1251 + writel(upper_32_bits(pci_addr),
1252 + pcie->dbi + PCIE_ATU_UPPER_TARGET);
1253 + writel(type, pcie->dbi + PCIE_ATU_CR1);
1254 + writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
1255 +}
1256 +
1257 +/* Use bar match mode and MEM type as default */
1258 +void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
1259 + int bar, u64 phys)
1260 +{
1261 + writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
1262 + writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
1263 + writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
1264 + writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
1265 + writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
1266 + PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
1267 +}
1268 +
1269 +void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep)
1270 +{
1271 + ls_pcie_try_cfg2(ep->pcie, ep->pf_idx, ep->vf_idx);
1272 +}
1273 +
1274 +void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
1275 +{
1276 + if (size < 4 * 1024)
1277 + return;
1278 +
1279 + switch (bar) {
1280 + case 0:
1281 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
1282 + break;
1283 + case 1:
1284 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
1285 + break;
1286 + case 2:
1287 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
1288 + writel(0, bar_base + PCI_BASE_ADDRESS_3);
1289 + break;
1290 + case 4:
1291 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
1292 + writel(0, bar_base + PCI_BASE_ADDRESS_5);
1293 + break;
1294 + default:
1295 + break;
1296 + }
1297 +}
1298 +
1299 +void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size)
1300 +{
1301 + struct ls_pcie *pcie = ep->pcie;
1302 + void *bar_base;
1303 +
1304 + if (size < 4 * 1024)
1305 + return;
1306 +
1307 + if (pcie->sriov)
1308 + bar_base = pcie->dbi;
1309 + else
1310 + bar_base = pcie->dbi + PCIE_NO_SRIOV_BAR_BASE;
1311 +
1312 + ls_pcie_ep_dev_cfg_enable(ep);
1313 + ls_pcie_ep_setup_bar(bar_base, bar, size);
1314 +}
1315 +
1316 +static int ls_pcie_ep_dev_init(struct ls_pcie *pcie, int pf_idx, int vf_idx)
1317 +{
1318 + struct ls_ep_dev *ep;
1319 +
1320 + ep = devm_kzalloc(pcie->dev, sizeof(*ep), GFP_KERNEL);
1321 + if (!ep)
1322 + return -ENOMEM;
1323 +
1324 + ep->pcie = pcie;
1325 + ep->pf_idx = pf_idx;
1326 + ep->vf_idx = vf_idx;
1327 + if (vf_idx)
1328 + ep->dev_id = pf_idx + 4 + 4 * (vf_idx - 1);
1329 + else
1330 + ep->dev_id = pf_idx;
1331 +
1332 + if (ep->vf_idx)
1333 + dev_set_name(&ep->dev, "pf%d-vf%d",
1334 + ep->pf_idx,
1335 + ep->vf_idx);
1336 + else
1337 + dev_set_name(&ep->dev, "pf%d",
1338 + ep->pf_idx);
1339 +
1340 + list_add_tail(&ep->node, &pcie->ep_list);
1341 +
1342 + return 0;
1343 +}
1344 +
1345 +static int ls_pcie_ep_init(struct ls_pcie *pcie)
1346 +{
1347 + u32 sriov_header;
1348 + int pf, vf, i, j;
1349 +
1350 + sriov_header = readl(pcie->dbi + PCIE_SRIOV_POS);
1351 +
1352 + if (PCI_EXT_CAP_ID(sriov_header) == PCI_EXT_CAP_ID_SRIOV) {
1353 + pcie->sriov = PCIE_SRIOV_POS;
1354 + pf = PCIE_PF_NUM;
1355 + vf = PCIE_VF_NUM;
1356 + } else {
1357 + pcie->sriov = 0;
1358 + pf = 1;
1359 + vf = 0;
1360 + }
1361 +
1362 + for (i = 0; i < pf; i++) {
1363 + for (j = 0; j <= vf; j++)
1364 + ls_pcie_ep_dev_init(pcie, i, j);
1365 + }
1366 +
1367 + return 0;
1368 +}
1369 +
1370 +static struct ls_pcie_ep_drvdata ls1043_drvdata = {
1371 + .lut_offset = 0x10000,
1372 + .ltssm_shift = 24,
1373 + .lut_dbg = 0x7fc,
1374 +};
1375 +
1376 +static struct ls_pcie_ep_drvdata ls1046_drvdata = {
1377 + .lut_offset = 0x80000,
1378 + .ltssm_shift = 24,
1379 + .lut_dbg = 0x407fc,
1380 +};
1381 +
1382 +static struct ls_pcie_ep_drvdata ls2080_drvdata = {
1383 + .lut_offset = 0x80000,
1384 + .ltssm_shift = 0,
1385 + .lut_dbg = 0x7fc,
1386 +};
1387 +
1388 +static const struct of_device_id ls_pcie_ep_of_match[] = {
1389 + { .compatible = "fsl,ls1021a-pcie", },
1390 + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1391 + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1392 + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
1393 + { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
1394 + { },
1395 +};
1396 +MODULE_DEVICE_TABLE(of, ls_pcie_ep_of_match);
1397 +
1398 +static int ls_pcie_ep_probe(struct platform_device *pdev)
1399 +{
1400 + struct ls_pcie *pcie;
1401 + struct resource *dbi_base, *cfg_res;
1402 + const struct of_device_id *match;
1403 + int ret;
1404 +
1405 + match = of_match_device(ls_pcie_ep_of_match, &pdev->dev);
1406 + if (!match)
1407 + return -ENODEV;
1408 +
1409 + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1410 + if (!pcie)
1411 + return -ENOMEM;
1412 +
1413 + pcie->dev = &pdev->dev;
1414 + INIT_LIST_HEAD(&pcie->ep_list);
1415 +
1416 + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1417 + pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
1418 + if (IS_ERR(pcie->dbi)) {
1419 + dev_err(&pdev->dev, "missing *regs* space\n");
1420 + return PTR_ERR(pcie->dbi);
1421 + }
1422 +
1423 + pcie->drvdata = match->data;
1424 + pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
1425 +
1426 + if (ls_pcie_is_bridge(pcie))
1427 + return -ENODEV;
1428 +
1429 + dev_info(pcie->dev, "in EP mode\n");
1430 +
1431 + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
1432 + if (cfg_res)
1433 + pcie->out_base = cfg_res->start;
1434 + else {
1435 + dev_err(&pdev->dev, "missing *config* space\n");
1436 + return -ENODEV;
1437 + }
1438 +
1439 + ret = ls_pcie_ep_init(pcie);
1440 + if (ret)
1441 + return ret;
1442 +
1443 + ls_pcie_ep_dbgfs_init(pcie);
1444 +
1445 + platform_set_drvdata(pdev, pcie);
1446 +
1447 + return 0;
1448 +}
1449 +
1450 +static int ls_pcie_ep_dev_remove(struct ls_ep_dev *ep)
1451 +{
1452 + list_del(&ep->node);
1453 +
1454 + return 0;
1455 +}
1456 +
1457 +static int ls_pcie_ep_remove(struct platform_device *pdev)
1458 +{
1459 + struct ls_pcie *pcie = platform_get_drvdata(pdev);
1460 + struct ls_ep_dev *ep, *tmp;
1461 +
1462 + if (!pcie)
1463 + return 0;
1464 +
1465 + ls_pcie_ep_dbgfs_remove(pcie);
1466 +
1467 + list_for_each_entry_safe(ep, tmp, &pcie->ep_list, node)
1468 + ls_pcie_ep_dev_remove(ep);
1469 +
1470 + return 0;
1471 +}
1472 +
1473 +static struct platform_driver ls_pcie_ep_driver = {
1474 + .driver = {
1475 + .name = "ls-pcie-ep",
1476 + .owner = THIS_MODULE,
1477 + .of_match_table = ls_pcie_ep_of_match,
1478 + },
1479 + .probe = ls_pcie_ep_probe,
1480 + .remove = ls_pcie_ep_remove,
1481 +};
1482 +
1483 +module_platform_driver(ls_pcie_ep_driver);
1484 +
1485 +MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
1486 +MODULE_DESCRIPTION("Freescale Layerscape PCIe EP driver");
1487 +MODULE_LICENSE("GPL v2");
1488 --- /dev/null
1489 +++ b/drivers/pci/host/pci-layerscape-ep.h
1490 @@ -0,0 +1,115 @@
1491 +/*
1492 + * PCIe Endpoint driver for Freescale Layerscape SoCs
1493 + *
1494 + * Copyright (C) 2015 Freescale Semiconductor.
1495 + *
1496 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
1497 + *
1498 + * This program is free software; you can redistribute it and/or modify
1499 + * it under the terms of the GNU General Public License version 2 as
1500 + * published by the Free Software Foundation.
1501 + */
1502 +
1503 +
1504 +#ifndef _PCIE_LAYERSCAPE_EP_H
1505 +#define _PCIE_LAYERSCAPE_EP_H
1506 +
1507 +#include <linux/device.h>
1508 +
1509 +/* Synopsis specific PCIE configuration registers */
1510 +#define PCIE_ATU_VIEWPORT 0x900
1511 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
1512 +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
1513 +#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
1514 +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
1515 +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
1516 +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
1517 +#define PCIE_ATU_CR1 0x904
1518 +#define PCIE_ATU_TYPE_MEM (0x0 << 0)
1519 +#define PCIE_ATU_TYPE_IO (0x2 << 0)
1520 +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
1521 +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
1522 +#define PCIE_ATU_CR2 0x908
1523 +#define PCIE_ATU_ENABLE (0x1 << 31)
1524 +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
1525 +#define PCIE_ATU_LOWER_BASE 0x90C
1526 +#define PCIE_ATU_UPPER_BASE 0x910
1527 +#define PCIE_ATU_LIMIT 0x914
1528 +#define PCIE_ATU_LOWER_TARGET 0x918
1529 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
1530 +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
1531 +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
1532 +#define PCIE_ATU_UPPER_TARGET 0x91C
1533 +
1534 +/* PEX internal configuration registers */
1535 +#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
1536 +
1537 +/* PEX LUT registers */
1538 +#define PCIE_LUT_BASE 0x80000
1539 +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug register */
1540 +
1541 +#define PCIE_LUT_LCTRL0 0x7F8
1542 +
1543 +#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
1544 +#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
1545 +#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
1546 +#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
1547 +#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
1548 +#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
1549 + PCIE_LCTRL0_VF(vf) | \
1550 + ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
1551 + PCIE_LCTRL0_CFG2_ENABLE)
1552 +
1553 +#define PCIE_NO_SRIOV_BAR_BASE 0x1000
1554 +
1555 +#define PCIE_SRIOV_POS 0x178
1556 +#define PCIE_PF_NUM 2
1557 +#define PCIE_VF_NUM 64
1558 +
1559 +struct ls_pcie_ep_drvdata {
1560 + u32 lut_offset;
1561 + u32 ltssm_shift;
1562 + u32 lut_dbg;
1563 +};
1564 +
1565 +struct ls_pcie {
1566 + struct list_head ep_list;
1567 + struct device *dev;
1568 + struct dentry *dir;
1569 + const struct ls_pcie_ep_drvdata *drvdata;
1570 + void __iomem *dbi;
1571 + void __iomem *lut;
1572 + phys_addr_t out_base;
1573 + int sriov;
1574 + int index;
1575 +};
1576 +
1577 +struct ls_ep_dev {
1578 + struct list_head node;
1579 + struct ls_pcie *pcie;
1580 + struct device dev;
1581 + struct dentry *dir;
1582 + int pf_idx;
1583 + int vf_idx;
1584 + int dev_id;
1585 + void *driver_data;
1586 +};
1587 +
1588 +struct ls_ep_dev *ls_pci_ep_find(struct ls_pcie *pcie, int dev_id);
1589 +
1590 +void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
1591 + u64 cpu_addr, u64 pci_addr, u32 size);
1592 +
1593 +/* Use bar match mode and MEM type as default */
1594 +void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
1595 + int bar, u64 phys);
1596 +
1597 +void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size);
1598 +
1599 +
1600 +void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep);
1601 +
1602 +int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie);
1603 +int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie);
1604 +
1605 +#endif /* _PCIE_LAYERSCAPE_EP_H */
1606 --- a/drivers/pci/host/pci-layerscape.c
1607 +++ b/drivers/pci/host/pci-layerscape.c
1608 @@ -35,12 +35,14 @@
1609 #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
1610 #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
1611
1612 -/* PEX LUT registers */
1613 -#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
1614 +#define PCIE_IATU_NUM 6
1615 +
1616 +static void ls_pcie_host_init(struct pcie_port *pp);
1617
1618 struct ls_pcie_drvdata {
1619 u32 lut_offset;
1620 u32 ltssm_shift;
1621 + u32 lut_dbg;
1622 struct pcie_host_ops *ops;
1623 };
1624
1625 @@ -86,6 +88,14 @@ static void ls_pcie_drop_msg_tlp(struct
1626 iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
1627 }
1628
1629 +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
1630 +{
1631 + int i;
1632 +
1633 + for (i = 0; i < PCIE_IATU_NUM; i++)
1634 + dw_pcie_disable_outbound_atu(&pcie->pp, i);
1635 +}
1636 +
1637 static int ls1021_pcie_link_up(struct pcie_port *pp)
1638 {
1639 u32 state;
1640 @@ -134,7 +144,7 @@ static int ls_pcie_link_up(struct pcie_p
1641 struct ls_pcie *pcie = to_ls_pcie(pp);
1642 u32 state;
1643
1644 - state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
1645 + state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
1646 pcie->drvdata->ltssm_shift) &
1647 LTSSM_STATE_MASK;
1648
1649 @@ -153,6 +163,9 @@ static void ls_pcie_host_init(struct pci
1650 ls_pcie_clear_multifunction(pcie);
1651 ls_pcie_drop_msg_tlp(pcie);
1652 iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
1653 +
1654 + ls_pcie_disable_outbound_atus(pcie);
1655 + dw_pcie_setup_rc(pp);
1656 }
1657
1658 static int ls_pcie_msi_host_init(struct pcie_port *pp,
1659 @@ -196,20 +209,38 @@ static struct ls_pcie_drvdata ls1021_drv
1660 static struct ls_pcie_drvdata ls1043_drvdata = {
1661 .lut_offset = 0x10000,
1662 .ltssm_shift = 24,
1663 + .lut_dbg = 0x7fc,
1664 + .ops = &ls_pcie_host_ops,
1665 +};
1666 +
1667 +static struct ls_pcie_drvdata ls1046_drvdata = {
1668 + .lut_offset = 0x80000,
1669 + .ltssm_shift = 24,
1670 + .lut_dbg = 0x407fc,
1671 .ops = &ls_pcie_host_ops,
1672 };
1673
1674 static struct ls_pcie_drvdata ls2080_drvdata = {
1675 .lut_offset = 0x80000,
1676 .ltssm_shift = 0,
1677 + .lut_dbg = 0x7fc,
1678 + .ops = &ls_pcie_host_ops,
1679 +};
1680 +
1681 +static struct ls_pcie_drvdata ls2088_drvdata = {
1682 + .lut_offset = 0x80000,
1683 + .ltssm_shift = 0,
1684 + .lut_dbg = 0x407fc,
1685 .ops = &ls_pcie_host_ops,
1686 };
1687
1688 static const struct of_device_id ls_pcie_of_match[] = {
1689 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
1690 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1691 + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1692 { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
1693 { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
1694 + { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
1695 { },
1696 };
1697
1698 --- a/drivers/pci/host/pcie-designware.c
1699 +++ b/drivers/pci/host/pcie-designware.c
1700 @@ -478,6 +478,12 @@ int dw_pcie_wait_for_link(struct pcie_po
1701 return -ETIMEDOUT;
1702 }
1703
1704 +void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index)
1705 +{
1706 + dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index);
1707 + dw_pcie_writel_rc(pp, PCIE_ATU_CR2, 0);
1708 +}
1709 +
1710 int dw_pcie_link_up(struct pcie_port *pp)
1711 {
1712 u32 val;
1713 --- a/drivers/pci/host/pcie-designware.h
1714 +++ b/drivers/pci/host/pcie-designware.h
1715 @@ -82,5 +82,6 @@ int dw_pcie_wait_for_link(struct pcie_po
1716 int dw_pcie_link_up(struct pcie_port *pp);
1717 void dw_pcie_setup_rc(struct pcie_port *pp);
1718 int dw_pcie_host_init(struct pcie_port *pp);
1719 +void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index);
1720
1721 #endif /* _PCIE_DESIGNWARE_H */
1722 --- a/drivers/pci/pcie/portdrv_core.c
1723 +++ b/drivers/pci/pcie/portdrv_core.c
1724 @@ -44,52 +44,30 @@ static void release_pcie_device(struct d
1725 }
1726
1727 /**
1728 - * pcie_port_msix_add_entry - add entry to given array of MSI-X entries
1729 - * @entries: Array of MSI-X entries
1730 - * @new_entry: Index of the entry to add to the array
1731 - * @nr_entries: Number of entries already in the array
1732 + * pcibios_check_service_irqs - check irqs in the device tree
1733 + * @dev: PCI Express port to handle
1734 + * @irqs: Array of irqs to populate
1735 + * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1736 + *
1737 + * Return value: 0 means no service irqs in the device tree
1738 *
1739 - * Return value: Position of the added entry in the array
1740 */
1741 -static int pcie_port_msix_add_entry(
1742 - struct msix_entry *entries, int new_entry, int nr_entries)
1743 +int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1744 {
1745 - int j;
1746 -
1747 - for (j = 0; j < nr_entries; j++)
1748 - if (entries[j].entry == new_entry)
1749 - return j;
1750 -
1751 - entries[j].entry = new_entry;
1752 - return j;
1753 + return 0;
1754 }
1755
1756 /**
1757 * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port
1758 * @dev: PCI Express port to handle
1759 - * @vectors: Array of interrupt vectors to populate
1760 + * @irqs: Array of interrupt vectors to populate
1761 * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1762 *
1763 * Return value: 0 on success, error code on failure
1764 */
1765 -static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1766 +static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask)
1767 {
1768 - struct msix_entry *msix_entries;
1769 - int idx[PCIE_PORT_DEVICE_MAXSERVICES];
1770 - int nr_entries, status, pos, i, nvec;
1771 - u16 reg16;
1772 - u32 reg32;
1773 -
1774 - nr_entries = pci_msix_vec_count(dev);
1775 - if (nr_entries < 0)
1776 - return nr_entries;
1777 - BUG_ON(!nr_entries);
1778 - if (nr_entries > PCIE_PORT_MAX_MSIX_ENTRIES)
1779 - nr_entries = PCIE_PORT_MAX_MSIX_ENTRIES;
1780 -
1781 - msix_entries = kzalloc(sizeof(*msix_entries) * nr_entries, GFP_KERNEL);
1782 - if (!msix_entries)
1783 - return -ENOMEM;
1784 + int nr_entries, entry, nvec = 0;
1785
1786 /*
1787 * Allocate as many entries as the port wants, so that we can check
1788 @@ -97,20 +75,13 @@ static int pcie_port_enable_msix(struct
1789 * equal to the number of entries this port actually uses, we'll happily
1790 * go through without any tricks.
1791 */
1792 - for (i = 0; i < nr_entries; i++)
1793 - msix_entries[i].entry = i;
1794 -
1795 - status = pci_enable_msix_exact(dev, msix_entries, nr_entries);
1796 - if (status)
1797 - goto Exit;
1798 -
1799 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1800 - idx[i] = -1;
1801 - status = -EIO;
1802 - nvec = 0;
1803 + nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSIX_ENTRIES,
1804 + PCI_IRQ_MSIX);
1805 + if (nr_entries < 0)
1806 + return nr_entries;
1807
1808 if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) {
1809 - int entry;
1810 + u16 reg16;
1811
1812 /*
1813 * The code below follows the PCI Express Base Specification 2.0
1814 @@ -125,18 +96,16 @@ static int pcie_port_enable_msix(struct
1815 pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16);
1816 entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
1817 if (entry >= nr_entries)
1818 - goto Error;
1819 + goto out_free_irqs;
1820
1821 - i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
1822 - if (i == nvec)
1823 - nvec++;
1824 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pci_irq_vector(dev, entry);
1825 + irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pci_irq_vector(dev, entry);
1826
1827 - idx[PCIE_PORT_SERVICE_PME_SHIFT] = i;
1828 - idx[PCIE_PORT_SERVICE_HP_SHIFT] = i;
1829 + nvec = max(nvec, entry + 1);
1830 }
1831
1832 if (mask & PCIE_PORT_SERVICE_AER) {
1833 - int entry;
1834 + u32 reg32, pos;
1835
1836 /*
1837 * The code below follows Section 7.10.10 of the PCI Express
1838 @@ -151,13 +120,11 @@ static int pcie_port_enable_msix(struct
1839 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
1840 entry = reg32 >> 27;
1841 if (entry >= nr_entries)
1842 - goto Error;
1843 + goto out_free_irqs;
1844
1845 - i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
1846 - if (i == nvec)
1847 - nvec++;
1848 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, entry);
1849
1850 - idx[PCIE_PORT_SERVICE_AER_SHIFT] = i;
1851 + nvec = max(nvec, entry + 1);
1852 }
1853
1854 /*
1855 @@ -165,41 +132,54 @@ static int pcie_port_enable_msix(struct
1856 * what we have. Otherwise, the port has some extra entries not for the
1857 * services we know and we need to work around that.
1858 */
1859 - if (nvec == nr_entries) {
1860 - status = 0;
1861 - } else {
1862 + if (nvec != nr_entries) {
1863 /* Drop the temporary MSI-X setup */
1864 - pci_disable_msix(dev);
1865 + pci_free_irq_vectors(dev);
1866
1867 /* Now allocate the MSI-X vectors for real */
1868 - status = pci_enable_msix_exact(dev, msix_entries, nvec);
1869 - if (status)
1870 - goto Exit;
1871 + nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec,
1872 + PCI_IRQ_MSIX);
1873 + if (nr_entries < 0)
1874 + return nr_entries;
1875 }
1876
1877 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1878 - vectors[i] = idx[i] >= 0 ? msix_entries[idx[i]].vector : -1;
1879 -
1880 - Exit:
1881 - kfree(msix_entries);
1882 - return status;
1883 + return 0;
1884
1885 - Error:
1886 - pci_disable_msix(dev);
1887 - goto Exit;
1888 +out_free_irqs:
1889 + pci_free_irq_vectors(dev);
1890 + return -EIO;
1891 }
1892
1893 /**
1894 - * init_service_irqs - initialize irqs for PCI Express port services
1895 + * pcie_init_service_irqs - initialize irqs for PCI Express port services
1896 * @dev: PCI Express port to handle
1897 * @irqs: Array of irqs to populate
1898 * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1899 *
1900 * Return value: Interrupt mode associated with the port
1901 */
1902 -static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1903 +static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1904 {
1905 - int i, irq = -1;
1906 + unsigned flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
1907 + int ret, i;
1908 + int irq = -1;
1909 +
1910 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1911 + irqs[i] = -1;
1912 +
1913 + /* Check if some platforms owns independent irq pins for AER/PME etc.
1914 + * Some platforms may own independent AER/PME interrupts and set
1915 + * them in the device tree file.
1916 + */
1917 + ret = pcibios_check_service_irqs(dev, irqs, mask);
1918 + if (ret) {
1919 + if (dev->irq)
1920 + irq = dev->irq;
1921 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1922 + if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
1923 + irqs[i] = irq;
1924 + return 0;
1925 + }
1926
1927 /*
1928 * If MSI cannot be used for PCIe PME or hotplug, we have to use
1929 @@ -207,41 +187,25 @@ static int init_service_irqs(struct pci_
1930 */
1931 if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) ||
1932 ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) {
1933 - if (dev->irq)
1934 - irq = dev->irq;
1935 - goto no_msi;
1936 + flags &= ~PCI_IRQ_MSI;
1937 + } else {
1938 + /* Try to use MSI-X if supported */
1939 + if (!pcie_port_enable_msix(dev, irqs, mask))
1940 + return 0;
1941 }
1942
1943 - /* Try to use MSI-X if supported */
1944 - if (!pcie_port_enable_msix(dev, irqs, mask))
1945 - return 0;
1946 -
1947 - /*
1948 - * We're not going to use MSI-X, so try MSI and fall back to INTx.
1949 - * If neither MSI/MSI-X nor INTx available, try other interrupt. On
1950 - * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
1951 - */
1952 - if (!pci_enable_msi(dev) || dev->irq)
1953 - irq = dev->irq;
1954 + ret = pci_alloc_irq_vectors(dev, 1, 1, flags);
1955 + if (ret < 0)
1956 + return -ENODEV;
1957
1958 - no_msi:
1959 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1960 - irqs[i] = irq;
1961 - irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
1962 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
1963 + if (i != PCIE_PORT_SERVICE_VC_SHIFT)
1964 + irqs[i] = pci_irq_vector(dev, 0);
1965 + }
1966
1967 - if (irq < 0)
1968 - return -ENODEV;
1969 return 0;
1970 }
1971
1972 -static void cleanup_service_irqs(struct pci_dev *dev)
1973 -{
1974 - if (dev->msix_enabled)
1975 - pci_disable_msix(dev);
1976 - else if (dev->msi_enabled)
1977 - pci_disable_msi(dev);
1978 -}
1979 -
1980 /**
1981 * get_port_device_capability - discover capabilities of a PCI Express port
1982 * @dev: PCI Express port to examine
1983 @@ -378,7 +342,7 @@ int pcie_port_device_register(struct pci
1984 * that can be used in the absence of irqs. Allow them to determine
1985 * if that is to be used.
1986 */
1987 - status = init_service_irqs(dev, irqs, capabilities);
1988 + status = pcie_init_service_irqs(dev, irqs, capabilities);
1989 if (status) {
1990 capabilities &= PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_HP;
1991 if (!capabilities)
1992 @@ -401,7 +365,7 @@ int pcie_port_device_register(struct pci
1993 return 0;
1994
1995 error_cleanup_irqs:
1996 - cleanup_service_irqs(dev);
1997 + pci_free_irq_vectors(dev);
1998 error_disable:
1999 pci_disable_device(dev);
2000 return status;
2001 @@ -469,7 +433,7 @@ static int remove_iter(struct device *de
2002 void pcie_port_device_remove(struct pci_dev *dev)
2003 {
2004 device_for_each_child(&dev->dev, NULL, remove_iter);
2005 - cleanup_service_irqs(dev);
2006 + pci_free_irq_vectors(dev);
2007 pci_disable_device(dev);
2008 }
2009
2010 @@ -499,7 +463,6 @@ static int pcie_port_probe_service(struc
2011 if (status)
2012 return status;
2013
2014 - dev_printk(KERN_DEBUG, dev, "service driver %s loaded\n", driver->name);
2015 get_device(dev);
2016 return 0;
2017 }
2018 @@ -524,8 +487,6 @@ static int pcie_port_remove_service(stru
2019 pciedev = to_pcie_device(dev);
2020 driver = to_service_driver(dev->driver);
2021 if (driver && driver->remove) {
2022 - dev_printk(KERN_DEBUG, dev, "unloading service driver %s\n",
2023 - driver->name);
2024 driver->remove(pciedev);
2025 put_device(dev);
2026 }
2027 --- a/include/linux/pci.h
2028 +++ b/include/linux/pci.h
2029 @@ -1823,6 +1823,7 @@ void pcibios_release_device(struct pci_d
2030 void pcibios_penalize_isa_irq(int irq, int active);
2031 int pcibios_alloc_irq(struct pci_dev *dev);
2032 void pcibios_free_irq(struct pci_dev *dev);
2033 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
2034
2035 #ifdef CONFIG_HIBERNATE_CALLBACKS
2036 extern struct dev_pm_ops pcibios_pm_ops;
Staging tree of Christian Lamparter