target/linux/layerscape/patches-4.9/815-spi-support-layerscape.patch

   1 From a12f522b48a8cb637c1c026b46a76b2ef7983f8d Mon Sep 17 00:00:00 2001
   2 From: Yangbo Lu <yangbo.lu@nxp.com>
   3 Date: Mon, 25 Sep 2017 12:12:41 +0800
   4 Subject: [PATCH] spi: support layerscape
   5
   6 This is a integrated patch for layerscape dspi support.
   7
   8 Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
   9 Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
  10 Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
  11 Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
  12 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  13 ---
  14  drivers/spi/Kconfig        |   1 +
  15  drivers/spi/spi-fsl-dspi.c | 309 ++++++++++++++++++++++++++++++++++++++++++++-
  16  2 files changed, 305 insertions(+), 5 deletions(-)
  17
  18 --- a/drivers/spi/Kconfig
  19 +++ b/drivers/spi/Kconfig
  20 @@ -365,6 +365,7 @@ config SPI_FSL_SPI
  21  config SPI_FSL_DSPI
  22         tristate "Freescale DSPI controller"
  23         select REGMAP_MMIO
  24 +       depends on HAS_DMA
  25         depends on SOC_VF610 || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
  26         help
  27           This enables support for the Freescale DSPI controller in master
  28 --- a/drivers/spi/spi-fsl-dspi.c
  29 +++ b/drivers/spi/spi-fsl-dspi.c
  30 @@ -15,6 +15,8 @@
  31
  32  #include <linux/clk.h>
  33  #include <linux/delay.h>
  34 +#include <linux/dmaengine.h>
  35 +#include <linux/dma-mapping.h>
  36  #include <linux/err.h>
  37  #include <linux/errno.h>
  38  #include <linux/interrupt.h>
  39 @@ -40,6 +42,7 @@
  40  #define TRAN_STATE_WORD_ODD_NUM        0x04
  41
  42  #define DSPI_FIFO_SIZE                 4
  43 +#define DSPI_DMA_BUFSIZE               (DSPI_FIFO_SIZE * 1024)
  44
  45  #define SPI_MCR                0x00
  46  #define SPI_MCR_MASTER         (1 << 31)
  47 @@ -72,6 +75,11 @@
  48  #define SPI_SR_TCFQF           0x80000000
  49  #define SPI_SR_CLEAR           0xdaad0000
  50
  51 +#define SPI_RSER_TFFFE         BIT(25)
  52 +#define SPI_RSER_TFFFD         BIT(24)
  53 +#define SPI_RSER_RFDFE         BIT(17)
  54 +#define SPI_RSER_RFDFD         BIT(16)
  55 +
  56  #define SPI_RSER               0x30
  57  #define SPI_RSER_EOQFE         0x10000000
  58  #define SPI_RSER_TCFQE         0x80000000
  59 @@ -109,6 +117,8 @@
  60
  61  #define SPI_TCR_TCNT_MAX       0x10000
  62
  63 +#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
  64 +
  65  struct chip_data {
  66         u32 mcr_val;
  67         u32 ctar_val;
  68 @@ -118,6 +128,7 @@ struct chip_data {
  69  enum dspi_trans_mode {
  70         DSPI_EOQ_MODE = 0,
  71         DSPI_TCFQ_MODE,
  72 +       DSPI_DMA_MODE,
  73  };
  74
  75  struct fsl_dspi_devtype_data {
  76 @@ -126,7 +137,7 @@ struct fsl_dspi_devtype_data {
  77  };
  78
  79  static const struct fsl_dspi_devtype_data vf610_data = {
  80 -       .trans_mode = DSPI_EOQ_MODE,
  81 +       .trans_mode = DSPI_DMA_MODE,
  82         .max_clock_factor = 2,
  83  };
  84
  85 @@ -140,6 +151,23 @@ static const struct fsl_dspi_devtype_dat
  86         .max_clock_factor = 8,
  87  };
  88
  89 +struct fsl_dspi_dma {
  90 +       /* Length of transfer in words of DSPI_FIFO_SIZE */
  91 +       u32 curr_xfer_len;
  92 +
  93 +       u32 *tx_dma_buf;
  94 +       struct dma_chan *chan_tx;
  95 +       dma_addr_t tx_dma_phys;
  96 +       struct completion cmd_tx_complete;
  97 +       struct dma_async_tx_descriptor *tx_desc;
  98 +
  99 +       u32 *rx_dma_buf;
 100 +       struct dma_chan *chan_rx;
 101 +       dma_addr_t rx_dma_phys;
 102 +       struct completion cmd_rx_complete;
 103 +       struct dma_async_tx_descriptor *rx_desc;
 104 +};
 105 +
 106  struct fsl_dspi {
 107         struct spi_master       *master;
 108         struct platform_device  *pdev;
 109 @@ -166,8 +194,11 @@ struct fsl_dspi {
 110         u32                     waitflags;
 111
 112         u32                     spi_tcnt;
 113 +       struct fsl_dspi_dma     *dma;
 114  };
 115
 116 +static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word);
 117 +
 118  static inline int is_double_byte_mode(struct fsl_dspi *dspi)
 119  {
 120         unsigned int val;
 121 @@ -177,6 +208,255 @@ static inline int is_double_byte_mode(st
 122         return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
 123  }
 124
 125 +static void dspi_tx_dma_callback(void *arg)
 126 +{
 127 +       struct fsl_dspi *dspi = arg;
 128 +       struct fsl_dspi_dma *dma = dspi->dma;
 129 +
 130 +       complete(&dma->cmd_tx_complete);
 131 +}
 132 +
 133 +static void dspi_rx_dma_callback(void *arg)
 134 +{
 135 +       struct fsl_dspi *dspi = arg;
 136 +       struct fsl_dspi_dma *dma = dspi->dma;
 137 +       int rx_word;
 138 +       int i;
 139 +       u16 d;
 140 +
 141 +       rx_word = is_double_byte_mode(dspi);
 142 +
 143 +       if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) {
 144 +               for (i = 0; i < dma->curr_xfer_len; i++) {
 145 +                       d = dspi->dma->rx_dma_buf[i];
 146 +                       rx_word ? (*(u16 *)dspi->rx = d) :
 147 +                                               (*(u8 *)dspi->rx = d);
 148 +                       dspi->rx += rx_word + 1;
 149 +               }
 150 +       }
 151 +
 152 +       complete(&dma->cmd_rx_complete);
 153 +}
 154 +
 155 +static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
 156 +{
 157 +       struct fsl_dspi_dma *dma = dspi->dma;
 158 +       struct device *dev = &dspi->pdev->dev;
 159 +       int time_left;
 160 +       int tx_word;
 161 +       int i;
 162 +
 163 +       tx_word = is_double_byte_mode(dspi);
 164 +
 165 +       for (i = 0; i < dma->curr_xfer_len; i++) {
 166 +               dspi->dma->tx_dma_buf[i] = dspi_data_to_pushr(dspi, tx_word);
 167 +               if ((dspi->cs_change) && (!dspi->len))
 168 +                       dspi->dma->tx_dma_buf[i] &= ~SPI_PUSHR_CONT;
 169 +       }
 170 +
 171 +       dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
 172 +                                       dma->tx_dma_phys,
 173 +                                       dma->curr_xfer_len *
 174 +                                       DMA_SLAVE_BUSWIDTH_4_BYTES,
 175 +                                       DMA_MEM_TO_DEV,
 176 +                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 177 +       if (!dma->tx_desc) {
 178 +               dev_err(dev, "Not able to get desc for DMA xfer\n");
 179 +               return -EIO;
 180 +       }
 181 +
 182 +       dma->tx_desc->callback = dspi_tx_dma_callback;
 183 +       dma->tx_desc->callback_param = dspi;
 184 +       if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
 185 +               dev_err(dev, "DMA submit failed\n");
 186 +               return -EINVAL;
 187 +       }
 188 +
 189 +       dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
 190 +                                       dma->rx_dma_phys,
 191 +                                       dma->curr_xfer_len *
 192 +                                       DMA_SLAVE_BUSWIDTH_4_BYTES,
 193 +                                       DMA_DEV_TO_MEM,
 194 +                                       DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 195 +       if (!dma->rx_desc) {
 196 +               dev_err(dev, "Not able to get desc for DMA xfer\n");
 197 +               return -EIO;
 198 +       }
 199 +
 200 +       dma->rx_desc->callback = dspi_rx_dma_callback;
 201 +       dma->rx_desc->callback_param = dspi;
 202 +       if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
 203 +               dev_err(dev, "DMA submit failed\n");
 204 +               return -EINVAL;
 205 +       }
 206 +
 207 +       reinit_completion(&dspi->dma->cmd_rx_complete);
 208 +       reinit_completion(&dspi->dma->cmd_tx_complete);
 209 +
 210 +       dma_async_issue_pending(dma->chan_rx);
 211 +       dma_async_issue_pending(dma->chan_tx);
 212 +
 213 +       time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
 214 +                                       DMA_COMPLETION_TIMEOUT);
 215 +       if (time_left == 0) {
 216 +               dev_err(dev, "DMA tx timeout\n");
 217 +               dmaengine_terminate_all(dma->chan_tx);
 218 +               dmaengine_terminate_all(dma->chan_rx);
 219 +               return -ETIMEDOUT;
 220 +       }
 221 +
 222 +       time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
 223 +                                       DMA_COMPLETION_TIMEOUT);
 224 +       if (time_left == 0) {
 225 +               dev_err(dev, "DMA rx timeout\n");
 226 +               dmaengine_terminate_all(dma->chan_tx);
 227 +               dmaengine_terminate_all(dma->chan_rx);
 228 +               return -ETIMEDOUT;
 229 +       }
 230 +
 231 +       return 0;
 232 +}
 233 +
 234 +static int dspi_dma_xfer(struct fsl_dspi *dspi)
 235 +{
 236 +       struct fsl_dspi_dma *dma = dspi->dma;
 237 +       struct device *dev = &dspi->pdev->dev;
 238 +       int curr_remaining_bytes;
 239 +       int bytes_per_buffer;
 240 +       int word = 1;
 241 +       int ret = 0;
 242 +
 243 +       if (is_double_byte_mode(dspi))
 244 +               word = 2;
 245 +       curr_remaining_bytes = dspi->len;
 246 +       bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
 247 +       while (curr_remaining_bytes) {
 248 +               /* Check if current transfer fits the DMA buffer */
 249 +               dma->curr_xfer_len = curr_remaining_bytes / word;
 250 +               if (dma->curr_xfer_len > bytes_per_buffer)
 251 +                       dma->curr_xfer_len = bytes_per_buffer;
 252 +
 253 +               ret = dspi_next_xfer_dma_submit(dspi);
 254 +               if (ret) {
 255 +                       dev_err(dev, "DMA transfer failed\n");
 256 +                       goto exit;
 257 +
 258 +               } else {
 259 +                       curr_remaining_bytes -= dma->curr_xfer_len * word;
 260 +                       if (curr_remaining_bytes < 0)
 261 +                               curr_remaining_bytes = 0;
 262 +               }
 263 +       }
 264 +
 265 +exit:
 266 +       return ret;
 267 +}
 268 +
 269 +static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
 270 +{
 271 +       struct fsl_dspi_dma *dma;
 272 +       struct dma_slave_config cfg;
 273 +       struct device *dev = &dspi->pdev->dev;
 274 +       int ret;
 275 +
 276 +       dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
 277 +       if (!dma)
 278 +               return -ENOMEM;
 279 +
 280 +       dma->chan_rx = dma_request_slave_channel(dev, "rx");
 281 +       if (!dma->chan_rx) {
 282 +               dev_err(dev, "rx dma channel not available\n");
 283 +               ret = -ENODEV;
 284 +               return ret;
 285 +       }
 286 +
 287 +       dma->chan_tx = dma_request_slave_channel(dev, "tx");
 288 +       if (!dma->chan_tx) {
 289 +               dev_err(dev, "tx dma channel not available\n");
 290 +               ret = -ENODEV;
 291 +               goto err_tx_channel;
 292 +       }
 293 +
 294 +       dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
 295 +                                       &dma->tx_dma_phys, GFP_KERNEL);
 296 +       if (!dma->tx_dma_buf) {
 297 +               ret = -ENOMEM;
 298 +               goto err_tx_dma_buf;
 299 +       }
 300 +
 301 +       dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
 302 +                                       &dma->rx_dma_phys, GFP_KERNEL);
 303 +       if (!dma->rx_dma_buf) {
 304 +               ret = -ENOMEM;
 305 +               goto err_rx_dma_buf;
 306 +       }
 307 +
 308 +       cfg.src_addr = phy_addr + SPI_POPR;
 309 +       cfg.dst_addr = phy_addr + SPI_PUSHR;
 310 +       cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 311 +       cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 312 +       cfg.src_maxburst = 1;
 313 +       cfg.dst_maxburst = 1;
 314 +
 315 +       cfg.direction = DMA_DEV_TO_MEM;
 316 +       ret = dmaengine_slave_config(dma->chan_rx, &cfg);
 317 +       if (ret) {
 318 +               dev_err(dev, "can't configure rx dma channel\n");
 319 +               ret = -EINVAL;
 320 +               goto err_slave_config;
 321 +       }
 322 +
 323 +       cfg.direction = DMA_MEM_TO_DEV;
 324 +       ret = dmaengine_slave_config(dma->chan_tx, &cfg);
 325 +       if (ret) {
 326 +               dev_err(dev, "can't configure tx dma channel\n");
 327 +               ret = -EINVAL;
 328 +               goto err_slave_config;
 329 +       }
 330 +
 331 +       dspi->dma = dma;
 332 +       init_completion(&dma->cmd_tx_complete);
 333 +       init_completion(&dma->cmd_rx_complete);
 334 +
 335 +       return 0;
 336 +
 337 +err_slave_config:
 338 +       dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
 339 +                       dma->rx_dma_buf, dma->rx_dma_phys);
 340 +err_rx_dma_buf:
 341 +       dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
 342 +                       dma->tx_dma_buf, dma->tx_dma_phys);
 343 +err_tx_dma_buf:
 344 +       dma_release_channel(dma->chan_tx);
 345 +err_tx_channel:
 346 +       dma_release_channel(dma->chan_rx);
 347 +
 348 +       devm_kfree(dev, dma);
 349 +       dspi->dma = NULL;
 350 +
 351 +       return ret;
 352 +}
 353 +
 354 +static void dspi_release_dma(struct fsl_dspi *dspi)
 355 +{
 356 +       struct fsl_dspi_dma *dma = dspi->dma;
 357 +       struct device *dev = &dspi->pdev->dev;
 358 +
 359 +       if (dma) {
 360 +               if (dma->chan_tx) {
 361 +                       dma_unmap_single(dev, dma->tx_dma_phys,
 362 +                                       DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
 363 +                       dma_release_channel(dma->chan_tx);
 364 +               }
 365 +
 366 +               if (dma->chan_rx) {
 367 +                       dma_unmap_single(dev, dma->rx_dma_phys,
 368 +                                       DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
 369 +                       dma_release_channel(dma->chan_rx);
 370 +               }
 371 +       }
 372 +}
 373 +
 374  static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
 375                 unsigned long clkrate)
 376  {
 377 @@ -425,6 +705,12 @@ static int dspi_transfer_one_message(str
 378                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
 379                         dspi_tcfq_write(dspi);
 380                         break;
 381 +               case DSPI_DMA_MODE:
 382 +                       regmap_write(dspi->regmap, SPI_RSER,
 383 +                               SPI_RSER_TFFFE | SPI_RSER_TFFFD |
 384 +                               SPI_RSER_RFDFE | SPI_RSER_RFDFD);
 385 +                       status = dspi_dma_xfer(dspi);
 386 +                       break;
 387                 default:
 388                         dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 389                                 trans_mode);
 390 @@ -432,9 +718,13 @@ static int dspi_transfer_one_message(str
 391                         goto out;
 392                 }
 393
 394 -               if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
 395 -                       dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
 396 -               dspi->waitflags = 0;
 397 +               if (trans_mode != DSPI_DMA_MODE) {
 398 +                       if (wait_event_interruptible(dspi->waitq,
 399 +                                               dspi->waitflags))
 400 +                               dev_err(&dspi->pdev->dev,
 401 +                                       "wait transfer complete fail!\n");
 402 +                       dspi->waitflags = 0;
 403 +               }
 404
 405                 if (transfer->delay_usecs)
 406                         udelay(transfer->delay_usecs);
 407 @@ -712,7 +1002,8 @@ static int dspi_probe(struct platform_de
 408         if (IS_ERR(dspi->regmap)) {
 409                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
 410                                 PTR_ERR(dspi->regmap));
 411 -               return PTR_ERR(dspi->regmap);
 412 +               ret = PTR_ERR(dspi->regmap);
 413 +               goto out_master_put;
 414         }
 415
 416         dspi_init(dspi);
 417 @@ -740,6 +1031,13 @@ static int dspi_probe(struct platform_de
 418         if (ret)
 419                 goto out_master_put;
 420
 421 +       if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
 422 +               if (dspi_request_dma(dspi, res->start)) {
 423 +                       dev_err(&pdev->dev, "can't get dma channels\n");
 424 +                       goto out_clk_put;
 425 +               }
 426 +       }
 427 +
 428         master->max_speed_hz =
 429                 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
 430
 431 @@ -768,6 +1066,7 @@ static int dspi_remove(struct platform_d
 432         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 433
 434         /* Disconnect from the SPI framework */
 435 +       dspi_release_dma(dspi);
 436         clk_disable_unprepare(dspi->clk);
 437         spi_unregister_master(dspi->master);
 438