652116d0da7e27fd1124009b907e4bf30107abf2
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.14 / 0107-usb-mtu3-support-36-bit-DMA-address.patch
1 From d366bf086a61b7a895d8819a3c1349b9c6b8e40f Mon Sep 17 00:00:00 2001
2 From: Chunfeng Yun <chunfeng.yun@mediatek.com>
3 Date: Fri, 13 Oct 2017 17:10:41 +0800
4 Subject: [PATCH 107/224] usb: mtu3: support 36-bit DMA address
5
6 add support for 36-bit DMA address
7
8 [ Felipe Balbi: fix printk format for dma_addr_t ]
9
10 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
11 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
12 ---
13 drivers/usb/mtu3/mtu3.h | 17 ++++++-
14 drivers/usb/mtu3/mtu3_core.c | 34 +++++++++++++-
15 drivers/usb/mtu3/mtu3_hw_regs.h | 10 ++++
16 drivers/usb/mtu3/mtu3_qmu.c | 102 +++++++++++++++++++++++++++++++++-------
17 4 files changed, 142 insertions(+), 21 deletions(-)
18
19 diff --git a/drivers/usb/mtu3/mtu3.h b/drivers/usb/mtu3/mtu3.h
20 index 2795294ec92a..ef2dc92a2109 100644
21 --- a/drivers/usb/mtu3/mtu3.h
22 +++ b/drivers/usb/mtu3/mtu3.h
23 @@ -46,6 +46,9 @@ struct mtu3_request;
24 #define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
25 #define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
26
27 +#define USB_QMU_TQHIAR(epnum) (U3D_TXQHIAR1 + (((epnum) - 1) * 0x4))
28 +#define USB_QMU_RQHIAR(epnum) (U3D_RXQHIAR1 + (((epnum) - 1) * 0x4))
29 +
30 #define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
31 #define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
32 #define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
33 @@ -138,23 +141,33 @@ struct mtu3_fifo_info {
34 * Checksum value is calculated over the 16 bytes of the GPD by default;
35 * @data_buf_len (RX ONLY): This value indicates the length of
36 * the assigned data buffer
37 + * @tx_ext_addr (TX ONLY): [3:0] are 4 extension bits of @buffer,
38 + * [7:4] are 4 extension bits of @next_gpd
39 * @next_gpd: Physical address of the next GPD
40 * @buffer: Physical address of the data buffer
41 * @buf_len:
42 * (TX): This value indicates the length of the assigned data buffer
43 * (RX): The total length of data received
44 * @ext_len: reserved
45 + * @rx_ext_addr(RX ONLY): [3:0] are 4 extension bits of @buffer,
46 + * [7:4] are 4 extension bits of @next_gpd
47 * @ext_flag:
48 * bit5 (TX ONLY): Zero Length Packet (ZLP),
49 */
50 struct qmu_gpd {
51 __u8 flag;
52 __u8 chksum;
53 - __le16 data_buf_len;
54 + union {
55 + __le16 data_buf_len;
56 + __le16 tx_ext_addr;
57 + };
58 __le32 next_gpd;
59 __le32 buffer;
60 __le16 buf_len;
61 - __u8 ext_len;
62 + union {
63 + __u8 ext_len;
64 + __u8 rx_ext_addr;
65 + };
66 __u8 ext_flag;
67 } __packed;
68
69 diff --git a/drivers/usb/mtu3/mtu3_core.c b/drivers/usb/mtu3/mtu3_core.c
70 index 947579842ad7..cd4528f5f337 100644
71 --- a/drivers/usb/mtu3/mtu3_core.c
72 +++ b/drivers/usb/mtu3/mtu3_core.c
73 @@ -17,6 +17,7 @@
74 *
75 */
76
77 +#include <linux/dma-mapping.h>
78 #include <linux/kernel.h>
79 #include <linux/module.h>
80 #include <linux/of_address.h>
81 @@ -759,7 +760,31 @@ static void mtu3_hw_exit(struct mtu3 *mtu)
82 mtu3_mem_free(mtu);
83 }
84
85 -/*-------------------------------------------------------------------------*/
86 +/**
87 + * we set 32-bit DMA mask by default, here check whether the controller
88 + * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
89 + */
90 +static int mtu3_set_dma_mask(struct mtu3 *mtu)
91 +{
92 + struct device *dev = mtu->dev;
93 + bool is_36bit = false;
94 + int ret = 0;
95 + u32 value;
96 +
97 + value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
98 + if (value & DMA_ADDR_36BIT) {
99 + is_36bit = true;
100 + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
101 + /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
102 + if (ret) {
103 + is_36bit = false;
104 + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
105 + }
106 + }
107 + dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
108 +
109 + return ret;
110 +}
111
112 int ssusb_gadget_init(struct ssusb_mtk *ssusb)
113 {
114 @@ -820,6 +845,12 @@ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
115 return ret;
116 }
117
118 + ret = mtu3_set_dma_mask(mtu);
119 + if (ret) {
120 + dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
121 + goto dma_mask_err;
122 + }
123 +
124 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
125 if (ret) {
126 dev_err(dev, "request irq %d failed!\n", mtu->irq);
127 @@ -845,6 +876,7 @@ int ssusb_gadget_init(struct ssusb_mtk *ssusb)
128 gadget_err:
129 device_init_wakeup(dev, false);
130
131 +dma_mask_err:
132 irq_err:
133 mtu3_hw_exit(mtu);
134 ssusb->u3d = NULL;
135 diff --git a/drivers/usb/mtu3/mtu3_hw_regs.h b/drivers/usb/mtu3/mtu3_hw_regs.h
136 index 06b29664470f..b6059752dc12 100644
137 --- a/drivers/usb/mtu3/mtu3_hw_regs.h
138 +++ b/drivers/usb/mtu3/mtu3_hw_regs.h
139 @@ -58,6 +58,8 @@
140 #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404)
141 #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408)
142 #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C)
143 +#define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484)
144 +#define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4)
145
146 #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510)
147 #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514)
148 @@ -189,6 +191,13 @@
149 #define QMU_RX_COZ(x) (BIT(16) << (x))
150 #define QMU_RX_ZLP(x) (BIT(0) << (x))
151
152 +/* U3D_TXQHIAR1 */
153 +/* U3D_RXQHIAR1 */
154 +#define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf)
155 +#define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf)
156 +#define QMU_START_ADDR_HI_MSK GENMASK(3, 0)
157 +#define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0)
158 +
159 /* U3D_TXQCSR1 */
160 /* U3D_RXQCSR1 */
161 #define QMU_Q_ACTIVE BIT(15)
162 @@ -225,6 +234,7 @@
163 #define CAP_TX_EP_NUM(x) ((x) & 0x1f)
164
165 /* U3D_MISC_CTRL */
166 +#define DMA_ADDR_36BIT BIT(31)
167 #define VBUS_ON BIT(1)
168 #define VBUS_FRC_EN BIT(0)
169
170 diff --git a/drivers/usb/mtu3/mtu3_qmu.c b/drivers/usb/mtu3/mtu3_qmu.c
171 index 7d9ba8a52368..42145a3f1422 100644
172 --- a/drivers/usb/mtu3/mtu3_qmu.c
173 +++ b/drivers/usb/mtu3/mtu3_qmu.c
174 @@ -40,7 +40,58 @@
175 #define GPD_FLAGS_IOC BIT(7)
176
177 #define GPD_EXT_FLAG_ZLP BIT(5)
178 +#define GPD_EXT_NGP(x) (((x) & 0xf) << 4)
179 +#define GPD_EXT_BUF(x) (((x) & 0xf) << 0)
180
181 +#define HILO_GEN64(hi, lo) (((u64)(hi) << 32) + (lo))
182 +#define HILO_DMA(hi, lo) \
183 + ((dma_addr_t)HILO_GEN64((le32_to_cpu(hi)), (le32_to_cpu(lo))))
184 +
185 +static dma_addr_t read_txq_cur_addr(void __iomem *mbase, u8 epnum)
186 +{
187 + u32 txcpr;
188 + u32 txhiar;
189 +
190 + txcpr = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
191 + txhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
192 +
193 + return HILO_DMA(QMU_CUR_GPD_ADDR_HI(txhiar), txcpr);
194 +}
195 +
196 +static dma_addr_t read_rxq_cur_addr(void __iomem *mbase, u8 epnum)
197 +{
198 + u32 rxcpr;
199 + u32 rxhiar;
200 +
201 + rxcpr = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
202 + rxhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
203 +
204 + return HILO_DMA(QMU_CUR_GPD_ADDR_HI(rxhiar), rxcpr);
205 +}
206 +
207 +static void write_txq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
208 +{
209 + u32 tqhiar;
210 +
211 + mtu3_writel(mbase, USB_QMU_TQSAR(epnum),
212 + cpu_to_le32(lower_32_bits(dma)));
213 + tqhiar = mtu3_readl(mbase, USB_QMU_TQHIAR(epnum));
214 + tqhiar &= ~QMU_START_ADDR_HI_MSK;
215 + tqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
216 + mtu3_writel(mbase, USB_QMU_TQHIAR(epnum), tqhiar);
217 +}
218 +
219 +static void write_rxq_start_addr(void __iomem *mbase, u8 epnum, dma_addr_t dma)
220 +{
221 + u32 rqhiar;
222 +
223 + mtu3_writel(mbase, USB_QMU_RQSAR(epnum),
224 + cpu_to_le32(lower_32_bits(dma)));
225 + rqhiar = mtu3_readl(mbase, USB_QMU_RQHIAR(epnum));
226 + rqhiar &= ~QMU_START_ADDR_HI_MSK;
227 + rqhiar |= QMU_START_ADDR_HI(upper_32_bits(dma));
228 + mtu3_writel(mbase, USB_QMU_RQHIAR(epnum), rqhiar);
229 +}
230
231 static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring,
232 dma_addr_t dma_addr)
233 @@ -193,21 +244,27 @@ static int mtu3_prepare_tx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
234 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
235 struct qmu_gpd *gpd = ring->enqueue;
236 struct usb_request *req = &mreq->request;
237 + dma_addr_t enq_dma;
238 + u16 ext_addr;
239
240 /* set all fields to zero as default value */
241 memset(gpd, 0, sizeof(*gpd));
242
243 - gpd->buffer = cpu_to_le32((u32)req->dma);
244 + gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
245 + ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma));
246 gpd->buf_len = cpu_to_le16(req->length);
247 gpd->flag |= GPD_FLAGS_IOC;
248
249 /* get the next GPD */
250 enq = advance_enq_gpd(ring);
251 - dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p\n",
252 - mep->epnum, gpd, enq);
253 + enq_dma = gpd_virt_to_dma(ring, enq);
254 + dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
255 + mep->epnum, gpd, enq, enq_dma);
256
257 enq->flag &= ~GPD_FLAGS_HWO;
258 - gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
259 + gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
260 + ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma));
261 + gpd->tx_ext_addr = cpu_to_le16(ext_addr);
262
263 if (req->zero)
264 gpd->ext_flag |= GPD_EXT_FLAG_ZLP;
265 @@ -226,21 +283,27 @@ static int mtu3_prepare_rx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq)
266 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
267 struct qmu_gpd *gpd = ring->enqueue;
268 struct usb_request *req = &mreq->request;
269 + dma_addr_t enq_dma;
270 + u16 ext_addr;
271
272 /* set all fields to zero as default value */
273 memset(gpd, 0, sizeof(*gpd));
274
275 - gpd->buffer = cpu_to_le32((u32)req->dma);
276 + gpd->buffer = cpu_to_le32(lower_32_bits(req->dma));
277 + ext_addr = GPD_EXT_BUF(upper_32_bits(req->dma));
278 gpd->data_buf_len = cpu_to_le16(req->length);
279 gpd->flag |= GPD_FLAGS_IOC;
280
281 /* get the next GPD */
282 enq = advance_enq_gpd(ring);
283 - dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p\n",
284 - mep->epnum, gpd, enq);
285 + enq_dma = gpd_virt_to_dma(ring, enq);
286 + dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p, qdma=%pad\n",
287 + mep->epnum, gpd, enq, enq_dma);
288
289 enq->flag &= ~GPD_FLAGS_HWO;
290 - gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq));
291 + gpd->next_gpd = cpu_to_le32(lower_32_bits(enq_dma));
292 + ext_addr |= GPD_EXT_NGP(upper_32_bits(enq_dma));
293 + gpd->rx_ext_addr = cpu_to_le16(ext_addr);
294 gpd->chksum = qmu_calc_checksum((u8 *)gpd);
295 gpd->flag |= GPD_FLAGS_HWO;
296
297 @@ -267,8 +330,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep)
298
299 if (mep->is_in) {
300 /* set QMU start address */
301 - mtu3_writel(mbase, USB_QMU_TQSAR(mep->epnum), ring->dma);
302 - mtu3_setbits(mbase, MU3D_EP_TXCR0(mep->epnum), TX_DMAREQEN);
303 + write_txq_start_addr(mbase, epnum, ring->dma);
304 + mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN);
305 mtu3_setbits(mbase, U3D_QCR0, QMU_TX_CS_EN(epnum));
306 /* send zero length packet according to ZLP flag in GPD */
307 mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum));
308 @@ -282,8 +345,8 @@ int mtu3_qmu_start(struct mtu3_ep *mep)
309 mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START);
310
311 } else {
312 - mtu3_writel(mbase, USB_QMU_RQSAR(mep->epnum), ring->dma);
313 - mtu3_setbits(mbase, MU3D_EP_RXCR0(mep->epnum), RX_DMAREQEN);
314 + write_rxq_start_addr(mbase, epnum, ring->dma);
315 + mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN);
316 mtu3_setbits(mbase, U3D_QCR0, QMU_RX_CS_EN(epnum));
317 /* don't expect ZLP */
318 mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum));
319 @@ -353,9 +416,9 @@ static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
320 struct mtu3_gpd_ring *ring = &mep->gpd_ring;
321 void __iomem *mbase = mtu->mac_base;
322 struct qmu_gpd *gpd_current = NULL;
323 - dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
324 struct usb_request *req = NULL;
325 struct mtu3_request *mreq;
326 + dma_addr_t cur_gpd_dma;
327 u32 txcsr = 0;
328 int ret;
329
330 @@ -365,7 +428,8 @@ static void qmu_tx_zlp_error_handler(struct mtu3 *mtu, u8 epnum)
331 else
332 return;
333
334 - gpd_current = gpd_dma_to_virt(ring, gpd_dma);
335 + cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
336 + gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
337
338 if (le16_to_cpu(gpd_current->buf_len) != 0) {
339 dev_err(mtu->dev, "TX EP%d buffer length error(!=0)\n", epnum);
340 @@ -408,12 +472,13 @@ static void qmu_done_tx(struct mtu3 *mtu, u8 epnum)
341 void __iomem *mbase = mtu->mac_base;
342 struct qmu_gpd *gpd = ring->dequeue;
343 struct qmu_gpd *gpd_current = NULL;
344 - dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum));
345 struct usb_request *request = NULL;
346 struct mtu3_request *mreq;
347 + dma_addr_t cur_gpd_dma;
348
349 /*transfer phy address got from QMU register to virtual address */
350 - gpd_current = gpd_dma_to_virt(ring, gpd_dma);
351 + cur_gpd_dma = read_txq_cur_addr(mbase, epnum);
352 + gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
353
354 dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
355 __func__, epnum, gpd, gpd_current, ring->enqueue);
356 @@ -446,11 +511,12 @@ static void qmu_done_rx(struct mtu3 *mtu, u8 epnum)
357 void __iomem *mbase = mtu->mac_base;
358 struct qmu_gpd *gpd = ring->dequeue;
359 struct qmu_gpd *gpd_current = NULL;
360 - dma_addr_t gpd_dma = mtu3_readl(mbase, USB_QMU_RQCPR(epnum));
361 struct usb_request *req = NULL;
362 struct mtu3_request *mreq;
363 + dma_addr_t cur_gpd_dma;
364
365 - gpd_current = gpd_dma_to_virt(ring, gpd_dma);
366 + cur_gpd_dma = read_rxq_cur_addr(mbase, epnum);
367 + gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma);
368
369 dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n",
370 __func__, epnum, gpd, gpd_current, ring->enqueue);
371 --
372 2.11.0
373