target/linux/mediatek/patches-4.14/0112-usb-mtu3-set-otg_sel-for-u2port-only-if-works-as-dua.patch

   1 From 36f70702b66cd3453b65d46b5c26ea87d8897363 Mon Sep 17 00:00:00 2001
   2 From: Chunfeng Yun <chunfeng.yun@mediatek.com>
   3 Date: Fri, 13 Oct 2017 17:10:46 +0800
   4 Subject: [PATCH 112/224] usb: mtu3: set otg_sel for u2port only if works as
   5  dual-role mode
   6
   7 When set otg_sel(SSUSB_U2_PORT_OTG_SEL) for u2port which supports
   8 dual-role mode, the controller will automatically switch mode
   9 between host and device according to IDDIG signal. But if the
  10 u2port only supports device mode, and no IDDIG pin is provided,
  11 setting otg_sel may cause failure of detection by host.
  12 So set it only for dual-role mode.
  13
  14 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  15 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
  16 ---
  17  drivers/usb/mtu3/mtu3_core.c | 9 +++++++--
  18  1 file changed, 7 insertions(+), 2 deletions(-)
  19
  20 --- a/drivers/usb/mtu3/mtu3_core.c
  21 +++ b/drivers/usb/mtu3/mtu3_core.c
  22 @@ -115,7 +115,9 @@ static int mtu3_device_enable(struct mtu
  23         mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
  24                 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
  25                 SSUSB_U2_PORT_HOST_SEL));
  26 -       mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
  27 +
  28 +       if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
  29 +               mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
  30
  31         return ssusb_check_clocks(mtu->ssusb, check_clk);
  32  }
  33 @@ -130,7 +132,10 @@ static void mtu3_device_disable(struct m
  34
  35         mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
  36                 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
  37 -       mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
  38 +
  39 +       if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
  40 +               mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
  41 +
  42         mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
  43  }
  44