target/linux/mediatek/patches-4.14/0218-arm64-dts-mt7622-add-ethernet-device-nodes.patch

   1 From 4fbacf244953285ac58cb833060076fafd990588 Mon Sep 17 00:00:00 2001
   2 From: Sean Wang <sean.wang@mediatek.com>
   3 Date: Fri, 29 Dec 2017 10:45:07 +0800
   4 Subject: [PATCH 218/224] arm64: dts: mt7622: add ethernet device nodes
   5
   6 add ethernet device nodes which enable GMAC1 with SGMII interface
   7
   8 Signed-off-by: Sean Wang <sean.wang@mediatek.com>
   9 ---
  10  arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 22 ++++++++++++++++++++
  11  arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 31 ++++++++++++++++++++++++++++
  12  2 files changed, 53 insertions(+)
  13
  14 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  15 +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
  16 @@ -249,6 +249,28 @@
  17         status = "okay";
  18  };
  19
  20 +&eth {
  21 +       pinctrl-names = "default";
  22 +       pinctrl-0 = <&eth_pins>;
  23 +       status = "okay";
  24 +
  25 +       gmac1: mac@1 {
  26 +               compatible = "mediatek,eth-mac";
  27 +               reg = <1>;
  28 +               phy-handle = <&phy5>;
  29 +       };
  30 +
  31 +       mdio-bus {
  32 +               #address-cells = <1>;
  33 +               #size-cells = <0>;
  34 +
  35 +               phy5: ethernet-phy@5 {
  36 +                       reg = <5>;
  37 +                       phy-mode = "sgmii";
  38 +               };
  39 +       };
  40 +};
  41 +
  42  &i2c1 {
  43         pinctrl-names = "default";
  44         pinctrl-0 = <&i2c1_pins>;
  45 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  46 +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
  47 @@ -550,6 +550,37 @@
  48                 #reset-cells = <1>;
  49         };
  50
  51 +       eth: ethernet@1b100000 {
  52 +               compatible = "mediatek,mt7622-eth",
  53 +                            "mediatek,mt2701-eth",
  54 +                            "syscon";
  55 +               reg = <0 0x1b100000 0 0x20000>;
  56 +               interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
  57 +                            <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
  58 +                            <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
  59 +               clocks = <&topckgen CLK_TOP_ETH_SEL>,
  60 +                        <&ethsys CLK_ETH_ESW_EN>,
  61 +                        <&ethsys CLK_ETH_GP0_EN>,
  62 +                        <&ethsys CLK_ETH_GP1_EN>,
  63 +                        <&ethsys CLK_ETH_GP2_EN>,
  64 +                        <&sgmiisys CLK_SGMII_TX250M_EN>,
  65 +                        <&sgmiisys CLK_SGMII_RX250M_EN>,
  66 +                        <&sgmiisys CLK_SGMII_CDR_REF>,
  67 +                        <&sgmiisys CLK_SGMII_CDR_FB>,
  68 +                        <&topckgen CLK_TOP_SGMIIPLL>,
  69 +                        <&apmixedsys CLK_APMIXED_ETH2PLL>;
  70 +               clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
  71 +                             "sgmii_tx250m", "sgmii_rx250m",
  72 +                             "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
  73 +                             "eth2pll";
  74 +               power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
  75 +               mediatek,ethsys = <&ethsys>;
  76 +               mediatek,sgmiisys = <&sgmiisys>;
  77 +               #address-cells = <1>;
  78 +               #size-cells = <0>;
  79 +               status = "disabled";
  80 +       };
  81 +
  82         sgmiisys: sgmiisys@1b128000 {
  83                 compatible = "mediatek,mt7622-sgmiisys",
  84                              "syscon";