mediatek: update patches
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0005-soc-mediatek-Add-MT2701-MT7623-scpsys-driver.patch
1 From c6711565985f359d7d3c05f01f081e4c216902de Mon Sep 17 00:00:00 2001
2 From: Shunli Wang <shunli.wang@mediatek.com>
3 Date: Wed, 30 Dec 2015 14:41:46 +0800
4 Subject: [PATCH 05/91] soc: mediatek: Add MT2701/MT7623 scpsys driver
5
6 Add scpsys driver for MT2701 and MT7623.
7
8 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
9 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
10 ---
11 drivers/soc/mediatek/Kconfig | 11 ++
12 drivers/soc/mediatek/Makefile | 1 +
13 drivers/soc/mediatek/mtk-scpsys-mt2701.c | 161 ++++++++++++++++++++++++++++++
14 3 files changed, 173 insertions(+)
15 create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt2701.c
16
17 diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
18 index eca6fb7..92cf838 100644
19 --- a/drivers/soc/mediatek/Kconfig
20 +++ b/drivers/soc/mediatek/Kconfig
21 @@ -39,3 +39,14 @@ config MTK_SCPSYS_MT8173
22 driver.
23 The System Control Processor System (SCPSYS) has several power
24 management related tasks in the system.
25 +
26 +config MTK_SCPSYS_MT2701
27 + bool "SCPSYS Support MediaTek MT2701 and MT7623"
28 + depends on ARCH_MEDIATEK || COMPILE_TEST
29 + select MTK_SCPSYS
30 + default ARCH_MEDIATEK
31 + help
32 + Say yes here to add support for the MT2701/MT7623 SCPSYS power
33 + domain driver.
34 + The System Control Processor System (SCPSYS) has several power
35 + management related tasks in the system.
36 diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
37 index 3b22baa..822986d 100644
38 --- a/drivers/soc/mediatek/Makefile
39 +++ b/drivers/soc/mediatek/Makefile
40 @@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
41 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
42 obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
43 obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
44 +obj-$(CONFIG_MTK_SCPSYS_MT2701) += mtk-scpsys-mt2701.o
45 diff --git a/drivers/soc/mediatek/mtk-scpsys-mt2701.c b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
46 new file mode 100644
47 index 0000000..339d5b8
48 --- /dev/null
49 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
50 @@ -0,0 +1,161 @@
51 +/*
52 + * Copyright (c) 2015 Mediatek, Shunli Wang <shunli.wang@mediatek.com>
53 + *
54 + * This program is free software; you can redistribute it and/or modify
55 + * it under the terms of the GNU General Public License version 2 as
56 + * published by the Free Software Foundation.
57 + *
58 + * This program is distributed in the hope that it will be useful,
59 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
60 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
61 + * GNU General Public License for more details.
62 + */
63 +#include <linux/mfd/syscon.h>
64 +#include <linux/module.h>
65 +#include <linux/of_device.h>
66 +#include <linux/pm_domain.h>
67 +#include <linux/soc/mediatek/infracfg.h>
68 +#include <dt-bindings/power/mt2701-power.h>
69 +
70 +#include "mtk-scpsys.h"
71 +
72 +#define SPM_VDE_PWR_CON 0x0210
73 +#define SPM_MFG_PWR_CON 0x0214
74 +#define SPM_ISP_PWR_CON 0x0238
75 +#define SPM_DIS_PWR_CON 0x023C
76 +#define SPM_CONN_PWR_CON 0x0280
77 +#define SPM_BDP_PWR_CON 0x029C
78 +#define SPM_ETH_PWR_CON 0x02A0
79 +#define SPM_HIF_PWR_CON 0x02A4
80 +#define SPM_IFR_MSC_PWR_CON 0x02A8
81 +#define SPM_PWR_STATUS 0x060c
82 +#define SPM_PWR_STATUS_2ND 0x0610
83 +
84 +#define CONN_PWR_STA_MASK BIT(1)
85 +#define DIS_PWR_STA_MASK BIT(3)
86 +#define MFG_PWR_STA_MASK BIT(4)
87 +#define ISP_PWR_STA_MASK BIT(5)
88 +#define VDE_PWR_STA_MASK BIT(7)
89 +#define BDP_PWR_STA_MASK BIT(14)
90 +#define ETH_PWR_STA_MASK BIT(15)
91 +#define HIF_PWR_STA_MASK BIT(16)
92 +#define IFR_MSC_PWR_STA_MASK BIT(17)
93 +
94 +#define MT2701_TOP_AXI_PROT_EN_CONN 0x0104
95 +#define MT2701_TOP_AXI_PROT_EN_DISP 0x0002
96 +
97 +static const struct scp_domain_data scp_domain_data[] = {
98 + [MT2701_POWER_DOMAIN_CONN] = {
99 + .name = "conn",
100 + .sta_mask = CONN_PWR_STA_MASK,
101 + .ctl_offs = SPM_CONN_PWR_CON,
102 + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN,
103 + .active_wakeup = true,
104 + },
105 + [MT2701_POWER_DOMAIN_DISP] = {
106 + .name = "disp",
107 + .sta_mask = DIS_PWR_STA_MASK,
108 + .ctl_offs = SPM_DIS_PWR_CON,
109 + .sram_pdn_bits = GENMASK(11, 8),
110 + .clk_id = {CLK_MM},
111 + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_DISP,
112 + .active_wakeup = true,
113 + },
114 + [MT2701_POWER_DOMAIN_MFG] = {
115 + .name = "mfg",
116 + .sta_mask = MFG_PWR_STA_MASK,
117 + .ctl_offs = SPM_MFG_PWR_CON,
118 + .sram_pdn_bits = GENMASK(11, 8),
119 + .sram_pdn_ack_bits = GENMASK(12, 12),
120 + .active_wakeup = true,
121 + },
122 + [MT2701_POWER_DOMAIN_VDEC] = {
123 + .name = "vdec",
124 + .sta_mask = VDE_PWR_STA_MASK,
125 + .ctl_offs = SPM_VDE_PWR_CON,
126 + .sram_pdn_bits = GENMASK(11, 8),
127 + .sram_pdn_ack_bits = GENMASK(12, 12),
128 + .clk_id = {CLK_MM},
129 + .active_wakeup = true,
130 + },
131 + [MT2701_POWER_DOMAIN_ISP] = {
132 + .name = "isp",
133 + .sta_mask = ISP_PWR_STA_MASK,
134 + .ctl_offs = SPM_ISP_PWR_CON,
135 + .sram_pdn_bits = GENMASK(11, 8),
136 + .sram_pdn_ack_bits = GENMASK(13, 12),
137 + .active_wakeup = true,
138 + },
139 + [MT2701_POWER_DOMAIN_BDP] = {
140 + .name = "bdp",
141 + .sta_mask = BDP_PWR_STA_MASK,
142 + .ctl_offs = SPM_BDP_PWR_CON,
143 + .sram_pdn_bits = GENMASK(11, 8),
144 + .active_wakeup = true,
145 + },
146 + [MT2701_POWER_DOMAIN_ETH] = {
147 + .name = "eth",
148 + .sta_mask = ETH_PWR_STA_MASK,
149 + .ctl_offs = SPM_ETH_PWR_CON,
150 + .sram_pdn_bits = GENMASK(11, 8),
151 + .sram_pdn_ack_bits = GENMASK(15, 12),
152 + .active_wakeup = true,
153 + },
154 + [MT2701_POWER_DOMAIN_HIF] = {
155 + .name = "hif",
156 + .sta_mask = HIF_PWR_STA_MASK,
157 + .ctl_offs = SPM_HIF_PWR_CON,
158 + .sram_pdn_bits = GENMASK(11, 8),
159 + .sram_pdn_ack_bits = GENMASK(15, 12),
160 + .active_wakeup = true,
161 + },
162 + [MT2701_POWER_DOMAIN_IFR_MSC] = {
163 + .name = "ifr_msc",
164 + .sta_mask = IFR_MSC_PWR_STA_MASK,
165 + .ctl_offs = SPM_IFR_MSC_PWR_CON,
166 + .active_wakeup = true,
167 + },
168 +};
169 +
170 +#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
171 +
172 +static int __init scpsys_probe(struct platform_device *pdev)
173 +{
174 + struct scp *scp;
175 +
176 + scp = init_scp(pdev, scp_domain_data, NUM_DOMAINS);
177 + if (IS_ERR(scp))
178 + return PTR_ERR(scp);
179 +
180 + mtk_register_power_domains(pdev, scp, NUM_DOMAINS);
181 +
182 + return 0;
183 +}
184 +
185 +static const struct of_device_id of_scpsys_match_tbl[] = {
186 + {
187 + .compatible = "mediatek,mt2701-scpsys",
188 + }, {
189 + /* sentinel */
190 + }
191 +};
192 +MODULE_DEVICE_TABLE(of, of_scpsys_match_tbl);
193 +
194 +static struct platform_driver scpsys_drv = {
195 + .driver = {
196 + .name = "mtk-scpsys-mt2701",
197 + .owner = THIS_MODULE,
198 + .of_match_table = of_match_ptr(of_scpsys_match_tbl),
199 + },
200 + .probe = scpsys_probe,
201 +};
202 +
203 +static int __init scpsys_init(void)
204 +{
205 + return platform_driver_register(&scpsys_drv);
206 +}
207 +
208 +subsys_initcall(scpsys_init);
209 +
210 +MODULE_DESCRIPTION("MediaTek MT2701 scpsys driver");
211 +MODULE_LICENSE("GPL v2");
212 --
213 1.7.10.4
214