4a6d5231b2edc6e0b86f5bd5af786059484ec851
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0005-soc-mediatek-Add-MT2701-MT7623-scpsys-driver.patch
1 From c6711565985f359d7d3c05f01f081e4c216902de Mon Sep 17 00:00:00 2001
2 From: Shunli Wang <shunli.wang@mediatek.com>
3 Date: Wed, 30 Dec 2015 14:41:46 +0800
4 Subject: [PATCH 05/81] soc: mediatek: Add MT2701/MT7623 scpsys driver
5
6 Add scpsys driver for MT2701 and MT7623.
7
8 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
9 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
10 ---
11 drivers/soc/mediatek/Kconfig | 11 ++
12 drivers/soc/mediatek/Makefile | 1 +
13 drivers/soc/mediatek/mtk-scpsys-mt2701.c | 161 ++++++++++++++++++++++++++++++
14 3 files changed, 173 insertions(+)
15 create mode 100644 drivers/soc/mediatek/mtk-scpsys-mt2701.c
16
17 --- a/drivers/soc/mediatek/Kconfig
18 +++ b/drivers/soc/mediatek/Kconfig
19 @@ -39,3 +39,14 @@ config MTK_SCPSYS_MT8173
20 driver.
21 The System Control Processor System (SCPSYS) has several power
22 management related tasks in the system.
23 +
24 +config MTK_SCPSYS_MT2701
25 + bool "SCPSYS Support MediaTek MT2701 and MT7623"
26 + depends on ARCH_MEDIATEK || COMPILE_TEST
27 + select MTK_SCPSYS
28 + default ARCH_MEDIATEK
29 + help
30 + Say yes here to add support for the MT2701/MT7623 SCPSYS power
31 + domain driver.
32 + The System Control Processor System (SCPSYS) has several power
33 + management related tasks in the system.
34 --- a/drivers/soc/mediatek/Makefile
35 +++ b/drivers/soc/mediatek/Makefile
36 @@ -2,3 +2,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infrac
37 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
38 obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
39 obj-$(CONFIG_MTK_SCPSYS_MT8173) += mtk-scpsys-mt8173.o
40 +obj-$(CONFIG_MTK_SCPSYS_MT2701) += mtk-scpsys-mt2701.o
41 --- /dev/null
42 +++ b/drivers/soc/mediatek/mtk-scpsys-mt2701.c
43 @@ -0,0 +1,161 @@
44 +/*
45 + * Copyright (c) 2015 Mediatek, Shunli Wang <shunli.wang@mediatek.com>
46 + *
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License version 2 as
49 + * published by the Free Software Foundation.
50 + *
51 + * This program is distributed in the hope that it will be useful,
52 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
53 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
54 + * GNU General Public License for more details.
55 + */
56 +#include <linux/mfd/syscon.h>
57 +#include <linux/module.h>
58 +#include <linux/of_device.h>
59 +#include <linux/pm_domain.h>
60 +#include <linux/soc/mediatek/infracfg.h>
61 +#include <dt-bindings/power/mt2701-power.h>
62 +
63 +#include "mtk-scpsys.h"
64 +
65 +#define SPM_VDE_PWR_CON 0x0210
66 +#define SPM_MFG_PWR_CON 0x0214
67 +#define SPM_ISP_PWR_CON 0x0238
68 +#define SPM_DIS_PWR_CON 0x023C
69 +#define SPM_CONN_PWR_CON 0x0280
70 +#define SPM_BDP_PWR_CON 0x029C
71 +#define SPM_ETH_PWR_CON 0x02A0
72 +#define SPM_HIF_PWR_CON 0x02A4
73 +#define SPM_IFR_MSC_PWR_CON 0x02A8
74 +#define SPM_PWR_STATUS 0x060c
75 +#define SPM_PWR_STATUS_2ND 0x0610
76 +
77 +#define CONN_PWR_STA_MASK BIT(1)
78 +#define DIS_PWR_STA_MASK BIT(3)
79 +#define MFG_PWR_STA_MASK BIT(4)
80 +#define ISP_PWR_STA_MASK BIT(5)
81 +#define VDE_PWR_STA_MASK BIT(7)
82 +#define BDP_PWR_STA_MASK BIT(14)
83 +#define ETH_PWR_STA_MASK BIT(15)
84 +#define HIF_PWR_STA_MASK BIT(16)
85 +#define IFR_MSC_PWR_STA_MASK BIT(17)
86 +
87 +#define MT2701_TOP_AXI_PROT_EN_CONN 0x0104
88 +#define MT2701_TOP_AXI_PROT_EN_DISP 0x0002
89 +
90 +static const struct scp_domain_data scp_domain_data[] = {
91 + [MT2701_POWER_DOMAIN_CONN] = {
92 + .name = "conn",
93 + .sta_mask = CONN_PWR_STA_MASK,
94 + .ctl_offs = SPM_CONN_PWR_CON,
95 + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN,
96 + .active_wakeup = true,
97 + },
98 + [MT2701_POWER_DOMAIN_DISP] = {
99 + .name = "disp",
100 + .sta_mask = DIS_PWR_STA_MASK,
101 + .ctl_offs = SPM_DIS_PWR_CON,
102 + .sram_pdn_bits = GENMASK(11, 8),
103 + .clk_id = {CLK_MM},
104 + .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_DISP,
105 + .active_wakeup = true,
106 + },
107 + [MT2701_POWER_DOMAIN_MFG] = {
108 + .name = "mfg",
109 + .sta_mask = MFG_PWR_STA_MASK,
110 + .ctl_offs = SPM_MFG_PWR_CON,
111 + .sram_pdn_bits = GENMASK(11, 8),
112 + .sram_pdn_ack_bits = GENMASK(12, 12),
113 + .active_wakeup = true,
114 + },
115 + [MT2701_POWER_DOMAIN_VDEC] = {
116 + .name = "vdec",
117 + .sta_mask = VDE_PWR_STA_MASK,
118 + .ctl_offs = SPM_VDE_PWR_CON,
119 + .sram_pdn_bits = GENMASK(11, 8),
120 + .sram_pdn_ack_bits = GENMASK(12, 12),
121 + .clk_id = {CLK_MM},
122 + .active_wakeup = true,
123 + },
124 + [MT2701_POWER_DOMAIN_ISP] = {
125 + .name = "isp",
126 + .sta_mask = ISP_PWR_STA_MASK,
127 + .ctl_offs = SPM_ISP_PWR_CON,
128 + .sram_pdn_bits = GENMASK(11, 8),
129 + .sram_pdn_ack_bits = GENMASK(13, 12),
130 + .active_wakeup = true,
131 + },
132 + [MT2701_POWER_DOMAIN_BDP] = {
133 + .name = "bdp",
134 + .sta_mask = BDP_PWR_STA_MASK,
135 + .ctl_offs = SPM_BDP_PWR_CON,
136 + .sram_pdn_bits = GENMASK(11, 8),
137 + .active_wakeup = true,
138 + },
139 + [MT2701_POWER_DOMAIN_ETH] = {
140 + .name = "eth",
141 + .sta_mask = ETH_PWR_STA_MASK,
142 + .ctl_offs = SPM_ETH_PWR_CON,
143 + .sram_pdn_bits = GENMASK(11, 8),
144 + .sram_pdn_ack_bits = GENMASK(15, 12),
145 + .active_wakeup = true,
146 + },
147 + [MT2701_POWER_DOMAIN_HIF] = {
148 + .name = "hif",
149 + .sta_mask = HIF_PWR_STA_MASK,
150 + .ctl_offs = SPM_HIF_PWR_CON,
151 + .sram_pdn_bits = GENMASK(11, 8),
152 + .sram_pdn_ack_bits = GENMASK(15, 12),
153 + .active_wakeup = true,
154 + },
155 + [MT2701_POWER_DOMAIN_IFR_MSC] = {
156 + .name = "ifr_msc",
157 + .sta_mask = IFR_MSC_PWR_STA_MASK,
158 + .ctl_offs = SPM_IFR_MSC_PWR_CON,
159 + .active_wakeup = true,
160 + },
161 +};
162 +
163 +#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
164 +
165 +static int __init scpsys_probe(struct platform_device *pdev)
166 +{
167 + struct scp *scp;
168 +
169 + scp = init_scp(pdev, scp_domain_data, NUM_DOMAINS);
170 + if (IS_ERR(scp))
171 + return PTR_ERR(scp);
172 +
173 + mtk_register_power_domains(pdev, scp, NUM_DOMAINS);
174 +
175 + return 0;
176 +}
177 +
178 +static const struct of_device_id of_scpsys_match_tbl[] = {
179 + {
180 + .compatible = "mediatek,mt2701-scpsys",
181 + }, {
182 + /* sentinel */
183 + }
184 +};
185 +MODULE_DEVICE_TABLE(of, of_scpsys_match_tbl);
186 +
187 +static struct platform_driver scpsys_drv = {
188 + .driver = {
189 + .name = "mtk-scpsys-mt2701",
190 + .owner = THIS_MODULE,
191 + .of_match_table = of_match_ptr(of_scpsys_match_tbl),
192 + },
193 + .probe = scpsys_probe,
194 +};
195 +
196 +static int __init scpsys_init(void)
197 +{
198 + return platform_driver_register(&scpsys_drv);
199 +}
200 +
201 +subsys_initcall(scpsys_init);
202 +
203 +MODULE_DESCRIPTION("MediaTek MT2701 scpsys driver");
204 +MODULE_LICENSE("GPL v2");