81f5048b45f064d8f0ee75e3ae00acb778246a3e
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0008-clk-mediatek-Add-dt-bindings-for-MT2701-clocks.patch
1 From 2fcbc15da2f13164e0851b9c7fae290249f0b44d Mon Sep 17 00:00:00 2001
2 From: Shunli Wang <shunli.wang@mediatek.com>
3 Date: Tue, 5 Jan 2016 14:30:19 +0800
4 Subject: [PATCH 08/81] clk: mediatek: Add dt-bindings for MT2701 clocks
5
6 Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
7 infracfg, pericfg and subsystem clocks.
8
9 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
10 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
11 ---
12 include/dt-bindings/clock/mt2701-clk.h | 481 ++++++++++++++++++++++++++++++++
13 1 file changed, 481 insertions(+)
14 create mode 100644 include/dt-bindings/clock/mt2701-clk.h
15
16 --- /dev/null
17 +++ b/include/dt-bindings/clock/mt2701-clk.h
18 @@ -0,0 +1,481 @@
19 +/*
20 + * Copyright (c) 2014 MediaTek Inc.
21 + * Author: Shunli Wang <shunli.wang@mediatek.com>
22 + *
23 + * This program is free software; you can redistribute it and/or modify
24 + * it under the terms of the GNU General Public License version 2 as
25 + * published by the Free Software Foundation.
26 + *
27 + * This program is distributed in the hope that it will be useful,
28 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 + * GNU General Public License for more details.
31 + */
32 +
33 +#ifndef _DT_BINDINGS_CLK_MT2701_H
34 +#define _DT_BINDINGS_CLK_MT2701_H
35 +
36 +/* TOPCKGEN */
37 +#define CLK_TOP_SYSPLL 1
38 +#define CLK_TOP_SYSPLL_D2 2
39 +#define CLK_TOP_SYSPLL_D3 3
40 +#define CLK_TOP_SYSPLL_D5 4
41 +#define CLK_TOP_SYSPLL_D7 5
42 +#define CLK_TOP_SYSPLL1_D2 6
43 +#define CLK_TOP_SYSPLL1_D4 7
44 +#define CLK_TOP_SYSPLL1_D8 8
45 +#define CLK_TOP_SYSPLL1_D16 9
46 +#define CLK_TOP_SYSPLL2_D2 10
47 +#define CLK_TOP_SYSPLL2_D4 11
48 +#define CLK_TOP_SYSPLL2_D8 12
49 +#define CLK_TOP_SYSPLL3_D2 13
50 +#define CLK_TOP_SYSPLL3_D4 14
51 +#define CLK_TOP_SYSPLL4_D2 15
52 +#define CLK_TOP_SYSPLL4_D4 16
53 +#define CLK_TOP_UNIVPLL 17
54 +#define CLK_TOP_UNIVPLL_D2 18
55 +#define CLK_TOP_UNIVPLL_D3 19
56 +#define CLK_TOP_UNIVPLL_D5 20
57 +#define CLK_TOP_UNIVPLL_D7 21
58 +#define CLK_TOP_UNIVPLL_D26 22
59 +#define CLK_TOP_UNIVPLL_D52 23
60 +#define CLK_TOP_UNIVPLL_D108 24
61 +#define CLK_TOP_USB_PHY48M 25
62 +#define CLK_TOP_UNIVPLL1_D2 26
63 +#define CLK_TOP_UNIVPLL1_D4 27
64 +#define CLK_TOP_UNIVPLL1_D8 28
65 +#define CLK_TOP_UNIVPLL2_D2 29
66 +#define CLK_TOP_UNIVPLL2_D4 30
67 +#define CLK_TOP_UNIVPLL2_D8 31
68 +#define CLK_TOP_UNIVPLL2_D16 32
69 +#define CLK_TOP_UNIVPLL2_D32 33
70 +#define CLK_TOP_UNIVPLL3_D2 34
71 +#define CLK_TOP_UNIVPLL3_D4 35
72 +#define CLK_TOP_UNIVPLL3_D8 36
73 +#define CLK_TOP_MSDCPLL 37
74 +#define CLK_TOP_MSDCPLL_D2 38
75 +#define CLK_TOP_MSDCPLL_D4 39
76 +#define CLK_TOP_MSDCPLL_D8 40
77 +#define CLK_TOP_MMPLL 41
78 +#define CLK_TOP_MMPLL_D2 42
79 +#define CLK_TOP_DMPLL 43
80 +#define CLK_TOP_DMPLL_D2 44
81 +#define CLK_TOP_DMPLL_D4 45
82 +#define CLK_TOP_DMPLL_X2 46
83 +#define CLK_TOP_TVDPLL 47
84 +#define CLK_TOP_TVDPLL_D2 48
85 +#define CLK_TOP_TVDPLL_D4 49
86 +#define CLK_TOP_TVD2PLL 50
87 +#define CLK_TOP_TVD2PLL_D2 51
88 +#define CLK_TOP_HADDS2PLL_98M 52
89 +#define CLK_TOP_HADDS2PLL_294M 53
90 +#define CLK_TOP_HADDS2_FB 54
91 +#define CLK_TOP_MIPIPLL_D2 55
92 +#define CLK_TOP_MIPIPLL_D4 56
93 +#define CLK_TOP_HDMIPLL 57
94 +#define CLK_TOP_HDMIPLL_D2 58
95 +#define CLK_TOP_HDMIPLL_D3 59
96 +#define CLK_TOP_HDMI_SCL_RX 60
97 +#define CLK_TOP_HDMI_0_PIX340M 61
98 +#define CLK_TOP_HDMI_0_DEEP340M 62
99 +#define CLK_TOP_HDMI_0_PLL340M 63
100 +#define CLK_TOP_AUD1PLL_98M 64
101 +#define CLK_TOP_AUD2PLL_90M 65
102 +#define CLK_TOP_AUDPLL 66
103 +#define CLK_TOP_AUDPLL_D4 67
104 +#define CLK_TOP_AUDPLL_D8 68
105 +#define CLK_TOP_AUDPLL_D16 69
106 +#define CLK_TOP_AUDPLL_D24 70
107 +#define CLK_TOP_ETHPLL_500M 71
108 +#define CLK_TOP_VDECPLL 72
109 +#define CLK_TOP_VENCPLL 73
110 +#define CLK_TOP_MIPIPLL 74
111 +#define CLK_TOP_ARMPLL_1P3G 75
112 +
113 +#define CLK_TOP_MM_SEL 76
114 +#define CLK_TOP_DDRPHYCFG_SEL 77
115 +#define CLK_TOP_MEM_SEL 78
116 +#define CLK_TOP_AXI_SEL 79
117 +#define CLK_TOP_CAMTG_SEL 80
118 +#define CLK_TOP_MFG_SEL 81
119 +#define CLK_TOP_VDEC_SEL 82
120 +#define CLK_TOP_PWM_SEL 83
121 +#define CLK_TOP_MSDC30_0_SEL 84
122 +#define CLK_TOP_USB20_SEL 85
123 +#define CLK_TOP_SPI0_SEL 86
124 +#define CLK_TOP_UART_SEL 87
125 +#define CLK_TOP_AUDINTBUS_SEL 88
126 +#define CLK_TOP_AUDIO_SEL 89
127 +#define CLK_TOP_MSDC30_2_SEL 90
128 +#define CLK_TOP_MSDC30_1_SEL 91
129 +#define CLK_TOP_DPI1_SEL 92
130 +#define CLK_TOP_DPI0_SEL 93
131 +#define CLK_TOP_SCP_SEL 94
132 +#define CLK_TOP_PMICSPI_SEL 95
133 +#define CLK_TOP_APLL_SEL 96
134 +#define CLK_TOP_HDMI_SEL 97
135 +#define CLK_TOP_TVE_SEL 98
136 +#define CLK_TOP_EMMC_HCLK_SEL 99
137 +#define CLK_TOP_NFI2X_SEL 100
138 +#define CLK_TOP_RTC_SEL 101
139 +#define CLK_TOP_OSD_SEL 102
140 +#define CLK_TOP_NR_SEL 103
141 +#define CLK_TOP_DI_SEL 104
142 +#define CLK_TOP_FLASH_SEL 105
143 +#define CLK_TOP_ASM_M_SEL 106
144 +#define CLK_TOP_ASM_I_SEL 107
145 +#define CLK_TOP_INTDIR_SEL 108
146 +#define CLK_TOP_HDMIRX_BIST_SEL 109
147 +#define CLK_TOP_ETHIF_SEL 110
148 +#define CLK_TOP_MS_CARD_SEL 111
149 +#define CLK_TOP_ASM_H_SEL 112
150 +#define CLK_TOP_SPI1_SEL 113
151 +#define CLK_TOP_CMSYS_SEL 114
152 +#define CLK_TOP_MSDC30_3_SEL 115
153 +#define CLK_TOP_HDMIRX26_24_SEL 116
154 +#define CLK_TOP_AUD2DVD_SEL 117
155 +#define CLK_TOP_8BDAC_SEL 118
156 +#define CLK_TOP_SPI2_SEL 119
157 +#define CLK_TOP_AUD_MUX1_SEL 120
158 +#define CLK_TOP_AUD_MUX2_SEL 121
159 +#define CLK_TOP_AUDPLL_MUX_SEL 122
160 +#define CLK_TOP_AUD_K1_SRC_SEL 123
161 +#define CLK_TOP_AUD_K2_SRC_SEL 124
162 +#define CLK_TOP_AUD_K3_SRC_SEL 125
163 +#define CLK_TOP_AUD_K4_SRC_SEL 126
164 +#define CLK_TOP_AUD_K5_SRC_SEL 127
165 +#define CLK_TOP_AUD_K6_SRC_SEL 128
166 +#define CLK_TOP_PADMCLK_SEL 129
167 +#define CLK_TOP_AUD_EXTCK1_DIV 130
168 +#define CLK_TOP_AUD_EXTCK2_DIV 131
169 +#define CLK_TOP_AUD_MUX1_DIV 132
170 +#define CLK_TOP_AUD_MUX2_DIV 133
171 +#define CLK_TOP_AUD_K1_SRC_DIV 134
172 +#define CLK_TOP_AUD_K2_SRC_DIV 135
173 +#define CLK_TOP_AUD_K3_SRC_DIV 136
174 +#define CLK_TOP_AUD_K4_SRC_DIV 137
175 +#define CLK_TOP_AUD_K5_SRC_DIV 138
176 +#define CLK_TOP_AUD_K6_SRC_DIV 139
177 +#define CLK_TOP_AUD_I2S1_MCLK 140
178 +#define CLK_TOP_AUD_I2S2_MCLK 141
179 +#define CLK_TOP_AUD_I2S3_MCLK 142
180 +#define CLK_TOP_AUD_I2S4_MCLK 143
181 +#define CLK_TOP_AUD_I2S5_MCLK 144
182 +#define CLK_TOP_AUD_I2S6_MCLK 145
183 +#define CLK_TOP_AUD_48K_TIMING 146
184 +#define CLK_TOP_AUD_44K_TIMING 147
185 +
186 +#define CLK_TOP_32K_INTERNAL 148
187 +#define CLK_TOP_32K_EXTERNAL 149
188 +#define CLK_TOP_CLK26M_D8 150
189 +#define CLK_TOP_8BDAC 151
190 +#define CLK_TOP_WBG_DIG_416M 152
191 +#define CLK_TOP_DPI 153
192 +#define CLK_TOP_HDMITX_CLKDIG_CTS 154
193 +#define CLK_TOP_NR 155
194 +
195 +/* APMIXEDSYS */
196 +
197 +#define CLK_APMIXED_ARMPLL 1
198 +#define CLK_APMIXED_MAINPLL 2
199 +#define CLK_APMIXED_UNIVPLL 3
200 +#define CLK_APMIXED_MMPLL 4
201 +#define CLK_APMIXED_MSDCPLL 5
202 +#define CLK_APMIXED_TVDPLL 6
203 +#define CLK_APMIXED_AUD1PLL 7
204 +#define CLK_APMIXED_TRGPLL 8
205 +#define CLK_APMIXED_ETHPLL 9
206 +#define CLK_APMIXED_VDECPLL 10
207 +#define CLK_APMIXED_HADDS2PLL 11
208 +#define CLK_APMIXED_AUD2PLL 12
209 +#define CLK_APMIXED_TVD2PLL 13
210 +#define CLK_APMIXED_NR 14
211 +
212 +/* DDRPHY */
213 +
214 +#define CLK_DDRPHY_VENCPLL 1
215 +#define CLK_DDRPHY_NR 2
216 +
217 +/* INFRACFG */
218 +
219 +#define CLK_INFRA_DBG 1
220 +#define CLK_INFRA_SMI 2
221 +#define CLK_INFRA_QAXI_CM4 3
222 +#define CLK_INFRA_AUD_SPLIN_B 4
223 +#define CLK_INFRA_AUDIO 5
224 +#define CLK_INFRA_EFUSE 6
225 +#define CLK_INFRA_L2C_SRAM 7
226 +#define CLK_INFRA_M4U 8
227 +#define CLK_INFRA_CONNMCU 9
228 +#define CLK_INFRA_TRNG 10
229 +#define CLK_INFRA_RAMBUFIF 11
230 +#define CLK_INFRA_CPUM 12
231 +#define CLK_INFRA_KP 13
232 +#define CLK_INFRA_CEC 14
233 +#define CLK_INFRA_IRRX 15
234 +#define CLK_INFRA_PMICSPI 16
235 +#define CLK_INFRA_PMICWRAP 17
236 +#define CLK_INFRA_DDCCI 18
237 +#define CLK_INFRA_CLK_13M 19
238 +#define CLK_INFRA_NR 20
239 +
240 +/* PERICFG */
241 +
242 +#define CLK_PERI_NFI 1
243 +#define CLK_PERI_THERM 2
244 +#define CLK_PERI_PWM1 3
245 +#define CLK_PERI_PWM2 4
246 +#define CLK_PERI_PWM3 5
247 +#define CLK_PERI_PWM4 6
248 +#define CLK_PERI_PWM5 7
249 +#define CLK_PERI_PWM6 8
250 +#define CLK_PERI_PWM7 9
251 +#define CLK_PERI_PWM 10
252 +#define CLK_PERI_USB0 11
253 +#define CLK_PERI_USB1 12
254 +#define CLK_PERI_AP_DMA 13
255 +#define CLK_PERI_MSDC30_0 14
256 +#define CLK_PERI_MSDC30_1 15
257 +#define CLK_PERI_MSDC30_2 16
258 +#define CLK_PERI_MSDC30_3 17
259 +#define CLK_PERI_MSDC50_3 18
260 +#define CLK_PERI_NLI 19
261 +#define CLK_PERI_UART0 20
262 +#define CLK_PERI_UART1 21
263 +#define CLK_PERI_UART2 22
264 +#define CLK_PERI_UART3 23
265 +#define CLK_PERI_BTIF 24
266 +#define CLK_PERI_I2C0 25
267 +#define CLK_PERI_I2C1 26
268 +#define CLK_PERI_I2C2 27
269 +#define CLK_PERI_I2C3 28
270 +#define CLK_PERI_AUXADC 29
271 +#define CLK_PERI_SPI0 30
272 +#define CLK_PERI_ETH 31
273 +#define CLK_PERI_USB0_MCU 32
274 +
275 +#define CLK_PERI_USB1_MCU 33
276 +#define CLK_PERI_USB_SLV 34
277 +#define CLK_PERI_GCPU 35
278 +#define CLK_PERI_NFI_ECC 36
279 +#define CLK_PERI_NFI_PAD 37
280 +#define CLK_PERI_FLASH 38
281 +#define CLK_PERI_HOST89_INT 39
282 +#define CLK_PERI_HOST89_SPI 40
283 +#define CLK_PERI_HOST89_DVD 41
284 +#define CLK_PERI_SPI1 42
285 +#define CLK_PERI_SPI2 43
286 +#define CLK_PERI_FCI 44
287 +
288 +#define CLK_PERI_UART0_SEL 45
289 +#define CLK_PERI_UART1_SEL 46
290 +#define CLK_PERI_UART2_SEL 47
291 +#define CLK_PERI_UART3_SEL 48
292 +#define CLK_PERI_NR 49
293 +
294 +/* AUDIO */
295 +
296 +#define CLK_AUD_AFE 1
297 +#define CLK_AUD_LRCK_DETECT 2
298 +#define CLK_AUD_I2S 3
299 +#define CLK_AUD_APLL_TUNER 4
300 +#define CLK_AUD_HDMI 5
301 +#define CLK_AUD_SPDF 6
302 +#define CLK_AUD_SPDF2 7
303 +#define CLK_AUD_APLL 8
304 +#define CLK_AUD_TML 9
305 +#define CLK_AUD_AHB_IDLE_EXT 10
306 +#define CLK_AUD_AHB_IDLE_INT 11
307 +
308 +#define CLK_AUD_I2SIN1 12
309 +#define CLK_AUD_I2SIN2 13
310 +#define CLK_AUD_I2SIN3 14
311 +#define CLK_AUD_I2SIN4 15
312 +#define CLK_AUD_I2SIN5 16
313 +#define CLK_AUD_I2SIN6 17
314 +#define CLK_AUD_I2SO1 18
315 +#define CLK_AUD_I2SO2 19
316 +#define CLK_AUD_I2SO3 20
317 +#define CLK_AUD_I2SO4 21
318 +#define CLK_AUD_I2SO5 22
319 +#define CLK_AUD_I2SO6 23
320 +#define CLK_AUD_ASRCI1 24
321 +#define CLK_AUD_ASRCI2 25
322 +#define CLK_AUD_ASRCO1 26
323 +#define CLK_AUD_ASRCO2 27
324 +#define CLK_AUD_ASRC11 28
325 +#define CLK_AUD_ASRC12 29
326 +#define CLK_AUD_HDMIRX 30
327 +#define CLK_AUD_INTDIR 31
328 +#define CLK_AUD_A1SYS 32
329 +#define CLK_AUD_A2SYS 33
330 +#define CLK_AUD_AFE_CONN 34
331 +#define CLK_AUD_AFE_PCMIF 35
332 +#define CLK_AUD_AFE_MRGIF 36
333 +
334 +#define CLK_AUD_MMIF_UL1 37
335 +#define CLK_AUD_MMIF_UL2 38
336 +#define CLK_AUD_MMIF_UL3 39
337 +#define CLK_AUD_MMIF_UL4 40
338 +#define CLK_AUD_MMIF_UL5 41
339 +#define CLK_AUD_MMIF_UL6 42
340 +#define CLK_AUD_MMIF_DL1 43
341 +#define CLK_AUD_MMIF_DL2 44
342 +#define CLK_AUD_MMIF_DL3 45
343 +#define CLK_AUD_MMIF_DL4 46
344 +#define CLK_AUD_MMIF_DL5 47
345 +#define CLK_AUD_MMIF_DL6 48
346 +#define CLK_AUD_MMIF_DLMCH 49
347 +#define CLK_AUD_MMIF_ARB1 50
348 +#define CLK_AUD_MMIF_AWB1 51
349 +#define CLK_AUD_MMIF_AWB2 52
350 +#define CLK_AUD_MMIF_DAI 53
351 +
352 +#define CLK_AUD_DMIC1 54
353 +#define CLK_AUD_DMIC2 55
354 +#define CLK_AUD_ASRCI3 56
355 +#define CLK_AUD_ASRCI4 57
356 +#define CLK_AUD_ASRCI5 58
357 +#define CLK_AUD_ASRCI6 59
358 +#define CLK_AUD_ASRCO3 60
359 +#define CLK_AUD_ASRCO4 61
360 +#define CLK_AUD_ASRCO5 62
361 +#define CLK_AUD_ASRCO6 63
362 +#define CLK_AUD_MEM_ASRC1 64
363 +#define CLK_AUD_MEM_ASRC2 65
364 +#define CLK_AUD_MEM_ASRC3 66
365 +#define CLK_AUD_MEM_ASRC4 67
366 +#define CLK_AUD_MEM_ASRC5 68
367 +#define CLK_AUD_DSD_ENC 69
368 +#define CLK_AUD_ASRC_BRG 70
369 +#define CLK_AUD_NR 71
370 +
371 +/* MMSYS */
372 +
373 +#define CLK_MM_SMI_COMMON 1
374 +#define CLK_MM_SMI_LARB0 2
375 +#define CLK_MM_CMDQ 3
376 +#define CLK_MM_MUTEX 4
377 +#define CLK_MM_DISP_COLOR 5
378 +#define CLK_MM_DISP_BLS 6
379 +#define CLK_MM_DISP_WDMA 7
380 +#define CLK_MM_DISP_RDMA 8
381 +#define CLK_MM_DISP_OVL 9
382 +#define CLK_MM_MDP_TDSHP 10
383 +#define CLK_MM_MDP_WROT 11
384 +#define CLK_MM_MDP_WDMA 12
385 +#define CLK_MM_MDP_RSZ1 13
386 +#define CLK_MM_MDP_RSZ0 14
387 +#define CLK_MM_MDP_RDMA 15
388 +#define CLK_MM_MDP_BLS_26M 16
389 +#define CLK_MM_CAM_MDP 17
390 +#define CLK_MM_FAKE_ENG 18
391 +#define CLK_MM_MUTEX_32K 19
392 +#define CLK_MM_DISP_RDMA1 20
393 +#define CLK_MM_DISP_UFOE 21
394 +
395 +#define CLK_MM_DSI_ENGINE 22
396 +#define CLK_MM_DSI_DIG 23
397 +#define CLK_MM_DPI_DIGL 24
398 +#define CLK_MM_DPI_ENGINE 25
399 +#define CLK_MM_DPI1_DIGL 26
400 +#define CLK_MM_DPI1_ENGINE 27
401 +#define CLK_MM_TVE_OUTPUT 28
402 +#define CLK_MM_TVE_INPUT 29
403 +#define CLK_MM_HDMI_PIXEL 30
404 +#define CLK_MM_HDMI_PLL 31
405 +#define CLK_MM_HDMI_AUDIO 32
406 +#define CLK_MM_HDMI_SPDIF 33
407 +#define CLK_MM_TVE_FMM 34
408 +#define CLK_MM_NR 35
409 +
410 +/* IMGSYS */
411 +
412 +#define CLK_IMG_SMI_COMM 1
413 +#define CLK_IMG_RESZ 2
414 +#define CLK_IMG_JPGDEC 3
415 +#define CLK_IMG_VENC_LT 4
416 +#define CLK_IMG_VENC 5
417 +#define CLK_IMG_NR 6
418 +
419 +/* VDEC */
420 +
421 +#define CLK_VDEC_CKGEN 1
422 +#define CLK_VDEC_LARB 2
423 +#define CLK_VDEC_NR 3
424 +
425 +/* HIFSYS */
426 +
427 +#define CLK_HIFSYS_USB0PHY 1
428 +#define CLK_HIFSYS_USB1PHY 2
429 +#define CLK_HIFSYS_PCIE0 3
430 +#define CLK_HIFSYS_PCIE1 4
431 +#define CLK_HIFSYS_PCIE2 5
432 +#define CLK_HIFSYS_NR 6
433 +
434 +/* ETHSYS */
435 +#define CLK_ETHSYS_HSDMA 1
436 +#define CLK_ETHSYS_ESW 2
437 +#define CLK_ETHSYS_GP2 3
438 +#define CLK_ETHSYS_GP1 4
439 +#define CLK_ETHSYS_PCM 5
440 +#define CLK_ETHSYS_GDMA 6
441 +#define CLK_ETHSYS_I2S 7
442 +#define CLK_ETHSYS_CRYPTO 8
443 +#define CLK_ETHSYS_NR 9
444 +
445 +/* BDP */
446 +
447 +#define CLK_BDP_BRG_BA 1
448 +#define CLK_BDP_BRG_DRAM 2
449 +#define CLK_BDP_LARB_DRAM 3
450 +#define CLK_BDP_WR_VDI_PXL 4
451 +#define CLK_BDP_WR_VDI_DRAM 5
452 +#define CLK_BDP_WR_B 6
453 +#define CLK_BDP_DGI_IN 7
454 +#define CLK_BDP_DGI_OUT 8
455 +#define CLK_BDP_FMT_MAST_27 9
456 +#define CLK_BDP_FMT_B 10
457 +#define CLK_BDP_OSD_B 11
458 +#define CLK_BDP_OSD_DRAM 12
459 +#define CLK_BDP_OSD_AGENT 13
460 +#define CLK_BDP_OSD_PXL 14
461 +#define CLK_BDP_RLE_B 15
462 +#define CLK_BDP_RLE_AGENT 16
463 +#define CLK_BDP_RLE_DRAM 17
464 +#define CLK_BDP_F27M 18
465 +#define CLK_BDP_F27M_VDOUT 19
466 +#define CLK_BDP_F27_74_74 20
467 +#define CLK_BDP_F2FS 21
468 +#define CLK_BDP_F2FS74_148 22
469 +#define CLK_BDP_FB 23
470 +#define CLK_BDP_VDO_DRAM 24
471 +#define CLK_BDP_VDO_2FS 25
472 +#define CLK_BDP_VDO_B 26
473 +#define CLK_BDP_WR_DI_PXL 27
474 +#define CLK_BDP_WR_DI_DRAM 28
475 +#define CLK_BDP_WR_DI_B 29
476 +#define CLK_BDP_NR_PXL 30
477 +#define CLK_BDP_NR_DRAM 31
478 +#define CLK_BDP_NR_B 32
479 +
480 +#define CLK_BDP_RX_F 33
481 +#define CLK_BDP_RX_X 34
482 +#define CLK_BDP_RXPDT 35
483 +#define CLK_BDP_RX_CSCL_N 36
484 +#define CLK_BDP_RX_CSCL 37
485 +#define CLK_BDP_RX_DDCSCL_N 38
486 +#define CLK_BDP_RX_DDCSCL 39
487 +#define CLK_BDP_RX_VCO 40
488 +#define CLK_BDP_RX_DP 41
489 +#define CLK_BDP_RX_P 42
490 +#define CLK_BDP_RX_M 43
491 +#define CLK_BDP_RX_PLL 44
492 +#define CLK_BDP_BRG_RT_B 45
493 +#define CLK_BDP_BRG_RT_DRAM 46
494 +#define CLK_BDP_LARBRT_DRAM 47
495 +#define CLK_BDP_TMDS_SYN 48
496 +#define CLK_BDP_HDMI_MON 49
497 +#define CLK_BDP_NR 50
498 +
499 +#endif /* _DT_BINDINGS_CLK_MT2701_H */