61cd4b4f3ca5214a511e047c3fb700c5d2907242
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0010-reset-mediatek-mt2701-reset-controller-dt-binding-fi.patch
1 From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
2 From: Shunli Wang <shunli.wang@mediatek.com>
3 Date: Tue, 5 Jan 2016 14:30:21 +0800
4 Subject: [PATCH 10/81] reset: mediatek: mt2701 reset controller dt-binding
5 file
6
7 Dt-binding file about reset controller is used to provide
8 kinds of definition, which is referenced by dts file and
9 IC-specified reset controller driver code.
10
11 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
12 ---
13 .../dt-bindings/reset-controller/mt2701-resets.h | 74 ++++++++++++++++++++
14 1 file changed, 74 insertions(+)
15 create mode 100644 include/dt-bindings/reset-controller/mt2701-resets.h
16
17 --- /dev/null
18 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
19 @@ -0,0 +1,74 @@
20 +/*
21 + * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>
22 + *
23 + * This program is free software; you can redistribute it and/or modify
24 + * it under the terms of the GNU General Public License version 2 as
25 + * published by the Free Software Foundation.
26 + *
27 + * This program is distributed in the hope that it will be useful,
28 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 + * GNU General Public License for more details.
31 + */
32 +
33 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
34 +#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
35 +
36 +/* INFRACFG resets */
37 +#define MT2701_INFRA_EMI_REG_RST 0
38 +#define MT2701_INFRA_DRAMC0_A0_RST 1
39 +#define MT2701_INFRA_FHCTL_RST 2
40 +#define MT2701_INFRA_APCIRQ_EINT_RST 3
41 +#define MT2701_INFRA_APXGPT_RST 4
42 +#define MT2701_INFRA_SCPSYS_RST 5
43 +#define MT2701_INFRA_KP_RST 6
44 +#define MT2701_INFRA_PMIC_WRAP_RST 7
45 +#define MT2701_INFRA_MIPI_RST 8
46 +#define MT2701_INFRA_IRRX_RST 9
47 +#define MT2701_INFRA_CEC_RST 10
48 +#define MT2701_INFRA_EMI_RST 32
49 +#define MT2701_INFRA_DRAMC0_RST 34
50 +#define MT2701_INFRA_TRNG_RST 37
51 +#define MT2701_INFRA_SYSIRQ_RST 38
52 +
53 +/* PERICFG resets */
54 +#define MT2701_PERI_UART0_SW_RST 0
55 +#define MT2701_PERI_UART1_SW_RST 1
56 +#define MT2701_PERI_UART2_SW_RST 2
57 +#define MT2701_PERI_UART3_SW_RST 3
58 +#define MT2701_PERI_GCPU_SW_RST 5
59 +#define MT2701_PERI_BTIF_SW_RST 6
60 +#define MT2701_PERI_PWM_SW_RST 8
61 +#define MT2701_PERI_AUXADC_SW_RST 10
62 +#define MT2701_PERI_DMA_SW_RST 11
63 +#define MT2701_PERI_NFI_SW_RST 14
64 +#define MT2701_PERI_NLI_SW_RST 15
65 +#define MT2701_PERI_THERM_SW_RST 16
66 +#define MT2701_PERI_MSDC2_SW_RST 17
67 +#define MT2701_PERI_MSDC0_SW_RST 19
68 +#define MT2701_PERI_MSDC1_SW_RST 20
69 +#define MT2701_PERI_I2C0_SW_RST 22
70 +#define MT2701_PERI_I2C1_SW_RST 23
71 +#define MT2701_PERI_I2C2_SW_RST 24
72 +#define MT2701_PERI_I2C3_SW_RST 25
73 +#define MT2701_PERI_USB_SW_RST 28
74 +#define MT2701_PERI_ETH_SW_RST 29
75 +#define MT2701_PERI_SPI0_SW_RST 33
76 +
77 +/* TOPRGU resets */
78 +#define MT2701_TOPRGU_INFRA_RST 0
79 +#define MT2701_TOPRGU_MM_RST 1
80 +#define MT2701_TOPRGU_MFG_RST 2
81 +#define MT2701_TOPRGU_ETHDMA_RST 3
82 +#define MT2701_TOPRGU_VDEC_RST 4
83 +#define MT2701_TOPRGU_VENC_IMG_RST 5
84 +#define MT2701_TOPRGU_DDRPHY_RST 6
85 +#define MT2701_TOPRGU_MD_RST 7
86 +#define MT2701_TOPRGU_INFRA_AO_RST 8
87 +#define MT2701_TOPRGU_CONN_RST 9
88 +#define MT2701_TOPRGU_APMIXED_RST 10
89 +#define MT2701_TOPRGU_HIFSYS_RST 11
90 +#define MT2701_TOPRGU_CONN_MCU_RST 12
91 +#define MT2701_TOPRGU_BDP_DISP_RST 13
92 +
93 +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */