68149a7e9c7b83c605caec21fb84fb1c2b11862e
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0014-pinctrl-dt-bindings-Add-pinfunc-header-file-for-mt27.patch
1 From 416720ba33d4fd7d3166c17be7c13651cc08d408 Mon Sep 17 00:00:00 2001
2 From: Biao Huang <biao.huang@mediatek.com>
3 Date: Mon, 28 Dec 2015 15:09:04 +0800
4 Subject: [PATCH 14/81] pinctrl: dt bindings: Add pinfunc header file for
5 mt2701
6
7 Add pinfunc header file, mt2701 related dts will include it
8
9 Signed-off-by: Biao Huang <biao.huang@mediatek.com>
10 Acked-by: Linus Walleij <linus.walleij@linaro.org>
11 ---
12 arch/arm/boot/dts/mt2701-pinfunc.h | 735 ++++++++
13 drivers/pinctrl/mediatek/Kconfig | 6 +
14 drivers/pinctrl/mediatek/Makefile | 1 +
15 drivers/pinctrl/mediatek/pinctrl-mt2701.c | 586 +++++++
16 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +
17 drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 12 +-
18 drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h | 2323 +++++++++++++++++++++++++
19 7 files changed, 3678 insertions(+), 1 deletion(-)
20 create mode 100644 arch/arm/boot/dts/mt2701-pinfunc.h
21 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2701.c
22 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
23
24 --- /dev/null
25 +++ b/arch/arm/boot/dts/mt2701-pinfunc.h
26 @@ -0,0 +1,735 @@
27 +/*
28 + * Copyright (c) 2015 MediaTek Inc.
29 + * Author: Biao Huang <biao.huang@mediatek.com>
30 + *
31 + * This program is free software; you can redistribute it and/or modify
32 + * it under the terms of the GNU General Public License version 2 as
33 + * published by the Free Software Foundation.
34 + *
35 + * This program is distributed in the hope that it will be useful,
36 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 + * GNU General Public License for more details.
39 + */
40 +
41 +#ifndef __DTS_MT2701_PINFUNC_H
42 +#define __DTS_MT2701_PINFUNC_H
43 +
44 +#include <dt-bindings/pinctrl/mt65xx.h>
45 +
46 +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
47 +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
48 +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
49 +
50 +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
51 +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
52 +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
53 +
54 +#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
55 +#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
56 +
57 +#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
58 +#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
59 +
60 +#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
61 +#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
62 +
63 +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
64 +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
65 +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
66 +
67 +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
68 +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
69 +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
70 +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)
71 +
72 +#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
73 +#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
74 +#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
75 +#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)
76 +
77 +#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
78 +#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
79 +#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
80 +#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
81 +#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)
82 +
83 +#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
84 +#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
85 +#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
86 +#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
87 +#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
88 +#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)
89 +
90 +#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
91 +#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
92 +
93 +#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
94 +#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
95 +
96 +#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
97 +#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
98 +
99 +#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
100 +#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
101 +
102 +#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
103 +#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
104 +#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
105 +#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
106 +#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)
107 +
108 +#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
109 +#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
110 +#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
111 +#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)
112 +
113 +#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
114 +#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
115 +#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
116 +#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
117 +#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
118 +#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
119 +#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)
120 +
121 +#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
122 +#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
123 +#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
124 +#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
125 +#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
126 +#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)
127 +
128 +#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
129 +#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
130 +#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
131 +#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
132 +#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
133 +#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
134 +#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
135 +#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)
136 +
137 +#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
138 +#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
139 +#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
140 +#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
141 +#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
142 +#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
143 +#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
144 +#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)
145 +
146 +#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
147 +#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
148 +#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
149 +#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
150 +#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
151 +#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
152 +#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)
153 +
154 +#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
155 +#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
156 +#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
157 +#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
158 +#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
159 +#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
160 +#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)
161 +
162 +#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
163 +#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
164 +#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
165 +#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
166 +#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
167 +#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)
168 +
169 +#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
170 +#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
171 +#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
172 +#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
173 +#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)
174 +
175 +#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
176 +#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
177 +#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
178 +#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
179 +#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
180 +#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
181 +#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
182 +#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)
183 +
184 +#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
185 +#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
186 +#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
187 +#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
188 +#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
189 +#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
190 +#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)
191 +
192 +#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
193 +#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
194 +#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
195 +#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
196 +#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
197 +#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)
198 +
199 +#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
200 +#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
201 +#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
202 +#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
203 +#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
204 +#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
205 +#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
206 +#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)
207 +
208 +#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
209 +#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
210 +#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
211 +#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
212 +#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
213 +#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
214 +#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
215 +#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)
216 +
217 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
218 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
219 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
220 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
221 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
222 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
223 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)
224 +
225 +#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
226 +#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
227 +#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
228 +#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
229 +#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
230 +#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)
231 +
232 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
233 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
234 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
235 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
236 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
237 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)
238 +
239 +#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
240 +#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
241 +#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
242 +#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)
243 +
244 +#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
245 +#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
246 +#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
247 +#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
248 +#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
249 +
250 +#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
251 +#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
252 +#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
253 +#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
254 +#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
255 +
256 +#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
257 +#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
258 +#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
259 +#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
260 +
261 +#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
262 +#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
263 +#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
264 +#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
265 +
266 +#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
267 +#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
268 +#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
269 +
270 +#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
271 +#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
272 +#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)
273 +
274 +#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
275 +#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
276 +#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
277 +
278 +#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
279 +#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)
280 +
281 +#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
282 +#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
283 +#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
284 +
285 +#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
286 +#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
287 +#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
288 +
289 +#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
290 +#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
291 +#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
292 +#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
293 +#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
294 +#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)
295 +
296 +#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
297 +#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
298 +#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
299 +#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
300 +#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
301 +#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)
302 +
303 +#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
304 +#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
305 +#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
306 +#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
307 +#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)
308 +
309 +#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
310 +#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
311 +#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
312 +#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
313 +#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
314 +#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
315 +#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)
316 +
317 +#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
318 +#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
319 +#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
320 +#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
321 +#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)
322 +
323 +#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
324 +#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)
325 +
326 +#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
327 +#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)
328 +
329 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
330 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
331 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
332 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
333 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
334 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
335 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)
336 +
337 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
338 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
339 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
340 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
341 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)
342 +
343 +#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
344 +#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
345 +#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
346 +#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
347 +#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)
348 +
349 +#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
350 +#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)
351 +
352 +#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
353 +#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)
354 +
355 +#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
356 +#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)
357 +
358 +#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
359 +#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)
360 +
361 +#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
362 +#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
363 +#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
364 +#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)
365 +
366 +#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
367 +#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
368 +#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)
369 +
370 +#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
371 +#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
372 +#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
373 +
374 +#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
375 +#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
376 +#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)
377 +
378 +#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
379 +#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
380 +#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
381 +#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)
382 +
383 +#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
384 +#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
385 +#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)
386 +
387 +#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
388 +#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)
389 +
390 +#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
391 +#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)
392 +
393 +#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
394 +#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)
395 +
396 +#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
397 +#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)
398 +
399 +#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
400 +#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)
401 +
402 +#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
403 +#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)
404 +
405 +#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
406 +#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)
407 +
408 +#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
409 +#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)
410 +
411 +#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
412 +#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)
413 +
414 +#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
415 +#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)
416 +
417 +#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
418 +#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
419 +#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
420 +#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)
421 +
422 +#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
423 +#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
424 +#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
425 +#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
426 +#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)
427 +
428 +#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
429 +#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
430 +#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
431 +#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
432 +#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)
433 +
434 +#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
435 +#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
436 +#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
437 +#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)
438 +
439 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
440 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
441 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
442 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
443 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
444 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)
445 +
446 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
447 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
448 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
449 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
450 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
451 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)
452 +
453 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
454 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
455 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
456 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
457 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
458 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)
459 +
460 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
461 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
462 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
463 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
464 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
465 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
466 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)
467 +
468 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
469 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
470 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
471 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
472 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
473 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
474 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)
475 +
476 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
477 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
478 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
479 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
480 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
481 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
482 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
483 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)
484 +
485 +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
486 +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
487 +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)
488 +
489 +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
490 +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
491 +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)
492 +
493 +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
494 +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
495 +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)
496 +
497 +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
498 +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
499 +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)
500 +
501 +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
502 +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
503 +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)
504 +
505 +#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
506 +#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
507 +#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)
508 +
509 +#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
510 +#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
511 +#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)
512 +
513 +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
514 +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
515 +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)
516 +
517 +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
518 +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
519 +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)
520 +
521 +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
522 +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
523 +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)
524 +
525 +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
526 +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
527 +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
528 +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
529 +
530 +#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
531 +#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
532 +#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
533 +#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)
534 +
535 +#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
536 +#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
537 +#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
538 +#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
539 +
540 +#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
541 +#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
542 +#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
543 +#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)
544 +
545 +#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
546 +#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
547 +#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
548 +#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)
549 +
550 +#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
551 +#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
552 +#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
553 +#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)
554 +
555 +#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
556 +#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
557 +#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
558 +#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
559 +#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)
560 +
561 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
562 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
563 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
564 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
565 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)
566 +
567 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
568 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
569 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
570 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
571 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)
572 +
573 +#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
574 +#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)
575 +
576 +#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
577 +#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
578 +#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
579 +#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
580 +#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
581 +#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)
582 +
583 +#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
584 +#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
585 +#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
586 +#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
587 +#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
588 +#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)
589 +
590 +#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
591 +#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
592 +#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
593 +#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
594 +#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)
595 +
596 +#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
597 +#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
598 +#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
599 +#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
600 +#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
601 +#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)
602 +
603 +#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
604 +#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
605 +#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
606 +#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
607 +#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
608 +#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)
609 +
610 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
611 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
612 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
613 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
614 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
615 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
616 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)
617 +
618 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
619 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
620 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
621 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
622 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
623 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)
624 +
625 +#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
626 +#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
627 +#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
628 +#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)
629 +
630 +#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
631 +#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
632 +#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
633 +
634 +#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
635 +#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
636 +#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)
637 +
638 +#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
639 +#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
640 +#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)
641 +
642 +#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
643 +#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
644 +
645 +#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
646 +#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
647 +
648 +#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
649 +#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
650 +#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
651 +#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
652 +#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
653 +#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)
654 +
655 +#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
656 +#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
657 +#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
658 +#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
659 +#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
660 +#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)
661 +
662 +#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
663 +#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)
664 +
665 +#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
666 +#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)
667 +
668 +#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
669 +
670 +#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
671 +#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)
672 +
673 +#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
674 +#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)
675 +
676 +#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)
677 +
678 +#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
679 +#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)
680 +
681 +#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
682 +#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)
683 +
684 +#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
685 +#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)
686 +
687 +#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
688 +#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)
689 +
690 +#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
691 +#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)
692 +
693 +#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
694 +#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)
695 +
696 +#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)
697 +
698 +#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)
699 +
700 +#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)
701 +
702 +#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)
703 +
704 +#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)
705 +
706 +#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
707 +#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
708 +#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)
709 +
710 +#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
711 +#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
712 +
713 +#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
714 +#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
715 +#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)
716 +
717 +#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
718 +#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
719 +#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)
720 +
721 +#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
722 +#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
723 +#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)
724 +
725 +#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
726 +#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
727 +#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)
728 +
729 +#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
730 +#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
731 +
732 +#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
733 +#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
734 +
735 +#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
736 +#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
737 +
738 +#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
739 +#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
740 +
741 +#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
742 +#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
743 +
744 +#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
745 +#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
746 +
747 +#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
748 +#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
749 +
750 +#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
751 +#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
752 +#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)
753 +
754 +#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
755 +#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
756 +#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)
757 +
758 +#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
759 +#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
760 +
761 +#endif /* __DTS_MT2701_PINFUNC_H */
762 --- a/drivers/pinctrl/mediatek/Kconfig
763 +++ b/drivers/pinctrl/mediatek/Kconfig
764 @@ -9,6 +9,12 @@ config PINCTRL_MTK_COMMON
765 select OF_GPIO
766
767 # For ARMv7 SoCs
768 +config PINCTRL_MT2701
769 + bool "Mediatek MT2701 pin control" if COMPILE_TEST && !MACH_MT2701
770 + depends on OF
771 + default MACH_MT2701
772 + select PINCTRL_MTK_COMMON
773 +
774 config PINCTRL_MT8135
775 bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
776 depends on OF
777 --- a/drivers/pinctrl/mediatek/Makefile
778 +++ b/drivers/pinctrl/mediatek/Makefile
779 @@ -2,6 +2,7 @@
780 obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
781
782 # SoC Drivers
783 +obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
784 obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
785 obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
786 obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
787 --- /dev/null
788 +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
789 @@ -0,0 +1,586 @@
790 +/*
791 + * Copyright (c) 2015 MediaTek Inc.
792 + * Author: Biao Huang <biao.huang@mediatek.com>
793 + *
794 + * This program is free software; you can redistribute it and/or modify
795 + * it under the terms of the GNU General Public License version 2 as
796 + * published by the Free Software Foundation.
797 + *
798 + * This program is distributed in the hope that it will be useful,
799 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
800 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
801 + * GNU General Public License for more details.
802 + */
803 +
804 +#include <dt-bindings/pinctrl/mt65xx.h>
805 +#include <linux/module.h>
806 +#include <linux/of.h>
807 +#include <linux/of_device.h>
808 +#include <linux/platform_device.h>
809 +#include <linux/pinctrl/pinctrl.h>
810 +#include <linux/regmap.h>
811 +
812 +#include "pinctrl-mtk-common.h"
813 +#include "pinctrl-mtk-mt2701.h"
814 +
815 +/**
816 + * struct mtk_spec_pinmux_set
817 + * - For special pins' mode setting
818 + * @pin: The pin number.
819 + * @offset: The offset of extra setting register.
820 + * @bit: The bit of extra setting register.
821 + */
822 +struct mtk_spec_pinmux_set {
823 + unsigned short pin;
824 + unsigned short offset;
825 + unsigned char bit;
826 +};
827 +
828 +#define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
829 + { \
830 + .pin = _pin, \
831 + .offset = _offset, \
832 + .bit = _bit, \
833 + }
834 +
835 +static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
836 + /* 0E4E8SR 4/8/12/16 */
837 + MTK_DRV_GRP(4, 16, 1, 2, 4),
838 + /* 0E2E4SR 2/4/6/8 */
839 + MTK_DRV_GRP(2, 8, 1, 2, 2),
840 + /* E8E4E2 2/4/6/8/10/12/14/16 */
841 + MTK_DRV_GRP(2, 16, 0, 2, 2)
842 +};
843 +
844 +static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
845 + MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
846 + MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
847 + MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
848 + MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
849 + MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
850 + MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
851 + MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
852 + MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
853 + MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
854 + MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
855 + MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
856 + MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
857 + MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
858 + MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
859 + MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
860 + MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
861 + MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
862 + MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
863 + MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
864 + MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
865 + MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
866 + MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
867 + MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
868 + MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
869 + MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
870 + MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
871 + MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
872 + MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
873 + MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
874 + MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
875 + MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
876 + MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
877 + MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
878 + MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
879 + MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
880 + MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
881 + MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
882 + MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
883 + MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
884 + MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
885 + MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
886 + MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
887 + MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
888 + MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
889 + MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
890 + MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
891 + MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
892 + MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
893 + MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
894 + MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
895 + MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
896 + MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
897 + MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
898 + MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
899 + MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
900 + MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
901 + MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
902 + MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
903 + MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
904 + MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
905 + MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
906 + MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
907 + MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
908 + MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
909 + MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
910 + MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
911 + MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
912 + MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
913 + MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
914 + MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
915 + MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
916 + MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
917 + MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
918 + MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
919 + MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
920 + MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
921 + MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
922 + MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
923 + MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
924 + MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
925 + MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
926 + MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
927 + MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
928 + MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
929 + MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
930 + MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
931 + MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
932 + MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
933 + MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
934 + MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
935 + MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
936 + MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
937 + MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
938 + MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
939 + MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
940 + MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
941 + MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
942 + MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
943 + MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
944 + MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
945 + MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
946 + MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
947 + MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
948 + MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
949 + MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
950 + MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
951 + MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
952 + MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
953 + MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
954 + MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
955 + MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
956 + MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
957 + MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
958 + MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
959 + MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
960 + MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
961 + MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
962 + MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
963 + MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
964 + MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
965 + MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
966 + MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
967 + MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
968 + MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
969 + MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
970 + MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
971 + MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
972 + MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
973 + MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
974 + MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
975 + MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
976 + MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
977 + MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
978 + MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
979 + MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
980 + MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
981 + MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
982 + MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
983 + MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
984 + MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
985 + MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
986 + MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
987 + MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
988 + MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
989 + MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
990 + MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
991 + MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
992 + MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
993 + MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
994 + MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
995 + MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
996 + MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
997 + MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
998 + MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
999 + MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
1000 + MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
1001 + MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
1002 + MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
1003 + MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
1004 + MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
1005 + MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
1006 + MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
1007 + MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
1008 + MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
1009 + MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
1010 + MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
1011 + MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
1012 + MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
1013 + MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
1014 + MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
1015 + MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
1016 + MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
1017 + MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
1018 + MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
1019 + MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
1020 + MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
1021 + MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
1022 + MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
1023 + MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
1024 + MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
1025 + MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
1026 + MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
1027 +};
1028 +
1029 +static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
1030 + MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14), /* ms0 data7 */
1031 + MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10), /* ms0 data6 */
1032 + MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6), /* ms0 data5 */
1033 + MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2), /* ms0 data4 */
1034 + MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2), /* ms0 rstb */
1035 + MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10), /* ms0 cmd */
1036 + MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10), /* ms0 clk */
1037 + MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14), /* ms0 data3 */
1038 + MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10), /* ms0 data2 */
1039 + MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6), /* ms0 data1 */
1040 + MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2), /* ms0 data0 */
1041 +
1042 + MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10), /* ms1 cmd */
1043 + MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10), /* ms1 clk */
1044 + MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2), /* ms1 dat0 */
1045 + MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8), /* ms1 dat1 */
1046 + MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6), /* ms1 dat2 */
1047 + MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14), /* ms1 dat3 */
1048 +
1049 + MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10), /* ms2 cmd */
1050 + MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10), /* ms2 clk */
1051 + MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2), /* ms2 dat0 */
1052 + MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8), /* ms2 dat1 */
1053 + MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6), /* ms2 dat2 */
1054 + MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14), /* ms2 dat3 */
1055 +
1056 + MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2), /* ms0e rstb */
1057 + MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */
1058 + MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10), /* ms0e dat6 */
1059 + MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6), /* ms0e dat5 */
1060 + MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2), /* ms0e dat4 */
1061 + MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14), /* ms0e dat3 */
1062 + MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10), /* ms0e dat2 */
1063 + MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6), /* ms0e dat1 */
1064 + MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2), /* ms0e dat0 */
1065 + MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10), /* ms0e cmd */
1066 + MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */
1067 + MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
1068 +};
1069 +
1070 +static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
1071 + unsigned char align, bool isup, unsigned int r1r0)
1072 +{
1073 + return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
1074 + ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
1075 +}
1076 +
1077 +static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
1078 + MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
1079 + MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
1080 + MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
1081 + MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
1082 + MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
1083 + MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
1084 + MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
1085 + MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
1086 + MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
1087 + MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
1088 + MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
1089 + MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
1090 + MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
1091 + MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
1092 + MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
1093 + MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
1094 + MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
1095 + MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
1096 + MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
1097 + MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
1098 + MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
1099 + MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
1100 + MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
1101 + MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
1102 + MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
1103 + MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
1104 + MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
1105 + MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
1106 + MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
1107 + MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
1108 + MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
1109 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
1110 + MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
1111 + MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
1112 + MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
1113 + MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
1114 + MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
1115 + MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
1116 + MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
1117 + MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
1118 + MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
1119 + MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
1120 + MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
1121 + MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
1122 + MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
1123 + MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
1124 + MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
1125 + MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
1126 + MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
1127 + MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
1128 + MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
1129 + MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
1130 + MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
1131 + MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
1132 + MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
1133 + MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
1134 + MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
1135 + MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
1136 + MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
1137 + MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
1138 + MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
1139 + MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
1140 + MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
1141 + MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
1142 + MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
1143 + MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
1144 +};
1145 +
1146 +static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
1147 + MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
1148 + MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
1149 + MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
1150 + MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
1151 + MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
1152 + MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
1153 + MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
1154 + MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
1155 + MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
1156 + MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
1157 + MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
1158 + MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
1159 + MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
1160 + MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
1161 + MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
1162 + MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
1163 + MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
1164 + MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
1165 + MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
1166 + MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
1167 + MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
1168 + MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
1169 + MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
1170 + MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
1171 + MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
1172 + MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
1173 + MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
1174 + MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
1175 + MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
1176 + MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
1177 + MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
1178 + MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
1179 + MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
1180 + MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
1181 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
1182 + MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
1183 + MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
1184 + MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
1185 + MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
1186 + MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
1187 + MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
1188 + MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
1189 + MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
1190 + MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
1191 + MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
1192 + MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
1193 + MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
1194 + MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
1195 + MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
1196 + MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
1197 + MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
1198 + MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
1199 + MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
1200 + MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
1201 + MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
1202 + MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
1203 + MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
1204 + MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
1205 + MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
1206 + MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
1207 + MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
1208 + MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
1209 + MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
1210 + MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
1211 + MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
1212 + MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
1213 + MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
1214 + MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
1215 + MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
1216 + MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
1217 + MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
1218 + MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
1219 + MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
1220 + MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
1221 + MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
1222 + MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
1223 + MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
1224 + MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
1225 + MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
1226 + MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
1227 + MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
1228 + MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
1229 + MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
1230 + MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
1231 + MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
1232 + MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
1233 + MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
1234 +};
1235 +
1236 +static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
1237 + unsigned char align, int value, enum pin_config_param arg)
1238 +{
1239 + if (arg == PIN_CONFIG_INPUT_ENABLE)
1240 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
1241 + ARRAY_SIZE(mt2701_ies_set), pin, align, value);
1242 + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
1243 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
1244 + ARRAY_SIZE(mt2701_smt_set), pin, align, value);
1245 + return -EINVAL;
1246 +}
1247 +
1248 +static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
1249 + MTK_PINMUX_SPEC(22, 0xb10, 3),
1250 + MTK_PINMUX_SPEC(23, 0xb10, 4),
1251 + MTK_PINMUX_SPEC(24, 0xb10, 5),
1252 + MTK_PINMUX_SPEC(29, 0xb10, 9),
1253 + MTK_PINMUX_SPEC(208, 0xb10, 7),
1254 + MTK_PINMUX_SPEC(209, 0xb10, 8),
1255 + MTK_PINMUX_SPEC(203, 0xf20, 0),
1256 + MTK_PINMUX_SPEC(204, 0xf20, 1),
1257 + MTK_PINMUX_SPEC(249, 0xef0, 0),
1258 + MTK_PINMUX_SPEC(250, 0xef0, 0),
1259 + MTK_PINMUX_SPEC(251, 0xef0, 0),
1260 + MTK_PINMUX_SPEC(252, 0xef0, 0),
1261 + MTK_PINMUX_SPEC(253, 0xef0, 0),
1262 + MTK_PINMUX_SPEC(254, 0xef0, 0),
1263 + MTK_PINMUX_SPEC(255, 0xef0, 0),
1264 + MTK_PINMUX_SPEC(256, 0xef0, 0),
1265 + MTK_PINMUX_SPEC(257, 0xef0, 0),
1266 + MTK_PINMUX_SPEC(258, 0xef0, 0),
1267 + MTK_PINMUX_SPEC(259, 0xef0, 0),
1268 + MTK_PINMUX_SPEC(260, 0xef0, 0),
1269 +};
1270 +
1271 +static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
1272 + unsigned int mode)
1273 +{
1274 + unsigned int i, value, mask;
1275 + unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
1276 + unsigned int spec_flag;
1277 +
1278 + for (i = 0; i < info_num; i++) {
1279 + if (pin == mt2701_spec_pinmux[i].pin)
1280 + break;
1281 + }
1282 +
1283 + if (i == info_num)
1284 + return;
1285 +
1286 + spec_flag = (mode >> 3);
1287 + mask = BIT(mt2701_spec_pinmux[i].bit);
1288 + if (!spec_flag)
1289 + value = mask;
1290 + else
1291 + value = 0;
1292 + regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
1293 +}
1294 +
1295 +static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
1296 +{
1297 + if (pin > 175)
1298 + *reg_addr += 0x10;
1299 +}
1300 +
1301 +static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
1302 + .pins = mtk_pins_mt2701,
1303 + .npins = ARRAY_SIZE(mtk_pins_mt2701),
1304 + .grp_desc = mt2701_drv_grp,
1305 + .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
1306 + .pin_drv_grp = mt2701_pin_drv,
1307 + .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
1308 + .spec_pull_set = mt2701_spec_pull_set,
1309 + .spec_ies_smt_set = mt2701_ies_smt_set,
1310 + .spec_pinmux_set = mt2701_spec_pinmux_set,
1311 + .spec_dir_set = mt2701_spec_dir_set,
1312 + .dir_offset = 0x0000,
1313 + .pullen_offset = 0x0150,
1314 + .pullsel_offset = 0x0280,
1315 + .dout_offset = 0x0500,
1316 + .din_offset = 0x0630,
1317 + .pinmux_offset = 0x0760,
1318 + .type1_start = 280,
1319 + .type1_end = 280,
1320 + .port_shf = 4,
1321 + .port_mask = 0x1f,
1322 + .port_align = 4,
1323 + .eint_offsets = {
1324 + .name = "mt2701_eint",
1325 + .stat = 0x000,
1326 + .ack = 0x040,
1327 + .mask = 0x080,
1328 + .mask_set = 0x0c0,
1329 + .mask_clr = 0x100,
1330 + .sens = 0x140,
1331 + .sens_set = 0x180,
1332 + .sens_clr = 0x1c0,
1333 + .soft = 0x200,
1334 + .soft_set = 0x240,
1335 + .soft_clr = 0x280,
1336 + .pol = 0x300,
1337 + .pol_set = 0x340,
1338 + .pol_clr = 0x380,
1339 + .dom_en = 0x400,
1340 + .dbnc_ctrl = 0x500,
1341 + .dbnc_set = 0x600,
1342 + .dbnc_clr = 0x700,
1343 + .port_mask = 6,
1344 + .ports = 6,
1345 + },
1346 + .ap_num = 169,
1347 + .db_cnt = 16,
1348 +};
1349 +
1350 +static int mt2701_pinctrl_probe(struct platform_device *pdev)
1351 +{
1352 + return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
1353 +}
1354 +
1355 +static const struct of_device_id mt2701_pctrl_match[] = {
1356 + { .compatible = "mediatek,mt2701-pinctrl", },
1357 + {}
1358 +};
1359 +MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
1360 +
1361 +static struct platform_driver mtk_pinctrl_driver = {
1362 + .probe = mt2701_pinctrl_probe,
1363 + .driver = {
1364 + .name = "mediatek-mt2701-pinctrl",
1365 + .owner = THIS_MODULE,
1366 + .of_match_table = mt2701_pctrl_match,
1367 + },
1368 +};
1369 +
1370 +static int __init mtk_pinctrl_init(void)
1371 +{
1372 + return platform_driver_register(&mtk_pinctrl_driver);
1373 +}
1374 +
1375 +arch_initcall(mtk_pinctrl_init);
1376 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
1377 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
1378 @@ -47,6 +47,8 @@
1379 static const char * const mtk_gpio_functions[] = {
1380 "func0", "func1", "func2", "func3",
1381 "func4", "func5", "func6", "func7",
1382 + "func8", "func9", "func10", "func11",
1383 + "func12", "func13", "func14", "func15",
1384 };
1385
1386 /*
1387 @@ -81,6 +83,9 @@ static int mtk_pmx_gpio_set_direction(st
1388 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
1389 bit = BIT(offset & 0xf);
1390
1391 + if (pctl->devdata->spec_dir_set)
1392 + pctl->devdata->spec_dir_set(&reg_addr, offset);
1393 +
1394 if (input)
1395 /* Different SoC has different alignment offset. */
1396 reg_addr = CLR_ADDR(reg_addr, pctl);
1397 @@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct p
1398 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
1399 break;
1400 case PIN_CONFIG_INPUT_ENABLE:
1401 + mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
1402 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
1403 break;
1404 case PIN_CONFIG_OUTPUT:
1405 @@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct p
1406 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
1407 break;
1408 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1409 + mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
1410 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
1411 break;
1412 case PIN_CONFIG_DRIVE_STRENGTH:
1413 @@ -667,9 +674,14 @@ static int mtk_pmx_set_mode(struct pinct
1414 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
1415 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1416
1417 + if (pctl->devdata->spec_pinmux_set)
1418 + pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
1419 + pin, mode);
1420 +
1421 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
1422 + pctl->devdata->pinmux_offset;
1423
1424 + mode &= mask;
1425 bit = pin % MAX_GPIO_MODE_PER_REG;
1426 mask <<= (GPIO_MODE_BITS * bit);
1427 val = (mode << (GPIO_MODE_BITS * bit));
1428 @@ -746,6 +758,10 @@ static int mtk_gpio_get_direction(struct
1429
1430 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
1431 bit = BIT(offset & 0xf);
1432 +
1433 + if (pctl->devdata->spec_dir_set)
1434 + pctl->devdata->spec_dir_set(&reg_addr, offset);
1435 +
1436 regmap_read(pctl->regmap1, reg_addr, &read_val);
1437 return !(read_val & bit);
1438 }
1439 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
1440 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
1441 @@ -209,7 +209,14 @@ struct mtk_eint_offsets {
1442 * means when user set smt, input enable is set at the same time. So they
1443 * also need special control. If special control is success, this should
1444 * return 0, otherwise return non-zero value.
1445 - *
1446 + * @spec_pinmux_set: In some cases, there are two pinmux functions share
1447 + * the same value in the same segment of pinmux control register. If user
1448 + * want to use one of the two functions, they need an extra bit setting to
1449 + * select the right one.
1450 + * @spec_dir_set: In very few SoCs, direction control registers are not
1451 + * arranged continuously, they may be cut to parts. So they need special
1452 + * dir setting.
1453 +
1454 * @dir_offset: The direction register offset.
1455 * @pullen_offset: The pull-up/pull-down enable register offset.
1456 * @pinmux_offset: The pinmux register offset.
1457 @@ -234,6 +241,9 @@ struct mtk_pinctrl_devdata {
1458 unsigned char align, bool isup, unsigned int arg);
1459 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
1460 unsigned char align, int value, enum pin_config_param arg);
1461 + void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
1462 + unsigned int mode);
1463 + void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
1464 unsigned int dir_offset;
1465 unsigned int ies_offset;
1466 unsigned int smt_offset;
1467 --- /dev/null
1468 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
1469 @@ -0,0 +1,2323 @@
1470 +/*
1471 + * Copyright (c) 2015 MediaTek Inc.
1472 + * Author: Biao Huang <biao.huang@mediatek.com>
1473 + *
1474 + * This program is free software; you can redistribute it and/or modify
1475 + * it under the terms of the GNU General Public License version 2 as
1476 + * published by the Free Software Foundation.
1477 + *
1478 + * This program is distributed in the hope that it will be useful,
1479 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1480 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1481 + * GNU General Public License for more details.
1482 + */
1483 +
1484 +#ifndef __PINCTRL_MTK_MT2701_H
1485 +#define __PINCTRL_MTK_MT2701_H
1486 +
1487 +#include <linux/pinctrl/pinctrl.h>
1488 +#include "pinctrl-mtk-common.h"
1489 +
1490 +static const struct mtk_desc_pin mtk_pins_mt2701[] = {
1491 + MTK_PIN(
1492 + PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
1493 + NULL, "mt2701",
1494 + MTK_EINT_FUNCTION(0, 148),
1495 + MTK_FUNCTION(0, "GPIO0"),
1496 + MTK_FUNCTION(1, "PWRAP_SPIDO"),
1497 + MTK_FUNCTION(2, "PWRAP_SPIDI")
1498 + ),
1499 + MTK_PIN(
1500 + PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
1501 + NULL, "mt2701",
1502 + MTK_EINT_FUNCTION(0, 149),
1503 + MTK_FUNCTION(0, "GPIO1"),
1504 + MTK_FUNCTION(1, "PWRAP_SPIDI"),
1505 + MTK_FUNCTION(2, "PWRAP_SPIDO")
1506 + ),
1507 + MTK_PIN(
1508 + PINCTRL_PIN(2, "PWRAP_INT"),
1509 + NULL, "mt2701",
1510 + MTK_EINT_FUNCTION(0, 150),
1511 + MTK_FUNCTION(0, "GPIO2"),
1512 + MTK_FUNCTION(1, "PWRAP_INT")
1513 + ),
1514 + MTK_PIN(
1515 + PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
1516 + NULL, "mt2701",
1517 + MTK_EINT_FUNCTION(0, 151),
1518 + MTK_FUNCTION(0, "GPIO3"),
1519 + MTK_FUNCTION(1, "PWRAP_SPICK_I")
1520 + ),
1521 + MTK_PIN(
1522 + PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
1523 + NULL, "mt2701",
1524 + MTK_EINT_FUNCTION(0, 152),
1525 + MTK_FUNCTION(0, "GPIO4"),
1526 + MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
1527 + ),
1528 + MTK_PIN(
1529 + PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
1530 + NULL, "mt2701",
1531 + MTK_EINT_FUNCTION(0, 153),
1532 + MTK_FUNCTION(0, "GPIO5"),
1533 + MTK_FUNCTION(1, "PWRAP_SPICK2_I"),
1534 + MTK_FUNCTION(5, "ANT_SEL1")
1535 + ),
1536 + MTK_PIN(
1537 + PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
1538 + NULL, "mt2701",
1539 + MTK_EINT_FUNCTION(0, 154),
1540 + MTK_FUNCTION(0, "GPIO6"),
1541 + MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"),
1542 + MTK_FUNCTION(5, "ANT_SEL0"),
1543 + MTK_FUNCTION(7, "DBG_MON_A[0]")
1544 + ),
1545 + MTK_PIN(
1546 + PINCTRL_PIN(7, "SPI1_CSN"),
1547 + NULL, "mt2701",
1548 + MTK_EINT_FUNCTION(0, 155),
1549 + MTK_FUNCTION(0, "GPIO7"),
1550 + MTK_FUNCTION(1, "SPI1_CS"),
1551 + MTK_FUNCTION(4, "KCOL0"),
1552 + MTK_FUNCTION(7, "DBG_MON_B[12]")
1553 + ),
1554 + MTK_PIN(
1555 + PINCTRL_PIN(8, "SPI1_MI"),
1556 + NULL, "mt2701",
1557 + MTK_EINT_FUNCTION(0, 156),
1558 + MTK_FUNCTION(0, "GPIO8"),
1559 + MTK_FUNCTION(1, "SPI1_MI"),
1560 + MTK_FUNCTION(2, "SPI1_MO"),
1561 + MTK_FUNCTION(4, "KCOL1"),
1562 + MTK_FUNCTION(7, "DBG_MON_B[13]")
1563 + ),
1564 + MTK_PIN(
1565 + PINCTRL_PIN(9, "SPI1_MO"),
1566 + NULL, "mt2701",
1567 + MTK_EINT_FUNCTION(0, 157),
1568 + MTK_FUNCTION(0, "GPIO9"),
1569 + MTK_FUNCTION(1, "SPI1_MO"),
1570 + MTK_FUNCTION(2, "SPI1_MI"),
1571 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
1572 + MTK_FUNCTION(4, "KCOL2"),
1573 + MTK_FUNCTION(7, "DBG_MON_B[14]")
1574 + ),
1575 + MTK_PIN(
1576 + PINCTRL_PIN(10, "RTC32K_CK"),
1577 + NULL, "mt2701",
1578 + MTK_EINT_FUNCTION(0, 158),
1579 + MTK_FUNCTION(0, "GPIO10"),
1580 + MTK_FUNCTION(1, "RTC32K_CK")
1581 + ),
1582 + MTK_PIN(
1583 + PINCTRL_PIN(11, "WATCHDOG"),
1584 + NULL, "mt2701",
1585 + MTK_EINT_FUNCTION(0, 159),
1586 + MTK_FUNCTION(0, "GPIO11"),
1587 + MTK_FUNCTION(1, "WATCHDOG")
1588 + ),
1589 + MTK_PIN(
1590 + PINCTRL_PIN(12, "SRCLKENA"),
1591 + NULL, "mt2701",
1592 + MTK_EINT_FUNCTION(0, 160),
1593 + MTK_FUNCTION(0, "GPIO12"),
1594 + MTK_FUNCTION(1, "SRCLKENA")
1595 + ),
1596 + MTK_PIN(
1597 + PINCTRL_PIN(13, "SRCLKENAI"),
1598 + NULL, "mt2701",
1599 + MTK_EINT_FUNCTION(0, 161),
1600 + MTK_FUNCTION(0, "GPIO13"),
1601 + MTK_FUNCTION(1, "SRCLKENAI")
1602 + ),
1603 + MTK_PIN(
1604 + PINCTRL_PIN(14, "URXD2"),
1605 + NULL, "mt2701",
1606 + MTK_EINT_FUNCTION(0, 162),
1607 + MTK_FUNCTION(0, "GPIO14"),
1608 + MTK_FUNCTION(1, "URXD2"),
1609 + MTK_FUNCTION(2, "UTXD2"),
1610 + MTK_FUNCTION(5, "SRCCLKENAI2"),
1611 + MTK_FUNCTION(7, "DBG_MON_B[30]")
1612 + ),
1613 + MTK_PIN(
1614 + PINCTRL_PIN(15, "UTXD2"),
1615 + NULL, "mt2701",
1616 + MTK_EINT_FUNCTION(0, 163),
1617 + MTK_FUNCTION(0, "GPIO15"),
1618 + MTK_FUNCTION(1, "UTXD2"),
1619 + MTK_FUNCTION(2, "URXD2"),
1620 + MTK_FUNCTION(7, "DBG_MON_B[31]")
1621 + ),
1622 + MTK_PIN(
1623 + PINCTRL_PIN(16, "I2S5_DATA_IN"),
1624 + NULL, "mt2701",
1625 + MTK_EINT_FUNCTION(0, 164),
1626 + MTK_FUNCTION(0, "GPIO16"),
1627 + MTK_FUNCTION(1, "I2S5_DATA_IN"),
1628 + MTK_FUNCTION(3, "PCM_RX"),
1629 + MTK_FUNCTION(4, "ANT_SEL4")
1630 + ),
1631 + MTK_PIN(
1632 + PINCTRL_PIN(17, "I2S5_BCK"),
1633 + NULL, "mt2701",
1634 + MTK_EINT_FUNCTION(0, 165),
1635 + MTK_FUNCTION(0, "GPIO17"),
1636 + MTK_FUNCTION(1, "I2S5_BCK"),
1637 + MTK_FUNCTION(3, "PCM_CLK0"),
1638 + MTK_FUNCTION(4, "ANT_SEL2")
1639 + ),
1640 + MTK_PIN(
1641 + PINCTRL_PIN(18, "PCM_CLK"),
1642 + NULL, "mt2701",
1643 + MTK_EINT_FUNCTION(0, 166),
1644 + MTK_FUNCTION(0, "GPIO18"),
1645 + MTK_FUNCTION(1, "PCM_CLK0"),
1646 + MTK_FUNCTION(2, "MRG_CLK"),
1647 + MTK_FUNCTION(4, "MM_TEST_CK"),
1648 + MTK_FUNCTION(5, "CONN_DSP_JCK"),
1649 + MTK_FUNCTION(6, "WCN_PCM_CLKO"),
1650 + MTK_FUNCTION(7, "DBG_MON_A[3]")
1651 + ),
1652 + MTK_PIN(
1653 + PINCTRL_PIN(19, "PCM_SYNC"),
1654 + NULL, "mt2701",
1655 + MTK_EINT_FUNCTION(0, 167),
1656 + MTK_FUNCTION(0, "GPIO19"),
1657 + MTK_FUNCTION(1, "PCM_SYNC"),
1658 + MTK_FUNCTION(2, "MRG_SYNC"),
1659 + MTK_FUNCTION(5, "CONN_DSP_JINTP"),
1660 + MTK_FUNCTION(6, "WCN_PCM_SYNC"),
1661 + MTK_FUNCTION(7, "DBG_MON_A[5]")
1662 + ),
1663 + MTK_PIN(
1664 + PINCTRL_PIN(20, "PCM_RX"),
1665 + NULL, "mt2701",
1666 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1667 + MTK_FUNCTION(0, "GPIO20"),
1668 + MTK_FUNCTION(1, "PCM_RX"),
1669 + MTK_FUNCTION(2, "MRG_RX"),
1670 + MTK_FUNCTION(3, "MRG_TX"),
1671 + MTK_FUNCTION(4, "PCM_TX"),
1672 + MTK_FUNCTION(5, "CONN_DSP_JDI"),
1673 + MTK_FUNCTION(6, "WCN_PCM_RX"),
1674 + MTK_FUNCTION(7, "DBG_MON_A[4]")
1675 + ),
1676 + MTK_PIN(
1677 + PINCTRL_PIN(21, "PCM_TX"),
1678 + NULL, "mt2701",
1679 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1680 + MTK_FUNCTION(0, "GPIO21"),
1681 + MTK_FUNCTION(1, "PCM_TX"),
1682 + MTK_FUNCTION(2, "MRG_TX"),
1683 + MTK_FUNCTION(3, "MRG_RX"),
1684 + MTK_FUNCTION(4, "PCM_RX"),
1685 + MTK_FUNCTION(5, "CONN_DSP_JMS"),
1686 + MTK_FUNCTION(6, "WCN_PCM_TX"),
1687 + MTK_FUNCTION(7, "DBG_MON_A[2]")
1688 + ),
1689 + MTK_PIN(
1690 + PINCTRL_PIN(22, "EINT0"),
1691 + NULL, "mt2701",
1692 + MTK_EINT_FUNCTION(0, 0),
1693 + MTK_FUNCTION(0, "GPIO22"),
1694 + MTK_FUNCTION(1, "UCTS0"),
1695 + MTK_FUNCTION(3, "KCOL3"),
1696 + MTK_FUNCTION(4, "CONN_DSP_JDO"),
1697 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
1698 + MTK_FUNCTION(7, "DBG_MON_A[30]"),
1699 + MTK_FUNCTION(10, "PCIE0_PERST_N")
1700 + ),
1701 + MTK_PIN(
1702 + PINCTRL_PIN(23, "EINT1"),
1703 + NULL, "mt2701",
1704 + MTK_EINT_FUNCTION(0, 1),
1705 + MTK_FUNCTION(0, "GPIO23"),
1706 + MTK_FUNCTION(1, "URTS0"),
1707 + MTK_FUNCTION(3, "KCOL2"),
1708 + MTK_FUNCTION(4, "CONN_MCU_TDO"),
1709 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
1710 + MTK_FUNCTION(7, "DBG_MON_A[29]"),
1711 + MTK_FUNCTION(10, "PCIE1_PERST_N")
1712 + ),
1713 + MTK_PIN(
1714 + PINCTRL_PIN(24, "EINT2"),
1715 + NULL, "mt2701",
1716 + MTK_EINT_FUNCTION(0, 2),
1717 + MTK_FUNCTION(0, "GPIO24"),
1718 + MTK_FUNCTION(1, "UCTS1"),
1719 + MTK_FUNCTION(3, "KCOL1"),
1720 + MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"),
1721 + MTK_FUNCTION(7, "DBG_MON_A[28]"),
1722 + MTK_FUNCTION(10, "PCIE2_PERST_N")
1723 + ),
1724 + MTK_PIN(
1725 + PINCTRL_PIN(25, "EINT3"),
1726 + NULL, "mt2701",
1727 + MTK_EINT_FUNCTION(0, 3),
1728 + MTK_FUNCTION(0, "GPIO25"),
1729 + MTK_FUNCTION(1, "URTS1"),
1730 + MTK_FUNCTION(3, "KCOL0"),
1731 + MTK_FUNCTION(4, "CONN_MCU_DBGI_N"),
1732 + MTK_FUNCTION(7, "DBG_MON_A[27]")
1733 + ),
1734 + MTK_PIN(
1735 + PINCTRL_PIN(26, "EINT4"),
1736 + NULL, "mt2701",
1737 + MTK_EINT_FUNCTION(0, 4),
1738 + MTK_FUNCTION(0, "GPIO26"),
1739 + MTK_FUNCTION(1, "UCTS3"),
1740 + MTK_FUNCTION(2, "DRV_VBUS_P1"),
1741 + MTK_FUNCTION(3, "KROW3"),
1742 + MTK_FUNCTION(4, "CONN_MCU_TCK0"),
1743 + MTK_FUNCTION(5, "CONN_MCU_AICE_JCKC"),
1744 + MTK_FUNCTION(6, "PCIE2_WAKE_N"),
1745 + MTK_FUNCTION(7, "DBG_MON_A[26]")
1746 + ),
1747 + MTK_PIN(
1748 + PINCTRL_PIN(27, "EINT5"),
1749 + NULL, "mt2701",
1750 + MTK_EINT_FUNCTION(0, 5),
1751 + MTK_FUNCTION(0, "GPIO27"),
1752 + MTK_FUNCTION(1, "URTS3"),
1753 + MTK_FUNCTION(2, "IDDIG_P1"),
1754 + MTK_FUNCTION(3, "KROW2"),
1755 + MTK_FUNCTION(4, "CONN_MCU_TDI"),
1756 + MTK_FUNCTION(6, "PCIE1_WAKE_N"),
1757 + MTK_FUNCTION(7, "DBG_MON_A[25]")
1758 + ),
1759 + MTK_PIN(
1760 + PINCTRL_PIN(28, "EINT6"),
1761 + NULL, "mt2701",
1762 + MTK_EINT_FUNCTION(0, 6),
1763 + MTK_FUNCTION(0, "GPIO28"),
1764 + MTK_FUNCTION(1, "DRV_VBUS"),
1765 + MTK_FUNCTION(3, "KROW1"),
1766 + MTK_FUNCTION(4, "CONN_MCU_TRST_B"),
1767 + MTK_FUNCTION(6, "PCIE0_WAKE_N"),
1768 + MTK_FUNCTION(7, "DBG_MON_A[24]")
1769 + ),
1770 + MTK_PIN(
1771 + PINCTRL_PIN(29, "EINT7"),
1772 + NULL, "mt2701",
1773 + MTK_EINT_FUNCTION(0, 7),
1774 + MTK_FUNCTION(0, "GPIO29"),
1775 + MTK_FUNCTION(1, "IDDIG"),
1776 + MTK_FUNCTION(2, "MSDC1_WP"),
1777 + MTK_FUNCTION(3, "KROW0"),
1778 + MTK_FUNCTION(4, "CONN_MCU_TMS"),
1779 + MTK_FUNCTION(5, "CONN_MCU_AICE_JMSC"),
1780 + MTK_FUNCTION(7, "DBG_MON_A[23]"),
1781 + MTK_FUNCTION(14, "PCIE2_PERST_N")
1782 + ),
1783 + MTK_PIN(
1784 + PINCTRL_PIN(30, "I2S5_LRCK"),
1785 + NULL, "mt2701",
1786 + MTK_EINT_FUNCTION(0, 12),
1787 + MTK_FUNCTION(0, "GPIO30"),
1788 + MTK_FUNCTION(1, "I2S5_LRCK"),
1789 + MTK_FUNCTION(3, "PCM_SYNC"),
1790 + MTK_FUNCTION(4, "ANT_SEL1")
1791 + ),
1792 + MTK_PIN(
1793 + PINCTRL_PIN(31, "I2S5_MCLK"),
1794 + NULL, "mt2701",
1795 + MTK_EINT_FUNCTION(0, 13),
1796 + MTK_FUNCTION(0, "GPIO31"),
1797 + MTK_FUNCTION(1, "I2S5_MCLK"),
1798 + MTK_FUNCTION(4, "ANT_SEL0")
1799 + ),
1800 + MTK_PIN(
1801 + PINCTRL_PIN(32, "I2S5_DATA"),
1802 + NULL, "mt2701",
1803 + MTK_EINT_FUNCTION(0, 14),
1804 + MTK_FUNCTION(0, "GPIO32"),
1805 + MTK_FUNCTION(1, "I2S5_DATA"),
1806 + MTK_FUNCTION(2, "I2S5_DATA_BYPS"),
1807 + MTK_FUNCTION(3, "PCM_TX"),
1808 + MTK_FUNCTION(4, "ANT_SEL3")
1809 + ),
1810 + MTK_PIN(
1811 + PINCTRL_PIN(33, "I2S1_DATA"),
1812 + NULL, "mt2701",
1813 + MTK_EINT_FUNCTION(0, 15),
1814 + MTK_FUNCTION(0, "GPIO33"),
1815 + MTK_FUNCTION(1, "I2S1_DATA"),
1816 + MTK_FUNCTION(2, "I2S1_DATA_BYPS"),
1817 + MTK_FUNCTION(3, "PCM_TX"),
1818 + MTK_FUNCTION(4, "IMG_TEST_CK"),
1819 + MTK_FUNCTION(5, "G1_RXD0"),
1820 + MTK_FUNCTION(6, "WCN_PCM_TX"),
1821 + MTK_FUNCTION(7, "DBG_MON_B[8]")
1822 + ),
1823 + MTK_PIN(
1824 + PINCTRL_PIN(34, "I2S1_DATA_IN"),
1825 + NULL, "mt2701",
1826 + MTK_EINT_FUNCTION(0, 16),
1827 + MTK_FUNCTION(0, "GPIO34"),
1828 + MTK_FUNCTION(1, "I2S1_DATA_IN"),
1829 + MTK_FUNCTION(3, "PCM_RX"),
1830 + MTK_FUNCTION(4, "VDEC_TEST_CK"),
1831 + MTK_FUNCTION(5, "G1_RXD1"),
1832 + MTK_FUNCTION(6, "WCN_PCM_RX"),
1833 + MTK_FUNCTION(7, "DBG_MON_B[7]")
1834 + ),
1835 + MTK_PIN(
1836 + PINCTRL_PIN(35, "I2S1_BCK"),
1837 + NULL, "mt2701",
1838 + MTK_EINT_FUNCTION(0, 17),
1839 + MTK_FUNCTION(0, "GPIO35"),
1840 + MTK_FUNCTION(1, "I2S1_BCK"),
1841 + MTK_FUNCTION(3, "PCM_CLK0"),
1842 + MTK_FUNCTION(5, "G1_RXD2"),
1843 + MTK_FUNCTION(6, "WCN_PCM_CLKO"),
1844 + MTK_FUNCTION(7, "DBG_MON_B[9]")
1845 + ),
1846 + MTK_PIN(
1847 + PINCTRL_PIN(36, "I2S1_LRCK"),
1848 + NULL, "mt2701",
1849 + MTK_EINT_FUNCTION(0, 18),
1850 + MTK_FUNCTION(0, "GPIO36"),
1851 + MTK_FUNCTION(1, "I2S1_LRCK"),
1852 + MTK_FUNCTION(3, "PCM_SYNC"),
1853 + MTK_FUNCTION(5, "G1_RXD3"),
1854 + MTK_FUNCTION(6, "WCN_PCM_SYNC"),
1855 + MTK_FUNCTION(7, "DBG_MON_B[10]")
1856 + ),
1857 + MTK_PIN(
1858 + PINCTRL_PIN(37, "I2S1_MCLK"),
1859 + NULL, "mt2701",
1860 + MTK_EINT_FUNCTION(0, 19),
1861 + MTK_FUNCTION(0, "GPIO37"),
1862 + MTK_FUNCTION(1, "I2S1_MCLK"),
1863 + MTK_FUNCTION(5, "G1_RXDV"),
1864 + MTK_FUNCTION(7, "DBG_MON_B[11]")
1865 + ),
1866 + MTK_PIN(
1867 + PINCTRL_PIN(38, "I2S2_DATA"),
1868 + NULL, "mt2701",
1869 + MTK_EINT_FUNCTION(0, 20),
1870 + MTK_FUNCTION(0, "GPIO38"),
1871 + MTK_FUNCTION(2, "I2S2_DATA_BYPS"),
1872 + MTK_FUNCTION(3, "PCM_TX"),
1873 + MTK_FUNCTION(4, "DMIC_DAT0")
1874 + ),
1875 + MTK_PIN(
1876 + PINCTRL_PIN(39, "JTMS"),
1877 + NULL, "mt2701",
1878 + MTK_EINT_FUNCTION(0, 21),
1879 + MTK_FUNCTION(0, "GPIO39"),
1880 + MTK_FUNCTION(1, "JTMS"),
1881 + MTK_FUNCTION(2, "CONN_MCU_TMS"),
1882 + MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC"),
1883 + MTK_FUNCTION(4, "DFD_TMS_XI")
1884 + ),
1885 + MTK_PIN(
1886 + PINCTRL_PIN(40, "JTCK"),
1887 + NULL, "mt2701",
1888 + MTK_EINT_FUNCTION(0, 22),
1889 + MTK_FUNCTION(0, "GPIO40"),
1890 + MTK_FUNCTION(1, "JTCK"),
1891 + MTK_FUNCTION(2, "CONN_MCU_TCK1"),
1892 + MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC"),
1893 + MTK_FUNCTION(4, "DFD_TCK_XI")
1894 + ),
1895 + MTK_PIN(
1896 + PINCTRL_PIN(41, "JTDI"),
1897 + NULL, "mt2701",
1898 + MTK_EINT_FUNCTION(0, 23),
1899 + MTK_FUNCTION(0, "GPIO41"),
1900 + MTK_FUNCTION(1, "JTDI"),
1901 + MTK_FUNCTION(2, "CONN_MCU_TDI"),
1902 + MTK_FUNCTION(4, "DFD_TDI_XI")
1903 + ),
1904 + MTK_PIN(
1905 + PINCTRL_PIN(42, "JTDO"),
1906 + NULL, "mt2701",
1907 + MTK_EINT_FUNCTION(0, 24),
1908 + MTK_FUNCTION(0, "GPIO42"),
1909 + MTK_FUNCTION(1, "JTDO"),
1910 + MTK_FUNCTION(2, "CONN_MCU_TDO"),
1911 + MTK_FUNCTION(4, "DFD_TDO")
1912 + ),
1913 + MTK_PIN(
1914 + PINCTRL_PIN(43, "NCLE"),
1915 + NULL, "mt2701",
1916 + MTK_EINT_FUNCTION(0, 25),
1917 + MTK_FUNCTION(0, "GPIO43"),
1918 + MTK_FUNCTION(1, "NCLE"),
1919 + MTK_FUNCTION(2, "EXT_XCS2")
1920 + ),
1921 + MTK_PIN(
1922 + PINCTRL_PIN(44, "NCEB1"),
1923 + NULL, "mt2701",
1924 + MTK_EINT_FUNCTION(0, 26),
1925 + MTK_FUNCTION(0, "GPIO44"),
1926 + MTK_FUNCTION(1, "NCEB1"),
1927 + MTK_FUNCTION(2, "IDDIG")
1928 + ),
1929 + MTK_PIN(
1930 + PINCTRL_PIN(45, "NCEB0"),
1931 + NULL, "mt2701",
1932 + MTK_EINT_FUNCTION(0, 27),
1933 + MTK_FUNCTION(0, "GPIO45"),
1934 + MTK_FUNCTION(1, "NCEB0"),
1935 + MTK_FUNCTION(2, "DRV_VBUS")
1936 + ),
1937 + MTK_PIN(
1938 + PINCTRL_PIN(46, "IR"),
1939 + NULL, "mt2701",
1940 + MTK_EINT_FUNCTION(0, 28),
1941 + MTK_FUNCTION(0, "GPIO46"),
1942 + MTK_FUNCTION(1, "IR")
1943 + ),
1944 + MTK_PIN(
1945 + PINCTRL_PIN(47, "NREB"),
1946 + NULL, "mt2701",
1947 + MTK_EINT_FUNCTION(0, 29),
1948 + MTK_FUNCTION(0, "GPIO47"),
1949 + MTK_FUNCTION(1, "NREB"),
1950 + MTK_FUNCTION(2, "IDDIG_P1")
1951 + ),
1952 + MTK_PIN(
1953 + PINCTRL_PIN(48, "NRNB"),
1954 + NULL, "mt2701",
1955 + MTK_EINT_FUNCTION(0, 30),
1956 + MTK_FUNCTION(0, "GPIO48"),
1957 + MTK_FUNCTION(1, "NRNB"),
1958 + MTK_FUNCTION(2, "DRV_VBUS_P1")
1959 + ),
1960 + MTK_PIN(
1961 + PINCTRL_PIN(49, "I2S0_DATA"),
1962 + NULL, "mt2701",
1963 + MTK_EINT_FUNCTION(0, 31),
1964 + MTK_FUNCTION(0, "GPIO49"),
1965 + MTK_FUNCTION(1, "I2S0_DATA"),
1966 + MTK_FUNCTION(2, "I2S0_DATA_BYPS"),
1967 + MTK_FUNCTION(3, "PCM_TX"),
1968 + MTK_FUNCTION(6, "WCN_I2S_DO"),
1969 + MTK_FUNCTION(7, "DBG_MON_B[3]")
1970 + ),
1971 + MTK_PIN(
1972 + PINCTRL_PIN(50, "I2S2_BCK"),
1973 + NULL, "mt2701",
1974 + MTK_EINT_FUNCTION(0, 32),
1975 + MTK_FUNCTION(0, "GPIO50"),
1976 + MTK_FUNCTION(1, "I2S2_BCK"),
1977 + MTK_FUNCTION(3, "PCM_CLK0"),
1978 + MTK_FUNCTION(4, "DMIC_SCK1")
1979 + ),
1980 + MTK_PIN(
1981 + PINCTRL_PIN(51, "I2S2_DATA_IN"),
1982 + NULL, "mt2701",
1983 + MTK_EINT_FUNCTION(0, 33),
1984 + MTK_FUNCTION(0, "GPIO51"),
1985 + MTK_FUNCTION(1, "I2S2_DATA_IN"),
1986 + MTK_FUNCTION(3, "PCM_RX"),
1987 + MTK_FUNCTION(4, "DMIC_SCK0")
1988 + ),
1989 + MTK_PIN(
1990 + PINCTRL_PIN(52, "I2S2_LRCK"),
1991 + NULL, "mt2701",
1992 + MTK_EINT_FUNCTION(0, 34),
1993 + MTK_FUNCTION(0, "GPIO52"),
1994 + MTK_FUNCTION(1, "I2S2_LRCK"),
1995 + MTK_FUNCTION(3, "PCM_SYNC"),
1996 + MTK_FUNCTION(4, "DMIC_DAT1")
1997 + ),
1998 + MTK_PIN(
1999 + PINCTRL_PIN(53, "SPI0_CSN"),
2000 + NULL, "mt2701",
2001 + MTK_EINT_FUNCTION(0, 35),
2002 + MTK_FUNCTION(0, "GPIO53"),
2003 + MTK_FUNCTION(1, "SPI0_CS"),
2004 + MTK_FUNCTION(3, "SPDIF"),
2005 + MTK_FUNCTION(4, "ADC_CK"),
2006 + MTK_FUNCTION(5, "PWM1"),
2007 + MTK_FUNCTION(7, "DBG_MON_A[7]")
2008 + ),
2009 + MTK_PIN(
2010 + PINCTRL_PIN(54, "SPI0_CK"),
2011 + NULL, "mt2701",
2012 + MTK_EINT_FUNCTION(0, 36),
2013 + MTK_FUNCTION(0, "GPIO54"),
2014 + MTK_FUNCTION(1, "SPI0_CK"),
2015 + MTK_FUNCTION(3, "SPDIF_IN1"),
2016 + MTK_FUNCTION(4, "ADC_DAT_IN"),
2017 + MTK_FUNCTION(7, "DBG_MON_A[10]")
2018 + ),
2019 + MTK_PIN(
2020 + PINCTRL_PIN(55, "SPI0_MI"),
2021 + NULL, "mt2701",
2022 + MTK_EINT_FUNCTION(0, 37),
2023 + MTK_FUNCTION(0, "GPIO55"),
2024 + MTK_FUNCTION(1, "SPI0_MI"),
2025 + MTK_FUNCTION(2, "SPI0_MO"),
2026 + MTK_FUNCTION(3, "MSDC1_WP"),
2027 + MTK_FUNCTION(4, "ADC_WS"),
2028 + MTK_FUNCTION(5, "PWM2"),
2029 + MTK_FUNCTION(7, "DBG_MON_A[8]")
2030 + ),
2031 + MTK_PIN(
2032 + PINCTRL_PIN(56, "SPI0_MO"),
2033 + NULL, "mt2701",
2034 + MTK_EINT_FUNCTION(0, 38),
2035 + MTK_FUNCTION(0, "GPIO56"),
2036 + MTK_FUNCTION(1, "SPI0_MO"),
2037 + MTK_FUNCTION(2, "SPI0_MI"),
2038 + MTK_FUNCTION(3, "SPDIF_IN0"),
2039 + MTK_FUNCTION(7, "DBG_MON_A[9]")
2040 + ),
2041 + MTK_PIN(
2042 + PINCTRL_PIN(57, "SDA1"),
2043 + NULL, "mt2701",
2044 + MTK_EINT_FUNCTION(0, 39),
2045 + MTK_FUNCTION(0, "GPIO57"),
2046 + MTK_FUNCTION(1, "SDA1")
2047 + ),
2048 + MTK_PIN(
2049 + PINCTRL_PIN(58, "SCL1"),
2050 + NULL, "mt2701",
2051 + MTK_EINT_FUNCTION(0, 40),
2052 + MTK_FUNCTION(0, "GPIO58"),
2053 + MTK_FUNCTION(1, "SCL1")
2054 + ),
2055 + MTK_PIN(
2056 + PINCTRL_PIN(59, "RAMBUF_I_CLK"),
2057 + NULL, "mt2701",
2058 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2059 + MTK_FUNCTION(0, "GPIO59"),
2060 + MTK_FUNCTION(1, "RAMBUF_I_CLK")
2061 + ),
2062 + MTK_PIN(
2063 + PINCTRL_PIN(60, "WB_RSTB"),
2064 + NULL, "mt2701",
2065 + MTK_EINT_FUNCTION(0, 41),
2066 + MTK_FUNCTION(0, "GPIO60"),
2067 + MTK_FUNCTION(1, "WB_RSTB"),
2068 + MTK_FUNCTION(7, "DBG_MON_A[11]")
2069 + ),
2070 + MTK_PIN(
2071 + PINCTRL_PIN(61, "F2W_DATA"),
2072 + NULL, "mt2701",
2073 + MTK_EINT_FUNCTION(0, 42),
2074 + MTK_FUNCTION(0, "GPIO61"),
2075 + MTK_FUNCTION(1, "F2W_DATA"),
2076 + MTK_FUNCTION(7, "DBG_MON_A[16]")
2077 + ),
2078 + MTK_PIN(
2079 + PINCTRL_PIN(62, "F2W_CLK"),
2080 + NULL, "mt2701",
2081 + MTK_EINT_FUNCTION(0, 43),
2082 + MTK_FUNCTION(0, "GPIO62"),
2083 + MTK_FUNCTION(1, "F2W_CK"),
2084 + MTK_FUNCTION(7, "DBG_MON_A[15]")
2085 + ),
2086 + MTK_PIN(
2087 + PINCTRL_PIN(63, "WB_SCLK"),
2088 + NULL, "mt2701",
2089 + MTK_EINT_FUNCTION(0, 44),
2090 + MTK_FUNCTION(0, "GPIO63"),
2091 + MTK_FUNCTION(1, "WB_SCLK"),
2092 + MTK_FUNCTION(7, "DBG_MON_A[13]")
2093 + ),
2094 + MTK_PIN(
2095 + PINCTRL_PIN(64, "WB_SDATA"),
2096 + NULL, "mt2701",
2097 + MTK_EINT_FUNCTION(0, 45),
2098 + MTK_FUNCTION(0, "GPIO64"),
2099 + MTK_FUNCTION(1, "WB_SDATA"),
2100 + MTK_FUNCTION(7, "DBG_MON_A[12]")
2101 + ),
2102 + MTK_PIN(
2103 + PINCTRL_PIN(65, "WB_SEN"),
2104 + NULL, "mt2701",
2105 + MTK_EINT_FUNCTION(0, 46),
2106 + MTK_FUNCTION(0, "GPIO65"),
2107 + MTK_FUNCTION(1, "WB_SEN"),
2108 + MTK_FUNCTION(7, "DBG_MON_A[14]")
2109 + ),
2110 + MTK_PIN(
2111 + PINCTRL_PIN(66, "WB_CRTL0"),
2112 + NULL, "mt2701",
2113 + MTK_EINT_FUNCTION(0, 47),
2114 + MTK_FUNCTION(0, "GPIO66"),
2115 + MTK_FUNCTION(1, "WB_CRTL0"),
2116 + MTK_FUNCTION(5, "DFD_NTRST_XI"),
2117 + MTK_FUNCTION(7, "DBG_MON_A[17]")
2118 + ),
2119 + MTK_PIN(
2120 + PINCTRL_PIN(67, "WB_CRTL1"),
2121 + NULL, "mt2701",
2122 + MTK_EINT_FUNCTION(0, 48),
2123 + MTK_FUNCTION(0, "GPIO67"),
2124 + MTK_FUNCTION(1, "WB_CRTL1"),
2125 + MTK_FUNCTION(5, "DFD_TMS_XI"),
2126 + MTK_FUNCTION(7, "DBG_MON_A[18]")
2127 + ),
2128 + MTK_PIN(
2129 + PINCTRL_PIN(68, "WB_CRTL2"),
2130 + NULL, "mt2701",
2131 + MTK_EINT_FUNCTION(0, 49),
2132 + MTK_FUNCTION(0, "GPIO68"),
2133 + MTK_FUNCTION(1, "WB_CRTL2"),
2134 + MTK_FUNCTION(5, "DFD_TCK_XI"),
2135 + MTK_FUNCTION(7, "DBG_MON_A[19]")
2136 + ),
2137 + MTK_PIN(
2138 + PINCTRL_PIN(69, "WB_CRTL3"),
2139 + NULL, "mt2701",
2140 + MTK_EINT_FUNCTION(0, 50),
2141 + MTK_FUNCTION(0, "GPIO69"),
2142 + MTK_FUNCTION(1, "WB_CRTL3"),
2143 + MTK_FUNCTION(5, "DFD_TDI_XI"),
2144 + MTK_FUNCTION(7, "DBG_MON_A[20]")
2145 + ),
2146 + MTK_PIN(
2147 + PINCTRL_PIN(70, "WB_CRTL4"),
2148 + NULL, "mt2701",
2149 + MTK_EINT_FUNCTION(0, 51),
2150 + MTK_FUNCTION(0, "GPIO70"),
2151 + MTK_FUNCTION(1, "WB_CRTL4"),
2152 + MTK_FUNCTION(5, "DFD_TDO"),
2153 + MTK_FUNCTION(7, "DBG_MON_A[21]")
2154 + ),
2155 + MTK_PIN(
2156 + PINCTRL_PIN(71, "WB_CRTL5"),
2157 + NULL, "mt2701",
2158 + MTK_EINT_FUNCTION(0, 52),
2159 + MTK_FUNCTION(0, "GPIO71"),
2160 + MTK_FUNCTION(1, "WB_CRTL5"),
2161 + MTK_FUNCTION(7, "DBG_MON_A[22]")
2162 + ),
2163 + MTK_PIN(
2164 + PINCTRL_PIN(72, "I2S0_DATA_IN"),
2165 + NULL, "mt2701",
2166 + MTK_EINT_FUNCTION(0, 53),
2167 + MTK_FUNCTION(0, "GPIO72"),
2168 + MTK_FUNCTION(1, "I2S0_DATA_IN"),
2169 + MTK_FUNCTION(3, "PCM_RX"),
2170 + MTK_FUNCTION(4, "PWM0"),
2171 + MTK_FUNCTION(5, "DISP_PWM"),
2172 + MTK_FUNCTION(6, "WCN_I2S_DI"),
2173 + MTK_FUNCTION(7, "DBG_MON_B[2]")
2174 + ),
2175 + MTK_PIN(
2176 + PINCTRL_PIN(73, "I2S0_LRCK"),
2177 + NULL, "mt2701",
2178 + MTK_EINT_FUNCTION(0, 54),
2179 + MTK_FUNCTION(0, "GPIO73"),
2180 + MTK_FUNCTION(1, "I2S0_LRCK"),
2181 + MTK_FUNCTION(3, "PCM_SYNC"),
2182 + MTK_FUNCTION(6, "WCN_I2S_LRCK"),
2183 + MTK_FUNCTION(7, "DBG_MON_B[5]")
2184 + ),
2185 + MTK_PIN(
2186 + PINCTRL_PIN(74, "I2S0_BCK"),
2187 + NULL, "mt2701",
2188 + MTK_EINT_FUNCTION(0, 55),
2189 + MTK_FUNCTION(0, "GPIO74"),
2190 + MTK_FUNCTION(1, "I2S0_BCK"),
2191 + MTK_FUNCTION(3, "PCM_CLK0"),
2192 + MTK_FUNCTION(6, "WCN_I2S_BCK"),
2193 + MTK_FUNCTION(7, "DBG_MON_B[4]")
2194 + ),
2195 + MTK_PIN(
2196 + PINCTRL_PIN(75, "SDA0"),
2197 + NULL, "mt2701",
2198 + MTK_EINT_FUNCTION(0, 56),
2199 + MTK_FUNCTION(0, "GPIO75"),
2200 + MTK_FUNCTION(1, "SDA0")
2201 + ),
2202 + MTK_PIN(
2203 + PINCTRL_PIN(76, "SCL0"),
2204 + NULL, "mt2701",
2205 + MTK_EINT_FUNCTION(0, 57),
2206 + MTK_FUNCTION(0, "GPIO76"),
2207 + MTK_FUNCTION(1, "SCL0")
2208 + ),
2209 + MTK_PIN(
2210 + PINCTRL_PIN(77, "SDA2"),
2211 + NULL, "mt2701",
2212 + MTK_EINT_FUNCTION(0, 58),
2213 + MTK_FUNCTION(0, "GPIO77"),
2214 + MTK_FUNCTION(1, "SDA2")
2215 + ),
2216 + MTK_PIN(
2217 + PINCTRL_PIN(78, "SCL2"),
2218 + NULL, "mt2701",
2219 + MTK_EINT_FUNCTION(0, 59),
2220 + MTK_FUNCTION(0, "GPIO78"),
2221 + MTK_FUNCTION(1, "SCL2")
2222 + ),
2223 + MTK_PIN(
2224 + PINCTRL_PIN(79, "URXD0"),
2225 + NULL, "mt2701",
2226 + MTK_EINT_FUNCTION(0, 60),
2227 + MTK_FUNCTION(0, "GPIO79"),
2228 + MTK_FUNCTION(1, "URXD0"),
2229 + MTK_FUNCTION(2, "UTXD0")
2230 + ),
2231 + MTK_PIN(
2232 + PINCTRL_PIN(80, "UTXD0"),
2233 + NULL, "mt2701",
2234 + MTK_EINT_FUNCTION(0, 61),
2235 + MTK_FUNCTION(0, "GPIO80"),
2236 + MTK_FUNCTION(1, "UTXD0"),
2237 + MTK_FUNCTION(2, "URXD0")
2238 + ),
2239 + MTK_PIN(
2240 + PINCTRL_PIN(81, "URXD1"),
2241 + NULL, "mt2701",
2242 + MTK_EINT_FUNCTION(0, 62),
2243 + MTK_FUNCTION(0, "GPIO81"),
2244 + MTK_FUNCTION(1, "URXD1"),
2245 + MTK_FUNCTION(2, "UTXD1")
2246 + ),
2247 + MTK_PIN(
2248 + PINCTRL_PIN(82, "UTXD1"),
2249 + NULL, "mt2701",
2250 + MTK_EINT_FUNCTION(0, 63),
2251 + MTK_FUNCTION(0, "GPIO82"),
2252 + MTK_FUNCTION(1, "UTXD1"),
2253 + MTK_FUNCTION(2, "URXD1")
2254 + ),
2255 + MTK_PIN(
2256 + PINCTRL_PIN(83, "LCM_RST"),
2257 + NULL, "mt2701",
2258 + MTK_EINT_FUNCTION(0, 64),
2259 + MTK_FUNCTION(0, "GPIO83"),
2260 + MTK_FUNCTION(1, "LCM_RST"),
2261 + MTK_FUNCTION(2, "VDAC_CK_XI"),
2262 + MTK_FUNCTION(7, "DBG_MON_B[1]")
2263 + ),
2264 + MTK_PIN(
2265 + PINCTRL_PIN(84, "DSI_TE"),
2266 + NULL, "mt2701",
2267 + MTK_EINT_FUNCTION(0, 65),
2268 + MTK_FUNCTION(0, "GPIO84"),
2269 + MTK_FUNCTION(1, "DSI_TE"),
2270 + MTK_FUNCTION(7, "DBG_MON_B[0]")
2271 + ),
2272 + MTK_PIN(
2273 + PINCTRL_PIN(85, "MSDC2_CMD"),
2274 + NULL, "mt2701",
2275 + MTK_EINT_FUNCTION(0, 66),
2276 + MTK_FUNCTION(0, "GPIO85"),
2277 + MTK_FUNCTION(1, "MSDC2_CMD"),
2278 + MTK_FUNCTION(2, "ANT_SEL0"),
2279 + MTK_FUNCTION(3, "SDA1"),
2280 + MTK_FUNCTION(6, "I2SOUT_BCK")
2281 + ),
2282 + MTK_PIN(
2283 + PINCTRL_PIN(86, "MSDC2_CLK"),
2284 + NULL, "mt2701",
2285 + MTK_EINT_FUNCTION(0, 67),
2286 + MTK_FUNCTION(0, "GPIO86"),
2287 + MTK_FUNCTION(1, "MSDC2_CLK"),
2288 + MTK_FUNCTION(2, "ANT_SEL1"),
2289 + MTK_FUNCTION(3, "SCL1"),
2290 + MTK_FUNCTION(6, "I2SOUT_LRCK")
2291 + ),
2292 + MTK_PIN(
2293 + PINCTRL_PIN(87, "MSDC2_DAT0"),
2294 + NULL, "mt2701",
2295 + MTK_EINT_FUNCTION(0, 68),
2296 + MTK_FUNCTION(0, "GPIO87"),
2297 + MTK_FUNCTION(1, "MSDC2_DAT0"),
2298 + MTK_FUNCTION(2, "ANT_SEL2"),
2299 + MTK_FUNCTION(5, "UTXD0"),
2300 + MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
2301 + ),
2302 + MTK_PIN(
2303 + PINCTRL_PIN(88, "MSDC2_DAT1"),
2304 + NULL, "mt2701",
2305 + MTK_EINT_FUNCTION(0, 71),
2306 + MTK_FUNCTION(0, "GPIO88"),
2307 + MTK_FUNCTION(1, "MSDC2_DAT1"),
2308 + MTK_FUNCTION(2, "ANT_SEL3"),
2309 + MTK_FUNCTION(3, "PWM0"),
2310 + MTK_FUNCTION(5, "URXD0"),
2311 + MTK_FUNCTION(6, "PWM1")
2312 + ),
2313 + MTK_PIN(
2314 + PINCTRL_PIN(89, "MSDC2_DAT2"),
2315 + NULL, "mt2701",
2316 + MTK_EINT_FUNCTION(0, 72),
2317 + MTK_FUNCTION(0, "GPIO89"),
2318 + MTK_FUNCTION(1, "MSDC2_DAT2"),
2319 + MTK_FUNCTION(2, "ANT_SEL4"),
2320 + MTK_FUNCTION(3, "SDA2"),
2321 + MTK_FUNCTION(5, "UTXD1"),
2322 + MTK_FUNCTION(6, "PWM2")
2323 + ),
2324 + MTK_PIN(
2325 + PINCTRL_PIN(90, "MSDC2_DAT3"),
2326 + NULL, "mt2701",
2327 + MTK_EINT_FUNCTION(0, 73),
2328 + MTK_FUNCTION(0, "GPIO90"),
2329 + MTK_FUNCTION(1, "MSDC2_DAT3"),
2330 + MTK_FUNCTION(2, "ANT_SEL5"),
2331 + MTK_FUNCTION(3, "SCL2"),
2332 + MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
2333 + MTK_FUNCTION(5, "URXD1"),
2334 + MTK_FUNCTION(6, "PWM3")
2335 + ),
2336 + MTK_PIN(
2337 + PINCTRL_PIN(91, "TDN3"),
2338 + NULL, "mt2701",
2339 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2340 + MTK_FUNCTION(0, "GPI91"),
2341 + MTK_FUNCTION(1, "TDN3")
2342 + ),
2343 + MTK_PIN(
2344 + PINCTRL_PIN(92, "TDP3"),
2345 + NULL, "mt2701",
2346 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2347 + MTK_FUNCTION(0, "GPI92"),
2348 + MTK_FUNCTION(1, "TDP3")
2349 + ),
2350 + MTK_PIN(
2351 + PINCTRL_PIN(93, "TDN2"),
2352 + NULL, "mt2701",
2353 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2354 + MTK_FUNCTION(0, "GPI93"),
2355 + MTK_FUNCTION(1, "TDN2")
2356 + ),
2357 + MTK_PIN(
2358 + PINCTRL_PIN(94, "TDP2"),
2359 + NULL, "mt2701",
2360 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2361 + MTK_FUNCTION(0, "GPI94"),
2362 + MTK_FUNCTION(1, "TDP2")
2363 + ),
2364 + MTK_PIN(
2365 + PINCTRL_PIN(95, "TCN"),
2366 + NULL, "mt2701",
2367 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2368 + MTK_FUNCTION(0, "GPI95"),
2369 + MTK_FUNCTION(1, "TCN")
2370 + ),
2371 + MTK_PIN(
2372 + PINCTRL_PIN(96, "TCP"),
2373 + NULL, "mt2701",
2374 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2375 + MTK_FUNCTION(0, "GPI96"),
2376 + MTK_FUNCTION(1, "TCP")
2377 + ),
2378 + MTK_PIN(
2379 + PINCTRL_PIN(97, "TDN1"),
2380 + NULL, "mt2701",
2381 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2382 + MTK_FUNCTION(0, "GPI97"),
2383 + MTK_FUNCTION(1, "TDN1")
2384 + ),
2385 + MTK_PIN(
2386 + PINCTRL_PIN(98, "TDP1"),
2387 + NULL, "mt2701",
2388 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2389 + MTK_FUNCTION(0, "GPI98"),
2390 + MTK_FUNCTION(1, "TDP1")
2391 + ),
2392 + MTK_PIN(
2393 + PINCTRL_PIN(99, "TDN0"),
2394 + NULL, "mt2701",
2395 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2396 + MTK_FUNCTION(0, "GPI99"),
2397 + MTK_FUNCTION(1, "TDN0")
2398 + ),
2399 + MTK_PIN(
2400 + PINCTRL_PIN(100, "TDP0"),
2401 + NULL, "mt2701",
2402 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2403 + MTK_FUNCTION(0, "GPI100"),
2404 + MTK_FUNCTION(1, "TDP0")
2405 + ),
2406 + MTK_PIN(
2407 + PINCTRL_PIN(101, "SPI2_CSN"),
2408 + NULL, "mt2701",
2409 + MTK_EINT_FUNCTION(0, 74),
2410 + MTK_FUNCTION(0, "GPIO101"),
2411 + MTK_FUNCTION(1, "SPI2_CS"),
2412 + MTK_FUNCTION(3, "SCL3"),
2413 + MTK_FUNCTION(4, "KROW0")
2414 + ),
2415 + MTK_PIN(
2416 + PINCTRL_PIN(102, "SPI2_MI"),
2417 + NULL, "mt2701",
2418 + MTK_EINT_FUNCTION(0, 75),
2419 + MTK_FUNCTION(0, "GPIO102"),
2420 + MTK_FUNCTION(1, "SPI2_MI"),
2421 + MTK_FUNCTION(2, "SPI2_MO"),
2422 + MTK_FUNCTION(3, "SDA3"),
2423 + MTK_FUNCTION(4, "KROW1")
2424 + ),
2425 + MTK_PIN(
2426 + PINCTRL_PIN(103, "SPI2_MO"),
2427 + NULL, "mt2701",
2428 + MTK_EINT_FUNCTION(0, 76),
2429 + MTK_FUNCTION(0, "GPIO103"),
2430 + MTK_FUNCTION(1, "SPI2_MO"),
2431 + MTK_FUNCTION(2, "SPI2_MI"),
2432 + MTK_FUNCTION(3, "SCL3"),
2433 + MTK_FUNCTION(4, "KROW2")
2434 + ),
2435 + MTK_PIN(
2436 + PINCTRL_PIN(104, "SPI2_CLK"),
2437 + NULL, "mt2701",
2438 + MTK_EINT_FUNCTION(0, 77),
2439 + MTK_FUNCTION(0, "GPIO104"),
2440 + MTK_FUNCTION(1, "SPI2_CK"),
2441 + MTK_FUNCTION(3, "SDA3"),
2442 + MTK_FUNCTION(4, "KROW3")
2443 + ),
2444 + MTK_PIN(
2445 + PINCTRL_PIN(105, "MSDC1_CMD"),
2446 + NULL, "mt2701",
2447 + MTK_EINT_FUNCTION(0, 78),
2448 + MTK_FUNCTION(0, "GPIO105"),
2449 + MTK_FUNCTION(1, "MSDC1_CMD"),
2450 + MTK_FUNCTION(2, "ANT_SEL0"),
2451 + MTK_FUNCTION(3, "SDA1"),
2452 + MTK_FUNCTION(6, "I2SOUT_BCK"),
2453 + MTK_FUNCTION(7, "DBG_MON_B[27]")
2454 + ),
2455 + MTK_PIN(
2456 + PINCTRL_PIN(106, "MSDC1_CLK"),
2457 + NULL, "mt2701",
2458 + MTK_EINT_FUNCTION(0, 79),
2459 + MTK_FUNCTION(0, "GPIO106"),
2460 + MTK_FUNCTION(1, "MSDC1_CLK"),
2461 + MTK_FUNCTION(2, "ANT_SEL1"),
2462 + MTK_FUNCTION(3, "SCL1"),
2463 + MTK_FUNCTION(6, "I2SOUT_LRCK"),
2464 + MTK_FUNCTION(7, "DBG_MON_B[28]")
2465 + ),
2466 + MTK_PIN(
2467 + PINCTRL_PIN(107, "MSDC1_DAT0"),
2468 + NULL, "mt2701",
2469 + MTK_EINT_FUNCTION(0, 80),
2470 + MTK_FUNCTION(0, "GPIO107"),
2471 + MTK_FUNCTION(1, "MSDC1_DAT0"),
2472 + MTK_FUNCTION(2, "ANT_SEL2"),
2473 + MTK_FUNCTION(5, "UTXD0"),
2474 + MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
2475 + MTK_FUNCTION(7, "DBG_MON_B[26]")
2476 + ),
2477 + MTK_PIN(
2478 + PINCTRL_PIN(108, "MSDC1_DAT1"),
2479 + NULL, "mt2701",
2480 + MTK_EINT_FUNCTION(0, 81),
2481 + MTK_FUNCTION(0, "GPIO108"),
2482 + MTK_FUNCTION(1, "MSDC1_DAT1"),
2483 + MTK_FUNCTION(2, "ANT_SEL3"),
2484 + MTK_FUNCTION(3, "PWM0"),
2485 + MTK_FUNCTION(5, "URXD0"),
2486 + MTK_FUNCTION(6, "PWM1"),
2487 + MTK_FUNCTION(7, "DBG_MON_B[25]")
2488 + ),
2489 + MTK_PIN(
2490 + PINCTRL_PIN(109, "MSDC1_DAT2"),
2491 + NULL, "mt2701",
2492 + MTK_EINT_FUNCTION(0, 82),
2493 + MTK_FUNCTION(0, "GPIO109"),
2494 + MTK_FUNCTION(1, "MSDC1_DAT2"),
2495 + MTK_FUNCTION(2, "ANT_SEL4"),
2496 + MTK_FUNCTION(3, "SDA2"),
2497 + MTK_FUNCTION(5, "UTXD1"),
2498 + MTK_FUNCTION(6, "PWM2"),
2499 + MTK_FUNCTION(7, "DBG_MON_B[24]")
2500 + ),
2501 + MTK_PIN(
2502 + PINCTRL_PIN(110, "MSDC1_DAT3"),
2503 + NULL, "mt2701",
2504 + MTK_EINT_FUNCTION(0, 83),
2505 + MTK_FUNCTION(0, "GPIO110"),
2506 + MTK_FUNCTION(1, "MSDC1_DAT3"),
2507 + MTK_FUNCTION(2, "ANT_SEL5"),
2508 + MTK_FUNCTION(3, "SCL2"),
2509 + MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
2510 + MTK_FUNCTION(5, "URXD1"),
2511 + MTK_FUNCTION(6, "PWM3"),
2512 + MTK_FUNCTION(7, "DBG_MON_B[23]")
2513 + ),
2514 + MTK_PIN(
2515 + PINCTRL_PIN(111, "MSDC0_DAT7"),
2516 + NULL, "mt2701",
2517 + MTK_EINT_FUNCTION(0, 84),
2518 + MTK_FUNCTION(0, "GPIO111"),
2519 + MTK_FUNCTION(1, "MSDC0_DAT7"),
2520 + MTK_FUNCTION(4, "NLD7")
2521 + ),
2522 + MTK_PIN(
2523 + PINCTRL_PIN(112, "MSDC0_DAT6"),
2524 + NULL, "mt2701",
2525 + MTK_EINT_FUNCTION(0, 85),
2526 + MTK_FUNCTION(0, "GPIO112"),
2527 + MTK_FUNCTION(1, "MSDC0_DAT6"),
2528 + MTK_FUNCTION(4, "NLD6")
2529 + ),
2530 + MTK_PIN(
2531 + PINCTRL_PIN(113, "MSDC0_DAT5"),
2532 + NULL, "mt2701",
2533 + MTK_EINT_FUNCTION(0, 86),
2534 + MTK_FUNCTION(0, "GPIO113"),
2535 + MTK_FUNCTION(1, "MSDC0_DAT5"),
2536 + MTK_FUNCTION(4, "NLD5")
2537 + ),
2538 + MTK_PIN(
2539 + PINCTRL_PIN(114, "MSDC0_DAT4"),
2540 + NULL, "mt2701",
2541 + MTK_EINT_FUNCTION(0, 87),
2542 + MTK_FUNCTION(0, "GPIO114"),
2543 + MTK_FUNCTION(1, "MSDC0_DAT4"),
2544 + MTK_FUNCTION(4, "NLD4")
2545 + ),
2546 + MTK_PIN(
2547 + PINCTRL_PIN(115, "MSDC0_RSTB"),
2548 + NULL, "mt2701",
2549 + MTK_EINT_FUNCTION(0, 88),
2550 + MTK_FUNCTION(0, "GPIO115"),
2551 + MTK_FUNCTION(1, "MSDC0_RSTB"),
2552 + MTK_FUNCTION(4, "NLD8")
2553 + ),
2554 + MTK_PIN(
2555 + PINCTRL_PIN(116, "MSDC0_CMD"),
2556 + NULL, "mt2701",
2557 + MTK_EINT_FUNCTION(0, 89),
2558 + MTK_FUNCTION(0, "GPIO116"),
2559 + MTK_FUNCTION(1, "MSDC0_CMD"),
2560 + MTK_FUNCTION(4, "NALE")
2561 + ),
2562 + MTK_PIN(
2563 + PINCTRL_PIN(117, "MSDC0_CLK"),
2564 + NULL, "mt2701",
2565 + MTK_EINT_FUNCTION(0, 90),
2566 + MTK_FUNCTION(0, "GPIO117"),
2567 + MTK_FUNCTION(1, "MSDC0_CLK"),
2568 + MTK_FUNCTION(4, "NWEB")
2569 + ),
2570 + MTK_PIN(
2571 + PINCTRL_PIN(118, "MSDC0_DAT3"),
2572 + NULL, "mt2701",
2573 + MTK_EINT_FUNCTION(0, 91),
2574 + MTK_FUNCTION(0, "GPIO118"),
2575 + MTK_FUNCTION(1, "MSDC0_DAT3"),
2576 + MTK_FUNCTION(4, "NLD3")
2577 + ),
2578 + MTK_PIN(
2579 + PINCTRL_PIN(119, "MSDC0_DAT2"),
2580 + NULL, "mt2701",
2581 + MTK_EINT_FUNCTION(0, 92),
2582 + MTK_FUNCTION(0, "GPIO119"),
2583 + MTK_FUNCTION(1, "MSDC0_DAT2"),
2584 + MTK_FUNCTION(4, "NLD2")
2585 + ),
2586 + MTK_PIN(
2587 + PINCTRL_PIN(120, "MSDC0_DAT1"),
2588 + NULL, "mt2701",
2589 + MTK_EINT_FUNCTION(0, 93),
2590 + MTK_FUNCTION(0, "GPIO120"),
2591 + MTK_FUNCTION(1, "MSDC0_DAT1"),
2592 + MTK_FUNCTION(4, "NLD1")
2593 + ),
2594 + MTK_PIN(
2595 + PINCTRL_PIN(121, "MSDC0_DAT0"),
2596 + NULL, "mt2701",
2597 + MTK_EINT_FUNCTION(0, 94),
2598 + MTK_FUNCTION(0, "GPIO121"),
2599 + MTK_FUNCTION(1, "MSDC0_DAT0"),
2600 + MTK_FUNCTION(4, "NLD0"),
2601 + MTK_FUNCTION(5, "WATCHDOG")
2602 + ),
2603 + MTK_PIN(
2604 + PINCTRL_PIN(122, "CEC"),
2605 + NULL, "mt2701",
2606 + MTK_EINT_FUNCTION(0, 95),
2607 + MTK_FUNCTION(0, "GPIO122"),
2608 + MTK_FUNCTION(1, "CEC"),
2609 + MTK_FUNCTION(4, "SDA2"),
2610 + MTK_FUNCTION(5, "URXD0")
2611 + ),
2612 + MTK_PIN(
2613 + PINCTRL_PIN(123, "HTPLG"),
2614 + NULL, "mt2701",
2615 + MTK_EINT_FUNCTION(0, 96),
2616 + MTK_FUNCTION(0, "GPIO123"),
2617 + MTK_FUNCTION(1, "HTPLG"),
2618 + MTK_FUNCTION(4, "SCL2"),
2619 + MTK_FUNCTION(5, "UTXD0")
2620 + ),
2621 + MTK_PIN(
2622 + PINCTRL_PIN(124, "HDMISCK"),
2623 + NULL, "mt2701",
2624 + MTK_EINT_FUNCTION(0, 97),
2625 + MTK_FUNCTION(0, "GPIO124"),
2626 + MTK_FUNCTION(1, "HDMISCK"),
2627 + MTK_FUNCTION(4, "SDA1"),
2628 + MTK_FUNCTION(5, "PWM3")
2629 + ),
2630 + MTK_PIN(
2631 + PINCTRL_PIN(125, "HDMISD"),
2632 + NULL, "mt2701",
2633 + MTK_EINT_FUNCTION(0, 98),
2634 + MTK_FUNCTION(0, "GPIO125"),
2635 + MTK_FUNCTION(1, "HDMISD"),
2636 + MTK_FUNCTION(4, "SCL1"),
2637 + MTK_FUNCTION(5, "PWM4")
2638 + ),
2639 + MTK_PIN(
2640 + PINCTRL_PIN(126, "I2S0_MCLK"),
2641 + NULL, "mt2701",
2642 + MTK_EINT_FUNCTION(0, 99),
2643 + MTK_FUNCTION(0, "GPIO126"),
2644 + MTK_FUNCTION(1, "I2S0_MCLK"),
2645 + MTK_FUNCTION(6, "WCN_I2S_MCLK"),
2646 + MTK_FUNCTION(7, "DBG_MON_B[6]")
2647 + ),
2648 + MTK_PIN(
2649 + PINCTRL_PIN(127, "RAMBUF_IDATA0"),
2650 + NULL, "mt2701",
2651 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2652 + MTK_FUNCTION(0, "GPIO127"),
2653 + MTK_FUNCTION(1, "RAMBUF_IDATA0")
2654 + ),
2655 + MTK_PIN(
2656 + PINCTRL_PIN(128, "RAMBUF_IDATA1"),
2657 + NULL, "mt2701",
2658 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2659 + MTK_FUNCTION(0, "GPIO128"),
2660 + MTK_FUNCTION(1, "RAMBUF_IDATA1")
2661 + ),
2662 + MTK_PIN(
2663 + PINCTRL_PIN(129, "RAMBUF_IDATA2"),
2664 + NULL, "mt2701",
2665 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2666 + MTK_FUNCTION(0, "GPIO129"),
2667 + MTK_FUNCTION(1, "RAMBUF_IDATA2")
2668 + ),
2669 + MTK_PIN(
2670 + PINCTRL_PIN(130, "RAMBUF_IDATA3"),
2671 + NULL, "mt2701",
2672 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2673 + MTK_FUNCTION(0, "GPIO130"),
2674 + MTK_FUNCTION(1, "RAMBUF_IDATA3")
2675 + ),
2676 + MTK_PIN(
2677 + PINCTRL_PIN(131, "RAMBUF_IDATA4"),
2678 + NULL, "mt2701",
2679 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2680 + MTK_FUNCTION(0, "GPIO131"),
2681 + MTK_FUNCTION(1, "RAMBUF_IDATA4")
2682 + ),
2683 + MTK_PIN(
2684 + PINCTRL_PIN(132, "RAMBUF_IDATA5"),
2685 + NULL, "mt2701",
2686 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2687 + MTK_FUNCTION(0, "GPIO132"),
2688 + MTK_FUNCTION(1, "RAMBUF_IDATA5")
2689 + ),
2690 + MTK_PIN(
2691 + PINCTRL_PIN(133, "RAMBUF_IDATA6"),
2692 + NULL, "mt2701",
2693 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2694 + MTK_FUNCTION(0, "GPIO133"),
2695 + MTK_FUNCTION(1, "RAMBUF_IDATA6")
2696 + ),
2697 + MTK_PIN(
2698 + PINCTRL_PIN(134, "RAMBUF_IDATA7"),
2699 + NULL, "mt2701",
2700 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2701 + MTK_FUNCTION(0, "GPIO134"),
2702 + MTK_FUNCTION(1, "RAMBUF_IDATA7")
2703 + ),
2704 + MTK_PIN(
2705 + PINCTRL_PIN(135, "RAMBUF_IDATA8"),
2706 + NULL, "mt2701",
2707 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2708 + MTK_FUNCTION(0, "GPIO135"),
2709 + MTK_FUNCTION(1, "RAMBUF_IDATA8")
2710 + ),
2711 + MTK_PIN(
2712 + PINCTRL_PIN(136, "RAMBUF_IDATA9"),
2713 + NULL, "mt2701",
2714 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2715 + MTK_FUNCTION(0, "GPIO136"),
2716 + MTK_FUNCTION(1, "RAMBUF_IDATA9")
2717 + ),
2718 + MTK_PIN(
2719 + PINCTRL_PIN(137, "RAMBUF_IDATA10"),
2720 + NULL, "mt2701",
2721 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2722 + MTK_FUNCTION(0, "GPIO137"),
2723 + MTK_FUNCTION(1, "RAMBUF_IDATA10")
2724 + ),
2725 + MTK_PIN(
2726 + PINCTRL_PIN(138, "RAMBUF_IDATA11"),
2727 + NULL, "mt2701",
2728 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2729 + MTK_FUNCTION(0, "GPIO138"),
2730 + MTK_FUNCTION(1, "RAMBUF_IDATA11")
2731 + ),
2732 + MTK_PIN(
2733 + PINCTRL_PIN(139, "RAMBUF_IDATA12"),
2734 + NULL, "mt2701",
2735 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2736 + MTK_FUNCTION(0, "GPIO139"),
2737 + MTK_FUNCTION(1, "RAMBUF_IDATA12")
2738 + ),
2739 + MTK_PIN(
2740 + PINCTRL_PIN(140, "RAMBUF_IDATA13"),
2741 + NULL, "mt2701",
2742 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2743 + MTK_FUNCTION(0, "GPIO140"),
2744 + MTK_FUNCTION(1, "RAMBUF_IDATA13")
2745 + ),
2746 + MTK_PIN(
2747 + PINCTRL_PIN(141, "RAMBUF_IDATA14"),
2748 + NULL, "mt2701",
2749 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2750 + MTK_FUNCTION(0, "GPIO141"),
2751 + MTK_FUNCTION(1, "RAMBUF_IDATA14")
2752 + ),
2753 + MTK_PIN(
2754 + PINCTRL_PIN(142, "RAMBUF_IDATA15"),
2755 + NULL, "mt2701",
2756 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2757 + MTK_FUNCTION(0, "GPIO142"),
2758 + MTK_FUNCTION(1, "RAMBUF_IDATA15")
2759 + ),
2760 + MTK_PIN(
2761 + PINCTRL_PIN(143, "RAMBUF_ODATA0"),
2762 + NULL, "mt2701",
2763 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2764 + MTK_FUNCTION(0, "GPIO143"),
2765 + MTK_FUNCTION(1, "RAMBUF_ODATA0")
2766 + ),
2767 + MTK_PIN(
2768 + PINCTRL_PIN(144, "RAMBUF_ODATA1"),
2769 + NULL, "mt2701",
2770 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2771 + MTK_FUNCTION(0, "GPIO144"),
2772 + MTK_FUNCTION(1, "RAMBUF_ODATA1")
2773 + ),
2774 + MTK_PIN(
2775 + PINCTRL_PIN(145, "RAMBUF_ODATA2"),
2776 + NULL, "mt2701",
2777 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2778 + MTK_FUNCTION(0, "GPIO145"),
2779 + MTK_FUNCTION(1, "RAMBUF_ODATA2")
2780 + ),
2781 + MTK_PIN(
2782 + PINCTRL_PIN(146, "RAMBUF_ODATA3"),
2783 + NULL, "mt2701",
2784 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2785 + MTK_FUNCTION(0, "GPIO146"),
2786 + MTK_FUNCTION(1, "RAMBUF_ODATA3")
2787 + ),
2788 + MTK_PIN(
2789 + PINCTRL_PIN(147, "RAMBUF_ODATA4"),
2790 + NULL, "mt2701",
2791 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2792 + MTK_FUNCTION(0, "GPIO147"),
2793 + MTK_FUNCTION(1, "RAMBUF_ODATA4")
2794 + ),
2795 + MTK_PIN(
2796 + PINCTRL_PIN(148, "RAMBUF_ODATA5"),
2797 + NULL, "mt2701",
2798 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2799 + MTK_FUNCTION(0, "GPIO148"),
2800 + MTK_FUNCTION(1, "RAMBUF_ODATA5")
2801 + ),
2802 + MTK_PIN(
2803 + PINCTRL_PIN(149, "RAMBUF_ODATA6"),
2804 + NULL, "mt2701",
2805 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2806 + MTK_FUNCTION(0, "GPIO149"),
2807 + MTK_FUNCTION(1, "RAMBUF_ODATA6")
2808 + ),
2809 + MTK_PIN(
2810 + PINCTRL_PIN(150, "RAMBUF_ODATA7"),
2811 + NULL, "mt2701",
2812 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2813 + MTK_FUNCTION(0, "GPIO150"),
2814 + MTK_FUNCTION(1, "RAMBUF_ODATA7")
2815 + ),
2816 + MTK_PIN(
2817 + PINCTRL_PIN(151, "RAMBUF_ODATA8"),
2818 + NULL, "mt2701",
2819 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2820 + MTK_FUNCTION(0, "GPIO151"),
2821 + MTK_FUNCTION(1, "RAMBUF_ODATA8")
2822 + ),
2823 + MTK_PIN(
2824 + PINCTRL_PIN(152, "RAMBUF_ODATA9"),
2825 + NULL, "mt2701",
2826 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2827 + MTK_FUNCTION(0, "GPIO152"),
2828 + MTK_FUNCTION(1, "RAMBUF_ODATA9")
2829 + ),
2830 + MTK_PIN(
2831 + PINCTRL_PIN(153, "RAMBUF_ODATA10"),
2832 + NULL, "mt2701",
2833 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2834 + MTK_FUNCTION(0, "GPIO153"),
2835 + MTK_FUNCTION(1, "RAMBUF_ODATA10")
2836 + ),
2837 + MTK_PIN(
2838 + PINCTRL_PIN(154, "RAMBUF_ODATA11"),
2839 + NULL, "mt2701",
2840 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2841 + MTK_FUNCTION(0, "GPIO154"),
2842 + MTK_FUNCTION(1, "RAMBUF_ODATA11")
2843 + ),
2844 + MTK_PIN(
2845 + PINCTRL_PIN(155, "RAMBUF_ODATA12"),
2846 + NULL, "mt2701",
2847 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2848 + MTK_FUNCTION(0, "GPIO155"),
2849 + MTK_FUNCTION(1, "RAMBUF_ODATA12")
2850 + ),
2851 + MTK_PIN(
2852 + PINCTRL_PIN(156, "RAMBUF_ODATA13"),
2853 + NULL, "mt2701",
2854 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2855 + MTK_FUNCTION(0, "GPIO156"),
2856 + MTK_FUNCTION(1, "RAMBUF_ODATA13")
2857 + ),
2858 + MTK_PIN(
2859 + PINCTRL_PIN(157, "RAMBUF_ODATA14"),
2860 + NULL, "mt2701",
2861 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2862 + MTK_FUNCTION(0, "GPIO157"),
2863 + MTK_FUNCTION(1, "RAMBUF_ODATA14")
2864 + ),
2865 + MTK_PIN(
2866 + PINCTRL_PIN(158, "RAMBUF_ODATA15"),
2867 + NULL, "mt2701",
2868 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2869 + MTK_FUNCTION(0, "GPIO158"),
2870 + MTK_FUNCTION(1, "RAMBUF_ODATA15")
2871 + ),
2872 + MTK_PIN(
2873 + PINCTRL_PIN(159, "RAMBUF_BE0"),
2874 + NULL, "mt2701",
2875 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2876 + MTK_FUNCTION(0, "GPIO159"),
2877 + MTK_FUNCTION(1, "RAMBUF_BE0")
2878 + ),
2879 + MTK_PIN(
2880 + PINCTRL_PIN(160, "RAMBUF_BE1"),
2881 + NULL, "mt2701",
2882 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2883 + MTK_FUNCTION(0, "GPIO160"),
2884 + MTK_FUNCTION(1, "RAMBUF_BE1")
2885 + ),
2886 + MTK_PIN(
2887 + PINCTRL_PIN(161, "AP2PT_INT"),
2888 + NULL, "mt2701",
2889 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2890 + MTK_FUNCTION(0, "GPIO161"),
2891 + MTK_FUNCTION(1, "AP2PT_INT")
2892 + ),
2893 + MTK_PIN(
2894 + PINCTRL_PIN(162, "AP2PT_INT_CLR"),
2895 + NULL, "mt2701",
2896 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2897 + MTK_FUNCTION(0, "GPIO162"),
2898 + MTK_FUNCTION(1, "AP2PT_INT_CLR")
2899 + ),
2900 + MTK_PIN(
2901 + PINCTRL_PIN(163, "PT2AP_INT"),
2902 + NULL, "mt2701",
2903 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2904 + MTK_FUNCTION(0, "GPIO163"),
2905 + MTK_FUNCTION(1, "PT2AP_INT")
2906 + ),
2907 + MTK_PIN(
2908 + PINCTRL_PIN(164, "PT2AP_INT_CLR"),
2909 + NULL, "mt2701",
2910 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2911 + MTK_FUNCTION(0, "GPIO164"),
2912 + MTK_FUNCTION(1, "PT2AP_INT_CLR")
2913 + ),
2914 + MTK_PIN(
2915 + PINCTRL_PIN(165, "AP2UP_INT"),
2916 + NULL, "mt2701",
2917 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2918 + MTK_FUNCTION(0, "GPIO165"),
2919 + MTK_FUNCTION(1, "AP2UP_INT")
2920 + ),
2921 + MTK_PIN(
2922 + PINCTRL_PIN(166, "AP2UP_INT_CLR"),
2923 + NULL, "mt2701",
2924 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2925 + MTK_FUNCTION(0, "GPIO166"),
2926 + MTK_FUNCTION(1, "AP2UP_INT_CLR")
2927 + ),
2928 + MTK_PIN(
2929 + PINCTRL_PIN(167, "UP2AP_INT"),
2930 + NULL, "mt2701",
2931 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2932 + MTK_FUNCTION(0, "GPIO167"),
2933 + MTK_FUNCTION(1, "UP2AP_INT")
2934 + ),
2935 + MTK_PIN(
2936 + PINCTRL_PIN(168, "UP2AP_INT_CLR"),
2937 + NULL, "mt2701",
2938 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2939 + MTK_FUNCTION(0, "GPIO168"),
2940 + MTK_FUNCTION(1, "UP2AP_INT_CLR")
2941 + ),
2942 + MTK_PIN(
2943 + PINCTRL_PIN(169, "RAMBUF_ADDR0"),
2944 + NULL, "mt2701",
2945 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2946 + MTK_FUNCTION(0, "GPIO169"),
2947 + MTK_FUNCTION(1, "RAMBUF_ADDR0")
2948 + ),
2949 + MTK_PIN(
2950 + PINCTRL_PIN(170, "RAMBUF_ADDR1"),
2951 + NULL, "mt2701",
2952 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2953 + MTK_FUNCTION(0, "GPIO170"),
2954 + MTK_FUNCTION(1, "RAMBUF_ADDR1")
2955 + ),
2956 + MTK_PIN(
2957 + PINCTRL_PIN(171, "RAMBUF_ADDR2"),
2958 + NULL, "mt2701",
2959 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2960 + MTK_FUNCTION(0, "GPIO171"),
2961 + MTK_FUNCTION(1, "RAMBUF_ADDR2")
2962 + ),
2963 + MTK_PIN(
2964 + PINCTRL_PIN(172, "RAMBUF_ADDR3"),
2965 + NULL, "mt2701",
2966 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2967 + MTK_FUNCTION(0, "GPIO172"),
2968 + MTK_FUNCTION(1, "RAMBUF_ADDR3")
2969 + ),
2970 + MTK_PIN(
2971 + PINCTRL_PIN(173, "RAMBUF_ADDR4"),
2972 + NULL, "mt2701",
2973 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2974 + MTK_FUNCTION(0, "GPIO173"),
2975 + MTK_FUNCTION(1, "RAMBUF_ADDR4")
2976 + ),
2977 + MTK_PIN(
2978 + PINCTRL_PIN(174, "RAMBUF_ADDR5"),
2979 + NULL, "mt2701",
2980 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2981 + MTK_FUNCTION(0, "GPIO174"),
2982 + MTK_FUNCTION(1, "RAMBUF_ADDR5")
2983 + ),
2984 + MTK_PIN(
2985 + PINCTRL_PIN(175, "RAMBUF_ADDR6"),
2986 + NULL, "mt2701",
2987 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2988 + MTK_FUNCTION(0, "GPIO175"),
2989 + MTK_FUNCTION(1, "RAMBUF_ADDR6")
2990 + ),
2991 + MTK_PIN(
2992 + PINCTRL_PIN(176, "RAMBUF_ADDR7"),
2993 + NULL, "mt2701",
2994 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2995 + MTK_FUNCTION(0, "GPIO176"),
2996 + MTK_FUNCTION(1, "RAMBUF_ADDR7")
2997 + ),
2998 + MTK_PIN(
2999 + PINCTRL_PIN(177, "RAMBUF_ADDR8"),
3000 + NULL, "mt2701",
3001 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3002 + MTK_FUNCTION(0, "GPIO177"),
3003 + MTK_FUNCTION(1, "RAMBUF_ADDR8")
3004 + ),
3005 + MTK_PIN(
3006 + PINCTRL_PIN(178, "RAMBUF_ADDR9"),
3007 + NULL, "mt2701",
3008 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3009 + MTK_FUNCTION(0, "GPIO178"),
3010 + MTK_FUNCTION(1, "RAMBUF_ADDR9")
3011 + ),
3012 + MTK_PIN(
3013 + PINCTRL_PIN(179, "RAMBUF_ADDR10"),
3014 + NULL, "mt2701",
3015 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3016 + MTK_FUNCTION(0, "GPIO179"),
3017 + MTK_FUNCTION(1, "RAMBUF_ADDR10")
3018 + ),
3019 + MTK_PIN(
3020 + PINCTRL_PIN(180, "RAMBUF_RW"),
3021 + NULL, "mt2701",
3022 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3023 + MTK_FUNCTION(0, "GPIO180"),
3024 + MTK_FUNCTION(1, "RAMBUF_RW")
3025 + ),
3026 + MTK_PIN(
3027 + PINCTRL_PIN(181, "RAMBUF_LAST"),
3028 + NULL, "mt2701",
3029 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3030 + MTK_FUNCTION(0, "GPIO181"),
3031 + MTK_FUNCTION(1, "RAMBUF_LAST")
3032 + ),
3033 + MTK_PIN(
3034 + PINCTRL_PIN(182, "RAMBUF_HP"),
3035 + NULL, "mt2701",
3036 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3037 + MTK_FUNCTION(0, "GPIO182"),
3038 + MTK_FUNCTION(1, "RAMBUF_HP")
3039 + ),
3040 + MTK_PIN(
3041 + PINCTRL_PIN(183, "RAMBUF_REQ"),
3042 + NULL, "mt2701",
3043 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3044 + MTK_FUNCTION(0, "GPIO183"),
3045 + MTK_FUNCTION(1, "RAMBUF_REQ")
3046 + ),
3047 + MTK_PIN(
3048 + PINCTRL_PIN(184, "RAMBUF_ALE"),
3049 + NULL, "mt2701",
3050 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3051 + MTK_FUNCTION(0, "GPIO184"),
3052 + MTK_FUNCTION(1, "RAMBUF_ALE")
3053 + ),
3054 + MTK_PIN(
3055 + PINCTRL_PIN(185, "RAMBUF_DLE"),
3056 + NULL, "mt2701",
3057 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3058 + MTK_FUNCTION(0, "GPIO185"),
3059 + MTK_FUNCTION(1, "RAMBUF_DLE")
3060 + ),
3061 + MTK_PIN(
3062 + PINCTRL_PIN(186, "RAMBUF_WDLE"),
3063 + NULL, "mt2701",
3064 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3065 + MTK_FUNCTION(0, "GPIO186"),
3066 + MTK_FUNCTION(1, "RAMBUF_WDLE")
3067 + ),
3068 + MTK_PIN(
3069 + PINCTRL_PIN(187, "RAMBUF_O_CLK"),
3070 + NULL, "mt2701",
3071 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3072 + MTK_FUNCTION(0, "GPIO187"),
3073 + MTK_FUNCTION(1, "RAMBUF_O_CLK")
3074 + ),
3075 + MTK_PIN(
3076 + PINCTRL_PIN(188, "I2S2_MCLK"),
3077 + NULL, "mt2701",
3078 + MTK_EINT_FUNCTION(0, 100),
3079 + MTK_FUNCTION(0, "GPIO188"),
3080 + MTK_FUNCTION(1, "I2S2_MCLK")
3081 + ),
3082 + MTK_PIN(
3083 + PINCTRL_PIN(189, "I2S3_DATA"),
3084 + NULL, "mt2701",
3085 + MTK_EINT_FUNCTION(0, 101),
3086 + MTK_FUNCTION(0, "GPIO189"),
3087 + MTK_FUNCTION(2, "I2S3_DATA_BYPS"),
3088 + MTK_FUNCTION(3, "PCM_TX")
3089 + ),
3090 + MTK_PIN(
3091 + PINCTRL_PIN(190, "I2S3_DATA_IN"),
3092 + NULL, "mt2701",
3093 + MTK_EINT_FUNCTION(0, 102),
3094 + MTK_FUNCTION(0, "GPIO190"),
3095 + MTK_FUNCTION(1, "I2S3_DATA_IN"),
3096 + MTK_FUNCTION(3, "PCM_RX")
3097 + ),
3098 + MTK_PIN(
3099 + PINCTRL_PIN(191, "I2S3_BCK"),
3100 + NULL, "mt2701",
3101 + MTK_EINT_FUNCTION(0, 103),
3102 + MTK_FUNCTION(0, "GPIO191"),
3103 + MTK_FUNCTION(1, "I2S3_BCK"),
3104 + MTK_FUNCTION(3, "PCM_CLK0")
3105 + ),
3106 + MTK_PIN(
3107 + PINCTRL_PIN(192, "I2S3_LRCK"),
3108 + NULL, "mt2701",
3109 + MTK_EINT_FUNCTION(0, 104),
3110 + MTK_FUNCTION(0, "GPIO192"),
3111 + MTK_FUNCTION(1, "I2S3_LRCK"),
3112 + MTK_FUNCTION(3, "PCM_SYNC")
3113 + ),
3114 + MTK_PIN(
3115 + PINCTRL_PIN(193, "I2S3_MCLK"),
3116 + NULL, "mt2701",
3117 + MTK_EINT_FUNCTION(0, 105),
3118 + MTK_FUNCTION(0, "GPIO193"),
3119 + MTK_FUNCTION(1, "I2S3_MCLK")
3120 + ),
3121 + MTK_PIN(
3122 + PINCTRL_PIN(194, "I2S4_DATA"),
3123 + NULL, "mt2701",
3124 + MTK_EINT_FUNCTION(0, 106),
3125 + MTK_FUNCTION(0, "GPIO194"),
3126 + MTK_FUNCTION(1, "I2S4_DATA"),
3127 + MTK_FUNCTION(2, "I2S4_DATA_BYPS"),
3128 + MTK_FUNCTION(3, "PCM_TX")
3129 + ),
3130 + MTK_PIN(
3131 + PINCTRL_PIN(195, "I2S4_DATA_IN"),
3132 + NULL, "mt2701",
3133 + MTK_EINT_FUNCTION(0, 107),
3134 + MTK_FUNCTION(0, "GPIO195"),
3135 + MTK_FUNCTION(1, "I2S4_DATA_IN"),
3136 + MTK_FUNCTION(3, "PCM_RX")
3137 + ),
3138 + MTK_PIN(
3139 + PINCTRL_PIN(196, "I2S4_BCK"),
3140 + NULL, "mt2701",
3141 + MTK_EINT_FUNCTION(0, 108),
3142 + MTK_FUNCTION(0, "GPIO196"),
3143 + MTK_FUNCTION(1, "I2S4_BCK"),
3144 + MTK_FUNCTION(3, "PCM_CLK0")
3145 + ),
3146 + MTK_PIN(
3147 + PINCTRL_PIN(197, "I2S4_LRCK"),
3148 + NULL, "mt2701",
3149 + MTK_EINT_FUNCTION(0, 109),
3150 + MTK_FUNCTION(0, "GPIO197"),
3151 + MTK_FUNCTION(1, "I2S4_LRCK"),
3152 + MTK_FUNCTION(3, "PCM_SYNC")
3153 + ),
3154 + MTK_PIN(
3155 + PINCTRL_PIN(198, "I2S4_MCLK"),
3156 + NULL, "mt2701",
3157 + MTK_EINT_FUNCTION(0, 110),
3158 + MTK_FUNCTION(0, "GPIO198"),
3159 + MTK_FUNCTION(1, "I2S4_MCLK")
3160 + ),
3161 + MTK_PIN(
3162 + PINCTRL_PIN(199, "SPI1_CLK"),
3163 + NULL, "mt2701",
3164 + MTK_EINT_FUNCTION(0, 111),
3165 + MTK_FUNCTION(0, "GPIO199"),
3166 + MTK_FUNCTION(1, "SPI1_CK"),
3167 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
3168 + MTK_FUNCTION(4, "KCOL3"),
3169 + MTK_FUNCTION(7, "DBG_MON_B[15]")
3170 + ),
3171 + MTK_PIN(
3172 + PINCTRL_PIN(200, "SPDIF_OUT"),
3173 + NULL, "mt2701",
3174 + MTK_EINT_FUNCTION(0, 112),
3175 + MTK_FUNCTION(0, "GPIO200"),
3176 + MTK_FUNCTION(1, "SPDIF_OUT"),
3177 + MTK_FUNCTION(5, "G1_TXD3"),
3178 + MTK_FUNCTION(6, "URXD2"),
3179 + MTK_FUNCTION(7, "DBG_MON_B[16]")
3180 + ),
3181 + MTK_PIN(
3182 + PINCTRL_PIN(201, "SPDIF_IN0"),
3183 + NULL, "mt2701",
3184 + MTK_EINT_FUNCTION(0, 113),
3185 + MTK_FUNCTION(0, "GPIO201"),
3186 + MTK_FUNCTION(1, "SPDIF_IN0"),
3187 + MTK_FUNCTION(5, "G1_TXEN"),
3188 + MTK_FUNCTION(6, "UTXD2"),
3189 + MTK_FUNCTION(7, "DBG_MON_B[17]")
3190 + ),
3191 + MTK_PIN(
3192 + PINCTRL_PIN(202, "SPDIF_IN1"),
3193 + NULL, "mt2701",
3194 + MTK_EINT_FUNCTION(0, 114),
3195 + MTK_FUNCTION(0, "GPIO202"),
3196 + MTK_FUNCTION(1, "SPDIF_IN1")
3197 + ),
3198 + MTK_PIN(
3199 + PINCTRL_PIN(203, "PWM0"),
3200 + NULL, "mt2701",
3201 + MTK_EINT_FUNCTION(0, 115),
3202 + MTK_FUNCTION(0, "GPIO203"),
3203 + MTK_FUNCTION(1, "PWM0"),
3204 + MTK_FUNCTION(2, "DISP_PWM"),
3205 + MTK_FUNCTION(5, "G1_TXD2"),
3206 + MTK_FUNCTION(7, "DBG_MON_B[18]"),
3207 + MTK_FUNCTION(9, "I2S2_DATA")
3208 + ),
3209 + MTK_PIN(
3210 + PINCTRL_PIN(204, "PWM1"),
3211 + NULL, "mt2701",
3212 + MTK_EINT_FUNCTION(0, 116),
3213 + MTK_FUNCTION(0, "GPIO204"),
3214 + MTK_FUNCTION(1, "PWM1"),
3215 + MTK_FUNCTION(2, "CLKM3"),
3216 + MTK_FUNCTION(5, "G1_TXD1"),
3217 + MTK_FUNCTION(7, "DBG_MON_B[19]"),
3218 + MTK_FUNCTION(9, "I2S3_DATA")
3219 + ),
3220 + MTK_PIN(
3221 + PINCTRL_PIN(205, "PWM2"),
3222 + NULL, "mt2701",
3223 + MTK_EINT_FUNCTION(0, 117),
3224 + MTK_FUNCTION(0, "GPIO205"),
3225 + MTK_FUNCTION(1, "PWM2"),
3226 + MTK_FUNCTION(2, "CLKM2"),
3227 + MTK_FUNCTION(5, "G1_TXD0"),
3228 + MTK_FUNCTION(7, "DBG_MON_B[20]")
3229 + ),
3230 + MTK_PIN(
3231 + PINCTRL_PIN(206, "PWM3"),
3232 + NULL, "mt2701",
3233 + MTK_EINT_FUNCTION(0, 118),
3234 + MTK_FUNCTION(0, "GPIO206"),
3235 + MTK_FUNCTION(1, "PWM3"),
3236 + MTK_FUNCTION(2, "CLKM1"),
3237 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
3238 + MTK_FUNCTION(5, "G1_TXC"),
3239 + MTK_FUNCTION(7, "DBG_MON_B[21]")
3240 + ),
3241 + MTK_PIN(
3242 + PINCTRL_PIN(207, "PWM4"),
3243 + NULL, "mt2701",
3244 + MTK_EINT_FUNCTION(0, 119),
3245 + MTK_FUNCTION(0, "GPIO207"),
3246 + MTK_FUNCTION(1, "PWM4"),
3247 + MTK_FUNCTION(2, "CLKM0"),
3248 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
3249 + MTK_FUNCTION(5, "G1_RXC"),
3250 + MTK_FUNCTION(7, "DBG_MON_B[22]")
3251 + ),
3252 + MTK_PIN(
3253 + PINCTRL_PIN(208, "AUD_EXT_CK1"),
3254 + NULL, "mt2701",
3255 + MTK_EINT_FUNCTION(0, 120),
3256 + MTK_FUNCTION(0, "GPIO208"),
3257 + MTK_FUNCTION(1, "AUD_EXT_CK1"),
3258 + MTK_FUNCTION(2, "PWM0"),
3259 + MTK_FUNCTION(4, "ANT_SEL5"),
3260 + MTK_FUNCTION(5, "DISP_PWM"),
3261 + MTK_FUNCTION(7, "DBG_MON_A[31]"),
3262 + MTK_FUNCTION(11, "PCIE0_PERST_N")
3263 + ),
3264 + MTK_PIN(
3265 + PINCTRL_PIN(209, "AUD_EXT_CK2"),
3266 + NULL, "mt2701",
3267 + MTK_EINT_FUNCTION(0, 121),
3268 + MTK_FUNCTION(0, "GPIO209"),
3269 + MTK_FUNCTION(1, "AUD_EXT_CK2"),
3270 + MTK_FUNCTION(2, "MSDC1_WP"),
3271 + MTK_FUNCTION(5, "PWM1"),
3272 + MTK_FUNCTION(7, "DBG_MON_A[32]"),
3273 + MTK_FUNCTION(11, "PCIE1_PERST_N")
3274 + ),
3275 + MTK_PIN(
3276 + PINCTRL_PIN(210, "AUD_CLOCK"),
3277 + NULL, "mt2701",
3278 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3279 + MTK_FUNCTION(0, "GPIO210"),
3280 + MTK_FUNCTION(1, "AUD_CLOCK")
3281 + ),
3282 + MTK_PIN(
3283 + PINCTRL_PIN(211, "DVP_RESET"),
3284 + NULL, "mt2701",
3285 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3286 + MTK_FUNCTION(0, "GPIO211"),
3287 + MTK_FUNCTION(1, "DVP_RESET")
3288 + ),
3289 + MTK_PIN(
3290 + PINCTRL_PIN(212, "DVP_CLOCK"),
3291 + NULL, "mt2701",
3292 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3293 + MTK_FUNCTION(0, "GPIO212"),
3294 + MTK_FUNCTION(1, "DVP_CLOCK")
3295 + ),
3296 + MTK_PIN(
3297 + PINCTRL_PIN(213, "DVP_CS"),
3298 + NULL, "mt2701",
3299 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3300 + MTK_FUNCTION(0, "GPIO213"),
3301 + MTK_FUNCTION(1, "DVP_CS")
3302 + ),
3303 + MTK_PIN(
3304 + PINCTRL_PIN(214, "DVP_CK"),
3305 + NULL, "mt2701",
3306 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3307 + MTK_FUNCTION(0, "GPIO214"),
3308 + MTK_FUNCTION(1, "DVP_CK")
3309 + ),
3310 + MTK_PIN(
3311 + PINCTRL_PIN(215, "DVP_DI"),
3312 + NULL, "mt2701",
3313 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3314 + MTK_FUNCTION(0, "GPIO215"),
3315 + MTK_FUNCTION(1, "DVP_DI")
3316 + ),
3317 + MTK_PIN(
3318 + PINCTRL_PIN(216, "DVP_DO"),
3319 + NULL, "mt2701",
3320 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3321 + MTK_FUNCTION(0, "GPIO216"),
3322 + MTK_FUNCTION(1, "DVP_DO")
3323 + ),
3324 + MTK_PIN(
3325 + PINCTRL_PIN(217, "AP_CS"),
3326 + NULL, "mt2701",
3327 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3328 + MTK_FUNCTION(0, "GPIO217"),
3329 + MTK_FUNCTION(1, "AP_CS")
3330 + ),
3331 + MTK_PIN(
3332 + PINCTRL_PIN(218, "AP_CK"),
3333 + NULL, "mt2701",
3334 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3335 + MTK_FUNCTION(0, "GPIO218"),
3336 + MTK_FUNCTION(1, "AP_CK")
3337 + ),
3338 + MTK_PIN(
3339 + PINCTRL_PIN(219, "AP_DI"),
3340 + NULL, "mt2701",
3341 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3342 + MTK_FUNCTION(0, "GPIO219"),
3343 + MTK_FUNCTION(1, "AP_DI")
3344 + ),
3345 + MTK_PIN(
3346 + PINCTRL_PIN(220, "AP_DO"),
3347 + NULL, "mt2701",
3348 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3349 + MTK_FUNCTION(0, "GPIO220"),
3350 + MTK_FUNCTION(1, "AP_DO")
3351 + ),
3352 + MTK_PIN(
3353 + PINCTRL_PIN(221, "DVD_BCLK"),
3354 + NULL, "mt2701",
3355 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3356 + MTK_FUNCTION(0, "GPIO221"),
3357 + MTK_FUNCTION(1, "DVD_BCLK")
3358 + ),
3359 + MTK_PIN(
3360 + PINCTRL_PIN(222, "T8032_CLK"),
3361 + NULL, "mt2701",
3362 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3363 + MTK_FUNCTION(0, "GPIO222"),
3364 + MTK_FUNCTION(1, "T8032_CLK")
3365 + ),
3366 + MTK_PIN(
3367 + PINCTRL_PIN(223, "AP_BCLK"),
3368 + NULL, "mt2701",
3369 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3370 + MTK_FUNCTION(0, "GPIO223"),
3371 + MTK_FUNCTION(1, "AP_BCLK")
3372 + ),
3373 + MTK_PIN(
3374 + PINCTRL_PIN(224, "HOST_CS"),
3375 + NULL, "mt2701",
3376 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3377 + MTK_FUNCTION(0, "GPIO224"),
3378 + MTK_FUNCTION(1, "HOST_CS")
3379 + ),
3380 + MTK_PIN(
3381 + PINCTRL_PIN(225, "HOST_CK"),
3382 + NULL, "mt2701",
3383 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3384 + MTK_FUNCTION(0, "GPIO225"),
3385 + MTK_FUNCTION(1, "HOST_CK")
3386 + ),
3387 + MTK_PIN(
3388 + PINCTRL_PIN(226, "HOST_DO0"),
3389 + NULL, "mt2701",
3390 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3391 + MTK_FUNCTION(0, "GPIO226"),
3392 + MTK_FUNCTION(1, "HOST_DO0")
3393 + ),
3394 + MTK_PIN(
3395 + PINCTRL_PIN(227, "HOST_DO1"),
3396 + NULL, "mt2701",
3397 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3398 + MTK_FUNCTION(0, "GPIO227"),
3399 + MTK_FUNCTION(1, "HOST_DO1")
3400 + ),
3401 + MTK_PIN(
3402 + PINCTRL_PIN(228, "SLV_CS"),
3403 + NULL, "mt2701",
3404 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3405 + MTK_FUNCTION(0, "GPIO228"),
3406 + MTK_FUNCTION(1, "SLV_CS")
3407 + ),
3408 + MTK_PIN(
3409 + PINCTRL_PIN(229, "SLV_CK"),
3410 + NULL, "mt2701",
3411 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3412 + MTK_FUNCTION(0, "GPIO229"),
3413 + MTK_FUNCTION(1, "SLV_CK")
3414 + ),
3415 + MTK_PIN(
3416 + PINCTRL_PIN(230, "SLV_DI0"),
3417 + NULL, "mt2701",
3418 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3419 + MTK_FUNCTION(0, "GPIO230"),
3420 + MTK_FUNCTION(1, "SLV_DI0")
3421 + ),
3422 + MTK_PIN(
3423 + PINCTRL_PIN(231, "SLV_DI1"),
3424 + NULL, "mt2701",
3425 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3426 + MTK_FUNCTION(0, "GPIO231"),
3427 + MTK_FUNCTION(1, "SLV_DI1")
3428 + ),
3429 + MTK_PIN(
3430 + PINCTRL_PIN(232, "AP2DSP_INT"),
3431 + NULL, "mt2701",
3432 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3433 + MTK_FUNCTION(0, "GPIO232"),
3434 + MTK_FUNCTION(1, "AP2DSP_INT")
3435 + ),
3436 + MTK_PIN(
3437 + PINCTRL_PIN(233, "AP2DSP_INT_CLR"),
3438 + NULL, "mt2701",
3439 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3440 + MTK_FUNCTION(0, "GPIO233"),
3441 + MTK_FUNCTION(1, "AP2DSP_INT_CLR")
3442 + ),
3443 + MTK_PIN(
3444 + PINCTRL_PIN(234, "DSP2AP_INT"),
3445 + NULL, "mt2701",
3446 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3447 + MTK_FUNCTION(0, "GPIO234"),
3448 + MTK_FUNCTION(1, "DSP2AP_INT")
3449 + ),
3450 + MTK_PIN(
3451 + PINCTRL_PIN(235, "DSP2AP_INT_CLR"),
3452 + NULL, "mt2701",
3453 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3454 + MTK_FUNCTION(0, "GPIO235"),
3455 + MTK_FUNCTION(1, "DSP2AP_INT_CLR")
3456 + ),
3457 + MTK_PIN(
3458 + PINCTRL_PIN(236, "EXT_SDIO3"),
3459 + NULL, "mt2701",
3460 + MTK_EINT_FUNCTION(0, 122),
3461 + MTK_FUNCTION(0, "GPIO236"),
3462 + MTK_FUNCTION(1, "EXT_SDIO3"),
3463 + MTK_FUNCTION(2, "IDDIG"),
3464 + MTK_FUNCTION(7, "DBG_MON_A[1]")
3465 + ),
3466 + MTK_PIN(
3467 + PINCTRL_PIN(237, "EXT_SDIO2"),
3468 + NULL, "mt2701",
3469 + MTK_EINT_FUNCTION(0, 123),