mediatek: update patches
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0014-pinctrl-dt-bindings-Add-pinfunc-header-file-for-mt27.patch
1 From 416720ba33d4fd7d3166c17be7c13651cc08d408 Mon Sep 17 00:00:00 2001
2 From: Biao Huang <biao.huang@mediatek.com>
3 Date: Mon, 28 Dec 2015 15:09:04 +0800
4 Subject: [PATCH 14/91] pinctrl: dt bindings: Add pinfunc header file for
5 mt2701
6
7 Add pinfunc header file, mt2701 related dts will include it
8
9 Signed-off-by: Biao Huang <biao.huang@mediatek.com>
10 Acked-by: Linus Walleij <linus.walleij@linaro.org>
11 ---
12 arch/arm/boot/dts/mt2701-pinfunc.h | 735 ++++++++
13 drivers/pinctrl/mediatek/Kconfig | 6 +
14 drivers/pinctrl/mediatek/Makefile | 1 +
15 drivers/pinctrl/mediatek/pinctrl-mt2701.c | 586 +++++++
16 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 16 +
17 drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 12 +-
18 drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h | 2323 +++++++++++++++++++++++++
19 7 files changed, 3678 insertions(+), 1 deletion(-)
20 create mode 100644 arch/arm/boot/dts/mt2701-pinfunc.h
21 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt2701.c
22 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
23
24 diff --git a/arch/arm/boot/dts/mt2701-pinfunc.h b/arch/arm/boot/dts/mt2701-pinfunc.h
25 new file mode 100644
26 index 0000000..e24ebc8
27 --- /dev/null
28 +++ b/arch/arm/boot/dts/mt2701-pinfunc.h
29 @@ -0,0 +1,735 @@
30 +/*
31 + * Copyright (c) 2015 MediaTek Inc.
32 + * Author: Biao Huang <biao.huang@mediatek.com>
33 + *
34 + * This program is free software; you can redistribute it and/or modify
35 + * it under the terms of the GNU General Public License version 2 as
36 + * published by the Free Software Foundation.
37 + *
38 + * This program is distributed in the hope that it will be useful,
39 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
40 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41 + * GNU General Public License for more details.
42 + */
43 +
44 +#ifndef __DTS_MT2701_PINFUNC_H
45 +#define __DTS_MT2701_PINFUNC_H
46 +
47 +#include <dt-bindings/pinctrl/mt65xx.h>
48 +
49 +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
50 +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDO (MTK_PIN_NO(0) | 1)
51 +#define MT2701_PIN_0_PWRAP_SPI0_MI__FUNC_PWRAP_SPIDI (MTK_PIN_NO(0) | 2)
52 +
53 +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
54 +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDI (MTK_PIN_NO(1) | 1)
55 +#define MT2701_PIN_1_PWRAP_SPI0_MO__FUNC_PWRAP_SPIDO (MTK_PIN_NO(1) | 2)
56 +
57 +#define MT2701_PIN_2_PWRAP_INT__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
58 +#define MT2701_PIN_2_PWRAP_INT__FUNC_PWRAP_INT (MTK_PIN_NO(2) | 1)
59 +
60 +#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
61 +#define MT2701_PIN_3_PWRAP_SPI0_CK__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(3) | 1)
62 +
63 +#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
64 +#define MT2701_PIN_4_PWRAP_SPI0_CSN__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(4) | 1)
65 +
66 +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
67 +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_PWRAP_SPICK2_I (MTK_PIN_NO(5) | 1)
68 +#define MT2701_PIN_5_PWRAP_SPI0_CK2__FUNC_ANT_SEL1 (MTK_PIN_NO(5) | 5)
69 +
70 +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
71 +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_PWRAP_SPICS2_B_I (MTK_PIN_NO(6) | 1)
72 +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_ANT_SEL0 (MTK_PIN_NO(6) | 5)
73 +#define MT2701_PIN_6_PWRAP_SPI0_CSN2__FUNC_DBG_MON_A_0 (MTK_PIN_NO(6) | 7)
74 +
75 +#define MT2701_PIN_7_SPI1_CSN__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
76 +#define MT2701_PIN_7_SPI1_CSN__FUNC_SPI1_CS (MTK_PIN_NO(7) | 1)
77 +#define MT2701_PIN_7_SPI1_CSN__FUNC_KCOL0 (MTK_PIN_NO(7) | 4)
78 +#define MT2701_PIN_7_SPI1_CSN__FUNC_DBG_MON_B_12 (MTK_PIN_NO(7) | 7)
79 +
80 +#define MT2701_PIN_8_SPI1_MI__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
81 +#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MI (MTK_PIN_NO(8) | 1)
82 +#define MT2701_PIN_8_SPI1_MI__FUNC_SPI1_MO (MTK_PIN_NO(8) | 2)
83 +#define MT2701_PIN_8_SPI1_MI__FUNC_KCOL1 (MTK_PIN_NO(8) | 4)
84 +#define MT2701_PIN_8_SPI1_MI__FUNC_DBG_MON_B_13 (MTK_PIN_NO(8) | 7)
85 +
86 +#define MT2701_PIN_9_SPI1_MO__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
87 +#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MO (MTK_PIN_NO(9) | 1)
88 +#define MT2701_PIN_9_SPI1_MO__FUNC_SPI1_MI (MTK_PIN_NO(9) | 2)
89 +#define MT2701_PIN_9_SPI1_MO__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(9) | 3)
90 +#define MT2701_PIN_9_SPI1_MO__FUNC_KCOL2 (MTK_PIN_NO(9) | 4)
91 +#define MT2701_PIN_9_SPI1_MO__FUNC_DBG_MON_B_14 (MTK_PIN_NO(9) | 7)
92 +
93 +#define MT2701_PIN_10_RTC32K_CK__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
94 +#define MT2701_PIN_10_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(10) | 1)
95 +
96 +#define MT2701_PIN_11_WATCHDOG__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
97 +#define MT2701_PIN_11_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(11) | 1)
98 +
99 +#define MT2701_PIN_12_SRCLKENA__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
100 +#define MT2701_PIN_12_SRCLKENA__FUNC_SRCLKENA (MTK_PIN_NO(12) | 1)
101 +
102 +#define MT2701_PIN_13_SRCLKENAI__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
103 +#define MT2701_PIN_13_SRCLKENAI__FUNC_SRCLKENAI (MTK_PIN_NO(13) | 1)
104 +
105 +#define MT2701_PIN_14_URXD2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
106 +#define MT2701_PIN_14_URXD2__FUNC_URXD2 (MTK_PIN_NO(14) | 1)
107 +#define MT2701_PIN_14_URXD2__FUNC_UTXD2 (MTK_PIN_NO(14) | 2)
108 +#define MT2701_PIN_14_URXD2__FUNC_SRCCLKENAI2 (MTK_PIN_NO(14) | 5)
109 +#define MT2701_PIN_14_URXD2__FUNC_DBG_MON_B_30 (MTK_PIN_NO(14) | 7)
110 +
111 +#define MT2701_PIN_15_UTXD2__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
112 +#define MT2701_PIN_15_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(15) | 1)
113 +#define MT2701_PIN_15_UTXD2__FUNC_URXD2 (MTK_PIN_NO(15) | 2)
114 +#define MT2701_PIN_15_UTXD2__FUNC_DBG_MON_B_31 (MTK_PIN_NO(15) | 7)
115 +
116 +#define MT2701_PIN_18_PCM_CLK__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
117 +#define MT2701_PIN_18_PCM_CLK__FUNC_PCM_CLK0 (MTK_PIN_NO(18) | 1)
118 +#define MT2701_PIN_18_PCM_CLK__FUNC_MRG_CLK (MTK_PIN_NO(18) | 2)
119 +#define MT2701_PIN_18_PCM_CLK__FUNC_MM_TEST_CK (MTK_PIN_NO(18) | 4)
120 +#define MT2701_PIN_18_PCM_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(18) | 5)
121 +#define MT2701_PIN_18_PCM_CLK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(18) | 6)
122 +#define MT2701_PIN_18_PCM_CLK__FUNC_DBG_MON_A_3 (MTK_PIN_NO(18) | 7)
123 +
124 +#define MT2701_PIN_19_PCM_SYNC__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
125 +#define MT2701_PIN_19_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(19) | 1)
126 +#define MT2701_PIN_19_PCM_SYNC__FUNC_MRG_SYNC (MTK_PIN_NO(19) | 2)
127 +#define MT2701_PIN_19_PCM_SYNC__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(19) | 5)
128 +#define MT2701_PIN_19_PCM_SYNC__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(19) | 6)
129 +#define MT2701_PIN_19_PCM_SYNC__FUNC_DBG_MON_A_5 (MTK_PIN_NO(19) | 7)
130 +
131 +#define MT2701_PIN_20_PCM_RX__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
132 +#define MT2701_PIN_20_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(20) | 1)
133 +#define MT2701_PIN_20_PCM_RX__FUNC_MRG_RX (MTK_PIN_NO(20) | 2)
134 +#define MT2701_PIN_20_PCM_RX__FUNC_MRG_TX (MTK_PIN_NO(20) | 3)
135 +#define MT2701_PIN_20_PCM_RX__FUNC_PCM_TX (MTK_PIN_NO(20) | 4)
136 +#define MT2701_PIN_20_PCM_RX__FUNC_CONN_DSP_JDI (MTK_PIN_NO(20) | 5)
137 +#define MT2701_PIN_20_PCM_RX__FUNC_WCN_PCM_RX (MTK_PIN_NO(20) | 6)
138 +#define MT2701_PIN_20_PCM_RX__FUNC_DBG_MON_A_4 (MTK_PIN_NO(20) | 7)
139 +
140 +#define MT2701_PIN_21_PCM_TX__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
141 +#define MT2701_PIN_21_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(21) | 1)
142 +#define MT2701_PIN_21_PCM_TX__FUNC_MRG_TX (MTK_PIN_NO(21) | 2)
143 +#define MT2701_PIN_21_PCM_TX__FUNC_MRG_RX (MTK_PIN_NO(21) | 3)
144 +#define MT2701_PIN_21_PCM_TX__FUNC_PCM_RX (MTK_PIN_NO(21) | 4)
145 +#define MT2701_PIN_21_PCM_TX__FUNC_CONN_DSP_JMS (MTK_PIN_NO(21) | 5)
146 +#define MT2701_PIN_21_PCM_TX__FUNC_WCN_PCM_TX (MTK_PIN_NO(21) | 6)
147 +#define MT2701_PIN_21_PCM_TX__FUNC_DBG_MON_A_2 (MTK_PIN_NO(21) | 7)
148 +
149 +#define MT2701_PIN_22_EINT0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
150 +#define MT2701_PIN_22_EINT0__FUNC_UCTS0 (MTK_PIN_NO(22) | 1)
151 +#define MT2701_PIN_22_EINT0__FUNC_KCOL3 (MTK_PIN_NO(22) | 3)
152 +#define MT2701_PIN_22_EINT0__FUNC_CONN_DSP_JDO (MTK_PIN_NO(22) | 4)
153 +#define MT2701_PIN_22_EINT0__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(22) | 5)
154 +#define MT2701_PIN_22_EINT0__FUNC_DBG_MON_A_30 (MTK_PIN_NO(22) | 7)
155 +#define MT2701_PIN_22_EINT0__FUNC_PCIE0_PERST_N (MTK_PIN_NO(22) | 10)
156 +
157 +#define MT2701_PIN_23_EINT1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
158 +#define MT2701_PIN_23_EINT1__FUNC_URTS0 (MTK_PIN_NO(23) | 1)
159 +#define MT2701_PIN_23_EINT1__FUNC_KCOL2 (MTK_PIN_NO(23) | 3)
160 +#define MT2701_PIN_23_EINT1__FUNC_CONN_MCU_TDO (MTK_PIN_NO(23) | 4)
161 +#define MT2701_PIN_23_EINT1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 5)
162 +#define MT2701_PIN_23_EINT1__FUNC_DBG_MON_A_29 (MTK_PIN_NO(23) | 7)
163 +#define MT2701_PIN_23_EINT1__FUNC_PCIE1_PERST_N (MTK_PIN_NO(23) | 10)
164 +
165 +#define MT2701_PIN_24_EINT2__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
166 +#define MT2701_PIN_24_EINT2__FUNC_UCTS1 (MTK_PIN_NO(24) | 1)
167 +#define MT2701_PIN_24_EINT2__FUNC_KCOL1 (MTK_PIN_NO(24) | 3)
168 +#define MT2701_PIN_24_EINT2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(24) | 4)
169 +#define MT2701_PIN_24_EINT2__FUNC_DBG_MON_A_28 (MTK_PIN_NO(24) | 7)
170 +#define MT2701_PIN_24_EINT2__FUNC_PCIE2_PERST_N (MTK_PIN_NO(24) | 10)
171 +
172 +#define MT2701_PIN_25_EINT3__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
173 +#define MT2701_PIN_25_EINT3__FUNC_URTS1 (MTK_PIN_NO(25) | 1)
174 +#define MT2701_PIN_25_EINT3__FUNC_KCOL0 (MTK_PIN_NO(25) | 3)
175 +#define MT2701_PIN_25_EINT3__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(25) | 4)
176 +#define MT2701_PIN_25_EINT3__FUNC_DBG_MON_A_27 (MTK_PIN_NO(25) | 7)
177 +
178 +#define MT2701_PIN_26_EINT4__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
179 +#define MT2701_PIN_26_EINT4__FUNC_UCTS3 (MTK_PIN_NO(26) | 1)
180 +#define MT2701_PIN_26_EINT4__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(26) | 2)
181 +#define MT2701_PIN_26_EINT4__FUNC_KROW3 (MTK_PIN_NO(26) | 3)
182 +#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_TCK0 (MTK_PIN_NO(26) | 4)
183 +#define MT2701_PIN_26_EINT4__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(26) | 5)
184 +#define MT2701_PIN_26_EINT4__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(26) | 6)
185 +#define MT2701_PIN_26_EINT4__FUNC_DBG_MON_A_26 (MTK_PIN_NO(26) | 7)
186 +
187 +#define MT2701_PIN_27_EINT5__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
188 +#define MT2701_PIN_27_EINT5__FUNC_URTS3 (MTK_PIN_NO(27) | 1)
189 +#define MT2701_PIN_27_EINT5__FUNC_IDDIG_P1 (MTK_PIN_NO(27) | 2)
190 +#define MT2701_PIN_27_EINT5__FUNC_KROW2 (MTK_PIN_NO(27) | 3)
191 +#define MT2701_PIN_27_EINT5__FUNC_CONN_MCU_TDI (MTK_PIN_NO(27) | 4)
192 +#define MT2701_PIN_27_EINT5__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(27) | 6)
193 +#define MT2701_PIN_27_EINT5__FUNC_DBG_MON_A_25 (MTK_PIN_NO(27) | 7)
194 +
195 +#define MT2701_PIN_28_EINT6__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
196 +#define MT2701_PIN_28_EINT6__FUNC_DRV_VBUS (MTK_PIN_NO(28) | 1)
197 +#define MT2701_PIN_28_EINT6__FUNC_KROW1 (MTK_PIN_NO(28) | 3)
198 +#define MT2701_PIN_28_EINT6__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(28) | 4)
199 +#define MT2701_PIN_28_EINT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(28) | 6)
200 +#define MT2701_PIN_28_EINT6__FUNC_DBG_MON_A_24 (MTK_PIN_NO(28) | 7)
201 +
202 +#define MT2701_PIN_29_EINT7__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
203 +#define MT2701_PIN_29_EINT7__FUNC_IDDIG (MTK_PIN_NO(29) | 1)
204 +#define MT2701_PIN_29_EINT7__FUNC_MSDC1_WP (MTK_PIN_NO(29) | 2)
205 +#define MT2701_PIN_29_EINT7__FUNC_KROW0 (MTK_PIN_NO(29) | 3)
206 +#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 4)
207 +#define MT2701_PIN_29_EINT7__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(29) | 5)
208 +#define MT2701_PIN_29_EINT7__FUNC_DBG_MON_A_23 (MTK_PIN_NO(29) | 7)
209 +#define MT2701_PIN_29_EINT7__FUNC_PCIE2_PERST_N (MTK_PIN_NO(29) | 14)
210 +
211 +#define MT2701_PIN_33_I2S1_DATA__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
212 +#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA (MTK_PIN_NO(33) | 1)
213 +#define MT2701_PIN_33_I2S1_DATA__FUNC_I2S1_DATA_BYPS (MTK_PIN_NO(33) | 2)
214 +#define MT2701_PIN_33_I2S1_DATA__FUNC_PCM_TX (MTK_PIN_NO(33) | 3)
215 +#define MT2701_PIN_33_I2S1_DATA__FUNC_IMG_TEST_CK (MTK_PIN_NO(33) | 4)
216 +#define MT2701_PIN_33_I2S1_DATA__FUNC_G1_RXD0 (MTK_PIN_NO(33) | 5)
217 +#define MT2701_PIN_33_I2S1_DATA__FUNC_WCN_PCM_TX (MTK_PIN_NO(33) | 6)
218 +#define MT2701_PIN_33_I2S1_DATA__FUNC_DBG_MON_B_8 (MTK_PIN_NO(33) | 7)
219 +
220 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
221 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_I2S1_DATA_IN (MTK_PIN_NO(34) | 1)
222 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(34) | 3)
223 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_VDEC_TEST_CK (MTK_PIN_NO(34) | 4)
224 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_G1_RXD1 (MTK_PIN_NO(34) | 5)
225 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_WCN_PCM_RX (MTK_PIN_NO(34) | 6)
226 +#define MT2701_PIN_34_I2S1_DATA_IN__FUNC_DBG_MON_B_7 (MTK_PIN_NO(34) | 7)
227 +
228 +#define MT2701_PIN_35_I2S1_BCK__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
229 +#define MT2701_PIN_35_I2S1_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(35) | 1)
230 +#define MT2701_PIN_35_I2S1_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(35) | 3)
231 +#define MT2701_PIN_35_I2S1_BCK__FUNC_G1_RXD2 (MTK_PIN_NO(35) | 5)
232 +#define MT2701_PIN_35_I2S1_BCK__FUNC_WCN_PCM_CLKO (MTK_PIN_NO(35) | 6)
233 +#define MT2701_PIN_35_I2S1_BCK__FUNC_DBG_MON_B_9 (MTK_PIN_NO(35) | 7)
234 +
235 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
236 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(36) | 1)
237 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(36) | 3)
238 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_G1_RXD3 (MTK_PIN_NO(36) | 5)
239 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_WCN_PCM_SYNC (MTK_PIN_NO(36) | 6)
240 +#define MT2701_PIN_36_I2S1_LRCK__FUNC_DBG_MON_B_10 (MTK_PIN_NO(36) | 7)
241 +
242 +#define MT2701_PIN_37_I2S1_MCLK__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
243 +#define MT2701_PIN_37_I2S1_MCLK__FUNC_I2S1_MCLK (MTK_PIN_NO(37) | 1)
244 +#define MT2701_PIN_37_I2S1_MCLK__FUNC_G1_RXDV (MTK_PIN_NO(37) | 5)
245 +#define MT2701_PIN_37_I2S1_MCLK__FUNC_DBG_MON_B_11 (MTK_PIN_NO(37) | 7)
246 +
247 +#define MT2701_PIN_39_JTMS__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
248 +#define MT2701_PIN_39_JTMS__FUNC_JTMS (MTK_PIN_NO(39) | 1)
249 +#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(39) | 2)
250 +#define MT2701_PIN_39_JTMS__FUNC_CONN_MCU_AICE_JMSC (MTK_PIN_NO(39) | 3)
251 +#define MT2701_PIN_39_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(39) | 4)
252 +
253 +#define MT2701_PIN_40_JTCK__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
254 +#define MT2701_PIN_40_JTCK__FUNC_JTCK (MTK_PIN_NO(40) | 1)
255 +#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_TCK1 (MTK_PIN_NO(40) | 2)
256 +#define MT2701_PIN_40_JTCK__FUNC_CONN_MCU_AICE_JCKC (MTK_PIN_NO(40) | 3)
257 +#define MT2701_PIN_40_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(40) | 4)
258 +
259 +#define MT2701_PIN_41_JTDI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
260 +#define MT2701_PIN_41_JTDI__FUNC_JTDI (MTK_PIN_NO(41) | 1)
261 +#define MT2701_PIN_41_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(41) | 2)
262 +#define MT2701_PIN_41_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(41) | 4)
263 +
264 +#define MT2701_PIN_42_JTDO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
265 +#define MT2701_PIN_42_JTDO__FUNC_JTDO (MTK_PIN_NO(42) | 1)
266 +#define MT2701_PIN_42_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(42) | 2)
267 +#define MT2701_PIN_42_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(42) | 4)
268 +
269 +#define MT2701_PIN_43_NCLE__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
270 +#define MT2701_PIN_43_NCLE__FUNC_NCLE (MTK_PIN_NO(43) | 1)
271 +#define MT2701_PIN_43_NCLE__FUNC_EXT_XCS2 (MTK_PIN_NO(43) | 2)
272 +
273 +#define MT2701_PIN_44_NCEB1__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
274 +#define MT2701_PIN_44_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(44) | 1)
275 +#define MT2701_PIN_44_NCEB1__FUNC_IDDIG (MTK_PIN_NO(44) | 2)
276 +
277 +#define MT2701_PIN_45_NCEB0__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
278 +#define MT2701_PIN_45_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(45) | 1)
279 +#define MT2701_PIN_45_NCEB0__FUNC_DRV_VBUS (MTK_PIN_NO(45) | 2)
280 +
281 +#define MT2701_PIN_46_IR__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
282 +#define MT2701_PIN_46_IR__FUNC_IR (MTK_PIN_NO(46) | 1)
283 +
284 +#define MT2701_PIN_47_NREB__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
285 +#define MT2701_PIN_47_NREB__FUNC_NREB (MTK_PIN_NO(47) | 1)
286 +#define MT2701_PIN_47_NREB__FUNC_IDDIG_P1 (MTK_PIN_NO(47) | 2)
287 +
288 +#define MT2701_PIN_48_NRNB__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
289 +#define MT2701_PIN_48_NRNB__FUNC_NRNB (MTK_PIN_NO(48) | 1)
290 +#define MT2701_PIN_48_NRNB__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(48) | 2)
291 +
292 +#define MT2701_PIN_49_I2S0_DATA__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
293 +#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA (MTK_PIN_NO(49) | 1)
294 +#define MT2701_PIN_49_I2S0_DATA__FUNC_I2S0_DATA_BYPS (MTK_PIN_NO(49) | 2)
295 +#define MT2701_PIN_49_I2S0_DATA__FUNC_PCM_TX (MTK_PIN_NO(49) | 3)
296 +#define MT2701_PIN_49_I2S0_DATA__FUNC_WCN_I2S_DO (MTK_PIN_NO(49) | 6)
297 +#define MT2701_PIN_49_I2S0_DATA__FUNC_DBG_MON_B_3 (MTK_PIN_NO(49) | 7)
298 +
299 +#define MT2701_PIN_53_SPI0_CSN__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
300 +#define MT2701_PIN_53_SPI0_CSN__FUNC_SPI0_CS (MTK_PIN_NO(53) | 1)
301 +#define MT2701_PIN_53_SPI0_CSN__FUNC_SPDIF (MTK_PIN_NO(53) | 3)
302 +#define MT2701_PIN_53_SPI0_CSN__FUNC_ADC_CK (MTK_PIN_NO(53) | 4)
303 +#define MT2701_PIN_53_SPI0_CSN__FUNC_PWM1 (MTK_PIN_NO(53) | 5)
304 +#define MT2701_PIN_53_SPI0_CSN__FUNC_DBG_MON_A_7 (MTK_PIN_NO(53) | 7)
305 +
306 +#define MT2701_PIN_54_SPI0_CK__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
307 +#define MT2701_PIN_54_SPI0_CK__FUNC_SPI0_CK (MTK_PIN_NO(54) | 1)
308 +#define MT2701_PIN_54_SPI0_CK__FUNC_SPDIF_IN1 (MTK_PIN_NO(54) | 3)
309 +#define MT2701_PIN_54_SPI0_CK__FUNC_ADC_DAT_IN (MTK_PIN_NO(54) | 4)
310 +#define MT2701_PIN_54_SPI0_CK__FUNC_DBG_MON_A_10 (MTK_PIN_NO(54) | 7)
311 +
312 +#define MT2701_PIN_55_SPI0_MI__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
313 +#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MI (MTK_PIN_NO(55) | 1)
314 +#define MT2701_PIN_55_SPI0_MI__FUNC_SPI0_MO (MTK_PIN_NO(55) | 2)
315 +#define MT2701_PIN_55_SPI0_MI__FUNC_MSDC1_WP (MTK_PIN_NO(55) | 3)
316 +#define MT2701_PIN_55_SPI0_MI__FUNC_ADC_WS (MTK_PIN_NO(55) | 4)
317 +#define MT2701_PIN_55_SPI0_MI__FUNC_PWM2 (MTK_PIN_NO(55) | 5)
318 +#define MT2701_PIN_55_SPI0_MI__FUNC_DBG_MON_A_8 (MTK_PIN_NO(55) | 7)
319 +
320 +#define MT2701_PIN_56_SPI0_MO__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
321 +#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
322 +#define MT2701_PIN_56_SPI0_MO__FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
323 +#define MT2701_PIN_56_SPI0_MO__FUNC_SPDIF_IN0 (MTK_PIN_NO(56) | 3)
324 +#define MT2701_PIN_56_SPI0_MO__FUNC_DBG_MON_A_9 (MTK_PIN_NO(56) | 7)
325 +
326 +#define MT2701_PIN_57_SDA1__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
327 +#define MT2701_PIN_57_SDA1__FUNC_SDA1 (MTK_PIN_NO(57) | 1)
328 +
329 +#define MT2701_PIN_58_SCL1__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
330 +#define MT2701_PIN_58_SCL1__FUNC_SCL1 (MTK_PIN_NO(58) | 1)
331 +
332 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
333 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_I2S0_DATA_IN (MTK_PIN_NO(72) | 1)
334 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PCM_RX (MTK_PIN_NO(72) | 3)
335 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_PWM0 (MTK_PIN_NO(72) | 4)
336 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DISP_PWM (MTK_PIN_NO(72) | 5)
337 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_WCN_I2S_DI (MTK_PIN_NO(72) | 6)
338 +#define MT2701_PIN_72_I2S0_DATA_IN__FUNC_DBG_MON_B_2 (MTK_PIN_NO(72) | 7)
339 +
340 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
341 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(73) | 1)
342 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_PCM_SYNC (MTK_PIN_NO(73) | 3)
343 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_WCN_I2S_LRCK (MTK_PIN_NO(73) | 6)
344 +#define MT2701_PIN_73_I2S0_LRCK__FUNC_DBG_MON_B_5 (MTK_PIN_NO(73) | 7)
345 +
346 +#define MT2701_PIN_74_I2S0_BCK__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
347 +#define MT2701_PIN_74_I2S0_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(74) | 1)
348 +#define MT2701_PIN_74_I2S0_BCK__FUNC_PCM_CLK0 (MTK_PIN_NO(74) | 3)
349 +#define MT2701_PIN_74_I2S0_BCK__FUNC_WCN_I2S_BCK (MTK_PIN_NO(74) | 6)
350 +#define MT2701_PIN_74_I2S0_BCK__FUNC_DBG_MON_B_4 (MTK_PIN_NO(74) | 7)
351 +
352 +#define MT2701_PIN_75_SDA0__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
353 +#define MT2701_PIN_75_SDA0__FUNC_SDA0 (MTK_PIN_NO(75) | 1)
354 +
355 +#define MT2701_PIN_76_SCL0__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
356 +#define MT2701_PIN_76_SCL0__FUNC_SCL0 (MTK_PIN_NO(76) | 1)
357 +
358 +#define MT2701_PIN_77_SDA2__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
359 +#define MT2701_PIN_77_SDA2__FUNC_SDA2 (MTK_PIN_NO(77) | 1)
360 +
361 +#define MT2701_PIN_78_SCL2__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
362 +#define MT2701_PIN_78_SCL2__FUNC_SCL2 (MTK_PIN_NO(78) | 1)
363 +
364 +#define MT2701_PIN_79_URXD0__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
365 +#define MT2701_PIN_79_URXD0__FUNC_URXD0 (MTK_PIN_NO(79) | 1)
366 +#define MT2701_PIN_79_URXD0__FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
367 +#define MT2701_PIN_79_URXD0__FUNC_ (MTK_PIN_NO(79) | 5)
368 +
369 +#define MT2701_PIN_80_UTXD0__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
370 +#define MT2701_PIN_80_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
371 +#define MT2701_PIN_80_UTXD0__FUNC_URXD0 (MTK_PIN_NO(80) | 2)
372 +
373 +#define MT2701_PIN_81_URXD1__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
374 +#define MT2701_PIN_81_URXD1__FUNC_URXD1 (MTK_PIN_NO(81) | 1)
375 +#define MT2701_PIN_81_URXD1__FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
376 +
377 +#define MT2701_PIN_82_UTXD1__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
378 +#define MT2701_PIN_82_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
379 +#define MT2701_PIN_82_UTXD1__FUNC_URXD1 (MTK_PIN_NO(82) | 2)
380 +
381 +#define MT2701_PIN_83_LCM_RST__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
382 +#define MT2701_PIN_83_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
383 +#define MT2701_PIN_83_LCM_RST__FUNC_VDAC_CK_XI (MTK_PIN_NO(83) | 2)
384 +#define MT2701_PIN_83_LCM_RST__FUNC_DBG_MON_B_1 (MTK_PIN_NO(83) | 7)
385 +
386 +#define MT2701_PIN_84_DSI_TE__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
387 +#define MT2701_PIN_84_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(84) | 1)
388 +#define MT2701_PIN_84_DSI_TE__FUNC_DBG_MON_B_0 (MTK_PIN_NO(84) | 7)
389 +
390 +#define MT2701_PIN_91_TDN3__FUNC_GPI91 (MTK_PIN_NO(91) | 0)
391 +#define MT2701_PIN_91_TDN3__FUNC_TDN3 (MTK_PIN_NO(91) | 1)
392 +
393 +#define MT2701_PIN_92_TDP3__FUNC_GPI92 (MTK_PIN_NO(92) | 0)
394 +#define MT2701_PIN_92_TDP3__FUNC_TDP3 (MTK_PIN_NO(92) | 1)
395 +
396 +#define MT2701_PIN_93_TDN2__FUNC_GPI93 (MTK_PIN_NO(93) | 0)
397 +#define MT2701_PIN_93_TDN2__FUNC_TDN2 (MTK_PIN_NO(93) | 1)
398 +
399 +#define MT2701_PIN_94_TDP2__FUNC_GPI94 (MTK_PIN_NO(94) | 0)
400 +#define MT2701_PIN_94_TDP2__FUNC_TDP2 (MTK_PIN_NO(94) | 1)
401 +
402 +#define MT2701_PIN_95_TCN__FUNC_GPI95 (MTK_PIN_NO(95) | 0)
403 +#define MT2701_PIN_95_TCN__FUNC_TCN (MTK_PIN_NO(95) | 1)
404 +
405 +#define MT2701_PIN_96_TCP__FUNC_GPI96 (MTK_PIN_NO(96) | 0)
406 +#define MT2701_PIN_96_TCP__FUNC_TCP (MTK_PIN_NO(96) | 1)
407 +
408 +#define MT2701_PIN_97_TDN1__FUNC_GPI97 (MTK_PIN_NO(97) | 0)
409 +#define MT2701_PIN_97_TDN1__FUNC_TDN1 (MTK_PIN_NO(97) | 1)
410 +
411 +#define MT2701_PIN_98_TDP1__FUNC_GPI98 (MTK_PIN_NO(98) | 0)
412 +#define MT2701_PIN_98_TDP1__FUNC_TDP1 (MTK_PIN_NO(98) | 1)
413 +
414 +#define MT2701_PIN_99_TDN0__FUNC_GPI99 (MTK_PIN_NO(99) | 0)
415 +#define MT2701_PIN_99_TDN0__FUNC_TDN0 (MTK_PIN_NO(99) | 1)
416 +
417 +#define MT2701_PIN_100_TDP0__FUNC_GPI100 (MTK_PIN_NO(100) | 0)
418 +#define MT2701_PIN_100_TDP0__FUNC_TDP0 (MTK_PIN_NO(100) | 1)
419 +
420 +#define MT2701_PIN_101_SPI2_CSN__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
421 +#define MT2701_PIN_101_SPI2_CSN__FUNC_SPI2_CS (MTK_PIN_NO(101) | 1)
422 +#define MT2701_PIN_101_SPI2_CSN__FUNC_SCL3 (MTK_PIN_NO(101) | 3)
423 +#define MT2701_PIN_101_SPI2_CSN__FUNC_KROW0 (MTK_PIN_NO(101) | 4)
424 +
425 +#define MT2701_PIN_102_SPI2_MI__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
426 +#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MI (MTK_PIN_NO(102) | 1)
427 +#define MT2701_PIN_102_SPI2_MI__FUNC_SPI2_MO (MTK_PIN_NO(102) | 2)
428 +#define MT2701_PIN_102_SPI2_MI__FUNC_SDA3 (MTK_PIN_NO(102) | 3)
429 +#define MT2701_PIN_102_SPI2_MI__FUNC_KROW1 (MTK_PIN_NO(102) | 4)
430 +
431 +#define MT2701_PIN_103_SPI2_MO__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
432 +#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MO (MTK_PIN_NO(103) | 1)
433 +#define MT2701_PIN_103_SPI2_MO__FUNC_SPI2_MI (MTK_PIN_NO(103) | 2)
434 +#define MT2701_PIN_103_SPI2_MO__FUNC_SCL3 (MTK_PIN_NO(103) | 3)
435 +#define MT2701_PIN_103_SPI2_MO__FUNC_KROW2 (MTK_PIN_NO(103) | 4)
436 +
437 +#define MT2701_PIN_104_SPI2_CLK__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
438 +#define MT2701_PIN_104_SPI2_CLK__FUNC_SPI2_CK (MTK_PIN_NO(104) | 1)
439 +#define MT2701_PIN_104_SPI2_CLK__FUNC_SDA3 (MTK_PIN_NO(104) | 3)
440 +#define MT2701_PIN_104_SPI2_CLK__FUNC_KROW3 (MTK_PIN_NO(104) | 4)
441 +
442 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
443 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1)
444 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_ANT_SEL0 (MTK_PIN_NO(105) | 2)
445 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_SDA1 (MTK_PIN_NO(105) | 3)
446 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_I2SOUT_BCK (MTK_PIN_NO(105) | 6)
447 +#define MT2701_PIN_105_MSDC1_CMD__FUNC_DBG_MON_B_27 (MTK_PIN_NO(105) | 7)
448 +
449 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
450 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(106) | 1)
451 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_ANT_SEL1 (MTK_PIN_NO(106) | 2)
452 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_SCL1 (MTK_PIN_NO(106) | 3)
453 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_I2SOUT_LRCK (MTK_PIN_NO(106) | 6)
454 +#define MT2701_PIN_106_MSDC1_CLK__FUNC_DBG_MON_B_28 (MTK_PIN_NO(106) | 7)
455 +
456 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
457 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(107) | 1)
458 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_ANT_SEL2 (MTK_PIN_NO(107) | 2)
459 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_UTXD0 (MTK_PIN_NO(107) | 5)
460 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_I2SOUT_DATA_OUT (MTK_PIN_NO(107) | 6)
461 +#define MT2701_PIN_107_MSDC1_DAT0__FUNC_DBG_MON_B_26 (MTK_PIN_NO(107) | 7)
462 +
463 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
464 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(108) | 1)
465 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_ANT_SEL3 (MTK_PIN_NO(108) | 2)
466 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM0 (MTK_PIN_NO(108) | 3)
467 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_URXD0 (MTK_PIN_NO(108) | 5)
468 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_PWM1 (MTK_PIN_NO(108) | 6)
469 +#define MT2701_PIN_108_MSDC1_DAT1__FUNC_DBG_MON_B_25 (MTK_PIN_NO(108) | 7)
470 +
471 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
472 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(109) | 1)
473 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_ANT_SEL4 (MTK_PIN_NO(109) | 2)
474 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_SDA2 (MTK_PIN_NO(109) | 3)
475 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_UTXD1 (MTK_PIN_NO(109) | 5)
476 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_PWM2 (MTK_PIN_NO(109) | 6)
477 +#define MT2701_PIN_109_MSDC1_DAT2__FUNC_DBG_MON_B_24 (MTK_PIN_NO(109) | 7)
478 +
479 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
480 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(110) | 1)
481 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_ANT_SEL5 (MTK_PIN_NO(110) | 2)
482 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_SCL2 (MTK_PIN_NO(110) | 3)
483 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(110) | 4)
484 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_URXD1 (MTK_PIN_NO(110) | 5)
485 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_PWM3 (MTK_PIN_NO(110) | 6)
486 +#define MT2701_PIN_110_MSDC1_DAT3__FUNC_DBG_MON_B_23 (MTK_PIN_NO(110) | 7)
487 +
488 +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
489 +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(111) | 1)
490 +#define MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(111) | 4)
491 +
492 +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
493 +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(112) | 1)
494 +#define MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(112) | 4)
495 +
496 +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
497 +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(113) | 1)
498 +#define MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5 (MTK_PIN_NO(113) | 4)
499 +
500 +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
501 +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(114) | 1)
502 +#define MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4 (MTK_PIN_NO(114) | 4)
503 +
504 +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
505 +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(115) | 1)
506 +#define MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8 (MTK_PIN_NO(115) | 4)
507 +
508 +#define MT2701_PIN_116_MSDC0_CMD__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
509 +#define MT2701_PIN_116_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(116) | 1)
510 +#define MT2701_PIN_116_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(116) | 4)
511 +
512 +#define MT2701_PIN_117_MSDC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
513 +#define MT2701_PIN_117_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(117) | 1)
514 +#define MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(117) | 4)
515 +
516 +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
517 +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(118) | 1)
518 +#define MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3 (MTK_PIN_NO(118) | 4)
519 +
520 +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
521 +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(119) | 1)
522 +#define MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2 (MTK_PIN_NO(119) | 4)
523 +
524 +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
525 +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(120) | 1)
526 +#define MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1 (MTK_PIN_NO(120) | 4)
527 +
528 +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
529 +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(121) | 1)
530 +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0 (MTK_PIN_NO(121) | 4)
531 +#define MT2701_PIN_121_MSDC0_DAT0__FUNC_WATCHDOG (MTK_PIN_NO(121) | 5)
532 +
533 +#define MT2701_PIN_122_CEC__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
534 +#define MT2701_PIN_122_CEC__FUNC_CEC (MTK_PIN_NO(122) | 1)
535 +#define MT2701_PIN_122_CEC__FUNC_SDA2 (MTK_PIN_NO(122) | 4)
536 +#define MT2701_PIN_122_CEC__FUNC_URXD0 (MTK_PIN_NO(122) | 5)
537 +
538 +#define MT2701_PIN_123_HTPLG__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
539 +#define MT2701_PIN_123_HTPLG__FUNC_HTPLG (MTK_PIN_NO(123) | 1)
540 +#define MT2701_PIN_123_HTPLG__FUNC_SCL2 (MTK_PIN_NO(123) | 4)
541 +#define MT2701_PIN_123_HTPLG__FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
542 +
543 +#define MT2701_PIN_124_HDMISCK__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
544 +#define MT2701_PIN_124_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(124) | 1)
545 +#define MT2701_PIN_124_HDMISCK__FUNC_SDA1 (MTK_PIN_NO(124) | 4)
546 +#define MT2701_PIN_124_HDMISCK__FUNC_PWM3 (MTK_PIN_NO(124) | 5)
547 +
548 +#define MT2701_PIN_125_HDMISD__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
549 +#define MT2701_PIN_125_HDMISD__FUNC_HDMISD (MTK_PIN_NO(125) | 1)
550 +#define MT2701_PIN_125_HDMISD__FUNC_SCL1 (MTK_PIN_NO(125) | 4)
551 +#define MT2701_PIN_125_HDMISD__FUNC_PWM4 (MTK_PIN_NO(125) | 5)
552 +
553 +#define MT2701_PIN_126_I2S0_MCLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
554 +#define MT2701_PIN_126_I2S0_MCLK__FUNC_I2S0_MCLK (MTK_PIN_NO(126) | 1)
555 +#define MT2701_PIN_126_I2S0_MCLK__FUNC_WCN_I2S_MCLK (MTK_PIN_NO(126) | 6)
556 +#define MT2701_PIN_126_I2S0_MCLK__FUNC_DBG_MON_B_6 (MTK_PIN_NO(126) | 7)
557 +
558 +#define MT2701_PIN_199_SPI1_CLK__FUNC_GPIO199 (MTK_PIN_NO(199) | 0)
559 +#define MT2701_PIN_199_SPI1_CLK__FUNC_SPI1_CK (MTK_PIN_NO(199) | 1)
560 +#define MT2701_PIN_199_SPI1_CLK__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(199) | 3)
561 +#define MT2701_PIN_199_SPI1_CLK__FUNC_KCOL3 (MTK_PIN_NO(199) | 4)
562 +#define MT2701_PIN_199_SPI1_CLK__FUNC_DBG_MON_B_15 (MTK_PIN_NO(199) | 7)
563 +
564 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_GPIO200 (MTK_PIN_NO(200) | 0)
565 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_SPDIF_OUT (MTK_PIN_NO(200) | 1)
566 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_G1_TXD3 (MTK_PIN_NO(200) | 5)
567 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_URXD2 (MTK_PIN_NO(200) | 6)
568 +#define MT2701_PIN_200_SPDIF_OUT__FUNC_DBG_MON_B_16 (MTK_PIN_NO(200) | 7)
569 +
570 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_GPIO201 (MTK_PIN_NO(201) | 0)
571 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_SPDIF_IN0 (MTK_PIN_NO(201) | 1)
572 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_G1_TXEN (MTK_PIN_NO(201) | 5)
573 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_UTXD2 (MTK_PIN_NO(201) | 6)
574 +#define MT2701_PIN_201_SPDIF_IN0__FUNC_DBG_MON_B_17 (MTK_PIN_NO(201) | 7)
575 +
576 +#define MT2701_PIN_202_SPDIF_IN1__FUNC_GPIO202 (MTK_PIN_NO(202) | 0)
577 +#define MT2701_PIN_202_SPDIF_IN1__FUNC_SPDIF_IN1 (MTK_PIN_NO(202) | 1)
578 +
579 +#define MT2701_PIN_203_PWM0__FUNC_GPIO203 (MTK_PIN_NO(203) | 0)
580 +#define MT2701_PIN_203_PWM0__FUNC_PWM0 (MTK_PIN_NO(203) | 1)
581 +#define MT2701_PIN_203_PWM0__FUNC_DISP_PWM (MTK_PIN_NO(203) | 2)
582 +#define MT2701_PIN_203_PWM0__FUNC_G1_TXD2 (MTK_PIN_NO(203) | 5)
583 +#define MT2701_PIN_203_PWM0__FUNC_DBG_MON_B_18 (MTK_PIN_NO(203) | 7)
584 +#define MT2701_PIN_203_PWM0__FUNC_I2S2_DATA (MTK_PIN_NO(203) | 9)
585 +
586 +#define MT2701_PIN_204_PWM1__FUNC_GPIO204 (MTK_PIN_NO(204) | 0)
587 +#define MT2701_PIN_204_PWM1__FUNC_PWM1 (MTK_PIN_NO(204) | 1)
588 +#define MT2701_PIN_204_PWM1__FUNC_CLKM3 (MTK_PIN_NO(204) | 2)
589 +#define MT2701_PIN_204_PWM1__FUNC_G1_TXD1 (MTK_PIN_NO(204) | 5)
590 +#define MT2701_PIN_204_PWM1__FUNC_DBG_MON_B_19 (MTK_PIN_NO(204) | 7)
591 +#define MT2701_PIN_204_PWM1__FUNC_I2S3_DATA (MTK_PIN_NO(204) | 9)
592 +
593 +#define MT2701_PIN_205_PWM2__FUNC_GPIO205 (MTK_PIN_NO(205) | 0)
594 +#define MT2701_PIN_205_PWM2__FUNC_PWM2 (MTK_PIN_NO(205) | 1)
595 +#define MT2701_PIN_205_PWM2__FUNC_CLKM2 (MTK_PIN_NO(205) | 2)
596 +#define MT2701_PIN_205_PWM2__FUNC_G1_TXD0 (MTK_PIN_NO(205) | 5)
597 +#define MT2701_PIN_205_PWM2__FUNC_DBG_MON_B_20 (MTK_PIN_NO(205) | 7)
598 +
599 +#define MT2701_PIN_206_PWM3__FUNC_GPIO206 (MTK_PIN_NO(206) | 0)
600 +#define MT2701_PIN_206_PWM3__FUNC_PWM3 (MTK_PIN_NO(206) | 1)
601 +#define MT2701_PIN_206_PWM3__FUNC_CLKM1 (MTK_PIN_NO(206) | 2)
602 +#define MT2701_PIN_206_PWM3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(206) | 3)
603 +#define MT2701_PIN_206_PWM3__FUNC_G1_TXC (MTK_PIN_NO(206) | 5)
604 +#define MT2701_PIN_206_PWM3__FUNC_DBG_MON_B_21 (MTK_PIN_NO(206) | 7)
605 +
606 +#define MT2701_PIN_207_PWM4__FUNC_GPIO207 (MTK_PIN_NO(207) | 0)
607 +#define MT2701_PIN_207_PWM4__FUNC_PWM4 (MTK_PIN_NO(207) | 1)
608 +#define MT2701_PIN_207_PWM4__FUNC_CLKM0 (MTK_PIN_NO(207) | 2)
609 +#define MT2701_PIN_207_PWM4__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(207) | 3)
610 +#define MT2701_PIN_207_PWM4__FUNC_G1_RXC (MTK_PIN_NO(207) | 5)
611 +#define MT2701_PIN_207_PWM4__FUNC_DBG_MON_B_22 (MTK_PIN_NO(207) | 7)
612 +
613 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_GPIO208 (MTK_PIN_NO(208) | 0)
614 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_AUD_EXT_CK1 (MTK_PIN_NO(208) | 1)
615 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PWM0 (MTK_PIN_NO(208) | 2)
616 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_ANT_SEL5 (MTK_PIN_NO(208) | 4)
617 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM (MTK_PIN_NO(208) | 5)
618 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_DBG_MON_A_31 (MTK_PIN_NO(208) | 7)
619 +#define MT2701_PIN_208_AUD_EXT_CK1__FUNC_PCIE0_PERST_N (MTK_PIN_NO(208) | 11)
620 +
621 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_GPIO209 (MTK_PIN_NO(209) | 0)
622 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_AUD_EXT_CK2 (MTK_PIN_NO(209) | 1)
623 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_MSDC1_WP (MTK_PIN_NO(209) | 2)
624 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PWM1 (MTK_PIN_NO(209) | 5)
625 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_DBG_MON_A_32 (MTK_PIN_NO(209) | 7)
626 +#define MT2701_PIN_209_AUD_EXT_CK2__FUNC_PCIE1_PERST_N (MTK_PIN_NO(209) | 11)
627 +
628 +#define MT2701_PIN_236_EXT_SDIO3__FUNC_GPIO236 (MTK_PIN_NO(236) | 0)
629 +#define MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3 (MTK_PIN_NO(236) | 1)
630 +#define MT2701_PIN_236_EXT_SDIO3__FUNC_IDDIG (MTK_PIN_NO(236) | 2)
631 +#define MT2701_PIN_236_EXT_SDIO3__FUNC_DBG_MON_A_1 (MTK_PIN_NO(236) | 7)
632 +
633 +#define MT2701_PIN_237_EXT_SDIO2__FUNC_GPIO237 (MTK_PIN_NO(237) | 0)
634 +#define MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2 (MTK_PIN_NO(237) | 1)
635 +#define MT2701_PIN_237_EXT_SDIO2__FUNC_DRV_VBUS (MTK_PIN_NO(237) | 2)
636 +
637 +#define MT2701_PIN_238_EXT_SDIO1__FUNC_GPIO238 (MTK_PIN_NO(238) | 0)
638 +#define MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1 (MTK_PIN_NO(238) | 1)
639 +#define MT2701_PIN_238_EXT_SDIO1__FUNC_IDDIG_P1 (MTK_PIN_NO(238) | 2)
640 +
641 +#define MT2701_PIN_239_EXT_SDIO0__FUNC_GPIO239 (MTK_PIN_NO(239) | 0)
642 +#define MT2701_PIN_239_EXT_SDIO0__FUNC_EXT_SDIO0 (MTK_PIN_NO(239) | 1)
643 +#define MT2701_PIN_239_EXT_SDIO0__FUNC_DRV_VBUS_P1 (MTK_PIN_NO(239) | 2)
644 +
645 +#define MT2701_PIN_240_EXT_XCS__FUNC_GPIO240 (MTK_PIN_NO(240) | 0)
646 +#define MT2701_PIN_240_EXT_XCS__FUNC_EXT_XCS (MTK_PIN_NO(240) | 1)
647 +
648 +#define MT2701_PIN_241_EXT_SCK__FUNC_GPIO241 (MTK_PIN_NO(241) | 0)
649 +#define MT2701_PIN_241_EXT_SCK__FUNC_EXT_SCK (MTK_PIN_NO(241) | 1)
650 +
651 +#define MT2701_PIN_242_URTS2__FUNC_GPIO242 (MTK_PIN_NO(242) | 0)
652 +#define MT2701_PIN_242_URTS2__FUNC_URTS2 (MTK_PIN_NO(242) | 1)
653 +#define MT2701_PIN_242_URTS2__FUNC_UTXD3 (MTK_PIN_NO(242) | 2)
654 +#define MT2701_PIN_242_URTS2__FUNC_URXD3 (MTK_PIN_NO(242) | 3)
655 +#define MT2701_PIN_242_URTS2__FUNC_SCL1 (MTK_PIN_NO(242) | 4)
656 +#define MT2701_PIN_242_URTS2__FUNC_DBG_MON_B_32 (MTK_PIN_NO(242) | 7)
657 +
658 +#define MT2701_PIN_243_UCTS2__FUNC_GPIO243 (MTK_PIN_NO(243) | 0)
659 +#define MT2701_PIN_243_UCTS2__FUNC_UCTS2 (MTK_PIN_NO(243) | 1)
660 +#define MT2701_PIN_243_UCTS2__FUNC_URXD3 (MTK_PIN_NO(243) | 2)
661 +#define MT2701_PIN_243_UCTS2__FUNC_UTXD3 (MTK_PIN_NO(243) | 3)
662 +#define MT2701_PIN_243_UCTS2__FUNC_SDA1 (MTK_PIN_NO(243) | 4)
663 +#define MT2701_PIN_243_UCTS2__FUNC_DBG_MON_A_6 (MTK_PIN_NO(243) | 7)
664 +
665 +#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_GPIO244 (MTK_PIN_NO(244) | 0)
666 +#define MT2701_PIN_244_HDMI_SDA_RX__FUNC_HDMI_SDA_RX (MTK_PIN_NO(244) | 1)
667 +
668 +#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_GPIO245 (MTK_PIN_NO(245) | 0)
669 +#define MT2701_PIN_245_HDMI_SCL_RX__FUNC_HDMI_SCL_RX (MTK_PIN_NO(245) | 1)
670 +
671 +#define MT2701_PIN_246_MHL_SENCE__FUNC_GPIO246 (MTK_PIN_NO(246) | 0)
672 +
673 +#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_GPIO247 (MTK_PIN_NO(247) | 0)
674 +#define MT2701_PIN_247_HDMI_HPD_CBUS_RX__FUNC_HDMI_HPD_RX (MTK_PIN_NO(247) | 1)
675 +
676 +#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_GPIO248 (MTK_PIN_NO(248) | 0)
677 +#define MT2701_PIN_248_HDMI_TESTOUTP_RX__FUNC_HDMI_TESTOUTP_RX (MTK_PIN_NO(248) | 1)
678 +
679 +#define MT2701_PIN_249_MSDC0E_RSTB__FUNC_MSDC0E_RSTB (MTK_PIN_NO(249) | 9)
680 +
681 +#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_MSDC3_DAT7 (MTK_PIN_NO(250) | 9)
682 +#define MT2701_PIN_250_MSDC0E_DAT7__FUNC_PCIE0_CLKREQ_N (MTK_PIN_NO(250) | 14)
683 +
684 +#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_MSDC3_DAT6 (MTK_PIN_NO(251) | 9)
685 +#define MT2701_PIN_251_MSDC0E_DAT6__FUNC_PCIE0_WAKE_N (MTK_PIN_NO(251) | 14)
686 +
687 +#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_MSDC3_DAT5 (MTK_PIN_NO(252) | 9)
688 +#define MT2701_PIN_252_MSDC0E_DAT5__FUNC_PCIE1_CLKREQ_N (MTK_PIN_NO(252) | 14)
689 +
690 +#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_MSDC3_DAT4 (MTK_PIN_NO(253) | 9)
691 +#define MT2701_PIN_253_MSDC0E_DAT4__FUNC_PCIE1_WAKE_N (MTK_PIN_NO(253) | 14)
692 +
693 +#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_MSDC3_DAT3 (MTK_PIN_NO(254) | 9)
694 +#define MT2701_PIN_254_MSDC0E_DAT3__FUNC_PCIE2_CLKREQ_N (MTK_PIN_NO(254) | 14)
695 +
696 +#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_MSDC3_DAT2 (MTK_PIN_NO(255) | 9)
697 +#define MT2701_PIN_255_MSDC0E_DAT2__FUNC_PCIE2_WAKE_N (MTK_PIN_NO(255) | 14)
698 +
699 +#define MT2701_PIN_256_MSDC0E_DAT1__FUNC_MSDC3_DAT1 (MTK_PIN_NO(256) | 9)
700 +
701 +#define MT2701_PIN_257_MSDC0E_DAT0__FUNC_MSDC3_DAT0 (MTK_PIN_NO(257) | 9)
702 +
703 +#define MT2701_PIN_258_MSDC0E_CMD__FUNC_MSDC3_CMD (MTK_PIN_NO(258) | 9)
704 +
705 +#define MT2701_PIN_259_MSDC0E_CLK__FUNC_MSDC3_CLK (MTK_PIN_NO(259) | 9)
706 +
707 +#define MT2701_PIN_260_MSDC0E_DSL__FUNC_MSDC3_DSL (MTK_PIN_NO(260) | 9)
708 +
709 +#define MT2701_PIN_261_MSDC1_INS__FUNC_GPIO261 (MTK_PIN_NO(261) | 0)
710 +#define MT2701_PIN_261_MSDC1_INS__FUNC_MSDC1_INS (MTK_PIN_NO(261) | 1)
711 +#define MT2701_PIN_261_MSDC1_INS__FUNC_DBG_MON_B_29 (MTK_PIN_NO(261) | 7)
712 +
713 +#define MT2701_PIN_262_G2_TXEN__FUNC_GPIO262 (MTK_PIN_NO(262) | 0)
714 +#define MT2701_PIN_262_G2_TXEN__FUNC_G2_TXEN (MTK_PIN_NO(262) | 1)
715 +
716 +#define MT2701_PIN_263_G2_TXD3__FUNC_GPIO263 (MTK_PIN_NO(263) | 0)
717 +#define MT2701_PIN_263_G2_TXD3__FUNC_G2_TXD3 (MTK_PIN_NO(263) | 1)
718 +#define MT2701_PIN_263_G2_TXD3__FUNC_ANT_SEL5 (MTK_PIN_NO(263) | 6)
719 +
720 +#define MT2701_PIN_264_G2_TXD2__FUNC_GPIO264 (MTK_PIN_NO(264) | 0)
721 +#define MT2701_PIN_264_G2_TXD2__FUNC_G2_TXD2 (MTK_PIN_NO(264) | 1)
722 +#define MT2701_PIN_264_G2_TXD2__FUNC_ANT_SEL4 (MTK_PIN_NO(264) | 6)
723 +
724 +#define MT2701_PIN_265_G2_TXD1__FUNC_GPIO265 (MTK_PIN_NO(265) | 0)
725 +#define MT2701_PIN_265_G2_TXD1__FUNC_G2_TXD1 (MTK_PIN_NO(265) | 1)
726 +#define MT2701_PIN_265_G2_TXD1__FUNC_ANT_SEL3 (MTK_PIN_NO(265) | 6)
727 +
728 +#define MT2701_PIN_266_G2_TXD0__FUNC_GPIO266 (MTK_PIN_NO(266) | 0)
729 +#define MT2701_PIN_266_G2_TXD0__FUNC_G2_TXD0 (MTK_PIN_NO(266) | 1)
730 +#define MT2701_PIN_266_G2_TXD0__FUNC_ANT_SEL2 (MTK_PIN_NO(266) | 6)
731 +
732 +#define MT2701_PIN_267_G2_TXC__FUNC_GPIO267 (MTK_PIN_NO(267) | 0)
733 +#define MT2701_PIN_267_G2_TXC__FUNC_G2_TXC (MTK_PIN_NO(267) | 1)
734 +
735 +#define MT2701_PIN_268_G2_RXC__FUNC_GPIO268 (MTK_PIN_NO(268) | 0)
736 +#define MT2701_PIN_268_G2_RXC__FUNC_G2_RXC (MTK_PIN_NO(268) | 1)
737 +
738 +#define MT2701_PIN_269_G2_RXD0__FUNC_GPIO269 (MTK_PIN_NO(269) | 0)
739 +#define MT2701_PIN_269_G2_RXD0__FUNC_G2_RXD0 (MTK_PIN_NO(269) | 1)
740 +
741 +#define MT2701_PIN_270_G2_RXD1__FUNC_GPIO270 (MTK_PIN_NO(270) | 0)
742 +#define MT2701_PIN_270_G2_RXD1__FUNC_G2_RXD1 (MTK_PIN_NO(270) | 1)
743 +
744 +#define MT2701_PIN_271_G2_RXD2__FUNC_GPIO271 (MTK_PIN_NO(271) | 0)
745 +#define MT2701_PIN_271_G2_RXD2__FUNC_G2_RXD2 (MTK_PIN_NO(271) | 1)
746 +
747 +#define MT2701_PIN_272_G2_RXD3__FUNC_GPIO272 (MTK_PIN_NO(272) | 0)
748 +#define MT2701_PIN_272_G2_RXD3__FUNC_G2_RXD3 (MTK_PIN_NO(272) | 1)
749 +
750 +#define MT2701_PIN_274_G2_RXDV__FUNC_GPIO274 (MTK_PIN_NO(274) | 0)
751 +#define MT2701_PIN_274_G2_RXDV__FUNC_G2_RXDV (MTK_PIN_NO(274) | 1)
752 +
753 +#define MT2701_PIN_275_MDC__FUNC_GPIO275 (MTK_PIN_NO(275) | 0)
754 +#define MT2701_PIN_275_MDC__FUNC_MDC (MTK_PIN_NO(275) | 1)
755 +#define MT2701_PIN_275_MDC__FUNC_ANT_SEL0 (MTK_PIN_NO(275) | 6)
756 +
757 +#define MT2701_PIN_276_MDIO__FUNC_GPIO276 (MTK_PIN_NO(276) | 0)
758 +#define MT2701_PIN_276_MDIO__FUNC_MDIO (MTK_PIN_NO(276) | 1)
759 +#define MT2701_PIN_276_MDIO__FUNC_ANT_SEL1 (MTK_PIN_NO(276) | 6)
760 +
761 +#define MT2701_PIN_278_JTAG_RESET__FUNC_GPIO278 (MTK_PIN_NO(278) | 0)
762 +#define MT2701_PIN_278_JTAG_RESET__FUNC_JTAG_RESET (MTK_PIN_NO(278) | 1)
763 +
764 +#endif /* __DTS_MT2701_PINFUNC_H */
765 diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
766 index 02f6f92..13e9939 100644
767 --- a/drivers/pinctrl/mediatek/Kconfig
768 +++ b/drivers/pinctrl/mediatek/Kconfig
769 @@ -9,6 +9,12 @@ config PINCTRL_MTK_COMMON
770 select OF_GPIO
771
772 # For ARMv7 SoCs
773 +config PINCTRL_MT2701
774 + bool "Mediatek MT2701 pin control" if COMPILE_TEST && !MACH_MT2701
775 + depends on OF
776 + default MACH_MT2701
777 + select PINCTRL_MTK_COMMON
778 +
779 config PINCTRL_MT8135
780 bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
781 depends on OF
782 diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
783 index eb923d6..da30314 100644
784 --- a/drivers/pinctrl/mediatek/Makefile
785 +++ b/drivers/pinctrl/mediatek/Makefile
786 @@ -2,6 +2,7 @@
787 obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
788
789 # SoC Drivers
790 +obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
791 obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
792 obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
793 obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
794 diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
795 new file mode 100644
796 index 0000000..4861b5d
797 --- /dev/null
798 +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c
799 @@ -0,0 +1,586 @@
800 +/*
801 + * Copyright (c) 2015 MediaTek Inc.
802 + * Author: Biao Huang <biao.huang@mediatek.com>
803 + *
804 + * This program is free software; you can redistribute it and/or modify
805 + * it under the terms of the GNU General Public License version 2 as
806 + * published by the Free Software Foundation.
807 + *
808 + * This program is distributed in the hope that it will be useful,
809 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
810 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
811 + * GNU General Public License for more details.
812 + */
813 +
814 +#include <dt-bindings/pinctrl/mt65xx.h>
815 +#include <linux/module.h>
816 +#include <linux/of.h>
817 +#include <linux/of_device.h>
818 +#include <linux/platform_device.h>
819 +#include <linux/pinctrl/pinctrl.h>
820 +#include <linux/regmap.h>
821 +
822 +#include "pinctrl-mtk-common.h"
823 +#include "pinctrl-mtk-mt2701.h"
824 +
825 +/**
826 + * struct mtk_spec_pinmux_set
827 + * - For special pins' mode setting
828 + * @pin: The pin number.
829 + * @offset: The offset of extra setting register.
830 + * @bit: The bit of extra setting register.
831 + */
832 +struct mtk_spec_pinmux_set {
833 + unsigned short pin;
834 + unsigned short offset;
835 + unsigned char bit;
836 +};
837 +
838 +#define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
839 + { \
840 + .pin = _pin, \
841 + .offset = _offset, \
842 + .bit = _bit, \
843 + }
844 +
845 +static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
846 + /* 0E4E8SR 4/8/12/16 */
847 + MTK_DRV_GRP(4, 16, 1, 2, 4),
848 + /* 0E2E4SR 2/4/6/8 */
849 + MTK_DRV_GRP(2, 8, 1, 2, 2),
850 + /* E8E4E2 2/4/6/8/10/12/14/16 */
851 + MTK_DRV_GRP(2, 16, 0, 2, 2)
852 +};
853 +
854 +static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
855 + MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
856 + MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
857 + MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
858 + MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
859 + MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
860 + MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
861 + MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
862 + MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
863 + MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
864 + MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
865 + MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
866 + MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
867 + MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
868 + MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
869 + MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
870 + MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
871 + MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
872 + MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
873 + MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
874 + MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
875 + MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
876 + MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
877 + MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
878 + MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
879 + MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
880 + MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
881 + MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
882 + MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
883 + MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
884 + MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
885 + MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
886 + MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
887 + MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
888 + MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
889 + MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
890 + MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
891 + MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
892 + MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
893 + MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
894 + MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
895 + MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
896 + MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
897 + MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
898 + MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
899 + MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
900 + MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
901 + MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
902 + MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
903 + MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
904 + MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
905 + MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
906 + MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
907 + MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
908 + MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
909 + MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
910 + MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
911 + MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
912 + MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
913 + MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
914 + MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
915 + MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
916 + MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
917 + MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
918 + MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
919 + MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
920 + MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
921 + MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
922 + MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
923 + MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
924 + MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
925 + MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
926 + MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
927 + MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
928 + MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
929 + MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
930 + MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
931 + MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
932 + MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
933 + MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
934 + MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
935 + MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
936 + MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
937 + MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
938 + MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
939 + MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
940 + MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
941 + MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
942 + MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
943 + MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
944 + MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
945 + MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
946 + MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
947 + MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
948 + MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
949 + MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
950 + MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
951 + MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
952 + MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
953 + MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
954 + MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
955 + MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
956 + MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
957 + MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
958 + MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
959 + MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
960 + MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
961 + MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
962 + MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
963 + MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
964 + MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
965 + MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
966 + MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
967 + MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
968 + MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
969 + MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
970 + MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
971 + MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
972 + MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
973 + MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
974 + MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
975 + MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
976 + MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
977 + MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
978 + MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
979 + MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
980 + MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
981 + MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
982 + MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
983 + MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
984 + MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
985 + MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
986 + MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
987 + MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
988 + MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
989 + MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
990 + MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
991 + MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
992 + MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
993 + MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
994 + MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
995 + MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
996 + MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
997 + MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
998 + MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
999 + MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
1000 + MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
1001 + MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
1002 + MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
1003 + MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
1004 + MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
1005 + MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
1006 + MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
1007 + MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
1008 + MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
1009 + MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
1010 + MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
1011 + MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
1012 + MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
1013 + MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
1014 + MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
1015 + MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
1016 + MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
1017 + MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
1018 + MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
1019 + MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
1020 + MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
1021 + MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
1022 + MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
1023 + MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
1024 + MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
1025 + MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
1026 + MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
1027 + MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
1028 + MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
1029 + MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
1030 + MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
1031 + MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
1032 + MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
1033 + MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
1034 + MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
1035 + MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
1036 + MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
1037 +};
1038 +
1039 +static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
1040 + MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14), /* ms0 data7 */
1041 + MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10), /* ms0 data6 */
1042 + MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6), /* ms0 data5 */
1043 + MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2), /* ms0 data4 */
1044 + MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2), /* ms0 rstb */
1045 + MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10), /* ms0 cmd */
1046 + MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10), /* ms0 clk */
1047 + MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14), /* ms0 data3 */
1048 + MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10), /* ms0 data2 */
1049 + MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6), /* ms0 data1 */
1050 + MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2), /* ms0 data0 */
1051 +
1052 + MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10), /* ms1 cmd */
1053 + MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10), /* ms1 clk */
1054 + MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2), /* ms1 dat0 */
1055 + MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8), /* ms1 dat1 */
1056 + MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6), /* ms1 dat2 */
1057 + MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14), /* ms1 dat3 */
1058 +
1059 + MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10), /* ms2 cmd */
1060 + MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10), /* ms2 clk */
1061 + MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2), /* ms2 dat0 */
1062 + MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8), /* ms2 dat1 */
1063 + MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6), /* ms2 dat2 */
1064 + MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14), /* ms2 dat3 */
1065 +
1066 + MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2), /* ms0e rstb */
1067 + MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */
1068 + MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10), /* ms0e dat6 */
1069 + MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6), /* ms0e dat5 */
1070 + MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2), /* ms0e dat4 */
1071 + MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14), /* ms0e dat3 */
1072 + MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10), /* ms0e dat2 */
1073 + MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6), /* ms0e dat1 */
1074 + MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2), /* ms0e dat0 */
1075 + MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10), /* ms0e cmd */
1076 + MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */
1077 + MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
1078 +};
1079 +
1080 +static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
1081 + unsigned char align, bool isup, unsigned int r1r0)
1082 +{
1083 + return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
1084 + ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
1085 +}
1086 +
1087 +static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
1088 + MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
1089 + MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
1090 + MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
1091 + MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
1092 + MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
1093 + MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
1094 + MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
1095 + MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
1096 + MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
1097 + MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
1098 + MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
1099 + MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
1100 + MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
1101 + MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
1102 + MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
1103 + MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
1104 + MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
1105 + MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
1106 + MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
1107 + MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
1108 + MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
1109 + MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
1110 + MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
1111 + MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
1112 + MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
1113 + MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
1114 + MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
1115 + MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
1116 + MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
1117 + MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
1118 + MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
1119 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
1120 + MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
1121 + MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
1122 + MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
1123 + MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
1124 + MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
1125 + MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
1126 + MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
1127 + MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
1128 + MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
1129 + MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
1130 + MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
1131 + MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
1132 + MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
1133 + MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
1134 + MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
1135 + MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
1136 + MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
1137 + MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
1138 + MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
1139 + MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
1140 + MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
1141 + MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
1142 + MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
1143 + MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
1144 + MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
1145 + MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
1146 + MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
1147 + MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
1148 + MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
1149 + MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
1150 + MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
1151 + MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
1152 + MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
1153 + MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
1154 +};
1155 +
1156 +static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
1157 + MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
1158 + MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
1159 + MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
1160 + MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
1161 + MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
1162 + MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
1163 + MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
1164 + MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
1165 + MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
1166 + MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
1167 + MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
1168 + MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
1169 + MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
1170 + MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
1171 + MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
1172 + MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
1173 + MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
1174 + MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
1175 + MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
1176 + MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
1177 + MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
1178 + MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
1179 + MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
1180 + MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
1181 + MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
1182 + MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
1183 + MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
1184 + MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
1185 + MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
1186 + MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
1187 + MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
1188 + MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
1189 + MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
1190 + MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
1191 + MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
1192 + MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
1193 + MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
1194 + MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
1195 + MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
1196 + MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
1197 + MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
1198 + MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
1199 + MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
1200 + MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
1201 + MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
1202 + MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
1203 + MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
1204 + MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
1205 + MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
1206 + MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
1207 + MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
1208 + MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
1209 + MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
1210 + MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
1211 + MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
1212 + MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
1213 + MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
1214 + MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
1215 + MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
1216 + MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
1217 + MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
1218 + MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
1219 + MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
1220 + MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
1221 + MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
1222 + MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
1223 + MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
1224 + MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
1225 + MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
1226 + MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
1227 + MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
1228 + MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
1229 + MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
1230 + MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
1231 + MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
1232 + MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
1233 + MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
1234 + MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
1235 + MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
1236 + MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
1237 + MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
1238 + MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
1239 + MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
1240 + MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
1241 + MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
1242 + MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
1243 + MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
1244 +};
1245 +
1246 +static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
1247 + unsigned char align, int value, enum pin_config_param arg)
1248 +{
1249 + if (arg == PIN_CONFIG_INPUT_ENABLE)
1250 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
1251 + ARRAY_SIZE(mt2701_ies_set), pin, align, value);
1252 + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
1253 + return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
1254 + ARRAY_SIZE(mt2701_smt_set), pin, align, value);
1255 + return -EINVAL;
1256 +}
1257 +
1258 +static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
1259 + MTK_PINMUX_SPEC(22, 0xb10, 3),
1260 + MTK_PINMUX_SPEC(23, 0xb10, 4),
1261 + MTK_PINMUX_SPEC(24, 0xb10, 5),
1262 + MTK_PINMUX_SPEC(29, 0xb10, 9),
1263 + MTK_PINMUX_SPEC(208, 0xb10, 7),
1264 + MTK_PINMUX_SPEC(209, 0xb10, 8),
1265 + MTK_PINMUX_SPEC(203, 0xf20, 0),
1266 + MTK_PINMUX_SPEC(204, 0xf20, 1),
1267 + MTK_PINMUX_SPEC(249, 0xef0, 0),
1268 + MTK_PINMUX_SPEC(250, 0xef0, 0),
1269 + MTK_PINMUX_SPEC(251, 0xef0, 0),
1270 + MTK_PINMUX_SPEC(252, 0xef0, 0),
1271 + MTK_PINMUX_SPEC(253, 0xef0, 0),
1272 + MTK_PINMUX_SPEC(254, 0xef0, 0),
1273 + MTK_PINMUX_SPEC(255, 0xef0, 0),
1274 + MTK_PINMUX_SPEC(256, 0xef0, 0),
1275 + MTK_PINMUX_SPEC(257, 0xef0, 0),
1276 + MTK_PINMUX_SPEC(258, 0xef0, 0),
1277 + MTK_PINMUX_SPEC(259, 0xef0, 0),
1278 + MTK_PINMUX_SPEC(260, 0xef0, 0),
1279 +};
1280 +
1281 +static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
1282 + unsigned int mode)
1283 +{
1284 + unsigned int i, value, mask;
1285 + unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
1286 + unsigned int spec_flag;
1287 +
1288 + for (i = 0; i < info_num; i++) {
1289 + if (pin == mt2701_spec_pinmux[i].pin)
1290 + break;
1291 + }
1292 +
1293 + if (i == info_num)
1294 + return;
1295 +
1296 + spec_flag = (mode >> 3);
1297 + mask = BIT(mt2701_spec_pinmux[i].bit);
1298 + if (!spec_flag)
1299 + value = mask;
1300 + else
1301 + value = 0;
1302 + regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
1303 +}
1304 +
1305 +static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
1306 +{
1307 + if (pin > 175)
1308 + *reg_addr += 0x10;
1309 +}
1310 +
1311 +static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
1312 + .pins = mtk_pins_mt2701,
1313 + .npins = ARRAY_SIZE(mtk_pins_mt2701),
1314 + .grp_desc = mt2701_drv_grp,
1315 + .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
1316 + .pin_drv_grp = mt2701_pin_drv,
1317 + .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
1318 + .spec_pull_set = mt2701_spec_pull_set,
1319 + .spec_ies_smt_set = mt2701_ies_smt_set,
1320 + .spec_pinmux_set = mt2701_spec_pinmux_set,
1321 + .spec_dir_set = mt2701_spec_dir_set,
1322 + .dir_offset = 0x0000,
1323 + .pullen_offset = 0x0150,
1324 + .pullsel_offset = 0x0280,
1325 + .dout_offset = 0x0500,
1326 + .din_offset = 0x0630,
1327 + .pinmux_offset = 0x0760,
1328 + .type1_start = 280,
1329 + .type1_end = 280,
1330 + .port_shf = 4,
1331 + .port_mask = 0x1f,
1332 + .port_align = 4,
1333 + .eint_offsets = {
1334 + .name = "mt2701_eint",
1335 + .stat = 0x000,
1336 + .ack = 0x040,
1337 + .mask = 0x080,
1338 + .mask_set = 0x0c0,
1339 + .mask_clr = 0x100,
1340 + .sens = 0x140,
1341 + .sens_set = 0x180,
1342 + .sens_clr = 0x1c0,
1343 + .soft = 0x200,
1344 + .soft_set = 0x240,
1345 + .soft_clr = 0x280,
1346 + .pol = 0x300,
1347 + .pol_set = 0x340,
1348 + .pol_clr = 0x380,
1349 + .dom_en = 0x400,
1350 + .dbnc_ctrl = 0x500,
1351 + .dbnc_set = 0x600,
1352 + .dbnc_clr = 0x700,
1353 + .port_mask = 6,
1354 + .ports = 6,
1355 + },
1356 + .ap_num = 169,
1357 + .db_cnt = 16,
1358 +};
1359 +
1360 +static int mt2701_pinctrl_probe(struct platform_device *pdev)
1361 +{
1362 + return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
1363 +}
1364 +
1365 +static const struct of_device_id mt2701_pctrl_match[] = {
1366 + { .compatible = "mediatek,mt2701-pinctrl", },
1367 + {}
1368 +};
1369 +MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
1370 +
1371 +static struct platform_driver mtk_pinctrl_driver = {
1372 + .probe = mt2701_pinctrl_probe,
1373 + .driver = {
1374 + .name = "mediatek-mt2701-pinctrl",
1375 + .owner = THIS_MODULE,
1376 + .of_match_table = mt2701_pctrl_match,
1377 + },
1378 +};
1379 +
1380 +static int __init mtk_pinctrl_init(void)
1381 +{
1382 + return platform_driver_register(&mtk_pinctrl_driver);
1383 +}
1384 +
1385 +arch_initcall(mtk_pinctrl_init);
1386 diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
1387 index 5c71727..05ba7a8 100644
1388 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
1389 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
1390 @@ -47,6 +47,8 @@
1391 static const char * const mtk_gpio_functions[] = {
1392 "func0", "func1", "func2", "func3",
1393 "func4", "func5", "func6", "func7",
1394 + "func8", "func9", "func10", "func11",
1395 + "func12", "func13", "func14", "func15",
1396 };
1397
1398 /*
1399 @@ -81,6 +83,9 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1400 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
1401 bit = BIT(offset & 0xf);
1402
1403 + if (pctl->devdata->spec_dir_set)
1404 + pctl->devdata->spec_dir_set(&reg_addr, offset);
1405 +
1406 if (input)
1407 /* Different SoC has different alignment offset. */
1408 reg_addr = CLR_ADDR(reg_addr, pctl);
1409 @@ -347,6 +352,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
1410 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
1411 break;
1412 case PIN_CONFIG_INPUT_ENABLE:
1413 + mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
1414 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
1415 break;
1416 case PIN_CONFIG_OUTPUT:
1417 @@ -354,6 +360,7 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
1418 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
1419 break;
1420 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1421 + mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
1422 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
1423 break;
1424 case PIN_CONFIG_DRIVE_STRENGTH:
1425 @@ -667,9 +674,14 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
1426 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
1427 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1428
1429 + if (pctl->devdata->spec_pinmux_set)
1430 + pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
1431 + pin, mode);
1432 +
1433 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
1434 + pctl->devdata->pinmux_offset;
1435
1436 + mode &= mask;
1437 bit = pin % MAX_GPIO_MODE_PER_REG;
1438 mask <<= (GPIO_MODE_BITS * bit);
1439 val = (mode << (GPIO_MODE_BITS * bit));
1440 @@ -746,6 +758,10 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1441
1442 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
1443 bit = BIT(offset & 0xf);
1444 +
1445 + if (pctl->devdata->spec_dir_set)
1446 + pctl->devdata->spec_dir_set(&reg_addr, offset);
1447 +
1448 regmap_read(pctl->regmap1, reg_addr, &read_val);
1449 return !(read_val & bit);
1450 }
1451 diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
1452 index 55a5343..8543bc4 100644
1453 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
1454 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
1455 @@ -209,7 +209,14 @@ struct mtk_eint_offsets {
1456 * means when user set smt, input enable is set at the same time. So they
1457 * also need special control. If special control is success, this should
1458 * return 0, otherwise return non-zero value.
1459 - *
1460 + * @spec_pinmux_set: In some cases, there are two pinmux functions share
1461 + * the same value in the same segment of pinmux control register. If user
1462 + * want to use one of the two functions, they need an extra bit setting to
1463 + * select the right one.
1464 + * @spec_dir_set: In very few SoCs, direction control registers are not
1465 + * arranged continuously, they may be cut to parts. So they need special
1466 + * dir setting.
1467 +
1468 * @dir_offset: The direction register offset.
1469 * @pullen_offset: The pull-up/pull-down enable register offset.
1470 * @pinmux_offset: The pinmux register offset.
1471 @@ -234,6 +241,9 @@ struct mtk_pinctrl_devdata {
1472 unsigned char align, bool isup, unsigned int arg);
1473 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
1474 unsigned char align, int value, enum pin_config_param arg);
1475 + void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin,
1476 + unsigned int mode);
1477 + void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin);
1478 unsigned int dir_offset;
1479 unsigned int ies_offset;
1480 unsigned int smt_offset;
1481 diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
1482 new file mode 100644
1483 index 0000000..f906420
1484 --- /dev/null
1485 +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
1486 @@ -0,0 +1,2323 @@
1487 +/*
1488 + * Copyright (c) 2015 MediaTek Inc.
1489 + * Author: Biao Huang <biao.huang@mediatek.com>
1490 + *
1491 + * This program is free software; you can redistribute it and/or modify
1492 + * it under the terms of the GNU General Public License version 2 as
1493 + * published by the Free Software Foundation.
1494 + *
1495 + * This program is distributed in the hope that it will be useful,
1496 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1497 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1498 + * GNU General Public License for more details.
1499 + */
1500 +
1501 +#ifndef __PINCTRL_MTK_MT2701_H
1502 +#define __PINCTRL_MTK_MT2701_H
1503 +
1504 +#include <linux/pinctrl/pinctrl.h>
1505 +#include "pinctrl-mtk-common.h"
1506 +
1507 +static const struct mtk_desc_pin mtk_pins_mt2701[] = {
1508 + MTK_PIN(
1509 + PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
1510 + NULL, "mt2701",
1511 + MTK_EINT_FUNCTION(0, 148),
1512 + MTK_FUNCTION(0, "GPIO0"),
1513 + MTK_FUNCTION(1, "PWRAP_SPIDO"),
1514 + MTK_FUNCTION(2, "PWRAP_SPIDI")
1515 + ),
1516 + MTK_PIN(
1517 + PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
1518 + NULL, "mt2701",
1519 + MTK_EINT_FUNCTION(0, 149),
1520 + MTK_FUNCTION(0, "GPIO1"),
1521 + MTK_FUNCTION(1, "PWRAP_SPIDI"),
1522 + MTK_FUNCTION(2, "PWRAP_SPIDO")
1523 + ),
1524 + MTK_PIN(
1525 + PINCTRL_PIN(2, "PWRAP_INT"),
1526 + NULL, "mt2701",
1527 + MTK_EINT_FUNCTION(0, 150),
1528 + MTK_FUNCTION(0, "GPIO2"),
1529 + MTK_FUNCTION(1, "PWRAP_INT")
1530 + ),
1531 + MTK_PIN(
1532 + PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
1533 + NULL, "mt2701",
1534 + MTK_EINT_FUNCTION(0, 151),
1535 + MTK_FUNCTION(0, "GPIO3"),
1536 + MTK_FUNCTION(1, "PWRAP_SPICK_I")
1537 + ),
1538 + MTK_PIN(
1539 + PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
1540 + NULL, "mt2701",
1541 + MTK_EINT_FUNCTION(0, 152),
1542 + MTK_FUNCTION(0, "GPIO4"),
1543 + MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
1544 + ),
1545 + MTK_PIN(
1546 + PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
1547 + NULL, "mt2701",
1548 + MTK_EINT_FUNCTION(0, 153),
1549 + MTK_FUNCTION(0, "GPIO5"),
1550 + MTK_FUNCTION(1, "PWRAP_SPICK2_I"),
1551 + MTK_FUNCTION(5, "ANT_SEL1")
1552 + ),
1553 + MTK_PIN(
1554 + PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
1555 + NULL, "mt2701",
1556 + MTK_EINT_FUNCTION(0, 154),
1557 + MTK_FUNCTION(0, "GPIO6"),
1558 + MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"),
1559 + MTK_FUNCTION(5, "ANT_SEL0"),
1560 + MTK_FUNCTION(7, "DBG_MON_A[0]")
1561 + ),
1562 + MTK_PIN(
1563 + PINCTRL_PIN(7, "SPI1_CSN"),
1564 + NULL, "mt2701",
1565 + MTK_EINT_FUNCTION(0, 155),
1566 + MTK_FUNCTION(0, "GPIO7"),
1567 + MTK_FUNCTION(1, "SPI1_CS"),
1568 + MTK_FUNCTION(4, "KCOL0"),
1569 + MTK_FUNCTION(7, "DBG_MON_B[12]")
1570 + ),
1571 + MTK_PIN(
1572 + PINCTRL_PIN(8, "SPI1_MI"),
1573 + NULL, "mt2701",
1574 + MTK_EINT_FUNCTION(0, 156),
1575 + MTK_FUNCTION(0, "GPIO8"),
1576 + MTK_FUNCTION(1, "SPI1_MI"),
1577 + MTK_FUNCTION(2, "SPI1_MO"),
1578 + MTK_FUNCTION(4, "KCOL1"),
1579 + MTK_FUNCTION(7, "DBG_MON_B[13]")
1580 + ),
1581 + MTK_PIN(
1582 + PINCTRL_PIN(9, "SPI1_MO"),
1583 + NULL, "mt2701",
1584 + MTK_EINT_FUNCTION(0, 157),
1585 + MTK_FUNCTION(0, "GPIO9"),
1586 + MTK_FUNCTION(1, "SPI1_MO"),
1587 + MTK_FUNCTION(2, "SPI1_MI"),
1588 + MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
1589 + MTK_FUNCTION(4, "KCOL2"),
1590 + MTK_FUNCTION(7, "DBG_MON_B[14]")
1591 + ),
1592 + MTK_PIN(
1593 + PINCTRL_PIN(10, "RTC32K_CK"),
1594 + NULL, "mt2701",
1595 + MTK_EINT_FUNCTION(0, 158),
1596 + MTK_FUNCTION(0, "GPIO10"),
1597 + MTK_FUNCTION(1, "RTC32K_CK")
1598 + ),
1599 + MTK_PIN(
1600 + PINCTRL_PIN(11, "WATCHDOG"),
1601 + NULL, "mt2701",
1602 + MTK_EINT_FUNCTION(0, 159),
1603 + MTK_FUNCTION(0, "GPIO11"),
1604 + MTK_FUNCTION(1, "WATCHDOG")
1605 + ),
1606 + MTK_PIN(
1607 + PINCTRL_PIN(12, "SRCLKENA"),
1608 + NULL, "mt2701",
1609 + MTK_EINT_FUNCTION(0, 160),
1610 + MTK_FUNCTION(0, "GPIO12"),
1611 + MTK_FUNCTION(1, "SRCLKENA")
1612 + ),
1613 + MTK_PIN(
1614 + PINCTRL_PIN(13, "SRCLKENAI"),
1615 + NULL, "mt2701",
1616 + MTK_EINT_FUNCTION(0, 161),
1617 + MTK_FUNCTION(0, "GPIO13"),
1618 + MTK_FUNCTION(1, "SRCLKENAI")
1619 + ),
1620 + MTK_PIN(
1621 + PINCTRL_PIN(14, "URXD2"),
1622 + NULL, "mt2701",
1623 + MTK_EINT_FUNCTION(0, 162),
1624 + MTK_FUNCTION(0, "GPIO14"),
1625 + MTK_FUNCTION(1, "URXD2"),
1626 + MTK_FUNCTION(2, "UTXD2"),
1627 + MTK_FUNCTION(5, "SRCCLKENAI2"),
1628 + MTK_FUNCTION(7, "DBG_MON_B[30]")
1629 + ),
1630 + MTK_PIN(
1631 + PINCTRL_PIN(15, "UTXD2"),
1632 + NULL, "mt2701",
1633 + MTK_EINT_FUNCTION(0, 163),
1634 + MTK_FUNCTION(0, "GPIO15"),
1635 + MTK_FUNCTION(1, "UTXD2"),
1636 + MTK_FUNCTION(2, "URXD2"),
1637 + MTK_FUNCTION(7, "DBG_MON_B[31]")
1638 + ),
1639 + MTK_PIN(
1640 + PINCTRL_PIN(16, "I2S5_DATA_IN"),
1641 + NULL, "mt2701",
1642 + MTK_EINT_FUNCTION(0, 164),
1643 + MTK_FUNCTION(0, "GPIO16"),
1644 + MTK_FUNCTION(1, "I2S5_DATA_IN"),
1645 + MTK_FUNCTION(3, "PCM_RX"),
1646 + MTK_FUNCTION(4, "ANT_SEL4")
1647 + ),
1648 + MTK_PIN(
1649 + PINCTRL_PIN(17, "I2S5_BCK"),
1650 + NULL, "mt2701",
1651 + MTK_EINT_FUNCTION(0, 165),
1652 + MTK_FUNCTION(0, "GPIO17"),
1653 + MTK_FUNCTION(1, "I2S5_BCK"),
1654 + MTK_FUNCTION(3, "PCM_CLK0"),
1655 + MTK_FUNCTION(4, "ANT_SEL2")
1656 + ),
1657 + MTK_PIN(
1658 + PINCTRL_PIN(18, "PCM_CLK"),
1659 + NULL, "mt2701",
1660 + MTK_EINT_FUNCTION(0, 166),
1661 + MTK_FUNCTION(0, "GPIO18"),
1662 + MTK_FUNCTION(1, "PCM_CLK0"),
1663 + MTK_FUNCTION(2, "MRG_CLK"),
1664 + MTK_FUNCTION(4, "MM_TEST_CK"),
1665 + MTK_FUNCTION(5, "CONN_DSP_JCK"),
1666 + MTK_FUNCTION(6, "WCN_PCM_CLKO"),
1667 + MTK_FUNCTION(7, "DBG_MON_A[3]")
1668 + ),
1669 + MTK_PIN(
1670 + PINCTRL_PIN(19, "PCM_SYNC"),
1671 + NULL, "mt2701",
1672 + MTK_EINT_FUNCTION(0, 167),
1673 + MTK_FUNCTION(0, "GPIO19"),
1674 + MTK_FUNCTION(1, "PCM_SYNC"),
1675 + MTK_FUNCTION(2, "MRG_SYNC"),
1676 + MTK_FUNCTION(5, "CONN_DSP_JINTP"),
1677 + MTK_FUNCTION(6, "WCN_PCM_SYNC"),
1678 + MTK_FUNCTION(7, "DBG_MON_A[5]")
1679 + ),
1680 + MTK_PIN(
1681 + PINCTRL_PIN(20, "PCM_RX"),
1682 + NULL, "mt2701",
1683 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1684 + MTK_FUNCTION(0, "GPIO20"),
1685 + MTK_FUNCTION(1, "PCM_RX"),
1686 + MTK_FUNCTION(2, "MRG_RX"),
1687 + MTK_FUNCTION(3, "MRG_TX"),
1688 + MTK_FUNCTION(4, "PCM_TX"),
1689 + MTK_FUNCTION(5, "CONN_DSP_JDI"),
1690 + MTK_FUNCTION(6, "WCN_PCM_RX"),
1691 + MTK_FUNCTION(7, "DBG_MON_A[4]")
1692 + ),
1693 + MTK_PIN(
1694 + PINCTRL_PIN(21, "PCM_TX"),
1695 + NULL, "mt2701",
1696 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1697 + MTK_FUNCTION(0, "GPIO21"),
1698 + MTK_FUNCTION(1, "PCM_TX"),
1699 + MTK_FUNCTION(2, "MRG_TX"),
1700 + MTK_FUNCTION(3, "MRG_RX"),
1701 + MTK_FUNCTION(4, "PCM_RX"),
1702 + MTK_FUNCTION(5, "CONN_DSP_JMS"),
1703 + MTK_FUNCTION(6, "WCN_PCM_TX"),
1704 + MTK_FUNCTION(7, "DBG_MON_A[2]")
1705 + ),
1706 + MTK_PIN(
1707 + PINCTRL_PIN(22, "EINT0"),
1708 + NULL, "mt2701",
1709 + MTK_EINT_FUNCTION(0, 0),
1710 + MTK_FUNCTION(0, "GPIO22"),
1711 + MTK_FUNCTION(1, "UCTS0"),
1712 + MTK_FUNCTION(3, "KCOL3"),
1713 + MTK_FUNCTION(4, "CONN_DSP_JDO"),
1714 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
1715 + MTK_FUNCTION(7, "DBG_MON_A[30]"),
1716 + MTK_FUNCTION(10, "PCIE0_PERST_N")
1717 + ),
1718 + MTK_PIN(
1719 + PINCTRL_PIN(23, "EINT1"),
1720 + NULL, "mt2701",
1721 + MTK_EINT_FUNCTION(0, 1),
1722 + MTK_FUNCTION(0, "GPIO23"),
1723 + MTK_FUNCTION(1, "URTS0"),
1724 + MTK_FUNCTION(3, "KCOL2"),
1725 + MTK_FUNCTION(4, "CONN_MCU_TDO"),
1726 + MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
1727 + MTK_FUNCTION(7, "DBG_MON_A[29]"),
1728 + MTK_FUNCTION(10, "PCIE1_PERST_N")
1729 + ),
1730 + MTK_PIN(
1731 + PINCTRL_PIN(24, "EINT2"),
1732 + NULL, "mt2701",
1733 + MTK_EINT_FUNCTION(0, 2),
1734 + MTK_FUNCTION(0, "GPIO24"),
1735 + MTK_FUNCTION(1, "UCTS1"),
1736 + MTK_FUNCTION(3, "KCOL1"),
1737 + MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"),
1738 + MTK_FUNCTION(7, "DBG_MON_A[28]"),
1739 + MTK_FUNCTION(10, "PCIE2_PERST_N")
1740 + ),
1741 + MTK_PIN(
1742 + PINCTRL_PIN(25, "EINT3"),
1743 + NULL, "mt2701",
1744 + MTK_EINT_FUNCTION(0, 3),
1745 + MTK_FUNCTION(0, "GPIO25"),
1746 + MTK_FUNCTION(1, "URTS1"),
1747 + MTK_FUNCTION(3, "KCOL0"),
1748 + MTK_FUNCTION(4, "CONN_MCU_DBGI_N"),
1749 + MTK_FUNCTION(7, "DBG_MON_A[27]")
1750 + ),
1751 + MTK_PIN(
1752 + PINCTRL_PIN(26, "EINT4"),
1753 + NULL, "mt2701",
1754 + MTK_EINT_FUNCTION(0, 4),
1755 + MTK_FUNCTION(0, "GPIO26"),
1756 + MTK_FUNCTION(1, "UCTS3"),
1757 + MTK_FUNCTION(2, "DRV_VBUS_P1"),
1758 + MTK_FUNCTION(3, "KROW3"),
1759 + MTK_FUNCTION(4, "CONN_MCU_TCK0"),
1760 + MTK_FUNCTION(5, "CONN_MCU_AICE_JCKC"),
1761 + MTK_FUNCTION(6, "PCIE2_WAKE_N"),
1762 + MTK_FUNCTION(7, "DBG_MON_A[26]")
1763 + ),
1764 + MTK_PIN(
1765 + PINCTRL_PIN(27, "EINT5"),
1766 + NULL, "mt2701",
1767 + MTK_EINT_FUNCTION(0, 5),
1768 + MTK_FUNCTION(0, "GPIO27"),
1769 + MTK_FUNCTION(1, "URTS3"),
1770 + MTK_FUNCTION(2, "IDDIG_P1"),
1771 + MTK_FUNCTION(3, "KROW2"),
1772 + MTK_FUNCTION(4, "CONN_MCU_TDI"),
1773 + MTK_FUNCTION(6, "PCIE1_WAKE_N"),
1774 + MTK_FUNCTION(7, "DBG_MON_A[25]")
1775 + ),
1776 + MTK_PIN(
1777 + PINCTRL_PIN(28, "EINT6"),
1778 + NULL, "mt2701",
1779 + MTK_EINT_FUNCTION(0, 6),
1780 + MTK_FUNCTION(0, "GPIO28"),
1781 + MTK_FUNCTION(1, "DRV_VBUS"),
1782 + MTK_FUNCTION(3, "KROW1"),
1783 + MTK_FUNCTION(4, "CONN_MCU_TRST_B"),
1784 + MTK_FUNCTION(6, "PCIE0_WAKE_N"),
1785 + MTK_FUNCTION(7, "DBG_MON_A[24]")
1786 + ),
1787 + MTK_PIN(
1788 + PINCTRL_PIN(29, "EINT7"),
1789 + NULL, "mt2701",
1790 + MTK_EINT_FUNCTION(0, 7),
1791 + MTK_FUNCTION(0, "GPIO29"),
1792 + MTK_FUNCTION(1, "IDDIG"),
1793 + MTK_FUNCTION(2, "MSDC1_WP"),
1794 + MTK_FUNCTION(3, "KROW0"),
1795 + MTK_FUNCTION(4, "CONN_MCU_TMS"),
1796 + MTK_FUNCTION(5, "CONN_MCU_AICE_JMSC"),
1797 + MTK_FUNCTION(7, "DBG_MON_A[23]"),
1798 + MTK_FUNCTION(14, "PCIE2_PERST_N")
1799 + ),
1800 + MTK_PIN(
1801 + PINCTRL_PIN(30, "I2S5_LRCK"),
1802 + NULL, "mt2701",
1803 + MTK_EINT_FUNCTION(0, 12),
1804 + MTK_FUNCTION(0, "GPIO30"),
1805 + MTK_FUNCTION(1, "I2S5_LRCK"),
1806 + MTK_FUNCTION(3, "PCM_SYNC"),
1807 + MTK_FUNCTION(4, "ANT_SEL1")
1808 + ),
1809 + MTK_PIN(
1810 + PINCTRL_PIN(31, "I2S5_MCLK"),
1811 + NULL, "mt2701",
1812 + MTK_EINT_FUNCTION(0, 13),
1813 + MTK_FUNCTION(0, "GPIO31"),
1814 + MTK_FUNCTION(1, "I2S5_MCLK"),
1815 + MTK_FUNCTION(4, "ANT_SEL0")
1816 + ),
1817 + MTK_PIN(
1818 + PINCTRL_PIN(32, "I2S5_DATA"),
1819 + NULL, "mt2701",
1820 + MTK_EINT_FUNCTION(0, 14),
1821 + MTK_FUNCTION(0, "GPIO32"),
1822 + MTK_FUNCTION(1, "I2S5_DATA"),
1823 + MTK_FUNCTION(2, "I2S5_DATA_BYPS"),
1824 + MTK_FUNCTION(3, "PCM_TX"),
1825 + MTK_FUNCTION(4, "ANT_SEL3")
1826 + ),
1827 + MTK_PIN(
1828 + PINCTRL_PIN(33, "I2S1_DATA"),
1829 + NULL, "mt2701",
1830 + MTK_EINT_FUNCTION(0, 15),
1831 + MTK_FUNCTION(0, "GPIO33"),
1832 + MTK_FUNCTION(1, "I2S1_DATA"),
1833 + MTK_FUNCTION(2, "I2S1_DATA_BYPS"),
1834 + MTK_FUNCTION(3, "PCM_TX"),
1835 + MTK_FUNCTION(4, "IMG_TEST_CK"),
1836 + MTK_FUNCTION(5, "G1_RXD0"),
1837 + MTK_FUNCTION(6, "WCN_PCM_TX"),
1838 + MTK_FUNCTION(7, "DBG_MON_B[8]")
1839 + ),
1840 + MTK_PIN(
1841 + PINCTRL_PIN(34, "I2S1_DATA_IN"),
1842 + NULL, "mt2701",
1843 + MTK_EINT_FUNCTION(0, 16),
1844 + MTK_FUNCTION(0, "GPIO34"),
1845 + MTK_FUNCTION(1, "I2S1_DATA_IN"),
1846 + MTK_FUNCTION(3, "PCM_RX"),
1847 + MTK_FUNCTION(4, "VDEC_TEST_CK"),
1848 + MTK_FUNCTION(5, "G1_RXD1"),
1849 + MTK_FUNCTION(6, "WCN_PCM_RX"),
1850 + MTK_FUNCTION(7, "DBG_MON_B[7]")
1851 + ),
1852 + MTK_PIN(
1853 + PINCTRL_PIN(35, "I2S1_BCK"),
1854 + NULL, "mt2701",
1855 + MTK_EINT_FUNCTION(0, 17),
1856 + MTK_FUNCTION(0, "GPIO35"),
1857 + MTK_FUNCTION(1, "I2S1_BCK"),
1858 + MTK_FUNCTION(3, "PCM_CLK0"),
1859 + MTK_FUNCTION(5, "G1_RXD2"),
1860 + MTK_FUNCTION(6, "WCN_PCM_CLKO"),
1861 + MTK_FUNCTION(7, "DBG_MON_B[9]")
1862 + ),
1863 + MTK_PIN(
1864 + PINCTRL_PIN(36, "I2S1_LRCK"),
1865 + NULL, "mt2701",
1866 + MTK_EINT_FUNCTION(0, 18),
1867 + MTK_FUNCTION(0, "GPIO36"),
1868 + MTK_FUNCTION(1, "I2S1_LRCK"),
1869 + MTK_FUNCTION(3, "PCM_SYNC"),
1870 + MTK_FUNCTION(5, "G1_RXD3"),
1871 + MTK_FUNCTION(6, "WCN_PCM_SYNC"),
1872 + MTK_FUNCTION(7, "DBG_MON_B[10]")
1873 + ),
1874 + MTK_PIN(
1875 + PINCTRL_PIN(37, "I2S1_MCLK"),
1876 + NULL, "mt2701",
1877 + MTK_EINT_FUNCTION(0, 19),
1878 + MTK_FUNCTION(0, "GPIO37"),
1879 + MTK_FUNCTION(1, "I2S1_MCLK"),
1880 + MTK_FUNCTION(5, "G1_RXDV"),
1881 + MTK_FUNCTION(7, "DBG_MON_B[11]")
1882 + ),
1883 + MTK_PIN(
1884 + PINCTRL_PIN(38, "I2S2_DATA"),
1885 + NULL, "mt2701",
1886 + MTK_EINT_FUNCTION(0, 20),
1887 + MTK_FUNCTION(0, "GPIO38"),
1888 + MTK_FUNCTION(2, "I2S2_DATA_BYPS"),
1889 + MTK_FUNCTION(3, "PCM_TX"),
1890 + MTK_FUNCTION(4, "DMIC_DAT0")
1891 + ),
1892 + MTK_PIN(
1893 + PINCTRL_PIN(39, "JTMS"),
1894 + NULL, "mt2701",
1895 + MTK_EINT_FUNCTION(0, 21),
1896 + MTK_FUNCTION(0, "GPIO39"),
1897 + MTK_FUNCTION(1, "JTMS"),
1898 + MTK_FUNCTION(2, "CONN_MCU_TMS"),
1899 + MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC"),
1900 + MTK_FUNCTION(4, "DFD_TMS_XI")
1901 + ),
1902 + MTK_PIN(
1903 + PINCTRL_PIN(40, "JTCK"),
1904 + NULL, "mt2701",
1905 + MTK_EINT_FUNCTION(0, 22),
1906 + MTK_FUNCTION(0, "GPIO40"),
1907 + MTK_FUNCTION(1, "JTCK"),
1908 + MTK_FUNCTION(2, "CONN_MCU_TCK1"),
1909 + MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC"),
1910 + MTK_FUNCTION(4, "DFD_TCK_XI")
1911 + ),
1912 + MTK_PIN(
1913 + PINCTRL_PIN(41, "JTDI"),
1914 + NULL, "mt2701",
1915 + MTK_EINT_FUNCTION(0, 23),
1916 + MTK_FUNCTION(0, "GPIO41"),
1917 + MTK_FUNCTION(1, "JTDI"),
1918 + MTK_FUNCTION(2, "CONN_MCU_TDI"),
1919 + MTK_FUNCTION(4, "DFD_TDI_XI")
1920 + ),
1921 + MTK_PIN(
1922 + PINCTRL_PIN(42, "JTDO"),
1923 + NULL, "mt2701",
1924 + MTK_EINT_FUNCTION(0, 24),
1925 + MTK_FUNCTION(0, "GPIO42"),
1926 + MTK_FUNCTION(1, "JTDO"),
1927 + MTK_FUNCTION(2, "CONN_MCU_TDO"),
1928 + MTK_FUNCTION(4, "DFD_TDO")
1929 + ),
1930 + MTK_PIN(
1931 + PINCTRL_PIN(43, "NCLE"),
1932 + NULL, "mt2701",
1933 + MTK_EINT_FUNCTION(0, 25),
1934 + MTK_FUNCTION(0, "GPIO43"),
1935 + MTK_FUNCTION(1, "NCLE"),
1936 + MTK_FUNCTION(2, "EXT_XCS2")
1937 + ),
1938 + MTK_PIN(
1939 + PINCTRL_PIN(44, "NCEB1"),
1940 + NULL, "mt2701",
1941 + MTK_EINT_FUNCTION(0, 26),
1942 + MTK_FUNCTION(0, "GPIO44"),
1943 + MTK_FUNCTION(1, "NCEB1"),
1944 + MTK_FUNCTION(2, "IDDIG")
1945 + ),
1946 + MTK_PIN(
1947 + PINCTRL_PIN(45, "NCEB0"),
1948 + NULL, "mt2701",
1949 + MTK_EINT_FUNCTION(0, 27),
1950 + MTK_FUNCTION(0, "GPIO45"),
1951 + MTK_FUNCTION(1, "NCEB0"),
1952 + MTK_FUNCTION(2, "DRV_VBUS")
1953 + ),
1954 + MTK_PIN(
1955 + PINCTRL_PIN(46, "IR"),
1956 + NULL, "mt2701",
1957 + MTK_EINT_FUNCTION(0, 28),
1958 + MTK_FUNCTION(0, "GPIO46"),
1959 + MTK_FUNCTION(1, "IR")
1960 + ),
1961 + MTK_PIN(
1962 + PINCTRL_PIN(47, "NREB"),
1963 + NULL, "mt2701",
1964 + MTK_EINT_FUNCTION(0, 29),
1965 + MTK_FUNCTION(0, "GPIO47"),
1966 + MTK_FUNCTION(1, "NREB"),
1967 + MTK_FUNCTION(2, "IDDIG_P1")
1968 + ),
1969 + MTK_PIN(
1970 + PINCTRL_PIN(48, "NRNB"),
1971 + NULL, "mt2701",
1972 + MTK_EINT_FUNCTION(0, 30),
1973 + MTK_FUNCTION(0, "GPIO48"),
1974 + MTK_FUNCTION(1, "NRNB"),
1975 + MTK_FUNCTION(2, "DRV_VBUS_P1")
1976 + ),
1977 + MTK_PIN(
1978 + PINCTRL_PIN(49, "I2S0_DATA"),
1979 + NULL, "mt2701",
1980 + MTK_EINT_FUNCTION(0, 31),
1981 + MTK_FUNCTION(0, "GPIO49"),
1982 + MTK_FUNCTION(1, "I2S0_DATA"),
1983 + MTK_FUNCTION(2, "I2S0_DATA_BYPS"),
1984 + MTK_FUNCTION(3, "PCM_TX"),
1985 + MTK_FUNCTION(6, "WCN_I2S_DO"),
1986 + MTK_FUNCTION(7, "DBG_MON_B[3]")
1987 + ),
1988 + MTK_PIN(
1989 + PINCTRL_PIN(50, "I2S2_BCK"),
1990 + NULL, "mt2701",
1991 + MTK_EINT_FUNCTION(0, 32),
1992 + MTK_FUNCTION(0, "GPIO50"),
1993 + MTK_FUNCTION(1, "I2S2_BCK"),
1994 + MTK_FUNCTION(3, "PCM_CLK0"),
1995 + MTK_FUNCTION(4, "DMIC_SCK1")
1996 + ),
1997 + MTK_PIN(
1998 + PINCTRL_PIN(51, "I2S2_DATA_IN"),
1999 + NULL, "mt2701",
2000 + MTK_EINT_FUNCTION(0, 33),
2001 + MTK_FUNCTION(0, "GPIO51"),
2002 + MTK_FUNCTION(1, "I2S2_DATA_IN"),
2003 + MTK_FUNCTION(3, "PCM_RX"),
2004 + MTK_FUNCTION(4, "DMIC_SCK0")
2005 + ),
2006 + MTK_PIN(
2007 + PINCTRL_PIN(52, "I2S2_LRCK"),
2008 + NULL, "mt2701",
2009 + MTK_EINT_FUNCTION(0, 34),
2010 + MTK_FUNCTION(0, "GPIO52"),
2011 + MTK_FUNCTION(1, "I2S2_LRCK"),
2012 + MTK_FUNCTION(3, "PCM_SYNC"),
2013 + MTK_FUNCTION(4, "DMIC_DAT1")
2014 + ),
2015 + MTK_PIN(
2016 + PINCTRL_PIN(53, "SPI0_CSN"),
2017 + NULL, "mt2701",
2018 + MTK_EINT_FUNCTION(0, 35),
2019 + MTK_FUNCTION(0, "GPIO53"),
2020 + MTK_FUNCTION(1, "SPI0_CS"),
2021 + MTK_FUNCTION(3, "SPDIF"),
2022 + MTK_FUNCTION(4, "ADC_CK"),
2023 + MTK_FUNCTION(5, "PWM1"),
2024 + MTK_FUNCTION(7, "DBG_MON_A[7]")
2025 + ),
2026 + MTK_PIN(
2027 + PINCTRL_PIN(54, "SPI0_CK"),
2028 + NULL, "mt2701",
2029 + MTK_EINT_FUNCTION(0, 36),
2030 + MTK_FUNCTION(0, "GPIO54"),
2031 + MTK_FUNCTION(1, "SPI0_CK"),
2032 + MTK_FUNCTION(3, "SPDIF_IN1"),
2033 + MTK_FUNCTION(4, "ADC_DAT_IN"),
2034 + MTK_FUNCTION(7, "DBG_MON_A[10]")
2035 + ),
2036 + MTK_PIN(
2037 + PINCTRL_PIN(55, "SPI0_MI"),
2038 + NULL, "mt2701",
2039 + MTK_EINT_FUNCTION(0, 37),
2040 + MTK_FUNCTION(0, "GPIO55"),
2041 + MTK_FUNCTION(1, "SPI0_MI"),
2042 + MTK_FUNCTION(2, "SPI0_MO"),
2043 + MTK_FUNCTION(3, "MSDC1_WP"),
2044 + MTK_FUNCTION(4, "ADC_WS"),
2045 + MTK_FUNCTION(5, "PWM2"),
2046 + MTK_FUNCTION(7, "DBG_MON_A[8]")
2047 + ),
2048 + MTK_PIN(
2049 + PINCTRL_PIN(56, "SPI0_MO"),
2050 + NULL, "mt2701",
2051 + MTK_EINT_FUNCTION(0, 38),
2052 + MTK_FUNCTION(0, "GPIO56"),
2053 + MTK_FUNCTION(1, "SPI0_MO"),
2054 + MTK_FUNCTION(2, "SPI0_MI"),
2055 + MTK_FUNCTION(3, "SPDIF_IN0"),
2056 + MTK_FUNCTION(7, "DBG_MON_A[9]")
2057 + ),
2058 + MTK_PIN(
2059 + PINCTRL_PIN(57, "SDA1"),
2060 + NULL, "mt2701",
2061 + MTK_EINT_FUNCTION(0, 39),
2062 + MTK_FUNCTION(0, "GPIO57"),
2063 + MTK_FUNCTION(1, "SDA1")
2064 + ),
2065 + MTK_PIN(
2066 + PINCTRL_PIN(58, "SCL1"),
2067 + NULL, "mt2701",
2068 + MTK_EINT_FUNCTION(0, 40),
2069 + MTK_FUNCTION(0, "GPIO58"),
2070 + MTK_FUNCTION(1, "SCL1")
2071 + ),
2072 + MTK_PIN(
2073 + PINCTRL_PIN(59, "RAMBUF_I_CLK"),
2074 + NULL, "mt2701",
2075 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2076 + MTK_FUNCTION(0, "GPIO59"),
2077 + MTK_FUNCTION(1, "RAMBUF_I_CLK")
2078 + ),
2079 + MTK_PIN(
2080 + PINCTRL_PIN(60, "WB_RSTB"),
2081 + NULL, "mt2701",
2082 + MTK_EINT_FUNCTION(0, 41),
2083 + MTK_FUNCTION(0, "GPIO60"),
2084 + MTK_FUNCTION(1, "WB_RSTB"),
2085 + MTK_FUNCTION(7, "DBG_MON_A[11]")
2086 + ),
2087 + MTK_PIN(
2088 + PINCTRL_PIN(61, "F2W_DATA"),
2089 + NULL, "mt2701",
2090 + MTK_EINT_FUNCTION(0, 42),
2091 + MTK_FUNCTION(0, "GPIO61"),
2092 + MTK_FUNCTION(1, "F2W_DATA"),
2093 + MTK_FUNCTION(7, "DBG_MON_A[16]")
2094 + ),
2095 + MTK_PIN(
2096 + PINCTRL_PIN(62, "F2W_CLK"),
2097 + NULL, "mt2701",
2098 + MTK_EINT_FUNCTION(0, 43),
2099 + MTK_FUNCTION(0, "GPIO62"),
2100 + MTK_FUNCTION(1, "F2W_CK"),
2101 + MTK_FUNCTION(7, "DBG_MON_A[15]")
2102 + ),
2103 + MTK_PIN(
2104 + PINCTRL_PIN(63, "WB_SCLK"),
2105 + NULL, "mt2701",
2106 + MTK_EINT_FUNCTION(0, 44),
2107 + MTK_FUNCTION(0, "GPIO63"),
2108 + MTK_FUNCTION(1, "WB_SCLK"),
2109 + MTK_FUNCTION(7, "DBG_MON_A[13]")
2110 + ),
2111 + MTK_PIN(
2112 + PINCTRL_PIN(64, "WB_SDATA"),
2113 + NULL, "mt2701",
2114 + MTK_EINT_FUNCTION(0, 45),
2115 + MTK_FUNCTION(0, "GPIO64"),
2116 + MTK_FUNCTION(1, "WB_SDATA"),
2117 + MTK_FUNCTION(7, "DBG_MON_A[12]")
2118 + ),
2119 + MTK_PIN(
2120 + PINCTRL_PIN(65, "WB_SEN"),
2121 + NULL, "mt2701",
2122 + MTK_EINT_FUNCTION(0, 46),
2123 + MTK_FUNCTION(0, "GPIO65"),
2124 + MTK_FUNCTION(1, "WB_SEN"),
2125 + MTK_FUNCTION(7, "DBG_MON_A[14]")
2126 + ),
2127 + MTK_PIN(
2128 + PINCTRL_PIN(66, "WB_CRTL0"),
2129 + NULL, "mt2701",
2130 + MTK_EINT_FUNCTION(0, 47),
2131 + MTK_FUNCTION(0, "GPIO66"),
2132 + MTK_FUNCTION(1, "WB_CRTL0"),
2133 + MTK_FUNCTION(5, "DFD_NTRST_XI"),
2134 + MTK_FUNCTION(7, "DBG_MON_A[17]")
2135 + ),
2136 + MTK_PIN(
2137 + PINCTRL_PIN(67, "WB_CRTL1"),
2138 + NULL, "mt2701",
2139 + MTK_EINT_FUNCTION(0, 48),
2140 + MTK_FUNCTION(0, "GPIO67"),
2141 + MTK_FUNCTION(1, "WB_CRTL1"),
2142 + MTK_FUNCTION(5, "DFD_TMS_XI"),
2143 + MTK_FUNCTION(7, "DBG_MON_A[18]")
2144 + ),
2145 + MTK_PIN(
2146 + PINCTRL_PIN(68, "WB_CRTL2"),
2147 + NULL, "mt2701",
2148 + MTK_EINT_FUNCTION(0, 49),
2149 + MTK_FUNCTION(0, "GPIO68"),
2150 + MTK_FUNCTION(1, "WB_CRTL2"),
2151 + MTK_FUNCTION(5, "DFD_TCK_XI"),
2152 + MTK_FUNCTION(7, "DBG_MON_A[19]")
2153 + ),
2154 + MTK_PIN(
2155 + PINCTRL_PIN(69, "WB_CRTL3"),
2156 + NULL, "mt2701",
2157 + MTK_EINT_FUNCTION(0, 50),
2158 + MTK_FUNCTION(0, "GPIO69"),
2159 + MTK_FUNCTION(1, "WB_CRTL3"),
2160 + MTK_FUNCTION(5, "DFD_TDI_XI"),
2161 + MTK_FUNCTION(7, "DBG_MON_A[20]")
2162 + ),
2163 + MTK_PIN(
2164 + PINCTRL_PIN(70, "WB_CRTL4"),
2165 + NULL, "mt2701",
2166 + MTK_EINT_FUNCTION(0, 51),
2167 + MTK_FUNCTION(0, "GPIO70"),
2168 + MTK_FUNCTION(1, "WB_CRTL4"),
2169 + MTK_FUNCTION(5, "DFD_TDO"),
2170 + MTK_FUNCTION(7, "DBG_MON_A[21]")
2171 + ),
2172 + MTK_PIN(
2173 + PINCTRL_PIN(71, "WB_CRTL5"),
2174 + NULL, "mt2701",
2175 + MTK_EINT_FUNCTION(0, 52),
2176 + MTK_FUNCTION(0, "GPIO71"),
2177 + MTK_FUNCTION(1, "WB_CRTL5"),
2178 + MTK_FUNCTION(7, "DBG_MON_A[22]")
2179 + ),
2180 + MTK_PIN(
2181 + PINCTRL_PIN(72, "I2S0_DATA_IN"),
2182 + NULL, "mt2701",
2183 + MTK_EINT_FUNCTION(0, 53),
2184 + MTK_FUNCTION(0, "GPIO72"),
2185 + MTK_FUNCTION(1, "I2S0_DATA_IN"),
2186 + MTK_FUNCTION(3, "PCM_RX"),
2187 + MTK_FUNCTION(4, "PWM0"),
2188 + MTK_FUNCTION(5, "DISP_PWM"),
2189 + MTK_FUNCTION(6, "WCN_I2S_DI"),
2190 + MTK_FUNCTION(7, "DBG_MON_B[2]")
2191 + ),
2192 + MTK_PIN(
2193 + PINCTRL_PIN(73, "I2S0_LRCK"),
2194 + NULL, "mt2701",
2195 + MTK_EINT_FUNCTION(0, 54),
2196 + MTK_FUNCTION(0, "GPIO73"),
2197 + MTK_FUNCTION(1, "I2S0_LRCK"),
2198 + MTK_FUNCTION(3, "PCM_SYNC"),
2199 + MTK_FUNCTION(6, "WCN_I2S_LRCK"),
2200 + MTK_FUNCTION(7, "DBG_MON_B[5]")
2201 + ),
2202 + MTK_PIN(
2203 + PINCTRL_PIN(74, "I2S0_BCK"),
2204 + NULL, "mt2701",
2205 + MTK_EINT_FUNCTION(0, 55),
2206 + MTK_FUNCTION(0, "GPIO74"),
2207 + MTK_FUNCTION(1, "I2S0_BCK"),
2208 + MTK_FUNCTION(3, "PCM_CLK0"),
2209 + MTK_FUNCTION(6, "WCN_I2S_BCK"),
2210 + MTK_FUNCTION(7, "DBG_MON_B[4]")
2211 + ),
2212 + MTK_PIN(
2213 + PINCTRL_PIN(75, "SDA0"),
2214 + NULL, "mt2701",
2215 + MTK_EINT_FUNCTION(0, 56),
2216 + MTK_FUNCTION(0, "GPIO75"),
2217 + MTK_FUNCTION(1, "SDA0")
2218 + ),
2219 + MTK_PIN(
2220 + PINCTRL_PIN(76, "SCL0"),
2221 + NULL, "mt2701",
2222 + MTK_EINT_FUNCTION(0, 57),
2223 + MTK_FUNCTION(0, "GPIO76"),
2224 + MTK_FUNCTION(1, "SCL0")
2225 + ),
2226 + MTK_PIN(
2227 + PINCTRL_PIN(77, "SDA2"),
2228 + NULL, "mt2701",
2229 + MTK_EINT_FUNCTION(0, 58),
2230 + MTK_FUNCTION(0, "GPIO77"),
2231 + MTK_FUNCTION(1, "SDA2")
2232 + ),
2233 + MTK_PIN(
2234 + PINCTRL_PIN(78, "SCL2"),
2235 + NULL, "mt2701",
2236 + MTK_EINT_FUNCTION(0, 59),
2237 + MTK_FUNCTION(0, "GPIO78"),
2238 + MTK_FUNCTION(1, "SCL2")
2239 + ),
2240 + MTK_PIN(
2241 + PINCTRL_PIN(79, "URXD0"),
2242 + NULL, "mt2701",
2243 + MTK_EINT_FUNCTION(0, 60),
2244 + MTK_FUNCTION(0, "GPIO79"),
2245 + MTK_FUNCTION(1, "URXD0"),
2246 + MTK_FUNCTION(2, "UTXD0")
2247 + ),
2248 + MTK_PIN(
2249 + PINCTRL_PIN(80, "UTXD0"),
2250 + NULL, "mt2701",
2251 + MTK_EINT_FUNCTION(0, 61),
2252 + MTK_FUNCTION(0, "GPIO80"),
2253 + MTK_FUNCTION(1, "UTXD0"),
2254 + MTK_FUNCTION(2, "URXD0")
2255 + ),
2256 + MTK_PIN(
2257 + PINCTRL_PIN(81, "URXD1"),
2258 + NULL, "mt2701",
2259 + MTK_EINT_FUNCTION(0, 62),
2260 + MTK_FUNCTION(0, "GPIO81"),
2261 + MTK_FUNCTION(1, "URXD1"),
2262 + MTK_FUNCTION(2, "UTXD1")
2263 + ),
2264 + MTK_PIN(
2265 + PINCTRL_PIN(82, "UTXD1"),
2266 + NULL, "mt2701",
2267 + MTK_EINT_FUNCTION(0, 63),
2268 + MTK_FUNCTION(0, "GPIO82"),
2269 + MTK_FUNCTION(1, "UTXD1"),
2270 + MTK_FUNCTION(2, "URXD1")
2271 + ),
2272 + MTK_PIN(
2273 + PINCTRL_PIN(83, "LCM_RST"),
2274 + NULL, "mt2701",
2275 + MTK_EINT_FUNCTION(0, 64),
2276 + MTK_FUNCTION(0, "GPIO83"),
2277 + MTK_FUNCTION(1, "LCM_RST"),
2278 + MTK_FUNCTION(2, "VDAC_CK_XI"),
2279 + MTK_FUNCTION(7, "DBG_MON_B[1]")
2280 + ),
2281 + MTK_PIN(
2282 + PINCTRL_PIN(84, "DSI_TE"),
2283 + NULL, "mt2701",
2284 + MTK_EINT_FUNCTION(0, 65),
2285 + MTK_FUNCTION(0, "GPIO84"),
2286 + MTK_FUNCTION(1, "DSI_TE"),
2287 + MTK_FUNCTION(7, "DBG_MON_B[0]")
2288 + ),
2289 + MTK_PIN(
2290 + PINCTRL_PIN(85, "MSDC2_CMD"),
2291 + NULL, "mt2701",
2292 + MTK_EINT_FUNCTION(0, 66),
2293 + MTK_FUNCTION(0, "GPIO85"),
2294 + MTK_FUNCTION(1, "MSDC2_CMD"),
2295 + MTK_FUNCTION(2, "ANT_SEL0"),
2296 + MTK_FUNCTION(3, "SDA1"),
2297 + MTK_FUNCTION(6, "I2SOUT_BCK")
2298 + ),
2299 + MTK_PIN(
2300 + PINCTRL_PIN(86, "MSDC2_CLK"),
2301 + NULL, "mt2701",
2302 + MTK_EINT_FUNCTION(0, 67),
2303 + MTK_FUNCTION(0, "GPIO86"),
2304 + MTK_FUNCTION(1, "MSDC2_CLK"),
2305 + MTK_FUNCTION(2, "ANT_SEL1"),
2306 + MTK_FUNCTION(3, "SCL1"),
2307 + MTK_FUNCTION(6, "I2SOUT_LRCK")
2308 + ),
2309 + MTK_PIN(
2310 + PINCTRL_PIN(87, "MSDC2_DAT0"),
2311 + NULL, "mt2701",
2312 + MTK_EINT_FUNCTION(0, 68),
2313 + MTK_FUNCTION(0, "GPIO87"),
2314 + MTK_FUNCTION(1, "MSDC2_DAT0"),
2315 + MTK_FUNCTION(2, "ANT_SEL2"),
2316 + MTK_FUNCTION(5, "UTXD0"),
2317 + MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
2318 + ),
2319 + MTK_PIN(
2320 + PINCTRL_PIN(88, "MSDC2_DAT1"),
2321 + NULL, "mt2701",
2322 + MTK_EINT_FUNCTION(0, 71),
2323 + MTK_FUNCTION(0, "GPIO88"),
2324 + MTK_FUNCTION(1, "MSDC2_DAT1"),
2325 + MTK_FUNCTION(2, "ANT_SEL3"),
2326 + MTK_FUNCTION(3, "PWM0"),
2327 + MTK_FUNCTION(5, "URXD0"),
2328 + MTK_FUNCTION(6, "PWM1")
2329 + ),
2330 + MTK_PIN(
2331 + PINCTRL_PIN(89, "MSDC2_DAT2"),
2332 + NULL, "mt2701",
2333 + MTK_EINT_FUNCTION(0, 72),
2334 + MTK_FUNCTION(0, "GPIO89"),
2335 + MTK_FUNCTION(1, "MSDC2_DAT2"),
2336 + MTK_FUNCTION(2, "ANT_SEL4"),
2337 + MTK_FUNCTION(3, "SDA2"),
2338 + MTK_FUNCTION(5, "UTXD1"),
2339 + MTK_FUNCTION(6, "PWM2")
2340 + ),
2341 + MTK_PIN(
2342 + PINCTRL_PIN(90, "MSDC2_DAT3"),
2343 + NULL, "mt2701",
2344 + MTK_EINT_FUNCTION(0, 73),
2345 + MTK_FUNCTION(0, "GPIO90"),
2346 + MTK_FUNCTION(1, "MSDC2_DAT3"),
2347 + MTK_FUNCTION(2, "ANT_SEL5"),
2348 + MTK_FUNCTION(3, "SCL2"),
2349 + MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
2350 + MTK_FUNCTION(5, "URXD1"),
2351 + MTK_FUNCTION(6, "PWM3")
2352 + ),
2353 + MTK_PIN(
2354 + PINCTRL_PIN(91, "TDN3"),
2355 + NULL, "mt2701",
2356 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2357 + MTK_FUNCTION(0, "GPI91"),
2358 + MTK_FUNCTION(1, "TDN3")
2359 + ),
2360 + MTK_PIN(
2361 + PINCTRL_PIN(92, "TDP3"),
2362 + NULL, "mt2701",
2363 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2364 + MTK_FUNCTION(0, "GPI92"),
2365 + MTK_FUNCTION(1, "TDP3")
2366 + ),
2367 + MTK_PIN(
2368 + PINCTRL_PIN(93, "TDN2"),
2369 + NULL, "mt2701",
2370 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2371 + MTK_FUNCTION(0, "GPI93"),
2372 + MTK_FUNCTION(1, "TDN2")
2373 + ),
2374 + MTK_PIN(
2375 + PINCTRL_PIN(94, "TDP2"),
2376 + NULL, "mt2701",
2377 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2378 + MTK_FUNCTION(0, "GPI94"),
2379 + MTK_FUNCTION(1, "TDP2")
2380 + ),
2381 + MTK_PIN(
2382 + PINCTRL_PIN(95, "TCN"),
2383 + NULL, "mt2701",
2384 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2385 + MTK_FUNCTION(0, "GPI95"),
2386 + MTK_FUNCTION(1, "TCN")
2387 + ),
2388 + MTK_PIN(
2389 + PINCTRL_PIN(96, "TCP"),
2390 + NULL, "mt2701",
2391 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2392 + MTK_FUNCTION(0, "GPI96"),
2393 + MTK_FUNCTION(1, "TCP")
2394 + ),
2395 + MTK_PIN(
2396 + PINCTRL_PIN(97, "TDN1"),
2397 + NULL, "mt2701",
2398 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2399 + MTK_FUNCTION(0, "GPI97"),
2400 + MTK_FUNCTION(1, "TDN1")
2401 + ),
2402 + MTK_PIN(
2403 + PINCTRL_PIN(98, "TDP1"),
2404 + NULL, "mt2701",
2405 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2406 + MTK_FUNCTION(0, "GPI98"),
2407 + MTK_FUNCTION(1, "TDP1")
2408 + ),
2409 + MTK_PIN(
2410 + PINCTRL_PIN(99, "TDN0"),
2411 + NULL, "mt2701",
2412 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2413 + MTK_FUNCTION(0, "GPI99"),
2414 + MTK_FUNCTION(1, "TDN0")
2415 + ),
2416 + MTK_PIN(
2417 + PINCTRL_PIN(100, "TDP0"),
2418 + NULL, "mt2701",
2419 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2420 + MTK_FUNCTION(0, "GPI100"),
2421 + MTK_FUNCTION(1, "TDP0")
2422 + ),
2423 + MTK_PIN(
2424 + PINCTRL_PIN(101, "SPI2_CSN"),
2425 + NULL, "mt2701",
2426 + MTK_EINT_FUNCTION(0, 74),
2427 + MTK_FUNCTION(0, "GPIO101"),
2428 + MTK_FUNCTION(1, "SPI2_CS"),
2429 + MTK_FUNCTION(3, "SCL3"),
2430 + MTK_FUNCTION(4, "KROW0")
2431 + ),
2432 + MTK_PIN(
2433 + PINCTRL_PIN(102, "SPI2_MI"),
2434 + NULL, "mt2701",
2435 + MTK_EINT_FUNCTION(0, 75),
2436 + MTK_FUNCTION(0, "GPIO102"),
2437 + MTK_FUNCTION(1, "SPI2_MI"),
2438 + MTK_FUNCTION(2, "SPI2_MO"),
2439 + MTK_FUNCTION(3, "SDA3"),
2440 + MTK_FUNCTION(4, "KROW1")
2441 + ),
2442 + MTK_PIN(
2443 + PINCTRL_PIN(103, "SPI2_MO"),
2444 + NULL, "mt2701",
2445 + MTK_EINT_FUNCTION(0, 76),
2446 + MTK_FUNCTION(0, "GPIO103"),
2447 + MTK_FUNCTION(1, "SPI2_MO"),
2448 + MTK_FUNCTION(2, "SPI2_MI"),
2449 + MTK_FUNCTION(3, "SCL3"),
2450 + MTK_FUNCTION(4, "KROW2")
2451 + ),
2452 + MTK_PIN(
2453 + PINCTRL_PIN(104, "SPI2_CLK"),
2454 + NULL, "mt2701",
2455 + MTK_EINT_FUNCTION(0, 77),
2456 + MTK_FUNCTION(0, "GPIO104"),
2457 + MTK_FUNCTION(1, "SPI2_CK"),
2458 + MTK_FUNCTION(3, "SDA3"),
2459 + MTK_FUNCTION(4, "KROW3")
2460 + ),
2461 + MTK_PIN(
2462 + PINCTRL_PIN(105, "MSDC1_CMD"),
2463 + NULL, "mt2701",
2464 + MTK_EINT_FUNCTION(0, 78),
2465 + MTK_FUNCTION(0, "GPIO105"),
2466 + MTK_FUNCTION(1, "MSDC1_CMD"),
2467 + MTK_FUNCTION(2, "ANT_SEL0"),
2468 + MTK_FUNCTION(3, "SDA1"),
2469 + MTK_FUNCTION(6, "I2SOUT_BCK"),
2470 + MTK_FUNCTION(7, "DBG_MON_B[27]")
2471 + ),
2472 + MTK_PIN(
2473 + PINCTRL_PIN(106, "MSDC1_CLK"),
2474 + NULL, "mt2701",
2475 + MTK_EINT_FUNCTION(0, 79),
2476 + MTK_FUNCTION(0, "GPIO106"),
2477 + MTK_FUNCTION(1, "MSDC1_CLK"),
2478 + MTK_FUNCTION(2, "ANT_SEL1"),
2479 + MTK_FUNCTION(3, "SCL1"),
2480 + MTK_FUNCTION(6, "I2SOUT_LRCK"),
2481 + MTK_FUNCTION(7, "DBG_MON_B[28]")
2482 + ),
2483 + MTK_PIN(
2484 + PINCTRL_PIN(107, "MSDC1_DAT0"),
2485 + NULL, "mt2701",
2486 + MTK_EINT_FUNCTION(0, 80),
2487 + MTK_FUNCTION(0, "GPIO107"),
2488 + MTK_FUNCTION(1, "MSDC1_DAT0"),
2489 + MTK_FUNCTION(2, "ANT_SEL2"),
2490 + MTK_FUNCTION(5, "UTXD0"),
2491 + MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
2492 + MTK_FUNCTION(7, "DBG_MON_B[26]")
2493 + ),
2494 + MTK_PIN(
2495 + PINCTRL_PIN(108, "MSDC1_DAT1"),
2496 + NULL, "mt2701",
2497 + MTK_EINT_FUNCTION(0, 81),
2498 + MTK_FUNCTION(0, "GPIO108"),
2499 + MTK_FUNCTION(1, "MSDC1_DAT1"),
2500 + MTK_FUNCTION(2, "ANT_SEL3"),
2501 + MTK_FUNCTION(3, "PWM0"),
2502 + MTK_FUNCTION(5, "URXD0"),
2503 + MTK_FUNCTION(6, "PWM1"),
2504 + MTK_FUNCTION(7, "DBG_MON_B[25]")
2505 + ),
2506 + MTK_PIN(
2507 + PINCTRL_PIN(109, "MSDC1_DAT2"),
2508 + NULL, "mt2701",
2509 + MTK_EINT_FUNCTION(0, 82),
2510 + MTK_FUNCTION(0, "GPIO109"),
2511 + MTK_FUNCTION(1, "MSDC1_DAT2"),
2512 + MTK_FUNCTION(2, "ANT_SEL4"),
2513 + MTK_FUNCTION(3, "SDA2"),
2514 + MTK_FUNCTION(5, "UTXD1"),
2515 + MTK_FUNCTION(6, "PWM2"),
2516 + MTK_FUNCTION(7, "DBG_MON_B[24]")
2517 + ),
2518 + MTK_PIN(
2519 + PINCTRL_PIN(110, "MSDC1_DAT3"),
2520 + NULL, "mt2701",
2521 + MTK_EINT_FUNCTION(0, 83),
2522 + MTK_FUNCTION(0, "GPIO110"),
2523 + MTK_FUNCTION(1, "MSDC1_DAT3"),
2524 + MTK_FUNCTION(2, "ANT_SEL5"),
2525 + MTK_FUNCTION(3, "SCL2"),
2526 + MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
2527 + MTK_FUNCTION(5, "URXD1"),
2528 + MTK_FUNCTION(6, "PWM3"),
2529 + MTK_FUNCTION(7, "DBG_MON_B[23]")
2530 + ),
2531 + MTK_PIN(
2532 + PINCTRL_PIN(111, "MSDC0_DAT7"),
2533 + NULL, "mt2701",
2534 + MTK_EINT_FUNCTION(0, 84),
2535 + MTK_FUNCTION(0, "GPIO111"),
2536 + MTK_FUNCTION(1, "MSDC0_DAT7"),
2537 + MTK_FUNCTION(4, "NLD7")
2538 + ),
2539 + MTK_PIN(
2540 + PINCTRL_PIN(112, "MSDC0_DAT6"),
2541 + NULL, "mt2701",
2542 + MTK_EINT_FUNCTION(0, 85),
2543 + MTK_FUNCTION(0, "GPIO112"),
2544 + MTK_FUNCTION(1, "MSDC0_DAT6"),
2545 + MTK_FUNCTION(4, "NLD6")
2546 + ),
2547 + MTK_PIN(
2548 + PINCTRL_PIN(113, "MSDC0_DAT5"),
2549 + NULL, "mt2701",
2550 + MTK_EINT_FUNCTION(0, 86),
2551 + MTK_FUNCTION(0, "GPIO113"),
2552 + MTK_FUNCTION(1, "MSDC0_DAT5"),
2553 + MTK_FUNCTION(4, "NLD5")
2554 + ),
2555 + MTK_PIN(
2556 + PINCTRL_PIN(114, "MSDC0_DAT4"),
2557 + NULL, "mt2701",
2558 + MTK_EINT_FUNCTION(0, 87),
2559 + MTK_FUNCTION(0, "GPIO114"),
2560 + MTK_FUNCTION(1, "MSDC0_DAT4"),
2561 + MTK_FUNCTION(4, "NLD4")
2562 + ),
2563 + MTK_PIN(
2564 + PINCTRL_PIN(115, "MSDC0_RSTB"),
2565 + NULL, "mt2701",
2566 + MTK_EINT_FUNCTION(0, 88),
2567 + MTK_FUNCTION(0, "GPIO115"),
2568 + MTK_FUNCTION(1, "MSDC0_RSTB"),
2569 + MTK_FUNCTION(4, "NLD8")
2570 + ),
2571 + MTK_PIN(
2572 + PINCTRL_PIN(116, "MSDC0_CMD"),
2573 + NULL, "mt2701",
2574 + MTK_EINT_FUNCTION(0, 89),
2575 + MTK_FUNCTION(0, "GPIO116"),
2576 + MTK_FUNCTION(1, "MSDC0_CMD"),
2577 + MTK_FUNCTION(4, "NALE")
2578 + ),
2579 + MTK_PIN(
2580 + PINCTRL_PIN(117, "MSDC0_CLK"),
2581 + NULL, "mt2701",
2582 + MTK_EINT_FUNCTION(0, 90),
2583 + MTK_FUNCTION(0, "GPIO117"),
2584 + MTK_FUNCTION(1, "MSDC0_CLK"),
2585 + MTK_FUNCTION(4, "NWEB")
2586 + ),
2587 + MTK_PIN(
2588 + PINCTRL_PIN(118, "MSDC0_DAT3"),
2589 + NULL, "mt2701",
2590 + MTK_EINT_FUNCTION(0, 91),
2591 + MTK_FUNCTION(0, "GPIO118"),
2592 + MTK_FUNCTION(1, "MSDC0_DAT3"),
2593 + MTK_FUNCTION(4, "NLD3")
2594 + ),
2595 + MTK_PIN(
2596 + PINCTRL_PIN(119, "MSDC0_DAT2"),
2597 + NULL, "mt2701",
2598 + MTK_EINT_FUNCTION(0, 92),
2599 + MTK_FUNCTION(0, "GPIO119"),
2600 + MTK_FUNCTION(1, "MSDC0_DAT2"),
2601 + MTK_FUNCTION(4, "NLD2")
2602 + ),
2603 + MTK_PIN(
2604 + PINCTRL_PIN(120, "MSDC0_DAT1"),
2605 + NULL, "mt2701",
2606 + MTK_EINT_FUNCTION(0, 93),
2607 + MTK_FUNCTION(0, "GPIO120"),
2608 + MTK_FUNCTION(1, "MSDC0_DAT1"),
2609 + MTK_FUNCTION(4, "NLD1")
2610 + ),
2611 + MTK_PIN(
2612 + PINCTRL_PIN(121, "MSDC0_DAT0"),
2613 + NULL, "mt2701",
2614 + MTK_EINT_FUNCTION(0, 94),
2615 + MTK_FUNCTION(0, "GPIO121"),
2616 + MTK_FUNCTION(1, "MSDC0_DAT0"),
2617 + MTK_FUNCTION(4, "NLD0"),
2618 + MTK_FUNCTION(5, "WATCHDOG")
2619 + ),
2620 + MTK_PIN(
2621 + PINCTRL_PIN(122, "CEC"),
2622 + NULL, "mt2701",
2623 + MTK_EINT_FUNCTION(0, 95),
2624 + MTK_FUNCTION(0, "GPIO122"),
2625 + MTK_FUNCTION(1, "CEC"),
2626 + MTK_FUNCTION(4, "SDA2"),
2627 + MTK_FUNCTION(5, "URXD0")
2628 + ),
2629 + MTK_PIN(
2630 + PINCTRL_PIN(123, "HTPLG"),
2631 + NULL, "mt2701",
2632 + MTK_EINT_FUNCTION(0, 96),
2633 + MTK_FUNCTION(0, "GPIO123"),
2634 + MTK_FUNCTION(1, "HTPLG"),
2635 + MTK_FUNCTION(4, "SCL2"),
2636 + MTK_FUNCTION(5, "UTXD0")
2637 + ),
2638 + MTK_PIN(
2639 + PINCTRL_PIN(124, "HDMISCK"),
2640 + NULL, "mt2701",
2641 + MTK_EINT_FUNCTION(0, 97),
2642 + MTK_FUNCTION(0, "GPIO124"),
2643 + MTK_FUNCTION(1, "HDMISCK"),
2644 + MTK_FUNCTION(4, "SDA1"),
2645 + MTK_FUNCTION(5, "PWM3")
2646 + ),
2647 + MTK_PIN(
2648 + PINCTRL_PIN(125, "HDMISD"),
2649 + NULL, "mt2701",
2650 + MTK_EINT_FUNCTION(0, 98),
2651 + MTK_FUNCTION(0, "GPIO125"),
2652 + MTK_FUNCTION(1, "HDMISD"),
2653 + MTK_FUNCTION(4, "SCL1"),
2654 + MTK_FUNCTION(5, "PWM4")
2655 + ),
2656 + MTK_PIN(
2657 + PINCTRL_PIN(126, "I2S0_MCLK"),
2658 + NULL, "mt2701",
2659 + MTK_EINT_FUNCTION(0, 99),
2660 + MTK_FUNCTION(0, "GPIO126"),
2661 + MTK_FUNCTION(1, "I2S0_MCLK"),
2662 + MTK_FUNCTION(6, "WCN_I2S_MCLK"),
2663 + MTK_FUNCTION(7, "DBG_MON_B[6]")
2664 + ),
2665 + MTK_PIN(
2666 + PINCTRL_PIN(127, "RAMBUF_IDATA0"),
2667 + NULL, "mt2701",
2668 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2669 + MTK_FUNCTION(0, "GPIO127"),
2670 + MTK_FUNCTION(1, "RAMBUF_IDATA0")
2671 + ),
2672 + MTK_PIN(
2673 + PINCTRL_PIN(128, "RAMBUF_IDATA1"),
2674 + NULL, "mt2701",
2675 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2676 + MTK_FUNCTION(0, "GPIO128"),
2677 + MTK_FUNCTION(1, "RAMBUF_IDATA1")
2678 + ),
2679 + MTK_PIN(
2680 + PINCTRL_PIN(129, "RAMBUF_IDATA2"),
2681 + NULL, "mt2701",
2682 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2683 + MTK_FUNCTION(0, "GPIO129"),
2684 + MTK_FUNCTION(1, "RAMBUF_IDATA2")
2685 + ),
2686 + MTK_PIN(
2687 + PINCTRL_PIN(130, "RAMBUF_IDATA3"),
2688 + NULL, "mt2701",
2689 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2690 + MTK_FUNCTION(0, "GPIO130"),
2691 + MTK_FUNCTION(1, "RAMBUF_IDATA3")
2692 + ),
2693 + MTK_PIN(
2694 + PINCTRL_PIN(131, "RAMBUF_IDATA4"),
2695 + NULL, "mt2701",
2696 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2697 + MTK_FUNCTION(0, "GPIO131"),
2698 + MTK_FUNCTION(1, "RAMBUF_IDATA4")
2699 + ),
2700 + MTK_PIN(
2701 + PINCTRL_PIN(132, "RAMBUF_IDATA5"),
2702 + NULL, "mt2701",
2703 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2704 + MTK_FUNCTION(0, "GPIO132"),
2705 + MTK_FUNCTION(1, "RAMBUF_IDATA5")
2706 + ),
2707 + MTK_PIN(
2708 + PINCTRL_PIN(133, "RAMBUF_IDATA6"),
2709 + NULL, "mt2701",
2710 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2711 + MTK_FUNCTION(0, "GPIO133"),
2712 + MTK_FUNCTION(1, "RAMBUF_IDATA6")
2713 + ),
2714 + MTK_PIN(
2715 + PINCTRL_PIN(134, "RAMBUF_IDATA7"),
2716 + NULL, "mt2701",
2717 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2718 + MTK_FUNCTION(0, "GPIO134"),
2719 + MTK_FUNCTION(1, "RAMBUF_IDATA7")
2720 + ),
2721 + MTK_PIN(
2722 + PINCTRL_PIN(135, "RAMBUF_IDATA8"),
2723 + NULL, "mt2701",
2724 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2725 + MTK_FUNCTION(0, "GPIO135"),
2726 + MTK_FUNCTION(1, "RAMBUF_IDATA8")
2727 + ),
2728 + MTK_PIN(
2729 + PINCTRL_PIN(136, "RAMBUF_IDATA9"),
2730 + NULL, "mt2701",
2731 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2732 + MTK_FUNCTION(0, "GPIO136"),
2733 + MTK_FUNCTION(1, "RAMBUF_IDATA9")
2734 + ),
2735 + MTK_PIN(
2736 + PINCTRL_PIN(137, "RAMBUF_IDATA10"),
2737 + NULL, "mt2701",
2738 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2739 + MTK_FUNCTION(0, "GPIO137"),
2740 + MTK_FUNCTION(1, "RAMBUF_IDATA10")
2741 + ),
2742 + MTK_PIN(
2743 + PINCTRL_PIN(138, "RAMBUF_IDATA11"),
2744 + NULL, "mt2701",
2745 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2746 + MTK_FUNCTION(0, "GPIO138"),
2747 + MTK_FUNCTION(1, "RAMBUF_IDATA11")
2748 + ),
2749 + MTK_PIN(
2750 + PINCTRL_PIN(139, "RAMBUF_IDATA12"),
2751 + NULL, "mt2701",
2752 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2753 + MTK_FUNCTION(0, "GPIO139"),
2754 + MTK_FUNCTION(1, "RAMBUF_IDATA12")
2755 + ),
2756 + MTK_PIN(
2757 + PINCTRL_PIN(140, "RAMBUF_IDATA13"),
2758 + NULL, "mt2701",
2759 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2760 + MTK_FUNCTION(0, "GPIO140"),
2761 + MTK_FUNCTION(1, "RAMBUF_IDATA13")
2762 + ),
2763 + MTK_PIN(
2764 + PINCTRL_PIN(141, "RAMBUF_IDATA14"),
2765 + NULL, "mt2701",
2766 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2767 + MTK_FUNCTION(0, "GPIO141"),
2768 + MTK_FUNCTION(1, "RAMBUF_IDATA14")
2769 + ),
2770 + MTK_PIN(
2771 + PINCTRL_PIN(142, "RAMBUF_IDATA15"),
2772 + NULL, "mt2701",
2773 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2774 + MTK_FUNCTION(0, "GPIO142"),
2775 + MTK_FUNCTION(1, "RAMBUF_IDATA15")
2776 + ),
2777 + MTK_PIN(
2778 + PINCTRL_PIN(143, "RAMBUF_ODATA0"),
2779 + NULL, "mt2701",
2780 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2781 + MTK_FUNCTION(0, "GPIO143"),
2782 + MTK_FUNCTION(1, "RAMBUF_ODATA0")
2783 + ),
2784 + MTK_PIN(
2785 + PINCTRL_PIN(144, "RAMBUF_ODATA1"),
2786 + NULL, "mt2701",
2787 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2788 + MTK_FUNCTION(0, "GPIO144"),
2789 + MTK_FUNCTION(1, "RAMBUF_ODATA1")
2790 + ),
2791 + MTK_PIN(
2792 + PINCTRL_PIN(145, "RAMBUF_ODATA2"),
2793 + NULL, "mt2701",
2794 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2795 + MTK_FUNCTION(0, "GPIO145"),
2796 + MTK_FUNCTION(1, "RAMBUF_ODATA2")
2797 + ),
2798 + MTK_PIN(
2799 + PINCTRL_PIN(146, "RAMBUF_ODATA3"),
2800 + NULL, "mt2701",
2801 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2802 + MTK_FUNCTION(0, "GPIO146"),
2803 + MTK_FUNCTION(1, "RAMBUF_ODATA3")
2804 + ),
2805 + MTK_PIN(
2806 + PINCTRL_PIN(147, "RAMBUF_ODATA4"),
2807 + NULL, "mt2701",
2808 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2809 + MTK_FUNCTION(0, "GPIO147"),
2810 + MTK_FUNCTION(1, "RAMBUF_ODATA4")
2811 + ),
2812 + MTK_PIN(
2813 + PINCTRL_PIN(148, "RAMBUF_ODATA5"),
2814 + NULL, "mt2701",
2815 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2816 + MTK_FUNCTION(0, "GPIO148"),
2817 + MTK_FUNCTION(1, "RAMBUF_ODATA5")
2818 + ),
2819 + MTK_PIN(
2820 + PINCTRL_PIN(149, "RAMBUF_ODATA6"),
2821 + NULL, "mt2701",
2822 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2823 + MTK_FUNCTION(0, "GPIO149"),
2824 + MTK_FUNCTION(1, "RAMBUF_ODATA6")
2825 + ),
2826 + MTK_PIN(
2827 + PINCTRL_PIN(150, "RAMBUF_ODATA7"),
2828 + NULL, "mt2701",
2829 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2830 + MTK_FUNCTION(0, "GPIO150"),
2831 + MTK_FUNCTION(1, "RAMBUF_ODATA7")
2832 + ),
2833 + MTK_PIN(
2834 + PINCTRL_PIN(151, "RAMBUF_ODATA8"),
2835 + NULL, "mt2701",
2836 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2837 + MTK_FUNCTION(0, "GPIO151"),
2838 + MTK_FUNCTION(1, "RAMBUF_ODATA8")
2839 + ),
2840 + MTK_PIN(
2841 + PINCTRL_PIN(152, "RAMBUF_ODATA9"),
2842 + NULL, "mt2701",
2843 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2844 + MTK_FUNCTION(0, "GPIO152"),
2845 + MTK_FUNCTION(1, "RAMBUF_ODATA9")
2846 + ),
2847 + MTK_PIN(
2848 + PINCTRL_PIN(153, "RAMBUF_ODATA10"),
2849 + NULL, "mt2701",
2850 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2851 + MTK_FUNCTION(0, "GPIO153"),
2852 + MTK_FUNCTION(1, "RAMBUF_ODATA10")
2853 + ),
2854 + MTK_PIN(
2855 + PINCTRL_PIN(154, "RAMBUF_ODATA11"),
2856 + NULL, "mt2701",
2857 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2858 + MTK_FUNCTION(0, "GPIO154"),
2859 + MTK_FUNCTION(1, "RAMBUF_ODATA11")
2860 + ),
2861 + MTK_PIN(
2862 + PINCTRL_PIN(155, "RAMBUF_ODATA12"),
2863 + NULL, "mt2701",
2864 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2865 + MTK_FUNCTION(0, "GPIO155"),
2866 + MTK_FUNCTION(1, "RAMBUF_ODATA12")
2867 + ),
2868 + MTK_PIN(
2869 + PINCTRL_PIN(156, "RAMBUF_ODATA13"),
2870 + NULL, "mt2701",
2871 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2872 + MTK_FUNCTION(0, "GPIO156"),
2873 + MTK_FUNCTION(1, "RAMBUF_ODATA13")
2874 + ),
2875 + MTK_PIN(
2876 + PINCTRL_PIN(157, "RAMBUF_ODATA14"),
2877 + NULL, "mt2701",
2878 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2879 + MTK_FUNCTION(0, "GPIO157"),
2880 + MTK_FUNCTION(1, "RAMBUF_ODATA14")
2881 + ),
2882 + MTK_PIN(
2883 + PINCTRL_PIN(158, "RAMBUF_ODATA15"),
2884 + NULL, "mt2701",
2885 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2886 + MTK_FUNCTION(0, "GPIO158"),
2887 + MTK_FUNCTION(1, "RAMBUF_ODATA15")
2888 + ),
2889 + MTK_PIN(
2890 + PINCTRL_PIN(159, "RAMBUF_BE0"),
2891 + NULL, "mt2701",
2892 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2893 + MTK_FUNCTION(0, "GPIO159"),
2894 + MTK_FUNCTION(1, "RAMBUF_BE0")
2895 + ),
2896 + MTK_PIN(
2897 + PINCTRL_PIN(160, "RAMBUF_BE1"),
2898 + NULL, "mt2701",
2899 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2900 + MTK_FUNCTION(0, "GPIO160"),
2901 + MTK_FUNCTION(1, "RAMBUF_BE1")
2902 + ),
2903 + MTK_PIN(
2904 + PINCTRL_PIN(161, "AP2PT_INT"),
2905 + NULL, "mt2701",
2906 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2907 + MTK_FUNCTION(0, "GPIO161"),
2908 + MTK_FUNCTION(1, "AP2PT_INT")
2909 + ),
2910 + MTK_PIN(
2911 + PINCTRL_PIN(162, "AP2PT_INT_CLR"),
2912 + NULL, "mt2701",
2913 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2914 + MTK_FUNCTION(0, "GPIO162"),
2915 + MTK_FUNCTION(1, "AP2PT_INT_CLR")
2916 + ),
2917 + MTK_PIN(
2918 + PINCTRL_PIN(163, "PT2AP_INT"),
2919 + NULL, "mt2701",
2920 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2921 + MTK_FUNCTION(0, "GPIO163"),
2922 + MTK_FUNCTION(1, "PT2AP_INT")
2923 + ),
2924 + MTK_PIN(
2925 + PINCTRL_PIN(164, "PT2AP_INT_CLR"),
2926 + NULL, "mt2701",
2927 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2928 + MTK_FUNCTION(0, "GPIO164"),
2929 + MTK_FUNCTION(1, "PT2AP_INT_CLR")
2930 + ),
2931 + MTK_PIN(
2932 + PINCTRL_PIN(165, "AP2UP_INT"),
2933 + NULL, "mt2701",
2934 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2935 + MTK_FUNCTION(0, "GPIO165"),
2936 + MTK_FUNCTION(1, "AP2UP_INT")
2937 + ),
2938 + MTK_PIN(
2939 + PINCTRL_PIN(166, "AP2UP_INT_CLR"),
2940 + NULL, "mt2701",
2941 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2942 + MTK_FUNCTION(0, "GPIO166"),
2943 + MTK_FUNCTION(1, "AP2UP_INT_CLR")
2944 + ),
2945 + MTK_PIN(
2946 + PINCTRL_PIN(167, "UP2AP_INT"),
2947 + NULL, "mt2701",
2948 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2949 + MTK_FUNCTION(0, "GPIO167"),
2950 + MTK_FUNCTION(1, "UP2AP_INT")
2951 + ),
2952 + MTK_PIN(
2953 + PINCTRL_PIN(168, "UP2AP_INT_CLR"),
2954 + NULL, "mt2701",
2955 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2956 + MTK_FUNCTION(0, "GPIO168"),
2957 + MTK_FUNCTION(1, "UP2AP_INT_CLR")
2958 + ),
2959 + MTK_PIN(
2960 + PINCTRL_PIN(169, "RAMBUF_ADDR0"),
2961 + NULL, "mt2701",
2962 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2963 + MTK_FUNCTION(0, "GPIO169"),
2964 + MTK_FUNCTION(1, "RAMBUF_ADDR0")
2965 + ),
2966 + MTK_PIN(
2967 + PINCTRL_PIN(170, "RAMBUF_ADDR1"),
2968 + NULL, "mt2701",
2969 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2970 + MTK_FUNCTION(0, "GPIO170"),
2971 + MTK_FUNCTION(1, "RAMBUF_ADDR1")
2972 + ),
2973 + MTK_PIN(
2974 + PINCTRL_PIN(171, "RAMBUF_ADDR2"),
2975 + NULL, "mt2701",
2976 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2977 + MTK_FUNCTION(0, "GPIO171"),
2978 + MTK_FUNCTION(1, "RAMBUF_ADDR2")
2979 + ),
2980 + MTK_PIN(
2981 + PINCTRL_PIN(172, "RAMBUF_ADDR3"),
2982 + NULL, "mt2701",
2983 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2984 + MTK_FUNCTION(0, "GPIO172"),
2985 + MTK_FUNCTION(1, "RAMBUF_ADDR3")
2986 + ),
2987 + MTK_PIN(
2988 + PINCTRL_PIN(173, "RAMBUF_ADDR4"),
2989 + NULL, "mt2701",
2990 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2991 + MTK_FUNCTION(0, "GPIO173"),
2992 + MTK_FUNCTION(1, "RAMBUF_ADDR4")
2993 + ),
2994 + MTK_PIN(
2995 + PINCTRL_PIN(174, "RAMBUF_ADDR5"),
2996 + NULL, "mt2701",
2997 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
2998 + MTK_FUNCTION(0, "GPIO174"),
2999 + MTK_FUNCTION(1, "RAMBUF_ADDR5")
3000 + ),
3001 + MTK_PIN(
3002 + PINCTRL_PIN(175, "RAMBUF_ADDR6"),
3003 + NULL, "mt2701",
3004 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3005 + MTK_FUNCTION(0, "GPIO175"),
3006 + MTK_FUNCTION(1, "RAMBUF_ADDR6")
3007 + ),
3008 + MTK_PIN(
3009 + PINCTRL_PIN(176, "RAMBUF_ADDR7"),
3010 + NULL, "mt2701",
3011 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3012 + MTK_FUNCTION(0, "GPIO176"),
3013 + MTK_FUNCTION(1, "RAMBUF_ADDR7")
3014 + ),
3015 + MTK_PIN(
3016 + PINCTRL_PIN(177, "RAMBUF_ADDR8"),
3017 + NULL, "mt2701",
3018 + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
3019 + MTK_FUNCTION(0, "GPIO177"),