5f7a495db62a6c5907f137f38f7993b48de7b734
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0017-clk-add-hifsys-reset.patch
1 From 294cf90337d70ad74edf147180bbeef837298bd0 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 6 Jan 2016 20:06:49 +0100
4 Subject: [PATCH 17/81] clk: add hifsys reset
5
6 Hi,
7
8 small patch to add hifsys reset bits. Maybe you could add it to the next
9 version of your patch series. i have teste scpsys and clk on mt7623 today
10 and it works well.
11
12 thanks,
13 John
14
15 Signed-off-by: John Crispin <blogic@openwrt.org>
16 ---
17 drivers/clk/mediatek/clk-mt2701.c | 2 ++
18 include/dt-bindings/reset-controller/mt2701-resets.h | 9 +++++++++
19 2 files changed, 11 insertions(+)
20
21 --- a/drivers/clk/mediatek/clk-mt2701.c
22 +++ b/drivers/clk/mediatek/clk-mt2701.c
23 @@ -1000,6 +1000,8 @@ static void __init mtk_hifsys_init(struc
24 if (r)
25 pr_err("%s(): could not register clock provider: %d\n",
26 __func__, r);
27 +
28 + mtk_register_reset_controller(node, 1, 0x34);
29 }
30 CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init);
31
32 --- a/include/dt-bindings/reset-controller/mt2701-resets.h
33 +++ b/include/dt-bindings/reset-controller/mt2701-resets.h
34 @@ -71,4 +71,13 @@
35 #define MT2701_TOPRGU_CONN_MCU_RST 12
36 #define MT2701_TOPRGU_BDP_DISP_RST 13
37
38 +/* HIFSYS resets */
39 +#define MT2701_HIFSYS_UHOST0_RST 3
40 +#define MT2701_HIFSYS_UHOST1_RST 4
41 +#define MT2701_HIFSYS_UPHY0_RST 21
42 +#define MT2701_HIFSYS_UPHY1_RST 22
43 +#define MT2701_HIFSYS_PCIE0_RST 24
44 +#define MT2701_HIFSYS_PCIE1_RST 25
45 +#define MT2701_HIFSYS_PCIE2_RST 26
46 +
47 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */