target/linux/mediatek/patches-4.4/0019-xhci-mediatek-support-MTK-xHCI-host-controller.patch

   1 From 651d8fff94718c7e48b8a40d7774878eb8ed62ee Mon Sep 17 00:00:00 2001
   2 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
   3 Date: Tue, 17 Nov 2015 17:18:40 +0800
   4 Subject: [PATCH 19/91] xhci: mediatek: support MTK xHCI host controller
   5
   6 There some vendor quirks for MTK xhci host controller:
   7 1. It defines some extra SW scheduling parameters for HW
   8   to minimize the scheduling effort for synchronous and
   9   interrupt endpoints. The parameters are put into reseved
  10   DWs of slot context and endpoint context.
  11 2. Its IMODI unit for Interrupter Moderation register is
  12   8 times as much as that defined in xHCI spec.
  13 3. Its TDS in  Normal TRB defines a number of packets that
  14   remains to be transferred for a TD after processing all
  15   Max packets in all previous TRBs.
  16
  17 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
  18 Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
  19 Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
  20 ---
  21  drivers/usb/host/Kconfig        |    9 +
  22  drivers/usb/host/Makefile       |    4 +
  23  drivers/usb/host/xhci-mtk-sch.c |  415 +++++++++++++++++++++
  24  drivers/usb/host/xhci-mtk.c     |  763 +++++++++++++++++++++++++++++++++++++++
  25  drivers/usb/host/xhci-mtk.h     |  162 +++++++++
  26  drivers/usb/host/xhci-ring.c    |   16 +-
  27  drivers/usb/host/xhci.c         |   19 +-
  28  drivers/usb/host/xhci.h         |    1 +
  29  8 files changed, 1383 insertions(+), 6 deletions(-)
  30  create mode 100644 drivers/usb/host/xhci-mtk-sch.c
  31  create mode 100644 drivers/usb/host/xhci-mtk.c
  32  create mode 100644 drivers/usb/host/xhci-mtk.h
  33
  34 diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
  35 index 3bb0887..daa563f 100644
  36 --- a/drivers/usb/host/Kconfig
  37 +++ b/drivers/usb/host/Kconfig
  38 @@ -41,6 +41,15 @@ config USB_XHCI_PLATFORM
  39
  40           If unsure, say N.
  41
  42 +config USB_XHCI_MTK
  43 +       tristate "xHCI support for Mediatek MT65xx"
  44 +       select MFD_SYSCON
  45 +       depends on ARCH_MEDIATEK || COMPILE_TEST
  46 +       ---help---
  47 +         Say 'Y' to enable the support for the xHCI host controller
  48 +         found in Mediatek MT65xx SoCs.
  49 +         If unsure, say N.
  50 +
  51  config USB_XHCI_MVEBU
  52         tristate "xHCI support for Marvell Armada 375/38x"
  53         select USB_XHCI_PLATFORM
  54 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
  55 index e7558ab..65a06b4 100644
  56 --- a/drivers/usb/host/Makefile
  57 +++ b/drivers/usb/host/Makefile
  58 @@ -13,6 +13,9 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
  59  xhci-hcd-y := xhci.o xhci-mem.o
  60  xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
  61  xhci-hcd-y += xhci-trace.o
  62 +ifneq ($(CONFIG_USB_XHCI_MTK), )
  63 +       xhci-hcd-y += xhci-mtk-sch.o
  64 +endif
  65
  66  xhci-plat-hcd-y := xhci-plat.o
  67  ifneq ($(CONFIG_USB_XHCI_MVEBU), )
  68 @@ -64,6 +67,7 @@ obj-$(CONFIG_USB_FHCI_HCD)    += fhci.o
  69  obj-$(CONFIG_USB_XHCI_HCD)     += xhci-hcd.o
  70  obj-$(CONFIG_USB_XHCI_PCI)     += xhci-pci.o
  71  obj-$(CONFIG_USB_XHCI_PLATFORM) += xhci-plat-hcd.o
  72 +obj-$(CONFIG_USB_XHCI_MTK)     += xhci-mtk.o
  73  obj-$(CONFIG_USB_SL811_HCD)    += sl811-hcd.o
  74  obj-$(CONFIG_USB_SL811_CS)     += sl811_cs.o
  75  obj-$(CONFIG_USB_U132_HCD)     += u132-hcd.o
  76 diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
  77 new file mode 100644
  78 index 0000000..c30de7c
  79 --- /dev/null
  80 +++ b/drivers/usb/host/xhci-mtk-sch.c
  81 @@ -0,0 +1,415 @@
  82 +/*
  83 + * Copyright (c) 2015 MediaTek Inc.
  84 + * Author:
  85 + *  Zhigang.Wei <zhigang.wei@mediatek.com>
  86 + *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
  87 + *
  88 + * This software is licensed under the terms of the GNU General Public
  89 + * License version 2, as published by the Free Software Foundation, and
  90 + * may be copied, distributed, and modified under those terms.
  91 + *
  92 + * This program is distributed in the hope that it will be useful,
  93 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  94 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  95 + * GNU General Public License for more details.
  96 + *
  97 + */
  98 +
  99 +#include <linux/kernel.h>
 100 +#include <linux/module.h>
 101 +#include <linux/slab.h>
 102 +
 103 +#include "xhci.h"
 104 +#include "xhci-mtk.h"
 105 +
 106 +#define SS_BW_BOUNDARY 51000
 107 +/* table 5-5. High-speed Isoc Transaction Limits in usb_20 spec */
 108 +#define HS_BW_BOUNDARY 6144
 109 +/* usb2 spec section11.18.1: at most 188 FS bytes per microframe */
 110 +#define FS_PAYLOAD_MAX 188
 111 +
 112 +/* mtk scheduler bitmasks */
 113 +#define EP_BPKTS(p)    ((p) & 0x3f)
 114 +#define EP_BCSCOUNT(p) (((p) & 0x7) << 8)
 115 +#define EP_BBM(p)      ((p) << 11)
 116 +#define EP_BOFFSET(p)  ((p) & 0x3fff)
 117 +#define EP_BREPEAT(p)  (((p) & 0x7fff) << 16)
 118 +
 119 +static int is_fs_or_ls(enum usb_device_speed speed)
 120 +{
 121 +       return speed == USB_SPEED_FULL || speed == USB_SPEED_LOW;
 122 +}
 123 +
 124 +/*
 125 +* get the index of bandwidth domains array which @ep belongs to.
 126 +*
 127 +* the bandwidth domain array is saved to @sch_array of struct xhci_hcd_mtk,
 128 +* each HS root port is treated as a single bandwidth domain,
 129 +* but each SS root port is treated as two bandwidth domains, one for IN eps,
 130 +* one for OUT eps.
 131 +* @real_port value is defined as follow according to xHCI spec:
 132 +* 1 for SSport0, ..., N+1 for SSportN, N+2 for HSport0, N+3 for HSport1, etc
 133 +* so the bandwidth domain array is organized as follow for simplification:
 134 +* SSport0-OUT, SSport0-IN, ..., SSportX-OUT, SSportX-IN, HSport0, ..., HSportY
 135 +*/
 136 +static int get_bw_index(struct xhci_hcd *xhci, struct usb_device *udev,
 137 +       struct usb_host_endpoint *ep)
 138 +{
 139 +       struct xhci_virt_device *virt_dev;
 140 +       int bw_index;
 141 +
 142 +       virt_dev = xhci->devs[udev->slot_id];
 143 +
 144 +       if (udev->speed == USB_SPEED_SUPER) {
 145 +               if (usb_endpoint_dir_out(&ep->desc))
 146 +                       bw_index = (virt_dev->real_port - 1) * 2;
 147 +               else
 148 +                       bw_index = (virt_dev->real_port - 1) * 2 + 1;
 149 +       } else {
 150 +               /* add one more for each SS port */
 151 +               bw_index = virt_dev->real_port + xhci->num_usb3_ports - 1;
 152 +       }
 153 +
 154 +       return bw_index;
 155 +}
 156 +
 157 +static void setup_sch_info(struct usb_device *udev,
 158 +               struct xhci_ep_ctx *ep_ctx, struct mu3h_sch_ep_info *sch_ep)
 159 +{
 160 +       u32 ep_type;
 161 +       u32 ep_interval;
 162 +       u32 max_packet_size;
 163 +       u32 max_burst;
 164 +       u32 mult;
 165 +       u32 esit_pkts;
 166 +
 167 +       ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
 168 +       ep_interval = CTX_TO_EP_INTERVAL(le32_to_cpu(ep_ctx->ep_info));
 169 +       max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
 170 +       max_burst = CTX_TO_MAX_BURST(le32_to_cpu(ep_ctx->ep_info2));
 171 +       mult = CTX_TO_EP_MULT(le32_to_cpu(ep_ctx->ep_info));
 172 +
 173 +       sch_ep->esit = 1 << ep_interval;
 174 +       sch_ep->offset = 0;
 175 +       sch_ep->burst_mode = 0;
 176 +
 177 +       if (udev->speed == USB_SPEED_HIGH) {
 178 +               sch_ep->cs_count = 0;
 179 +
 180 +               /*
 181 +                * usb_20 spec section5.9
 182 +                * a single microframe is enough for HS synchromous endpoints
 183 +                * in a interval
 184 +                */
 185 +               sch_ep->num_budget_microframes = 1;
 186 +               sch_ep->repeat = 0;
 187 +
 188 +               /*
 189 +                * xHCI spec section6.2.3.4
 190 +                * @max_burst is the number of additional transactions
 191 +                * opportunities per microframe
 192 +                */
 193 +               sch_ep->pkts = max_burst + 1;
 194 +               sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
 195 +       } else if (udev->speed == USB_SPEED_SUPER) {
 196 +               /* usb3_r1 spec section4.4.7 & 4.4.8 */
 197 +               sch_ep->cs_count = 0;
 198 +               esit_pkts = (mult + 1) * (max_burst + 1);
 199 +               if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
 200 +                       sch_ep->pkts = esit_pkts;
 201 +                       sch_ep->num_budget_microframes = 1;
 202 +                       sch_ep->repeat = 0;
 203 +               }
 204 +
 205 +               if (ep_type == ISOC_IN_EP || ep_type == ISOC_OUT_EP) {
 206 +                       if (esit_pkts <= sch_ep->esit)
 207 +                               sch_ep->pkts = 1;
 208 +                       else
 209 +                               sch_ep->pkts = roundup_pow_of_two(esit_pkts)
 210 +                                       / sch_ep->esit;
 211 +
 212 +                       sch_ep->num_budget_microframes =
 213 +                               DIV_ROUND_UP(esit_pkts, sch_ep->pkts);
 214 +
 215 +                       if (sch_ep->num_budget_microframes > 1)
 216 +                               sch_ep->repeat = 1;
 217 +                       else
 218 +                               sch_ep->repeat = 0;
 219 +               }
 220 +               sch_ep->bw_cost_per_microframe = max_packet_size * sch_ep->pkts;
 221 +       } else if (is_fs_or_ls(udev->speed)) {
 222 +
 223 +               /*
 224 +                * usb_20 spec section11.18.4
 225 +                * assume worst cases
 226 +                */
 227 +               sch_ep->repeat = 0;
 228 +               sch_ep->pkts = 1; /* at most one packet for each microframe */
 229 +               if (ep_type == INT_IN_EP || ep_type == INT_OUT_EP) {
 230 +                       sch_ep->cs_count = 3; /* at most need 3 CS*/
 231 +                       /* one for SS and one for budgeted transaction */
 232 +                       sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
 233 +                       sch_ep->bw_cost_per_microframe = max_packet_size;
 234 +               }
 235 +               if (ep_type == ISOC_OUT_EP) {
 236 +
 237 +                       /*
 238 +                        * the best case FS budget assumes that 188 FS bytes
 239 +                        * occur in each microframe
 240 +                        */
 241 +                       sch_ep->num_budget_microframes = DIV_ROUND_UP(
 242 +                               max_packet_size, FS_PAYLOAD_MAX);
 243 +                       sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
 244 +                       sch_ep->cs_count = sch_ep->num_budget_microframes;
 245 +               }
 246 +               if (ep_type == ISOC_IN_EP) {
 247 +                       /* at most need additional two CS. */
 248 +                       sch_ep->cs_count = DIV_ROUND_UP(
 249 +                               max_packet_size, FS_PAYLOAD_MAX) + 2;
 250 +                       sch_ep->num_budget_microframes = sch_ep->cs_count + 2;
 251 +                       sch_ep->bw_cost_per_microframe = FS_PAYLOAD_MAX;
 252 +               }
 253 +       }
 254 +}
 255 +
 256 +/* Get maximum bandwidth when we schedule at offset slot. */
 257 +static u32 get_max_bw(struct mu3h_sch_bw_info *sch_bw,
 258 +       struct mu3h_sch_ep_info *sch_ep, u32 offset)
 259 +{
 260 +       u32 num_esit;
 261 +       u32 max_bw = 0;
 262 +       int i;
 263 +       int j;
 264 +
 265 +       num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
 266 +       for (i = 0; i < num_esit; i++) {
 267 +               u32 base = offset + i * sch_ep->esit;
 268 +
 269 +               for (j = 0; j < sch_ep->num_budget_microframes; j++) {
 270 +                       if (sch_bw->bus_bw[base + j] > max_bw)
 271 +                               max_bw = sch_bw->bus_bw[base + j];
 272 +               }
 273 +       }
 274 +       return max_bw;
 275 +}
 276 +
 277 +static void update_bus_bw(struct mu3h_sch_bw_info *sch_bw,
 278 +       struct mu3h_sch_ep_info *sch_ep, int bw_cost)
 279 +{
 280 +       u32 num_esit;
 281 +       u32 base;
 282 +       int i;
 283 +       int j;
 284 +
 285 +       num_esit = XHCI_MTK_MAX_ESIT / sch_ep->esit;
 286 +       for (i = 0; i < num_esit; i++) {
 287 +               base = sch_ep->offset + i * sch_ep->esit;
 288 +               for (j = 0; j < sch_ep->num_budget_microframes; j++)
 289 +                       sch_bw->bus_bw[base + j] += bw_cost;
 290 +       }
 291 +}
 292 +
 293 +static int check_sch_bw(struct usb_device *udev,
 294 +       struct mu3h_sch_bw_info *sch_bw, struct mu3h_sch_ep_info *sch_ep)
 295 +{
 296 +       u32 offset;
 297 +       u32 esit;
 298 +       u32 num_budget_microframes;
 299 +       u32 min_bw;
 300 +       u32 min_index;
 301 +       u32 worst_bw;
 302 +       u32 bw_boundary;
 303 +
 304 +       if (sch_ep->esit > XHCI_MTK_MAX_ESIT)
 305 +               sch_ep->esit = XHCI_MTK_MAX_ESIT;
 306 +
 307 +       esit = sch_ep->esit;
 308 +       num_budget_microframes = sch_ep->num_budget_microframes;
 309 +
 310 +       /*
 311 +        * Search through all possible schedule microframes.
 312 +        * and find a microframe where its worst bandwidth is minimum.
 313 +        */
 314 +       min_bw = ~0;
 315 +       min_index = 0;
 316 +       for (offset = 0; offset < esit; offset++) {
 317 +               if ((offset + num_budget_microframes) > sch_ep->esit)
 318 +                       break;
 319 +
 320 +               /*
 321 +                * usb_20 spec section11.18:
 322 +                * must never schedule Start-Split in Y6
 323 +                */
 324 +               if (is_fs_or_ls(udev->speed) && (offset % 8 == 6))
 325 +                       continue;
 326 +
 327 +               worst_bw = get_max_bw(sch_bw, sch_ep, offset);
 328 +               if (min_bw > worst_bw) {
 329 +                       min_bw = worst_bw;
 330 +                       min_index = offset;
 331 +               }
 332 +               if (min_bw == 0)
 333 +                       break;
 334 +       }
 335 +       sch_ep->offset = min_index;
 336 +
 337 +       bw_boundary = (udev->speed == USB_SPEED_SUPER)
 338 +                               ? SS_BW_BOUNDARY : HS_BW_BOUNDARY;
 339 +
 340 +       /* check bandwidth */
 341 +       if (min_bw + sch_ep->bw_cost_per_microframe > bw_boundary)
 342 +               return -ERANGE;
 343 +
 344 +       /* update bus bandwidth info */
 345 +       update_bus_bw(sch_bw, sch_ep, sch_ep->bw_cost_per_microframe);
 346 +
 347 +       return 0;
 348 +}
 349 +
 350 +static bool need_bw_sch(struct usb_host_endpoint *ep,
 351 +       enum usb_device_speed speed, int has_tt)
 352 +{
 353 +       /* only for periodic endpoints */
 354 +       if (usb_endpoint_xfer_control(&ep->desc)
 355 +               || usb_endpoint_xfer_bulk(&ep->desc))
 356 +               return false;
 357 +
 358 +       /*
 359 +        * for LS & FS periodic endpoints which its device don't attach
 360 +        * to TT are also ignored, root-hub will schedule them directly
 361 +        */
 362 +       if (is_fs_or_ls(speed) && !has_tt)
 363 +               return false;
 364 +
 365 +       return true;
 366 +}
 367 +
 368 +int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk)
 369 +{
 370 +       struct mu3h_sch_bw_info *sch_array;
 371 +       int num_usb_bus;
 372 +       int i;
 373 +
 374 +       /* ss IN and OUT are separated */
 375 +       num_usb_bus = mtk->num_u3_ports * 2 + mtk->num_u2_ports;
 376 +
 377 +       sch_array = kcalloc(num_usb_bus, sizeof(*sch_array), GFP_KERNEL);
 378 +       if (sch_array == NULL)
 379 +               return -ENOMEM;
 380 +
 381 +       for (i = 0; i < num_usb_bus; i++)
 382 +               INIT_LIST_HEAD(&sch_array[i].bw_ep_list);
 383 +
 384 +       mtk->sch_array = sch_array;
 385 +
 386 +       return 0;
 387 +}
 388 +EXPORT_SYMBOL_GPL(xhci_mtk_sch_init);
 389 +
 390 +void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk)
 391 +{
 392 +       kfree(mtk->sch_array);
 393 +}
 394 +EXPORT_SYMBOL_GPL(xhci_mtk_sch_exit);
 395 +
 396 +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
 397 +               struct usb_host_endpoint *ep)
 398 +{
 399 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 400 +       struct xhci_hcd *xhci;
 401 +       struct xhci_ep_ctx *ep_ctx;
 402 +       struct xhci_slot_ctx *slot_ctx;
 403 +       struct xhci_virt_device *virt_dev;
 404 +       struct mu3h_sch_bw_info *sch_bw;
 405 +       struct mu3h_sch_ep_info *sch_ep;
 406 +       struct mu3h_sch_bw_info *sch_array;
 407 +       unsigned int ep_index;
 408 +       int bw_index;
 409 +       int ret = 0;
 410 +
 411 +       xhci = hcd_to_xhci(hcd);
 412 +       virt_dev = xhci->devs[udev->slot_id];
 413 +       ep_index = xhci_get_endpoint_index(&ep->desc);
 414 +       slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
 415 +       ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
 416 +       sch_array = mtk->sch_array;
 417 +
 418 +       xhci_dbg(xhci, "%s() type:%d, speed:%d, mpkt:%d, dir:%d, ep:%p\n",
 419 +               __func__, usb_endpoint_type(&ep->desc), udev->speed,
 420 +               GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)),
 421 +               usb_endpoint_dir_in(&ep->desc), ep);
 422 +
 423 +       if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
 424 +               return 0;
 425 +
 426 +       bw_index = get_bw_index(xhci, udev, ep);
 427 +       sch_bw = &sch_array[bw_index];
 428 +
 429 +       sch_ep = kzalloc(sizeof(struct mu3h_sch_ep_info), GFP_NOIO);
 430 +       if (!sch_ep)
 431 +               return -ENOMEM;
 432 +
 433 +       setup_sch_info(udev, ep_ctx, sch_ep);
 434 +
 435 +       ret = check_sch_bw(udev, sch_bw, sch_ep);
 436 +       if (ret) {
 437 +               xhci_err(xhci, "Not enough bandwidth!\n");
 438 +               kfree(sch_ep);
 439 +               return -ENOSPC;
 440 +       }
 441 +
 442 +       list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
 443 +       sch_ep->ep = ep;
 444 +
 445 +       ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
 446 +               | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode));
 447 +       ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
 448 +               | EP_BREPEAT(sch_ep->repeat));
 449 +
 450 +       xhci_dbg(xhci, " PKTS:%x, CSCOUNT:%x, BM:%x, OFFSET:%x, REPEAT:%x\n",
 451 +                       sch_ep->pkts, sch_ep->cs_count, sch_ep->burst_mode,
 452 +                       sch_ep->offset, sch_ep->repeat);
 453 +
 454 +       return 0;
 455 +}
 456 +EXPORT_SYMBOL_GPL(xhci_mtk_add_ep_quirk);
 457 +
 458 +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
 459 +               struct usb_host_endpoint *ep)
 460 +{
 461 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 462 +       struct xhci_hcd *xhci;
 463 +       struct xhci_slot_ctx *slot_ctx;
 464 +       struct xhci_virt_device *virt_dev;
 465 +       struct mu3h_sch_bw_info *sch_array;
 466 +       struct mu3h_sch_bw_info *sch_bw;
 467 +       struct mu3h_sch_ep_info *sch_ep;
 468 +       int bw_index;
 469 +
 470 +       xhci = hcd_to_xhci(hcd);
 471 +       virt_dev = xhci->devs[udev->slot_id];
 472 +       slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
 473 +       sch_array = mtk->sch_array;
 474 +
 475 +       xhci_dbg(xhci, "%s() type:%d, speed:%d, mpks:%d, dir:%d, ep:%p\n",
 476 +               __func__, usb_endpoint_type(&ep->desc), udev->speed,
 477 +               GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc)),
 478 +               usb_endpoint_dir_in(&ep->desc), ep);
 479 +
 480 +       if (!need_bw_sch(ep, udev->speed, slot_ctx->tt_info & TT_SLOT))
 481 +               return;
 482 +
 483 +       bw_index = get_bw_index(xhci, udev, ep);
 484 +       sch_bw = &sch_array[bw_index];
 485 +
 486 +       list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) {
 487 +               if (sch_ep->ep == ep) {
 488 +                       update_bus_bw(sch_bw, sch_ep,
 489 +                               -sch_ep->bw_cost_per_microframe);
 490 +                       list_del(&sch_ep->endpoint);
 491 +                       kfree(sch_ep);
 492 +                       break;
 493 +               }
 494 +       }
 495 +}
 496 +EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
 497 diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
 498 new file mode 100644
 499 index 0000000..c9ab6a4
 500 --- /dev/null
 501 +++ b/drivers/usb/host/xhci-mtk.c
 502 @@ -0,0 +1,763 @@
 503 +/*
 504 + * MediaTek xHCI Host Controller Driver
 505 + *
 506 + * Copyright (c) 2015 MediaTek Inc.
 507 + * Author:
 508 + *  Chunfeng Yun <chunfeng.yun@mediatek.com>
 509 + *
 510 + * This software is licensed under the terms of the GNU General Public
 511 + * License version 2, as published by the Free Software Foundation, and
 512 + * may be copied, distributed, and modified under those terms.
 513 + *
 514 + * This program is distributed in the hope that it will be useful,
 515 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 516 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 517 + * GNU General Public License for more details.
 518 + *
 519 + */
 520 +
 521 +#include <linux/clk.h>
 522 +#include <linux/dma-mapping.h>
 523 +#include <linux/iopoll.h>
 524 +#include <linux/kernel.h>
 525 +#include <linux/mfd/syscon.h>
 526 +#include <linux/module.h>
 527 +#include <linux/of.h>
 528 +#include <linux/phy/phy.h>
 529 +#include <linux/platform_device.h>
 530 +#include <linux/pm_runtime.h>
 531 +#include <linux/regmap.h>
 532 +#include <linux/regulator/consumer.h>
 533 +
 534 +#include "xhci.h"
 535 +#include "xhci-mtk.h"
 536 +
 537 +/* ip_pw_ctrl0 register */
 538 +#define CTRL0_IP_SW_RST        BIT(0)
 539 +
 540 +/* ip_pw_ctrl1 register */
 541 +#define CTRL1_IP_HOST_PDN      BIT(0)
 542 +
 543 +/* ip_pw_ctrl2 register */
 544 +#define CTRL2_IP_DEV_PDN       BIT(0)
 545 +
 546 +/* ip_pw_sts1 register */
 547 +#define STS1_IP_SLEEP_STS      BIT(30)
 548 +#define STS1_XHCI_RST          BIT(11)
 549 +#define STS1_SYS125_RST        BIT(10)
 550 +#define STS1_REF_RST           BIT(8)
 551 +#define STS1_SYSPLL_STABLE     BIT(0)
 552 +
 553 +/* ip_xhci_cap register */
 554 +#define CAP_U3_PORT_NUM(p)     ((p) & 0xff)
 555 +#define CAP_U2_PORT_NUM(p)     (((p) >> 8) & 0xff)
 556 +
 557 +/* u3_ctrl_p register */
 558 +#define CTRL_U3_PORT_HOST_SEL  BIT(2)
 559 +#define CTRL_U3_PORT_PDN       BIT(1)
 560 +#define CTRL_U3_PORT_DIS       BIT(0)
 561 +
 562 +/* u2_ctrl_p register */
 563 +#define CTRL_U2_PORT_HOST_SEL  BIT(2)
 564 +#define CTRL_U2_PORT_PDN       BIT(1)
 565 +#define CTRL_U2_PORT_DIS       BIT(0)
 566 +
 567 +/* u2_phy_pll register */
 568 +#define CTRL_U2_FORCE_PLL_STB  BIT(28)
 569 +
 570 +#define PERI_WK_CTRL0          0x400
 571 +#define UWK_CTR0_0P_LS_PE      BIT(8)  /* posedge */
 572 +#define UWK_CTR0_0P_LS_NE      BIT(7)  /* negedge for 0p linestate*/
 573 +#define UWK_CTL1_1P_LS_C(x)    (((x) & 0xf) << 1)
 574 +#define UWK_CTL1_1P_LS_E       BIT(0)
 575 +
 576 +#define PERI_WK_CTRL1          0x404
 577 +#define UWK_CTL1_IS_C(x)       (((x) & 0xf) << 26)
 578 +#define UWK_CTL1_IS_E          BIT(25)
 579 +#define UWK_CTL1_0P_LS_C(x)    (((x) & 0xf) << 21)
 580 +#define UWK_CTL1_0P_LS_E       BIT(20)
 581 +#define UWK_CTL1_IDDIG_C(x)    (((x) & 0xf) << 11)  /* cycle debounce */
 582 +#define UWK_CTL1_IDDIG_E       BIT(10) /* enable debounce */
 583 +#define UWK_CTL1_IDDIG_P       BIT(9)  /* polarity */
 584 +#define UWK_CTL1_0P_LS_P       BIT(7)
 585 +#define UWK_CTL1_IS_P          BIT(6)  /* polarity for ip sleep */
 586 +
 587 +enum ssusb_wakeup_src {
 588 +       SSUSB_WK_IP_SLEEP = 1,
 589 +       SSUSB_WK_LINE_STATE = 2,
 590 +};
 591 +
 592 +static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
 593 +{
 594 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 595 +       u32 value, check_val;
 596 +       int ret;
 597 +       int i;
 598 +
 599 +       /* power on host ip */
 600 +       value = readl(&ippc->ip_pw_ctr1);
 601 +       value &= ~CTRL1_IP_HOST_PDN;
 602 +       writel(value, &ippc->ip_pw_ctr1);
 603 +
 604 +       /* power on and enable all u3 ports */
 605 +       for (i = 0; i < mtk->num_u3_ports; i++) {
 606 +               value = readl(&ippc->u3_ctrl_p[i]);
 607 +               value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
 608 +               value |= CTRL_U3_PORT_HOST_SEL;
 609 +               writel(value, &ippc->u3_ctrl_p[i]);
 610 +       }
 611 +
 612 +       /* power on and enable all u2 ports */
 613 +       for (i = 0; i < mtk->num_u2_ports; i++) {
 614 +               value = readl(&ippc->u2_ctrl_p[i]);
 615 +               value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
 616 +               value |= CTRL_U2_PORT_HOST_SEL;
 617 +               writel(value, &ippc->u2_ctrl_p[i]);
 618 +       }
 619 +
 620 +       /*
 621 +        * wait for clocks to be stable, and clock domains reset to
 622 +        * be inactive after power on and enable ports
 623 +        */
 624 +       check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
 625 +                       STS1_SYS125_RST | STS1_XHCI_RST;
 626 +
 627 +       ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
 628 +                         (check_val == (value & check_val)), 100, 20000);
 629 +       if (ret) {
 630 +               dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
 631 +               return ret;
 632 +       }
 633 +
 634 +       return 0;
 635 +}
 636 +
 637 +static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
 638 +{
 639 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 640 +       u32 value;
 641 +       int ret;
 642 +       int i;
 643 +
 644 +       /* power down all u3 ports */
 645 +       for (i = 0; i < mtk->num_u3_ports; i++) {
 646 +               value = readl(&ippc->u3_ctrl_p[i]);
 647 +               value |= CTRL_U3_PORT_PDN;
 648 +               writel(value, &ippc->u3_ctrl_p[i]);
 649 +       }
 650 +
 651 +       /* power down all u2 ports */
 652 +       for (i = 0; i < mtk->num_u2_ports; i++) {
 653 +               value = readl(&ippc->u2_ctrl_p[i]);
 654 +               value |= CTRL_U2_PORT_PDN;
 655 +               writel(value, &ippc->u2_ctrl_p[i]);
 656 +       }
 657 +
 658 +       /* power down host ip */
 659 +       value = readl(&ippc->ip_pw_ctr1);
 660 +       value |= CTRL1_IP_HOST_PDN;
 661 +       writel(value, &ippc->ip_pw_ctr1);
 662 +
 663 +       /* wait for host ip to sleep */
 664 +       ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
 665 +                         (value & STS1_IP_SLEEP_STS), 100, 100000);
 666 +       if (ret) {
 667 +               dev_err(mtk->dev, "ip sleep failed!!!\n");
 668 +               return ret;
 669 +       }
 670 +       return 0;
 671 +}
 672 +
 673 +static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
 674 +{
 675 +       struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
 676 +       u32 value;
 677 +
 678 +       /* reset whole ip */
 679 +       value = readl(&ippc->ip_pw_ctr0);
 680 +       value |= CTRL0_IP_SW_RST;
 681 +       writel(value, &ippc->ip_pw_ctr0);
 682 +       udelay(1);
 683 +       value = readl(&ippc->ip_pw_ctr0);
 684 +       value &= ~CTRL0_IP_SW_RST;
 685 +       writel(value, &ippc->ip_pw_ctr0);
 686 +
 687 +       /*
 688 +        * device ip is default power-on in fact
 689 +        * power down device ip, otherwise ip-sleep will fail
 690 +        */
 691 +       value = readl(&ippc->ip_pw_ctr2);
 692 +       value |= CTRL2_IP_DEV_PDN;
 693 +       writel(value, &ippc->ip_pw_ctr2);
 694 +
 695 +       value = readl(&ippc->ip_xhci_cap);
 696 +       mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
 697 +       mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
 698 +       dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
 699 +                       mtk->num_u2_ports, mtk->num_u3_ports);
 700 +
 701 +       return xhci_mtk_host_enable(mtk);
 702 +}
 703 +
 704 +static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
 705 +{
 706 +       int ret;
 707 +
 708 +       ret = clk_prepare_enable(mtk->sys_clk);
 709 +       if (ret) {
 710 +               dev_err(mtk->dev, "failed to enable sys_clk\n");
 711 +               goto sys_clk_err;
 712 +       }
 713 +
 714 +       if (mtk->wakeup_src) {
 715 +               ret = clk_prepare_enable(mtk->wk_deb_p0);
 716 +               if (ret) {
 717 +                       dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
 718 +                       goto usb_p0_err;
 719 +               }
 720 +
 721 +               ret = clk_prepare_enable(mtk->wk_deb_p1);
 722 +               if (ret) {
 723 +                       dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
 724 +                       goto usb_p1_err;
 725 +               }
 726 +       }
 727 +       return 0;
 728 +
 729 +usb_p1_err:
 730 +       clk_disable_unprepare(mtk->wk_deb_p0);
 731 +usb_p0_err:
 732 +       clk_disable_unprepare(mtk->sys_clk);
 733 +sys_clk_err:
 734 +       return -EINVAL;
 735 +}
 736 +
 737 +static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
 738 +{
 739 +       if (mtk->wakeup_src) {
 740 +               clk_disable_unprepare(mtk->wk_deb_p1);
 741 +               clk_disable_unprepare(mtk->wk_deb_p0);
 742 +       }
 743 +       clk_disable_unprepare(mtk->sys_clk);
 744 +}
 745 +
 746 +/* only clocks can be turn off for ip-sleep wakeup mode */
 747 +static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
 748 +{
 749 +       u32 tmp;
 750 +       struct regmap *pericfg = mtk->pericfg;
 751 +
 752 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 753 +       tmp &= ~UWK_CTL1_IS_P;
 754 +       tmp &= ~(UWK_CTL1_IS_C(0xf));
 755 +       tmp |= UWK_CTL1_IS_C(0x8);
 756 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 757 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
 758 +
 759 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 760 +       dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
 761 +               __func__, tmp);
 762 +}
 763 +
 764 +static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
 765 +{
 766 +       u32 tmp;
 767 +
 768 +       regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
 769 +       tmp &= ~UWK_CTL1_IS_E;
 770 +       regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
 771 +}
 772 +
 773 +/*
 774 +* for line-state wakeup mode, phy's power should not power-down
 775 +* and only support cable plug in/out
 776 +*/
 777 +static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
 778 +{
 779 +       u32 tmp;
 780 +       struct regmap *pericfg = mtk->pericfg;
 781 +
 782 +       /* line-state of u2-port0 */
 783 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 784 +       tmp &= ~UWK_CTL1_0P_LS_P;
 785 +       tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
 786 +       tmp |= UWK_CTL1_0P_LS_C(0x8);
 787 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 788 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 789 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
 790 +
 791 +       /* line-state of u2-port1 */
 792 +       regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
 793 +       tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
 794 +       tmp |= UWK_CTL1_1P_LS_C(0x8);
 795 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp);
 796 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
 797 +}
 798 +
 799 +static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
 800 +{
 801 +       u32 tmp;
 802 +       struct regmap *pericfg = mtk->pericfg;
 803 +
 804 +       /* line-state of u2-port0 */
 805 +       regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
 806 +       tmp &= ~UWK_CTL1_0P_LS_E;
 807 +       regmap_write(pericfg, PERI_WK_CTRL1, tmp);
 808 +
 809 +       /* line-state of u2-port1 */
 810 +       regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
 811 +       tmp &= ~UWK_CTL1_1P_LS_E;
 812 +       regmap_write(pericfg, PERI_WK_CTRL0, tmp);
 813 +}
 814 +
 815 +static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
 816 +{
 817 +       if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
 818 +               usb_wakeup_ip_sleep_en(mtk);
 819 +       else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
 820 +               usb_wakeup_line_state_en(mtk);
 821 +}
 822 +
 823 +static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
 824 +{
 825 +       if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
 826 +               usb_wakeup_ip_sleep_dis(mtk);
 827 +       else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
 828 +               usb_wakeup_line_state_dis(mtk);
 829 +}
 830 +
 831 +static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
 832 +                               struct device_node *dn)
 833 +{
 834 +       struct device *dev = mtk->dev;
 835 +
 836 +       /*
 837 +       * wakeup function is optional, so it is not an error if this property
 838 +       * does not exist, and in such case, no need to get relative
 839 +       * properties anymore.
 840 +       */
 841 +       of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
 842 +       if (!mtk->wakeup_src)
 843 +               return 0;
 844 +
 845 +       mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
 846 +       if (IS_ERR(mtk->wk_deb_p0)) {
 847 +               dev_err(dev, "fail to get wakeup_deb_p0\n");
 848 +               return PTR_ERR(mtk->wk_deb_p0);
 849 +       }
 850 +
 851 +       mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
 852 +       if (IS_ERR(mtk->wk_deb_p1)) {
 853 +               dev_err(dev, "fail to get wakeup_deb_p1\n");
 854 +               return PTR_ERR(mtk->wk_deb_p1);
 855 +       }
 856 +
 857 +       mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
 858 +                                               "mediatek,syscon-wakeup");
 859 +       if (IS_ERR(mtk->pericfg)) {
 860 +               dev_err(dev, "fail to get pericfg regs\n");
 861 +               return PTR_ERR(mtk->pericfg);
 862 +       }
 863 +
 864 +       return 0;
 865 +}
 866 +
 867 +static int xhci_mtk_setup(struct usb_hcd *hcd);
 868 +static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
 869 +       .extra_priv_size = sizeof(struct xhci_hcd),
 870 +       .reset = xhci_mtk_setup,
 871 +};
 872 +
 873 +static struct hc_driver __read_mostly xhci_mtk_hc_driver;
 874 +
 875 +static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
 876 +{
 877 +       int i;
 878 +       int ret;
 879 +
 880 +       for (i = 0; i < mtk->num_phys; i++) {
 881 +               ret = phy_init(mtk->phys[i]);
 882 +               if (ret)
 883 +                       goto exit_phy;
 884 +       }
 885 +       return 0;
 886 +
 887 +exit_phy:
 888 +       for (; i > 0; i--)
 889 +               phy_exit(mtk->phys[i - 1]);
 890 +
 891 +       return ret;
 892 +}
 893 +
 894 +static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
 895 +{
 896 +       int i;
 897 +
 898 +       for (i = 0; i < mtk->num_phys; i++)
 899 +               phy_exit(mtk->phys[i]);
 900 +
 901 +       return 0;
 902 +}
 903 +
 904 +static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
 905 +{
 906 +       int i;
 907 +       int ret;
 908 +
 909 +       for (i = 0; i < mtk->num_phys; i++) {
 910 +               ret = phy_power_on(mtk->phys[i]);
 911 +               if (ret)
 912 +                       goto power_off_phy;
 913 +       }
 914 +       return 0;
 915 +
 916 +power_off_phy:
 917 +       for (; i > 0; i--)
 918 +               phy_power_off(mtk->phys[i - 1]);
 919 +
 920 +       return ret;
 921 +}
 922 +
 923 +static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
 924 +{
 925 +       unsigned int i;
 926 +
 927 +       for (i = 0; i < mtk->num_phys; i++)
 928 +               phy_power_off(mtk->phys[i]);
 929 +}
 930 +
 931 +static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
 932 +{
 933 +       int ret;
 934 +
 935 +       ret = regulator_enable(mtk->vbus);
 936 +       if (ret) {
 937 +               dev_err(mtk->dev, "failed to enable vbus\n");
 938 +               return ret;
 939 +       }
 940 +
 941 +       ret = regulator_enable(mtk->vusb33);
 942 +       if (ret) {
 943 +               dev_err(mtk->dev, "failed to enable vusb33\n");
 944 +               regulator_disable(mtk->vbus);
 945 +               return ret;
 946 +       }
 947 +       return 0;
 948 +}
 949 +
 950 +static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
 951 +{
 952 +       regulator_disable(mtk->vbus);
 953 +       regulator_disable(mtk->vusb33);
 954 +}
 955 +
 956 +static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
 957 +{
 958 +       struct usb_hcd *hcd = xhci_to_hcd(xhci);
 959 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 960 +
 961 +       /*
 962 +        * As of now platform drivers don't provide MSI support so we ensure
 963 +        * here that the generic code does not try to make a pci_dev from our
 964 +        * dev struct in order to setup MSI
 965 +        */
 966 +       xhci->quirks |= XHCI_PLAT;
 967 +       xhci->quirks |= XHCI_MTK_HOST;
 968 +       /*
 969 +        * MTK host controller gives a spurious successful event after a
 970 +        * short transfer. Ignore it.
 971 +        */
 972 +       xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
 973 +       if (mtk->lpm_support)
 974 +               xhci->quirks |= XHCI_LPM_SUPPORT;
 975 +}
 976 +
 977 +/* called during probe() after chip reset completes */
 978 +static int xhci_mtk_setup(struct usb_hcd *hcd)
 979 +{
 980 +       struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
 981 +       int ret;
 982 +
 983 +       if (usb_hcd_is_primary_hcd(hcd)) {
 984 +               ret = xhci_mtk_ssusb_config(mtk);
 985 +               if (ret)
 986 +                       return ret;
 987 +               ret = xhci_mtk_sch_init(mtk);
 988 +               if (ret)
 989 +                       return ret;
 990 +       }
 991 +
 992 +       return xhci_gen_setup(hcd, xhci_mtk_quirks);
 993 +}
 994 +
 995 +static int xhci_mtk_probe(struct platform_device *pdev)
 996 +{
 997 +       struct device *dev = &pdev->dev;
 998 +       struct device_node *node = dev->of_node;
 999 +       struct xhci_hcd_mtk *mtk;
1000 +       const struct hc_driver *driver;
1001 +       struct xhci_hcd *xhci;
1002 +       struct resource *res;
1003 +       struct usb_hcd *hcd;
1004 +       struct phy *phy;
1005 +       int phy_num;
1006 +       int ret = -ENODEV;
1007 +       int irq;
1008 +
1009 +       if (usb_disabled())
1010 +               return -ENODEV;
1011 +
1012 +       driver = &xhci_mtk_hc_driver;
1013 +       mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
1014 +       if (!mtk)
1015 +               return -ENOMEM;
1016 +
1017 +       mtk->dev = dev;
1018 +       mtk->vbus = devm_regulator_get(dev, "vbus");
1019 +       if (IS_ERR(mtk->vbus)) {
1020 +               dev_err(dev, "fail to get vbus\n");
1021 +               return PTR_ERR(mtk->vbus);
1022 +       }
1023 +
1024 +       mtk->vusb33 = devm_regulator_get(dev, "vusb33");
1025 +       if (IS_ERR(mtk->vusb33)) {
1026 +               dev_err(dev, "fail to get vusb33\n");
1027 +               return PTR_ERR(mtk->vusb33);
1028 +       }
1029 +
1030 +       mtk->sys_clk = devm_clk_get(dev, "sys_ck");
1031 +       if (IS_ERR(mtk->sys_clk)) {
1032 +               dev_err(dev, "fail to get sys_ck\n");
1033 +               return PTR_ERR(mtk->sys_clk);
1034 +       }
1035 +
1036 +       mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
1037 +
1038 +       ret = usb_wakeup_of_property_parse(mtk, node);
1039 +       if (ret)
1040 +               return ret;
1041 +
1042 +       mtk->num_phys = of_count_phandle_with_args(node,
1043 +                       "phys", "#phy-cells");
1044 +       if (mtk->num_phys > 0) {
1045 +               mtk->phys = devm_kcalloc(dev, mtk->num_phys,
1046 +                                       sizeof(*mtk->phys), GFP_KERNEL);
1047 +               if (!mtk->phys)
1048 +                       return -ENOMEM;
1049 +       } else {
1050 +               mtk->num_phys = 0;
1051 +       }
1052 +       pm_runtime_enable(dev);
1053 +       pm_runtime_get_sync(dev);
1054 +       device_enable_async_suspend(dev);
1055 +
1056 +       ret = xhci_mtk_ldos_enable(mtk);
1057 +       if (ret)
1058 +               goto disable_pm;
1059 +
1060 +       ret = xhci_mtk_clks_enable(mtk);
1061 +       if (ret)
1062 +               goto disable_ldos;
1063 +
1064 +       irq = platform_get_irq(pdev, 0);
1065 +       if (irq < 0)
1066 +               goto disable_clk;
1067 +
1068 +       /* Initialize dma_mask and coherent_dma_mask to 32-bits */
1069 +       ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
1070 +       if (ret)
1071 +               goto disable_clk;
1072 +
1073 +       if (!dev->dma_mask)
1074 +               dev->dma_mask = &dev->coherent_dma_mask;
1075 +       else
1076 +               dma_set_mask(dev, DMA_BIT_MASK(32));
1077 +
1078 +       hcd = usb_create_hcd(driver, dev, dev_name(dev));
1079 +       if (!hcd) {
1080 +               ret = -ENOMEM;
1081 +               goto disable_clk;
1082 +       }
1083 +
1084 +       /*
1085 +        * USB 2.0 roothub is stored in the platform_device.
1086 +        * Swap it with mtk HCD.
1087 +        */
1088 +       mtk->hcd = platform_get_drvdata(pdev);
1089 +       platform_set_drvdata(pdev, mtk);
1090 +
1091 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1092 +       hcd->regs = devm_ioremap_resource(dev, res);
1093 +       if (IS_ERR(hcd->regs)) {
1094 +               ret = PTR_ERR(hcd->regs);
1095 +               goto put_usb2_hcd;
1096 +       }
1097 +       hcd->rsrc_start = res->start;
1098 +       hcd->rsrc_len = resource_size(res);
1099 +
1100 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1101 +       mtk->ippc_regs = devm_ioremap_resource(dev, res);
1102 +       if (IS_ERR(mtk->ippc_regs)) {
1103 +               ret = PTR_ERR(mtk->ippc_regs);
1104 +               goto put_usb2_hcd;
1105 +       }
1106 +
1107 +       for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
1108 +               phy = devm_of_phy_get_by_index(dev, node, phy_num);
1109 +               if (IS_ERR(phy)) {
1110 +                       ret = PTR_ERR(phy);
1111 +                       goto put_usb2_hcd;
1112 +               }
1113 +               mtk->phys[phy_num] = phy;
1114 +       }
1115 +
1116 +       ret = xhci_mtk_phy_init(mtk);
1117 +       if (ret)
1118 +               goto put_usb2_hcd;
1119 +
1120 +       ret = xhci_mtk_phy_power_on(mtk);
1121 +       if (ret)
1122 +               goto exit_phys;
1123 +
1124 +       device_init_wakeup(dev, true);
1125 +
1126 +       xhci = hcd_to_xhci(hcd);
1127 +       xhci->main_hcd = hcd;
1128 +       xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
1129 +                       dev_name(dev), hcd);
1130 +       if (!xhci->shared_hcd) {
1131 +               ret = -ENOMEM;
1132 +               goto power_off_phys;
1133 +       }
1134 +
1135 +       if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
1136 +               xhci->shared_hcd->can_do_streams = 1;
1137 +
1138 +       ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
1139 +       if (ret)
1140 +               goto put_usb3_hcd;
1141 +
1142 +       ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
1143 +       if (ret)
1144 +               goto dealloc_usb2_hcd;
1145 +
1146 +       return 0;
1147 +
1148 +dealloc_usb2_hcd:
1149 +       usb_remove_hcd(hcd);
1150 +
1151 +put_usb3_hcd:
1152 +       xhci_mtk_sch_exit(mtk);
1153 +       usb_put_hcd(xhci->shared_hcd);
1154 +
1155 +power_off_phys:
1156 +       xhci_mtk_phy_power_off(mtk);
1157 +       device_init_wakeup(dev, false);
1158 +
1159 +exit_phys:
1160 +       xhci_mtk_phy_exit(mtk);
1161 +
1162 +put_usb2_hcd:
1163 +       usb_put_hcd(hcd);
1164 +
1165 +disable_clk:
1166 +       xhci_mtk_clks_disable(mtk);
1167 +
1168 +disable_ldos:
1169 +       xhci_mtk_ldos_disable(mtk);
1170 +
1171 +disable_pm:
1172 +       pm_runtime_put_sync(dev);
1173 +       pm_runtime_disable(dev);
1174 +       return ret;
1175 +}
1176 +
1177 +static int xhci_mtk_remove(struct platform_device *dev)
1178 +{
1179 +       struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
1180 +       struct usb_hcd  *hcd = mtk->hcd;
1181 +       struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1182 +
1183 +       usb_remove_hcd(xhci->shared_hcd);
1184 +       xhci_mtk_phy_power_off(mtk);
1185 +       xhci_mtk_phy_exit(mtk);
1186 +       device_init_wakeup(&dev->dev, false);
1187 +
1188 +       usb_remove_hcd(hcd);
1189 +       usb_put_hcd(xhci->shared_hcd);
1190 +       usb_put_hcd(hcd);
1191 +       xhci_mtk_sch_exit(mtk);
1192 +       xhci_mtk_clks_disable(mtk);
1193 +       xhci_mtk_ldos_disable(mtk);
1194 +       pm_runtime_put_sync(&dev->dev);
1195 +       pm_runtime_disable(&dev->dev);
1196 +
1197 +       return 0;
1198 +}
1199 +
1200 +#ifdef CONFIG_PM_SLEEP
1201 +static int xhci_mtk_suspend(struct device *dev)
1202 +{
1203 +       struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
1204 +
1205 +       xhci_mtk_host_disable(mtk);
1206 +       xhci_mtk_phy_power_off(mtk);
1207 +       xhci_mtk_clks_disable(mtk);
1208 +       usb_wakeup_enable(mtk);
1209 +       return 0;
1210 +}
1211 +
1212 +static int xhci_mtk_resume(struct device *dev)
1213 +{
1214 +       struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
1215 +
1216 +       usb_wakeup_disable(mtk);
1217 +       xhci_mtk_clks_enable(mtk);
1218 +       xhci_mtk_phy_power_on(mtk);
1219 +       xhci_mtk_host_enable(mtk);
1220 +       return 0;
1221 +}
1222 +
1223 +static const struct dev_pm_ops xhci_mtk_pm_ops = {
1224 +       SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
1225 +};
1226 +#define DEV_PM_OPS     (&xhci_mtk_pm_ops)
1227 +#else
1228 +#define DEV_PM_OPS     NULL
1229 +#endif /* CONFIG_PM */
1230 +
1231 +#ifdef CONFIG_OF
1232 +static const struct of_device_id mtk_xhci_of_match[] = {
1233 +       { .compatible = "mediatek,mt8173-xhci"},
1234 +       { },
1235 +};
1236 +MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
1237 +#endif
1238 +
1239 +static struct platform_driver mtk_xhci_driver = {
1240 +       .probe  = xhci_mtk_probe,
1241 +       .remove = xhci_mtk_remove,
1242 +       .driver = {
1243 +               .name = "xhci-mtk",
1244 +               .pm = DEV_PM_OPS,
1245 +               .of_match_table = of_match_ptr(mtk_xhci_of_match),
1246 +       },
1247 +};
1248 +MODULE_ALIAS("platform:xhci-mtk");
1249 +
1250 +static int __init xhci_mtk_init(void)
1251 +{
1252 +       xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
1253 +       return platform_driver_register(&mtk_xhci_driver);
1254 +}
1255 +module_init(xhci_mtk_init);
1256 +
1257 +static void __exit xhci_mtk_exit(void)
1258 +{
1259 +       platform_driver_unregister(&mtk_xhci_driver);
1260 +}
1261 +module_exit(xhci_mtk_exit);
1262 +
1263 +MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
1264 +MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
1265 +MODULE_LICENSE("GPL v2");
1266 diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
1267 new file mode 100644
1268 index 0000000..7da677c
1269 --- /dev/null
1270 +++ b/drivers/usb/host/xhci-mtk.h
1271 @@ -0,0 +1,162 @@
1272 +/*
1273 + * Copyright (c) 2015 MediaTek Inc.
1274 + * Author:
1275 + *  Zhigang.Wei <zhigang.wei@mediatek.com>
1276 + *  Chunfeng.Yun <chunfeng.yun@mediatek.com>
1277 + *
1278 + * This software is licensed under the terms of the GNU General Public
1279 + * License version 2, as published by the Free Software Foundation, and
1280 + * may be copied, distributed, and modified under those terms.
1281 + *
1282 + * This program is distributed in the hope that it will be useful,
1283 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1284 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1285 + * GNU General Public License for more details.
1286 + *
1287 + */
1288 +
1289 +#ifndef _XHCI_MTK_H_
1290 +#define _XHCI_MTK_H_
1291 +
1292 +#include "xhci.h"
1293 +
1294 +/**
1295 + * To simplify scheduler algorithm, set a upper limit for ESIT,
1296 + * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
1297 + * round down to the limit value, that means allocating more
1298 + * bandwidth to it.
1299 + */
1300 +#define XHCI_MTK_MAX_ESIT      64
1301 +
1302 +/**
1303 + * struct mu3h_sch_bw_info: schedule information for bandwidth domain
1304 + *
1305 + * @bus_bw: array to keep track of bandwidth already used at each uframes
1306 + * @bw_ep_list: eps in the bandwidth domain
1307 + *
1308 + * treat a HS root port as a bandwidth domain, but treat a SS root port as
1309 + * two bandwidth domains, one for IN eps and another for OUT eps.
1310 + */
1311 +struct mu3h_sch_bw_info {
1312 +       u32 bus_bw[XHCI_MTK_MAX_ESIT];
1313 +       struct list_head bw_ep_list;
1314 +};
1315 +
1316 +/**
1317 + * struct mu3h_sch_ep_info: schedule information for endpoint
1318 + *
1319 + * @esit: unit is 125us, equal to 2 << Interval field in ep-context
1320 + * @num_budget_microframes: number of continuous uframes
1321 + *             (@repeat==1) scheduled within the interval
1322 + * @bw_cost_per_microframe: bandwidth cost per microframe
1323 + * @endpoint: linked into bandwidth domain which it belongs to
1324 + * @ep: address of usb_host_endpoint struct
1325 + * @offset: which uframe of the interval that transfer should be
1326 + *             scheduled first time within the interval
1327 + * @repeat: the time gap between two uframes that transfers are
1328 + *             scheduled within a interval. in the simple algorithm, only
1329 + *             assign 0 or 1 to it; 0 means using only one uframe in a
1330 + *             interval, and 1 means using @num_budget_microframes
1331 + *             continuous uframes
1332 + * @pkts: number of packets to be transferred in the scheduled uframes
1333 + * @cs_count: number of CS that host will trigger
1334 + * @burst_mode: burst mode for scheduling. 0: normal burst mode,
1335 + *             distribute the bMaxBurst+1 packets for a single burst
1336 + *             according to @pkts and @repeat, repeate the burst multiple
1337 + *             times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
1338 + *             according to @pkts and @repeat. normal mode is used by
1339 + *             default
1340 + */
1341 +struct mu3h_sch_ep_info {
1342 +       u32 esit;
1343 +       u32 num_budget_microframes;
1344 +       u32 bw_cost_per_microframe;
1345 +       struct list_head endpoint;
1346 +       void *ep;
1347 +       /*
1348 +        * mtk xHCI scheduling information put into reserved DWs
1349 +        * in ep context
1350 +        */
1351 +       u32 offset;
1352 +       u32 repeat;
1353 +       u32 pkts;
1354 +       u32 cs_count;
1355 +       u32 burst_mode;
1356 +};
1357 +
1358 +#define MU3C_U3_PORT_MAX 4
1359 +#define MU3C_U2_PORT_MAX 5
1360 +
1361 +/**
1362 + * struct mu3c_ippc_regs: MTK ssusb ip port control registers
1363 + * @ip_pw_ctr0~3: ip power and clock control registers
1364 + * @ip_pw_sts1~2: ip power and clock status registers
1365 + * @ip_xhci_cap: ip xHCI capability register
1366 + * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
1367 + * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
1368 + * @u2_phy_pll: usb2 phy pll control register
1369 + */
1370 +struct mu3c_ippc_regs {
1371 +       __le32 ip_pw_ctr0;
1372 +       __le32 ip_pw_ctr1;
1373 +       __le32 ip_pw_ctr2;
1374 +       __le32 ip_pw_ctr3;
1375 +       __le32 ip_pw_sts1;
1376 +       __le32 ip_pw_sts2;
1377 +       __le32 reserved0[3];
1378 +       __le32 ip_xhci_cap;
1379 +       __le32 reserved1[2];
1380 +       __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
1381 +       __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
1382 +       __le32 reserved2;
1383 +       __le32 u2_phy_pll;
1384 +       __le32 reserved3[33]; /* 0x80 ~ 0xff */
1385 +};
1386 +
1387 +struct xhci_hcd_mtk {
1388 +       struct device *dev;
1389 +       struct usb_hcd *hcd;
1390 +       struct mu3h_sch_bw_info *sch_array;
1391 +       struct mu3c_ippc_regs __iomem *ippc_regs;
1392 +       int num_u2_ports;
1393 +       int num_u3_ports;
1394 +       struct regulator *vusb33;
1395 +       struct regulator *vbus;
1396 +       struct clk *sys_clk;    /* sys and mac clock */
1397 +       struct clk *wk_deb_p0;  /* port0's wakeup debounce clock */
1398 +       struct clk *wk_deb_p1;
1399 +       struct regmap *pericfg;
1400 +       struct phy **phys;
1401 +       int num_phys;
1402 +       int wakeup_src;
1403 +       bool lpm_support;
1404 +};
1405 +
1406 +static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
1407 +{
1408 +       return dev_get_drvdata(hcd->self.controller);
1409 +}
1410 +
1411 +#if IS_ENABLED(CONFIG_USB_XHCI_MTK)
1412 +int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
1413 +void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
1414 +int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
1415 +               struct usb_host_endpoint *ep);
1416 +void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
1417 +               struct usb_host_endpoint *ep);
1418 +
1419 +#else
1420 +static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
1421 +       struct usb_device *udev, struct usb_host_endpoint *ep)
1422 +{
1423 +       return 0;
1424 +}
1425 +
1426 +static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
1427 +       struct usb_device *udev, struct usb_host_endpoint *ep)
1428 +{
1429 +}
1430 +
1431 +#endif
1432 +
1433 +#endif         /* _XHCI_MTK_H_ */
1434 diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
1435 index eeaa6c6..f1c21c4 100644
1436 --- a/drivers/usb/host/xhci-ring.c
1437 +++ b/drivers/usb/host/xhci-ring.c
1438 @@ -68,6 +68,7 @@
1439  #include <linux/slab.h>
1440  #include "xhci.h"
1441  #include "xhci-trace.h"
1442 +#include "xhci-mtk.h"
1443
1444  /*
1445   * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
1446 @@ -3075,17 +3076,22 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
1447  {
1448         u32 maxp, total_packet_count;
1449
1450 -       if (xhci->hci_version < 0x100)
1451 +       /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */
1452 +       if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
1453                 return ((td_total_len - transferred) >> 10);
1454
1455 -       maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
1456 -       total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
1457 -
1458         /* One TRB with a zero-length data packet. */
1459         if (num_trbs_left == 0 || (transferred == 0 && trb_buff_len == 0) ||
1460             trb_buff_len == td_total_len)
1461                 return 0;
1462
1463 +       /* for MTK xHCI, TD size doesn't include this TRB */
1464 +       if (xhci->quirks & XHCI_MTK_HOST)
1465 +               trb_buff_len = 0;
1466 +
1467 +       maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
1468 +       total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
1469 +
1470         /* Queueing functions don't count the current TRB into transferred */
1471         return (total_packet_count - ((transferred + trb_buff_len) / maxp));
1472  }
1473 @@ -3473,7 +3479,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
1474                 field |= 0x1;
1475
1476         /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
1477 -       if (xhci->hci_version >= 0x100) {
1478 +       if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
1479                 if (urb->transfer_buffer_length > 0) {
1480                         if (setup->bRequestType & USB_DIR_IN)
1481                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
1482 diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
1483 index 3f91270..15fedb2 100644
1484 --- a/drivers/usb/host/xhci.c
1485 +++ b/drivers/usb/host/xhci.c
1486 @@ -31,6 +31,7 @@
1487
1488  #include "xhci.h"
1489  #include "xhci-trace.h"
1490 +#include "xhci-mtk.h"
1491
1492  #define DRIVER_AUTHOR "Sarah Sharp"
1493  #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
1494 @@ -634,7 +635,11 @@ int xhci_run(struct usb_hcd *hcd)
1495                         "// Set the interrupt modulation register");
1496         temp = readl(&xhci->ir_set->irq_control);
1497         temp &= ~ER_IRQ_INTERVAL_MASK;
1498 -       temp |= (u32) 160;
1499 +       /*
1500 +        * the increment interval is 8 times as much as that defined
1501 +        * in xHCI spec on MTK's controller
1502 +        */
1503 +       temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
1504         writel(temp, &xhci->ir_set->irq_control);
1505
1506         /* Set the HCD state before we enable the irqs */
1507 @@ -1698,6 +1703,9 @@ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1508
1509         xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1510
1511 +       if (xhci->quirks & XHCI_MTK_HOST)
1512 +               xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1513 +
1514         xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1515                         (unsigned int) ep->desc.bEndpointAddress,
1516                         udev->slot_id,
1517 @@ -1793,6 +1801,15 @@ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1518                 return -ENOMEM;
1519         }
1520
1521 +       if (xhci->quirks & XHCI_MTK_HOST) {
1522 +               ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1523 +               if (ret < 0) {
1524 +                       xhci_free_or_cache_endpoint_ring(xhci,
1525 +                               virt_dev, ep_index);
1526 +                       return ret;
1527 +               }
1528 +       }
1529 +
1530         ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1531         new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1532
1533 diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
1534 index 0b94512..40cf36e 100644
1535 --- a/drivers/usb/host/xhci.h
1536 +++ b/drivers/usb/host/xhci.h
1537 @@ -1630,6 +1630,7 @@ struct xhci_hcd {
1538  /* For controllers with a broken beyond repair streams implementation */
1539  #define XHCI_BROKEN_STREAMS    (1 << 19)
1540  #define XHCI_PME_STUCK_QUIRK   (1 << 20)
1541 +#define XHCI_MTK_HOST          (1 << 21)
1542         unsigned int            num_active_eps;
1543         unsigned int            limit_active_eps;
1544         /* There are two roothubs to keep track of bus suspend info for */
1545 --
1546 1.7.10.4
1547