96c6bc1c01c995e1ff7f9dc6f0a4975483ac9c53
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0020-arm64-dts-mediatek-add-xHCI-usb-phy-for-mt8173.patch
1 From 31a22fbd0d3b187be61c4c5d22b19c95abb327c3 Mon Sep 17 00:00:00 2001
2 From: "chunfeng.yun@mediatek.com" <chunfeng.yun@mediatek.com>
3 Date: Tue, 17 Nov 2015 17:18:41 +0800
4 Subject: [PATCH 20/81] arm64: dts: mediatek: add xHCI & usb phy for mt8173
5
6 add xHCI and phy drivers for MT8173-EVB
7
8 Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 ---
10 arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 16 ++++++++++
11 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 42 +++++++++++++++++++++++++++
12 2 files changed, 58 insertions(+)
13
14 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
15 +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
16 @@ -13,6 +13,7 @@
17 */
18
19 /dts-v1/;
20 +#include <dt-bindings/gpio/gpio.h>
21 #include "mt8173.dtsi"
22
23 / {
24 @@ -32,6 +33,15 @@
25 };
26
27 chosen { };
28 +
29 + usb_p1_vbus: regulator@0 {
30 + compatible = "regulator-fixed";
31 + regulator-name = "usb_vbus";
32 + regulator-min-microvolt = <5000000>;
33 + regulator-max-microvolt = <5000000>;
34 + gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
35 + enable-active-high;
36 + };
37 };
38
39 &i2c1 {
40 @@ -408,3 +418,9 @@
41 &uart0 {
42 status = "okay";
43 };
44 +
45 +&usb30 {
46 + vusb33-supply = <&mt6397_vusb_reg>;
47 + vbus-supply = <&usb_p1_vbus>;
48 + mediatek,wakeup-src = <1>;
49 +};
50 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
51 +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
52 @@ -14,6 +14,7 @@
53 #include <dt-bindings/clock/mt8173-clk.h>
54 #include <dt-bindings/interrupt-controller/irq.h>
55 #include <dt-bindings/interrupt-controller/arm-gic.h>
56 +#include <dt-bindings/phy/phy.h>
57 #include <dt-bindings/power/mt8173-power.h>
58 #include <dt-bindings/reset-controller/mt8173-resets.h>
59 #include "mt8173-pinfunc.h"
60 @@ -510,6 +511,47 @@
61 status = "disabled";
62 };
63
64 + usb30: usb@11270000 {
65 + compatible = "mediatek,mt8173-xhci";
66 + reg = <0 0x11270000 0 0x1000>,
67 + <0 0x11280700 0 0x0100>;
68 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
69 + power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
70 + clocks = <&topckgen CLK_TOP_USB30_SEL>,
71 + <&pericfg CLK_PERI_USB0>,
72 + <&pericfg CLK_PERI_USB1>;
73 + clock-names = "sys_ck",
74 + "wakeup_deb_p0",
75 + "wakeup_deb_p1";
76 + phys = <&phy_port0 PHY_TYPE_USB3>,
77 + <&phy_port1 PHY_TYPE_USB2>;
78 + mediatek,syscon-wakeup = <&pericfg>;
79 + status = "okay";
80 + };
81 +
82 + u3phy: usb-phy@11290000 {
83 + compatible = "mediatek,mt8173-u3phy";
84 + reg = <0 0x11290000 0 0x800>;
85 + clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
86 + clock-names = "u3phya_ref";
87 + #address-cells = <2>;
88 + #size-cells = <2>;
89 + ranges;
90 + status = "okay";
91 +
92 + phy_port0: port@11290800 {
93 + reg = <0 0x11290800 0 0x800>;
94 + #phy-cells = <1>;
95 + status = "okay";
96 + };
97 +
98 + phy_port1: port@11291000 {
99 + reg = <0 0x11291000 0 0x800>;
100 + #phy-cells = <1>;
101 + status = "okay";
102 + };
103 + };
104 +
105 mmsys: clock-controller@14000000 {
106 compatible = "mediatek,mt8173-mmsys", "syscon";
107 reg = <0 0x14000000 0 0x1000>;