4e13a3879e4d303a6663601c68613503e82fca7e
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0033-soc-mediatek-PMIC-wrap-add-wrapper-callbacks-for-ini.patch
1 From 915340f70c0594d1f0717fee3eb678fa71206509 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 20 Jan 2016 05:27:17 +0100
4 Subject: [PATCH 33/81] soc: mediatek: PMIC wrap: add wrapper callbacks for
5 init_reg_clock
6
7 Split init_reg_clock up into SoC specific callbacks. The patch also
8 reorders the code to avoid the need for callback function prototypes.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 ---
12 drivers/soc/mediatek/mtk-pmic-wrap.c | 70 ++++++++++++++++++----------------
13 1 file changed, 38 insertions(+), 32 deletions(-)
14
15 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
16 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
17 @@ -354,24 +354,6 @@ enum pwrap_type {
18 PWRAP_MT8173,
19 };
20
21 -struct pmic_wrapper_type {
22 - int *regs;
23 - enum pwrap_type type;
24 - u32 arb_en_all;
25 -};
26 -
27 -static struct pmic_wrapper_type pwrap_mt8135 = {
28 - .regs = mt8135_regs,
29 - .type = PWRAP_MT8135,
30 - .arb_en_all = 0x1ff,
31 -};
32 -
33 -static struct pmic_wrapper_type pwrap_mt8173 = {
34 - .regs = mt8173_regs,
35 - .type = PWRAP_MT8173,
36 - .arb_en_all = 0x3f,
37 -};
38 -
39 struct pmic_wrapper {
40 struct device *dev;
41 void __iomem *base;
42 @@ -385,6 +367,13 @@ struct pmic_wrapper {
43 void __iomem *bridge_base;
44 };
45
46 +struct pmic_wrapper_type {
47 + int *regs;
48 + enum pwrap_type type;
49 + u32 arb_en_all;
50 + int (*init_reg_clock)(struct pmic_wrapper *wrp);
51 +};
52 +
53 static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
54 {
55 return wrp->master->type == PWRAP_MT8135;
56 @@ -578,20 +567,23 @@ static int pwrap_init_sidly(struct pmic_
57 return 0;
58 }
59
60 -static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
61 +static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
62 {
63 - if (pwrap_is_mt8135(wrp)) {
64 - pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
65 - pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
66 - pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
67 - pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
68 - pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
69 - } else {
70 - pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
71 - pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
72 - pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
73 - pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
74 - }
75 + pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
76 + pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
77 + pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
78 + pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
79 + pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
80 +
81 + return 0;
82 +}
83 +
84 +static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
85 +{
86 + pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
87 + pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
88 + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
89 + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
90
91 return 0;
92 }
93 @@ -699,7 +691,7 @@ static int pwrap_init(struct pmic_wrappe
94
95 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
96
97 - ret = pwrap_init_reg_clock(wrp);
98 + ret = wrp->master->init_reg_clock(wrp);
99 if (ret)
100 return ret;
101
102 @@ -814,6 +806,20 @@ static const struct regmap_config pwrap_
103 .max_register = 0xffff,
104 };
105
106 +static struct pmic_wrapper_type pwrap_mt8135 = {
107 + .regs = mt8135_regs,
108 + .type = PWRAP_MT8135,
109 + .arb_en_all = 0x1ff,
110 + .init_reg_clock = pwrap_mt8135_init_reg_clock,
111 +};
112 +
113 +static struct pmic_wrapper_type pwrap_mt8173 = {
114 + .regs = mt8173_regs,
115 + .type = PWRAP_MT8173,
116 + .arb_en_all = 0x3f,
117 + .init_reg_clock = pwrap_mt8173_init_reg_clock,
118 +};
119 +
120 static struct of_device_id of_pwrap_match_tbl[] = {
121 {
122 .compatible = "mediatek,mt8135-pwrap",