mediatek: update patches
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0041-soc-mediatek-PMIC-wrap-add-MT2701-7623-support.patch
1 From ec6ad56b62c6cd769b5a35e7009518d99bbbb7b6 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 20 Jan 2016 12:09:14 +0100
4 Subject: [PATCH 41/91] soc: mediatek: PMIC wrap: add MT2701/7623 support
5
6 Add the registers, callbacks and data structures required to make the
7 wrapper work on MT2701 and MT7623.
8
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 ---
11 drivers/soc/mediatek/mtk-pmic-wrap.c | 154 ++++++++++++++++++++++++++++++++++
12 1 file changed, 154 insertions(+)
13
14 diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
15 index 0e4ebb8..3c3e56d 100644
16 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
17 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
18 @@ -52,6 +52,7 @@
19 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
20
21 /* macro for manual command */
22 +#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
23 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
24 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
25 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
26 @@ -200,6 +201,13 @@ enum pwrap_regs {
27 PWRAP_DCM_EN,
28 PWRAP_DCM_DBC_PRD,
29
30 + /* MT2701 only regs */
31 + PWRAP_ADC_CMD_ADDR,
32 + PWRAP_PWRAP_ADC_CMD,
33 + PWRAP_ADC_RDY_ADDR,
34 + PWRAP_ADC_RDATA_ADDR1,
35 + PWRAP_ADC_RDATA_ADDR2,
36 +
37 /* MT8135 only regs */
38 PWRAP_CSHEXT,
39 PWRAP_EVENT_IN_EN,
40 @@ -236,6 +244,92 @@ enum pwrap_regs {
41 PWRAP_CIPHER_EN,
42 };
43
44 +static int mt2701_regs[] = {
45 + [PWRAP_MUX_SEL] = 0x0,
46 + [PWRAP_WRAP_EN] = 0x4,
47 + [PWRAP_DIO_EN] = 0x8,
48 + [PWRAP_SIDLY] = 0xc,
49 + [PWRAP_RDDMY] = 0x18,
50 + [PWRAP_SI_CK_CON] = 0x1c,
51 + [PWRAP_CSHEXT_WRITE] = 0x20,
52 + [PWRAP_CSHEXT_READ] = 0x24,
53 + [PWRAP_CSLEXT_START] = 0x28,
54 + [PWRAP_CSLEXT_END] = 0x2c,
55 + [PWRAP_STAUPD_PRD] = 0x30,
56 + [PWRAP_STAUPD_GRPEN] = 0x34,
57 + [PWRAP_STAUPD_MAN_TRIG] = 0x38,
58 + [PWRAP_STAUPD_STA] = 0x3c,
59 + [PWRAP_WRAP_STA] = 0x44,
60 + [PWRAP_HARB_INIT] = 0x48,
61 + [PWRAP_HARB_HPRIO] = 0x4c,
62 + [PWRAP_HIPRIO_ARB_EN] = 0x50,
63 + [PWRAP_HARB_STA0] = 0x54,
64 + [PWRAP_HARB_STA1] = 0x58,
65 + [PWRAP_MAN_EN] = 0x5c,
66 + [PWRAP_MAN_CMD] = 0x60,
67 + [PWRAP_MAN_RDATA] = 0x64,
68 + [PWRAP_MAN_VLDCLR] = 0x68,
69 + [PWRAP_WACS0_EN] = 0x6c,
70 + [PWRAP_INIT_DONE0] = 0x70,
71 + [PWRAP_WACS0_CMD] = 0x74,
72 + [PWRAP_WACS0_RDATA] = 0x78,
73 + [PWRAP_WACS0_VLDCLR] = 0x7c,
74 + [PWRAP_WACS1_EN] = 0x80,
75 + [PWRAP_INIT_DONE1] = 0x84,
76 + [PWRAP_WACS1_CMD] = 0x88,
77 + [PWRAP_WACS1_RDATA] = 0x8c,
78 + [PWRAP_WACS1_VLDCLR] = 0x90,
79 + [PWRAP_WACS2_EN] = 0x94,
80 + [PWRAP_INIT_DONE2] = 0x98,
81 + [PWRAP_WACS2_CMD] = 0x9c,
82 + [PWRAP_WACS2_RDATA] = 0xa0,
83 + [PWRAP_WACS2_VLDCLR] = 0xa4,
84 + [PWRAP_INT_EN] = 0xa8,
85 + [PWRAP_INT_FLG_RAW] = 0xac,
86 + [PWRAP_INT_FLG] = 0xb0,
87 + [PWRAP_INT_CLR] = 0xb4,
88 + [PWRAP_SIG_ADR] = 0xb8,
89 + [PWRAP_SIG_MODE] = 0xbc,
90 + [PWRAP_SIG_VALUE] = 0xc0,
91 + [PWRAP_SIG_ERRVAL] = 0xc4,
92 + [PWRAP_CRC_EN] = 0xc8,
93 + [PWRAP_TIMER_EN] = 0xcc,
94 + [PWRAP_TIMER_STA] = 0xd0,
95 + [PWRAP_WDT_UNIT] = 0xd4,
96 + [PWRAP_WDT_SRC_EN] = 0xd8,
97 + [PWRAP_WDT_FLG] = 0xdc,
98 + [PWRAP_DEBUG_INT_SEL] = 0xe0,
99 + [PWRAP_DVFS_ADR0] = 0xe4,
100 + [PWRAP_DVFS_WDATA0] = 0xe8,
101 + [PWRAP_DVFS_ADR1] = 0xec,
102 + [PWRAP_DVFS_WDATA1] = 0xf0,
103 + [PWRAP_DVFS_ADR2] = 0xf4,
104 + [PWRAP_DVFS_WDATA2] = 0xf8,
105 + [PWRAP_DVFS_ADR3] = 0xfc,
106 + [PWRAP_DVFS_WDATA3] = 0x100,
107 + [PWRAP_DVFS_ADR4] = 0x104,
108 + [PWRAP_DVFS_WDATA4] = 0x108,
109 + [PWRAP_DVFS_ADR5] = 0x10c,
110 + [PWRAP_DVFS_WDATA5] = 0x110,
111 + [PWRAP_DVFS_ADR6] = 0x114,
112 + [PWRAP_DVFS_WDATA6] = 0x118,
113 + [PWRAP_DVFS_ADR7] = 0x11c,
114 + [PWRAP_DVFS_WDATA7] = 0x120,
115 + [PWRAP_CIPHER_KEY_SEL] = 0x124,
116 + [PWRAP_CIPHER_IV_SEL] = 0x128,
117 + [PWRAP_CIPHER_EN] = 0x12c,
118 + [PWRAP_CIPHER_RDY] = 0x130,
119 + [PWRAP_CIPHER_MODE] = 0x134,
120 + [PWRAP_CIPHER_SWRST] = 0x138,
121 + [PWRAP_DCM_EN] = 0x13c,
122 + [PWRAP_DCM_DBC_PRD] = 0x140,
123 + [PWRAP_ADC_CMD_ADDR] = 0x144,
124 + [PWRAP_PWRAP_ADC_CMD] = 0x148,
125 + [PWRAP_ADC_RDY_ADDR] = 0x14c,
126 + [PWRAP_ADC_RDATA_ADDR1] = 0x150,
127 + [PWRAP_ADC_RDATA_ADDR2] = 0x154,
128 +};
129 +
130 static int mt8173_regs[] = {
131 [PWRAP_MUX_SEL] = 0x0,
132 [PWRAP_WRAP_EN] = 0x4,
133 @@ -397,6 +491,7 @@ enum pmic_type {
134 };
135
136 enum pwrap_type {
137 + PWRAP_MT2701,
138 PWRAP_MT8135,
139 PWRAP_MT8173,
140 };
141 @@ -637,6 +732,31 @@ static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
142 return 0;
143 }
144
145 +static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
146 +{
147 + switch (wrp->slave->type) {
148 + case PMIC_MT6397:
149 + pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
150 + pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
151 + pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
152 + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
153 + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
154 + break;
155 +
156 + case PMIC_MT6323:
157 + pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
158 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
159 + 0x8);
160 + pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
161 + pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
162 + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
163 + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
164 + break;
165 + }
166 +
167 + return 0;
168 +}
169 +
170 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
171 {
172 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
173 @@ -670,6 +790,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
174 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
175 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
176 break;
177 + case PWRAP_MT2701:
178 case PWRAP_MT8173:
179 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
180 break;
181 @@ -772,6 +893,24 @@ static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
182 return 0;
183 }
184
185 +static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
186 +{
187 + /* GPS_INTF initialization */
188 + switch (wrp->slave->type) {
189 + case PMIC_MT6323:
190 + pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
191 + pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
192 + pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
193 + pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
194 + pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
195 + break;
196 + default:
197 + break;
198 + }
199 +
200 + return 0;
201 +}
202 +
203 static int pwrap_init(struct pmic_wrapper *wrp)
204 {
205 int ret;
206 @@ -916,6 +1055,18 @@ static const struct of_device_id of_slave_match_tbl[] = {
207 };
208 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
209
210 +static const struct pmic_wrapper_type pwrap_mt2701 = {
211 + .regs = mt2701_regs,
212 + .type = PWRAP_MT2701,
213 + .arb_en_all = 0x3f,
214 + .int_en_all = ~(BIT(31) | BIT(2)),
215 + .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
216 + .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
217 + .has_bridge = 0,
218 + .init_reg_clock = pwrap_mt2701_init_reg_clock,
219 + .init_soc_specific = pwrap_mt2701_init_soc_specific,
220 +};
221 +
222 static struct pmic_wrapper_type pwrap_mt8135 = {
223 .regs = mt8135_regs,
224 .type = PWRAP_MT8135,
225 @@ -942,6 +1093,9 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
226
227 static struct of_device_id of_pwrap_match_tbl[] = {
228 {
229 + .compatible = "mediatek,mt2701-pwrap",
230 + .data = &pwrap_mt2701,
231 + }, {
232 .compatible = "mediatek,mt8135-pwrap",
233 .data = &pwrap_mt8135,
234 }, {
235 --
236 1.7.10.4
237