mediatek: update patches
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0045-mfd-mt6397-add-MT6323-support-to-MT6397-driver.patch
1 From 52dde352cc7a558eab85458c3f7ab90dc652f761 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 8 Jan 2016 04:09:43 +0100
4 Subject: [PATCH 45/91] mfd: mt6397: add MT6323 support to MT6397 driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mfd/mt6397-core.c | 20 ++
9 include/linux/mfd/mt6323/core.h | 36 +++
10 include/linux/mfd/mt6323/registers.h | 408 ++++++++++++++++++++++++++++++++++
11 3 files changed, 464 insertions(+)
12 create mode 100644 include/linux/mfd/mt6323/core.h
13 create mode 100644 include/linux/mfd/mt6323/registers.h
14
15 diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
16 index aa91606..8234cd3 100644
17 --- a/drivers/mfd/mt6397-core.c
18 +++ b/drivers/mfd/mt6397-core.c
19 @@ -19,11 +19,14 @@
20 #include <linux/regmap.h>
21 #include <linux/mfd/core.h>
22 #include <linux/mfd/mt6397/core.h>
23 +#include <linux/mfd/mt6323/core.h>
24 #include <linux/mfd/mt6397/registers.h>
25 +#include <linux/mfd/mt6323/registers.h>
26
27 #define MT6397_RTC_BASE 0xe000
28 #define MT6397_RTC_SIZE 0x3e
29
30 +#define MT6323_CID_CODE 0x23
31 #define MT6391_CID_CODE 0x91
32 #define MT6397_CID_CODE 0x97
33
34 @@ -40,6 +43,13 @@ static const struct resource mt6397_rtc_resources[] = {
35 },
36 };
37
38 +static const struct mfd_cell mt6323_devs[] = {
39 + {
40 + .name = "mt6323-regulator",
41 + .of_compatible = "mediatek,mt6323-regulator"
42 + },
43 +};
44 +
45 static const struct mfd_cell mt6397_devs[] = {
46 {
47 .name = "mt6397-rtc",
48 @@ -261,6 +271,15 @@ static int mt6397_probe(struct platform_device *pdev)
49 }
50
51 switch (id & 0xff) {
52 + case MT6323_CID_CODE:
53 + pmic->int_con[0] = MT6323_INT_CON0;
54 + pmic->int_con[1] = MT6323_INT_CON1;
55 + pmic->int_status[0] = MT6323_INT_STATUS0;
56 + pmic->int_status[1] = MT6323_INT_STATUS1;
57 + ret = mfd_add_devices(&pdev->dev, -1, mt6323_devs,
58 + ARRAY_SIZE(mt6323_devs), NULL, 0, NULL);
59 + break;
60 +
61 case MT6397_CID_CODE:
62 case MT6391_CID_CODE:
63 pmic->int_con[0] = MT6397_INT_CON0;
64 @@ -302,6 +321,7 @@ static int mt6397_remove(struct platform_device *pdev)
65
66 static const struct of_device_id mt6397_of_match[] = {
67 { .compatible = "mediatek,mt6397" },
68 + { .compatible = "mediatek,mt6323" },
69 { }
70 };
71 MODULE_DEVICE_TABLE(of, mt6397_of_match);
72 diff --git a/include/linux/mfd/mt6323/core.h b/include/linux/mfd/mt6323/core.h
73 new file mode 100644
74 index 0000000..06d0ec3
75 --- /dev/null
76 +++ b/include/linux/mfd/mt6323/core.h
77 @@ -0,0 +1,36 @@
78 +/*
79 + * Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
80 + *
81 + * This program is free software; you can redistribute it and/or modify
82 + * it under the terms of the GNU General Public License version 2 as
83 + * published by the Free Software Foundation.
84 + */
85 +
86 +#ifndef __MFD_MT6323_CORE_H__
87 +#define __MFD_MT6323_CORE_H__
88 +
89 +enum MT6323_IRQ_STATUS_numbers {
90 + MT6323_IRQ_STATUS_SPKL_AB = 0,
91 + MT6323_IRQ_STATUS_SPKL,
92 + MT6323_IRQ_STATUS_BAT_L,
93 + MT6323_IRQ_STATUS_BAT_H,
94 + MT6323_IRQ_STATUS_WATCHDOG,
95 + MT6323_IRQ_STATUS_PWRKEY,
96 + MT6323_IRQ_STATUS_THR_L,
97 + MT6323_IRQ_STATUS_THR_H,
98 + MT6323_IRQ_STATUS_VBATON_UNDET,
99 + MT6323_IRQ_STATUS_BVALID_DET,
100 + MT6323_IRQ_STATUS_CHRDET,
101 + MT6323_IRQ_STATUS_OV,
102 + MT6323_IRQ_STATUS_LDO = 16,
103 + MT6323_IRQ_STATUS_FCHRKEY,
104 + MT6323_IRQ_STATUS_ACCDET,
105 + MT6323_IRQ_STATUS_AUDIO,
106 + MT6323_IRQ_STATUS_RTC,
107 + MT6323_IRQ_STATUS_VPROC,
108 + MT6323_IRQ_STATUS_VSYS,
109 + MT6323_IRQ_STATUS_VPA,
110 + MT6323_IRQ_STATUS_NR,
111 +};
112 +
113 +#endif /* __MFD_MT6323_CORE_H__ */
114 diff --git a/include/linux/mfd/mt6323/registers.h b/include/linux/mfd/mt6323/registers.h
115 new file mode 100644
116 index 0000000..160f3c0
117 --- /dev/null
118 +++ b/include/linux/mfd/mt6323/registers.h
119 @@ -0,0 +1,408 @@
120 +/*
121 + * Copyright (c) 2016 Chen Zhong <chen.zhong@mediatek.com>
122 + *
123 + * This program is free software; you can redistribute it and/or modify
124 + * it under the terms of the GNU General Public License version 2 as
125 + * published by the Free Software Foundation.
126 + */
127 +
128 +#ifndef __MFD_MT6323_REGISTERS_H__
129 +#define __MFD_MT6323_REGISTERS_H__
130 +
131 +/* PMIC Registers */
132 +#define MT6323_CHR_CON0 0x0000
133 +#define MT6323_CHR_CON1 0x0002
134 +#define MT6323_CHR_CON2 0x0004
135 +#define MT6323_CHR_CON3 0x0006
136 +#define MT6323_CHR_CON4 0x0008
137 +#define MT6323_CHR_CON5 0x000A
138 +#define MT6323_CHR_CON6 0x000C
139 +#define MT6323_CHR_CON7 0x000E
140 +#define MT6323_CHR_CON8 0x0010
141 +#define MT6323_CHR_CON9 0x0012
142 +#define MT6323_CHR_CON10 0x0014
143 +#define MT6323_CHR_CON11 0x0016
144 +#define MT6323_CHR_CON12 0x0018
145 +#define MT6323_CHR_CON13 0x001A
146 +#define MT6323_CHR_CON14 0x001C
147 +#define MT6323_CHR_CON15 0x001E
148 +#define MT6323_CHR_CON16 0x0020
149 +#define MT6323_CHR_CON17 0x0022
150 +#define MT6323_CHR_CON18 0x0024
151 +#define MT6323_CHR_CON19 0x0026
152 +#define MT6323_CHR_CON20 0x0028
153 +#define MT6323_CHR_CON21 0x002A
154 +#define MT6323_CHR_CON22 0x002C
155 +#define MT6323_CHR_CON23 0x002E
156 +#define MT6323_CHR_CON24 0x0030
157 +#define MT6323_CHR_CON25 0x0032
158 +#define MT6323_CHR_CON26 0x0034
159 +#define MT6323_CHR_CON27 0x0036
160 +#define MT6323_CHR_CON28 0x0038
161 +#define MT6323_CHR_CON29 0x003A
162 +#define MT6323_STRUP_CON0 0x003C
163 +#define MT6323_STRUP_CON2 0x003E
164 +#define MT6323_STRUP_CON3 0x0040
165 +#define MT6323_STRUP_CON4 0x0042
166 +#define MT6323_STRUP_CON5 0x0044
167 +#define MT6323_STRUP_CON6 0x0046
168 +#define MT6323_STRUP_CON7 0x0048
169 +#define MT6323_STRUP_CON8 0x004A
170 +#define MT6323_STRUP_CON9 0x004C
171 +#define MT6323_STRUP_CON10 0x004E
172 +#define MT6323_STRUP_CON11 0x0050
173 +#define MT6323_SPK_CON0 0x0052
174 +#define MT6323_SPK_CON1 0x0054
175 +#define MT6323_SPK_CON2 0x0056
176 +#define MT6323_SPK_CON6 0x005E
177 +#define MT6323_SPK_CON7 0x0060
178 +#define MT6323_SPK_CON8 0x0062
179 +#define MT6323_SPK_CON9 0x0064
180 +#define MT6323_SPK_CON10 0x0066
181 +#define MT6323_SPK_CON11 0x0068
182 +#define MT6323_SPK_CON12 0x006A
183 +#define MT6323_CID 0x0100
184 +#define MT6323_TOP_CKPDN0 0x0102
185 +#define MT6323_TOP_CKPDN0_SET 0x0104
186 +#define MT6323_TOP_CKPDN0_CLR 0x0106
187 +#define MT6323_TOP_CKPDN1 0x0108
188 +#define MT6323_TOP_CKPDN1_SET 0x010A
189 +#define MT6323_TOP_CKPDN1_CLR 0x010C
190 +#define MT6323_TOP_CKPDN2 0x010E
191 +#define MT6323_TOP_CKPDN2_SET 0x0110
192 +#define MT6323_TOP_CKPDN2_CLR 0x0112
193 +#define MT6323_TOP_RST_CON 0x0114
194 +#define MT6323_TOP_RST_CON_SET 0x0116
195 +#define MT6323_TOP_RST_CON_CLR 0x0118
196 +#define MT6323_TOP_RST_MISC 0x011A
197 +#define MT6323_TOP_RST_MISC_SET 0x011C
198 +#define MT6323_TOP_RST_MISC_CLR 0x011E
199 +#define MT6323_TOP_CKCON0 0x0120
200 +#define MT6323_TOP_CKCON0_SET 0x0122
201 +#define MT6323_TOP_CKCON0_CLR 0x0124
202 +#define MT6323_TOP_CKCON1 0x0126
203 +#define MT6323_TOP_CKCON1_SET 0x0128
204 +#define MT6323_TOP_CKCON1_CLR 0x012A
205 +#define MT6323_TOP_CKTST0 0x012C
206 +#define MT6323_TOP_CKTST1 0x012E
207 +#define MT6323_TOP_CKTST2 0x0130
208 +#define MT6323_TEST_OUT 0x0132
209 +#define MT6323_TEST_CON0 0x0134
210 +#define MT6323_TEST_CON1 0x0136
211 +#define MT6323_EN_STATUS0 0x0138
212 +#define MT6323_EN_STATUS1 0x013A
213 +#define MT6323_OCSTATUS0 0x013C
214 +#define MT6323_OCSTATUS1 0x013E
215 +#define MT6323_PGSTATUS 0x0140
216 +#define MT6323_CHRSTATUS 0x0142
217 +#define MT6323_TDSEL_CON 0x0144
218 +#define MT6323_RDSEL_CON 0x0146
219 +#define MT6323_SMT_CON0 0x0148
220 +#define MT6323_SMT_CON1 0x014A
221 +#define MT6323_SMT_CON2 0x014C
222 +#define MT6323_SMT_CON3 0x014E
223 +#define MT6323_SMT_CON4 0x0150
224 +#define MT6323_DRV_CON0 0x0152
225 +#define MT6323_DRV_CON1 0x0154
226 +#define MT6323_DRV_CON2 0x0156
227 +#define MT6323_DRV_CON3 0x0158
228 +#define MT6323_DRV_CON4 0x015A
229 +#define MT6323_SIMLS1_CON 0x015C
230 +#define MT6323_SIMLS2_CON 0x015E
231 +#define MT6323_INT_CON0 0x0160
232 +#define MT6323_INT_CON0_SET 0x0162
233 +#define MT6323_INT_CON0_CLR 0x0164
234 +#define MT6323_INT_CON1 0x0166
235 +#define MT6323_INT_CON1_SET 0x0168
236 +#define MT6323_INT_CON1_CLR 0x016A
237 +#define MT6323_INT_MISC_CON 0x016C
238 +#define MT6323_INT_MISC_CON_SET 0x016E
239 +#define MT6323_INT_MISC_CON_CLR 0x0170
240 +#define MT6323_INT_STATUS0 0x0172
241 +#define MT6323_INT_STATUS1 0x0174
242 +#define MT6323_OC_GEAR_0 0x0176
243 +#define MT6323_OC_GEAR_1 0x0178
244 +#define MT6323_OC_GEAR_2 0x017A
245 +#define MT6323_OC_CTL_VPROC 0x017C
246 +#define MT6323_OC_CTL_VSYS 0x017E
247 +#define MT6323_OC_CTL_VPA 0x0180
248 +#define MT6323_FQMTR_CON0 0x0182
249 +#define MT6323_FQMTR_CON1 0x0184
250 +#define MT6323_FQMTR_CON2 0x0186
251 +#define MT6323_RG_SPI_CON 0x0188
252 +#define MT6323_DEW_DIO_EN 0x018A
253 +#define MT6323_DEW_READ_TEST 0x018C
254 +#define MT6323_DEW_WRITE_TEST 0x018E
255 +#define MT6323_DEW_CRC_SWRST 0x0190
256 +#define MT6323_DEW_CRC_EN 0x0192
257 +#define MT6323_DEW_CRC_VAL 0x0194
258 +#define MT6323_DEW_DBG_MON_SEL 0x0196
259 +#define MT6323_DEW_CIPHER_KEY_SEL 0x0198
260 +#define MT6323_DEW_CIPHER_IV_SEL 0x019A
261 +#define MT6323_DEW_CIPHER_EN 0x019C
262 +#define MT6323_DEW_CIPHER_RDY 0x019E
263 +#define MT6323_DEW_CIPHER_MODE 0x01A0
264 +#define MT6323_DEW_CIPHER_SWRST 0x01A2
265 +#define MT6323_DEW_RDDMY_NO 0x01A4
266 +#define MT6323_DEW_RDATA_DLY_SEL 0x01A6
267 +#define MT6323_BUCK_CON0 0x0200
268 +#define MT6323_BUCK_CON1 0x0202
269 +#define MT6323_BUCK_CON2 0x0204
270 +#define MT6323_BUCK_CON3 0x0206
271 +#define MT6323_BUCK_CON4 0x0208
272 +#define MT6323_BUCK_CON5 0x020A
273 +#define MT6323_VPROC_CON0 0x020C
274 +#define MT6323_VPROC_CON1 0x020E
275 +#define MT6323_VPROC_CON2 0x0210
276 +#define MT6323_VPROC_CON3 0x0212
277 +#define MT6323_VPROC_CON4 0x0214
278 +#define MT6323_VPROC_CON5 0x0216
279 +#define MT6323_VPROC_CON7 0x021A
280 +#define MT6323_VPROC_CON8 0x021C
281 +#define MT6323_VPROC_CON9 0x021E
282 +#define MT6323_VPROC_CON10 0x0220
283 +#define MT6323_VPROC_CON11 0x0222
284 +#define MT6323_VPROC_CON12 0x0224
285 +#define MT6323_VPROC_CON13 0x0226
286 +#define MT6323_VPROC_CON14 0x0228
287 +#define MT6323_VPROC_CON15 0x022A
288 +#define MT6323_VPROC_CON18 0x0230
289 +#define MT6323_VSYS_CON0 0x0232
290 +#define MT6323_VSYS_CON1 0x0234
291 +#define MT6323_VSYS_CON2 0x0236
292 +#define MT6323_VSYS_CON3 0x0238
293 +#define MT6323_VSYS_CON4 0x023A
294 +#define MT6323_VSYS_CON5 0x023C
295 +#define MT6323_VSYS_CON7 0x0240
296 +#define MT6323_VSYS_CON8 0x0242
297 +#define MT6323_VSYS_CON9 0x0244
298 +#define MT6323_VSYS_CON10 0x0246
299 +#define MT6323_VSYS_CON11 0x0248
300 +#define MT6323_VSYS_CON12 0x024A
301 +#define MT6323_VSYS_CON13 0x024C
302 +#define MT6323_VSYS_CON14 0x024E
303 +#define MT6323_VSYS_CON15 0x0250
304 +#define MT6323_VSYS_CON18 0x0256
305 +#define MT6323_VPA_CON0 0x0300
306 +#define MT6323_VPA_CON1 0x0302
307 +#define MT6323_VPA_CON2 0x0304
308 +#define MT6323_VPA_CON3 0x0306
309 +#define MT6323_VPA_CON4 0x0308
310 +#define MT6323_VPA_CON5 0x030A
311 +#define MT6323_VPA_CON7 0x030E
312 +#define MT6323_VPA_CON8 0x0310
313 +#define MT6323_VPA_CON9 0x0312
314 +#define MT6323_VPA_CON10 0x0314
315 +#define MT6323_VPA_CON11 0x0316
316 +#define MT6323_VPA_CON12 0x0318
317 +#define MT6323_VPA_CON14 0x031C
318 +#define MT6323_VPA_CON16 0x0320
319 +#define MT6323_VPA_CON17 0x0322
320 +#define MT6323_VPA_CON18 0x0324
321 +#define MT6323_VPA_CON19 0x0326
322 +#define MT6323_VPA_CON20 0x0328
323 +#define MT6323_BUCK_K_CON0 0x032A
324 +#define MT6323_BUCK_K_CON1 0x032C
325 +#define MT6323_BUCK_K_CON2 0x032E
326 +#define MT6323_ISINK0_CON0 0x0330
327 +#define MT6323_ISINK0_CON1 0x0332
328 +#define MT6323_ISINK0_CON2 0x0334
329 +#define MT6323_ISINK0_CON3 0x0336
330 +#define MT6323_ISINK1_CON0 0x0338
331 +#define MT6323_ISINK1_CON1 0x033A
332 +#define MT6323_ISINK1_CON2 0x033C
333 +#define MT6323_ISINK1_CON3 0x033E
334 +#define MT6323_ISINK2_CON0 0x0340
335 +#define MT6323_ISINK2_CON1 0x0342
336 +#define MT6323_ISINK2_CON2 0x0344
337 +#define MT6323_ISINK2_CON3 0x0346
338 +#define MT6323_ISINK3_CON0 0x0348
339 +#define MT6323_ISINK3_CON1 0x034A
340 +#define MT6323_ISINK3_CON2 0x034C
341 +#define MT6323_ISINK3_CON3 0x034E
342 +#define MT6323_ISINK_ANA0 0x0350
343 +#define MT6323_ISINK_ANA1 0x0352
344 +#define MT6323_ISINK_PHASE_DLY 0x0354
345 +#define MT6323_ISINK_EN_CTRL 0x0356
346 +#define MT6323_ANALDO_CON0 0x0400
347 +#define MT6323_ANALDO_CON1 0x0402
348 +#define MT6323_ANALDO_CON2 0x0404
349 +#define MT6323_ANALDO_CON3 0x0406
350 +#define MT6323_ANALDO_CON4 0x0408
351 +#define MT6323_ANALDO_CON5 0x040A
352 +#define MT6323_ANALDO_CON6 0x040C
353 +#define MT6323_ANALDO_CON7 0x040E
354 +#define MT6323_ANALDO_CON8 0x0410
355 +#define MT6323_ANALDO_CON10 0x0412
356 +#define MT6323_ANALDO_CON15 0x0414
357 +#define MT6323_ANALDO_CON16 0x0416
358 +#define MT6323_ANALDO_CON17 0x0418
359 +#define MT6323_ANALDO_CON18 0x041A
360 +#define MT6323_ANALDO_CON19 0x041C
361 +#define MT6323_ANALDO_CON20 0x041E
362 +#define MT6323_ANALDO_CON21 0x0420
363 +#define MT6323_DIGLDO_CON0 0x0500
364 +#define MT6323_DIGLDO_CON2 0x0502
365 +#define MT6323_DIGLDO_CON3 0x0504
366 +#define MT6323_DIGLDO_CON5 0x0506
367 +#define MT6323_DIGLDO_CON6 0x0508
368 +#define MT6323_DIGLDO_CON7 0x050A
369 +#define MT6323_DIGLDO_CON8 0x050C
370 +#define MT6323_DIGLDO_CON9 0x050E
371 +#define MT6323_DIGLDO_CON10 0x0510
372 +#define MT6323_DIGLDO_CON11 0x0512
373 +#define MT6323_DIGLDO_CON12 0x0514
374 +#define MT6323_DIGLDO_CON13 0x0516
375 +#define MT6323_DIGLDO_CON14 0x0518
376 +#define MT6323_DIGLDO_CON15 0x051A
377 +#define MT6323_DIGLDO_CON16 0x051C
378 +#define MT6323_DIGLDO_CON17 0x051E
379 +#define MT6323_DIGLDO_CON18 0x0520
380 +#define MT6323_DIGLDO_CON19 0x0522
381 +#define MT6323_DIGLDO_CON20 0x0524
382 +#define MT6323_DIGLDO_CON21 0x0526
383 +#define MT6323_DIGLDO_CON23 0x0528
384 +#define MT6323_DIGLDO_CON24 0x052A
385 +#define MT6323_DIGLDO_CON26 0x052C
386 +#define MT6323_DIGLDO_CON27 0x052E
387 +#define MT6323_DIGLDO_CON28 0x0530
388 +#define MT6323_DIGLDO_CON29 0x0532
389 +#define MT6323_DIGLDO_CON30 0x0534
390 +#define MT6323_DIGLDO_CON31 0x0536
391 +#define MT6323_DIGLDO_CON32 0x0538
392 +#define MT6323_DIGLDO_CON33 0x053A
393 +#define MT6323_DIGLDO_CON34 0x053C
394 +#define MT6323_DIGLDO_CON35 0x053E
395 +#define MT6323_DIGLDO_CON36 0x0540
396 +#define MT6323_DIGLDO_CON39 0x0542
397 +#define MT6323_DIGLDO_CON40 0x0544
398 +#define MT6323_DIGLDO_CON41 0x0546
399 +#define MT6323_DIGLDO_CON42 0x0548
400 +#define MT6323_DIGLDO_CON43 0x054A
401 +#define MT6323_DIGLDO_CON44 0x054C
402 +#define MT6323_DIGLDO_CON45 0x054E
403 +#define MT6323_DIGLDO_CON46 0x0550
404 +#define MT6323_DIGLDO_CON47 0x0552
405 +#define MT6323_DIGLDO_CON48 0x0554
406 +#define MT6323_DIGLDO_CON49 0x0556
407 +#define MT6323_DIGLDO_CON50 0x0558
408 +#define MT6323_DIGLDO_CON51 0x055A
409 +#define MT6323_DIGLDO_CON52 0x055C
410 +#define MT6323_DIGLDO_CON53 0x055E
411 +#define MT6323_DIGLDO_CON54 0x0560
412 +#define MT6323_EFUSE_CON0 0x0600
413 +#define MT6323_EFUSE_CON1 0x0602
414 +#define MT6323_EFUSE_CON2 0x0604
415 +#define MT6323_EFUSE_CON3 0x0606
416 +#define MT6323_EFUSE_CON4 0x0608
417 +#define MT6323_EFUSE_CON5 0x060A
418 +#define MT6323_EFUSE_CON6 0x060C
419 +#define MT6323_EFUSE_VAL_0_15 0x060E
420 +#define MT6323_EFUSE_VAL_16_31 0x0610
421 +#define MT6323_EFUSE_VAL_32_47 0x0612
422 +#define MT6323_EFUSE_VAL_48_63 0x0614
423 +#define MT6323_EFUSE_VAL_64_79 0x0616
424 +#define MT6323_EFUSE_VAL_80_95 0x0618
425 +#define MT6323_EFUSE_VAL_96_111 0x061A
426 +#define MT6323_EFUSE_VAL_112_127 0x061C
427 +#define MT6323_EFUSE_VAL_128_143 0x061E
428 +#define MT6323_EFUSE_VAL_144_159 0x0620
429 +#define MT6323_EFUSE_VAL_160_175 0x0622
430 +#define MT6323_EFUSE_VAL_176_191 0x0624
431 +#define MT6323_EFUSE_DOUT_0_15 0x0626
432 +#define MT6323_EFUSE_DOUT_16_31 0x0628
433 +#define MT6323_EFUSE_DOUT_32_47 0x062A
434 +#define MT6323_EFUSE_DOUT_48_63 0x062C
435 +#define MT6323_EFUSE_DOUT_64_79 0x062E
436 +#define MT6323_EFUSE_DOUT_80_95 0x0630
437 +#define MT6323_EFUSE_DOUT_96_111 0x0632
438 +#define MT6323_EFUSE_DOUT_112_127 0x0634
439 +#define MT6323_EFUSE_DOUT_128_143 0x0636
440 +#define MT6323_EFUSE_DOUT_144_159 0x0638
441 +#define MT6323_EFUSE_DOUT_160_175 0x063A
442 +#define MT6323_EFUSE_DOUT_176_191 0x063C
443 +#define MT6323_EFUSE_CON7 0x063E
444 +#define MT6323_EFUSE_CON8 0x0640
445 +#define MT6323_EFUSE_CON9 0x0642
446 +#define MT6323_RTC_MIX_CON0 0x0644
447 +#define MT6323_RTC_MIX_CON1 0x0646
448 +#define MT6323_AUDTOP_CON0 0x0700
449 +#define MT6323_AUDTOP_CON1 0x0702
450 +#define MT6323_AUDTOP_CON2 0x0704
451 +#define MT6323_AUDTOP_CON3 0x0706
452 +#define MT6323_AUDTOP_CON4 0x0708
453 +#define MT6323_AUDTOP_CON5 0x070A
454 +#define MT6323_AUDTOP_CON6 0x070C
455 +#define MT6323_AUDTOP_CON7 0x070E
456 +#define MT6323_AUDTOP_CON8 0x0710
457 +#define MT6323_AUDTOP_CON9 0x0712
458 +#define MT6323_AUXADC_ADC0 0x0714
459 +#define MT6323_AUXADC_ADC1 0x0716
460 +#define MT6323_AUXADC_ADC2 0x0718
461 +#define MT6323_AUXADC_ADC3 0x071A
462 +#define MT6323_AUXADC_ADC4 0x071C
463 +#define MT6323_AUXADC_ADC5 0x071E
464 +#define MT6323_AUXADC_ADC6 0x0720
465 +#define MT6323_AUXADC_ADC7 0x0722
466 +#define MT6323_AUXADC_ADC8 0x0724
467 +#define MT6323_AUXADC_ADC9 0x0726
468 +#define MT6323_AUXADC_ADC10 0x0728
469 +#define MT6323_AUXADC_ADC11 0x072A
470 +#define MT6323_AUXADC_ADC12 0x072C
471 +#define MT6323_AUXADC_ADC13 0x072E
472 +#define MT6323_AUXADC_ADC14 0x0730
473 +#define MT6323_AUXADC_ADC15 0x0732
474 +#define MT6323_AUXADC_ADC16 0x0734
475 +#define MT6323_AUXADC_ADC17 0x0736
476 +#define MT6323_AUXADC_ADC18 0x0738
477 +#define MT6323_AUXADC_ADC19 0x073A
478 +#define MT6323_AUXADC_ADC20 0x073C
479 +#define MT6323_AUXADC_RSV1 0x073E
480 +#define MT6323_AUXADC_RSV2 0x0740
481 +#define MT6323_AUXADC_CON0 0x0742
482 +#define MT6323_AUXADC_CON1 0x0744
483 +#define MT6323_AUXADC_CON2 0x0746
484 +#define MT6323_AUXADC_CON3 0x0748
485 +#define MT6323_AUXADC_CON4 0x074A
486 +#define MT6323_AUXADC_CON5 0x074C
487 +#define MT6323_AUXADC_CON6 0x074E
488 +#define MT6323_AUXADC_CON7 0x0750
489 +#define MT6323_AUXADC_CON8 0x0752
490 +#define MT6323_AUXADC_CON9 0x0754
491 +#define MT6323_AUXADC_CON10 0x0756
492 +#define MT6323_AUXADC_CON11 0x0758
493 +#define MT6323_AUXADC_CON12 0x075A
494 +#define MT6323_AUXADC_CON13 0x075C
495 +#define MT6323_AUXADC_CON14 0x075E
496 +#define MT6323_AUXADC_CON15 0x0760
497 +#define MT6323_AUXADC_CON16 0x0762
498 +#define MT6323_AUXADC_CON17 0x0764
499 +#define MT6323_AUXADC_CON18 0x0766
500 +#define MT6323_AUXADC_CON19 0x0768
501 +#define MT6323_AUXADC_CON20 0x076A
502 +#define MT6323_AUXADC_CON21 0x076C
503 +#define MT6323_AUXADC_CON22 0x076E
504 +#define MT6323_AUXADC_CON23 0x0770
505 +#define MT6323_AUXADC_CON24 0x0772
506 +#define MT6323_AUXADC_CON25 0x0774
507 +#define MT6323_AUXADC_CON26 0x0776
508 +#define MT6323_AUXADC_CON27 0x0778
509 +#define MT6323_ACCDET_CON0 0x077A
510 +#define MT6323_ACCDET_CON1 0x077C
511 +#define MT6323_ACCDET_CON2 0x077E
512 +#define MT6323_ACCDET_CON3 0x0780
513 +#define MT6323_ACCDET_CON4 0x0782
514 +#define MT6323_ACCDET_CON5 0x0784
515 +#define MT6323_ACCDET_CON6 0x0786
516 +#define MT6323_ACCDET_CON7 0x0788
517 +#define MT6323_ACCDET_CON8 0x078A
518 +#define MT6323_ACCDET_CON9 0x078C
519 +#define MT6323_ACCDET_CON10 0x078E
520 +#define MT6323_ACCDET_CON11 0x0790
521 +#define MT6323_ACCDET_CON12 0x0792
522 +#define MT6323_ACCDET_CON13 0x0794
523 +#define MT6323_ACCDET_CON14 0x0796
524 +#define MT6323_ACCDET_CON15 0x0798
525 +#define MT6323_ACCDET_CON16 0x079A
526 +
527 +#endif /* __MFD_MT6323_REGISTERS_H__ */
528 --
529 1.7.10.4
530