mediatek: update patches
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-4.4 / 0048-net-next-mediatek-document-MediaTek-SoC-ethernet-bin.patch
1 From 1e759a179923236660f7f2070fd52e9d2cc09b22 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 2 Mar 2016 07:18:52 +0100
4 Subject: [PATCH 48/91] net-next: mediatek: document MediaTek SoC ethernet
5 binding
6
7 This adds the binding documentation for the MediaTek Ethernet
8 controller.
9
10 Signed-off-by: John Crispin <blogic@openwrt.org>
11 Acked-by: Rob Herring <robh@kernel.org>
12 Cc: devicetree@vger.kernel.org
13 ---
14 .../devicetree/bindings/net/mediatek-net.txt | 77 ++++++++++++++++++++
15 1 file changed, 77 insertions(+)
16 create mode 100644 Documentation/devicetree/bindings/net/mediatek-net.txt
17
18 diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
19 new file mode 100644
20 index 0000000..5ca7929
21 --- /dev/null
22 +++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
23 @@ -0,0 +1,77 @@
24 +MediaTek Frame Engine Ethernet controller
25 +=========================================
26 +
27 +The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
28 +have dual GMAC each represented by a child node..
29 +
30 +* Ethernet controller node
31 +
32 +Required properties:
33 +- compatible: Should be "mediatek,mt7623-eth"
34 +- reg: Address and length of the register set for the device
35 +- interrupts: Should contain the frame engines interrupt
36 +- clocks: the clock used by the core
37 +- clock-names: the names of the clock listed in the clocks property. These are
38 + "ethif", "esw", "gp2", "gp1"
39 +- power-domains: phandle to the power domain that the ethernet is part of
40 +- resets: Should contain a phandle to the ethsys reset signal
41 +- reset-names: Should contain the reset signal name "eth"
42 +- mediatek,ethsys: phandle to the syscon node that handles the port setup
43 +- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
44 + and driver current
45 +
46 +Optional properties:
47 +- interrupt-parent: Should be the phandle for the interrupt controller
48 + that services interrupts for this device
49 +
50 +
51 +* Ethernet MAC node
52 +
53 +Required properties:
54 +- compatible: Should be "mediatek,eth-mac"
55 +- reg: The number of the MAC
56 +- phy-handle: see ethernet.txt file in the same directory.
57 +
58 +Example:
59 +
60 +eth: ethernet@1b100000 {
61 + compatible = "mediatek,mt7623-eth";
62 + reg = <0 0x1b100000 0 0x20000>;
63 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
64 + <&ethsys CLK_ETHSYS_ESW>,
65 + <&ethsys CLK_ETHSYS_GP2>,
66 + <&ethsys CLK_ETHSYS_GP1>;
67 + clock-names = "ethif", "esw", "gp2", "gp1";
68 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
69 + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
70 + resets = <&ethsys MT2701_ETHSYS_ETH_RST>;
71 + reset-names = "eth";
72 + mediatek,ethsys = <&ethsys>;
73 + mediatek,pctl = <&syscfg_pctl_a>;
74 + #address-cells = <1>;
75 + #size-cells = <0>;
76 +
77 + gmac1: mac@0 {
78 + compatible = "mediatek,eth-mac";
79 + reg = <0>;
80 + phy-handle = <&phy0>;
81 + };
82 +
83 + gmac2: mac@1 {
84 + compatible = "mediatek,eth-mac";
85 + reg = <1>;
86 + phy-handle = <&phy1>;
87 + };
88 +
89 + mdio-bus {
90 + phy0: ethernet-phy@0 {
91 + reg = <0>;
92 + phy-mode = "rgmii";
93 + };
94 +
95 + phy1: ethernet-phy@1 {
96 + reg = <1>;
97 + phy-mode = "rgmii";
98 + };
99 + };
100 +};
101 --
102 1.7.10.4
103