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kernel: update 4.1 to 4.1.13
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches / 0005-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8173.patch
1 From 0efcd47787019284a334186fce134ee475c79211 Mon Sep 17 00:00:00 2001
2 From: James Liao <jamesjj.liao@mediatek.com>
3 Date: Thu, 23 Apr 2015 10:35:42 +0200
4 Subject: [PATCH 05/76] clk: mediatek: Add basic clocks for Mediatek MT8173.
5
6 This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs,
7 INFRA and PERI clocks.
8
9 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
10 Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
11 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
12 ---
13 drivers/clk/mediatek/Makefile | 1 +
14 drivers/clk/mediatek/clk-mt8173.c | 830 ++++++++++++++++++++
15 include/dt-bindings/clock/mt8173-clk.h | 235 ++++++
16 .../dt-bindings/reset-controller/mt8173-resets.h | 63 ++
17 4 files changed, 1129 insertions(+)
18 create mode 100644 drivers/clk/mediatek/clk-mt8173.c
19 create mode 100644 include/dt-bindings/clock/mt8173-clk.h
20 create mode 100644 include/dt-bindings/reset-controller/mt8173-resets.h
21
22 --- a/drivers/clk/mediatek/Makefile
23 +++ b/drivers/clk/mediatek/Makefile
24 @@ -1,3 +1,4 @@
25 obj-y += clk-mtk.o clk-pll.o clk-gate.o
26 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
27 obj-y += clk-mt8135.o
28 +obj-y += clk-mt8173.o
29 --- /dev/null
30 +++ b/drivers/clk/mediatek/clk-mt8173.c
31 @@ -0,0 +1,830 @@
32 +/*
33 + * Copyright (c) 2014 MediaTek Inc.
34 + * Author: James Liao <jamesjj.liao@mediatek.com>
35 + *
36 + * This program is free software; you can redistribute it and/or modify
37 + * it under the terms of the GNU General Public License version 2 as
38 + * published by the Free Software Foundation.
39 + *
40 + * This program is distributed in the hope that it will be useful,
41 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
42 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 + * GNU General Public License for more details.
44 + */
45 +
46 +#include <linux/of.h>
47 +#include <linux/of_address.h>
48 +#include <linux/slab.h>
49 +#include <linux/mfd/syscon.h>
50 +
51 +#include "clk-mtk.h"
52 +#include "clk-gate.h"
53 +
54 +#include <dt-bindings/clock/mt8173-clk.h>
55 +
56 +static DEFINE_SPINLOCK(mt8173_clk_lock);
57 +
58 +static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
59 + FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1),
60 + FACTOR(CLK_TOP_DPI, "dpi_ck", "clk_null", 1, 1),
61 + FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1),
62 + FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1),
63 +};
64 +
65 +static const struct mtk_fixed_factor top_divs[] __initconst = {
66 + FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
67 + FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
68 +
69 + FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
70 + FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
71 + FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
72 + FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
73 +
74 + FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
75 + FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
76 +
77 + FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
78 + FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
79 + FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
80 + FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
81 + FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
82 +
83 + FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
84 + FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
85 + FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
86 +
87 + FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
88 + FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
89 +
90 + FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
91 + FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
92 +
93 + FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
94 + FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
95 +
96 + FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
97 + FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
98 + FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
99 + FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
100 + FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
101 +
102 + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
103 + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
104 + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
105 +
106 + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
107 + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
108 +
109 + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
110 + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
111 + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
112 + FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
113 + FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
114 + FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
115 +
116 + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
117 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
118 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
119 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
120 + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
121 + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
122 + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
123 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
124 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
125 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
126 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
127 + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
128 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
129 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
130 +
131 + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
132 + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
133 + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
134 + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
135 + FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
136 +
137 + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
138 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
139 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
140 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
141 + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
142 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
143 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
144 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
145 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
146 + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
147 + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
148 + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
149 + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
150 + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
151 + FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
152 +
153 + FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
154 + FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
155 +
156 + FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
157 + FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
158 + FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
159 +};
160 +
161 +static const char * const axi_parents[] __initconst = {
162 + "clk26m",
163 + "syspll1_d2",
164 + "syspll_d5",
165 + "syspll1_d4",
166 + "univpll_d5",
167 + "univpll2_d2",
168 + "dmpll_d2",
169 + "dmpll_d4"
170 +};
171 +
172 +static const char * const mem_parents[] __initconst = {
173 + "clk26m",
174 + "dmpll_ck"
175 +};
176 +
177 +static const char * const ddrphycfg_parents[] __initconst = {
178 + "clk26m",
179 + "syspll1_d8"
180 +};
181 +
182 +static const char * const mm_parents[] __initconst = {
183 + "clk26m",
184 + "vencpll_d2",
185 + "main_h364m",
186 + "syspll1_d2",
187 + "syspll_d5",
188 + "syspll1_d4",
189 + "univpll1_d2",
190 + "univpll2_d2",
191 + "dmpll_d2"
192 +};
193 +
194 +static const char * const pwm_parents[] __initconst = {
195 + "clk26m",
196 + "univpll2_d4",
197 + "univpll3_d2",
198 + "univpll1_d4"
199 +};
200 +
201 +static const char * const vdec_parents[] __initconst = {
202 + "clk26m",
203 + "vcodecpll_ck",
204 + "tvdpll_445p5m",
205 + "univpll_d3",
206 + "vencpll_d2",
207 + "syspll_d3",
208 + "univpll1_d2",
209 + "mmpll_d2",
210 + "dmpll_d2",
211 + "dmpll_d4"
212 +};
213 +
214 +static const char * const venc_parents[] __initconst = {
215 + "clk26m",
216 + "vcodecpll_ck",
217 + "tvdpll_445p5m",
218 + "univpll_d3",
219 + "vencpll_d2",
220 + "syspll_d3",
221 + "univpll1_d2",
222 + "univpll2_d2",
223 + "dmpll_d2",
224 + "dmpll_d4"
225 +};
226 +
227 +static const char * const mfg_parents[] __initconst = {
228 + "clk26m",
229 + "mmpll_ck",
230 + "dmpll_ck",
231 + "clk26m",
232 + "clk26m",
233 + "clk26m",
234 + "clk26m",
235 + "clk26m",
236 + "clk26m",
237 + "syspll_d3",
238 + "syspll1_d2",
239 + "syspll_d5",
240 + "univpll_d3",
241 + "univpll1_d2",
242 + "univpll_d5",
243 + "univpll2_d2"
244 +};
245 +
246 +static const char * const camtg_parents[] __initconst = {
247 + "clk26m",
248 + "univpll_d26",
249 + "univpll2_d2",
250 + "syspll3_d2",
251 + "syspll3_d4",
252 + "univpll1_d4"
253 +};
254 +
255 +static const char * const uart_parents[] __initconst = {
256 + "clk26m",
257 + "univpll2_d8"
258 +};
259 +
260 +static const char * const spi_parents[] __initconst = {
261 + "clk26m",
262 + "syspll3_d2",
263 + "syspll1_d4",
264 + "syspll4_d2",
265 + "univpll3_d2",
266 + "univpll2_d4",
267 + "univpll1_d8"
268 +};
269 +
270 +static const char * const usb20_parents[] __initconst = {
271 + "clk26m",
272 + "univpll1_d8",
273 + "univpll3_d4"
274 +};
275 +
276 +static const char * const usb30_parents[] __initconst = {
277 + "clk26m",
278 + "univpll3_d2",
279 + "usb_syspll_125m",
280 + "univpll2_d4"
281 +};
282 +
283 +static const char * const msdc50_0_h_parents[] __initconst = {
284 + "clk26m",
285 + "syspll1_d2",
286 + "syspll2_d2",
287 + "syspll4_d2",
288 + "univpll_d5",
289 + "univpll1_d4"
290 +};
291 +
292 +static const char * const msdc50_0_parents[] __initconst = {
293 + "clk26m",
294 + "msdcpll_ck",
295 + "msdcpll_d2",
296 + "univpll1_d4",
297 + "syspll2_d2",
298 + "syspll_d7",
299 + "msdcpll_d4",
300 + "vencpll_d4",
301 + "tvdpll_ck",
302 + "univpll_d2",
303 + "univpll1_d2",
304 + "mmpll_ck",
305 + "msdcpll2_ck",
306 + "msdcpll2_d2",
307 + "msdcpll2_d4"
308 +};
309 +
310 +static const char * const msdc30_1_parents[] __initconst = {
311 + "clk26m",
312 + "univpll2_d2",
313 + "msdcpll_d4",
314 + "univpll1_d4",
315 + "syspll2_d2",
316 + "syspll_d7",
317 + "univpll_d7",
318 + "vencpll_d4"
319 +};
320 +
321 +static const char * const msdc30_2_parents[] __initconst = {
322 + "clk26m",
323 + "univpll2_d2",
324 + "msdcpll_d4",
325 + "univpll1_d4",
326 + "syspll2_d2",
327 + "syspll_d7",
328 + "univpll_d7",
329 + "vencpll_d2"
330 +};
331 +
332 +static const char * const msdc30_3_parents[] __initconst = {
333 + "clk26m",
334 + "msdcpll2_ck",
335 + "msdcpll2_d2",
336 + "univpll2_d2",
337 + "msdcpll2_d4",
338 + "msdcpll_d4",
339 + "univpll1_d4",
340 + "syspll2_d2",
341 + "syspll_d7",
342 + "univpll_d7",
343 + "vencpll_d4",
344 + "msdcpll_ck",
345 + "msdcpll_d2",
346 + "msdcpll_d4"
347 +};
348 +
349 +static const char * const audio_parents[] __initconst = {
350 + "clk26m",
351 + "syspll3_d4",
352 + "syspll4_d4",
353 + "syspll1_d16"
354 +};
355 +
356 +static const char * const aud_intbus_parents[] __initconst = {
357 + "clk26m",
358 + "syspll1_d4",
359 + "syspll4_d2",
360 + "univpll3_d2",
361 + "univpll2_d8",
362 + "dmpll_d4",
363 + "dmpll_d8"
364 +};
365 +
366 +static const char * const pmicspi_parents[] __initconst = {
367 + "clk26m",
368 + "syspll1_d8",
369 + "syspll3_d4",
370 + "syspll1_d16",
371 + "univpll3_d4",
372 + "univpll_d26",
373 + "dmpll_d8",
374 + "dmpll_d16"
375 +};
376 +
377 +static const char * const scp_parents[] __initconst = {
378 + "clk26m",
379 + "syspll1_d2",
380 + "univpll_d5",
381 + "syspll_d5",
382 + "dmpll_d2",
383 + "dmpll_d4"
384 +};
385 +
386 +static const char * const atb_parents[] __initconst = {
387 + "clk26m",
388 + "syspll1_d2",
389 + "univpll_d5",
390 + "dmpll_d2"
391 +};
392 +
393 +static const char * const venc_lt_parents[] __initconst = {
394 + "clk26m",
395 + "univpll_d3",
396 + "vcodecpll_ck",
397 + "tvdpll_445p5m",
398 + "vencpll_d2",
399 + "syspll_d3",
400 + "univpll1_d2",
401 + "univpll2_d2",
402 + "syspll1_d2",
403 + "univpll_d5",
404 + "vcodecpll_370p5",
405 + "dmpll_ck"
406 +};
407 +
408 +static const char * const dpi0_parents[] __initconst = {
409 + "clk26m",
410 + "tvdpll_d2",
411 + "tvdpll_d4",
412 + "clk26m",
413 + "clk26m",
414 + "tvdpll_d8",
415 + "tvdpll_d16"
416 +};
417 +
418 +static const char * const irda_parents[] __initconst = {
419 + "clk26m",
420 + "univpll2_d4",
421 + "syspll2_d4"
422 +};
423 +
424 +static const char * const cci400_parents[] __initconst = {
425 + "clk26m",
426 + "vencpll_ck",
427 + "armca7pll_754m",
428 + "armca7pll_502m",
429 + "univpll_d2",
430 + "syspll_d2",
431 + "msdcpll_ck",
432 + "dmpll_ck"
433 +};
434 +
435 +static const char * const aud_1_parents[] __initconst = {
436 + "clk26m",
437 + "apll1_ck",
438 + "univpll2_d4",
439 + "univpll2_d8"
440 +};
441 +
442 +static const char * const aud_2_parents[] __initconst = {
443 + "clk26m",
444 + "apll2_ck",
445 + "univpll2_d4",
446 + "univpll2_d8"
447 +};
448 +
449 +static const char * const mem_mfg_in_parents[] __initconst = {
450 + "clk26m",
451 + "mmpll_ck",
452 + "dmpll_ck",
453 + "clk26m"
454 +};
455 +
456 +static const char * const axi_mfg_in_parents[] __initconst = {
457 + "clk26m",
458 + "axi_sel",
459 + "dmpll_d2"
460 +};
461 +
462 +static const char * const scam_parents[] __initconst = {
463 + "clk26m",
464 + "syspll3_d2",
465 + "univpll2_d4",
466 + "dmpll_d4"
467 +};
468 +
469 +static const char * const spinfi_ifr_parents[] __initconst = {
470 + "clk26m",
471 + "univpll2_d8",
472 + "univpll3_d4",
473 + "syspll4_d2",
474 + "univpll2_d4",
475 + "univpll3_d2",
476 + "syspll1_d4",
477 + "univpll1_d4"
478 +};
479 +
480 +static const char * const hdmi_parents[] __initconst = {
481 + "clk26m",
482 + "hdmitx_dig_cts",
483 + "hdmitxpll_d2",
484 + "hdmitxpll_d3"
485 +};
486 +
487 +static const char * const dpilvds_parents[] __initconst = {
488 + "clk26m",
489 + "lvdspll",
490 + "lvdspll_d2",
491 + "lvdspll_d4",
492 + "lvdspll_d8",
493 + "fpc_ck"
494 +};
495 +
496 +static const char * const msdc50_2_h_parents[] __initconst = {
497 + "clk26m",
498 + "syspll1_d2",
499 + "syspll2_d2",
500 + "syspll4_d2",
501 + "univpll_d5",
502 + "univpll1_d4"
503 +};
504 +
505 +static const char * const hdcp_parents[] __initconst = {
506 + "clk26m",
507 + "syspll4_d2",
508 + "syspll3_d4",
509 + "univpll2_d4"
510 +};
511 +
512 +static const char * const hdcp_24m_parents[] __initconst = {
513 + "clk26m",
514 + "univpll_d26",
515 + "univpll_d52",
516 + "univpll2_d8"
517 +};
518 +
519 +static const char * const rtc_parents[] __initconst = {
520 + "clkrtc_int",
521 + "clkrtc_ext",
522 + "clk26m",
523 + "univpll3_d8"
524 +};
525 +
526 +static const char * const i2s0_m_ck_parents[] __initconst = {
527 + "apll1_div1",
528 + "apll2_div1"
529 +};
530 +
531 +static const char * const i2s1_m_ck_parents[] __initconst = {
532 + "apll1_div2",
533 + "apll2_div2"
534 +};
535 +
536 +static const char * const i2s2_m_ck_parents[] __initconst = {
537 + "apll1_div3",
538 + "apll2_div3"
539 +};
540 +
541 +static const char * const i2s3_m_ck_parents[] __initconst = {
542 + "apll1_div4",
543 + "apll2_div4"
544 +};
545 +
546 +static const char * const i2s3_b_ck_parents[] __initconst = {
547 + "apll1_div5",
548 + "apll2_div5"
549 +};
550 +
551 +static const struct mtk_composite top_muxes[] __initconst = {
552 + /* CLK_CFG_0 */
553 + MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
554 + MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
555 + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
556 + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
557 + /* CLK_CFG_1 */
558 + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
559 + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
560 + MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
561 + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
562 + /* CLK_CFG_2 */
563 + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
564 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
565 + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
566 + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
567 + /* CLK_CFG_3 */
568 + MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
569 + MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
570 + MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
571 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
572 + /* CLK_CFG_4 */
573 + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
574 + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15),
575 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23),
576 + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
577 + /* CLK_CFG_5 */
578 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */),
579 + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
580 + MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
581 + MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
582 + /* CLK_CFG_6 */
583 + MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
584 + MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
585 + MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
586 + MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
587 + /* CLK_CFG_7 */
588 + MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
589 + MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15),
590 + MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23),
591 + MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
592 + /* CLK_CFG_12 */
593 + MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
594 + MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
595 + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
596 + /* CLK_CFG_13 */
597 + MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
598 + MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
599 + MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23),
600 + MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
601 +
602 + DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
603 + DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
604 + DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
605 + DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
606 + DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
607 + DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
608 +
609 + DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
610 + DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
611 + DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
612 + DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
613 + DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
614 + DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
615 +
616 + MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
617 + MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
618 + MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
619 + MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
620 + MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
621 +};
622 +
623 +static const struct mtk_gate_regs infra_cg_regs = {
624 + .set_ofs = 0x0040,
625 + .clr_ofs = 0x0044,
626 + .sta_ofs = 0x0048,
627 +};
628 +
629 +#define GATE_ICG(_id, _name, _parent, _shift) { \
630 + .id = _id, \
631 + .name = _name, \
632 + .parent_name = _parent, \
633 + .regs = &infra_cg_regs, \
634 + .shift = _shift, \
635 + .ops = &mtk_clk_gate_ops_setclr, \
636 + }
637 +
638 +static const struct mtk_gate infra_clks[] __initconst = {
639 + GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
640 + GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
641 + GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
642 + GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
643 + GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
644 + GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
645 + GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "clk_null", 15),
646 + GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
647 + GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
648 + GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
649 + GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
650 +};
651 +
652 +static const struct mtk_gate_regs peri0_cg_regs = {
653 + .set_ofs = 0x0008,
654 + .clr_ofs = 0x0010,
655 + .sta_ofs = 0x0018,
656 +};
657 +
658 +static const struct mtk_gate_regs peri1_cg_regs = {
659 + .set_ofs = 0x000c,
660 + .clr_ofs = 0x0014,
661 + .sta_ofs = 0x001c,
662 +};
663 +
664 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
665 + .id = _id, \
666 + .name = _name, \
667 + .parent_name = _parent, \
668 + .regs = &peri0_cg_regs, \
669 + .shift = _shift, \
670 + .ops = &mtk_clk_gate_ops_setclr, \
671 + }
672 +
673 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
674 + .id = _id, \
675 + .name = _name, \
676 + .parent_name = _parent, \
677 + .regs = &peri1_cg_regs, \
678 + .shift = _shift, \
679 + .ops = &mtk_clk_gate_ops_setclr, \
680 + }
681 +
682 +static const struct mtk_gate peri_gates[] __initconst = {
683 + /* PERI0 */
684 + GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
685 + GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
686 + GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
687 + GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
688 + GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
689 + GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
690 + GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
691 + GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
692 + GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
693 + GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
694 + GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
695 + GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
696 + GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
697 + GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
698 + GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
699 + GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
700 + GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
701 + GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
702 + GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
703 + GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
704 + GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
705 + GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
706 + GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
707 + GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
708 + GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
709 + GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
710 + GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
711 + GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
712 + GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
713 + GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
714 + GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
715 + GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
716 + /* PERI1 */
717 + GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
718 + GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
719 + GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
720 +};
721 +
722 +static const char * const uart_ck_sel_parents[] __initconst = {
723 + "clk26m",
724 + "uart_sel",
725 +};
726 +
727 +static const struct mtk_composite peri_clks[] __initconst = {
728 + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
729 + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
730 + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
731 + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
732 +};
733 +
734 +static void __init mtk_topckgen_init(struct device_node *node)
735 +{
736 + struct clk_onecell_data *clk_data;
737 + void __iomem *base;
738 + int r;
739 +
740 + base = of_iomap(node, 0);
741 + if (!base) {
742 + pr_err("%s(): ioremap failed\n", __func__);
743 + return;
744 + }
745 +
746 + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
747 +
748 + mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
749 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
750 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
751 + &mt8173_clk_lock, clk_data);
752 +
753 + clk_prepare_enable(clk_data->clks[CLK_TOP_CCI400_SEL]);
754 +
755 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
756 + if (r)
757 + pr_err("%s(): could not register clock provider: %d\n",
758 + __func__, r);
759 +}
760 +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
761 +
762 +static void __init mtk_infrasys_init(struct device_node *node)
763 +{
764 + struct clk_onecell_data *clk_data;
765 + int r;
766 +
767 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
768 +
769 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
770 + clk_data);
771 +
772 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
773 + if (r)
774 + pr_err("%s(): could not register clock provider: %d\n",
775 + __func__, r);
776 +
777 + mtk_register_reset_controller(node, 2, 0x30);
778 +}
779 +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
780 +
781 +static void __init mtk_pericfg_init(struct device_node *node)
782 +{
783 + struct clk_onecell_data *clk_data;
784 + int r;
785 + void __iomem *base;
786 +
787 + base = of_iomap(node, 0);
788 + if (!base) {
789 + pr_err("%s(): ioremap failed\n", __func__);
790 + return;
791 + }
792 +
793 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
794 +
795 + mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
796 + clk_data);
797 + mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
798 + &mt8173_clk_lock, clk_data);
799 +
800 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
801 + if (r)
802 + pr_err("%s(): could not register clock provider: %d\n",
803 + __func__, r);
804 +
805 + mtk_register_reset_controller(node, 2, 0);
806 +}
807 +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
808 +
809 +#define MT8173_PLL_FMAX (3000UL * MHZ)
810 +
811 +#define CON0_MT8173_RST_BAR BIT(24)
812 +
813 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, \
814 + _tuner_reg, _pcw_reg, _pcw_shift) { \
815 + .id = _id, \
816 + .name = _name, \
817 + .reg = _reg, \
818 + .pwr_reg = _pwr_reg, \
819 + .en_mask = _en_mask, \
820 + .flags = _flags, \
821 + .rst_bar_mask = CON0_MT8173_RST_BAR, \
822 + .fmax = MT8173_PLL_FMAX, \
823 + .pcwbits = _pcwbits, \
824 + .pd_reg = _pd_reg, \
825 + .pd_shift = _pd_shift, \
826 + .tuner_reg = _tuner_reg, \
827 + .pcw_reg = _pcw_reg, \
828 + .pcw_shift = _pcw_shift, \
829 + }
830 +
831 +static const struct mtk_pll_data plls[] = {
832 + PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
833 + PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
834 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
835 + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
836 + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0),
837 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
838 + PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
839 + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
840 + PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
841 + PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
842 + PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
843 + PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
844 + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
845 + PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
846 +};
847 +
848 +static void __init mtk_apmixedsys_init(struct device_node *node)
849 +{
850 + struct clk_onecell_data *clk_data;
851 +
852 + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
853 + if (!clk_data)
854 + return;
855 +
856 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
857 +
858 + clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
859 +}
860 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
861 + mtk_apmixedsys_init);
862 --- /dev/null
863 +++ b/include/dt-bindings/clock/mt8173-clk.h
864 @@ -0,0 +1,235 @@
865 +/*
866 + * Copyright (c) 2014 MediaTek Inc.
867 + * Author: James Liao <jamesjj.liao@mediatek.com>
868 + *
869 + * This program is free software; you can redistribute it and/or modify
870 + * it under the terms of the GNU General Public License version 2 as
871 + * published by the Free Software Foundation.
872 + *
873 + * This program is distributed in the hope that it will be useful,
874 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
875 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
876 + * GNU General Public License for more details.
877 + */
878 +
879 +#ifndef _DT_BINDINGS_CLK_MT8173_H
880 +#define _DT_BINDINGS_CLK_MT8173_H
881 +
882 +/* TOPCKGEN */
883 +
884 +#define CLK_TOP_CLKPH_MCK_O 1
885 +#define CLK_TOP_DPI 2
886 +#define CLK_TOP_USB_SYSPLL_125M 3
887 +#define CLK_TOP_HDMITX_DIG_CTS 4
888 +#define CLK_TOP_ARMCA7PLL_754M 5
889 +#define CLK_TOP_ARMCA7PLL_502M 6
890 +#define CLK_TOP_MAIN_H546M 7
891 +#define CLK_TOP_MAIN_H364M 8
892 +#define CLK_TOP_MAIN_H218P4M 9
893 +#define CLK_TOP_MAIN_H156M 10
894 +#define CLK_TOP_TVDPLL_445P5M 11
895 +#define CLK_TOP_TVDPLL_594M 12
896 +#define CLK_TOP_UNIV_624M 13
897 +#define CLK_TOP_UNIV_416M 14
898 +#define CLK_TOP_UNIV_249P6M 15
899 +#define CLK_TOP_UNIV_178P3M 16
900 +#define CLK_TOP_UNIV_48M 17
901 +#define CLK_TOP_CLKRTC_EXT 18
902 +#define CLK_TOP_CLKRTC_INT 19
903 +#define CLK_TOP_FPC 20
904 +#define CLK_TOP_HDMITXPLL_D2 21
905 +#define CLK_TOP_HDMITXPLL_D3 22
906 +#define CLK_TOP_ARMCA7PLL_D2 23
907 +#define CLK_TOP_ARMCA7PLL_D3 24
908 +#define CLK_TOP_APLL1 25
909 +#define CLK_TOP_APLL2 26
910 +#define CLK_TOP_DMPLL 27
911 +#define CLK_TOP_DMPLL_D2 28
912 +#define CLK_TOP_DMPLL_D4 29
913 +#define CLK_TOP_DMPLL_D8 30
914 +#define CLK_TOP_DMPLL_D16 31
915 +#define CLK_TOP_LVDSPLL_D2 32
916 +#define CLK_TOP_LVDSPLL_D4 33
917 +#define CLK_TOP_LVDSPLL_D8 34
918 +#define CLK_TOP_MMPLL 35
919 +#define CLK_TOP_MMPLL_D2 36
920 +#define CLK_TOP_MSDCPLL 37
921 +#define CLK_TOP_MSDCPLL_D2 38
922 +#define CLK_TOP_MSDCPLL_D4 39
923 +#define CLK_TOP_MSDCPLL2 40
924 +#define CLK_TOP_MSDCPLL2_D2 41
925 +#define CLK_TOP_MSDCPLL2_D4 42
926 +#define CLK_TOP_SYSPLL_D2 43
927 +#define CLK_TOP_SYSPLL1_D2 44
928 +#define CLK_TOP_SYSPLL1_D4 45
929 +#define CLK_TOP_SYSPLL1_D8 46
930 +#define CLK_TOP_SYSPLL1_D16 47
931 +#define CLK_TOP_SYSPLL_D3 48
932 +#define CLK_TOP_SYSPLL2_D2 49
933 +#define CLK_TOP_SYSPLL2_D4 50
934 +#define CLK_TOP_SYSPLL_D5 51
935 +#define CLK_TOP_SYSPLL3_D2 52
936 +#define CLK_TOP_SYSPLL3_D4 53
937 +#define CLK_TOP_SYSPLL_D7 54
938 +#define CLK_TOP_SYSPLL4_D2 55
939 +#define CLK_TOP_SYSPLL4_D4 56
940 +#define CLK_TOP_TVDPLL 57
941 +#define CLK_TOP_TVDPLL_D2 58
942 +#define CLK_TOP_TVDPLL_D4 59
943 +#define CLK_TOP_TVDPLL_D8 60
944 +#define CLK_TOP_TVDPLL_D16 61
945 +#define CLK_TOP_UNIVPLL_D2 62
946 +#define CLK_TOP_UNIVPLL1_D2 63
947 +#define CLK_TOP_UNIVPLL1_D4 64
948 +#define CLK_TOP_UNIVPLL1_D8 65
949 +#define CLK_TOP_UNIVPLL_D3 66
950 +#define CLK_TOP_UNIVPLL2_D2 67
951 +#define CLK_TOP_UNIVPLL2_D4 68
952 +#define CLK_TOP_UNIVPLL2_D8 69
953 +#define CLK_TOP_UNIVPLL_D5 70
954 +#define CLK_TOP_UNIVPLL3_D2 71
955 +#define CLK_TOP_UNIVPLL3_D4 72
956 +#define CLK_TOP_UNIVPLL3_D8 73
957 +#define CLK_TOP_UNIVPLL_D7 74
958 +#define CLK_TOP_UNIVPLL_D26 75
959 +#define CLK_TOP_UNIVPLL_D52 76
960 +#define CLK_TOP_VCODECPLL 77
961 +#define CLK_TOP_VCODECPLL_370P5 78
962 +#define CLK_TOP_VENCPLL 79
963 +#define CLK_TOP_VENCPLL_D2 80
964 +#define CLK_TOP_VENCPLL_D4 81
965 +#define CLK_TOP_AXI_SEL 82
966 +#define CLK_TOP_MEM_SEL 83
967 +#define CLK_TOP_DDRPHYCFG_SEL 84
968 +#define CLK_TOP_MM_SEL 85
969 +#define CLK_TOP_PWM_SEL 86
970 +#define CLK_TOP_VDEC_SEL 87
971 +#define CLK_TOP_VENC_SEL 88
972 +#define CLK_TOP_MFG_SEL 89
973 +#define CLK_TOP_CAMTG_SEL 90
974 +#define CLK_TOP_UART_SEL 91
975 +#define CLK_TOP_SPI_SEL 92
976 +#define CLK_TOP_USB20_SEL 93
977 +#define CLK_TOP_USB30_SEL 94
978 +#define CLK_TOP_MSDC50_0_H_SEL 95
979 +#define CLK_TOP_MSDC50_0_SEL 96
980 +#define CLK_TOP_MSDC30_1_SEL 97
981 +#define CLK_TOP_MSDC30_2_SEL 98
982 +#define CLK_TOP_MSDC30_3_SEL 99
983 +#define CLK_TOP_AUDIO_SEL 100
984 +#define CLK_TOP_AUD_INTBUS_SEL 101
985 +#define CLK_TOP_PMICSPI_SEL 102
986 +#define CLK_TOP_SCP_SEL 103
987 +#define CLK_TOP_ATB_SEL 104
988 +#define CLK_TOP_VENC_LT_SEL 105
989 +#define CLK_TOP_DPI0_SEL 106
990 +#define CLK_TOP_IRDA_SEL 107
991 +#define CLK_TOP_CCI400_SEL 108
992 +#define CLK_TOP_AUD_1_SEL 109
993 +#define CLK_TOP_AUD_2_SEL 110
994 +#define CLK_TOP_MEM_MFG_IN_SEL 111
995 +#define CLK_TOP_AXI_MFG_IN_SEL 112
996 +#define CLK_TOP_SCAM_SEL 113
997 +#define CLK_TOP_SPINFI_IFR_SEL 114
998 +#define CLK_TOP_HDMI_SEL 115
999 +#define CLK_TOP_DPILVDS_SEL 116
1000 +#define CLK_TOP_MSDC50_2_H_SEL 117
1001 +#define CLK_TOP_HDCP_SEL 118
1002 +#define CLK_TOP_HDCP_24M_SEL 119
1003 +#define CLK_TOP_RTC_SEL 120
1004 +#define CLK_TOP_APLL1_DIV0 121
1005 +#define CLK_TOP_APLL1_DIV1 122
1006 +#define CLK_TOP_APLL1_DIV2 123
1007 +#define CLK_TOP_APLL1_DIV3 124
1008 +#define CLK_TOP_APLL1_DIV4 125
1009 +#define CLK_TOP_APLL1_DIV5 126
1010 +#define CLK_TOP_APLL2_DIV0 127
1011 +#define CLK_TOP_APLL2_DIV1 128
1012 +#define CLK_TOP_APLL2_DIV2 129
1013 +#define CLK_TOP_APLL2_DIV3 130
1014 +#define CLK_TOP_APLL2_DIV4 131
1015 +#define CLK_TOP_APLL2_DIV5 132
1016 +#define CLK_TOP_I2S0_M_SEL 133
1017 +#define CLK_TOP_I2S1_M_SEL 134
1018 +#define CLK_TOP_I2S2_M_SEL 135
1019 +#define CLK_TOP_I2S3_M_SEL 136
1020 +#define CLK_TOP_I2S3_B_SEL 137
1021 +#define CLK_TOP_NR_CLK 138
1022 +
1023 +/* APMIXED_SYS */
1024 +
1025 +#define CLK_APMIXED_ARMCA15PLL 1
1026 +#define CLK_APMIXED_ARMCA7PLL 2
1027 +#define CLK_APMIXED_MAINPLL 3
1028 +#define CLK_APMIXED_UNIVPLL 4
1029 +#define CLK_APMIXED_MMPLL 5
1030 +#define CLK_APMIXED_MSDCPLL 6
1031 +#define CLK_APMIXED_VENCPLL 7
1032 +#define CLK_APMIXED_TVDPLL 8
1033 +#define CLK_APMIXED_MPLL 9
1034 +#define CLK_APMIXED_VCODECPLL 10
1035 +#define CLK_APMIXED_APLL1 11
1036 +#define CLK_APMIXED_APLL2 12
1037 +#define CLK_APMIXED_LVDSPLL 13
1038 +#define CLK_APMIXED_MSDCPLL2 14
1039 +#define CLK_APMIXED_NR_CLK 15
1040 +
1041 +/* INFRA_SYS */
1042 +
1043 +#define CLK_INFRA_DBGCLK 1
1044 +#define CLK_INFRA_SMI 2
1045 +#define CLK_INFRA_AUDIO 3
1046 +#define CLK_INFRA_GCE 4
1047 +#define CLK_INFRA_L2C_SRAM 5
1048 +#define CLK_INFRA_M4U 6
1049 +#define CLK_INFRA_CPUM 7
1050 +#define CLK_INFRA_KP 8
1051 +#define CLK_INFRA_CEC 9
1052 +#define CLK_INFRA_PMICSPI 10
1053 +#define CLK_INFRA_PMICWRAP 11
1054 +#define CLK_INFRA_NR_CLK 12
1055 +
1056 +/* PERI_SYS */
1057 +
1058 +#define CLK_PERI_NFI 1
1059 +#define CLK_PERI_THERM 2
1060 +#define CLK_PERI_PWM1 3
1061 +#define CLK_PERI_PWM2 4
1062 +#define CLK_PERI_PWM3 5
1063 +#define CLK_PERI_PWM4 6
1064 +#define CLK_PERI_PWM5 7
1065 +#define CLK_PERI_PWM6 8
1066 +#define CLK_PERI_PWM7 9
1067 +#define CLK_PERI_PWM 10
1068 +#define CLK_PERI_USB0 11
1069 +#define CLK_PERI_USB1 12
1070 +#define CLK_PERI_AP_DMA 13
1071 +#define CLK_PERI_MSDC30_0 14
1072 +#define CLK_PERI_MSDC30_1 15
1073 +#define CLK_PERI_MSDC30_2 16
1074 +#define CLK_PERI_MSDC30_3 17
1075 +#define CLK_PERI_NLI_ARB 18
1076 +#define CLK_PERI_IRDA 19
1077 +#define CLK_PERI_UART0 20
1078 +#define CLK_PERI_UART1 21
1079 +#define CLK_PERI_UART2 22
1080 +#define CLK_PERI_UART3 23
1081 +#define CLK_PERI_I2C0 24
1082 +#define CLK_PERI_I2C1 25
1083 +#define CLK_PERI_I2C2 26
1084 +#define CLK_PERI_I2C3 27
1085 +#define CLK_PERI_I2C4 28
1086 +#define CLK_PERI_AUXADC 29
1087 +#define CLK_PERI_SPI0 30
1088 +#define CLK_PERI_I2C5 31
1089 +#define CLK_PERI_NFIECC 32
1090 +#define CLK_PERI_SPI 33
1091 +#define CLK_PERI_IRRX 34
1092 +#define CLK_PERI_I2C6 35
1093 +#define CLK_PERI_UART0_SEL 36
1094 +#define CLK_PERI_UART1_SEL 37
1095 +#define CLK_PERI_UART2_SEL 38
1096 +#define CLK_PERI_UART3_SEL 39
1097 +#define CLK_PERI_NR_CLK 40
1098 +
1099 +#endif /* _DT_BINDINGS_CLK_MT8173_H */
1100 --- /dev/null
1101 +++ b/include/dt-bindings/reset-controller/mt8173-resets.h
1102 @@ -0,0 +1,63 @@
1103 +/*
1104 + * Copyright (c) 2014 MediaTek Inc.
1105 + * Author: Flora Fu, MediaTek
1106 + *
1107 + * This program is free software; you can redistribute it and/or modify
1108 + * it under the terms of the GNU General Public License version 2 as
1109 + * published by the Free Software Foundation.
1110 + *
1111 + * This program is distributed in the hope that it will be useful,
1112 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1113 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1114 + * GNU General Public License for more details.
1115 + */
1116 +
1117 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173
1118 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8173
1119 +
1120 +/* INFRACFG resets */
1121 +#define MT8173_INFRA_EMI_REG_RST 0
1122 +#define MT8173_INFRA_DRAMC0_A0_RST 1
1123 +#define MT8173_INFRA_APCIRQ_EINT_RST 3
1124 +#define MT8173_INFRA_APXGPT_RST 4
1125 +#define MT8173_INFRA_SCPSYS_RST 5
1126 +#define MT8173_INFRA_KP_RST 6
1127 +#define MT8173_INFRA_PMIC_WRAP_RST 7
1128 +#define MT8173_INFRA_MPIP_RST 8
1129 +#define MT8173_INFRA_CEC_RST 9
1130 +#define MT8173_INFRA_EMI_RST 32
1131 +#define MT8173_INFRA_DRAMC0_RST 34
1132 +#define MT8173_INFRA_APMIXEDSYS_RST 35
1133 +#define MT8173_INFRA_MIPI_DSI_RST 36
1134 +#define MT8173_INFRA_TRNG_RST 37
1135 +#define MT8173_INFRA_SYSIRQ_RST 38
1136 +#define MT8173_INFRA_MIPI_CSI_RST 39
1137 +#define MT8173_INFRA_GCE_FAXI_RST 40
1138 +#define MT8173_INFRA_MMIOMMURST 47
1139 +
1140 +
1141 +/* PERICFG resets */
1142 +#define MT8173_PERI_UART0_SW_RST 0
1143 +#define MT8173_PERI_UART1_SW_RST 1
1144 +#define MT8173_PERI_UART2_SW_RST 2
1145 +#define MT8173_PERI_UART3_SW_RST 3
1146 +#define MT8173_PERI_IRRX_SW_RST 4
1147 +#define MT8173_PERI_PWM_SW_RST 8
1148 +#define MT8173_PERI_AUXADC_SW_RST 10
1149 +#define MT8173_PERI_DMA_SW_RST 11
1150 +#define MT8173_PERI_I2C6_SW_RST 13
1151 +#define MT8173_PERI_NFI_SW_RST 14
1152 +#define MT8173_PERI_THERM_SW_RST 16
1153 +#define MT8173_PERI_MSDC2_SW_RST 17
1154 +#define MT8173_PERI_MSDC3_SW_RST 18
1155 +#define MT8173_PERI_MSDC0_SW_RST 19
1156 +#define MT8173_PERI_MSDC1_SW_RST 20
1157 +#define MT8173_PERI_I2C0_SW_RST 22
1158 +#define MT8173_PERI_I2C1_SW_RST 23
1159 +#define MT8173_PERI_I2C2_SW_RST 24
1160 +#define MT8173_PERI_I2C3_SW_RST 25
1161 +#define MT8173_PERI_I2C4_SW_RST 26
1162 +#define MT8173_PERI_HDMI_SW_RST 29
1163 +#define MT8173_PERI_SPI0_SW_RST 33
1164 +
1165 +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */
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