projects / openwrt / staging / chunkeey.git / blob
? search:


9c0e2891a7eb26d9c1b9f38ba821aaa947dc92f4
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches / 0005-clk-mediatek-Add-basic-clocks-for-Mediatek-MT8173.patch
1 From 0efcd47787019284a334186fce134ee475c79211 Mon Sep 17 00:00:00 2001
2 From: James Liao <jamesjj.liao@mediatek.com>
3 Date: Thu, 23 Apr 2015 10:35:42 +0200
4 Subject: [PATCH 05/76] clk: mediatek: Add basic clocks for Mediatek MT8173.
5
6 This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs,
7 INFRA and PERI clocks.
8
9 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
10 Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
11 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
12 ---
13 drivers/clk/mediatek/Makefile | 1 +
14 drivers/clk/mediatek/clk-mt8173.c | 830 ++++++++++++++++++++
15 include/dt-bindings/clock/mt8173-clk.h | 235 ++++++
16 .../dt-bindings/reset-controller/mt8173-resets.h | 63 ++
17 4 files changed, 1129 insertions(+)
18 create mode 100644 drivers/clk/mediatek/clk-mt8173.c
19 create mode 100644 include/dt-bindings/clock/mt8173-clk.h
20 create mode 100644 include/dt-bindings/reset-controller/mt8173-resets.h
21
22 diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
23 index 12ce576..8e4b2a4 100644
24 --- a/drivers/clk/mediatek/Makefile
25 +++ b/drivers/clk/mediatek/Makefile
26 @@ -1,3 +1,4 @@
27 obj-y += clk-mtk.o clk-pll.o clk-gate.o
28 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
29 obj-y += clk-mt8135.o
30 +obj-y += clk-mt8173.o
31 diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
32 new file mode 100644
33 index 0000000..357b080
34 --- /dev/null
35 +++ b/drivers/clk/mediatek/clk-mt8173.c
36 @@ -0,0 +1,830 @@
37 +/*
38 + * Copyright (c) 2014 MediaTek Inc.
39 + * Author: James Liao <jamesjj.liao@mediatek.com>
40 + *
41 + * This program is free software; you can redistribute it and/or modify
42 + * it under the terms of the GNU General Public License version 2 as
43 + * published by the Free Software Foundation.
44 + *
45 + * This program is distributed in the hope that it will be useful,
46 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
47 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48 + * GNU General Public License for more details.
49 + */
50 +
51 +#include <linux/of.h>
52 +#include <linux/of_address.h>
53 +#include <linux/slab.h>
54 +#include <linux/mfd/syscon.h>
55 +
56 +#include "clk-mtk.h"
57 +#include "clk-gate.h"
58 +
59 +#include <dt-bindings/clock/mt8173-clk.h>
60 +
61 +static DEFINE_SPINLOCK(mt8173_clk_lock);
62 +
63 +static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
64 + FACTOR(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk_null", 1, 1),
65 + FACTOR(CLK_TOP_DPI, "dpi_ck", "clk_null", 1, 1),
66 + FACTOR(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk_null", 1, 1),
67 + FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "clk_null", 1, 1),
68 +};
69 +
70 +static const struct mtk_fixed_factor top_divs[] __initconst = {
71 + FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2),
72 + FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3),
73 +
74 + FACTOR(CLK_TOP_MAIN_H546M, "main_h546m", "mainpll", 1, 2),
75 + FACTOR(CLK_TOP_MAIN_H364M, "main_h364m", "mainpll", 1, 3),
76 + FACTOR(CLK_TOP_MAIN_H218P4M, "main_h218p4m", "mainpll", 1, 5),
77 + FACTOR(CLK_TOP_MAIN_H156M, "main_h156m", "mainpll", 1, 7),
78 +
79 + FACTOR(CLK_TOP_TVDPLL_445P5M, "tvdpll_445p5m", "tvdpll", 1, 4),
80 + FACTOR(CLK_TOP_TVDPLL_594M, "tvdpll_594m", "tvdpll", 1, 3),
81 +
82 + FACTOR(CLK_TOP_UNIV_624M, "univ_624m", "univpll", 1, 2),
83 + FACTOR(CLK_TOP_UNIV_416M, "univ_416m", "univpll", 1, 3),
84 + FACTOR(CLK_TOP_UNIV_249P6M, "univ_249p6m", "univpll", 1, 5),
85 + FACTOR(CLK_TOP_UNIV_178P3M, "univ_178p3m", "univpll", 1, 7),
86 + FACTOR(CLK_TOP_UNIV_48M, "univ_48m", "univpll", 1, 26),
87 +
88 + FACTOR(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", "clk32k", 1, 1),
89 + FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),
90 + FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),
91 +
92 + FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),
93 + FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
94 +
95 + FACTOR(CLK_TOP_ARMCA7PLL_D2, "armca7pll_d2", "armca7pll_754m", 1, 1),
96 + FACTOR(CLK_TOP_ARMCA7PLL_D3, "armca7pll_d3", "armca7pll_502m", 1, 1),
97 +
98 + FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
99 + FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
100 +
101 + FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "clkph_mck_o", 1, 1),
102 + FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "clkph_mck_o", 1, 2),
103 + FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "clkph_mck_o", 1, 4),
104 + FACTOR(CLK_TOP_DMPLL_D8, "dmpll_d8", "clkph_mck_o", 1, 8),
105 + FACTOR(CLK_TOP_DMPLL_D16, "dmpll_d16", "clkph_mck_o", 1, 16),
106 +
107 + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
108 + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
109 + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
110 +
111 + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
112 + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
113 +
114 + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
115 + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
116 + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
117 + FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1),
118 + FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2", 1, 2),
119 + FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2", 1, 4),
120 +
121 + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "main_h546m", 1, 1),
122 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2),
123 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "main_h546m", 1, 4),
124 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "main_h546m", 1, 8),
125 + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "main_h546m", 1, 16),
126 + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "main_h364m", 1, 1),
127 + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "main_h364m", 1, 2),
128 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "main_h364m", 1, 4),
129 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "main_h218p4m", 1, 1),
130 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "main_h218p4m", 1, 2),
131 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "main_h218p4m", 1, 4),
132 + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "main_h156m", 1, 1),
133 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "main_h156m", 1, 2),
134 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "main_h156m", 1, 4),
135 +
136 + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll_594m", 1, 1),
137 + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_594m", 1, 2),
138 + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_594m", 1, 4),
139 + FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_594m", 1, 8),
140 + FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll_594m", 1, 16),
141 +
142 + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univ_624m", 1, 1),
143 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univ_624m", 1, 2),
144 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univ_624m", 1, 4),
145 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univ_624m", 1, 8),
146 + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univ_416m", 1, 1),
147 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univ_416m", 1, 2),
148 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univ_416m", 1, 4),
149 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univ_416m", 1, 8),
150 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univ_249p6m", 1, 1),
151 + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univ_249p6m", 1, 2),
152 + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univ_249p6m", 1, 4),
153 + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univ_249p6m", 1, 8),
154 + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univ_178p3m", 1, 1),
155 + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univ_48m", 1, 1),
156 + FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univ_48m", 1, 2),
157 +
158 + FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 3),
159 + FACTOR(CLK_TOP_VCODECPLL_370P5, "vcodecpll_370p5", "vcodecpll", 1, 4),
160 +
161 + FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1),
162 + FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll", 1, 2),
163 + FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4),
164 +};
165 +
166 +static const char * const axi_parents[] __initconst = {
167 + "clk26m",
168 + "syspll1_d2",
169 + "syspll_d5",
170 + "syspll1_d4",
171 + "univpll_d5",
172 + "univpll2_d2",
173 + "dmpll_d2",
174 + "dmpll_d4"
175 +};
176 +
177 +static const char * const mem_parents[] __initconst = {
178 + "clk26m",
179 + "dmpll_ck"
180 +};
181 +
182 +static const char * const ddrphycfg_parents[] __initconst = {
183 + "clk26m",
184 + "syspll1_d8"
185 +};
186 +
187 +static const char * const mm_parents[] __initconst = {
188 + "clk26m",
189 + "vencpll_d2",
190 + "main_h364m",
191 + "syspll1_d2",
192 + "syspll_d5",
193 + "syspll1_d4",
194 + "univpll1_d2",
195 + "univpll2_d2",
196 + "dmpll_d2"
197 +};
198 +
199 +static const char * const pwm_parents[] __initconst = {
200 + "clk26m",
201 + "univpll2_d4",
202 + "univpll3_d2",
203 + "univpll1_d4"
204 +};
205 +
206 +static const char * const vdec_parents[] __initconst = {
207 + "clk26m",
208 + "vcodecpll_ck",
209 + "tvdpll_445p5m",
210 + "univpll_d3",
211 + "vencpll_d2",
212 + "syspll_d3",
213 + "univpll1_d2",
214 + "mmpll_d2",
215 + "dmpll_d2",
216 + "dmpll_d4"
217 +};
218 +
219 +static const char * const venc_parents[] __initconst = {
220 + "clk26m",
221 + "vcodecpll_ck",
222 + "tvdpll_445p5m",
223 + "univpll_d3",
224 + "vencpll_d2",
225 + "syspll_d3",
226 + "univpll1_d2",
227 + "univpll2_d2",
228 + "dmpll_d2",
229 + "dmpll_d4"
230 +};
231 +
232 +static const char * const mfg_parents[] __initconst = {
233 + "clk26m",
234 + "mmpll_ck",
235 + "dmpll_ck",
236 + "clk26m",
237 + "clk26m",
238 + "clk26m",
239 + "clk26m",
240 + "clk26m",
241 + "clk26m",
242 + "syspll_d3",
243 + "syspll1_d2",
244 + "syspll_d5",
245 + "univpll_d3",
246 + "univpll1_d2",
247 + "univpll_d5",
248 + "univpll2_d2"
249 +};
250 +
251 +static const char * const camtg_parents[] __initconst = {
252 + "clk26m",
253 + "univpll_d26",
254 + "univpll2_d2",
255 + "syspll3_d2",
256 + "syspll3_d4",
257 + "univpll1_d4"
258 +};
259 +
260 +static const char * const uart_parents[] __initconst = {
261 + "clk26m",
262 + "univpll2_d8"
263 +};
264 +
265 +static const char * const spi_parents[] __initconst = {
266 + "clk26m",
267 + "syspll3_d2",
268 + "syspll1_d4",
269 + "syspll4_d2",
270 + "univpll3_d2",
271 + "univpll2_d4",
272 + "univpll1_d8"
273 +};
274 +
275 +static const char * const usb20_parents[] __initconst = {
276 + "clk26m",
277 + "univpll1_d8",
278 + "univpll3_d4"
279 +};
280 +
281 +static const char * const usb30_parents[] __initconst = {
282 + "clk26m",
283 + "univpll3_d2",
284 + "usb_syspll_125m",
285 + "univpll2_d4"
286 +};
287 +
288 +static const char * const msdc50_0_h_parents[] __initconst = {
289 + "clk26m",
290 + "syspll1_d2",
291 + "syspll2_d2",
292 + "syspll4_d2",
293 + "univpll_d5",
294 + "univpll1_d4"
295 +};
296 +
297 +static const char * const msdc50_0_parents[] __initconst = {
298 + "clk26m",
299 + "msdcpll_ck",
300 + "msdcpll_d2",
301 + "univpll1_d4",
302 + "syspll2_d2",
303 + "syspll_d7",
304 + "msdcpll_d4",
305 + "vencpll_d4",
306 + "tvdpll_ck",
307 + "univpll_d2",
308 + "univpll1_d2",
309 + "mmpll_ck",
310 + "msdcpll2_ck",
311 + "msdcpll2_d2",
312 + "msdcpll2_d4"
313 +};
314 +
315 +static const char * const msdc30_1_parents[] __initconst = {
316 + "clk26m",
317 + "univpll2_d2",
318 + "msdcpll_d4",
319 + "univpll1_d4",
320 + "syspll2_d2",
321 + "syspll_d7",
322 + "univpll_d7",
323 + "vencpll_d4"
324 +};
325 +
326 +static const char * const msdc30_2_parents[] __initconst = {
327 + "clk26m",
328 + "univpll2_d2",
329 + "msdcpll_d4",
330 + "univpll1_d4",
331 + "syspll2_d2",
332 + "syspll_d7",
333 + "univpll_d7",
334 + "vencpll_d2"
335 +};
336 +
337 +static const char * const msdc30_3_parents[] __initconst = {
338 + "clk26m",
339 + "msdcpll2_ck",
340 + "msdcpll2_d2",
341 + "univpll2_d2",
342 + "msdcpll2_d4",
343 + "msdcpll_d4",
344 + "univpll1_d4",
345 + "syspll2_d2",
346 + "syspll_d7",
347 + "univpll_d7",
348 + "vencpll_d4",
349 + "msdcpll_ck",
350 + "msdcpll_d2",
351 + "msdcpll_d4"
352 +};
353 +
354 +static const char * const audio_parents[] __initconst = {
355 + "clk26m",
356 + "syspll3_d4",
357 + "syspll4_d4",
358 + "syspll1_d16"
359 +};
360 +
361 +static const char * const aud_intbus_parents[] __initconst = {
362 + "clk26m",
363 + "syspll1_d4",
364 + "syspll4_d2",
365 + "univpll3_d2",
366 + "univpll2_d8",
367 + "dmpll_d4",
368 + "dmpll_d8"
369 +};
370 +
371 +static const char * const pmicspi_parents[] __initconst = {
372 + "clk26m",
373 + "syspll1_d8",
374 + "syspll3_d4",
375 + "syspll1_d16",
376 + "univpll3_d4",
377 + "univpll_d26",
378 + "dmpll_d8",
379 + "dmpll_d16"
380 +};
381 +
382 +static const char * const scp_parents[] __initconst = {
383 + "clk26m",
384 + "syspll1_d2",
385 + "univpll_d5",
386 + "syspll_d5",
387 + "dmpll_d2",
388 + "dmpll_d4"
389 +};
390 +
391 +static const char * const atb_parents[] __initconst = {
392 + "clk26m",
393 + "syspll1_d2",
394 + "univpll_d5",
395 + "dmpll_d2"
396 +};
397 +
398 +static const char * const venc_lt_parents[] __initconst = {
399 + "clk26m",
400 + "univpll_d3",
401 + "vcodecpll_ck",
402 + "tvdpll_445p5m",
403 + "vencpll_d2",
404 + "syspll_d3",
405 + "univpll1_d2",
406 + "univpll2_d2",
407 + "syspll1_d2",
408 + "univpll_d5",
409 + "vcodecpll_370p5",
410 + "dmpll_ck"
411 +};
412 +
413 +static const char * const dpi0_parents[] __initconst = {
414 + "clk26m",
415 + "tvdpll_d2",
416 + "tvdpll_d4",
417 + "clk26m",
418 + "clk26m",
419 + "tvdpll_d8",
420 + "tvdpll_d16"
421 +};
422 +
423 +static const char * const irda_parents[] __initconst = {
424 + "clk26m",
425 + "univpll2_d4",
426 + "syspll2_d4"
427 +};
428 +
429 +static const char * const cci400_parents[] __initconst = {
430 + "clk26m",
431 + "vencpll_ck",
432 + "armca7pll_754m",
433 + "armca7pll_502m",
434 + "univpll_d2",
435 + "syspll_d2",
436 + "msdcpll_ck",
437 + "dmpll_ck"
438 +};
439 +
440 +static const char * const aud_1_parents[] __initconst = {
441 + "clk26m",
442 + "apll1_ck",
443 + "univpll2_d4",
444 + "univpll2_d8"
445 +};
446 +
447 +static const char * const aud_2_parents[] __initconst = {
448 + "clk26m",
449 + "apll2_ck",
450 + "univpll2_d4",
451 + "univpll2_d8"
452 +};
453 +
454 +static const char * const mem_mfg_in_parents[] __initconst = {
455 + "clk26m",
456 + "mmpll_ck",
457 + "dmpll_ck",
458 + "clk26m"
459 +};
460 +
461 +static const char * const axi_mfg_in_parents[] __initconst = {
462 + "clk26m",
463 + "axi_sel",
464 + "dmpll_d2"
465 +};
466 +
467 +static const char * const scam_parents[] __initconst = {
468 + "clk26m",
469 + "syspll3_d2",
470 + "univpll2_d4",
471 + "dmpll_d4"
472 +};
473 +
474 +static const char * const spinfi_ifr_parents[] __initconst = {
475 + "clk26m",
476 + "univpll2_d8",
477 + "univpll3_d4",
478 + "syspll4_d2",
479 + "univpll2_d4",
480 + "univpll3_d2",
481 + "syspll1_d4",
482 + "univpll1_d4"
483 +};
484 +
485 +static const char * const hdmi_parents[] __initconst = {
486 + "clk26m",
487 + "hdmitx_dig_cts",
488 + "hdmitxpll_d2",
489 + "hdmitxpll_d3"
490 +};
491 +
492 +static const char * const dpilvds_parents[] __initconst = {
493 + "clk26m",
494 + "lvdspll",
495 + "lvdspll_d2",
496 + "lvdspll_d4",
497 + "lvdspll_d8",
498 + "fpc_ck"
499 +};
500 +
501 +static const char * const msdc50_2_h_parents[] __initconst = {
502 + "clk26m",
503 + "syspll1_d2",
504 + "syspll2_d2",
505 + "syspll4_d2",
506 + "univpll_d5",
507 + "univpll1_d4"
508 +};
509 +
510 +static const char * const hdcp_parents[] __initconst = {
511 + "clk26m",
512 + "syspll4_d2",
513 + "syspll3_d4",
514 + "univpll2_d4"
515 +};
516 +
517 +static const char * const hdcp_24m_parents[] __initconst = {
518 + "clk26m",
519 + "univpll_d26",
520 + "univpll_d52",
521 + "univpll2_d8"
522 +};
523 +
524 +static const char * const rtc_parents[] __initconst = {
525 + "clkrtc_int",
526 + "clkrtc_ext",
527 + "clk26m",
528 + "univpll3_d8"
529 +};
530 +
531 +static const char * const i2s0_m_ck_parents[] __initconst = {
532 + "apll1_div1",
533 + "apll2_div1"
534 +};
535 +
536 +static const char * const i2s1_m_ck_parents[] __initconst = {
537 + "apll1_div2",
538 + "apll2_div2"
539 +};
540 +
541 +static const char * const i2s2_m_ck_parents[] __initconst = {
542 + "apll1_div3",
543 + "apll2_div3"
544 +};
545 +
546 +static const char * const i2s3_m_ck_parents[] __initconst = {
547 + "apll1_div4",
548 + "apll2_div4"
549 +};
550 +
551 +static const char * const i2s3_b_ck_parents[] __initconst = {
552 + "apll1_div5",
553 + "apll2_div5"
554 +};
555 +
556 +static const struct mtk_composite top_muxes[] __initconst = {
557 + /* CLK_CFG_0 */
558 + MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3),
559 + MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
560 + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
561 + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
562 + /* CLK_CFG_1 */
563 + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
564 + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
565 + MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),
566 + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),
567 + /* CLK_CFG_2 */
568 + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),
569 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
570 + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),
571 + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),
572 + /* CLK_CFG_3 */
573 + MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x0070, 0, 2, 7),
574 + MUX_GATE(CLK_TOP_MSDC50_0_H_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 0x0070, 8, 3, 15),
575 + MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
576 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
577 + /* CLK_CFG_4 */
578 + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
579 + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 0x0080, 8, 4, 15),
580 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0080, 16, 2, 23),
581 + MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
582 + /* CLK_CFG_5 */
583 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0090, 0, 3, 7 /* 7:5 */),
584 + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
585 + MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),
586 + MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),
587 + /* CLK_CFG_6 */
588 + MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),
589 + MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),
590 + MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),
591 + MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
592 + /* CLK_CFG_7 */
593 + MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
594 + MUX_GATE(CLK_TOP_MEM_MFG_IN_SEL, "mem_mfg_in_sel", mem_mfg_in_parents, 0x00b0, 8, 2, 15),
595 + MUX_GATE(CLK_TOP_AXI_MFG_IN_SEL, "axi_mfg_in_sel", axi_mfg_in_parents, 0x00b0, 16, 2, 23),
596 + MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x00b0, 24, 2, 31),
597 + /* CLK_CFG_12 */
598 + MUX_GATE(CLK_TOP_SPINFI_IFR_SEL, "spinfi_ifr_sel", spinfi_ifr_parents, 0x00c0, 0, 3, 7),
599 + MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x00c0, 8, 2, 15),
600 + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x00c0, 24, 3, 31),
601 + /* CLK_CFG_13 */
602 + MUX_GATE(CLK_TOP_MSDC50_2_H_SEL, "msdc50_2_h_sel", msdc50_2_h_parents, 0x00d0, 0, 3, 7),
603 + MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
604 + MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 0x00d0, 16, 2, 23),
605 + MUX(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00d0, 24, 2),
606 +
607 + DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
608 + DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
609 + DIV_GATE(CLK_TOP_APLL1_DIV2, "apll1_div2", "aud_1_sel", 0x12c, 10, 0x124, 8, 8),
610 + DIV_GATE(CLK_TOP_APLL1_DIV3, "apll1_div3", "aud_1_sel", 0x12c, 11, 0x124, 8, 16),
611 + DIV_GATE(CLK_TOP_APLL1_DIV4, "apll1_div4", "aud_1_sel", 0x12c, 12, 0x124, 8, 24),
612 + DIV_GATE(CLK_TOP_APLL1_DIV5, "apll1_div5", "apll1_div4", 0x12c, 13, 0x12c, 4, 0),
613 +
614 + DIV_GATE(CLK_TOP_APLL2_DIV0, "apll2_div0", "aud_2_sel", 0x12c, 16, 0x120, 4, 28),
615 + DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
616 + DIV_GATE(CLK_TOP_APLL2_DIV2, "apll2_div2", "aud_2_sel", 0x12c, 18, 0x128, 8, 8),
617 + DIV_GATE(CLK_TOP_APLL2_DIV3, "apll2_div3", "aud_2_sel", 0x12c, 19, 0x128, 8, 16),
618 + DIV_GATE(CLK_TOP_APLL2_DIV4, "apll2_div4", "aud_2_sel", 0x12c, 20, 0x128, 8, 24),
619 + DIV_GATE(CLK_TOP_APLL2_DIV5, "apll2_div5", "apll2_div4", 0x12c, 21, 0x12c, 4, 4),
620 +
621 + MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents, 0x120, 4, 1),
622 + MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents, 0x120, 5, 1),
623 + MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents, 0x120, 6, 1),
624 + MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents, 0x120, 7, 1),
625 + MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1),
626 +};
627 +
628 +static const struct mtk_gate_regs infra_cg_regs = {
629 + .set_ofs = 0x0040,
630 + .clr_ofs = 0x0044,
631 + .sta_ofs = 0x0048,
632 +};
633 +
634 +#define GATE_ICG(_id, _name, _parent, _shift) { \
635 + .id = _id, \
636 + .name = _name, \
637 + .parent_name = _parent, \
638 + .regs = &infra_cg_regs, \
639 + .shift = _shift, \
640 + .ops = &mtk_clk_gate_ops_setclr, \
641 + }
642 +
643 +static const struct mtk_gate infra_clks[] __initconst = {
644 + GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
645 + GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1),
646 + GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5),
647 + GATE_ICG(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
648 + GATE_ICG(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "axi_sel", 7),
649 + GATE_ICG(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
650 + GATE_ICG(CLK_INFRA_CPUM, "infra_cpum", "clk_null", 15),
651 + GATE_ICG(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
652 + GATE_ICG(CLK_INFRA_CEC, "infra_cec", "clk26m", 18),
653 + GATE_ICG(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22),
654 + GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23),
655 +};
656 +
657 +static const struct mtk_gate_regs peri0_cg_regs = {
658 + .set_ofs = 0x0008,
659 + .clr_ofs = 0x0010,
660 + .sta_ofs = 0x0018,
661 +};
662 +
663 +static const struct mtk_gate_regs peri1_cg_regs = {
664 + .set_ofs = 0x000c,
665 + .clr_ofs = 0x0014,
666 + .sta_ofs = 0x001c,
667 +};
668 +
669 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
670 + .id = _id, \
671 + .name = _name, \
672 + .parent_name = _parent, \
673 + .regs = &peri0_cg_regs, \
674 + .shift = _shift, \
675 + .ops = &mtk_clk_gate_ops_setclr, \
676 + }
677 +
678 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
679 + .id = _id, \
680 + .name = _name, \
681 + .parent_name = _parent, \
682 + .regs = &peri1_cg_regs, \
683 + .shift = _shift, \
684 + .ops = &mtk_clk_gate_ops_setclr, \
685 + }
686 +
687 +static const struct mtk_gate peri_gates[] __initconst = {
688 + /* PERI0 */
689 + GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
690 + GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
691 + GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
692 + GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
693 + GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
694 + GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
695 + GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
696 + GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
697 + GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
698 + GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
699 + GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
700 + GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
701 + GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
702 + GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
703 + GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
704 + GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
705 + GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
706 + GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
707 + GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
708 + GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
709 + GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
710 + GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
711 + GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
712 + GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
713 + GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
714 + GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
715 + GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
716 + GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
717 + GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
718 + GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
719 + GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
720 + GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
721 + /* PERI1 */
722 + GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
723 + GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
724 + GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
725 +};
726 +
727 +static const char * const uart_ck_sel_parents[] __initconst = {
728 + "clk26m",
729 + "uart_sel",
730 +};
731 +
732 +static const struct mtk_composite peri_clks[] __initconst = {
733 + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
734 + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
735 + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
736 + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
737 +};
738 +
739 +static void __init mtk_topckgen_init(struct device_node *node)
740 +{
741 + struct clk_onecell_data *clk_data;
742 + void __iomem *base;
743 + int r;
744 +
745 + base = of_iomap(node, 0);
746 + if (!base) {
747 + pr_err("%s(): ioremap failed\n", __func__);
748 + return;
749 + }
750 +
751 + clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
752 +
753 + mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
754 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
755 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
756 + &mt8173_clk_lock, clk_data);
757 +
758 + clk_prepare_enable(clk_data->clks[CLK_TOP_CCI400_SEL]);
759 +
760 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
761 + if (r)
762 + pr_err("%s(): could not register clock provider: %d\n",
763 + __func__, r);
764 +}
765 +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
766 +
767 +static void __init mtk_infrasys_init(struct device_node *node)
768 +{
769 + struct clk_onecell_data *clk_data;
770 + int r;
771 +
772 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
773 +
774 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
775 + clk_data);
776 +
777 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
778 + if (r)
779 + pr_err("%s(): could not register clock provider: %d\n",
780 + __func__, r);
781 +
782 + mtk_register_reset_controller(node, 2, 0x30);
783 +}
784 +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
785 +
786 +static void __init mtk_pericfg_init(struct device_node *node)
787 +{
788 + struct clk_onecell_data *clk_data;
789 + int r;
790 + void __iomem *base;
791 +
792 + base = of_iomap(node, 0);
793 + if (!base) {
794 + pr_err("%s(): ioremap failed\n", __func__);
795 + return;
796 + }
797 +
798 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
799 +
800 + mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
801 + clk_data);
802 + mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
803 + &mt8173_clk_lock, clk_data);
804 +
805 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
806 + if (r)
807 + pr_err("%s(): could not register clock provider: %d\n",
808 + __func__, r);
809 +
810 + mtk_register_reset_controller(node, 2, 0);
811 +}
812 +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
813 +
814 +#define MT8173_PLL_FMAX (3000UL * MHZ)
815 +
816 +#define CON0_MT8173_RST_BAR BIT(24)
817 +
818 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, \
819 + _tuner_reg, _pcw_reg, _pcw_shift) { \
820 + .id = _id, \
821 + .name = _name, \
822 + .reg = _reg, \
823 + .pwr_reg = _pwr_reg, \
824 + .en_mask = _en_mask, \
825 + .flags = _flags, \
826 + .rst_bar_mask = CON0_MT8173_RST_BAR, \
827 + .fmax = MT8173_PLL_FMAX, \
828 + .pcwbits = _pcwbits, \
829 + .pd_reg = _pd_reg, \
830 + .pd_shift = _pd_shift, \
831 + .tuner_reg = _tuner_reg, \
832 + .pcw_reg = _pcw_reg, \
833 + .pcw_shift = _pcw_shift, \
834 + }
835 +
836 +static const struct mtk_pll_data plls[] = {
837 + PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
838 + PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
839 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
840 + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
841 + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0),
842 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
843 + PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
844 + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
845 + PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
846 + PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
847 + PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
848 + PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
849 + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
850 + PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
851 +};
852 +
853 +static void __init mtk_apmixedsys_init(struct device_node *node)
854 +{
855 + struct clk_onecell_data *clk_data;
856 +
857 + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
858 + if (!clk_data)
859 + return;
860 +
861 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
862 +
863 + clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
864 +}
865 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
866 + mtk_apmixedsys_init);
867 diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
868 new file mode 100644
869 index 0000000..4ad76ed
870 --- /dev/null
871 +++ b/include/dt-bindings/clock/mt8173-clk.h
872 @@ -0,0 +1,235 @@
873 +/*
874 + * Copyright (c) 2014 MediaTek Inc.
875 + * Author: James Liao <jamesjj.liao@mediatek.com>
876 + *
877 + * This program is free software; you can redistribute it and/or modify
878 + * it under the terms of the GNU General Public License version 2 as
879 + * published by the Free Software Foundation.
880 + *
881 + * This program is distributed in the hope that it will be useful,
882 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
883 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
884 + * GNU General Public License for more details.
885 + */
886 +
887 +#ifndef _DT_BINDINGS_CLK_MT8173_H
888 +#define _DT_BINDINGS_CLK_MT8173_H
889 +
890 +/* TOPCKGEN */
891 +
892 +#define CLK_TOP_CLKPH_MCK_O 1
893 +#define CLK_TOP_DPI 2
894 +#define CLK_TOP_USB_SYSPLL_125M 3
895 +#define CLK_TOP_HDMITX_DIG_CTS 4
896 +#define CLK_TOP_ARMCA7PLL_754M 5
897 +#define CLK_TOP_ARMCA7PLL_502M 6
898 +#define CLK_TOP_MAIN_H546M 7
899 +#define CLK_TOP_MAIN_H364M 8
900 +#define CLK_TOP_MAIN_H218P4M 9
901 +#define CLK_TOP_MAIN_H156M 10
902 +#define CLK_TOP_TVDPLL_445P5M 11
903 +#define CLK_TOP_TVDPLL_594M 12
904 +#define CLK_TOP_UNIV_624M 13
905 +#define CLK_TOP_UNIV_416M 14
906 +#define CLK_TOP_UNIV_249P6M 15
907 +#define CLK_TOP_UNIV_178P3M 16
908 +#define CLK_TOP_UNIV_48M 17
909 +#define CLK_TOP_CLKRTC_EXT 18
910 +#define CLK_TOP_CLKRTC_INT 19
911 +#define CLK_TOP_FPC 20
912 +#define CLK_TOP_HDMITXPLL_D2 21
913 +#define CLK_TOP_HDMITXPLL_D3 22
914 +#define CLK_TOP_ARMCA7PLL_D2 23
915 +#define CLK_TOP_ARMCA7PLL_D3 24
916 +#define CLK_TOP_APLL1 25
917 +#define CLK_TOP_APLL2 26
918 +#define CLK_TOP_DMPLL 27
919 +#define CLK_TOP_DMPLL_D2 28
920 +#define CLK_TOP_DMPLL_D4 29
921 +#define CLK_TOP_DMPLL_D8 30
922 +#define CLK_TOP_DMPLL_D16 31
923 +#define CLK_TOP_LVDSPLL_D2 32
924 +#define CLK_TOP_LVDSPLL_D4 33
925 +#define CLK_TOP_LVDSPLL_D8 34
926 +#define CLK_TOP_MMPLL 35
927 +#define CLK_TOP_MMPLL_D2 36
928 +#define CLK_TOP_MSDCPLL 37
929 +#define CLK_TOP_MSDCPLL_D2 38
930 +#define CLK_TOP_MSDCPLL_D4 39
931 +#define CLK_TOP_MSDCPLL2 40
932 +#define CLK_TOP_MSDCPLL2_D2 41
933 +#define CLK_TOP_MSDCPLL2_D4 42
934 +#define CLK_TOP_SYSPLL_D2 43
935 +#define CLK_TOP_SYSPLL1_D2 44
936 +#define CLK_TOP_SYSPLL1_D4 45
937 +#define CLK_TOP_SYSPLL1_D8 46
938 +#define CLK_TOP_SYSPLL1_D16 47
939 +#define CLK_TOP_SYSPLL_D3 48
940 +#define CLK_TOP_SYSPLL2_D2 49
941 +#define CLK_TOP_SYSPLL2_D4 50
942 +#define CLK_TOP_SYSPLL_D5 51
943 +#define CLK_TOP_SYSPLL3_D2 52
944 +#define CLK_TOP_SYSPLL3_D4 53
945 +#define CLK_TOP_SYSPLL_D7 54
946 +#define CLK_TOP_SYSPLL4_D2 55
947 +#define CLK_TOP_SYSPLL4_D4 56
948 +#define CLK_TOP_TVDPLL 57
949 +#define CLK_TOP_TVDPLL_D2 58
950 +#define CLK_TOP_TVDPLL_D4 59
951 +#define CLK_TOP_TVDPLL_D8 60
952 +#define CLK_TOP_TVDPLL_D16 61
953 +#define CLK_TOP_UNIVPLL_D2 62
954 +#define CLK_TOP_UNIVPLL1_D2 63
955 +#define CLK_TOP_UNIVPLL1_D4 64
956 +#define CLK_TOP_UNIVPLL1_D8 65
957 +#define CLK_TOP_UNIVPLL_D3 66
958 +#define CLK_TOP_UNIVPLL2_D2 67
959 +#define CLK_TOP_UNIVPLL2_D4 68
960 +#define CLK_TOP_UNIVPLL2_D8 69
961 +#define CLK_TOP_UNIVPLL_D5 70
962 +#define CLK_TOP_UNIVPLL3_D2 71
963 +#define CLK_TOP_UNIVPLL3_D4 72
964 +#define CLK_TOP_UNIVPLL3_D8 73
965 +#define CLK_TOP_UNIVPLL_D7 74
966 +#define CLK_TOP_UNIVPLL_D26 75
967 +#define CLK_TOP_UNIVPLL_D52 76
968 +#define CLK_TOP_VCODECPLL 77
969 +#define CLK_TOP_VCODECPLL_370P5 78
970 +#define CLK_TOP_VENCPLL 79
971 +#define CLK_TOP_VENCPLL_D2 80
972 +#define CLK_TOP_VENCPLL_D4 81
973 +#define CLK_TOP_AXI_SEL 82
974 +#define CLK_TOP_MEM_SEL 83
975 +#define CLK_TOP_DDRPHYCFG_SEL 84
976 +#define CLK_TOP_MM_SEL 85
977 +#define CLK_TOP_PWM_SEL 86
978 +#define CLK_TOP_VDEC_SEL 87
979 +#define CLK_TOP_VENC_SEL 88
980 +#define CLK_TOP_MFG_SEL 89
981 +#define CLK_TOP_CAMTG_SEL 90
982 +#define CLK_TOP_UART_SEL 91
983 +#define CLK_TOP_SPI_SEL 92
984 +#define CLK_TOP_USB20_SEL 93
985 +#define CLK_TOP_USB30_SEL 94
986 +#define CLK_TOP_MSDC50_0_H_SEL 95
987 +#define CLK_TOP_MSDC50_0_SEL 96
988 +#define CLK_TOP_MSDC30_1_SEL 97
989 +#define CLK_TOP_MSDC30_2_SEL 98
990 +#define CLK_TOP_MSDC30_3_SEL 99
991 +#define CLK_TOP_AUDIO_SEL 100
992 +#define CLK_TOP_AUD_INTBUS_SEL 101
993 +#define CLK_TOP_PMICSPI_SEL 102
994 +#define CLK_TOP_SCP_SEL 103
995 +#define CLK_TOP_ATB_SEL 104
996 +#define CLK_TOP_VENC_LT_SEL 105
997 +#define CLK_TOP_DPI0_SEL 106
998 +#define CLK_TOP_IRDA_SEL 107
999 +#define CLK_TOP_CCI400_SEL 108
1000 +#define CLK_TOP_AUD_1_SEL 109
1001 +#define CLK_TOP_AUD_2_SEL 110
1002 +#define CLK_TOP_MEM_MFG_IN_SEL 111
1003 +#define CLK_TOP_AXI_MFG_IN_SEL 112
1004 +#define CLK_TOP_SCAM_SEL 113
1005 +#define CLK_TOP_SPINFI_IFR_SEL 114
1006 +#define CLK_TOP_HDMI_SEL 115
1007 +#define CLK_TOP_DPILVDS_SEL 116
1008 +#define CLK_TOP_MSDC50_2_H_SEL 117
1009 +#define CLK_TOP_HDCP_SEL 118
1010 +#define CLK_TOP_HDCP_24M_SEL 119
1011 +#define CLK_TOP_RTC_SEL 120
1012 +#define CLK_TOP_APLL1_DIV0 121
1013 +#define CLK_TOP_APLL1_DIV1 122
1014 +#define CLK_TOP_APLL1_DIV2 123
1015 +#define CLK_TOP_APLL1_DIV3 124
1016 +#define CLK_TOP_APLL1_DIV4 125
1017 +#define CLK_TOP_APLL1_DIV5 126
1018 +#define CLK_TOP_APLL2_DIV0 127
1019 +#define CLK_TOP_APLL2_DIV1 128
1020 +#define CLK_TOP_APLL2_DIV2 129
1021 +#define CLK_TOP_APLL2_DIV3 130
1022 +#define CLK_TOP_APLL2_DIV4 131
1023 +#define CLK_TOP_APLL2_DIV5 132
1024 +#define CLK_TOP_I2S0_M_SEL 133
1025 +#define CLK_TOP_I2S1_M_SEL 134
1026 +#define CLK_TOP_I2S2_M_SEL 135
1027 +#define CLK_TOP_I2S3_M_SEL 136
1028 +#define CLK_TOP_I2S3_B_SEL 137
1029 +#define CLK_TOP_NR_CLK 138
1030 +
1031 +/* APMIXED_SYS */
1032 +
1033 +#define CLK_APMIXED_ARMCA15PLL 1
1034 +#define CLK_APMIXED_ARMCA7PLL 2
1035 +#define CLK_APMIXED_MAINPLL 3
1036 +#define CLK_APMIXED_UNIVPLL 4
1037 +#define CLK_APMIXED_MMPLL 5
1038 +#define CLK_APMIXED_MSDCPLL 6
1039 +#define CLK_APMIXED_VENCPLL 7
1040 +#define CLK_APMIXED_TVDPLL 8
1041 +#define CLK_APMIXED_MPLL 9
1042 +#define CLK_APMIXED_VCODECPLL 10
1043 +#define CLK_APMIXED_APLL1 11
1044 +#define CLK_APMIXED_APLL2 12
1045 +#define CLK_APMIXED_LVDSPLL 13
1046 +#define CLK_APMIXED_MSDCPLL2 14
1047 +#define CLK_APMIXED_NR_CLK 15
1048 +
1049 +/* INFRA_SYS */
1050 +
1051 +#define CLK_INFRA_DBGCLK 1
1052 +#define CLK_INFRA_SMI 2
1053 +#define CLK_INFRA_AUDIO 3
1054 +#define CLK_INFRA_GCE 4
1055 +#define CLK_INFRA_L2C_SRAM 5
1056 +#define CLK_INFRA_M4U 6
1057 +#define CLK_INFRA_CPUM 7
1058 +#define CLK_INFRA_KP 8
1059 +#define CLK_INFRA_CEC 9
1060 +#define CLK_INFRA_PMICSPI 10
1061 +#define CLK_INFRA_PMICWRAP 11
1062 +#define CLK_INFRA_NR_CLK 12
1063 +
1064 +/* PERI_SYS */
1065 +
1066 +#define CLK_PERI_NFI 1
1067 +#define CLK_PERI_THERM 2
1068 +#define CLK_PERI_PWM1 3
1069 +#define CLK_PERI_PWM2 4
1070 +#define CLK_PERI_PWM3 5
1071 +#define CLK_PERI_PWM4 6
1072 +#define CLK_PERI_PWM5 7
1073 +#define CLK_PERI_PWM6 8
1074 +#define CLK_PERI_PWM7 9
1075 +#define CLK_PERI_PWM 10
1076 +#define CLK_PERI_USB0 11
1077 +#define CLK_PERI_USB1 12
1078 +#define CLK_PERI_AP_DMA 13
1079 +#define CLK_PERI_MSDC30_0 14
1080 +#define CLK_PERI_MSDC30_1 15
1081 +#define CLK_PERI_MSDC30_2 16
1082 +#define CLK_PERI_MSDC30_3 17
1083 +#define CLK_PERI_NLI_ARB 18
1084 +#define CLK_PERI_IRDA 19
1085 +#define CLK_PERI_UART0 20
1086 +#define CLK_PERI_UART1 21
1087 +#define CLK_PERI_UART2 22
1088 +#define CLK_PERI_UART3 23
1089 +#define CLK_PERI_I2C0 24
1090 +#define CLK_PERI_I2C1 25
1091 +#define CLK_PERI_I2C2 26
1092 +#define CLK_PERI_I2C3 27
1093 +#define CLK_PERI_I2C4 28
1094 +#define CLK_PERI_AUXADC 29
1095 +#define CLK_PERI_SPI0 30
1096 +#define CLK_PERI_I2C5 31
1097 +#define CLK_PERI_NFIECC 32
1098 +#define CLK_PERI_SPI 33
1099 +#define CLK_PERI_IRRX 34
1100 +#define CLK_PERI_I2C6 35
1101 +#define CLK_PERI_UART0_SEL 36
1102 +#define CLK_PERI_UART1_SEL 37
1103 +#define CLK_PERI_UART2_SEL 38
1104 +#define CLK_PERI_UART3_SEL 39
1105 +#define CLK_PERI_NR_CLK 40
1106 +
1107 +#endif /* _DT_BINDINGS_CLK_MT8173_H */
1108 diff --git a/include/dt-bindings/reset-controller/mt8173-resets.h b/include/dt-bindings/reset-controller/mt8173-resets.h
1109 new file mode 100644
1110 index 0000000..9464b37
1111 --- /dev/null
1112 +++ b/include/dt-bindings/reset-controller/mt8173-resets.h
1113 @@ -0,0 +1,63 @@
1114 +/*
1115 + * Copyright (c) 2014 MediaTek Inc.
1116 + * Author: Flora Fu, MediaTek
1117 + *
1118 + * This program is free software; you can redistribute it and/or modify
1119 + * it under the terms of the GNU General Public License version 2 as
1120 + * published by the Free Software Foundation.
1121 + *
1122 + * This program is distributed in the hope that it will be useful,
1123 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1124 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1125 + * GNU General Public License for more details.
1126 + */
1127 +
1128 +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173
1129 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8173
1130 +
1131 +/* INFRACFG resets */
1132 +#define MT8173_INFRA_EMI_REG_RST 0
1133 +#define MT8173_INFRA_DRAMC0_A0_RST 1
1134 +#define MT8173_INFRA_APCIRQ_EINT_RST 3
1135 +#define MT8173_INFRA_APXGPT_RST 4
1136 +#define MT8173_INFRA_SCPSYS_RST 5
1137 +#define MT8173_INFRA_KP_RST 6
1138 +#define MT8173_INFRA_PMIC_WRAP_RST 7
1139 +#define MT8173_INFRA_MPIP_RST 8
1140 +#define MT8173_INFRA_CEC_RST 9
1141 +#define MT8173_INFRA_EMI_RST 32
1142 +#define MT8173_INFRA_DRAMC0_RST 34
1143 +#define MT8173_INFRA_APMIXEDSYS_RST 35
1144 +#define MT8173_INFRA_MIPI_DSI_RST 36
1145 +#define MT8173_INFRA_TRNG_RST 37
1146 +#define MT8173_INFRA_SYSIRQ_RST 38
1147 +#define MT8173_INFRA_MIPI_CSI_RST 39
1148 +#define MT8173_INFRA_GCE_FAXI_RST 40
1149 +#define MT8173_INFRA_MMIOMMURST 47
1150 +
1151 +
1152 +/* PERICFG resets */
1153 +#define MT8173_PERI_UART0_SW_RST 0
1154 +#define MT8173_PERI_UART1_SW_RST 1
1155 +#define MT8173_PERI_UART2_SW_RST 2
1156 +#define MT8173_PERI_UART3_SW_RST 3
1157 +#define MT8173_PERI_IRRX_SW_RST 4
1158 +#define MT8173_PERI_PWM_SW_RST 8
1159 +#define MT8173_PERI_AUXADC_SW_RST 10
1160 +#define MT8173_PERI_DMA_SW_RST 11
1161 +#define MT8173_PERI_I2C6_SW_RST 13
1162 +#define MT8173_PERI_NFI_SW_RST 14
1163 +#define MT8173_PERI_THERM_SW_RST 16
1164 +#define MT8173_PERI_MSDC2_SW_RST 17
1165 +#define MT8173_PERI_MSDC3_SW_RST 18
1166 +#define MT8173_PERI_MSDC0_SW_RST 19
1167 +#define MT8173_PERI_MSDC1_SW_RST 20
1168 +#define MT8173_PERI_I2C0_SW_RST 22
1169 +#define MT8173_PERI_I2C1_SW_RST 23
1170 +#define MT8173_PERI_I2C2_SW_RST 24
1171 +#define MT8173_PERI_I2C3_SW_RST 25
1172 +#define MT8173_PERI_I2C4_SW_RST 26
1173 +#define MT8173_PERI_HDMI_SW_RST 29
1174 +#define MT8173_PERI_SPI0_SW_RST 33
1175 +
1176 +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */
1177 --
1178 1.7.10.4
1179
Staging tree of Christian Lamparter