target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch

   1 From 908a87b47af8303c9aa8fb6aa183ca9f8b544d78 Mon Sep 17 00:00:00 2001
   2 From: YH Huang <yh.huang@mediatek.com>
   3 Date: Mon, 11 May 2015 17:26:21 +0800
   4 Subject: [PATCH 27/76] dt-bindings: pwm: add Mediatek display PWM bindings
   5
   6 Document the device-tree binding of Mediatek display PWM.
   7
   8 Signed-off-by: YH Huang <yh.huang@mediatek.com>
   9 ---
  10  .../devicetree/bindings/pwm/pwm-disp-mediatek.txt  |   25 ++++++++++++++++++++
  11  1 file changed, 25 insertions(+)
  12  create mode 100644 Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt
  13
  14 --- /dev/null
  15 +++ b/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt
  16 @@ -0,0 +1,25 @@
  17 +Mediatek display PWM controller
  18 +
  19 +Required properties:
  20 + - compatible: should be "mediatek,<name>-disp-pwm"
  21 +   - "mediatek,mt8173-disp-pwm": found on mt8173 SoC
  22 +   - "mediatek,mt6595-disp-pwm": found on mt6595 SoC
  23 + - reg: physical base address and length of the controller's registers
  24 + - #pwm-cells: must be 2. See pwm.txt in this directory
  25 +   for a description of the cell format
  26 + - clocks: phandle and clock specifier of the PWM reference clock
  27 + - clock-names: must contain the following
  28 +   - "main": clock used to generate PWM signals
  29 +   - "mm": sync signals from the modules of mmsys
  30 +
  31 +Example:
  32 +       pwm0: pwm@1401e000 {
  33 +               compatible = "mediatek,mt8173-disp-pwm",
  34 +                            "mediatek,mt6595-disp-pwm";
  35 +               reg = <0 0x1401e000 0 0x1000>;
  36 +               #pwm-cells = <2>;
  37 +               clocks = <&mmsys MM_DISP_PWM026M>,
  38 +                        <&mmsys MM_DISP_PWM0MM>;
  39 +               clock-names = "main",
  40 +                             "mm";
  41 +       };