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kernel: update 4.1 to 4.1.13
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches / 0061-arm-mediatek-add-mt7623-clock.patch
1 From 7342787e992a70443081b9203d2131cbf6bc3562 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 27 Jun 2015 13:12:38 +0200
4 Subject: [PATCH 61/76] arm: mediatek: add mt7623 clock
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/clk/mediatek/Makefile | 1 +
9 drivers/clk/mediatek/clk-mt7623.c | 634 ++++++++++++++++++++++++++++++++
10 include/dt-bindings/clock/mt7623-clk.h | 173 +++++++++
11 3 files changed, 808 insertions(+)
12 create mode 100644 drivers/clk/mediatek/clk-mt7623.c
13 create mode 100644 include/dt-bindings/clock/mt7623-clk.h
14
15 --- a/drivers/clk/mediatek/Makefile
16 +++ b/drivers/clk/mediatek/Makefile
17 @@ -1,4 +1,5 @@
18 obj-y += clk-mtk.o clk-pll.o clk-gate.o
19 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
20 +obj-y += clk-mt7623.o
21 obj-y += clk-mt8135.o
22 obj-y += clk-mt8173.o
23 --- /dev/null
24 +++ b/drivers/clk/mediatek/clk-mt7623.c
25 @@ -0,0 +1,634 @@
26 +/*
27 + * Copyright (c) 2014 MediaTek Inc.
28 + * Author: James Liao <jamesjj.liao@mediatek.com>
29 + *
30 + * This program is free software; you can redistribute it and/or modify
31 + * it under the terms of the GNU General Public License version 2 as
32 + * published by the Free Software Foundation.
33 + *
34 + * This program is distributed in the hope that it will be useful,
35 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 + * GNU General Public License for more details.
38 + */
39 +
40 +#include <linux/of.h>
41 +#include <linux/of_address.h>
42 +#include <linux/slab.h>
43 +#include <linux/mfd/syscon.h>
44 +#include <dt-bindings/clock/mt7623-clk.h>
45 +
46 +#include "clk-mtk.h"
47 +#include "clk-gate.h"
48 +
49 +static DEFINE_SPINLOCK(mt7623_clk_lock);
50 +
51 +static struct clk_onecell_data *mt7623_top_clk_data;
52 +static struct clk_onecell_data *mt7623_pll_clk_data;
53 +
54 +static void mtk_clk_enable_critical(void)
55 +{
56 + if (!mt7623_top_clk_data || !mt7623_pll_clk_data)
57 + return;
58 +
59 + clk_prepare_enable(mt7623_pll_clk_data->clks[CLK_APMIXED_ARMPLL]);
60 + clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_MEM_SEL]);
61 + clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_DDR_SEL]);
62 + clk_prepare_enable(mt7623_top_clk_data->clks[CLK_TOP_RTC_SEL]);
63 +}
64 +
65 +static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
66 + FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
67 + FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
68 + FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
69 + FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
70 +};
71 +
72 +static const struct mtk_fixed_factor top_divs[] __initconst = {
73 + FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_650m", "mainpll", 1, 2),
74 + FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_433p3m", "mainpll", 1, 3),
75 + FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_260m", "mainpll", 1, 5),
76 + FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_185p6m", "mainpll", 1, 7),
77 +
78 + FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
79 + FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
80 + FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
81 + FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
82 + FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
83 +
84 + FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll", 1, 4),
85 + FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll", 1, 8),
86 + FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll", 1, 16),
87 + FACTOR(CLK_TOP_AUDPLL_24, "audpll_d24", "audpll", 1, 24),
88 +
89 + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
90 + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
91 + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
92 + FACTOR(CLK_TOP_LVDS_ETH, "lvdspll_eth", "lvdspll", 1, 16),
93 +
94 + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
95 +
96 + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
97 +
98 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll_650m", 1, 2),
99 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll_650m", 1, 4),
100 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll_650m", 1, 8),
101 + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll_650m", 1, 16),
102 + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll_650m", 1, 2),
103 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll_650m", 1, 4),
104 + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll_650m", 1, 8),
105 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll_650m", 1, 2),
106 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll_650m", 1, 4),
107 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll_650m", 1, 2),
108 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll_650m", 1, 4),
109 + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_433p3m", 1, 1),
110 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_260m", 1, 1),
111 + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll_185p6m", 1, 1),
112 +
113 + FACTOR(CLK_TOP_TVDPLL_d2, "tvdpll_d2", "tvdpll", 1, 2),
114 + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
115 +
116 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
117 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
118 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
119 + FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
120 +
121 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
122 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
123 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
124 +
125 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
126 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
127 + FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
128 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
129 + FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
130 +
131 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
132 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
133 + FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
134 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
135 +
136 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
137 + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
138 +
139 +
140 + FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
141 +};
142 +
143 +static const char * const axi_parents[] __initconst = {
144 + "clk26m",
145 + "syspll1_d2",
146 + "syspll_d5",
147 + "syspll1_d4",
148 + "univpll_d5",
149 + "univpll2_d2",
150 + "dmpll_ck",
151 + "dmpll_d2"
152 +};
153 +
154 +static const char * const mem_parents[] __initconst = {
155 + "clk26m",
156 + "dmpll_ck",
157 +};
158 +
159 +static const char * const ddr_parents[] __initconst = {
160 + "clk26m",
161 + "syspll1_d8",
162 +};
163 +
164 +static const char * const mm_parents[] __initconst = {
165 + "clk26m",
166 + "clk26m",
167 + "vencpll_ck",
168 + "syspll1_d2",
169 + "syspll1_d4",
170 + "univpll_d5",
171 + "univpll1_d2",
172 + "univpll2_d2",
173 + "dmpll_ck"
174 +};
175 +
176 +static const char * const pwm_parents[] __initconst = {
177 + "clk26m",
178 + "univpll2_d4",
179 + "univpll3_d2",
180 + "univpll1_d4",
181 +};
182 +
183 +static const char * const vdec_parents[] __initconst = {
184 + "clk26m",
185 + "syspll1_d2",
186 + "syspll_d5",
187 + "syspll1_d4",
188 + "univpll_d5",
189 + "univpll2_d2",
190 + "univpll2_d4",
191 + "msdcpll_d2",
192 + "mmpll_d2",
193 +};
194 +
195 +static const char * const mfg_parents[] __initconst = {
196 + "clk26m",
197 + "mmpll_ck",
198 + "dmpll_x2_ck",
199 + "msdcpll_ck",
200 + "clk26m",
201 + "syspll_d3",
202 + "univpll_d3",
203 + "univpll1_d2",
204 +};
205 +
206 +static const char * const cam_parents[] __initconst = {
207 + "clk26m",
208 + "univpll_d26",
209 + "univpll2_d2",
210 + "syspll3_d2",
211 + "syspll3_d4",
212 + "msdcpll_d2",
213 + "mmpll_d2",
214 + "clk26m",
215 +};
216 +
217 +static const char * const uart_parents[] __initconst = {
218 + "clk26m",
219 + "univpll2_d8",
220 +};
221 +
222 +static const char * const spi_parents[] __initconst = {
223 + "clk26m",
224 + "syspll3_d2",
225 + "syspll4_d2",
226 + "univpll2_d4",
227 + "univpll1_d8",
228 +};
229 +
230 +static const char * const usb20_parents[] __initconst = {
231 + "clk26m",
232 + "univpll1_d8",
233 + "univpll3_d4",
234 + "clk26m",
235 +};
236 +
237 +static const char * const msdc_30_0_parents[] __initconst = {
238 + "clk26m",
239 + "msdcpll_d2",
240 + "syspll2_d2",
241 + "syspll1_d4",
242 + "univpll1_d4",
243 + "univpll2_d4",
244 + "clk26m",
245 + "clk26m",
246 +};
247 +
248 +static const char * const msdc_30_1_parents[] __initconst = {
249 + "clk26m",
250 + "msdcpll_d2",
251 + "syspll2_d2",
252 + "syspll1_d4",
253 + "univpll1_d4",
254 + "univpll2_d4",
255 + "clk26m",
256 + "clk26m",
257 +};
258 +
259 +static const char * const msdc_30_2_parents[] __initconst = {
260 + "clk26m",
261 + "msdcpll_d2",
262 + "syspll2_d2",
263 + "syspll1_d4",
264 + "univpll1_d4",
265 + "univpll2_d4",
266 + "clk26m",
267 + "clk26m",
268 +};
269 +
270 +static const char * const audio_parents[] __initconst = {
271 + "f_f26m_ck",
272 + "syspll1_d16",
273 +};
274 +
275 +static const char * const audio_intbus_parents[] __initconst = {
276 + "clk26m",
277 + "syspll1_d4",
278 + "syspll3_d2",
279 + "syspll4_d2",
280 + "univpll3_d2",
281 + "univpll2_d4",
282 +};
283 +
284 +static const char * const pmic_spi_parents[] __initconst = {
285 + "clk26m",
286 + "syspll1_d8",
287 + "syspll2_d4",
288 + "syspll4_d2",
289 + "syspll3_d4",
290 + "syspll2_d8",
291 + "syspll1_d16",
292 + "univpll3_d4",
293 + "univpll_d26",
294 + "dmpll_d2",
295 + "dmpll_d4",
296 +};
297 +
298 +static const char * const scp_parents[] __initconst = {
299 + "clk26m",
300 + "syspll1_d8",
301 + "dmpll_d2",
302 + "dmpll_d4",
303 +};
304 +
305 +static const char * const dpi0_parents[] __initconst = {
306 + "clk26m",
307 + "mipipll",
308 + "mipipll_d2",
309 + "mipipll_d4",
310 + "lvdspll",
311 + "lvdspll_d2",
312 + "lvdspll_d4",
313 + "lvdspll_d8",
314 +};
315 +
316 +static const char * const dpi1_parents[] __initconst = {
317 + "clk26m",
318 + "tvdpll",
319 + "tvdpll_d2",
320 + "tvdpll_d4",
321 +};
322 +
323 +static const char * const tve_parents[] __initconst = {
324 + "clk26m",
325 + "mipipll",
326 + "mipipll_d2",
327 + "mipipll_d4",
328 + "clk26m",
329 + "tvdpll",
330 + "tvdpll_d2",
331 + "tvdpll_d4",
332 +};
333 +
334 +static const char * const apll_parents[] __initconst = {
335 + "clk26m",
336 + "audpll",
337 + "audpll_d4",
338 + "audpll_d8",
339 + "audpll_d16",
340 + "audpll_d24",
341 + "clk26m",
342 + "clk26m",
343 +};
344 +
345 +static const char * const dpilvds_parents[] __initconst = {
346 + "clk26m",
347 + "lvdspll",
348 + "lvdspll_d2",
349 + "lvdspll_d4",
350 + "lvdspll_d8",
351 + "fpc_ck",
352 + "clk26m",
353 + "clk26m",
354 +};
355 +
356 +static const char * const rtc_parents[] __initconst = {
357 + "clk32k",
358 + "external_32k",
359 + "clk26m",
360 + "univpll3_d8",
361 +};
362 +
363 +static const char * const nfi2x_parents[] __initconst = {
364 + "clk26m",
365 + "syspll2_d2",
366 + "syspll_d7",
367 + "univpll3_d2",
368 + "syspll2_d4",
369 + "univpll3_d4",
370 + "syspll4_d4",
371 + "clk26m",
372 +};
373 +
374 +static const char * const eth_parents[] __initconst = {
375 + "clk26m",
376 + "syspll3_d4",
377 + "univpll2_d8",
378 + "lvdspll_eth",
379 + "univpll_d26",
380 + "syspll2_d8",
381 + "syspll4_d4",
382 + "univpll3_d8",
383 +};
384 +
385 +static const struct mtk_composite top_muxes[] __initconst = {
386 + /* CLK_CFG_0 */
387 + MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
388 + 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
389 + MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 2, 15),
390 + MUX_GATE(CLK_TOP_DDR_SEL, "ddr_sel", ddr_parents, 0x0040, 16, 2, 23),
391 + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
392 + 0x0140, 24, 3, INVALID_MUX_GATE_BIT),
393 + /* CLK_CFG_1 */
394 + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
395 + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
396 + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 16, 3, 23),
397 + MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0050, 24, 3, 31),
398 + /* CLK_CFG_2 */
399 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7),
400 + MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 8, 3, 15),
401 + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 16, 2, 23),
402 + MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc_30_0_sel", msdc_30_0_parents, 0x0060, 24, 3, 31),
403 + /* CLK_CFG_3 */
404 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc_30_1_sel", msdc_30_1_parents, 0x0070, 0, 3, 7),
405 + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc_30_2_sel", msdc_30_2_parents, 0x0070, 8, 3, 15),
406 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0070, 16, 1, 23),
407 + MUX_GATE(CLK_TOP_AUDIO_INTBUS_SEL,
408 + "audio_intbus_sel", audio_intbus_parents, 0x0070, 24, 3, 31),
409 + /* CLK_CFG_4 */
410 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmic_spi_parents, 0x0080, 0, 4, 7),
411 + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15),
412 + MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23),
413 + MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0080, 24, 2, 31),
414 + /* CLK_CFG_5 */
415 + MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7),
416 + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0090, 16, 3, 23),
417 + MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0090, 24, 3, 31),
418 + /* CLK_CFG_6 */
419 + MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00a0, 0, 2, 7),
420 + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00a0, 8, 3, 15),
421 + MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x00a0, 16, 3, 23),
422 +};
423 +
424 +static const struct mtk_gate_regs infra_cg_regs = {
425 + .set_ofs = 0x0040,
426 + .clr_ofs = 0x0044,
427 + .sta_ofs = 0x0048,
428 +};
429 +
430 +#define GATE_ICG(_id, _name, _parent, _shift) { \
431 + .id = _id, \
432 + .name = _name, \
433 + .parent_name = _parent, \
434 + .regs = &infra_cg_regs, \
435 + .shift = _shift, \
436 + .ops = &mtk_clk_gate_ops_setclr, \
437 + }
438 +
439 +static const struct mtk_gate infra_clks[] __initconst = {
440 + GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
441 + GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
442 + GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
443 + GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "axi_sel", 5),
444 + GATE_ICG(CLK_INFRA_EFUSE, "l2c_sram_ck", "axi_sel", 5),
445 + GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
446 + GATE_ICG(CLK_INFRA_CONNMCU, "connmcu_ck", "axi_sel", 8),
447 + GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 8),
448 + GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
449 + GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
450 + GATE_ICG(CLK_INFRA_CEC, "cec_ck", "axi_sel", 16),
451 + GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 16),
452 + GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
453 + GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
454 +};
455 +
456 +static const struct mtk_gate_regs peri0_cg_regs = {
457 + .set_ofs = 0x0008,
458 + .clr_ofs = 0x0010,
459 + .sta_ofs = 0x0018,
460 +};
461 +
462 +static const struct mtk_gate_regs peri1_cg_regs = {
463 + .set_ofs = 0x000c,
464 + .clr_ofs = 0x0014,
465 + .sta_ofs = 0x001c,
466 +};
467 +
468 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
469 + .id = _id, \
470 + .name = _name, \
471 + .parent_name = _parent, \
472 + .regs = &peri0_cg_regs, \
473 + .shift = _shift, \
474 + .ops = &mtk_clk_gate_ops_setclr, \
475 + }
476 +
477 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
478 + .id = _id, \
479 + .name = _name, \
480 + .parent_name = _parent, \
481 + .regs = &peri1_cg_regs, \
482 + .shift = _shift, \
483 + .ops = &mtk_clk_gate_ops_setclr, \
484 + }
485 +
486 +static const struct mtk_gate peri_gates[] __initconst = {
487 + /* PERI0 */
488 + GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
489 + GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
490 + GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
491 + GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
492 + GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
493 + GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
494 + GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
495 + GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
496 + GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
497 + GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
498 + GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
499 + GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
500 + GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
501 + GATE_PERI0(CLK_PERI_MSDC20_1, "msdc_20_1_ck", "msdc_30_0_sel", 13),
502 + GATE_PERI0(CLK_PERI_MSDC20_2, "msdc_20_2_ck", "msdc_30_1_sel", 14),
503 + GATE_PERI0(CLK_PERI_MSDC30_1, "msdc_30_1_ck", "msdc_30_2_sel", 15),
504 + GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 16),
505 + GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 17),
506 + GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 18),
507 + GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 19),
508 + GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 20),
509 + GATE_PERI0(CLK_PERI_BTIF, "btif_ck", "axi_sel", 21),
510 + GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 22),
511 + GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 23),
512 + GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 24),
513 + GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 25),
514 + GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "axi_sel", 26),
515 + GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 27),
516 + GATE_PERI0(CLK_PERI_ETH, "eth_ck", "eth_sel", 28),
517 + GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu", "axi_sel", 29),
518 + GATE_PERI0(CLK_PERI_USB1_MCU, "usb1_mcu","axi_sel", 30),
519 + GATE_PERI0(CLK_PERI_USB_SLV, "usb_slv", "axi_sel", 31),
520 +
521 + /* PERI1 */
522 + GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 0),
523 + GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "axi_sel", 1),
524 + GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "axi_sel", 2),
525 +};
526 +
527 +static const char * const uart_ck_sel_parents[] __initconst = {
528 + "clk26m",
529 + "uart_sel",
530 +};
531 +
532 +static const struct mtk_composite peri_clks[] __initconst = {
533 + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
534 + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
535 + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
536 + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
537 +};
538 +
539 +static void __init mtk_topckgen_init(struct device_node *node)
540 +{
541 + struct clk_onecell_data *clk_data;
542 + void __iomem *base;
543 + int r;
544 +
545 + base = of_iomap(node, 0);
546 + if (!base) {
547 + pr_err("%s(): ioremap failed\n", __func__);
548 + return;
549 + }
550 +
551 + mt7623_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
552 +
553 + mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
554 + mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
555 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
556 + &mt7623_clk_lock, clk_data);
557 +
558 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
559 + if (r)
560 + pr_err("%s(): could not register clock provider: %d\n",
561 + __func__, r);
562 +
563 + mtk_clk_enable_critical();
564 +}
565 +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt7623-topckgen", mtk_topckgen_init);
566 +
567 +static void __init mtk_infrasys_init(struct device_node *node)
568 +{
569 + struct clk_onecell_data *clk_data;
570 + int r;
571 +
572 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
573 +
574 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
575 + clk_data);
576 +
577 + clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
578 +
579 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
580 + if (r)
581 + pr_err("%s(): could not register clock provider: %d\n",
582 + __func__, r);
583 +
584 + mtk_register_reset_controller(node, 2, 0x30);
585 +}
586 +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt7623-infracfg", mtk_infrasys_init);
587 +
588 +static void __init mtk_pericfg_init(struct device_node *node)
589 +{
590 + struct clk_onecell_data *clk_data;
591 + int r;
592 + void __iomem *base;
593 +
594 + base = of_iomap(node, 0);
595 + if (!base) {
596 + pr_err("%s(): ioremap failed\n", __func__);
597 + return;
598 + }
599 +
600 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
601 +
602 + mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
603 + clk_data);
604 + mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
605 + &mt7623_clk_lock, clk_data);
606 +
607 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
608 + if (r)
609 + pr_err("%s(): could not register clock provider: %d\n",
610 + __func__, r);
611 +
612 + mtk_register_reset_controller(node, 2, 0);
613 +}
614 +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt7623-pericfg", mtk_pericfg_init);
615 +
616 +#define MT7623_PLL_FMAX (2000 * MHZ)
617 +#define CON0_MT7623_RST_BAR BIT(27)
618 +
619 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
620 + .id = _id, \
621 + .name = _name, \
622 + .reg = _reg, \
623 + .pwr_reg = _pwr_reg, \
624 + .en_mask = _en_mask, \
625 + .flags = _flags, \
626 + .rst_bar_mask = CON0_MT7623_RST_BAR, \
627 + .fmax = MT7623_PLL_FMAX, \
628 + .pcwbits = _pcwbits, \
629 + .pd_reg = _pd_reg, \
630 + .pd_shift = _pd_shift, \
631 + .tuner_reg = _tuner_reg, \
632 + .pcw_reg = _pcw_reg, \
633 + .pcw_shift = _pcw_shift, \
634 + }
635 +
636 +static const struct mtk_pll_data plls[] = {
637 + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
638 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0x78000001, HAVE_RST_BAR, 21, 0x214, 6, 0x0, 0x214, 0),
639 + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xFC000001, HAVE_RST_BAR, 7, 0x224, 6, 0x0, 0x224, 0),
640 + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0, 21, 0x254, 6, 0x0, 0x258, 0),
641 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 6, 0x0, 0x244, 0),
642 + PLL(CLK_APMIXED_AUDPLL, "audpll", 0x250, 0x25c, 0x00000001, 0, 31, 0x2e8, 6, 0x2f8, 0x254, 0),
643 + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x260, 0x26c, 0x00000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
644 + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x270, 0x27c, 0x00000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
645 +};
646 +
647 +static void __init mtk_apmixedsys_init(struct device_node *node)
648 +{
649 + struct clk_onecell_data *clk_data;
650 +
651 + mt7623_pll_clk_data = clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
652 + if (!clk_data)
653 + return;
654 +
655 + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
656 + mtk_clk_enable_critical();
657 +}
658 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt7623-apmixedsys",
659 + mtk_apmixedsys_init);
660 --- /dev/null
661 +++ b/include/dt-bindings/clock/mt7623-clk.h
662 @@ -0,0 +1,173 @@
663 +/*
664 + * Copyright c 2014 MediaTek Inc.
665 + * Author: James Liao <jamesjj.liao@mediatek.com>
666 + *
667 + * This program is free software; you can redistribute it and/or modify
668 + * it under the terms of the GNU General Public License version 2 as
669 + * published by the Free Software Foundation.
670 + *
671 + * This program is distributed in the hope that it will be useful,
672 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
673 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
674 + * GNU General Public License for more details.
675 + */
676 +
677 +#ifndef _DT_BINDINGS_CLK_MT7623_H
678 +#define _DT_BINDINGS_CLK_MT7623_H
679 +
680 +/* TOPCKGEN */
681 +
682 +#define CLK_TOP_AUDPLL_24 1
683 +#define CLK_TOP_AUDPLL_D16 2
684 +#define CLK_TOP_AUDPLL_D4 3
685 +#define CLK_TOP_AUDPLL_D8 4
686 +#define CLK_TOP_CLKPH_MCK 5
687 +#define CLK_TOP_CPUM_TCK_IN 6
688 +#define CLK_TOP_DSI0_LNTC_DSICLK 7
689 +#define CLK_TOP_HDMITX_CLKDIG_CTS 8
690 +#define CLK_TOP_LVDS_ETH 9
691 +#define CLK_TOP_LVDSPLL_D2 10
692 +#define CLK_TOP_LVDSPLL_D4 11
693 +#define CLK_TOP_LVDSPLL_D8 12
694 +#define CLK_TOP_MAINPLL_230P3M 13
695 +#define CLK_TOP_MAINPLL_322P4M 14
696 +#define CLK_TOP_MAINPLL_537P3M 15
697 +#define CLK_TOP_MAINPLL_806M 16
698 +#define CLK_TOP_MEMPLL_MCK_D4 17
699 +#define CLK_TOP_MMPLL_D2 18
700 +#define CLK_TOP_MSDCPLL_D2 19
701 +#define CLK_TOP_SYSPLL1_D16 20
702 +#define CLK_TOP_SYSPLL1_D2 21
703 +#define CLK_TOP_SYSPLL1_D4 22
704 +#define CLK_TOP_SYSPLL1_D8 23
705 +#define CLK_TOP_SYSPLL2_D2 24
706 +#define CLK_TOP_SYSPLL2_D4 25
707 +#define CLK_TOP_SYSPLL2_D8 26
708 +#define CLK_TOP_SYSPLL3_D2 27
709 +#define CLK_TOP_SYSPLL3_D4 28
710 +#define CLK_TOP_SYSPLL4_D2 29
711 +#define CLK_TOP_SYSPLL4_D4 30
712 +#define CLK_TOP_SYSPLL_D3 31
713 +#define CLK_TOP_SYSPLL_D5 32
714 +#define CLK_TOP_SYSPLL_D7 33
715 +#define CLK_TOP_TVDPLL_d2 34
716 +#define CLK_TOP_TVDPLL_D4 35
717 +#define CLK_TOP_UNIVPLL_178P3M 36
718 +#define CLK_TOP_UNIVPLL1_D10 37
719 +#define CLK_TOP_UNIVPLL1_D2 38
720 +#define CLK_TOP_UNIVPLL1_D4 39
721 +#define CLK_TOP_UNIVPLL1_D6 40
722 +#define CLK_TOP_UNIVPLL1_D8 41
723 +#define CLK_TOP_UNIVPLL_249P6M 42
724 +#define CLK_TOP_UNIVPLL2_D2 43
725 +#define CLK_TOP_UNIVPLL2_D4 44
726 +#define CLK_TOP_UNIVPLL2_D6 45
727 +#define CLK_TOP_UNIVPLL2_D8 46
728 +#define CLK_TOP_UNIVPLL_416M 47
729 +#define CLK_TOP_UNIVPLL_48M 48
730 +#define CLK_TOP_UNIVPLL_624M 49
731 +#define CLK_TOP_UNIVPLL_D26 50
732 +#define CLK_TOP_UNIVPLL_D5 51
733 +#define CLK_TOP_APLL_SEL 52
734 +#define CLK_TOP_AUDIO_INTBUS_SEL 53
735 +#define CLK_TOP_AUDIO_SEL 54
736 +#define CLK_TOP_AXI_SEL 55
737 +#define CLK_TOP_CAM_SEL 56
738 +#define CLK_TOP_DDR_SEL 57
739 +#define CLK_TOP_DPI0_SEL 58
740 +#define CLK_TOP_DPI1_SEL 59
741 +#define CLK_TOP_DPILVDS_SEL 60
742 +#define CLK_TOP_ETH_SEL 61
743 +#define CLK_TOP_MEM_SEL 62
744 +#define CLK_TOP_MFG_SEL 63
745 +#define CLK_TOP_MM_SEL 64
746 +#define CLK_TOP_MSDC30_0_SEL 65
747 +#define CLK_TOP_MSDC30_1_SEL 66
748 +#define CLK_TOP_MSDC30_2_SEL 67
749 +#define CLK_TOP_NFI2X_SEL 68
750 +#define CLK_TOP_PMICSPI_SEL 69
751 +#define CLK_TOP_PWM_SEL 70
752 +#define CLK_TOP_RTC_SEL 71
753 +#define CLK_TOP_SCP_SEL 72
754 +#define CLK_TOP_SPI_SEL 73
755 +#define CLK_TOP_TVE_SEL 74
756 +#define CLK_TOP_UART_SEL 75
757 +#define CLK_TOP_USB20_SEL 76
758 +#define CLK_TOP_VDEC_SEL 77
759 +#define CLK_TOP_NR_CLK 78
760 +
761 +/* APMIXED_SYS */
762 +
763 +#define CLK_APMIXED_ARMPLL 1
764 +#define CLK_APMIXED_MAINPLL 2
765 +#define CLK_APMIXED_MSDCPLL 3
766 +#define CLK_APMIXED_UNIVPLL 4
767 +#define CLK_APMIXED_MMPLL 5
768 +#define CLK_APMIXED_VENCPLL 6
769 +#define CLK_APMIXED_TVDPLL 7
770 +#define CLK_APMIXED_LVDSPLL 8
771 +#define CLK_APMIXED_AUDPLL 9
772 +
773 +/* INFRA_SYS */
774 +
775 +#define CLK_INFRA_DBGCLK 0
776 +#define CLK_INFRA_SMI 1
777 +#define CLK_INFRA_AUDIO 5
778 +#define CLK_INFRA_EFUSE 6
779 +#define CLK_INFRA_L2C_SRAM 7
780 +#define CLK_INFRA_M4U 8
781 +#define CLK_INFRA_CONNMCU 12
782 +#define CLK_INFRA_TRNG 13
783 +#define CLK_INFRA_CPUM 15
784 +#define CLK_INFRA_KP 16
785 +#define CLK_INFRA_CEC 18
786 +#define CLK_INFRA_IRRX 19
787 +#define CLK_INFRA_PMICSPI 22
788 +#define CLK_INFRA_PMIC_WRAP 23
789 +#define CLK_INFRA_NR_CLK 24
790 +
791 +/* PERI_SYS */
792 +
793 +#define CLK_PERI_NFI 0
794 +#define CLK_PERI_THERM 1
795 +#define CLK_PERI_PWM1 2
796 +#define CLK_PERI_PWM2 3
797 +#define CLK_PERI_PWM3 4
798 +#define CLK_PERI_PWM4 5
799 +#define CLK_PERI_PWM5 6
800 +#define CLK_PERI_PWM6 7
801 +#define CLK_PERI_PWM7 8
802 +#define CLK_PERI_PWM 9
803 +#define CLK_PERI_USB0 10
804 +#define CLK_PERI_USB1 11
805 +#define CLK_PERI_AP_DMA 12
806 +#define CLK_PERI_MSDC20_1 13
807 +#define CLK_PERI_MSDC20_2 14
808 +#define CLK_PERI_MSDC30_1 15
809 +#define CLK_PERI_NLI 16
810 +#define CLK_PERI_UART0 17
811 +#define CLK_PERI_UART1 18
812 +#define CLK_PERI_UART2 19
813 +#define CLK_PERI_UART3 20
814 +#define CLK_PERI_BTIF 21
815 +#define CLK_PERI_I2C0 22
816 +#define CLK_PERI_I2C1 23
817 +#define CLK_PERI_I2C2 24
818 +#define CLK_PERI_I2C3 25
819 +#define CLK_PERI_AUXADC 26
820 +#define CLK_PERI_SPI0 27
821 +#define CLK_PERI_ETH 28
822 +#define CLK_PERI_USB0_MCU 29
823 +#define CLK_PERI_USB1_MCU 30
824 +#define CLK_PERI_USB_SLV 31
825 +#define CLK_PERI_GCPU 32
826 +#define CLK_PERI_NFI_ECC 33
827 +#define CLK_PERI_NFI_PAD 34
828 +#define CLK_PERI_UART0_SEL 35
829 +#define CLK_PERI_UART1_SEL 36
830 +#define CLK_PERI_UART2_SEL 37
831 +#define CLK_PERI_UART3_SEL 38
832 +#define CLK_PERI_NR_CLK 39
833 +
834 +#endif /* _DT_BINDINGS_CLK_MT7623_H */
835 +
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