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kernel: update 4.1 to 4.1.13
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches / 0069-arm-mediatek-add-mt7623-support-to-pmic-wrapper.patch
1 From 0ec1ddd9233579b6d6dc0df325e870c5560344be Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 28 Jun 2015 19:50:51 +0200
4 Subject: [PATCH 69/76] arm: mediatek: add mt7623 support to pmic-wrapper
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/soc/mediatek/mtk-pmic-wrap.c | 345 +++++++++++++++++++++++++++++-----
9 1 file changed, 296 insertions(+), 49 deletions(-)
10
11 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
12 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
13 @@ -31,6 +31,13 @@
14 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
15 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
16
17 +#define PWRAP_MT7623_AUXADC_CON21 0x076C
18 +#define PWRAP_MT7623_AUXADC_ADC12 0x072C
19 +#define PWRAP_MT7623_AUXADC_ADC13 0x072E
20 +#define PWRAP_MT7623_AUXADC_ADC14 0x0730
21 +#define PWRAP_MT7623_AUXADC_CON2 0x0746
22 +#define PWRAP_MT7623_AUXADC_CON3 0x0748
23 +
24 /* macro for wrapper status */
25 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
26 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
27 @@ -61,32 +68,104 @@
28 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
29
30 /* macro for slave device wrapper registers */
31 -#define PWRAP_DEW_BASE 0xbc00
32 -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
33 -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
34 -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
35 -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
36 -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
37 -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
38 -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
39 -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
40 -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
41 -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
42 -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
43 -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
44 -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
45 -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
46 -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
47 -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
48 -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
49 -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
50 -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
51 -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
52 -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
53 -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
54 -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
55 -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
56 -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
57 +enum pwrap_dew_regs {
58 + PWRAP_DEW_EVENT_OUT_EN,
59 + PWRAP_DEW_DIO_EN,
60 + PWRAP_DEW_EVENT_SRC_EN,
61 + PWRAP_DEW_EVENT_SRC,
62 + PWRAP_DEW_EVENT_FLAG,
63 + PWRAP_DEW_READ_TEST,
64 + PWRAP_DEW_WRITE_TEST,
65 + PWRAP_DEW_CRC_EN,
66 + PWRAP_DEW_CRC_VAL,
67 + PWRAP_DEW_MON_GRP_SEL,
68 + PWRAP_DEW_MON_FLAG_SEL,
69 + PWRAP_DEW_EVENT_TEST,
70 + PWRAP_DEW_CIPHER_KEY_SEL,
71 + PWRAP_DEW_CIPHER_IV_SEL,
72 + PWRAP_DEW_CIPHER_LOAD,
73 + PWRAP_DEW_CIPHER_START,
74 + PWRAP_DEW_CIPHER_RDY,
75 + PWRAP_DEW_CIPHER_MODE,
76 + PWRAP_DEW_CIPHER_SWRST,
77 +
78 + /* MT7623 only regs */
79 + PWRAP_DEW_CIPHER_EN,
80 + PWRAP_DEW_RDDMY_NO,
81 +
82 + /* MT8173 only regs */
83 + PWRAP_DEW_CIPHER_IV0,
84 + PWRAP_DEW_CIPHER_IV1,
85 + PWRAP_DEW_CIPHER_IV2,
86 + PWRAP_DEW_CIPHER_IV3,
87 + PWRAP_DEW_CIPHER_IV4,
88 + PWRAP_DEW_CIPHER_IV5,
89 +};
90 +
91 +static int mt7623_dew_regs[] = {
92 + [PWRAP_DEW_DIO_EN] = 0x18a,
93 + [PWRAP_DEW_READ_TEST] = 0x18c,
94 + [PWRAP_DEW_WRITE_TEST] = 0x18e,
95 + [PWRAP_DEW_CRC_EN] = 0x192,
96 + [PWRAP_DEW_CRC_VAL] = 0x194,
97 + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x198,
98 + [PWRAP_DEW_CIPHER_IV_SEL] = 0x19a,
99 + [PWRAP_DEW_CIPHER_EN] = 0x19c,
100 + [PWRAP_DEW_CIPHER_RDY] = 0x19e,
101 + [PWRAP_DEW_CIPHER_MODE] = 0x1a0,
102 + [PWRAP_DEW_CIPHER_SWRST] = 0x1a2,
103 + [PWRAP_DEW_RDDMY_NO] = 0x1a4,
104 +};
105 +
106 +static int mt8135_dew_regs[] = {
107 + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
108 + [PWRAP_DEW_DIO_EN] = 0x2,
109 + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
110 + [PWRAP_DEW_EVENT_SRC] = 0x6,
111 + [PWRAP_DEW_EVENT_FLAG] = 0x8,
112 + [PWRAP_DEW_READ_TEST] = 0xa,
113 + [PWRAP_DEW_WRITE_TEST] = 0xc,
114 + [PWRAP_DEW_CRC_EN] = 0xe,
115 + [PWRAP_DEW_CRC_VAL] = 0x10,
116 + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
117 + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
118 + [PWRAP_DEW_EVENT_TEST] = 0x16,
119 + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
120 + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
121 + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
122 + [PWRAP_DEW_CIPHER_START] = 0x1e,
123 + [PWRAP_DEW_CIPHER_RDY] = 0x20,
124 + [PWRAP_DEW_CIPHER_MODE] = 0x22,
125 + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
126 +};
127 +
128 +static int mt8173_dew_regs[] = {
129 + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
130 + [PWRAP_DEW_DIO_EN] = 0x2,
131 + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
132 + [PWRAP_DEW_EVENT_SRC] = 0x6,
133 + [PWRAP_DEW_EVENT_FLAG] = 0x8,
134 + [PWRAP_DEW_READ_TEST] = 0xa,
135 + [PWRAP_DEW_WRITE_TEST] = 0xc,
136 + [PWRAP_DEW_CRC_EN] = 0xe,
137 + [PWRAP_DEW_CRC_VAL] = 0x10,
138 + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
139 + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
140 + [PWRAP_DEW_EVENT_TEST] = 0x16,
141 + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
142 + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
143 + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
144 + [PWRAP_DEW_CIPHER_START] = 0x1e,
145 + [PWRAP_DEW_CIPHER_RDY] = 0x20,
146 + [PWRAP_DEW_CIPHER_MODE] = 0x22,
147 + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
148 + [PWRAP_DEW_CIPHER_IV0] = 0x26,
149 + [PWRAP_DEW_CIPHER_IV1] = 0x28,
150 + [PWRAP_DEW_CIPHER_IV2] = 0x2a,
151 + [PWRAP_DEW_CIPHER_IV3] = 0x2c,
152 + [PWRAP_DEW_CIPHER_IV4] = 0x2e,
153 + [PWRAP_DEW_CIPHER_IV5] = 0x30,
154 +};
155
156 enum pwrap_regs {
157 PWRAP_MUX_SEL,
158 @@ -162,7 +241,7 @@ enum pwrap_regs {
159 PWRAP_CIPHER_LOAD,
160 PWRAP_CIPHER_START,
161
162 - /* MT8173 only regs */
163 + /* MT7623/MT8173 only regs */
164 PWRAP_RDDMY,
165 PWRAP_SI_CK_CON,
166 PWRAP_DVFS_ADR0,
167 @@ -183,6 +262,107 @@ enum pwrap_regs {
168 PWRAP_DVFS_WDATA7,
169 PWRAP_SPMINF_STA,
170 PWRAP_CIPHER_EN,
171 +
172 + /* MT7623 only regs */
173 + PWRAP_OP_TYPE,
174 + PWRAP_MSB_FIRST,
175 + PWRAP_TOP_CKCON1,
176 + PWRAP_TOP_CKCON1_CLR,
177 + PWRAP_ADC_CMD_ADDR,
178 + PWRAP_ADC_CMD,
179 + PWRAP_ADC_RDY_ADDR,
180 + PWRAP_ADC_RDATA_ADDR1,
181 + PWRAP_ADC_RDATA_ADDR2,
182 +};
183 +
184 +static int mt7623_regs[] = {
185 + [PWRAP_MUX_SEL] = 0x0,
186 + [PWRAP_WRAP_EN] = 0x4,
187 + [PWRAP_DIO_EN] = 0x8,
188 + [PWRAP_SIDLY] = 0xc,
189 + [PWRAP_OP_TYPE] = 0x10,
190 + [PWRAP_MSB_FIRST] = 0x14,
191 + [PWRAP_RDDMY] = 0x18,
192 + [PWRAP_SI_CK_CON] = 0x1c,
193 + [PWRAP_CSHEXT_WRITE] = 0x20,
194 + [PWRAP_CSHEXT_READ] = 0x24,
195 + [PWRAP_CSLEXT_START] = 0x28,
196 + [PWRAP_CSLEXT_END] = 0x2c,
197 + [PWRAP_STAUPD_PRD] = 0x30,
198 + [PWRAP_STAUPD_GRPEN] = 0x34,
199 + [PWRAP_STAUPD_MAN_TRIG] = 0x38,
200 + [PWRAP_STAUPD_STA] = 0x3C,
201 + [PWRAP_WRAP_STA] = 0x44,
202 + [PWRAP_HARB_INIT] = 0x48,
203 + [PWRAP_HARB_HPRIO] = 0x4c,
204 + [PWRAP_HIPRIO_ARB_EN] = 0x50,
205 + [PWRAP_HARB_STA0] = 0x54,
206 + [PWRAP_HARB_STA1] = 0x58,
207 + [PWRAP_MAN_EN] = 0x5c,
208 + [PWRAP_MAN_CMD] = 0x60,
209 + [PWRAP_MAN_RDATA] = 0x6c,
210 + [PWRAP_MAN_VLDCLR] = 0x68,
211 + [PWRAP_WACS0_EN] = 0x6c,
212 + [PWRAP_INIT_DONE0] = 0x70,
213 + [PWRAP_WACS0_CMD] = 0x74,
214 + [PWRAP_WACS0_RDATA] = 0x78,
215 + [PWRAP_WACS0_VLDCLR] = 0x7c,
216 + [PWRAP_WACS1_EN] = 0x80,
217 + [PWRAP_INIT_DONE1] = 0x84,
218 + [PWRAP_WACS1_CMD] = 0x88,
219 + [PWRAP_WACS1_RDATA] = 0x9c,
220 + [PWRAP_WACS1_VLDCLR] = 0x90,
221 + [PWRAP_WACS2_EN] = 0x94,
222 + [PWRAP_INIT_DONE2] = 0x98,
223 + [PWRAP_WACS2_CMD] = 0x9c,
224 + [PWRAP_WACS2_RDATA] = 0xa0,
225 + [PWRAP_WACS2_VLDCLR] = 0xa4,
226 + [PWRAP_INT_EN] = 0xa8,
227 + [PWRAP_INT_FLG_RAW] = 0xac,
228 + [PWRAP_INT_FLG] = 0xb0,
229 + [PWRAP_INT_CLR] = 0xb4,
230 + [PWRAP_SIG_ADR] = 0xb8,
231 + [PWRAP_SIG_MODE] = 0xbc,
232 + [PWRAP_SIG_VALUE] = 0xc0,
233 + [PWRAP_SIG_ERRVAL] = 0xc4,
234 + [PWRAP_CRC_EN] = 0xc8,
235 + [PWRAP_TIMER_EN] = 0xcc,
236 + [PWRAP_TIMER_STA] = 0xd0,
237 + [PWRAP_WDT_UNIT] = 0xd4,
238 + [PWRAP_WDT_SRC_EN] = 0xd8,
239 + [PWRAP_WDT_FLG] = 0xdc,
240 + [PWRAP_DEBUG_INT_SEL] = 0xe0,
241 + [PWRAP_DVFS_ADR0] = 0xe4,
242 + [PWRAP_DVFS_WDATA0] = 0xe8,
243 + [PWRAP_DVFS_ADR1] = 0xec,
244 + [PWRAP_DVFS_WDATA1] = 0xf0,
245 + [PWRAP_DVFS_ADR2] = 0xf4,
246 + [PWRAP_DVFS_WDATA2] = 0xf8,
247 + [PWRAP_DVFS_ADR3] = 0xfc,
248 + [PWRAP_DVFS_WDATA3] = 0x100,
249 + [PWRAP_DVFS_ADR4] = 0x104,
250 + [PWRAP_DVFS_WDATA4] = 0x108,
251 + [PWRAP_DVFS_ADR5] = 0x10c,
252 + [PWRAP_DVFS_WDATA5] = 0x110,
253 + [PWRAP_DVFS_ADR6] = 0x114,
254 + [PWRAP_DVFS_WDATA6] = 0x118,
255 + [PWRAP_DVFS_ADR7] = 0x11c,
256 + [PWRAP_DVFS_WDATA7] = 0x120,
257 + [PWRAP_CIPHER_KEY_SEL] = 0x124,
258 + [PWRAP_TOP_CKCON1] = 0x126,
259 + [PWRAP_CIPHER_IV_SEL] = 0x128,
260 + [PWRAP_TOP_CKCON1_CLR] = 0x12a,
261 + [PWRAP_CIPHER_EN] = 0x12c,
262 + [PWRAP_CIPHER_RDY] = 0x130,
263 + [PWRAP_CIPHER_MODE] = 0x134,
264 + [PWRAP_CIPHER_SWRST] = 0x138,
265 + [PWRAP_DCM_EN] = 0x13c,
266 + [PWRAP_DCM_DBC_PRD] = 0x140,
267 + [PWRAP_ADC_CMD_ADDR] = 0x144,
268 + [PWRAP_ADC_CMD] = 0x148,
269 + [PWRAP_ADC_RDY_ADDR] = 0x14C,
270 + [PWRAP_ADC_RDATA_ADDR1] = 0x150,
271 + [PWRAP_ADC_RDATA_ADDR2] = 0x154,
272 };
273
274 static int mt8173_regs[] = {
275 @@ -341,24 +521,39 @@ static int mt8135_regs[] = {
276 };
277
278 enum pwrap_type {
279 + PWRAP_MT7623,
280 PWRAP_MT8135,
281 PWRAP_MT8173,
282 };
283
284 struct pmic_wrapper_type {
285 int *regs;
286 + int *dew_regs;
287 + u32 dew_base;
288 enum pwrap_type type;
289 u32 arb_en_all;
290 };
291
292 +static struct pmic_wrapper_type pwrap_mt7623 = {
293 + .regs = mt7623_regs,
294 + .dew_regs = mt7623_dew_regs,
295 + .dew_base = 0x0,
296 + .type = PWRAP_MT7623,
297 + .arb_en_all = 0x3f,
298 +};
299 +
300 static struct pmic_wrapper_type pwrap_mt8135 = {
301 .regs = mt8135_regs,
302 + .dew_regs = mt8135_dew_regs,
303 + .dew_base = 0xbc00,
304 .type = PWRAP_MT8135,
305 .arb_en_all = 0x1ff,
306 };
307
308 static struct pmic_wrapper_type pwrap_mt8173 = {
309 .regs = mt8173_regs,
310 + .dew_regs = mt8173_dew_regs,
311 + .dew_base = 0xbc00,
312 .type = PWRAP_MT8173,
313 .arb_en_all = 0x3f,
314 };
315 @@ -368,6 +563,8 @@ struct pmic_wrapper {
316 void __iomem *base;
317 struct regmap *regmap;
318 int *regs;
319 + int *dew_regs;
320 + u32 dew_base;
321 enum pwrap_type type;
322 u32 arb_en_all;
323 struct clk *clk_spi;
324 @@ -378,6 +575,11 @@ struct pmic_wrapper {
325 void __iomem *bridge_base;
326 };
327
328 +static inline int pwrap_is_mt7623(struct pmic_wrapper *wrp)
329 +{
330 + return wrp->type == PWRAP_MT7623;
331 +}
332 +
333 static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
334 {
335 return wrp->type == PWRAP_MT8135;
336 @@ -475,6 +677,16 @@ static int pwrap_read(struct pmic_wrappe
337 return 0;
338 }
339
340 +static int pwrap_dew_write(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg, u32 wdata)
341 +{
342 + return pwrap_write(wrp, wrp->dew_base + wrp->dew_regs[reg], wdata);
343 +}
344 +
345 +static int pwrap_dew_read(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg, u32 *rdata)
346 +{
347 + return pwrap_read(wrp, wrp->dew_base + wrp->dew_regs[reg], rdata);
348 +}
349 +
350 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
351 {
352 return pwrap_read(context, adr, rdata);
353 @@ -535,7 +747,7 @@ static int pwrap_init_sidly(struct pmic_
354
355 for (i = 0; i < 4; i++) {
356 pwrap_writel(wrp, i, PWRAP_SIDLY);
357 - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
358 + pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
359 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
360 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
361 pass |= 1 << i;
362 @@ -561,6 +773,14 @@ static int pwrap_init_reg_clock(struct p
363 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
364 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
365 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
366 + } else if (pwrap_is_mt7623(wrp)) {
367 + pwrap_writel(wrp, 0x3, PWRAP_TOP_CKCON1_CLR);
368 + pwrap_dew_write(wrp, 0x8, PWRAP_DEW_RDDMY_NO);
369 + pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
370 + pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
371 + pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
372 + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
373 + pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
374 } else {
375 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
376 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
377 @@ -581,7 +801,7 @@ static bool pwrap_is_pmic_cipher_ready(s
378 u32 rdata;
379 int ret;
380
381 - ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
382 + ret = pwrap_dew_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
383 if (ret)
384 return 0;
385
386 @@ -606,12 +826,16 @@ static int pwrap_init_cipher(struct pmic
387 }
388
389 /* Config cipher mode @PMIC */
390 - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
391 - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
392 - pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
393 - pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
394 - pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
395 - pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
396 + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
397 + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
398 + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
399 + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
400 + if (pwrap_is_mt7623(wrp)) {
401 + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_EN, 0x1);
402 + } else {
403 + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
404 + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
405 + }
406
407 /* wait for cipher data ready@AP */
408 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
409 @@ -628,7 +852,7 @@ static int pwrap_init_cipher(struct pmic
410 }
411
412 /* wait for cipher mode idle */
413 - pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
414 + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
415 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
416 if (ret) {
417 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
418 @@ -638,8 +862,8 @@ static int pwrap_init_cipher(struct pmic
419 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
420
421 /* Write Test */
422 - if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
423 - pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
424 + if (pwrap_dew_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
425 + pwrap_dew_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
426 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
427 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
428 return -EFAULT;
429 @@ -657,12 +881,17 @@ static int pwrap_init(struct pmic_wrappe
430 if (wrp->rstc_bridge)
431 reset_control_reset(wrp->rstc_bridge);
432
433 - if (pwrap_is_mt8173(wrp)) {
434 + if (pwrap_is_mt7623(wrp) || pwrap_is_mt8173(wrp)) {
435 /* Enable DCM */
436 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
437 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
438 }
439
440 + if (pwrap_is_mt7623(wrp)) {
441 + pwrap_writel(wrp, 0, PWRAP_OP_TYPE);
442 + pwrap_writel(wrp, 1, PWRAP_MSB_FIRST);
443 + }
444 +
445 /* Reset SPI slave */
446 ret = pwrap_reset_spislave(wrp);
447 if (ret)
448 @@ -674,6 +903,9 @@ static int pwrap_init(struct pmic_wrappe
449
450 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
451
452 + if (pwrap_is_mt7623(wrp))
453 + pwrap_writel(wrp, 0xf, PWRAP_RDDMY);
454 +
455 ret = pwrap_init_reg_clock(wrp);
456 if (ret)
457 return ret;
458 @@ -684,7 +916,7 @@ static int pwrap_init(struct pmic_wrappe
459 return ret;
460
461 /* Enable dual IO mode */
462 - pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
463 + pwrap_dew_write(wrp, PWRAP_DEW_DIO_EN, 1);
464
465 /* Check IDLE & INIT_DONE in advance */
466 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
467 @@ -696,7 +928,7 @@ static int pwrap_init(struct pmic_wrappe
468 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
469
470 /* Read Test */
471 - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
472 + pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
473 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
474 dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
475 PWRAP_DEW_READ_TEST_VAL, rdata);
476 @@ -709,12 +941,13 @@ static int pwrap_init(struct pmic_wrappe
477 return ret;
478
479 /* Signature checking - using CRC */
480 - if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
481 + if (pwrap_dew_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
482 return -EFAULT;
483
484 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
485 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
486 - pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
487 + pwrap_writel(wrp, wrp->dew_base + wrp->dew_regs[PWRAP_DEW_CRC_VAL],
488 + PWRAP_SIG_ADR);
489 pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
490
491 if (pwrap_is_mt8135(wrp))
492 @@ -728,7 +961,16 @@ static int pwrap_init(struct pmic_wrappe
493 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
494 pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN);
495 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
496 - pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
497 +// pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
498 + pwrap_writel(wrp, ~(BIT(31) | BIT(2)), PWRAP_INT_EN);
499 +
500 + if (pwrap_is_mt7623(wrp)) {
501 + pwrap_writel(wrp, PWRAP_MT7623_AUXADC_CON21, PWRAP_ADC_CMD_ADDR);
502 + pwrap_writel(wrp, 0x8000, PWRAP_ADC_CMD);
503 + pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC12, PWRAP_ADC_RDY_ADDR);
504 + pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC13, PWRAP_ADC_RDATA_ADDR1);
505 + pwrap_writel(wrp, PWRAP_MT7623_AUXADC_ADC14, PWRAP_ADC_RDATA_ADDR2);
506 + }
507
508 if (pwrap_is_mt8135(wrp)) {
509 /* enable pwrap events and pwrap bridge in AP side */
510 @@ -743,15 +985,15 @@ static int pwrap_init(struct pmic_wrappe
511 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
512
513 /* enable PMIC event out and sources */
514 - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
515 - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
516 + if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
517 + pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
518 dev_err(wrp->dev, "enable dewrap fail\n");
519 return -EFAULT;
520 }
521 - } else {
522 + } else if (!pwrap_is_mt7623(wrp)) {
523 /* PMIC_DEWRAP enables */
524 - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
525 - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
526 + if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
527 + pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
528 dev_err(wrp->dev, "enable dewrap fail\n");
529 return -EFAULT;
530 }
531 @@ -795,6 +1037,9 @@ static const struct regmap_config pwrap_
532
533 static struct of_device_id of_pwrap_match_tbl[] = {
534 {
535 + .compatible = "mediatek,mt7623-pwrap",
536 + .data = &pwrap_mt7623,
537 + }, {
538 .compatible = "mediatek,mt8135-pwrap",
539 .data = &pwrap_mt8135,
540 }, {
541 @@ -824,6 +1069,8 @@ static int pwrap_probe(struct platform_d
542
543 type = of_id->data;
544 wrp->regs = type->regs;
545 + wrp->dew_regs = type->dew_regs;
546 + wrp->dew_base = type->dew_base;
547 wrp->type = type->type;
548 wrp->arb_en_all = type->arb_en_all;
549 wrp->dev = &pdev->dev;
Staging tree of Christian Lamparter