8d80c4f2b81ead83134db294668272bae703a3ef
[openwrt/staging/chunkeey.git] / target / linux / oxnas / files / drivers / clk / clk-oxnas.c
1 /*
2 * Copyright (C) 2010 Broadcom
3 * Copyright (C) 2012 Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include <linux/clk-provider.h>
19 #include <linux/clkdev.h>
20 #include <linux/clk-provider.h>
21 #include <linux/of.h>
22 #include <linux/delay.h>
23 #include <linux/stringify.h>
24 #include <linux/reset.h>
25 #include <linux/io.h>
26 #include <mach/hardware.h>
27 #include <mach/utils.h>
28
29 #define MHZ (1000 * 1000)
30
31 static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
32 unsigned long parent_rate)
33 {
34 unsigned long fin = parent_rate;
35 unsigned long pll0;
36 unsigned long fbdiv, refdiv, outdiv;
37
38 pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0);
39 refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
40 refdiv += 1;
41 outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
42 outdiv += 1;
43 fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1);
44
45 /* seems we will not be here when pll is bypassed, so ignore this
46 * case */
47
48 return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
49 }
50
51 static const char *pll_clk_parents[] = {
52 "oscillator",
53 };
54
55 static struct clk_ops plla_ops = {
56 .recalc_rate = plla_clk_recalc_rate,
57 };
58
59 static struct clk_init_data clk_plla_init = {
60 .name = "plla",
61 .ops = &plla_ops,
62 .parent_names = pll_clk_parents,
63 .num_parents = ARRAY_SIZE(pll_clk_parents),
64 };
65
66 static struct clk_hw plla_hw = {
67 .init = &clk_plla_init,
68 };
69
70 static struct device_node *node_pllb;
71
72 int pllb_clk_enable(struct clk_hw *hw)
73 {
74 struct reset_control *rstc;
75
76 rstc = of_reset_control_get(node_pllb, NULL);
77 if (IS_ERR(rstc))
78 return PTR_ERR(rstc);
79
80 /* put PLL into bypass */
81 oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
82 wmb();
83 udelay(10);
84 reset_control_assert(rstc);
85 udelay(10);
86 /* set PLL B control information */
87 writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
88 SEC_CTRL_PLLB_CTRL0);
89 reset_control_deassert(rstc);
90 reset_control_put(rstc);
91 udelay(100);
92 oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
93
94 return 0;
95 }
96
97 void pllb_clk_disable(struct clk_hw *hw)
98 {
99 struct reset_control *rstc;
100
101 /* put PLL into bypass */
102 oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
103 wmb();
104 udelay(10);
105
106 rstc = of_reset_control_get(node_pllb, NULL);
107 if (!IS_ERR(rstc))
108 reset_control_assert(rstc);
109 }
110
111 static struct clk_ops pllb_ops = {
112 .enable = pllb_clk_enable,
113 .disable = pllb_clk_disable,
114 };
115
116 static struct clk_init_data clk_pllb_init = {
117 .name = "pllb",
118 .ops = &pllb_ops,
119 .parent_names = pll_clk_parents,
120 .num_parents = ARRAY_SIZE(pll_clk_parents),
121 };
122
123 static struct clk_hw pllb_hw = {
124 .init = &clk_pllb_init,
125 };
126
127 /* standard gate clock */
128 struct clk_std {
129 struct clk_hw hw;
130 signed char bit;
131 };
132
133 #define NUM_STD_CLKS 17
134 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
135
136 static int std_clk_is_enabled(struct clk_hw *hw)
137 {
138 struct clk_std *std = to_stdclk(hw);
139
140 return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit);
141 }
142
143 static int std_clk_enable(struct clk_hw *hw)
144 {
145 struct clk_std *std = to_stdclk(hw);
146
147 writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL);
148 return 0;
149 }
150
151 static void std_clk_disable(struct clk_hw *hw)
152 {
153 struct clk_std *std = to_stdclk(hw);
154
155 writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL);
156 }
157
158 static struct clk_ops std_clk_ops = {
159 .enable = std_clk_enable,
160 .disable = std_clk_disable,
161 .is_enabled = std_clk_is_enabled,
162 };
163
164 static const char *std_clk_parents[] = {
165 "oscillator",
166 };
167
168 static const char *eth_parents[] = {
169 "gmacclk",
170 };
171
172 #define DECLARE_STD_CLKP(__clk, __bit, __parent) \
173 static struct clk_init_data clk_##__clk##_init = { \
174 .name = __stringify(__clk), \
175 .ops = &std_clk_ops, \
176 .parent_names = __parent, \
177 .num_parents = ARRAY_SIZE(__parent), \
178 }; \
179 \
180 static struct clk_std clk_##__clk = { \
181 .bit = __bit, \
182 .hw = { \
183 .init = &clk_##__clk##_init, \
184 }, \
185 }
186
187 #define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \
188 std_clk_parents)
189
190 DECLARE_STD_CLK(leon, 0);
191 DECLARE_STD_CLK(dma_sgdma, 1);
192 DECLARE_STD_CLK(cipher, 2);
193 DECLARE_STD_CLK(sd, 3);
194 DECLARE_STD_CLK(sata, 4);
195 DECLARE_STD_CLK(audio, 5);
196 DECLARE_STD_CLK(usbmph, 6);
197 DECLARE_STD_CLKP(etha, 7, eth_parents);
198 DECLARE_STD_CLK(pciea, 8);
199 DECLARE_STD_CLK(static, 9);
200 DECLARE_STD_CLK(ethb, 10);
201 DECLARE_STD_CLK(pcieb, 11);
202 DECLARE_STD_CLK(ref600, 12);
203 DECLARE_STD_CLK(usbdev, 13);
204
205 struct clk_hw *std_clk_hw_tbl[] = {
206 &clk_leon.hw,
207 &clk_dma_sgdma.hw,
208 &clk_cipher.hw,
209 &clk_sd.hw,
210 &clk_sata.hw,
211 &clk_audio.hw,
212 &clk_usbmph.hw,
213 &clk_etha.hw,
214 &clk_pciea.hw,
215 &clk_static.hw,
216 &clk_ethb.hw,
217 &clk_pcieb.hw,
218 &clk_ref600.hw,
219 &clk_usbdev.hw,
220 };
221
222 struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)];
223
224 static struct clk_onecell_data std_clk_data;
225
226 void __init oxnas_init_stdclk(struct device_node *np)
227 {
228 int i;
229
230 for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) {
231 std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]);
232 BUG_ON(IS_ERR(std_clk_tbl[i]));
233 }
234 std_clk_data.clks = std_clk_tbl;
235 std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl);
236 of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data);
237 }
238 CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk);
239
240 void __init oxnas_init_plla(struct device_node *np)
241 {
242 struct clk *clk;
243
244 clk = clk_register(NULL, &plla_hw);
245 BUG_ON(IS_ERR(clk));
246 /* mark it as enabled */
247 clk_prepare_enable(clk);
248 of_clk_add_provider(np, of_clk_src_simple_get, clk);
249 }
250 CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
251
252 void __init oxnas_init_pllb(struct device_node *np)
253 {
254 struct clk *clk;
255
256 node_pllb = np;
257
258 clk = clk_register(NULL, &pllb_hw);
259 BUG_ON(IS_ERR(clk));
260 of_clk_add_provider(np, of_clk_src_simple_get, clk);
261 }
262 CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);