target/linux/ramips/patches-3.10/0500-spi-mt7621.patch

   1 Index: linux-3.10.21/drivers/spi/spi-rt2880.c
   2 ===================================================================
   3 --- linux-3.10.21.orig/drivers/spi/spi-rt2880.c 2013-12-09 20:17:54.380713104 +0100
   4 +++ linux-3.10.21/drivers/spi/spi-rt2880.c      2013-12-09 20:35:08.004737585 +0100
   5 @@ -21,8 +21,11 @@
   6  #include <linux/io.h>
   7  #include <linux/reset.h>
   8  #include <linux/spi/spi.h>
   9 +#include <linux/of_device.h>
  10  #include <linux/platform_device.h>
  11
  12 +#include <ralink_regs.h>
  13 +
  14  #define DRIVER_NAME                    "spi-rt2880"
  15  /* only one slave is supported*/
  16  #define RALINK_NUM_CHIPSELECTS         1
  17 @@ -63,6 +66,25 @@
  18  /* SPIFIFOSTAT register bit field */
  19  #define SPIFIFOSTAT_TXFULL             BIT(17)
  20
  21 +#define MT7621_SPI_TRANS       0x00
  22 +#define SPITRANS_BUSY          BIT(16)
  23 +#define MT7621_SPI_OPCODE      0x04
  24 +#define MT7621_SPI_DATA0       0x08
  25 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
  26 +#define SPI_CTL_START          BIT(8)
  27 +#define MT7621_SPI_POLAR       0x38
  28 +#define MT7621_SPI_MASTER      0x28
  29 +#define MT7621_SPI_SPACE       0x3c
  30 +
  31 +struct rt2880_spi;
  32 +
  33 +struct rt2880_spi_ops {
  34 +       void (*init_hw)(struct rt2880_spi *rs);
  35 +       void (*set_cs)(struct rt2880_spi *rs, int enable);
  36 +       int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
  37 +       unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
  38 +};
  39 +
  40  struct rt2880_spi {
  41         struct spi_master       *master;
  42         void __iomem            *base;
  43 @@ -70,6 +92,8 @@
  44         unsigned int            speed;
  45         struct clk              *clk;
  46         spinlock_t              lock;
  47 +
  48 +       struct rt2880_spi_ops   *ops;
  49  };
  50
  51  static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
  52 @@ -149,6 +173,17 @@
  53         return 0;
  54  }
  55
  56 +static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  57 +{
  58 +/*     u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
  59 +
  60 +       // set default clock to hclk/5
  61 +       master &= ~(0xfff << 16);
  62 +       master |= 0x3 << 16;
  63 +*/
  64 +       return 0;
  65 +}
  66 +
  67  /*
  68   * called only when no transfer is active on the bus
  69   */
  70 @@ -164,7 +199,7 @@
  71
  72         if (rs->speed != speed) {
  73                 dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
  74 -               rc = rt2880_spi_baudrate_set(spi, speed);
  75 +               rc = rs->ops->baudrate_set(spi, speed);
  76                 if (rc)
  77                         return rc;
  78         }
  79 @@ -180,6 +215,17 @@
  80                 rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
  81  }
  82
  83 +static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
  84 +{
  85 +       u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
  86 +
  87 +       if (enable)
  88 +               polar |= 1;
  89 +       else
  90 +               polar &= ~1;
  91 +       rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
  92 +}
  93 +
  94  static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
  95  {
  96         int i;
  97 @@ -198,8 +244,26 @@
  98         return -ETIMEDOUT;
  99  }
 100
 101 +static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
 102 +{
 103 +       int i;
 104 +
 105 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 106 +               u32 status;
 107 +
 108 +               status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
 109 +               if ((status & SPITRANS_BUSY) == 0) {
 110 +                       return 0;
 111 +               }
 112 +               cpu_relax();
 113 +               udelay(1);
 114 +       }
 115 +
 116 +       return -ETIMEDOUT;
 117 +}
 118 +
 119  static unsigned int
 120 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 121 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
 122  {
 123         struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 124         unsigned count = 0;
 125 @@ -239,6 +303,100 @@
 126         return count;
 127  }
 128
 129 +static unsigned int
 130 +mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
 131 +{
 132 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 133 +       struct spi_transfer *next = NULL;
 134 +       const u8 *tx = xfer->tx_buf;
 135 +       u8 *rx = NULL;
 136 +       u32 trans;
 137 +       int len = xfer->len;
 138 +
 139 +       if (!tx)
 140 +               return 0;
 141 +
 142 +       if (!list_is_last(&xfer->transfer_list, list)) {
 143 +               next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
 144 +               rx = next->rx_buf;
 145 +       }
 146 +
 147 +       trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
 148 +       trans &= ~SPI_CTL_TX_RX_CNT_MASK;
 149 +
 150 +       if (tx) {
 151 +               u32 data0 = 0, opcode = 0;
 152 +
 153 +               switch (xfer->len) {
 154 +               case 8:
 155 +                       data0 |= tx[7] << 24;
 156 +               case 7:
 157 +                       data0 |= tx[6] << 16;
 158 +               case 6:
 159 +                       data0 |= tx[5] << 8;
 160 +               case 5:
 161 +                       data0 |= tx[4];
 162 +               case 4:
 163 +                       opcode |= tx[3] << 8;
 164 +               case 3:
 165 +                       opcode |= tx[2] << 16;
 166 +               case 2:
 167 +                       opcode |= tx[1] << 24;
 168 +               case 1:
 169 +                       opcode |= tx[0];
 170 +                       break;
 171 +
 172 +               default:
 173 +                       dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
 174 +                       return -EINVAL;
 175 +               }
 176 +
 177 +               rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
 178 +               rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
 179 +               trans |= xfer->len;
 180 +       }
 181 +
 182 +       if (rx)
 183 +               trans |= (next->len << 4);
 184 +       rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
 185 +       trans |= SPI_CTL_START;
 186 +       rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
 187 +
 188 +       mt7621_spi_wait_till_ready(rs);
 189 +
 190 +       if (rx) {
 191 +               u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
 192 +               u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
 193 +
 194 +               switch (next->len) {
 195 +               case 8:
 196 +                       rx[7] = (opcode >> 24) & 0xff;
 197 +               case 7:
 198 +                       rx[6] = (opcode >> 16) & 0xff;
 199 +               case 6:
 200 +                       rx[5] = (opcode >> 8) & 0xff;
 201 +               case 5:
 202 +                       rx[4] = opcode & 0xff;
 203 +               case 4:
 204 +                       rx[3] = (data0 >> 24) & 0xff;
 205 +               case 3:
 206 +                       rx[2] = (data0 >> 16) & 0xff;
 207 +               case 2:
 208 +                       rx[1] = (data0 >> 8) & 0xff;
 209 +               case 1:
 210 +                       rx[0] = data0 & 0xff;
 211 +                       break;
 212 +
 213 +               default:
 214 +                       dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
 215 +                       return -EINVAL;
 216 +               }
 217 +               len += next->len;
 218 +       }
 219 +
 220 +       return len;
 221 +}
 222 +
 223  static int rt2880_spi_transfer_one_message(struct spi_master *master,
 224                                            struct spi_message *m)
 225  {
 226 @@ -280,25 +438,25 @@
 227                 }
 228
 229                 if (!cs_active) {
 230 -                       rt2880_spi_set_cs(rs, 1);
 231 +                       rs->ops->set_cs(rs, 1);
 232                         cs_active = 1;
 233                 }
 234
 235                 if (t->len)
 236 -                       m->actual_length += rt2880_spi_write_read(spi, t);
 237 +                       m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
 238
 239                 if (t->delay_usecs)
 240                         udelay(t->delay_usecs);
 241
 242                 if (t->cs_change) {
 243 -                       rt2880_spi_set_cs(rs, 0);
 244 +                       rs->ops->set_cs(rs, 0);
 245                         cs_active = 0;
 246                 }
 247         }
 248
 249  msg_done:
 250         if (cs_active)
 251 -               rt2880_spi_set_cs(rs, 0);
 252 +               rs->ops->set_cs(rs, 0);
 253
 254         m->status = status;
 255         spi_finalize_current_message(master);
 256 @@ -334,8 +492,41 @@
 257         rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 258  }
 259
 260 +static void mt7621_spi_reset(struct rt2880_spi *rs)
 261 +{
 262 +       u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
 263 +
 264 +       master &= ~(0xfff << 16);
 265 +       master |= 3 << 16;
 266 +
 267 +       master |= 7 << 29;
 268 +       rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
 269 +}
 270 +
 271 +static struct rt2880_spi_ops spi_ops[] = {
 272 +       {
 273 +               .init_hw = rt2880_spi_reset,
 274 +               .set_cs = rt2880_spi_set_cs,
 275 +               .baudrate_set = rt2880_spi_baudrate_set,
 276 +               .write_read = rt2880_spi_write_read,
 277 +       }, {
 278 +               .init_hw = mt7621_spi_reset,
 279 +               .set_cs = mt7621_spi_set_cs,
 280 +               .baudrate_set = mt7621_spi_baudrate_set,
 281 +               .write_read = mt7621_spi_write_read,
 282 +       },
 283 +};
 284 +
 285 +static const struct of_device_id rt2880_spi_match[] = {
 286 +       { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
 287 +       { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
 288 +       {},
 289 +};
 290 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 291 +
 292  static int rt2880_spi_probe(struct platform_device *pdev)
 293  {
 294 +        const struct of_device_id *match;
 295         struct spi_master *master;
 296         struct rt2880_spi *rs;
 297         unsigned long flags;
 298 @@ -344,6 +535,10 @@
 299         int status = 0;
 300         struct clk *clk;
 301
 302 +        match = of_match_device(rt2880_spi_match, &pdev->dev);
 303 +       if (!match)
 304 +               return -EINVAL;
 305 +
 306         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 307         base = devm_ioremap_resource(&pdev->dev, r);
 308         if (IS_ERR(base))
 309 @@ -382,12 +577,13 @@
 310         rs->clk = clk;
 311         rs->master = master;
 312         rs->sys_freq = clk_get_rate(rs->clk);
 313 +       rs->ops = (struct rt2880_spi_ops *) match->data;
 314         dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 315         spin_lock_irqsave(&rs->lock, flags);
 316
 317         device_reset(&pdev->dev);
 318
 319 -       rt2880_spi_reset(rs);
 320 +       rs->ops->init_hw(rs);
 321
 322         return spi_register_master(master);
 323  }
 324 @@ -408,12 +604,6 @@
 325
 326  MODULE_ALIAS("platform:" DRIVER_NAME);
 327
 328 -static const struct of_device_id rt2880_spi_match[] = {
 329 -       { .compatible = "ralink,rt2880-spi" },
 330 -       {},
 331 -};
 332 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 333 -
 334  static struct platform_driver rt2880_spi_driver = {
 335         .driver = {
 336                 .name = DRIVER_NAME,