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74ab97308fd93ba54d72a5cc499809da2458ab5b
[openwrt/staging/chunkeey.git] / target / linux / xburst / patches-2.6.35 / 054-mmc.patch
1 From 11bc6d97096ab89da31f628c89b19ff37dfdd526 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Thu, 15 Jul 2010 20:06:04 +0000
4 Subject: [PATCH] MMC: Add support for the controller on JZ4740 SoCs.
5
6 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
7 Acked-by: Matt Fleming <matt@console-pimps.org>
8 Cc: Andrew Morton <akpm@linux-foundation.org>
9 Cc: Matt Fleming <matt@console-pimps.org>
10 Cc: linux-mmc@vger.kernel.org
11 Cc: linux-mips@linux-mips.org
12 Cc: linux-kernel@vger.kernel.org
13 Patchwork: https://patchwork.linux-mips.org/patch/1463/
14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
15 ---
16 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h | 15 +
17 drivers/mmc/host/Kconfig | 9 +
18 drivers/mmc/host/Makefile | 1 +
19 drivers/mmc/host/jz4740_mmc.c | 1029 ++++++++++++++++++++++++
20 4 files changed, 1054 insertions(+), 0 deletions(-)
21 create mode 100644 arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
22 create mode 100644 drivers/mmc/host/jz4740_mmc.c
23
24 diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
25 new file mode 100644
26 index 0000000..8543f43
27 --- /dev/null
28 +++ b/arch/mips/include/asm/mach-jz4740/jz4740_mmc.h
29 @@ -0,0 +1,15 @@
30 +#ifndef __LINUX_MMC_JZ4740_MMC
31 +#define __LINUX_MMC_JZ4740_MMC
32 +
33 +struct jz4740_mmc_platform_data {
34 + int gpio_power;
35 + int gpio_card_detect;
36 + int gpio_read_only;
37 + unsigned card_detect_active_low:1;
38 + unsigned read_only_active_low:1;
39 + unsigned power_active_low:1;
40 +
41 + unsigned data_1bit:1;
42 +};
43 +
44 +#endif
45 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
46 index f06d06e..d25e22c 100644
47 --- a/drivers/mmc/host/Kconfig
48 +++ b/drivers/mmc/host/Kconfig
49 @@ -432,3 +432,12 @@ config MMC_SH_MMCIF
50 This selects the MMC Host Interface controler (MMCIF).
51
52 This driver supports MMCIF in sh7724/sh7757/sh7372.
53 +
54 +config MMC_JZ4740
55 + tristate "JZ4740 SD/Multimedia Card Interface support"
56 + depends on MACH_JZ4740
57 + help
58 + This selects support for the SD/MMC controller on Ingenic JZ4740
59 + SoCs.
60 + If you have a board based on such a SoC and with a SD/MMC slot,
61 + say Y or M here.
62 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
63 index e30c2ee..f4e53c9 100644
64 --- a/drivers/mmc/host/Makefile
65 +++ b/drivers/mmc/host/Makefile
66 @@ -36,6 +36,7 @@ obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
67 obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
68 obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
69 obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
70 +obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
71
72 obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
73 sdhci-of-y := sdhci-of-core.o
74 diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c
75 new file mode 100644
76 index 0000000..ad4f987
77 --- /dev/null
78 +++ b/drivers/mmc/host/jz4740_mmc.c
79 @@ -0,0 +1,1029 @@
80 +/*
81 + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
82 + * JZ4740 SD/MMC controller driver
83 + *
84 + * This program is free software; you can redistribute it and/or modify it
85 + * under the terms of the GNU General Public License as published by the
86 + * Free Software Foundation; either version 2 of the License, or (at your
87 + * option) any later version.
88 + *
89 + * You should have received a copy of the GNU General Public License along
90 + * with this program; if not, write to the Free Software Foundation, Inc.,
91 + * 675 Mass Ave, Cambridge, MA 02139, USA.
92 + *
93 + */
94 +
95 +#include <linux/mmc/host.h>
96 +#include <linux/io.h>
97 +#include <linux/irq.h>
98 +#include <linux/interrupt.h>
99 +#include <linux/module.h>
100 +#include <linux/platform_device.h>
101 +#include <linux/delay.h>
102 +#include <linux/scatterlist.h>
103 +#include <linux/clk.h>
104 +
105 +#include <linux/bitops.h>
106 +#include <linux/gpio.h>
107 +#include <asm/mach-jz4740/gpio.h>
108 +#include <asm/cacheflush.h>
109 +#include <linux/dma-mapping.h>
110 +
111 +#include <asm/mach-jz4740/jz4740_mmc.h>
112 +
113 +#define JZ_REG_MMC_STRPCL 0x00
114 +#define JZ_REG_MMC_STATUS 0x04
115 +#define JZ_REG_MMC_CLKRT 0x08
116 +#define JZ_REG_MMC_CMDAT 0x0C
117 +#define JZ_REG_MMC_RESTO 0x10
118 +#define JZ_REG_MMC_RDTO 0x14
119 +#define JZ_REG_MMC_BLKLEN 0x18
120 +#define JZ_REG_MMC_NOB 0x1C
121 +#define JZ_REG_MMC_SNOB 0x20
122 +#define JZ_REG_MMC_IMASK 0x24
123 +#define JZ_REG_MMC_IREG 0x28
124 +#define JZ_REG_MMC_CMD 0x2C
125 +#define JZ_REG_MMC_ARG 0x30
126 +#define JZ_REG_MMC_RESP_FIFO 0x34
127 +#define JZ_REG_MMC_RXFIFO 0x38
128 +#define JZ_REG_MMC_TXFIFO 0x3C
129 +
130 +#define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
131 +#define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
132 +#define JZ_MMC_STRPCL_START_READWAIT BIT(5)
133 +#define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
134 +#define JZ_MMC_STRPCL_RESET BIT(3)
135 +#define JZ_MMC_STRPCL_START_OP BIT(2)
136 +#define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
137 +#define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
138 +#define JZ_MMC_STRPCL_CLOCK_START BIT(1)
139 +
140 +
141 +#define JZ_MMC_STATUS_IS_RESETTING BIT(15)
142 +#define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
143 +#define JZ_MMC_STATUS_PRG_DONE BIT(13)
144 +#define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
145 +#define JZ_MMC_STATUS_END_CMD_RES BIT(11)
146 +#define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
147 +#define JZ_MMC_STATUS_IS_READWAIT BIT(9)
148 +#define JZ_MMC_STATUS_CLK_EN BIT(8)
149 +#define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
150 +#define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
151 +#define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
152 +#define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
153 +#define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
154 +#define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
155 +#define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
156 +#define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
157 +
158 +#define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
159 +#define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
160 +
161 +
162 +#define JZ_MMC_CMDAT_IO_ABORT BIT(11)
163 +#define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
164 +#define JZ_MMC_CMDAT_DMA_EN BIT(8)
165 +#define JZ_MMC_CMDAT_INIT BIT(7)
166 +#define JZ_MMC_CMDAT_BUSY BIT(6)
167 +#define JZ_MMC_CMDAT_STREAM BIT(5)
168 +#define JZ_MMC_CMDAT_WRITE BIT(4)
169 +#define JZ_MMC_CMDAT_DATA_EN BIT(3)
170 +#define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
171 +#define JZ_MMC_CMDAT_RSP_R1 1
172 +#define JZ_MMC_CMDAT_RSP_R2 2
173 +#define JZ_MMC_CMDAT_RSP_R3 3
174 +
175 +#define JZ_MMC_IRQ_SDIO BIT(7)
176 +#define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
177 +#define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
178 +#define JZ_MMC_IRQ_END_CMD_RES BIT(2)
179 +#define JZ_MMC_IRQ_PRG_DONE BIT(1)
180 +#define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
181 +
182 +
183 +#define JZ_MMC_CLK_RATE 24000000
184 +
185 +enum jz4740_mmc_state {
186 + JZ4740_MMC_STATE_READ_RESPONSE,
187 + JZ4740_MMC_STATE_TRANSFER_DATA,
188 + JZ4740_MMC_STATE_SEND_STOP,
189 + JZ4740_MMC_STATE_DONE,
190 +};
191 +
192 +struct jz4740_mmc_host {
193 + struct mmc_host *mmc;
194 + struct platform_device *pdev;
195 + struct jz4740_mmc_platform_data *pdata;
196 + struct clk *clk;
197 +
198 + int irq;
199 + int card_detect_irq;
200 +
201 + struct resource *mem;
202 + void __iomem *base;
203 + struct mmc_request *req;
204 + struct mmc_command *cmd;
205 +
206 + unsigned long waiting;
207 +
208 + uint32_t cmdat;
209 +
210 + uint16_t irq_mask;
211 +
212 + spinlock_t lock;
213 +
214 + struct timer_list timeout_timer;
215 + struct sg_mapping_iter miter;
216 + enum jz4740_mmc_state state;
217 +};
218 +
219 +static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
220 + unsigned int irq, bool enabled)
221 +{
222 + unsigned long flags;
223 +
224 + spin_lock_irqsave(&host->lock, flags);
225 + if (enabled)
226 + host->irq_mask &= ~irq;
227 + else
228 + host->irq_mask |= irq;
229 + spin_unlock_irqrestore(&host->lock, flags);
230 +
231 + writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK);
232 +}
233 +
234 +static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
235 + bool start_transfer)
236 +{
237 + uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
238 +
239 + if (start_transfer)
240 + val |= JZ_MMC_STRPCL_START_OP;
241 +
242 + writew(val, host->base + JZ_REG_MMC_STRPCL);
243 +}
244 +
245 +static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
246 +{
247 + uint32_t status;
248 + unsigned int timeout = 1000;
249 +
250 + writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
251 + do {
252 + status = readl(host->base + JZ_REG_MMC_STATUS);
253 + } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
254 +}
255 +
256 +static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
257 +{
258 + uint32_t status;
259 + unsigned int timeout = 1000;
260 +
261 + writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
262 + udelay(10);
263 + do {
264 + status = readl(host->base + JZ_REG_MMC_STATUS);
265 + } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
266 +}
267 +
268 +static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
269 +{
270 + struct mmc_request *req;
271 +
272 + req = host->req;
273 + host->req = NULL;
274 +
275 + mmc_request_done(host->mmc, req);
276 +}
277 +
278 +static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
279 + unsigned int irq)
280 +{
281 + unsigned int timeout = 0x800;
282 + uint16_t status;
283 +
284 + do {
285 + status = readw(host->base + JZ_REG_MMC_IREG);
286 + } while (!(status & irq) && --timeout);
287 +
288 + if (timeout == 0) {
289 + set_bit(0, &host->waiting);
290 + mod_timer(&host->timeout_timer, jiffies + 5*HZ);
291 + jz4740_mmc_set_irq_enabled(host, irq, true);
292 + return true;
293 + }
294 +
295 + return false;
296 +}
297 +
298 +static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
299 + struct mmc_data *data)
300 +{
301 + int status;
302 +
303 + status = readl(host->base + JZ_REG_MMC_STATUS);
304 + if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
305 + if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
306 + host->req->cmd->error = -ETIMEDOUT;
307 + data->error = -ETIMEDOUT;
308 + } else {
309 + host->req->cmd->error = -EIO;
310 + data->error = -EIO;
311 + }
312 + }
313 +}
314 +
315 +static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
316 + struct mmc_data *data)
317 +{
318 + struct sg_mapping_iter *miter = &host->miter;
319 + void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
320 + uint32_t *buf;
321 + bool timeout;
322 + size_t i, j;
323 +
324 + while (sg_miter_next(miter)) {
325 + buf = miter->addr;
326 + i = miter->length / 4;
327 + j = i / 8;
328 + i = i & 0x7;
329 + while (j) {
330 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
331 + if (unlikely(timeout))
332 + goto poll_timeout;
333 +
334 + writel(buf[0], fifo_addr);
335 + writel(buf[1], fifo_addr);
336 + writel(buf[2], fifo_addr);
337 + writel(buf[3], fifo_addr);
338 + writel(buf[4], fifo_addr);
339 + writel(buf[5], fifo_addr);
340 + writel(buf[6], fifo_addr);
341 + writel(buf[7], fifo_addr);
342 + buf += 8;
343 + --j;
344 + }
345 + if (unlikely(i)) {
346 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
347 + if (unlikely(timeout))
348 + goto poll_timeout;
349 +
350 + while (i) {
351 + writel(*buf, fifo_addr);
352 + ++buf;
353 + --i;
354 + }
355 + }
356 + data->bytes_xfered += miter->length;
357 + }
358 + sg_miter_stop(miter);
359 +
360 + return false;
361 +
362 +poll_timeout:
363 + miter->consumed = (void *)buf - miter->addr;
364 + data->bytes_xfered += miter->consumed;
365 + sg_miter_stop(miter);
366 +
367 + return true;
368 +}
369 +
370 +static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
371 + struct mmc_data *data)
372 +{
373 + struct sg_mapping_iter *miter = &host->miter;
374 + void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
375 + uint32_t *buf;
376 + uint32_t d;
377 + uint16_t status;
378 + size_t i, j;
379 + unsigned int timeout;
380 +
381 + while (sg_miter_next(miter)) {
382 + buf = miter->addr;
383 + i = miter->length;
384 + j = i / 32;
385 + i = i & 0x1f;
386 + while (j) {
387 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
388 + if (unlikely(timeout))
389 + goto poll_timeout;
390 +
391 + buf[0] = readl(fifo_addr);
392 + buf[1] = readl(fifo_addr);
393 + buf[2] = readl(fifo_addr);
394 + buf[3] = readl(fifo_addr);
395 + buf[4] = readl(fifo_addr);
396 + buf[5] = readl(fifo_addr);
397 + buf[6] = readl(fifo_addr);
398 + buf[7] = readl(fifo_addr);
399 +
400 + buf += 8;
401 + --j;
402 + }
403 +
404 + if (unlikely(i)) {
405 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
406 + if (unlikely(timeout))
407 + goto poll_timeout;
408 +
409 + while (i >= 4) {
410 + *buf++ = readl(fifo_addr);
411 + i -= 4;
412 + }
413 + if (unlikely(i > 0)) {
414 + d = readl(fifo_addr);
415 + memcpy(buf, &d, i);
416 + }
417 + }
418 + data->bytes_xfered += miter->length;
419 +
420 + /* This can go away once MIPS implements
421 + * flush_kernel_dcache_page */
422 + flush_dcache_page(miter->page);
423 + }
424 + sg_miter_stop(miter);
425 +
426 + /* For whatever reason there is sometime one word more in the fifo then
427 + * requested */
428 + timeout = 1000;
429 + status = readl(host->base + JZ_REG_MMC_STATUS);
430 + while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
431 + d = readl(fifo_addr);
432 + status = readl(host->base + JZ_REG_MMC_STATUS);
433 + }
434 +
435 + return false;
436 +
437 +poll_timeout:
438 + miter->consumed = (void *)buf - miter->addr;
439 + data->bytes_xfered += miter->consumed;
440 + sg_miter_stop(miter);
441 +
442 + return true;
443 +}
444 +
445 +static void jz4740_mmc_timeout(unsigned long data)
446 +{
447 + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data;
448 +
449 + if (!test_and_clear_bit(0, &host->waiting))
450 + return;
451 +
452 + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
453 +
454 + host->req->cmd->error = -ETIMEDOUT;
455 + jz4740_mmc_request_done(host);
456 +}
457 +
458 +static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
459 + struct mmc_command *cmd)
460 +{
461 + int i;
462 + uint16_t tmp;
463 + void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
464 +
465 + if (cmd->flags & MMC_RSP_136) {
466 + tmp = readw(fifo_addr);
467 + for (i = 0; i < 4; ++i) {
468 + cmd->resp[i] = tmp << 24;
469 + tmp = readw(fifo_addr);
470 + cmd->resp[i] |= tmp << 8;
471 + tmp = readw(fifo_addr);
472 + cmd->resp[i] |= tmp >> 8;
473 + }
474 + } else {
475 + cmd->resp[0] = readw(fifo_addr) << 24;
476 + cmd->resp[0] |= readw(fifo_addr) << 8;
477 + cmd->resp[0] |= readw(fifo_addr) & 0xff;
478 + }
479 +}
480 +
481 +static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
482 + struct mmc_command *cmd)
483 +{
484 + uint32_t cmdat = host->cmdat;
485 +
486 + host->cmdat &= ~JZ_MMC_CMDAT_INIT;
487 + jz4740_mmc_clock_disable(host);
488 +
489 + host->cmd = cmd;
490 +
491 + if (cmd->flags & MMC_RSP_BUSY)
492 + cmdat |= JZ_MMC_CMDAT_BUSY;
493 +
494 + switch (mmc_resp_type(cmd)) {
495 + case MMC_RSP_R1B:
496 + case MMC_RSP_R1:
497 + cmdat |= JZ_MMC_CMDAT_RSP_R1;
498 + break;
499 + case MMC_RSP_R2:
500 + cmdat |= JZ_MMC_CMDAT_RSP_R2;
501 + break;
502 + case MMC_RSP_R3:
503 + cmdat |= JZ_MMC_CMDAT_RSP_R3;
504 + break;
505 + default:
506 + break;
507 + }
508 +
509 + if (cmd->data) {
510 + cmdat |= JZ_MMC_CMDAT_DATA_EN;
511 + if (cmd->data->flags & MMC_DATA_WRITE)
512 + cmdat |= JZ_MMC_CMDAT_WRITE;
513 + if (cmd->data->flags & MMC_DATA_STREAM)
514 + cmdat |= JZ_MMC_CMDAT_STREAM;
515 +
516 + writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
517 + writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
518 + }
519 +
520 + writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
521 + writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
522 + writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
523 +
524 + jz4740_mmc_clock_enable(host, 1);
525 +}
526 +
527 +static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
528 +{
529 + struct mmc_command *cmd = host->req->cmd;
530 + struct mmc_data *data = cmd->data;
531 + int direction;
532 +
533 + if (data->flags & MMC_DATA_READ)
534 + direction = SG_MITER_TO_SG;
535 + else
536 + direction = SG_MITER_FROM_SG;
537 +
538 + sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
539 +}
540 +
541 +
542 +static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
543 +{
544 + struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
545 + struct mmc_command *cmd = host->req->cmd;
546 + struct mmc_request *req = host->req;
547 + bool timeout = false;
548 +
549 + if (cmd->error)
550 + host->state = JZ4740_MMC_STATE_DONE;
551 +
552 + switch (host->state) {
553 + case JZ4740_MMC_STATE_READ_RESPONSE:
554 + if (cmd->flags & MMC_RSP_PRESENT)
555 + jz4740_mmc_read_response(host, cmd);
556 +
557 + if (!cmd->data)
558 + break;
559 +
560 + jz_mmc_prepare_data_transfer(host);
561 +
562 + case JZ4740_MMC_STATE_TRANSFER_DATA:
563 + if (cmd->data->flags & MMC_DATA_READ)
564 + timeout = jz4740_mmc_read_data(host, cmd->data);
565 + else
566 + timeout = jz4740_mmc_write_data(host, cmd->data);
567 +
568 + if (unlikely(timeout)) {
569 + host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
570 + break;
571 + }
572 +
573 + jz4740_mmc_transfer_check_state(host, cmd->data);
574 +
575 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
576 + if (unlikely(timeout)) {
577 + host->state = JZ4740_MMC_STATE_SEND_STOP;
578 + break;
579 + }
580 + writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG);
581 +
582 + case JZ4740_MMC_STATE_SEND_STOP:
583 + if (!req->stop)
584 + break;
585 +
586 + jz4740_mmc_send_command(host, req->stop);
587 +
588 + timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE);
589 + if (timeout) {
590 + host->state = JZ4740_MMC_STATE_DONE;
591 + break;
592 + }
593 + case JZ4740_MMC_STATE_DONE:
594 + break;
595 + }
596 +
597 + if (!timeout)
598 + jz4740_mmc_request_done(host);
599 +
600 + return IRQ_HANDLED;
601 +}
602 +
603 +static irqreturn_t jz_mmc_irq(int irq, void *devid)
604 +{
605 + struct jz4740_mmc_host *host = devid;
606 + struct mmc_command *cmd = host->cmd;
607 + uint16_t irq_reg, status, tmp;
608 +
609 + irq_reg = readw(host->base + JZ_REG_MMC_IREG);
610 +
611 + tmp = irq_reg;
612 + irq_reg &= ~host->irq_mask;
613 +
614 + tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
615 + JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
616 +
617 + if (tmp != irq_reg)
618 + writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG);
619 +
620 + if (irq_reg & JZ_MMC_IRQ_SDIO) {
621 + writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG);
622 + mmc_signal_sdio_irq(host->mmc);
623 + irq_reg &= ~JZ_MMC_IRQ_SDIO;
624 + }
625 +
626 + if (host->req && cmd && irq_reg) {
627 + if (test_and_clear_bit(0, &host->waiting)) {
628 + del_timer(&host->timeout_timer);
629 +
630 + status = readl(host->base + JZ_REG_MMC_STATUS);
631 +
632 + if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
633 + cmd->error = -ETIMEDOUT;
634 + } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
635 + cmd->error = -EIO;
636 + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
637 + JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
638 + if (cmd->data)
639 + cmd->data->error = -EIO;
640 + cmd->error = -EIO;
641 + } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
642 + JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
643 + if (cmd->data)
644 + cmd->data->error = -EIO;
645 + cmd->error = -EIO;
646 + }
647 +
648 + jz4740_mmc_set_irq_enabled(host, irq_reg, false);
649 + writew(irq_reg, host->base + JZ_REG_MMC_IREG);
650 +
651 + return IRQ_WAKE_THREAD;
652 + }
653 + }
654 +
655 + return IRQ_HANDLED;
656 +}
657 +
658 +static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
659 +{
660 + int div = 0;
661 + int real_rate;
662 +
663 + jz4740_mmc_clock_disable(host);
664 + clk_set_rate(host->clk, JZ_MMC_CLK_RATE);
665 +
666 + real_rate = clk_get_rate(host->clk);
667 +
668 + while (real_rate > rate && div < 7) {
669 + ++div;
670 + real_rate >>= 1;
671 + }
672 +
673 + writew(div, host->base + JZ_REG_MMC_CLKRT);
674 + return real_rate;
675 +}
676 +
677 +static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
678 +{
679 + struct jz4740_mmc_host *host = mmc_priv(mmc);
680 +
681 + host->req = req;
682 +
683 + writew(0xffff, host->base + JZ_REG_MMC_IREG);
684 +
685 + writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG);
686 + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
687 +
688 + host->state = JZ4740_MMC_STATE_READ_RESPONSE;
689 + set_bit(0, &host->waiting);
690 + mod_timer(&host->timeout_timer, jiffies + 5*HZ);
691 + jz4740_mmc_send_command(host, req->cmd);
692 +}
693 +
694 +static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
695 +{
696 + struct jz4740_mmc_host *host = mmc_priv(mmc);
697 + if (ios->clock)
698 + jz4740_mmc_set_clock_rate(host, ios->clock);
699 +
700 + switch (ios->power_mode) {
701 + case MMC_POWER_UP:
702 + jz4740_mmc_reset(host);
703 + if (gpio_is_valid(host->pdata->gpio_power))
704 + gpio_set_value(host->pdata->gpio_power,
705 + !host->pdata->power_active_low);
706 + host->cmdat |= JZ_MMC_CMDAT_INIT;
707 + clk_enable(host->clk);
708 + break;
709 + case MMC_POWER_ON:
710 + break;
711 + default:
712 + if (gpio_is_valid(host->pdata->gpio_power))
713 + gpio_set_value(host->pdata->gpio_power,
714 + host->pdata->power_active_low);
715 + clk_disable(host->clk);
716 + break;
717 + }
718 +
719 + switch (ios->bus_width) {
720 + case MMC_BUS_WIDTH_1:
721 + host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
722 + break;
723 + case MMC_BUS_WIDTH_4:
724 + host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
725 + break;
726 + default:
727 + break;
728 + }
729 +}
730 +
731 +static int jz4740_mmc_get_ro(struct mmc_host *mmc)
732 +{
733 + struct jz4740_mmc_host *host = mmc_priv(mmc);
734 + if (!gpio_is_valid(host->pdata->gpio_read_only))
735 + return -ENOSYS;
736 +
737 + return gpio_get_value(host->pdata->gpio_read_only) ^
738 + host->pdata->read_only_active_low;
739 +}
740 +
741 +static int jz4740_mmc_get_cd(struct mmc_host *mmc)
742 +{
743 + struct jz4740_mmc_host *host = mmc_priv(mmc);
744 + if (!gpio_is_valid(host->pdata->gpio_card_detect))
745 + return -ENOSYS;
746 +
747 + return gpio_get_value(host->pdata->gpio_card_detect) ^
748 + host->pdata->card_detect_active_low;
749 +}
750 +
751 +static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
752 +{
753 + struct jz4740_mmc_host *host = devid;
754 +
755 + mmc_detect_change(host->mmc, HZ / 2);
756 +
757 + return IRQ_HANDLED;
758 +}
759 +
760 +static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
761 +{
762 + struct jz4740_mmc_host *host = mmc_priv(mmc);
763 + jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
764 +}
765 +
766 +static const struct mmc_host_ops jz4740_mmc_ops = {
767 + .request = jz4740_mmc_request,
768 + .set_ios = jz4740_mmc_set_ios,
769 + .get_ro = jz4740_mmc_get_ro,
770 + .get_cd = jz4740_mmc_get_cd,
771 + .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
772 +};
773 +
774 +static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = {
775 + JZ_GPIO_BULK_PIN(MSC_CMD),
776 + JZ_GPIO_BULK_PIN(MSC_CLK),
777 + JZ_GPIO_BULK_PIN(MSC_DATA0),
778 + JZ_GPIO_BULK_PIN(MSC_DATA1),
779 + JZ_GPIO_BULK_PIN(MSC_DATA2),
780 + JZ_GPIO_BULK_PIN(MSC_DATA3),
781 +};
782 +
783 +static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio,
784 + const char *name, bool output, int value)
785 +{
786 + int ret;
787 +
788 + if (!gpio_is_valid(gpio))
789 + return 0;
790 +
791 + ret = gpio_request(gpio, name);
792 + if (ret) {
793 + dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
794 + return ret;
795 + }
796 +
797 + if (output)
798 + gpio_direction_output(gpio, value);
799 + else
800 + gpio_direction_input(gpio);
801 +
802 + return 0;
803 +}
804 +
805 +static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev)
806 +{
807 + int ret;
808 + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
809 +
810 + if (!pdata)
811 + return 0;
812 +
813 + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect,
814 + "MMC detect change", false, 0);
815 + if (ret)
816 + goto err;
817 +
818 + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only,
819 + "MMC read only", false, 0);
820 + if (ret)
821 + goto err_free_gpio_card_detect;
822 +
823 + ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
824 + "MMC read only", true, pdata->power_active_low);
825 + if (ret)
826 + goto err_free_gpio_read_only;
827 +
828 + return 0;
829 +
830 +err_free_gpio_read_only:
831 + if (gpio_is_valid(pdata->gpio_read_only))
832 + gpio_free(pdata->gpio_read_only);
833 +err_free_gpio_card_detect:
834 + if (gpio_is_valid(pdata->gpio_card_detect))
835 + gpio_free(pdata->gpio_card_detect);
836 +err:
837 + return ret;
838 +}
839 +
840 +static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev,
841 + struct jz4740_mmc_host *host)
842 +{
843 + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
844 +
845 + if (!gpio_is_valid(pdata->gpio_card_detect))
846 + return 0;
847 +
848 + host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
849 + if (host->card_detect_irq < 0) {
850 + dev_warn(&pdev->dev, "Failed to get card detect irq\n");
851 + return 0;
852 + }
853 +
854 + return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq,
855 + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
856 + "MMC card detect", host);
857 +}
858 +
859 +static void jz4740_mmc_free_gpios(struct platform_device *pdev)
860 +{
861 + struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
862 +
863 + if (!pdata)
864 + return;
865 +
866 + if (gpio_is_valid(pdata->gpio_power))
867 + gpio_free(pdata->gpio_power);
868 + if (gpio_is_valid(pdata->gpio_read_only))
869 + gpio_free(pdata->gpio_read_only);
870 + if (gpio_is_valid(pdata->gpio_card_detect))
871 + gpio_free(pdata->gpio_card_detect);
872 +}
873 +
874 +static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
875 +{
876 + size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins);
877 + if (host->pdata && host->pdata->data_1bit)
878 + num_pins -= 3;
879 +
880 + return num_pins;
881 +}
882 +
883 +static int __devinit jz4740_mmc_probe(struct platform_device* pdev)
884 +{
885 + int ret;
886 + struct mmc_host *mmc;
887 + struct jz4740_mmc_host *host;
888 + struct jz4740_mmc_platform_data *pdata;
889 +
890 + pdata = pdev->dev.platform_data;
891 +
892 + mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
893 + if (!mmc) {
894 + dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
895 + return -ENOMEM;
896 + }
897 +
898 + host = mmc_priv(mmc);
899 + host->pdata = pdata;
900 +
901 + host->irq = platform_get_irq(pdev, 0);
902 + if (host->irq < 0) {
903 + ret = host->irq;
904 + dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
905 + goto err_free_host;
906 + }
907 +
908 + host->clk = clk_get(&pdev->dev, "mmc");
909 + if (!host->clk) {
910 + ret = -ENOENT;
911 + dev_err(&pdev->dev, "Failed to get mmc clock\n");
912 + goto err_free_host;
913 + }
914 +
915 + host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
916 + if (!host->mem) {
917 + ret = -ENOENT;
918 + dev_err(&pdev->dev, "Failed to get base platform memory\n");
919 + goto err_clk_put;
920 + }
921 +
922 + host->mem = request_mem_region(host->mem->start,
923 + resource_size(host->mem), pdev->name);
924 + if (!host->mem) {
925 + ret = -EBUSY;
926 + dev_err(&pdev->dev, "Failed to request base memory region\n");
927 + goto err_clk_put;
928 + }
929 +
930 + host->base = ioremap_nocache(host->mem->start, resource_size(host->mem));
931 + if (!host->base) {
932 + ret = -EBUSY;
933 + dev_err(&pdev->dev, "Failed to ioremap base memory\n");
934 + goto err_release_mem_region;
935 + }
936 +
937 + ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
938 + if (ret) {
939 + dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret);
940 + goto err_iounmap;
941 + }
942 +
943 + ret = jz4740_mmc_request_gpios(pdev);
944 + if (ret)
945 + goto err_gpio_bulk_free;
946 +
947 + mmc->ops = &jz4740_mmc_ops;
948 + mmc->f_min = JZ_MMC_CLK_RATE / 128;
949 + mmc->f_max = JZ_MMC_CLK_RATE;
950 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
951 + mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA;
952 + mmc->caps |= MMC_CAP_SDIO_IRQ;
953 +
954 + mmc->max_blk_size = (1 << 10) - 1;
955 + mmc->max_blk_count = (1 << 15) - 1;
956 + mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
957 +
958 + mmc->max_phys_segs = 128;
959 + mmc->max_hw_segs = 128;
960 + mmc->max_seg_size = mmc->max_req_size;
961 +
962 + host->mmc = mmc;
963 + host->pdev = pdev;
964 + spin_lock_init(&host->lock);
965 + host->irq_mask = 0xffff;
966 +
967 + ret = jz4740_mmc_request_cd_irq(pdev, host);
968 + if (ret) {
969 + dev_err(&pdev->dev, "Failed to request card detect irq\n");
970 + goto err_free_gpios;
971 + }
972 +
973 + ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
974 + dev_name(&pdev->dev), host);
975 + if (ret) {
976 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
977 + goto err_free_card_detect_irq;
978 + }
979 +
980 + jz4740_mmc_reset(host);
981 + jz4740_mmc_clock_disable(host);
982 + setup_timer(&host->timeout_timer, jz4740_mmc_timeout,
983 + (unsigned long)host);
984 + /* It is not important when it times out, it just needs to timeout. */
985 + set_timer_slack(&host->timeout_timer, HZ);
986 +
987 + platform_set_drvdata(pdev, host);
988 + ret = mmc_add_host(mmc);
989 +
990 + if (ret) {
991 + dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
992 + goto err_free_irq;
993 + }
994 + dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
995 +
996 + return 0;
997 +
998 +err_free_irq:
999 + free_irq(host->irq, host);
1000 +err_free_card_detect_irq:
1001 + if (host->card_detect_irq >= 0)
1002 + free_irq(host->card_detect_irq, host);
1003 +err_free_gpios:
1004 + jz4740_mmc_free_gpios(pdev);
1005 +err_gpio_bulk_free:
1006 + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1007 +err_iounmap:
1008 + iounmap(host->base);
1009 +err_release_mem_region:
1010 + release_mem_region(host->mem->start, resource_size(host->mem));
1011 +err_clk_put:
1012 + clk_put(host->clk);
1013 +err_free_host:
1014 + platform_set_drvdata(pdev, NULL);
1015 + mmc_free_host(mmc);
1016 +
1017 + return ret;
1018 +}
1019 +
1020 +static int __devexit jz4740_mmc_remove(struct platform_device *pdev)
1021 +{
1022 + struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1023 +
1024 + del_timer_sync(&host->timeout_timer);
1025 + jz4740_mmc_set_irq_enabled(host, 0xff, false);
1026 + jz4740_mmc_reset(host);
1027 +
1028 + mmc_remove_host(host->mmc);
1029 +
1030 + free_irq(host->irq, host);
1031 + if (host->card_detect_irq >= 0)
1032 + free_irq(host->card_detect_irq, host);
1033 +
1034 + jz4740_mmc_free_gpios(pdev);
1035 + jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1036 +
1037 + iounmap(host->base);
1038 + release_mem_region(host->mem->start, resource_size(host->mem));
1039 +
1040 + clk_put(host->clk);
1041 +
1042 + platform_set_drvdata(pdev, NULL);
1043 + mmc_free_host(host->mmc);
1044 +
1045 + return 0;
1046 +}
1047 +
1048 +#ifdef CONFIG_PM
1049 +
1050 +static int jz4740_mmc_suspend(struct device *dev)
1051 +{
1052 + struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1053 +
1054 + mmc_suspend_host(host->mmc);
1055 +
1056 + jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1057 +
1058 + return 0;
1059 +}
1060 +
1061 +static int jz4740_mmc_resume(struct device *dev)
1062 +{
1063 + struct jz4740_mmc_host *host = dev_get_drvdata(dev);
1064 +
1065 + jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
1066 +
1067 + mmc_resume_host(host->mmc);
1068 +
1069 + return 0;
1070 +}
1071 +
1072 +const struct dev_pm_ops jz4740_mmc_pm_ops = {
1073 + .suspend = jz4740_mmc_suspend,
1074 + .resume = jz4740_mmc_resume,
1075 + .poweroff = jz4740_mmc_suspend,
1076 + .restore = jz4740_mmc_resume,
1077 +};
1078 +
1079 +#define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
1080 +#else
1081 +#define JZ4740_MMC_PM_OPS NULL
1082 +#endif
1083 +
1084 +static struct platform_driver jz4740_mmc_driver = {
1085 + .probe = jz4740_mmc_probe,
1086 + .remove = __devexit_p(jz4740_mmc_remove),
1087 + .driver = {
1088 + .name = "jz4740-mmc",
1089 + .owner = THIS_MODULE,
1090 + .pm = JZ4740_MMC_PM_OPS,
1091 + },
1092 +};
1093 +
1094 +static int __init jz4740_mmc_init(void)
1095 +{
1096 + return platform_driver_register(&jz4740_mmc_driver);
1097 +}
1098 +module_init(jz4740_mmc_init);
1099 +
1100 +static void __exit jz4740_mmc_exit(void)
1101 +{
1102 + platform_driver_unregister(&jz4740_mmc_driver);
1103 +}
1104 +module_exit(jz4740_mmc_exit);
1105 +
1106 +MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
1107 +MODULE_LICENSE("GPL");
1108 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1109 --
1110 1.5.6.5
1111
Staging tree of Christian Lamparter