#define IFX_MPS_PLATFORM_NAME "MIPS24KEc"
--- a/src/mps/drv_mps_vmmc_linux.c
+++ b/src/mps/drv_mps_vmmc_linux.c
-@@ -2225,7 +2225,7 @@ IFX_int32_t __init ifx_mps_init_module (
+@@ -2229,7 +2229,7 @@ IFX_int32_t __init ifx_mps_init_module (
#if defined(CONFIG_MIPS) && !defined(CONFIG_MIPS_UNCACHED)
#if defined(SYSTEM_DANUBE)
bDoCacheOps = IFX_TRUE; /* on Danube always perform cache ops */
/* on AR9/VR9 cache is configured by BSP;
here we check whether the D-cache is shared or partitioned;
1) in case of shared D-cache all cache operations are omitted;
-@@ -2255,7 +2255,8 @@ IFX_int32_t __init ifx_mps_init_module (
+@@ -2259,7 +2259,8 @@ IFX_int32_t __init ifx_mps_init_module (
/* reset the device before initializing the device driver */
ifx_mps_reset ();
+
+ result = request_irq (INT_NUM_IM4_IRL18,
#ifdef LINUX_2_6
- ifx_mps_ad0_irq, IRQF_DISABLED
+ ifx_mps_ad0_irq, 0x0
#else /* */
-@@ -2396,7 +2397,7 @@ IFX_int32_t __init ifx_mps_init_module (
+@@ -2400,7 +2401,7 @@ IFX_int32_t __init ifx_mps_init_module (
if (result = ifx_mps_init_gpt_danube ())
return result;
#endif /*DANUBE*/
+IFX_void_t ifx_mps_release (IFX_void_t);
+extern IFX_uint32_t ifx_mps_reset_structures (mps_comm_dev * pMPSDev);
+extern IFX_int32_t ifx_mps_bufman_close (IFX_void_t);
-+IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count);
++IFX_int32_t ifx_mps_wdog_callback (IFX_ulong_t wdog_cleared_ok_count);
+extern IFXOS_event_t fw_ready_evt;
+/* ============================= */
+/* Local function declaration */
+ * \return 0 IFX_SUCCESS, cannot fail
+ * \ingroup Internal
+ */
-+IFX_int32_t ifx_mps_wdog_callback (IFX_uint32_t wdog_cleared_ok_count)
++IFX_int32_t ifx_mps_wdog_callback (IFX_ulong_t wdog_cleared_ok_count)
+{
+#ifdef DEBUG
+ TRACE (MPS, DBG_LEVEL_HIGH,
pMPSDev->event.MPS_Ad1Reg.val = MPS_Ad1StatusReg.val;
/* use callback function or queue wake up to notify about data reception */
-@@ -2977,11 +2990,13 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t
+@@ -2977,11 +2990,13 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t
IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;
/* handle only enabled interrupts */
MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];
+++ b/src/mps/drv_mps_vmmc_device.h
@@ -22,7 +22,12 @@
# include <lantiq_soc.h>
- # include <gpio.h>
+ # include <linux/gpio.h>
#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
+#if defined(SYSTEM_FALCON)
+#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1D004000)