#include "ag71xx.h"
-#if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
-static inline void skb_free_frag(void *data)
-{
- put_page(virt_to_head_page(data));
-}
-#endif
-
#define AG71XX_DEFAULT_MSG_ENABLE \
(NETIF_MSG_DRV \
| NETIF_MSG_PROBE \
#define ETH_SWITCH_HEADER_LEN 2
static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
+static void ag71xx_qca955x_sgmii_init(void);
static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
{
(intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
}
-static void ag71xx_ring_free(struct ag71xx_ring *ring)
-{
- int ring_size = BIT(ring->order);
- kfree(ring->buf);
-
- if (ring->descs_cpu)
- dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
- ring->descs_cpu, ring->descs_dma);
-}
-
-static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
-{
- int ring_size = BIT(ring->order);
- int err;
-
- ring->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
- &ring->descs_dma, GFP_ATOMIC);
- if (!ring->descs_cpu) {
- err = -ENOMEM;
- goto err;
- }
-
-
- ring->buf = kzalloc(ring_size * sizeof(*ring->buf), GFP_KERNEL);
- if (!ring->buf) {
- err = -ENOMEM;
- goto err;
- }
-
- return 0;
-
-err:
- return err;
-}
-
static void ag71xx_ring_tx_clean(struct ag71xx *ag)
{
struct ag71xx_ring *ring = &ag->tx_ring;
static int ag71xx_rings_init(struct ag71xx *ag)
{
- int ret;
+ struct ag71xx_ring *tx = &ag->tx_ring;
+ struct ag71xx_ring *rx = &ag->rx_ring;
+ int ring_size = BIT(tx->order) + BIT(rx->order);
+ int tx_size = BIT(tx->order);
+
+ tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
+ if (!tx->buf)
+ return -ENOMEM;
+
+ tx->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
+ &tx->descs_dma, GFP_ATOMIC);
+ if (!tx->descs_cpu) {
+ kfree(tx->buf);
+ tx->buf = NULL;
+ return -ENOMEM;
+ }
- ret = ag71xx_ring_alloc(&ag->tx_ring);
- if (ret)
- return ret;
+ rx->buf = &tx->buf[BIT(tx->order)];
+ rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
+ rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
ag71xx_ring_tx_init(ag);
+ return ag71xx_ring_rx_init(ag);
+}
- ret = ag71xx_ring_alloc(&ag->rx_ring);
- if (ret)
- return ret;
+static void ag71xx_rings_free(struct ag71xx *ag)
+{
+ struct ag71xx_ring *tx = &ag->tx_ring;
+ struct ag71xx_ring *rx = &ag->rx_ring;
+ int ring_size = BIT(tx->order) + BIT(rx->order);
- ret = ag71xx_ring_rx_init(ag);
- return ret;
+ if (tx->descs_cpu)
+ dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
+ tx->descs_cpu, tx->descs_dma);
+
+ kfree(tx->buf);
+
+ tx->descs_cpu = NULL;
+ rx->descs_cpu = NULL;
+ tx->buf = NULL;
+ rx->buf = NULL;
}
static void ag71xx_rings_cleanup(struct ag71xx *ag)
{
ag71xx_ring_rx_clean(ag);
- ag71xx_ring_free(&ag->rx_ring);
-
ag71xx_ring_tx_clean(ag);
+ ag71xx_rings_free(ag);
+
netdev_reset_queue(ag->dev);
- ag71xx_ring_free(&ag->tx_ring);
}
static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
/* setup FIFO configuration registers */
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
if (pdata->is_ar724x) {
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0010ffff);
+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x015500aa);
} else {
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
if (pdata->is_ar91xx)
fifo3 = 0x00780fff;
else if (pdata->is_ar724x)
- fifo3 = pdata->fifo_cfg3;
+ fifo3 = 0x01f00140;
else
fifo3 = 0x008001ff;
if (update && pdata->set_speed)
pdata->set_speed(ag->speed);
+ if (update && pdata->enable_sgmii_fixup)
+ ag71xx_qca955x_sgmii_init();
+
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
+
+ if (pdata->disable_inline_checksum_engine) {
+ /*
+ * The rx ring buffer can stall on small packets on QCA953x and
+ * QCA956x. Disabling the inline checksum engine fixes the stall.
+ * The wr, rr functions cannot be used since this hidden register
+ * is outside of the normal ag71xx register block.
+ */
+ void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
+ if (dam) {
+ __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
+ (void)__raw_readl(dam);
+ iounmap(dam);
+ }
+ }
+
ag71xx_hw_start(ag);
netif_carrier_on(ag->dev);
ag71xx_speed_str(ag),
(DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
- DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
- ag->dev->name,
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
-
- DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
- ag->dev->name,
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
-
- DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
- ag->dev->name,
- ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
- ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
+ ag71xx_dump_regs(ag);
}
void ag71xx_link_adjust(struct ag71xx *ag)
static void ag71xx_hw_disable(struct ag71xx *ag)
{
- unsigned long flags;
-
- spin_lock_irqsave(&ag->lock, flags);
-
netif_stop_queue(ag->dev);
ag71xx_hw_stop(ag);
napi_disable(&ag->napi);
del_timer_sync(&ag->oom_timer);
- spin_unlock_irqrestore(&ag->lock, flags);
-
ag71xx_rings_cleanup(ag);
}
i = (ring->curr + n - 1) & ring_mask;
ring->buf[i].len = skb->len;
ring->buf[i].skb = skb;
- ring->buf[i].timestamp = jiffies;
netdev_sent_queue(dev, skb->len);
static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
struct ag71xx *ag = netdev_priv(dev);
- int ret;
switch (cmd) {
- case SIOCETHTOOL:
- if (ag->phy_dev == NULL)
- break;
-
- spin_lock_irq(&ag->lock);
- ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
- spin_unlock_irq(&ag->lock);
- return ret;
-
case SIOCSIFHWADDR:
if (copy_from_user
(dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
schedule_delayed_work(&ag->restart_work, 1);
}
+static void ag71xx_bit_set(void __iomem *reg, u32 bit)
+{
+ u32 val = __raw_readl(reg) | bit;
+ __raw_writel(val, reg);
+ __raw_readl(reg);
+}
+
+static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
+{
+ u32 val = __raw_readl(reg) & ~bit;
+ __raw_writel(val, reg);
+ __raw_readl(reg);
+}
+
+static void ag71xx_qca955x_sgmii_init()
+{
+ void __iomem *gmac_base;
+ u32 mr_an_status, sgmii_status;
+ u8 tries = 0;
+
+ gmac_base = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+ if (!gmac_base)
+ goto sgmii_out;
+
+ mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
+ if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
+ goto sgmii_out;
+
+ __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET ,
+ gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
+ __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
+ udelay(10);
+
+ /* Init sequence */
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_HW_RX_125M_N);
+ udelay(10);
+
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_RX_125M_N);
+ udelay(10);
+
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_TX_125M_N);
+ udelay(10);
+
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_RX_CLK_N);
+ udelay(10);
+
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
+ QCA955X_SGMII_RESET_TX_CLK_N);
+ udelay(10);
+
+ do {
+ ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
+ QCA955X_MR_AN_CONTROL_PHY_RESET |
+ QCA955X_MR_AN_CONTROL_AN_ENABLE);
+ udelay(100);
+ ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
+ QCA955X_MR_AN_CONTROL_PHY_RESET);
+ mdelay(10);
+ sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) & 0xF;
+
+ if (tries++ >= QCA955X_SGMII_LINK_WAR_MAX_TRY) {
+ pr_warn("ag71xx: max retries for SGMII fixup exceeded!\n");
+ break;
+ }
+ } while (!(sgmii_status == 0xf || sgmii_status == 0x10));
+
+sgmii_out:
+ iounmap(gmac_base);
+}
+
static void ag71xx_restart_work_func(struct work_struct *work)
{
struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
rtnl_unlock();
}
-static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
+static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
{
+ unsigned long timestamp;
u32 rx_sm, tx_sm, rx_fd;
+ timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
if (likely(time_before(jiffies, timestamp + HZ/10)))
return false;
if (!flush && !ag71xx_desc_empty(desc)) {
if (pdata->is_ar724x &&
- ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) {
+ ag71xx_check_dma_stuck(ag)) {
schedule_delayed_work(&ag->restart_work, HZ / 2);
dma_stuck = true;
}
DBG("%s: %d packets sent out\n", ag->dev->name, sent);
- ag->dev->stats.tx_bytes += bytes_compl;
- ag->dev->stats.tx_packets += sent;
-
if (!sent)
return 0;
+ ag->dev->stats.tx_bytes += bytes_compl;
+ ag->dev->stats.tx_packets += sent;
+
netdev_completed_queue(ag->dev, sent, bytes_compl);
if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
netif_wake_queue(ag->dev);
projects / openwrt / staging / chunkeey.git / blobdiff