u32 init = MAC_CFG1_INIT;
/* setup MAC configuration registers */
- if (pdata->builtin_switch)
+ if (pdata->use_flow_control)
init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
+ ag71xx_tx_packets(ag, true);
+
ath79_device_reset_set(reset_mask);
udelay(10);
ath79_device_reset_clear(reset_mask);
ag71xx_dma_reset(ag);
ag71xx_hw_setup(ag);
- ag71xx_tx_packets(ag, true);
ag->tx_ring.curr = 0;
ag->tx_ring.dirty = 0;
netdev_reset_queue(ag->dev);
netdev_sent_queue(dev, skb->len);
+ skb_tx_timestamp(skb);
+
desc->ctrl &= ~DESC_EMPTY;
ring->curr += n;
{
struct ag71xx_ring *ring = &ag->tx_ring;
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
+ bool dma_stuck = false;
int ring_mask = BIT(ring->order) - 1;
int ring_size = BIT(ring->order);
int sent = 0;
if (!flush && !ag71xx_desc_empty(desc)) {
if (pdata->is_ar724x &&
- ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
+ ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) {
schedule_delayed_work(&ag->restart_work, HZ / 2);
+ dma_stuck = true;
+ }
break;
}
netdev_completed_queue(ag->dev, sent, bytes_compl);
if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
netif_wake_queue(ag->dev);
- cancel_delayed_work(&ag->restart_work);
+
+ if (!dma_stuck)
+ cancel_delayed_work(&ag->restart_work);
return sent;
}