#include <linux/of_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
+#include <linux/version.h>
#include "ar8216.h"
struct ar8xxx_chip {
unsigned long caps;
+ bool config_at_probe;
+ bool mii_lo_first;
+
+ /* parameters to calculate REG_PORT_STATS_BASE */
+ unsigned reg_port_stats_start;
+ unsigned reg_port_stats_length;
int (*hw_init)(struct ar8xxx_priv *priv);
void (*cleanup)(struct ar8xxx_priv *priv);
+ const char *name;
+ int vlans;
+ int ports;
+ const struct switch_dev_ops *swops;
+
void (*init_globals)(struct ar8xxx_priv *priv);
void (*init_port)(struct ar8xxx_priv *priv, int port);
void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
int (*atu_flush)(struct ar8xxx_priv *priv);
void (*vtu_flush)(struct ar8xxx_priv *priv);
void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
- void (*fixup_phys)(struct ar8xxx_priv *priv);
+ void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
+ void (*set_mirror_regs)(struct ar8xxx_priv *priv);
const struct ar8xxx_mib_desc *mib_decs;
unsigned num_mibs;
+ unsigned mib_func;
};
enum ar8327_led_pattern {
u8 chip_ver;
u8 chip_rev;
const struct ar8xxx_chip *chip;
- union {
- struct ar8327_data ar8327;
- } chip_data;
+ void *chip_data;
bool initialized;
bool port4_phy;
char buf[2048];
bool init;
- bool mii_lo_first;
struct mutex mib_lock;
struct delayed_work mib_work;
return -ETIMEDOUT;
}
+static int
+ar8xxx_phy_check_aneg(struct phy_device *phydev)
+{
+ int ret;
+
+ if (phydev->autoneg != AUTONEG_ENABLE)
+ return 0;
+ /*
+ * BMCR_ANENABLE might have been cleared
+ * by phy_init_hw in certain kernel versions
+ * therefore check for it
+ */
+ ret = phy_read(phydev, MII_BMCR);
+ if (ret < 0)
+ return ret;
+ if (ret & BMCR_ANENABLE)
+ return 0;
+
+ dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
+ ret |= BMCR_ANENABLE | BMCR_ANRESTART;
+ return phy_write(phydev, MII_BMCR, ret);
+}
+
+static void
+ar8xxx_phy_init(struct ar8xxx_priv *priv)
+{
+ int i;
+ struct mii_bus *bus;
+
+ bus = priv->mii_bus;
+ for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
+ if (priv->chip->phy_fixup)
+ priv->chip->phy_fixup(priv, i);
+
+ /* initialize the port itself */
+ mdiobus_write(bus, i, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
+ if (ar8xxx_has_gige(priv))
+ mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ }
+
+ ar8xxx_phy_poll_reset(bus);
+}
+
+static u32
+mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
+{
+ struct mii_bus *bus = priv->mii_bus;
+ u16 lo, hi;
+
+ lo = bus->read(bus, phy_id, regnum);
+ hi = bus->read(bus, phy_id, regnum + 1);
+
+ return (hi << 16) | lo;
+}
+
+static void
+mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
+{
+ struct mii_bus *bus = priv->mii_bus;
+ u16 lo, hi;
+
+ lo = val & 0xffff;
+ hi = (u16) (val >> 16);
+
+ if (priv->chip->mii_lo_first)
+ {
+ bus->write(bus, phy_id, regnum, lo);
+ bus->write(bus, phy_id, regnum + 1, hi);
+ } else {
+ bus->write(bus, phy_id, regnum + 1, hi);
+ bus->write(bus, phy_id, regnum, lo);
+ }
+}
+
static u32
ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
{
struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
- u16 lo, hi;
+ u32 val;
split_addr((u32) reg, &r1, &r2, &page);
bus->write(bus, 0x18, 0, page);
usleep_range(1000, 2000); /* wait for the page switch to propagate */
- lo = bus->read(bus, 0x10 | r2, r1);
- hi = bus->read(bus, 0x10 | r2, r1 + 1);
+ val = mii_read32(priv, 0x10 | r2, r1);
mutex_unlock(&bus->mdio_lock);
- return (hi << 16) | lo;
+ return val;
}
static void
ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
{
struct mii_bus *bus = priv->mii_bus;
- u16 r1, r2, r3;
- u16 lo, hi;
+ u16 r1, r2, page;
- split_addr((u32) reg, &r1, &r2, &r3);
- lo = val & 0xffff;
- hi = (u16) (val >> 16);
+ split_addr((u32) reg, &r1, &r2, &page);
mutex_lock(&bus->mdio_lock);
- bus->write(bus, 0x18, 0, r3);
+ bus->write(bus, 0x18, 0, page);
usleep_range(1000, 2000); /* wait for the page switch to propagate */
- if (priv->mii_lo_first) {
- bus->write(bus, 0x10 | r2, r1, lo);
- bus->write(bus, 0x10 | r2, r1 + 1, hi);
- } else {
- bus->write(bus, 0x10 | r2, r1 + 1, hi);
- bus->write(bus, 0x10 | r2, r1, lo);
- }
+ mii_write32(priv, 0x10 | r2, r1, val);
mutex_unlock(&bus->mdio_lock);
}
{
struct mii_bus *bus = priv->mii_bus;
u16 r1, r2, page;
- u16 lo, hi;
u32 ret;
split_addr((u32) reg, &r1, &r2, &page);
bus->write(bus, 0x18, 0, page);
usleep_range(1000, 2000); /* wait for the page switch to propagate */
- lo = bus->read(bus, 0x10 | r2, r1);
- hi = bus->read(bus, 0x10 | r2, r1 + 1);
-
- ret = hi << 16 | lo;
+ ret = mii_read32(priv, 0x10 | r2, r1);
ret &= ~mask;
ret |= val;
-
- lo = ret & 0xffff;
- hi = (u16) (ret >> 16);
-
- if (priv->mii_lo_first) {
- bus->write(bus, 0x10 | r2, r1, lo);
- bus->write(bus, 0x10 | r2, r1 + 1, hi);
- } else {
- bus->write(bus, 0x10 | r2, r1 + 1, hi);
- bus->write(bus, 0x10 | r2, r1, lo);
- }
+ mii_write32(priv, 0x10 | r2, r1, ret);
mutex_unlock(&bus->mdio_lock);
return ret;
}
-
static void
ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
u16 dbg_addr, u16 dbg_data)
static int
ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
{
- unsigned mib_func;
+ unsigned mib_func = priv->chip->mib_func;
int ret;
lockdep_assert_held(&priv->mib_lock);
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
- mib_func = AR8327_REG_MIB_FUNC;
- else
- mib_func = AR8216_REG_MIB_FUNC;
-
/* Capture the hardware statistics for all ports */
ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
lockdep_assert_held(&priv->mib_lock);
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
- base = AR8327_REG_PORT_STATS_BASE(port);
- else if (chip_is_ar8236(priv) ||
- chip_is_ar8316(priv))
- base = AR8236_REG_PORT_STATS_BASE(port);
- else
- base = AR8216_REG_PORT_STATS_BASE(port);
+ base = priv->chip->reg_port_stats_start +
+ priv->chip->reg_port_stats_length * port;
mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
for (i = 0; i < priv->chip->num_mibs; i++) {
static int
ar8216_hw_init(struct ar8xxx_priv *priv)
{
+ if (priv->initialized)
+ return 0;
+
+ ar8xxx_phy_init(priv);
+
+ priv->initialized = true;
return 0;
}
}
}
-static const struct ar8xxx_chip ar8216_chip = {
- .caps = AR8XXX_CAP_MIB_COUNTERS,
-
- .hw_init = ar8216_hw_init,
- .init_globals = ar8216_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8216_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
-
- .num_mibs = ARRAY_SIZE(ar8216_mibs),
- .mib_decs = ar8216_mibs,
-};
-
static void
ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
{
(members << AR8236_PORT_VLAN2_MEMBER_S));
}
-static int
-ar8236_hw_init(struct ar8xxx_priv *priv)
-{
- int i;
- struct mii_bus *bus;
-
- if (priv->initialized)
- return 0;
-
- /* Initialize the PHYs */
- bus = priv->mii_bus;
- for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
- mdiobus_write(bus, i, MII_ADVERTISE,
- ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
- ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- }
-
- ar8xxx_phy_poll_reset(bus);
-
- priv->initialized = true;
- return 0;
-}
-
static void
ar8236_init_globals(struct ar8xxx_priv *priv)
{
ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8316_GCTRL_MTU, 9018 + 8 + 2);
+ /* enable cpu port to receive arp frames */
+ ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
+ AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
+
+ /* enable cpu port to receive multicast and broadcast frames */
+ ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
+ AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
+ AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
+
/* Enable MIB counters */
ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
(AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
AR8236_MIB_EN);
}
-static const struct ar8xxx_chip ar8236_chip = {
- .caps = AR8XXX_CAP_MIB_COUNTERS,
- .hw_init = ar8236_hw_init,
- .init_globals = ar8236_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8236_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
-
- .num_mibs = ARRAY_SIZE(ar8236_mibs),
- .mib_decs = ar8236_mibs,
-};
-
static int
ar8316_hw_init(struct ar8xxx_priv *priv)
{
- int i;
u32 val, newval;
- struct mii_bus *bus;
val = priv->read(priv, AR8316_REG_POSTRIP);
msleep(1000);
}
- /* Initialize the ports */
- bus = priv->mii_bus;
- for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
- /* initialize the port itself */
- mdiobus_write(bus, i, MII_ADVERTISE,
- ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- }
-
- ar8xxx_phy_poll_reset(bus);
+ ar8xxx_phy_init(priv);
out:
priv->initialized = true;
AR8236_MIB_EN);
}
-static const struct ar8xxx_chip ar8316_chip = {
- .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
- .hw_init = ar8316_hw_init,
- .init_globals = ar8316_init_globals,
- .init_port = ar8216_init_port,
- .setup_port = ar8216_setup_port,
- .read_port_status = ar8216_read_port_status,
- .atu_flush = ar8216_atu_flush,
- .vtu_flush = ar8216_vtu_flush,
- .vtu_load_vlan = ar8216_vtu_load_vlan,
-
- .num_mibs = ARRAY_SIZE(ar8236_mibs),
- .mib_decs = ar8236_mibs,
-};
-
static u32
ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
{
ar8327_led_enable_hw_mode_store);
static int
-ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
+ar8327_led_register(struct ar8327_led *aled)
{
int ret;
ar8327_led_create(struct ar8xxx_priv *priv,
const struct ar8327_led_info *led_info)
{
- struct ar8327_data *data = &priv->chip_data.ar8327;
+ struct ar8327_data *data = priv->chip_data;
struct ar8327_led *aled;
int ret;
mutex_init(&aled->mutex);
INIT_WORK(&aled->led_work, ar8327_led_work_func);
- ret = ar8327_led_register(priv, aled);
+ ret = ar8327_led_register(aled);
if (ret)
goto err_free;
static void
ar8327_leds_init(struct ar8xxx_priv *priv)
{
- struct ar8327_data *data;
+ struct ar8327_data *data = priv->chip_data;
unsigned i;
if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
return;
- data = &priv->chip_data.ar8327;
-
for (i = 0; i < data->num_leds; i++) {
struct ar8327_led *aled;
static void
ar8327_leds_cleanup(struct ar8xxx_priv *priv)
{
- struct ar8327_data *data = &priv->chip_data.ar8327;
+ struct ar8327_data *data = priv->chip_data;
unsigned i;
if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
struct ar8327_platform_data *pdata)
{
struct ar8327_led_cfg *led_cfg;
- struct ar8327_data *data;
+ struct ar8327_data *data = priv->chip_data;
u32 pos, new_pos;
u32 t;
priv->get_port_link = pdata->get_port_link;
- data = &priv->chip_data.ar8327;
-
data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
static int
ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
{
+ struct ar8327_data *data = priv->chip_data;
const __be32 *paddr;
int len;
int i;
switch (reg) {
case AR8327_REG_PORT_STATUS(0):
- priv->chip_data.ar8327.port0_status = val;
+ data->port0_status = val;
break;
case AR8327_REG_PORT_STATUS(6):
- priv->chip_data.ar8327.port6_status = val;
+ data->port6_status = val;
break;
default:
priv->write(priv, reg, val);
static int
ar8327_hw_init(struct ar8xxx_priv *priv)
{
- struct mii_bus *bus;
int ret;
- int i;
+
+ priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
+ if (!priv->chip_data)
+ return -ENOMEM;
if (priv->phy->dev.of_node)
ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
ar8327_leds_init(priv);
- priv->chip->fixup_phys(priv);
-
- bus = priv->mii_bus;
- for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
- /* start aneg on the PHY */
- mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
- ADVERTISE_PAUSE_CAP |
- ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- }
-
- ar8xxx_phy_poll_reset(bus);
+ ar8xxx_phy_init(priv);
return 0;
}
static void
ar8327_init_port(struct ar8xxx_priv *priv, int port)
{
+ struct ar8327_data *data = priv->chip_data;
u32 t;
if (port == AR8216_PORT_CPU)
- t = priv->chip_data.ar8327.port0_status;
+ t = data->port0_status;
else if (port == 6)
- t = priv->chip_data.ar8327.port6_status;
+ t = data->port6_status;
else
t = AR8216_PORT_STATUS_LINK_AUTO;
priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
}
-static void
-ar8327_fixup_phys(struct ar8xxx_priv *priv)
-{
- int i;
-
- for (i = 0; i < AR8XXX_NUM_PHYS; i++)
- ar8327_phy_fixup(priv, i);
-}
-
-static const struct ar8xxx_chip ar8327_chip = {
- .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
- .hw_init = ar8327_hw_init,
- .cleanup = ar8327_cleanup,
- .init_globals = ar8327_init_globals,
- .init_port = ar8327_init_port,
- .setup_port = ar8327_setup_port,
- .read_port_status = ar8327_read_port_status,
- .atu_flush = ar8327_atu_flush,
- .vtu_flush = ar8327_vtu_flush,
- .vtu_load_vlan = ar8327_vtu_load_vlan,
- .fixup_phys = ar8327_fixup_phys,
-
- .num_mibs = ARRAY_SIZE(ar8236_mibs),
- .mib_decs = ar8236_mibs,
-};
-
static int
ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
struct switch_val *val)
AR8216_PORT_CTRL_MIRROR_TX);
}
-static void
-ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
-{
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
- ar8327_set_mirror_regs(priv);
- } else {
- ar8216_set_mirror_regs(priv);
- }
-}
-
static int
ar8xxx_sw_hw_apply(struct switch_dev *dev)
{
priv->chip->setup_port(priv, i, portmask[i]);
}
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
mutex_lock(&priv->reg_mutex);
priv->mirror_rx = !!val->value.i;
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
mutex_lock(&priv->reg_mutex);
priv->mirror_tx = !!val->value.i;
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
mutex_lock(&priv->reg_mutex);
priv->monitor_port = val->value.i;
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
mutex_lock(&priv->reg_mutex);
priv->source_port = val->value.i;
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
.get_port_link = ar8xxx_sw_get_port_link,
};
+static const struct ar8xxx_chip ar8216_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x19000,
+ .reg_port_stats_length = 0xa0,
+
+ .name = "Atheros AR8216",
+ .ports = AR8216_NUM_PORTS,
+ .vlans = AR8216_NUM_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar8216_hw_init,
+ .init_globals = ar8216_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8216_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+
+ .num_mibs = ARRAY_SIZE(ar8216_mibs),
+ .mib_decs = ar8216_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
+};
+
+static const struct ar8xxx_chip ar8236_chip = {
+ .caps = AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+
+ .name = "Atheros AR8236",
+ .ports = AR8216_NUM_PORTS,
+ .vlans = AR8216_NUM_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar8216_hw_init,
+ .init_globals = ar8236_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8236_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
+};
+
+static const struct ar8xxx_chip ar8316_chip = {
+ .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+
+ .name = "Atheros AR8316",
+ .ports = AR8216_NUM_PORTS,
+ .vlans = AR8X16_MAX_VLANS,
+ .swops = &ar8xxx_sw_ops,
+
+ .hw_init = ar8316_hw_init,
+ .init_globals = ar8316_init_globals,
+ .init_port = ar8216_init_port,
+ .setup_port = ar8216_setup_port,
+ .read_port_status = ar8216_read_port_status,
+ .atu_flush = ar8216_atu_flush,
+ .vtu_flush = ar8216_vtu_flush,
+ .vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
+};
+
+static const struct ar8xxx_chip ar8327_chip = {
+ .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
+ .config_at_probe = true,
+ .mii_lo_first = true,
+
+ .name = "Atheros AR8327",
+ .ports = AR8327_NUM_PORTS,
+ .vlans = AR8X16_MAX_VLANS,
+ .swops = &ar8327_sw_ops,
+
+ .reg_port_stats_start = 0x1000,
+ .reg_port_stats_length = 0x100,
+
+ .hw_init = ar8327_hw_init,
+ .cleanup = ar8327_cleanup,
+ .init_globals = ar8327_init_globals,
+ .init_port = ar8327_init_port,
+ .setup_port = ar8327_setup_port,
+ .read_port_status = ar8327_read_port_status,
+ .atu_flush = ar8327_atu_flush,
+ .vtu_flush = ar8327_vtu_flush,
+ .vtu_load_vlan = ar8327_vtu_load_vlan,
+ .phy_fixup = ar8327_phy_fixup,
+ .set_mirror_regs = ar8327_set_mirror_regs,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8327_REG_MIB_FUNC
+};
+
+static const struct ar8xxx_chip ar8337_chip = {
+ .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
+ .config_at_probe = true,
+ .mii_lo_first = true,
+
+ .name = "Atheros AR8337",
+ .ports = AR8327_NUM_PORTS,
+ .vlans = AR8X16_MAX_VLANS,
+ .swops = &ar8327_sw_ops,
+
+ .reg_port_stats_start = 0x1000,
+ .reg_port_stats_length = 0x100,
+
+ .hw_init = ar8327_hw_init,
+ .cleanup = ar8327_cleanup,
+ .init_globals = ar8327_init_globals,
+ .init_port = ar8327_init_port,
+ .setup_port = ar8327_setup_port,
+ .read_port_status = ar8327_read_port_status,
+ .atu_flush = ar8327_atu_flush,
+ .vtu_flush = ar8327_vtu_flush,
+ .vtu_load_vlan = ar8327_vtu_load_vlan,
+ .phy_fixup = ar8327_phy_fixup,
+ .set_mirror_regs = ar8327_set_mirror_regs,
+
+ .num_mibs = ARRAY_SIZE(ar8236_mibs),
+ .mib_decs = ar8236_mibs,
+ .mib_func = AR8327_REG_MIB_FUNC
+};
+
static int
ar8xxx_id_chip(struct ar8xxx_priv *priv)
{
priv->chip = &ar8316_chip;
break;
case AR8XXX_VER_AR8327:
- priv->mii_lo_first = true;
priv->chip = &ar8327_chip;
break;
case AR8XXX_VER_AR8337:
- priv->mii_lo_first = true;
- priv->chip = &ar8327_chip;
+ priv->chip = &ar8337_chip;
break;
default:
pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
if (priv->chip && priv->chip->cleanup)
priv->chip->cleanup(priv);
+ kfree(priv->chip_data);
kfree(priv->mib_stats);
kfree(priv);
}
static int
ar8xxx_probe_switch(struct ar8xxx_priv *priv)
{
+ const struct ar8xxx_chip *chip;
struct switch_dev *swdev;
int ret;
if (ret)
return ret;
+ chip = priv->chip;
+
swdev = &priv->dev;
swdev->cpu_port = AR8216_PORT_CPU;
- swdev->ops = &ar8xxx_sw_ops;
-
- if (chip_is_ar8316(priv)) {
- swdev->name = "Atheros AR8316";
- swdev->vlans = AR8X16_MAX_VLANS;
- swdev->ports = AR8216_NUM_PORTS;
- } else if (chip_is_ar8236(priv)) {
- swdev->name = "Atheros AR8236";
- swdev->vlans = AR8216_NUM_VLANS;
- swdev->ports = AR8216_NUM_PORTS;
- } else if (chip_is_ar8327(priv)) {
- swdev->name = "Atheros AR8327";
- swdev->vlans = AR8X16_MAX_VLANS;
- swdev->ports = AR8327_NUM_PORTS;
- swdev->ops = &ar8327_sw_ops;
- } else if (chip_is_ar8337(priv)) {
- swdev->name = "Atheros AR8337";
- swdev->vlans = AR8X16_MAX_VLANS;
- swdev->ports = AR8327_NUM_PORTS;
- swdev->ops = &ar8327_sw_ops;
- } else {
- swdev->name = "Atheros AR8216";
- swdev->vlans = AR8216_NUM_VLANS;
- swdev->ports = AR8216_NUM_PORTS;
- }
+ swdev->name = chip->name;
+ swdev->vlans = chip->vlans;
+ swdev->ports = chip->ports;
+ swdev->ops = chip->swops;
ret = ar8xxx_mib_init(priv);
if (ret)
if (WARN_ON(!priv))
return -ENODEV;
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
- return 0;
+ if (priv->chip->config_at_probe)
+ return ar8xxx_phy_check_aneg(phydev);
priv->phy = phydev;
phydev->advertising = ADVERTISED_100baseT_Full;
}
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
+ if (priv->chip->config_at_probe) {
priv->phy = phydev;
ret = ar8xxx_start(priv);
ar8xxx_free(priv);
}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
+static int
+ar8xxx_phy_soft_reset(struct phy_device *phydev)
+{
+ /* we don't need an extra reset */
+ return 0;
+}
+#endif
+
static struct phy_driver ar8xxx_phy_driver = {
.phy_id = 0x004d0000,
.name = "Atheros AR8216/AR8236/AR8316",
.config_init = ar8xxx_phy_config_init,
.config_aneg = ar8xxx_phy_config_aneg,
.read_status = ar8xxx_phy_read_status,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
+ .soft_reset = ar8xxx_phy_soft_reset,
+#endif
.driver = { .owner = THIS_MODULE },
};
projects / openwrt / staging / chunkeey.git / blobdiff