#include <linux/of_device.h>
#include <linux/leds.h>
#include <linux/gpio.h>
+#include <linux/version.h>
#include "ar8216.h"
#define AR8XXX_CAP_GIGE BIT(0)
#define AR8XXX_CAP_MIB_COUNTERS BIT(1)
+#define AR8XXX_NUM_PHYS 5
+
+static void ar8216_set_mirror_regs(struct ar8xxx_priv *priv);
+static void ar8327_set_mirror_regs(struct ar8xxx_priv *priv);
+
enum {
AR8XXX_VER_AR8216 = 0x01,
AR8XXX_VER_AR8236 = 0x03,
struct ar8xxx_chip {
unsigned long caps;
+ bool config_at_probe;
+ bool mii_lo_first;
+
+ /* parameters to calculate REG_PORT_STATS_BASE */
+ unsigned reg_port_stats_start;
+ unsigned reg_port_stats_length;
int (*hw_init)(struct ar8xxx_priv *priv);
void (*cleanup)(struct ar8xxx_priv *priv);
u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
int (*atu_flush)(struct ar8xxx_priv *priv);
void (*vtu_flush)(struct ar8xxx_priv *priv);
- void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vlan);
+ void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
+ void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
+ void (*set_mirror_regs)(struct ar8xxx_priv *priv);
const struct ar8xxx_mib_desc *mib_decs;
unsigned num_mibs;
+ unsigned mib_func;
};
enum ar8327_led_pattern {
enum ar8327_led_pattern pattern;
};
-struct ar8216_data {
- u8 vlan_tagged;
-};
-
struct ar8327_data {
- u8 vlan_tagged[AR8X16_MAX_VLANS];
u32 port0_status;
u32 port6_status;
u8 chip_ver;
u8 chip_rev;
const struct ar8xxx_chip *chip;
- union {
- struct ar8216_data ar8216;
- struct ar8327_data ar8327;
- } chip_data;
+ void *chip_data;
bool initialized;
bool port4_phy;
char buf[2048];
bool init;
- bool mii_lo_first;
struct mutex mib_lock;
struct delayed_work mib_work;
bool vlan;
u16 vlan_id[AR8X16_MAX_VLANS];
u8 vlan_table[AR8X16_MAX_VLANS];
+ u8 vlan_tagged;
u16 pvid[AR8X16_MAX_PORTS];
/* mirroring */
*page = regaddr & 0x1ff;
}
+/* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
+static int
+ar8xxx_phy_poll_reset(struct mii_bus *bus)
+{
+ unsigned int sleep_msecs = 20;
+ int ret, elapsed, i;
+
+ for (elapsed = sleep_msecs; elapsed <= 600;
+ elapsed += sleep_msecs) {
+ msleep(sleep_msecs);
+ for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
+ ret = mdiobus_read(bus, i, MII_BMCR);
+ if (ret < 0)
+ return ret;
+ if (ret & BMCR_RESET)
+ break;
+ if (i == AR8XXX_NUM_PHYS - 1) {
+ usleep_range(1000, 2000);
+ return 0;
+ }
+ }
+ }
+ return -ETIMEDOUT;
+}
+
+static int
+ar8xxx_phy_check_aneg(struct phy_device *phydev)
+{
+ int ret;
+
+ if (phydev->autoneg != AUTONEG_ENABLE)
+ return 0;
+ /*
+ * BMCR_ANENABLE might have been cleared
+ * by phy_init_hw in certain kernel versions
+ * therefore check for it
+ */
+ ret = phy_read(phydev, MII_BMCR);
+ if (ret < 0)
+ return ret;
+ if (ret & BMCR_ANENABLE)
+ return 0;
+
+ dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
+ ret |= BMCR_ANENABLE | BMCR_ANRESTART;
+ return phy_write(phydev, MII_BMCR, ret);
+}
+
+static void
+ar8xxx_phy_init(struct ar8xxx_priv *priv)
+{
+ int i;
+ struct mii_bus *bus;
+
+ bus = priv->mii_bus;
+ for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
+ if (priv->chip->phy_fixup)
+ priv->chip->phy_fixup(priv, i);
+
+ /* initialize the port itself */
+ mdiobus_write(bus, i, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
+ if (ar8xxx_has_gige(priv))
+ mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
+ mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ }
+
+ ar8xxx_phy_poll_reset(bus);
+}
+
static u32
ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
{
bus->write(bus, 0x18, 0, r3);
usleep_range(1000, 2000); /* wait for the page switch to propagate */
- if (priv->mii_lo_first) {
+ if (priv->chip->mii_lo_first) {
bus->write(bus, 0x10 | r2, r1, lo);
bus->write(bus, 0x10 | r2, r1 + 1, hi);
} else {
lo = ret & 0xffff;
hi = (u16) (ret >> 16);
- if (priv->mii_lo_first) {
+ if (priv->chip->mii_lo_first) {
bus->write(bus, 0x10 | r2, r1, lo);
bus->write(bus, 0x10 | r2, r1 + 1, hi);
} else {
static int
ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
{
- unsigned mib_func;
+ unsigned mib_func = priv->chip->mib_func;
int ret;
lockdep_assert_held(&priv->mib_lock);
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
- mib_func = AR8327_REG_MIB_FUNC;
- else
- mib_func = AR8216_REG_MIB_FUNC;
-
/* Capture the hardware statistics for all ports */
ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
lockdep_assert_held(&priv->mib_lock);
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
- base = AR8327_REG_PORT_STATS_BASE(port);
- else if (chip_is_ar8236(priv) ||
- chip_is_ar8316(priv))
- base = AR8236_REG_PORT_STATS_BASE(port);
- else
- base = AR8216_REG_PORT_STATS_BASE(port);
+ base = priv->chip->reg_port_stats_start +
+ priv->chip->reg_port_stats_length * port;
mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
for (i = 0; i < priv->chip->num_mibs; i++) {
port = buf[0] & 0xf;
/* no need to fix up packets coming from a tagged source */
- if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
+ if (priv->vlan_tagged & (1 << port))
return;
/* lookup port vid from local table, the switch passes an invalid vlan id */
}
static void
-ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vlan)
+ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
{
u32 op;
- u32 vid = priv->vlan_id[vlan];
- u32 port_mask = priv->vlan_table[vlan];
-
op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
-
ar8216_vtu_op(priv, op, port_mask);
}
if (priv->vlan) {
pvid = priv->vlan_id[priv->pvid[port]];
- if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
+ if (priv->vlan_tagged & (1 << port))
egress = AR8216_OUT_ADD_VLAN;
else
egress = AR8216_OUT_STRIP_VLAN;
ingress = AR8216_IN_PORT_ONLY;
}
-
-
if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
header = AR8216_PORT_CTRL_HEADER;
else
static int
ar8216_hw_init(struct ar8xxx_priv *priv)
{
+ if (priv->initialized)
+ return 0;
+
+ ar8xxx_phy_init(priv);
+
+ priv->initialized = true;
return 0;
}
static const struct ar8xxx_chip ar8216_chip = {
.caps = AR8XXX_CAP_MIB_COUNTERS,
+ .reg_port_stats_start = 0x19000,
+ .reg_port_stats_length = 0xa0,
+
.hw_init = ar8216_hw_init,
.init_globals = ar8216_init_globals,
.init_port = ar8216_init_port,
.atu_flush = ar8216_atu_flush,
.vtu_flush = ar8216_vtu_flush,
.vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
.num_mibs = ARRAY_SIZE(ar8216_mibs),
.mib_decs = ar8216_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
};
static void
if (priv->vlan) {
pvid = priv->vlan_id[priv->pvid[port]];
- if (priv->chip_data.ar8216.vlan_tagged & BIT(port))
+ if (priv->vlan_tagged & (1 << port))
egress = AR8216_OUT_ADD_VLAN;
else
egress = AR8216_OUT_STRIP_VLAN;
(members << AR8236_PORT_VLAN2_MEMBER_S));
}
-static int
-ar8236_hw_init(struct ar8xxx_priv *priv)
-{
- int i;
- struct mii_bus *bus;
-
- if (priv->initialized)
- return 0;
-
- /* Initialize the PHYs */
- bus = priv->mii_bus;
- for (i = 0; i < 5; i++) {
- mdiobus_write(bus, i, MII_ADVERTISE,
- ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
- ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- }
- msleep(1000);
-
- priv->initialized = true;
- return 0;
-}
-
static void
ar8236_init_globals(struct ar8xxx_priv *priv)
{
ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
AR8316_GCTRL_MTU, 9018 + 8 + 2);
+ /* enable cpu port to receive arp frames */
+ ar8xxx_rmw(priv, AR8216_REG_ATU_CTRL,
+ AR8236_ATU_CTRL_RES, AR8236_ATU_CTRL_RES);
+
+ /* enable cpu port to receive multicast and broadcast frames */
+ ar8xxx_rmw(priv, AR8216_REG_FLOOD_MASK,
+ AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN,
+ AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
+
/* Enable MIB counters */
ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
(AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
static const struct ar8xxx_chip ar8236_chip = {
.caps = AR8XXX_CAP_MIB_COUNTERS,
- .hw_init = ar8236_hw_init,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+
+ .hw_init = ar8216_hw_init,
.init_globals = ar8236_init_globals,
.init_port = ar8216_init_port,
.setup_port = ar8236_setup_port,
.atu_flush = ar8216_atu_flush,
.vtu_flush = ar8216_vtu_flush,
.vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
};
static int
ar8316_hw_init(struct ar8xxx_priv *priv)
{
- int i;
u32 val, newval;
- struct mii_bus *bus;
val = priv->read(priv, AR8316_REG_POSTRIP);
msleep(1000);
}
- /* Initialize the ports */
- bus = priv->mii_bus;
- for (i = 0; i < 5; i++) {
- /* initialize the port itself */
- mdiobus_write(bus, i, MII_ADVERTISE,
- ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- }
-
- msleep(1000);
+ ar8xxx_phy_init(priv);
out:
priv->initialized = true;
static const struct ar8xxx_chip ar8316_chip = {
.caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
+
+ .reg_port_stats_start = 0x20000,
+ .reg_port_stats_length = 0x100,
+
.hw_init = ar8316_hw_init,
.init_globals = ar8316_init_globals,
.init_port = ar8216_init_port,
.atu_flush = ar8216_atu_flush,
.vtu_flush = ar8216_vtu_flush,
.vtu_load_vlan = ar8216_vtu_load_vlan,
+ .set_mirror_regs = ar8216_set_mirror_regs,
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
+ .mib_func = AR8216_REG_MIB_FUNC
};
static u32
ar8327_led_create(struct ar8xxx_priv *priv,
const struct ar8327_led_info *led_info)
{
- struct ar8327_data *data = &priv->chip_data.ar8327;
+ struct ar8327_data *data = priv->chip_data;
struct ar8327_led *aled;
int ret;
static void
ar8327_leds_init(struct ar8xxx_priv *priv)
{
- struct ar8327_data *data;
+ struct ar8327_data *data = priv->chip_data;
unsigned i;
if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
return;
- data = &priv->chip_data.ar8327;
-
for (i = 0; i < data->num_leds; i++) {
struct ar8327_led *aled;
static void
ar8327_leds_cleanup(struct ar8xxx_priv *priv)
{
- struct ar8327_data *data = &priv->chip_data.ar8327;
+ struct ar8327_data *data = priv->chip_data;
unsigned i;
if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
struct ar8327_platform_data *pdata)
{
struct ar8327_led_cfg *led_cfg;
- struct ar8327_data *data;
+ struct ar8327_data *data = priv->chip_data;
u32 pos, new_pos;
u32 t;
priv->get_port_link = pdata->get_port_link;
- data = &priv->chip_data.ar8327;
-
data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
static int
ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
{
+ struct ar8327_data *data = priv->chip_data;
const __be32 *paddr;
int len;
int i;
switch (reg) {
case AR8327_REG_PORT_STATUS(0):
- priv->chip_data.ar8327.port0_status = val;
+ data->port0_status = val;
break;
case AR8327_REG_PORT_STATUS(6):
- priv->chip_data.ar8327.port6_status = val;
+ data->port6_status = val;
break;
default:
priv->write(priv, reg, val);
static int
ar8327_hw_init(struct ar8xxx_priv *priv)
{
- struct mii_bus *bus;
int ret;
- int i;
+
+ priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
+ if (!priv->chip_data)
+ return -ENOMEM;
if (priv->phy->dev.of_node)
ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
ar8327_leds_init(priv);
- bus = priv->mii_bus;
- for (i = 0; i < AR8327_NUM_PHYS; i++) {
- ar8327_phy_fixup(priv, i);
-
- /* start aneg on the PHY */
- mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
- ADVERTISE_PAUSE_CAP |
- ADVERTISE_PAUSE_ASYM);
- mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
- mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
- }
-
- msleep(1000);
+ ar8xxx_phy_init(priv);
return 0;
}
/* Enable MIB counters */
ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
AR8327_MODULE_EN_MIB);
+
+ /* Disable EEE on all ports due to stability issues */
+ t = priv->read(priv, AR8327_REG_EEE_CTRL);
+ t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
+ AR8327_EEE_CTRL_DISABLE_PHY(1) |
+ AR8327_EEE_CTRL_DISABLE_PHY(2) |
+ AR8327_EEE_CTRL_DISABLE_PHY(3) |
+ AR8327_EEE_CTRL_DISABLE_PHY(4);
+ priv->write(priv, AR8327_REG_EEE_CTRL, t);
}
static void
ar8327_init_port(struct ar8xxx_priv *priv, int port)
{
+ struct ar8327_data *data = priv->chip_data;
u32 t;
if (port == AR8216_PORT_CPU)
- t = priv->chip_data.ar8327.port0_status;
+ t = data->port0_status;
else if (port == 6)
- t = priv->chip_data.ar8327.port6_status;
+ t = data->port6_status;
else
t = AR8216_PORT_STATUS_LINK_AUTO;
}
static void
-ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vlan)
+ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
{
- u32 op, val;
+ u32 op;
+ u32 val;
int i;
- u32 vid = priv->vlan_id[vlan];
- u32 port_mask = priv->vlan_table[vlan];
- u32 tagged = priv->chip_data.ar8327.vlan_tagged[vlan];
-
-
op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
for (i = 0; i < AR8327_NUM_PORTS; i++) {
mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
else if (priv->vlan == 0)
mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
- else if (tagged & BIT(i))
+ else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
else
mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
static void
ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
{
- u32 ingress, mode;
- u32 pvid;
-
u32 t;
+ u32 egress, ingress;
+ u32 pvid = priv->vlan_id[priv->pvid[port]];
if (priv->vlan) {
- pvid = priv->vlan_id[priv->pvid[port]];
- mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
+ egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
ingress = AR8216_IN_SECURE;
} else {
- pvid = port;
- mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
+ egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
ingress = AR8216_IN_PORT_ONLY;
}
priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
- t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
+ t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
t = members;
static const struct ar8xxx_chip ar8327_chip = {
.caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
+ .config_at_probe = true,
+ .mii_lo_first = true,
+
+ .reg_port_stats_start = 0x1000,
+ .reg_port_stats_length = 0x100,
+
.hw_init = ar8327_hw_init,
.cleanup = ar8327_cleanup,
.init_globals = ar8327_init_globals,
.atu_flush = ar8327_atu_flush,
.vtu_flush = ar8327_vtu_flush,
.vtu_load_vlan = ar8327_vtu_load_vlan,
+ .phy_fixup = ar8327_phy_fixup,
+ .set_mirror_regs = ar8327_set_mirror_regs,
.num_mibs = ARRAY_SIZE(ar8236_mibs),
.mib_decs = ar8236_mibs,
+ .mib_func = AR8327_REG_MIB_FUNC
};
static int
}
static int
-ar8xxx_sw_get_ports(struct switch_val *val, int ports, u8 port_mask, u8 tagged)
+ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
{
+ struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
+ u8 ports = priv->vlan_table[val->port_vlan];
int i;
+
val->len = 0;
- for (i = 0; i < ports; i++) {
+ for (i = 0; i < dev->ports; i++) {
struct switch_port *p;
- if (!(port_mask & BIT(i)))
+ if (!(ports & (1 << i)))
continue;
p = &val->value.ports[val->len++];
p->id = i;
- if (tagged & BIT(i))
- p->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
+ if (priv->vlan_tagged & (1 << i))
+ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
else
p->flags = 0;
}
}
static int
-ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
+ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
{
- int ports = dev->ports;
struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
- u8 port_mask = priv->vlan_table[val->port_vlan];
- u8 tagged = priv->chip_data.ar8216.vlan_tagged;
+ u8 ports = priv->vlan_table[val->port_vlan];
+ int i;
- return ar8xxx_sw_get_ports(val, ports, port_mask, tagged);
-}
+ val->len = 0;
+ for (i = 0; i < dev->ports; i++) {
+ struct switch_port *p;
-static int
-ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
-{
- int ports = dev->ports;
- struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
- u8 port_mask = priv->vlan_table[val->port_vlan];
- u8 tagged = priv->chip_data.ar8327.vlan_tagged[val->port_vlan];
+ if (!(ports & (1 << i)))
+ continue;
- return ar8xxx_sw_get_ports(val, ports, port_mask, tagged);
+ p = &val->value.ports[val->len++];
+ p->id = i;
+ if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
+ p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
+ else
+ p->flags = 0;
+ }
+ return 0;
}
static int
-ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
+ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
{
struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
u8 *vt = &priv->vlan_table[val->port_vlan];
- u8 *tagged = &priv->chip_data.ar8216.vlan_tagged;
-
int i, j;
*vt = 0;
for (i = 0; i < val->len; i++) {
struct switch_port *p = &val->value.ports[i];
- if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
-
- /* if port was untagged before then
- * remove him from other vlans */
- if(*tagged & BIT(p->id)){
- for (j = 0; j < AR8X16_MAX_VLANS; j++) {
- if (j == val->port_vlan)
- continue;
-
- priv->vlan_table[j] &= ~(BIT(p->id));
- }
- }
-
- *tagged |= BIT(p->id);
+ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
+ priv->vlan_tagged |= (1 << p->id);
} else {
- *tagged &= ~(BIT(p->id));
+ priv->vlan_tagged &= ~(1 << p->id);
priv->pvid[p->id] = val->port_vlan;
/* make sure that an untagged port does not
for (j = 0; j < AR8X16_MAX_VLANS; j++) {
if (j == val->port_vlan)
continue;
-
- priv->vlan_table[j] &= ~(BIT(p->id));
+ priv->vlan_table[j] &= ~(1 << p->id);
}
}
- *vt |= BIT(p->id);
+ *vt |= 1 << p->id;
}
return 0;
}
{
struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
u8 *vt = &priv->vlan_table[val->port_vlan];
- u8 *vlan_tagged = priv->chip_data.ar8327.vlan_tagged;
- u8 *tagged = &vlan_tagged[val->port_vlan];
-
- int i, j;
+ int i;
*vt = 0;
- *tagged = 0;
for (i = 0; i < val->len; i++) {
struct switch_port *p = &val->value.ports[i];
- if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED)) {
- *tagged |= BIT(p->id);
+ if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
+ if (val->port_vlan == priv->pvid[p->id]) {
+ priv->vlan_tagged |= (1 << p->id);
+ }
} else {
+ priv->vlan_tagged &= ~(1 << p->id);
priv->pvid[p->id] = val->port_vlan;
}
- *vt |= BIT(p->id);
+ *vt |= 1 << p->id;
}
return 0;
}
AR8216_PORT_CTRL_MIRROR_TX);
}
-static void
-ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
-{
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
- ar8327_set_mirror_regs(priv);
- } else {
- ar8216_set_mirror_regs(priv);
- }
-}
-
static int
ar8xxx_sw_hw_apply(struct switch_dev *dev)
{
continue;
for (i = 0; i < dev->ports; i++) {
- u8 mask = BIT(i);
+ u8 mask = (1 << i);
if (vp & mask)
portmask[i] |= vp & ~mask;
}
- priv->chip->vtu_load_vlan(priv, j);
+
+ priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
+ priv->vlan_table[j]);
}
} else {
/* vlan disabled:
if (i == AR8216_PORT_CPU)
continue;
- portmask[i] = BIT(AR8216_PORT_CPU);
- portmask[AR8216_PORT_CPU] |= BIT(i);
+ portmask[i] = 1 << AR8216_PORT_CPU;
+ portmask[AR8216_PORT_CPU] |= (1 << i);
}
}
priv->chip->setup_port(priv, i, portmask[i]);
}
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
mutex_lock(&priv->reg_mutex);
priv->mirror_rx = !!val->value.i;
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
mutex_lock(&priv->reg_mutex);
priv->mirror_tx = !!val->value.i;
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
mutex_lock(&priv->reg_mutex);
priv->monitor_port = val->value.i;
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
mutex_lock(&priv->reg_mutex);
priv->source_port = val->value.i;
- ar8xxx_set_mirror_regs(priv);
+ priv->chip->set_mirror_regs(priv);
mutex_unlock(&priv->reg_mutex);
return 0;
},
.get_port_pvid = ar8xxx_sw_get_pvid,
.set_port_pvid = ar8xxx_sw_set_pvid,
- .get_vlan_ports = ar8216_sw_get_ports,
- .set_vlan_ports = ar8216_sw_set_ports,
+ .get_vlan_ports = ar8xxx_sw_get_ports,
+ .set_vlan_ports = ar8xxx_sw_set_ports,
.apply_config = ar8xxx_sw_hw_apply,
.reset_switch = ar8xxx_sw_reset_switch,
.get_port_link = ar8xxx_sw_get_port_link,
priv->chip = &ar8316_chip;
break;
case AR8XXX_VER_AR8327:
- priv->mii_lo_first = true;
priv->chip = &ar8327_chip;
break;
case AR8XXX_VER_AR8337:
- priv->mii_lo_first = true;
priv->chip = &ar8327_chip;
break;
default:
if (priv->chip && priv->chip->cleanup)
priv->chip->cleanup(priv);
+ kfree(priv->chip_data);
kfree(priv->mib_stats);
kfree(priv);
}
if (WARN_ON(!priv))
return -ENODEV;
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
- return 0;
+ if (priv->chip->config_at_probe)
+ return ar8xxx_phy_check_aneg(phydev);
priv->phy = phydev;
0x004dd036, /* AR8337 */
0x004dd041,
0x004dd042,
+ 0x004dd043, /* AR8236 */
};
static bool
phydev->advertising = ADVERTISED_100baseT_Full;
}
- if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
+ if (priv->chip->config_at_probe) {
priv->phy = phydev;
ret = ar8xxx_start(priv);
ar8xxx_free(priv);
}
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
+static int
+ar8xxx_phy_soft_reset(struct phy_device *phydev)
+{
+ /* we don't need an extra reset */
+ return 0;
+}
+#endif
+
static struct phy_driver ar8xxx_phy_driver = {
.phy_id = 0x004d0000,
.name = "Atheros AR8216/AR8236/AR8316",
.config_init = ar8xxx_phy_config_init,
.config_aneg = ar8xxx_phy_config_aneg,
.read_status = ar8xxx_phy_read_status,
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
+ .soft_reset = ar8xxx_phy_soft_reset,
+#endif
.driver = { .owner = THIS_MODULE },
};
projects / openwrt / staging / chunkeey.git / blobdiff