mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
MV_VTUOP_INPROGRESS, 0);
sw16(dev, MV_GLOBALREG(VTU_OP),
- MV_VTUOP_INPROGRESS | MV_VTUOP_VALID);
+ MV_VTUOP_INPROGRESS | MV_VTUOP_PURGE);
/* Write VLAN table */
for (i = 1; i < dev->vlans; i++) {
MV_VTUOP_INPROGRESS, 0);
sw16(dev, MV_GLOBALREG(VTU_VID),
- MV_VTUOP_VALID | state->vlans[i].vid);
+ MV_VTU_VID_VALID | state->vlans[i].vid);
v1 = (u16)(state->vlans[i].port_mode & 0xffff);
v2 = (u16)((state->vlans[i].port_mode >> 16) & 0xffff);
/* Disable all ports before reset */
for (i = 0; i < dev->ports; i++) {
reg = sr16(dev, MV_PORTREG(CONTROL, i)) &
- ~MV_PORTCTRL_ENABLED;
+ ~MV_PORTCTRL_FORWARDING;
sw16(dev, MV_PORTREG(CONTROL, i), reg);
}
state->ports[i].pvid = 0;
/* Force flow control off */
- reg = sr16(dev, MV_PORTREG(FORCE, i)) & ~MV_FORCE_FC_MASK;
- reg |= MV_FORCE_FC_DISABLE;
- sw16(dev, MV_PORTREG(FORCE, i), reg);
+ reg = sr16(dev, MV_PORTREG(PHYCTL, i)) & ~MV_PHYCTL_FC_MASK;
+ reg |= MV_PHYCTL_FC_DISABLE;
+ sw16(dev, MV_PORTREG(PHYCTL, i), reg);
/* Set port association vector */
sw16(dev, MV_PORTREG(ASSOC, i), (1 << i));
/* Re-enable ports */
for (i = 0; i < dev->ports; i++) {
reg = sr16(dev, MV_PORTREG(CONTROL, i)) |
- MV_PORTCTRL_ENABLED;
+ MV_PORTCTRL_FORWARDING;
sw16(dev, MV_PORTREG(CONTROL, i), reg);
}