ipq806x: fix PCIe reset gpio handling - the core already handles the active-low flag

[openwrt/staging/chunkeey.git] / target / linux / ipq806x / patches-3.18 / 114-pcie-add-ctlr-init.patch

diff --git a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch
index 11c9810fe276c914a7c058152e34d4e415ff25b6..c00abca75377d7cb29cd8ec6416affe5bb748234 100644 (file)
--- a/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch
+++ b/target/linux/ipq806x/patches-3.18/114-pcie-add-ctlr-init.patch
@@ -83,7 +83,29 @@
  };
  
  struct qcom_pcie_resources_v1 {
-@@ -156,10 +202,13 @@ static void qcom_pcie_disable_resources_
+@@ -106,20 +152,10 @@ writel_masked(void __iomem *addr, u32 cl
+ 
+ static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert)
+ {
+-      int val, active_low;
+-
+       if (IS_ERR_OR_NULL(pcie->reset))
+               return;
+ 
+-      active_low = gpiod_is_active_low(pcie->reset);
+-
+-      if (assert)
+-              val = !!active_low;
+-      else
+-              val = !active_low;
+-
+-      gpiod_set_value(pcie->reset, val);
+-
++      gpiod_set_value(pcie->reset, assert);
+       usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US);
+ }
+ 
+@@ -156,10 +192,13 @@ static void qcom_pcie_disable_resources_
        reset_control_assert(res->axi_reset);
        reset_control_assert(res->ahb_reset);
        reset_control_assert(res->por_reset);
@@ -98,7 +120,7 @@
        regulator_disable(res->vdda);
        regulator_disable(res->vdda_phy);
        regulator_disable(res->vdda_refclk);
-@@ -201,6 +250,12 @@ static int qcom_pcie_enable_resources_v0
+@@ -201,6 +240,12 @@ static int qcom_pcie_enable_resources_v0
                goto err_vdda_phy;
        }
  
@@ -111,7 +133,7 @@
        ret = clk_prepare_enable(res->iface_clk);
        if (ret) {
                dev_err(dev, "cannot prepare/enable iface clock\n");
-@@ -219,6 +274,18 @@ static int qcom_pcie_enable_resources_v0
+@@ -219,21 +264,40 @@ static int qcom_pcie_enable_resources_v0
                goto err_clk_phy;
        }
  
@@ -130,7 +152,10 @@
        ret = reset_control_deassert(res->ahb_reset);
        if (ret) {
                dev_err(dev, "cannot deassert ahb reset\n");
-@@ -228,12 +295,18 @@ static int qcom_pcie_enable_resources_v0
+               goto err_reset_ahb;
+       }
++      udelay(1);
+ 
        return 0;
  
  err_reset_ahb:
@@ -149,7 +174,7 @@
        regulator_disable(res->vdda_phy);
  err_vdda_phy:
        regulator_disable(res->vdda_refclk);
-@@ -329,6 +402,14 @@ static int qcom_pcie_get_resources_v0(st
+@@ -329,6 +393,14 @@ static int qcom_pcie_get_resources_v0(st
        if (IS_ERR(res->phy_clk))
                return PTR_ERR(res->phy_clk);
  
@@ -164,7 +189,7 @@
        res->pci_reset = devm_reset_control_get(dev, "pci");
        if (IS_ERR(res->pci_reset))
                return PTR_ERR(res->pci_reset);
-@@ -349,6 +430,14 @@ static int qcom_pcie_get_resources_v0(st
+@@ -349,6 +421,14 @@ static int qcom_pcie_get_resources_v0(st
        if (IS_ERR(res->phy_reset))
                return PTR_ERR(res->phy_reset);
  
@@ -179,7 +204,7 @@
        return 0;
  }
  
-@@ -461,6 +550,57 @@ err_res:
+@@ -461,6 +541,57 @@ err_res:
        qcom_pcie_disable_resources_v1(pcie);
  }
  
@@ -229,15 +254,23 @@
 +      writel(upper_32_bits(pp->mem_bus_addr),
 +             pcie->dbi + PCIE20_PLR_IATU_UTAR);
 +
-+      /* 1K PCIE buffer setting */
-+      writel(0x3, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
++      /* 256B PCIE buffer setting */
++      writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
 +      writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
 +}
 +
  static void qcom_pcie_host_init_v0(struct pcie_port *pp)
  {
        struct qcom_pcie *pcie = to_qcom_pcie(pp);
-@@ -476,9 +616,26 @@ static void qcom_pcie_host_init_v0(struc
+@@ -470,15 +601,34 @@ static void qcom_pcie_host_init_v0(struc
+ 
+       qcom_ep_reset_assert(pcie);
+ 
++      reset_control_assert(res->ahb_reset);
++
+       ret = qcom_pcie_enable_resources_v0(pcie);
+       if (ret)
+               return;
  
        writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
  
@@ -266,7 +299,7 @@
        ret = reset_control_deassert(res->phy_reset);
        if (ret) {
                dev_err(dev, "cannot deassert phy reset\n");
-@@ -517,6 +674,9 @@ static void qcom_pcie_host_init_v0(struc
+@@ -517,6 +667,9 @@ static void qcom_pcie_host_init_v0(struc
        if (ret)
                goto err;