ramips: make ethernet register map u16 instead of u32

[openwrt/staging/chunkeey.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / soc_mt7620.c

diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
index 5a7ee35eb0379ae7f227eca2aa613e835e192f51..a18c1c9a5451b6a32aaef0539389629581f268c5 100644 (file)
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c
@@ -27,7 +27,8 @@
 
 #define MT7620A_CDMA_CSG_CFG   0x400
 #define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
-#define MT7621_DMA_VID         0xa8
+#define MT7621_CDMP_IG_CTRL    (MT7620A_CDMA_CSG_CFG + 0x00)
+#define MT7621_CDMP_EG_CTRL    (MT7620A_CDMA_CSG_CFG + 0x04)
 #define MT7620A_RESET_FE       BIT(21)
 #define MT7621_RESET_FE                BIT(6)
 #define MT7620A_RESET_ESW      BIT(23)
@@ -61,8 +62,17 @@
 #define GSW_REG_GDMA1_MAC_ADRH 0x50C
 
 #define MT7621_FE_RST_GL       (FE_FE_OFFSET + 0x04)
+#define MT7620_FE_INT_STATUS2  (FE_FE_OFFSET + 0x08)
 
-static const u32 mt7620_reg_table[FE_REG_COUNT] = {
+/*
+ * FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
+ * but after test it should be BIT(13).
+ */
+#define MT7620_FE_GDM1_AF      BIT(13)
+#define MT7621_FE_GDM1_AF      BIT(28)
+#define MT7621_FE_GDM2_AF      BIT(29)
+
+static const u16 mt7620_reg_table[FE_REG_COUNT] = {
        [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
        [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
        [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
@@ -79,9 +89,10 @@ static const u32 mt7620_reg_table[FE_REG_COUNT] = {
        [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
        [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
        [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
+       [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
 };
 
-static const u32 mt7621_reg_table[FE_REG_COUNT] = {
+static const u16 mt7621_reg_table[FE_REG_COUNT] = {
        [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
        [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
        [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
@@ -95,9 +106,10 @@ static const u32 mt7621_reg_table[FE_REG_COUNT] = {
        [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
        [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
        [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
-       [FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
+       [FE_REG_FE_DMA_VID_BASE] = 0,
        [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
        [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
+       [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
 };
 
 static void mt7620_fe_reset(void)
@@ -134,6 +146,14 @@ static void mt7620_txcsum_config(bool enable)
                                MT7620A_CDMA_CSG_CFG);
 }
 
+static void mt7621_rxvlan_config(bool enable)
+{
+       if (enable)
+               fe_w32(1, MT7621_CDMP_EG_CTRL);
+       else
+               fe_w32(0, MT7621_CDMP_EG_CTRL);
+}
+
 static int mt7620_fwd_config(struct fe_priv *priv)
 {
        struct net_device *dev = priv_netdev(priv);
@@ -152,15 +172,16 @@ static int mt7621_fwd_config(struct fe_priv *priv)
 
        fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
 
-       mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
+       /* mt7621 don't have txcsum config */
        mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
+       mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
+                       (priv->flags & FE_FLAG_RX_VLAN_CTAG));
 
        return 0;
 }
 
 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 {
-       txd->txd4 = 0;
 }
 
 static void mt7621_tx_dma(struct fe_tx_dma *txd)
@@ -175,10 +196,10 @@ static void mt7620_init_data(struct fe_soc_data *data,
 
        priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
                FE_FLAG_RX_SG_DMA;
+
        netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
                NETIF_F_HW_VLAN_CTAG_TX;
-
-       if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621))
+       if (mt7620_get_eco() >= 5)
                netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
                        NETIF_F_IPV6_CSUM;
 }
@@ -189,8 +210,11 @@ static void mt7621_init_data(struct fe_soc_data *data,
        struct fe_priv *priv = netdev_priv(netdev);
 
        priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
-               FE_FLAG_RX_SG_DMA;
-       netdev->hw_features = NETIF_F_HW_VLAN_CTAG_TX;
+               FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT;
+
+       netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
+               NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
+               NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
 }
 
 static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
@@ -205,7 +229,6 @@ static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
 }
 
 static struct fe_soc_data mt7620_data = {
-       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
        .init_data = mt7620_init_data,
        .reset_fe = mt7620_fe_reset,
        .set_mac = mt7620_set_mac,
@@ -218,8 +241,8 @@ static struct fe_soc_data mt7620_data = {
        .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
        .rx_int = RT5350_RX_DONE_INT,
        .tx_int = RT5350_TX_DONE_INT,
+       .status_int = MT7620_FE_GDM1_AF,
        .checksum_bit = MT7620_L4_VALID,
-       .tx_udf_bit = MT7620_TX_DMA_UDF,
        .has_carrier = mt7620a_has_carrier,
        .mdio_read = mt7620_mdio_read,
        .mdio_write = mt7620_mdio_write,
@@ -227,7 +250,6 @@ static struct fe_soc_data mt7620_data = {
 };
 
 static struct fe_soc_data mt7621_data = {
-       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
        .init_data = mt7621_init_data,
        .reset_fe = mt7621_fe_reset,
        .set_mac = mt7621_set_mac,
@@ -239,8 +261,8 @@ static struct fe_soc_data mt7621_data = {
        .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
        .rx_int = RT5350_RX_DONE_INT,
        .tx_int = RT5350_TX_DONE_INT,
+       .status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF),
        .checksum_bit = MT7621_L4_VALID,
-       .tx_udf_bit = MT7621_TX_DMA_UDF,
        .has_carrier = mt7620a_has_carrier,
        .mdio_read = mt7620_mdio_read,
        .mdio_write = mt7620_mdio_write,