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(parent: b7933a4) | patch
ar71xx: fix ar724x clock calculation
authorFelix Fietkau <nbd@openwrt.org>
Fri, 11 Sep 2015 16:32:45 +0000 (16:32 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Fri, 11 Sep 2015 16:32:45 +0000 (16:32 +0000)
commitbc4f2c5ce4fa70444f5f59a23852fc81e4c092bb
tree166747c55981286ad33fd105d3962c5933f6c199tree | snapshot
parentb7933a47bb8ef485fe503425a817780905372068commit | diff
ar71xx: fix ar724x clock calculation

According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
input clock as the REF_CLK instead of 5MHz.

The correct CPU PLL calculation procedure is as follows:
CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2.

This patch is compatible with the current calculation procedure with default
DIV and REF_DIV values.

Test on both AR7240, AR7241 and AR7242.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
SVN-Revision: 46856
target/linux/ar71xx/patches-4.1/634-MIPS-ath79-ar724x-clock-calculation-fixes.patch [new file with mode: 0644] blob
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