ar71xx: ethernet: reduce tx and rx DMA ring size to improve cache footprint

256 entries is a bit excessive, even for gigabit speeds

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 37762

diff --git a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
index 6d51e722b0cd7a0b97a65557d36cade994c6fc61..83607b38bf01e74790e46a8a52edc80cb76b398c 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
@@ -58,8 +58,8 @@
 #define AG71XX_TX_RING_SIZE_DEFAULT    64
 #define AG71XX_RX_RING_SIZE_DEFAULT    128
 
-#define AG71XX_TX_RING_SIZE_MAX                256
-#define AG71XX_RX_RING_SIZE_MAX                256
+#define AG71XX_TX_RING_SIZE_MAX                128
+#define AG71XX_RX_RING_SIZE_MAX                128
 
 #ifdef CONFIG_AG71XX_DEBUG
 #define DBG(fmt, args...)      pr_debug(fmt, ## args)