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[openwrt/staging/dedeckeh.git] / openwrt / target / linux / brcm-2.4 / patches / 001-bcm47xx.patch
1 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
2 --- linux.old/arch/mips/Makefile 2006-04-27 18:04:37.000000000 +0200
3 +++ linux.dev/arch/mips/Makefile 2006-04-27 19:24:19.000000000 +0200
4 @@ -726,6 +726,19 @@
5 endif
6
7 #
8 +# Broadcom BCM947XX variants
9 +#
10 +ifdef CONFIG_BCM947XX
11 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
12 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
13 +LOADADDR := 0x80001000
14 +
15 +zImage: vmlinux
16 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
17 +export LOADADDR
18 +endif
19 +
20 +#
21 # Choosing incompatible machines durings configuration will result in
22 # error messages during linking. Select a default linkscript if
23 # none has been choosen above.
24 @@ -778,6 +791,7 @@
25 $(MAKE) -C arch/$(ARCH)/tools clean
26 $(MAKE) -C arch/mips/baget clean
27 $(MAKE) -C arch/mips/lasat clean
28 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
29
30 archmrproper:
31 @$(MAKEBOOT) mrproper
32 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
33 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
34 +++ linux.dev/arch/mips/bcm947xx/Makefile 2006-05-02 17:46:22.000000000 +0200
35 @@ -0,0 +1,17 @@
36 +#
37 +# Makefile for the BCM947xx specific kernel interface routines
38 +# under Linux.
39 +#
40 +
41 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
42 +
43 +O_TARGET := bcm947xx.o
44 +
45 +export-objs := export.o
46 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
47 +obj-y += nvram.o nvram_linux.o sflash.o cfe_env.o
48 +obj-y += sbutils.o bcmutils.o bcmsrom.o hndchipc.o
49 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
50 +obj-y += export.o
51 +
52 +include $(TOPDIR)/Rules.make
53 diff -urN linux.old/arch/mips/bcm947xx/bcmsrom.c linux.dev/arch/mips/bcm947xx/bcmsrom.c
54 --- linux.old/arch/mips/bcm947xx/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
55 +++ linux.dev/arch/mips/bcm947xx/bcmsrom.c 2006-04-27 20:32:48.000000000 +0200
56 @@ -0,0 +1,1212 @@
57 +/*
58 + * Misc useful routines to access NIC SROM/OTP .
59 + *
60 + * Copyright 2006, Broadcom Corporation
61 + * All Rights Reserved.
62 + *
63 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
64 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
65 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
66 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
67 + * $Id: bcmsrom.c,v 1.1.1.14 2006/04/15 01:28:25 michael Exp $
68 + */
69 +
70 +#include <typedefs.h>
71 +#include <bcmdefs.h>
72 +#include <osl.h>
73 +#include <bcmutils.h>
74 +#include <bcmsrom.h>
75 +#include <bcmdevs.h>
76 +#include <bcmendian.h>
77 +#include <sbpcmcia.h>
78 +#include <pcicfg.h>
79 +#include <sbutils.h>
80 +#include <bcmnvram.h>
81 +
82 +/* debug/trace */
83 +#if defined(WLTEST)
84 +#define BS_ERROR(args) printf args
85 +#else
86 +#define BS_ERROR(args)
87 +#endif /* BCMDBG_ERR || WLTEST */
88 +
89 +#define VARS_MAX 4096 /* should be reduced */
90 +
91 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
92 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
93 +
94 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count);
95 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count);
96 +static int initvars_flash_sb(void *sbh, char **vars, uint *count);
97 +static int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count);
98 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
99 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
100 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
101 +static int sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords,
102 + bool check_crc);
103 +
104 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
105 +static int initvars_flash(osl_t *osh, char **vp, uint len, char *devpath);
106 +
107 +/*
108 + * Initialize local vars from the right source for this platform.
109 + * Return 0 on success, nonzero on error.
110 + */
111 +int
112 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, uint *count)
113 +{
114 + ASSERT(bustype == BUSTYPE(bustype));
115 + if (vars == NULL || count == NULL)
116 + return (0);
117 +
118 + switch (BUSTYPE(bustype)) {
119 + case SB_BUS:
120 + case JTAG_BUS:
121 + return initvars_flash_sb(sbh, vars, count);
122 +
123 + case PCI_BUS:
124 + ASSERT(curmap); /* can not be NULL */
125 + return initvars_srom_pci(sbh, curmap, vars, count);
126 +
127 + case PCMCIA_BUS:
128 + return initvars_cis_pcmcia(sbh, osh, vars, count);
129 +
130 +
131 + default:
132 + ASSERT(0);
133 + }
134 + return (-1);
135 +}
136 +
137 +/* support only 16-bit word read from srom */
138 +int
139 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
140 +{
141 + void *srom;
142 + uint i, off, nw;
143 +
144 + ASSERT(bustype == BUSTYPE(bustype));
145 +
146 + /* check input - 16-bit access only */
147 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
148 + return 1;
149 +
150 + off = byteoff / 2;
151 + nw = nbytes / 2;
152 +
153 + if (BUSTYPE(bustype) == PCI_BUS) {
154 + if (!curmap)
155 + return 1;
156 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
157 + if (sprom_read_pci(osh, srom, off, buf, nw, FALSE))
158 + return 1;
159 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
160 + for (i = 0; i < nw; i++) {
161 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
162 + return 1;
163 + }
164 + } else {
165 + return 1;
166 + }
167 +
168 + return 0;
169 +}
170 +
171 +/* support only 16-bit word write into srom */
172 +int
173 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
174 +{
175 + uint16 *srom;
176 + uint i, nw, crc_range;
177 + uint16 image[SPROM_SIZE];
178 + uint8 crc;
179 + volatile uint32 val32;
180 +
181 + ASSERT(bustype == BUSTYPE(bustype));
182 +
183 + /* check input - 16-bit access only */
184 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
185 + return 1;
186 +
187 + /* Are we writing the whole thing at once? */
188 + if ((byteoff == 0) &&
189 + ((nbytes == SPROM_SIZE) ||
190 + (nbytes == (SPROM_CRC_RANGE * 2)) ||
191 + (nbytes == (SROM4_WORDS * 2)))) {
192 + crc_range = nbytes;
193 + bcopy((void*)buf, (void*)image, nbytes);
194 + nw = nbytes / 2;
195 + } else {
196 + if ((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS))
197 + crc_range = SPROM_SIZE;
198 + else
199 + crc_range = SPROM_CRC_RANGE * 2; /* Tentative */
200 +
201 + nw = crc_range / 2;
202 + /* read first 64 words from srom */
203 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
204 + return 1;
205 + if (image[SROM4_SIGN] == SROM4_SIGNATURE) {
206 + crc_range = SROM4_WORDS;
207 + nw = crc_range / 2;
208 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
209 + return 1;
210 + }
211 + /* make changes */
212 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
213 + }
214 +
215 + /* calculate crc */
216 + htol16_buf(image, crc_range);
217 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
218 + ltoh16_buf(image, crc_range);
219 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
220 +
221 + if (BUSTYPE(bustype) == PCI_BUS) {
222 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
223 + /* enable writes to the SPROM */
224 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
225 + val32 |= SPROM_WRITEEN;
226 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
227 + bcm_mdelay(WRITE_ENABLE_DELAY);
228 + /* write srom */
229 + for (i = 0; i < nw; i++) {
230 + W_REG(osh, &srom[i], image[i]);
231 + bcm_mdelay(WRITE_WORD_DELAY);
232 + }
233 + /* disable writes to the SPROM */
234 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 &
235 + ~SPROM_WRITEEN);
236 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
237 + /* enable writes to the SPROM */
238 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
239 + return 1;
240 + bcm_mdelay(WRITE_ENABLE_DELAY);
241 + /* write srom */
242 + for (i = 0; i < nw; i++) {
243 + sprom_write_pcmcia(osh, (uint16)(i), image[i]);
244 + bcm_mdelay(WRITE_WORD_DELAY);
245 + }
246 + /* disable writes to the SPROM */
247 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
248 + return 1;
249 + } else {
250 + return 1;
251 + }
252 +
253 + bcm_mdelay(WRITE_ENABLE_DELAY);
254 + return 0;
255 +}
256 +
257 +
258 +static int
259 +srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt, char **vars, uint *count)
260 +{
261 + char eabuf[32];
262 + char *vp, *base;
263 + uint8 *cis, tup, tlen, sromrev = 1;
264 + int i, j;
265 + uint varsize;
266 + bool ag_init = FALSE;
267 + uint32 w32;
268 +
269 + ASSERT(vars);
270 + ASSERT(count);
271 +
272 + base = vp = MALLOC(osh, VARS_MAX);
273 + ASSERT(vp);
274 + if (!vp)
275 + return -2;
276 +
277 + while (ciscnt--) {
278 + cis = *pcis++;
279 + i = 0;
280 + do {
281 + tup = cis[i++];
282 + tlen = cis[i++];
283 + if ((i + tlen) >= CIS_SIZE)
284 + break;
285 +
286 + switch (tup) {
287 + case CISTPL_MANFID:
288 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
289 + vp++;
290 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
291 + vp++;
292 + break;
293 +
294 + case CISTPL_FUNCE:
295 + switch (cis[i]) {
296 + case LAN_NID:
297 + ASSERT(cis[i + 1] == 6);
298 + bcm_ether_ntoa((struct ether_addr *)&cis[i + 2], eabuf);
299 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
300 + vp++;
301 + break;
302 + case 1: /* SDIO Extended Data */
303 + vp += sprintf(vp, "sdmaxblk=%d",
304 + (cis[i + 13] << 8) | cis[i + 12]);
305 + vp++;
306 + break;
307 + }
308 + break;
309 +
310 + case CISTPL_CFTABLE:
311 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
312 + vp++;
313 + break;
314 +
315 + case CISTPL_BRCM_HNBU:
316 + switch (cis[i]) {
317 + case HNBU_SROMREV:
318 + sromrev = cis[i + 1];
319 + break;
320 +
321 + case HNBU_CHIPID:
322 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) +
323 + cis[i + 1]);
324 + vp++;
325 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) +
326 + cis[i + 3]);
327 + vp++;
328 + if (tlen == 7) {
329 + vp += sprintf(vp, "chiprev=%d",
330 + (cis[i + 6] << 8) + cis[i + 5]);
331 + vp++;
332 + }
333 + break;
334 +
335 + case HNBU_BOARDREV:
336 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
337 + vp++;
338 + break;
339 +
340 + case HNBU_AA:
341 + vp += sprintf(vp, "aa2g=%d", cis[i + 1]);
342 + vp++;
343 + break;
344 +
345 + case HNBU_AG:
346 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
347 + vp++;
348 + ag_init = TRUE;
349 + break;
350 +
351 + case HNBU_CC:
352 + ASSERT(sromrev == 1);
353 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
354 + vp++;
355 + break;
356 +
357 + case HNBU_PAPARMS:
358 + if (tlen == 2) {
359 + ASSERT(sromrev == 1);
360 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
361 + vp++;
362 + } else if (tlen >= 9) {
363 + if (tlen == 10) {
364 + ASSERT(sromrev == 2);
365 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
366 + vp++;
367 + } else
368 + ASSERT(tlen == 9);
369 +
370 + for (j = 0; j < 3; j++) {
371 + vp += sprintf(vp, "pa0b%d=%d", j,
372 + (cis[i + (j * 2) + 2] << 8) +
373 + cis[i + (j * 2) + 1]);
374 + vp++;
375 + }
376 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
377 + vp++;
378 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
379 + vp++;
380 + } else
381 + ASSERT(tlen >= 9);
382 + break;
383 +
384 + case HNBU_OEM:
385 + ASSERT(sromrev == 1);
386 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
387 + cis[i + 1], cis[i + 2],
388 + cis[i + 3], cis[i + 4],
389 + cis[i + 5], cis[i + 6],
390 + cis[i + 7], cis[i + 8]);
391 + vp++;
392 + break;
393 +
394 + case HNBU_BOARDFLAGS:
395 + w32 = (cis[i + 2] << 8) + cis[i + 1];
396 + if (tlen == 5)
397 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
398 + vp += sprintf(vp, "boardflags=0x%x", w32);
399 + vp++;
400 + break;
401 +
402 + case HNBU_LEDS:
403 + if (cis[i + 1] != 0xff) {
404 + vp += sprintf(vp, "ledbh0=%d", cis[i + 1]);
405 + vp++;
406 + }
407 + if (cis[i + 2] != 0xff) {
408 + vp += sprintf(vp, "ledbh1=%d", cis[i + 2]);
409 + vp++;
410 + }
411 + if (cis[i + 3] != 0xff) {
412 + vp += sprintf(vp, "ledbh2=%d", cis[i + 3]);
413 + vp++;
414 + }
415 + if (cis[i + 4] != 0xff) {
416 + vp += sprintf(vp, "ledbh3=%d", cis[i + 4]);
417 + vp++;
418 + }
419 + break;
420 +
421 + case HNBU_CCODE:
422 + {
423 + char str[3];
424 + ASSERT(sromrev > 1);
425 + str[0] = cis[i + 1];
426 + str[1] = cis[i + 2];
427 + str[2] = 0;
428 + vp += sprintf(vp, "ccode=%s", str);
429 + vp++;
430 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
431 + vp++;
432 + break;
433 + }
434 +
435 + case HNBU_CCKPO:
436 + ASSERT(sromrev > 2);
437 + vp += sprintf(vp, "cckpo=0x%x",
438 + (cis[i + 2] << 8) | cis[i + 1]);
439 + vp++;
440 + break;
441 +
442 + case HNBU_OFDMPO:
443 + ASSERT(sromrev > 2);
444 + vp += sprintf(vp, "ofdmpo=0x%x",
445 + (cis[i + 4] << 24) |
446 + (cis[i + 3] << 16) |
447 + (cis[i + 2] << 8) |
448 + cis[i + 1]);
449 + vp++;
450 + break;
451 + }
452 + break;
453 +
454 + }
455 + i += tlen;
456 + } while (tup != 0xff);
457 + }
458 +
459 + /* Set the srom version */
460 + vp += sprintf(vp, "sromrev=%d", sromrev);
461 + vp++;
462 +
463 + /* if there is no antenna gain field, set default */
464 + if (ag_init == FALSE) {
465 + ASSERT(sromrev == 1);
466 + vp += sprintf(vp, "ag0=%d", 0xff);
467 + vp++;
468 + }
469 +
470 + /* final nullbyte terminator */
471 + *vp++ = '\0';
472 + varsize = (uint)(vp - base);
473 +
474 + ASSERT((vp - base) < VARS_MAX);
475 +
476 + if (varsize == VARS_MAX) {
477 + *vars = base;
478 + } else {
479 + vp = MALLOC(osh, varsize);
480 + ASSERT(vp);
481 + if (vp)
482 + bcopy(base, vp, varsize);
483 + MFREE(osh, base, VARS_MAX);
484 + *vars = vp;
485 + if (!vp) {
486 + *count = 0;
487 + return -2;
488 + }
489 + }
490 + *count = varsize;
491 +
492 + return (0);
493 +}
494 +
495 +
496 +/* set PCMCIA sprom command register */
497 +static int
498 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
499 +{
500 + uint8 status = 0;
501 + uint wait_cnt = 1000;
502 +
503 + /* write sprom command register */
504 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
505 +
506 + /* wait status */
507 + while (wait_cnt--) {
508 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
509 + if (status & SROM_DONE)
510 + return 0;
511 + }
512 +
513 + return 1;
514 +}
515 +
516 +/* read a word from the PCMCIA srom */
517 +static int
518 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
519 +{
520 + uint8 addr_l, addr_h, data_l, data_h;
521 +
522 + addr_l = (uint8)((addr * 2) & 0xff);
523 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
524 +
525 + /* set address */
526 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
527 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
528 +
529 + /* do read */
530 + if (sprom_cmd_pcmcia(osh, SROM_READ))
531 + return 1;
532 +
533 + /* read data */
534 + data_h = data_l = 0;
535 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
536 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
537 +
538 + *data = (data_h << 8) | data_l;
539 + return 0;
540 +}
541 +
542 +/* write a word to the PCMCIA srom */
543 +static int
544 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
545 +{
546 + uint8 addr_l, addr_h, data_l, data_h;
547 +
548 + addr_l = (uint8)((addr * 2) & 0xff);
549 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
550 + data_l = (uint8)(data & 0xff);
551 + data_h = (uint8)((data >> 8) & 0xff);
552 +
553 + /* set address */
554 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
555 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
556 +
557 + /* write data */
558 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
559 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
560 +
561 + /* do write */
562 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
563 +}
564 +
565 +/*
566 + * Read in and validate sprom.
567 + * Return 0 on success, nonzero on error.
568 + */
569 +static int
570 +sprom_read_pci(osl_t *osh, uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
571 +{
572 + int err = 0;
573 + uint i;
574 +
575 + /* read the sprom */
576 + for (i = 0; i < nwords; i++)
577 + buf[i] = R_REG(osh, &sprom[wordoff + i]);
578 +
579 + if (check_crc) {
580 + /* fixup the endianness so crc8 will pass */
581 + htol16_buf(buf, nwords * 2);
582 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
583 + err = 1;
584 + /* now correct the endianness of the byte array */
585 + ltoh16_buf(buf, nwords * 2);
586 + }
587 +
588 + return err;
589 +}
590 +
591 +/*
592 +* Create variable table from memory.
593 +* Return 0 on success, nonzero on error.
594 +*/
595 +static int
596 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
597 +{
598 + int c = (int)(end - start);
599 +
600 + /* do it only when there is more than just the null string */
601 + if (c > 1) {
602 + char *vp = MALLOC(osh, c);
603 + ASSERT(vp);
604 + if (!vp)
605 + return BCME_NOMEM;
606 + bcopy(start, vp, c);
607 + *vars = vp;
608 + *count = c;
609 + }
610 + else {
611 + *vars = NULL;
612 + *count = 0;
613 + }
614 +
615 + return 0;
616 +}
617 +
618 +/*
619 + * Find variables with <devpath> from flash. 'base' points to the beginning
620 + * of the table upon enter and to the end of the table upon exit when success.
621 + * Return 0 on success, nonzero on error.
622 + */
623 +static int
624 +initvars_flash(osl_t *osh, char **base, uint len, char *devpath)
625 +{
626 + char *vp = *base;
627 + char *flash;
628 + int err;
629 + char *s;
630 + uint l, dl, copy_len;
631 +
632 + /* allocate memory and read in flash */
633 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
634 + return BCME_NOMEM;
635 + if ((err = nvram_getall(flash, NVRAM_SPACE)))
636 + goto exit;
637 +
638 + /* grab vars with the <devpath> prefix in name */
639 + dl = strlen(devpath);
640 + for (s = flash; s && *s; s += l + 1) {
641 + l = strlen(s);
642 +
643 + /* skip non-matching variable */
644 + if (strncmp(s, devpath, dl))
645 + continue;
646 +
647 + /* is there enough room to copy? */
648 + copy_len = l - dl + 1;
649 + if (len < copy_len) {
650 + err = BCME_BUFTOOSHORT;
651 + goto exit;
652 + }
653 +
654 + /* no prefix, just the name=value */
655 + strcpy(vp, &s[dl]);
656 + vp += copy_len;
657 + len -= copy_len;
658 + }
659 +
660 + /* add null string as terminator */
661 + if (len < 1) {
662 + err = BCME_BUFTOOSHORT;
663 + goto exit;
664 + }
665 + *vp++ = '\0';
666 +
667 + *base = vp;
668 +
669 +exit: MFREE(osh, flash, NVRAM_SPACE);
670 + return err;
671 +}
672 +
673 +/*
674 + * Initialize nonvolatile variable table from flash.
675 + * Return 0 on success, nonzero on error.
676 + */
677 +static int
678 +initvars_flash_sb(void *sbh, char **vars, uint *count)
679 +{
680 + osl_t *osh = sb_osh(sbh);
681 + char devpath[SB_DEVPATH_BUFSZ];
682 + char *vp, *base;
683 + int err;
684 +
685 + ASSERT(vars);
686 + ASSERT(count);
687 +
688 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
689 + return err;
690 +
691 + base = vp = MALLOC(osh, VARS_MAX);
692 + ASSERT(vp);
693 + if (!vp)
694 + return BCME_NOMEM;
695 +
696 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
697 + goto err;
698 +
699 + err = initvars_table(osh, base, vp, vars, count);
700 +
701 +err: MFREE(osh, base, VARS_MAX);
702 + return err;
703 +}
704 +
705 +#ifdef WLTEST
706 +char mfgsromvars[256];
707 +char *defaultsromvars = "il0macaddr=00:11:22:33:44:51\0"
708 + "et0macaddr=00:11:22:33:44:52\0"
709 + "et1macaddr=00:11:22:33:44:53\0"
710 + "boardtype=0xffff\0"
711 + "boardrev=0x10\0"
712 + "boardflags=8\0"
713 + "sromrev=2\0"
714 + "aa2g=3";
715 +#define MFGSROM_DEFVARSLEN 147 /* default srom len */
716 +#endif /* WL_TEST */
717 +
718 +/*
719 + * Initialize nonvolatile variable table from sprom.
720 + * Return 0 on success, nonzero on error.
721 + */
722 +static int
723 +initvars_srom_pci(void *sbh, void *curmap, char **vars, uint *count)
724 +{
725 + uint16 w, *b;
726 + uint8 sromrev = 0;
727 + struct ether_addr ea;
728 + char eabuf[32];
729 + uint32 w32;
730 + int woff, i;
731 + char *vp, *base;
732 + osl_t *osh = sb_osh(sbh);
733 + bool flash = FALSE;
734 + char name[SB_DEVPATH_BUFSZ+16], *value;
735 + char devpath[SB_DEVPATH_BUFSZ];
736 + int err;
737 +
738 + /*
739 + * Apply CRC over SROM content regardless SROM is present or not,
740 + * and use variable <devpath>sromrev's existance in flash to decide
741 + * if we should return an error when CRC fails or read SROM variables
742 + * from flash.
743 + */
744 + b = MALLOC(osh, SROM_MAX);
745 + ASSERT(b);
746 + if (!b)
747 + return -2;
748 +
749 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
750 + 64, TRUE);
751 + if (err == 0) {
752 + /* srom is good and is rev < 4 */
753 + /* top word of sprom contains version and crc8 */
754 + sromrev = b[63] & 0xff;
755 + /* bcm4401 sroms misprogrammed */
756 + if (sromrev == 0x10)
757 + sromrev = 1;
758 + } else if (b[SROM4_SIGN] == SROM4_SIGNATURE) {
759 + /* If sromrev >= 4, read more */
760 + err = sprom_read_pci(osh, (void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b,
761 + SROM4_WORDS, TRUE);
762 + sromrev = b[SROM4_WORDS - 1] & 0xff;
763 + }
764 +
765 + if (err) {
766 +#ifdef WLTEST
767 + BS_ERROR(("SROM Crc Error, so see if we could use a default\n"));
768 + w32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
769 + if (w32 & SPROM_OTPIN_USE) {
770 + BS_ERROR(("srom crc failed with OTP, use default vars....\n"));
771 + vp = base = mfgsromvars;
772 + if (sb_chip(sbh) == BCM4311_CHIP_ID) {
773 + BS_ERROR(("setting the devid to be 4311\n"));
774 + vp += sprintf(vp, "devid=0x4311");
775 + vp++;
776 + }
777 + bcopy(defaultsromvars, vp, MFGSROM_DEFVARSLEN);
778 + vp += MFGSROM_DEFVARSLEN;
779 + goto varsdone;
780 + } else {
781 + BS_ERROR(("srom crc failed with SPROM....\n"));
782 +#endif /* WLTEST */
783 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
784 + return err;
785 + sprintf(name, "%ssromrev", devpath);
786 + if (!(value = getvar(NULL, name)))
787 + return (-1);
788 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
789 + flash = TRUE;
790 +#ifdef WLTEST
791 + }
792 +#endif /* WLTEST */
793 + }
794 +
795 + /* srom version check */
796 + if (sromrev > 4)
797 + return (-2);
798 +
799 + ASSERT(vars);
800 + ASSERT(count);
801 +
802 + base = vp = MALLOC(osh, VARS_MAX);
803 + ASSERT(vp);
804 + if (!vp)
805 + return -2;
806 +
807 + /* read variables from flash */
808 + if (flash) {
809 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
810 + goto err;
811 + goto varsdone;
812 + }
813 +
814 + vp += sprintf(vp, "sromrev=%d", sromrev);
815 + vp++;
816 +
817 + if (sromrev >= 4) {
818 + uint path, pathbase;
819 + const uint pathbases[MAX_PATH] = {SROM4_PATH0, SROM4_PATH1,
820 + SROM4_PATH2, SROM4_PATH3};
821 +
822 + vp += sprintf(vp, "boardrev=%d", b[SROM4_BREV]);
823 + vp++;
824 +
825 + vp += sprintf(vp, "boardflags=%d", (b[SROM4_BFL1] << 16) | b[SROM4_BFL0]);
826 + vp++;
827 +
828 + vp += sprintf(vp, "boardflags2=%d", (b[SROM4_BFL3] << 16) | b[SROM4_BFL2]);
829 + vp++;
830 +
831 + /* The macaddr */
832 + ea.octet[0] = (b[SROM4_MACHI] >> 8) & 0xff;
833 + ea.octet[1] = b[SROM4_MACHI] & 0xff;
834 + ea.octet[2] = (b[SROM4_MACMID] >> 8) & 0xff;
835 + ea.octet[3] = b[SROM4_MACMID] & 0xff;
836 + ea.octet[4] = (b[SROM4_MACLO] >> 8) & 0xff;
837 + ea.octet[5] = b[SROM4_MACLO] & 0xff;
838 + bcm_ether_ntoa(&ea, eabuf);
839 + vp += sprintf(vp, "macaddr=%s", eabuf);
840 + vp++;
841 +
842 + w = b[SROM4_CCODE];
843 + if (w == 0)
844 + vp += sprintf(vp, "ccode=");
845 + else
846 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
847 + vp++;
848 + vp += sprintf(vp, "regrev=%d", b[SROM4_REGREV]);
849 + vp++;
850 +
851 + w = b[SROM4_LEDBH10];
852 + if ((w != 0) && (w != 0xffff)) {
853 + /* ledbh0 */
854 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
855 + vp++;
856 +
857 + /* ledbh1 */
858 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
859 + vp++;
860 + }
861 + w = b[SROM4_LEDBH32];
862 + if ((w != 0) && (w != 0xffff)) {
863 + /* ledbh2 */
864 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
865 + vp++;
866 +
867 + /* ledbh3 */
868 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
869 + vp++;
870 + }
871 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
872 + w = b[SROM4_LEDDC];
873 + w32 = ((uint32)((unsigned char)(w >> 8) & 0xff) << 24) | /* oncount */
874 + ((uint32)((unsigned char)(w & 0xff)) << 8); /* offcount */
875 + vp += sprintf(vp, "leddc=%d", w32);
876 + vp++;
877 +
878 + w = b[SROM4_AA];
879 + vp += sprintf(vp, "aa2g=%d", w & SROM4_AA2G_MASK);
880 + vp++;
881 + vp += sprintf(vp, "aa5g=%d", w >> SROM4_AA5G_SHIFT);
882 + vp++;
883 +
884 + w = b[SROM4_AG10];
885 + vp += sprintf(vp, "ag0=%d", w & 0xff);
886 + vp++;
887 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
888 + vp++;
889 + w = b[SROM4_AG32];
890 + vp += sprintf(vp, "ag2=%d", w & 0xff);
891 + vp++;
892 + vp += sprintf(vp, "ag3=%d", (w >> 8) & 0xff);
893 + vp++;
894 +
895 + /* Fixed power indices when power control is disabled */
896 + for (i = 0; i < 2; i++) {
897 + w = b[SROM4_TXPID2G + i];
898 + vp += sprintf(vp, "txpid2ga%d=%d", 2 * i, w & 0xff);
899 + vp++;
900 + vp += sprintf(vp, "txpid2ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
901 + vp++;
902 + w = b[SROM4_TXPID5G + i];
903 + vp += sprintf(vp, "txpid5ga%d=%d", 2 * i, w & 0xff);
904 + vp++;
905 + vp += sprintf(vp, "txpid5ga%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
906 + vp++;
907 + w = b[SROM4_TXPID5GL + i];
908 + vp += sprintf(vp, "txpid5gla%d=%d", 2 * i, w & 0xff);
909 + vp++;
910 + vp += sprintf(vp, "txpid5gla%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
911 + vp++;
912 + w = b[SROM4_TXPID5GH + i];
913 + vp += sprintf(vp, "txpid5gha%d=%d", 2 * i, w & 0xff);
914 + vp++;
915 + vp += sprintf(vp, "txpid5gha%d=%d", (2 * i) + 1, (w >> 8) & 0xff);
916 + vp++;
917 + }
918 +
919 + /* Per path variables */
920 + for (path = 0; path < MAX_PATH; path++) {
921 + pathbase = pathbases[path];
922 + w = b[pathbase + SROM4_2G_ITT_MAXP];
923 + vp += sprintf(vp, "itt2ga%d=%d", path, w >> B2G_ITT_SHIFT);
924 + vp++;
925 + vp += sprintf(vp, "maxp2ga%d=%d", path, w & B2G_MAXP_MASK);
926 + vp++;
927 +
928 + for (i = 0; i < 4; i++) {
929 + vp += sprintf(vp, "pa2gw%da%d=%d", i, path,
930 + b[pathbase + SROM4_2G_PA + i]);
931 + vp++;
932 + }
933 +
934 + w = b[pathbase + SROM4_5G_ITT_MAXP];
935 + vp += sprintf(vp, "itt5ga%d=%d", path, w >> B5G_ITT_SHIFT);
936 + vp++;
937 + vp += sprintf(vp, "maxp5ga%d=%d", path, w & B5G_MAXP_MASK);
938 + vp++;
939 +
940 + w = b[pathbase + SROM4_5GLH_MAXP];
941 + vp += sprintf(vp, "maxp5lga%d=%d", path, w >> B5GL_MAXP_SHIFT);
942 + vp++;
943 + vp += sprintf(vp, "maxp5gha%d=%d", path, w & B5GH_MAXP_MASK);
944 + vp++;
945 +
946 + for (i = 0; i < 4; i++) {
947 + vp += sprintf(vp, "pa5gw%da%d=%d", i, path,
948 + b[pathbase + SROM4_5G_PA + i]);
949 + vp++;
950 + vp += sprintf(vp, "pa5glw%da%d=%d", i, path,
951 + b[pathbase + SROM4_5GL_PA + i]);
952 + vp++;
953 + vp += sprintf(vp, "pa5hgw%da%d=%d", i, path,
954 + b[pathbase + SROM4_5GH_PA + i]);
955 + vp++;
956 + }
957 + }
958 +
959 + vp += sprintf(vp, "cck2gpo=%d", b[SROM4_2G_CCKPO]);
960 + vp++;
961 +
962 + w32 = ((uint32)b[SROM4_2G_OFDMPO + 1] << 16) | b[SROM4_2G_OFDMPO];
963 + vp += sprintf(vp, "ofdm2gpo=%d", w32);
964 + vp++;
965 +
966 + w32 = ((uint32)b[SROM4_5G_OFDMPO + 1] << 16) | b[SROM4_5G_OFDMPO];
967 + vp += sprintf(vp, "ofdm5gpo=%d", w32);
968 + vp++;
969 +
970 + w32 = ((uint32)b[SROM4_5GL_OFDMPO + 1] << 16) | b[SROM4_5GL_OFDMPO];
971 + vp += sprintf(vp, "ofdm5glpo=%d", w32);
972 + vp++;
973 +
974 + w32 = ((uint32)b[SROM4_5GH_OFDMPO + 1] << 16) | b[SROM4_5GH_OFDMPO];
975 + vp += sprintf(vp, "ofdm5ghpo=%d", w32);
976 + vp++;
977 +
978 + for (i = 0; i < 8; i++) {
979 + vp += sprintf(vp, "mcs2gpo%d=%d", i, b[SROM4_2G_MCSPO]);
980 + vp++;
981 + vp += sprintf(vp, "mcs5gpo%d=%d", i, b[SROM4_5G_MCSPO]);
982 + vp++;
983 + vp += sprintf(vp, "mcs5glpo%d=%d", i, b[SROM4_5GL_MCSPO]);
984 + vp++;
985 + vp += sprintf(vp, "mcs5ghpo%d=%d", i, b[SROM4_5GH_MCSPO]);
986 + vp++;
987 + }
988 +
989 + vp += sprintf(vp, "ccdpo%d=%d", i, b[SROM4_CCDPO]);
990 + vp++;
991 + vp += sprintf(vp, "stbcpo%d=%d", i, b[SROM4_STBCPO]);
992 + vp++;
993 + vp += sprintf(vp, "bw40po%d=%d", i, b[SROM4_BW40PO]);
994 + vp++;
995 + vp += sprintf(vp, "bwduppo%d=%d", i, b[SROM4_BWDUPPO]);
996 + vp++;
997 +
998 + goto done;
999 + }
1000 + if (sromrev >= 3) {
1001 + /* New section takes over the 3th hardware function space */
1002 +
1003 + /* Words 22+23 are 11a (mid) ofdm power offsets */
1004 + w32 = ((uint32)b[23] << 16) | b[22];
1005 + vp += sprintf(vp, "ofdmapo=%d", w32);
1006 + vp++;
1007 +
1008 + /* Words 24+25 are 11a (low) ofdm power offsets */
1009 + w32 = ((uint32)b[25] << 16) | b[24];
1010 + vp += sprintf(vp, "ofdmalpo=%d", w32);
1011 + vp++;
1012 +
1013 + /* Words 26+27 are 11a (high) ofdm power offsets */
1014 + w32 = ((uint32)b[27] << 16) | b[26];
1015 + vp += sprintf(vp, "ofdmahpo=%d", w32);
1016 + vp++;
1017 +
1018 + /* LED Powersave duty cycle (oncount >> 24) (offcount >> 8) */
1019 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xff) << 24) | /* oncount */
1020 + ((uint32)((unsigned char)(b[21] & 0xff)) << 8); /* offcount */
1021 + vp += sprintf(vp, "leddc=%d", w32);
1022 +
1023 + vp++;
1024 + }
1025 +
1026 + if (sromrev >= 2) {
1027 + /* New section takes over the 4th hardware function space */
1028 +
1029 + /* Word 29 is max power 11a high/low */
1030 + w = b[29];
1031 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
1032 + vp++;
1033 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
1034 + vp++;
1035 +
1036 + /* Words 30-32 set the 11alow pa settings,
1037 + * 33-35 are the 11ahigh ones.
1038 + */
1039 + for (i = 0; i < 3; i++) {
1040 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
1041 + vp++;
1042 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
1043 + vp++;
1044 + }
1045 + w = b[59];
1046 + if (w == 0)
1047 + vp += sprintf(vp, "ccode=");
1048 + else
1049 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
1050 + vp++;
1051 +
1052 + }
1053 +
1054 + /* parameter section of sprom starts at byte offset 72 */
1055 + woff = 72/2;
1056 +
1057 + /* first 6 bytes are il0macaddr */
1058 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1059 + ea.octet[1] = b[woff] & 0xff;
1060 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1061 + ea.octet[3] = b[woff+1] & 0xff;
1062 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1063 + ea.octet[5] = b[woff+2] & 0xff;
1064 + woff += 3;
1065 + bcm_ether_ntoa(&ea, eabuf);
1066 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
1067 + vp++;
1068 +
1069 + /* next 6 bytes are et0macaddr */
1070 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1071 + ea.octet[1] = b[woff] & 0xff;
1072 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1073 + ea.octet[3] = b[woff+1] & 0xff;
1074 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1075 + ea.octet[5] = b[woff+2] & 0xff;
1076 + woff += 3;
1077 + bcm_ether_ntoa(&ea, eabuf);
1078 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
1079 + vp++;
1080 +
1081 + /* next 6 bytes are et1macaddr */
1082 + ea.octet[0] = (b[woff] >> 8) & 0xff;
1083 + ea.octet[1] = b[woff] & 0xff;
1084 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
1085 + ea.octet[3] = b[woff+1] & 0xff;
1086 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
1087 + ea.octet[5] = b[woff+2] & 0xff;
1088 + woff += 3;
1089 + bcm_ether_ntoa(&ea, eabuf);
1090 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
1091 + vp++;
1092 +
1093 + /*
1094 + * Enet phy settings one or two singles or a dual
1095 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
1096 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
1097 + * Bit 14 : Mdio for enet0
1098 + * Bit 15 : Mdio for enet1
1099 + */
1100 + w = b[woff];
1101 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
1102 + vp++;
1103 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
1104 + vp++;
1105 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
1106 + vp++;
1107 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
1108 + vp++;
1109 +
1110 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
1111 + w = b[46];
1112 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
1113 + vp++;
1114 +
1115 + if (sromrev > 1)
1116 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
1117 + else
1118 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
1119 + vp++;
1120 +
1121 + vp += sprintf(vp, "aa2g=%d", (w >> 12) & 0x3);
1122 + vp++;
1123 +
1124 + vp += sprintf(vp, "aa5g=%d", (w >> 14) & 0x3);
1125 + vp++;
1126 +
1127 + /* Words 47-49 set the (wl) pa settings */
1128 + woff = 47;
1129 +
1130 + for (i = 0; i < 3; i++) {
1131 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
1132 + vp++;
1133 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
1134 + vp++;
1135 + }
1136 +
1137 + /*
1138 + * Words 50-51 set the customer-configured wl led behavior.
1139 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
1140 + * LED behavior values defined in wlioctl.h .
1141 + */
1142 + w = b[50];
1143 + if ((w != 0) && (w != 0xffff)) {
1144 + /* ledbh0 */
1145 + vp += sprintf(vp, "ledbh0=%d", (w & 0xff));
1146 + vp++;
1147 +
1148 + /* ledbh1 */
1149 + vp += sprintf(vp, "ledbh1=%d", (w >> 8) & 0xff);
1150 + vp++;
1151 + }
1152 + w = b[51];
1153 + if ((w != 0) && (w != 0xffff)) {
1154 + /* ledbh2 */
1155 + vp += sprintf(vp, "ledbh2=%d", w & 0xff);
1156 + vp++;
1157 +
1158 + /* ledbh */
1159 + vp += sprintf(vp, "ledbh3=%d", (w >> 8) & 0xff);
1160 + vp++;
1161 + }
1162 +
1163 + /* Word 52 is max power 0/1 */
1164 + w = b[52];
1165 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
1166 + vp++;
1167 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
1168 + vp++;
1169 +
1170 + /* Word 56 is idle tssi target 0/1 */
1171 + w = b[56];
1172 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
1173 + vp++;
1174 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
1175 + vp++;
1176 +
1177 + /* Word 57 is boardflags, if not programmed make it zero */
1178 + w32 = (uint32)b[57];
1179 + if (w32 == 0xffff) w32 = 0;
1180 + if (sromrev > 1) {
1181 + /* Word 28 is the high bits of boardflags */
1182 + w32 |= (uint32)b[28] << 16;
1183 + }
1184 + vp += sprintf(vp, "boardflags=%d", w32);
1185 + vp++;
1186 +
1187 + /* Word 58 is antenna gain 0/1 */
1188 + w = b[58];
1189 + vp += sprintf(vp, "ag0=%d", w & 0xff);
1190 + vp++;
1191 +
1192 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
1193 + vp++;
1194 +
1195 + if (sromrev == 1) {
1196 + /* set the oem string */
1197 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
1198 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
1199 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
1200 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
1201 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
1202 + vp++;
1203 + } else if (sromrev == 2) {
1204 + /* Word 60 OFDM tx power offset from CCK level */
1205 + /* OFDM Power Offset - opo */
1206 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
1207 + vp++;
1208 + } else {
1209 + /* Word 60: cck power offsets */
1210 + vp += sprintf(vp, "cckpo=%d", b[60]);
1211 + vp++;
1212 +
1213 + /* Words 61+62: 11g ofdm power offsets */
1214 + w32 = ((uint32)b[62] << 16) | b[61];
1215 + vp += sprintf(vp, "ofdmgpo=%d", w32);
1216 + vp++;
1217 + }
1218 +
1219 + /* final nullbyte terminator */
1220 +done: *vp++ = '\0';
1221 +
1222 + ASSERT((vp - base) <= VARS_MAX);
1223 +
1224 +varsdone:
1225 + err = initvars_table(osh, base, vp, vars, count);
1226 +
1227 +err:
1228 +#ifdef WLTEST
1229 + if (base != mfgsromvars)
1230 +#endif
1231 + MFREE(osh, base, VARS_MAX);
1232 + MFREE(osh, b, SROM_MAX);
1233 + return err;
1234 +}
1235 +
1236 +/*
1237 + * Read the cis and call parsecis to initialize the vars.
1238 + * Return 0 on success, nonzero on error.
1239 + */
1240 +static int
1241 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, uint *count)
1242 +{
1243 + uint8 *cis = NULL;
1244 + int rc;
1245 + uint data_sz;
1246 +
1247 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
1248 +
1249 + if ((cis = MALLOC(osh, data_sz)) == NULL)
1250 + return (-2);
1251 +
1252 + if (sb_pcmciarev(sbh) == 1) {
1253 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
1254 + MFREE(osh, cis, data_sz);
1255 + return (-1);
1256 + }
1257 + /* fix up endianess for 16-bit data vs 8-bit parsing */
1258 + ltoh16_buf((uint16 *)cis, data_sz);
1259 + } else
1260 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
1261 +
1262 + rc = srom_parsecis(osh, &cis, 1, vars, count);
1263 +
1264 + MFREE(osh, cis, data_sz);
1265 +
1266 + return (rc);
1267 +}
1268 +
1269 diff -urN linux.old/arch/mips/bcm947xx/bcmutils.c linux.dev/arch/mips/bcm947xx/bcmutils.c
1270 --- linux.old/arch/mips/bcm947xx/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
1271 +++ linux.dev/arch/mips/bcm947xx/bcmutils.c 2006-04-28 00:34:02.000000000 +0200
1272 @@ -0,0 +1,247 @@
1273 +/*
1274 + * Misc useful OS-independent routines.
1275 + *
1276 + * Copyright 2006, Broadcom Corporation
1277 + * All Rights Reserved.
1278 + *
1279 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1280 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1281 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1282 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1283 + * $Id: bcmutils.c,v 1.1.1.12 2006/02/27 03:43:16 honor Exp $
1284 + */
1285 +
1286 +#include <typedefs.h>
1287 +#include <bcmdefs.h>
1288 +#include <stdarg.h>
1289 +#include <bcmutils.h>
1290 +#include <osl.h>
1291 +#include <sbutils.h>
1292 +#include <bcmnvram.h>
1293 +#include <bcmendian.h>
1294 +#include <bcmdevs.h>
1295 +
1296 +unsigned char bcm_ctype[] = {
1297 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
1298 + _BCM_C, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C|_BCM_S, _BCM_C,
1299 + _BCM_C, /* 8-15 */
1300 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
1301 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
1302 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
1303 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
1304 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
1305 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
1306 + _BCM_P, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X, _BCM_U|_BCM_X,
1307 + _BCM_U|_BCM_X, _BCM_U, /* 64-71 */
1308 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
1309 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
1310 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
1311 + _BCM_P, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X, _BCM_L|_BCM_X,
1312 + _BCM_L|_BCM_X, _BCM_L, /* 96-103 */
1313 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
1314 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
1315 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
1316 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 128-143 */
1317 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 144-159 */
1318 + _BCM_S|_BCM_SP, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1319 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 160-175 */
1320 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P,
1321 + _BCM_P, _BCM_P, _BCM_P, _BCM_P, _BCM_P, /* 176-191 */
1322 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U,
1323 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, /* 192-207 */
1324 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_P, _BCM_U, _BCM_U, _BCM_U,
1325 + _BCM_U, _BCM_U, _BCM_U, _BCM_U, _BCM_L, /* 208-223 */
1326 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L,
1327 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, /* 224-239 */
1328 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_P, _BCM_L, _BCM_L, _BCM_L,
1329 + _BCM_L, _BCM_L, _BCM_L, _BCM_L, _BCM_L /* 240-255 */
1330 +};
1331 +
1332 +
1333 +ulong
1334 +bcm_strtoul(char *cp, char **endp, uint base)
1335 +{
1336 + ulong result, value;
1337 + bool minus;
1338 +
1339 + minus = FALSE;
1340 +
1341 + while (bcm_isspace(*cp))
1342 + cp++;
1343 +
1344 + if (cp[0] == '+')
1345 + cp++;
1346 + else if (cp[0] == '-') {
1347 + minus = TRUE;
1348 + cp++;
1349 + }
1350 +
1351 + if (base == 0) {
1352 + if (cp[0] == '0') {
1353 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
1354 + base = 16;
1355 + cp = &cp[2];
1356 + } else {
1357 + base = 8;
1358 + cp = &cp[1];
1359 + }
1360 + } else
1361 + base = 10;
1362 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
1363 + cp = &cp[2];
1364 + }
1365 +
1366 + result = 0;
1367 +
1368 + while (bcm_isxdigit(*cp) &&
1369 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
1370 + result = result*base + value;
1371 + cp++;
1372 + }
1373 +
1374 + if (minus)
1375 + result = (ulong)(result * -1);
1376 +
1377 + if (endp)
1378 + *endp = (char *)cp;
1379 +
1380 + return (result);
1381 +}
1382 +
1383 +uchar
1384 +bcm_toupper(uchar c)
1385 +{
1386 + if (bcm_islower(c))
1387 + c -= 'a'-'A';
1388 + return (c);
1389 +}
1390 +
1391 +char*
1392 +bcm_ether_ntoa(struct ether_addr *ea, char *buf)
1393 +{
1394 + sprintf(buf, "%02x:%02x:%02x:%02x:%02x:%02x",
1395 + ea->octet[0]&0xff, ea->octet[1]&0xff, ea->octet[2]&0xff,
1396 + ea->octet[3]&0xff, ea->octet[4]&0xff, ea->octet[5]&0xff);
1397 + return (buf);
1398 +}
1399 +
1400 +
1401 +/*
1402 + * Search the name=value vars for a specific one and return its value.
1403 + * Returns NULL if not found.
1404 + */
1405 +char*
1406 +getvar(char *vars, char *name)
1407 +{
1408 + char *s;
1409 + int len;
1410 +
1411 + len = strlen(name);
1412 +
1413 + /* first look in vars[] */
1414 + for (s = vars; s && *s;) {
1415 + /* CSTYLED */
1416 + if ((memcmp(s, name, len) == 0) && (s[len] == '='))
1417 + return (&s[len+1]);
1418 +
1419 + while (*s++)
1420 + ;
1421 + }
1422 +
1423 + /* then query nvram */
1424 + return (nvram_get(name));
1425 +}
1426 +
1427 +/*
1428 + * Search the vars for a specific one and return its value as
1429 + * an integer. Returns 0 if not found.
1430 + */
1431 +int
1432 +getintvar(char *vars, char *name)
1433 +{
1434 + char *val;
1435 +
1436 + if ((val = getvar(vars, name)) == NULL)
1437 + return (0);
1438 +
1439 + return (bcm_strtoul(val, NULL, 0));
1440 +}
1441 +
1442 +
1443 +/*******************************************************************************
1444 + * crc8
1445 + *
1446 + * Computes a crc8 over the input data using the polynomial:
1447 + *
1448 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
1449 + *
1450 + * The caller provides the initial value (either CRC8_INIT_VALUE
1451 + * or the previous returned value) to allow for processing of
1452 + * discontiguous blocks of data. When generating the CRC the
1453 + * caller is responsible for complementing the final return value
1454 + * and inserting it into the byte stream. When checking, a final
1455 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
1456 + *
1457 + * Reference: Dallas Semiconductor Application Note 27
1458 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
1459 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
1460 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
1461 + *
1462 + * ****************************************************************************
1463 + */
1464 +
1465 +static uint8 crc8_table[256] = {
1466 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
1467 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
1468 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
1469 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
1470 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
1471 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
1472 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
1473 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
1474 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
1475 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
1476 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
1477 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
1478 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
1479 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
1480 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
1481 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
1482 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
1483 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
1484 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
1485 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
1486 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
1487 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
1488 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
1489 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
1490 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
1491 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
1492 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
1493 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
1494 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
1495 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
1496 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
1497 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
1498 +};
1499 +
1500 +#define CRC_INNER_LOOP(n, c, x) \
1501 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
1502 +
1503 +uint8
1504 +hndcrc8(
1505 + uint8 *pdata, /* pointer to array of data to process */
1506 + uint nbytes, /* number of input data bytes to process */
1507 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
1508 +)
1509 +{
1510 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
1511 + * to avoid the undefined and unnecessary (uint8 >> 8) operation.
1512 + */
1513 + while (nbytes-- > 0)
1514 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
1515 +
1516 + return crc;
1517 +}
1518 +
1519 +
1520 diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
1521 --- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
1522 +++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2006-04-27 19:24:19.000000000 +0200
1523 @@ -0,0 +1,234 @@
1524 +/*
1525 + * NVRAM variable manipulation (Linux kernel half)
1526 + *
1527 + * Copyright 2001-2003, Broadcom Corporation
1528 + * All Rights Reserved.
1529 + *
1530 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1531 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1532 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1533 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1534 + *
1535 + * $Id$
1536 + */
1537 +
1538 +#include <linux/config.h>
1539 +#include <linux/init.h>
1540 +#include <linux/module.h>
1541 +#include <linux/kernel.h>
1542 +#include <linux/string.h>
1543 +#include <asm/io.h>
1544 +#include <asm/uaccess.h>
1545 +
1546 +#include <typedefs.h>
1547 +#include <osl.h>
1548 +#include <bcmendian.h>
1549 +#include <bcmutils.h>
1550 +
1551 +#define NVRAM_SIZE (0x1ff0)
1552 +static char _nvdata[NVRAM_SIZE] __initdata;
1553 +static char _valuestr[256] __initdata;
1554 +
1555 +/*
1556 + * TLV types. These codes are used in the "type-length-value"
1557 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
1558 + *
1559 + * The layout of the flash/nvram is as follows:
1560 + *
1561 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
1562 + *
1563 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
1564 + * The "length" field marks the length of the data section, not
1565 + * including the type and length fields.
1566 + *
1567 + * Environment variables are stored as follows:
1568 + *
1569 + * <type_env> <length> <flags> <name> = <value>
1570 + *
1571 + * If bit 0 (low bit) is set, the length is an 8-bit value.
1572 + * If bit 0 (low bit) is clear, the length is a 16-bit value
1573 + *
1574 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
1575 + * indicates the size of the length field.
1576 + *
1577 + * Flags are from the constants below:
1578 + *
1579 + */
1580 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
1581 +#define ENV_LENGTH_8BITS 0x01
1582 +
1583 +#define ENV_TYPE_USER 0x80
1584 +
1585 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
1586 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
1587 +
1588 +/*
1589 + * The actual TLV types we support
1590 + */
1591 +
1592 +#define ENV_TLV_TYPE_END 0x00
1593 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
1594 +
1595 +/*
1596 + * Environment variable flags
1597 + */
1598 +
1599 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
1600 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
1601 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
1602 +
1603 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
1604 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
1605 +
1606 +
1607 +/* *********************************************************************
1608 + * _nvram_read(buffer,offset,length)
1609 + *
1610 + * Read data from the NVRAM device
1611 + *
1612 + * Input parameters:
1613 + * buffer - destination buffer
1614 + * offset - offset of data to read
1615 + * length - number of bytes to read
1616 + *
1617 + * Return value:
1618 + * number of bytes read, or <0 if error occured
1619 + ********************************************************************* */
1620 +static int
1621 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1622 +{
1623 + int i;
1624 + if (offset > NVRAM_SIZE)
1625 + return -1;
1626 +
1627 + for ( i = 0; i < length; i++) {
1628 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1629 + }
1630 + return length;
1631 +}
1632 +
1633 +
1634 +static char*
1635 +_strnchr(const char *dest,int c,size_t cnt)
1636 +{
1637 + while (*dest && (cnt > 0)) {
1638 + if (*dest == c) return (char *) dest;
1639 + dest++;
1640 + cnt--;
1641 + }
1642 + return NULL;
1643 +}
1644 +
1645 +
1646 +
1647 +/*
1648 + * Core support API: Externally visible.
1649 + */
1650 +
1651 +/*
1652 + * Get the value of an NVRAM variable
1653 + * @param name name of variable to get
1654 + * @return value of variable or NULL if undefined
1655 + */
1656 +
1657 +char*
1658 +cfe_env_get(unsigned char *nv_buf, char* name)
1659 +{
1660 + int size;
1661 + unsigned char *buffer;
1662 + unsigned char *ptr;
1663 + unsigned char *envval;
1664 + unsigned int reclen;
1665 + unsigned int rectype;
1666 + int offset;
1667 + int flg;
1668 +
1669 + size = NVRAM_SIZE;
1670 + buffer = &_nvdata[0];
1671 +
1672 + ptr = buffer;
1673 + offset = 0;
1674 +
1675 + /* Read the record type and length */
1676 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1677 + goto error;
1678 + }
1679 +
1680 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1681 +
1682 + /* Adjust pointer for TLV type */
1683 + rectype = *(ptr);
1684 + offset++;
1685 + size--;
1686 +
1687 + /*
1688 + * Read the length. It can be either 1 or 2 bytes
1689 + * depending on the code
1690 + */
1691 + if (rectype & ENV_LENGTH_8BITS) {
1692 + /* Read the record type and length - 8 bits */
1693 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1694 + goto error;
1695 + }
1696 + reclen = *(ptr);
1697 + size--;
1698 + offset++;
1699 + }
1700 + else {
1701 + /* Read the record type and length - 16 bits, MSB first */
1702 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1703 + goto error;
1704 + }
1705 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1706 + size -= 2;
1707 + offset += 2;
1708 + }
1709 +
1710 + if (reclen > size)
1711 + break; /* should not happen, bad NVRAM */
1712 +
1713 + switch (rectype) {
1714 + case ENV_TLV_TYPE_ENV:
1715 + /* Read the TLV data */
1716 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1717 + goto error;
1718 + flg = *ptr++;
1719 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1720 + if (envval) {
1721 + *envval++ = '\0';
1722 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1723 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1724 +#if 0
1725 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1726 +#endif
1727 + if(!strcmp(ptr, name)){
1728 + return _valuestr;
1729 + }
1730 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1731 + return _valuestr;
1732 + }
1733 + break;
1734 +
1735 + default:
1736 + /* Unknown TLV type, skip it. */
1737 + break;
1738 + }
1739 +
1740 + /*
1741 + * Advance to next TLV
1742 + */
1743 +
1744 + size -= (int)reclen;
1745 + offset += reclen;
1746 +
1747 + /* Read the next record type */
1748 + ptr = buffer;
1749 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1750 + goto error;
1751 + }
1752 +
1753 +error:
1754 + return NULL;
1755 +
1756 +}
1757 +
1758 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
1759 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
1760 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2006-04-27 19:24:19.000000000 +0200
1761 @@ -0,0 +1,33 @@
1762 +#
1763 +# Makefile for Broadcom BCM947XX boards
1764 +#
1765 +# Copyright 2001-2003, Broadcom Corporation
1766 +# All Rights Reserved.
1767 +#
1768 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1769 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1770 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1771 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1772 +#
1773 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
1774 +#
1775 +
1776 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
1777 +SYSTEM ?= $(TOPDIR)/vmlinux
1778 +
1779 +all: vmlinuz
1780 +
1781 +# Don't build dependencies, this may die if $(CC) isn't gcc
1782 +dep:
1783 +
1784 +# Create a gzipped version named vmlinuz for compatibility
1785 +vmlinuz: piggy
1786 + gzip -c9 $< > $@
1787 +
1788 +piggy: $(SYSTEM)
1789 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
1790 +
1791 +mrproper: clean
1792 +
1793 +clean:
1794 + rm -f vmlinuz piggy
1795 diff -urN linux.old/arch/mips/bcm947xx/export.c linux.dev/arch/mips/bcm947xx/export.c
1796 --- linux.old/arch/mips/bcm947xx/export.c 1970-01-01 01:00:00.000000000 +0100
1797 +++ linux.dev/arch/mips/bcm947xx/export.c 2006-04-28 02:57:34.000000000 +0200
1798 @@ -0,0 +1,65 @@
1799 +#include <linux/module.h>
1800 +
1801 +#define _export(n) \
1802 + void n(void); \
1803 + EXPORT_SYMBOL(n);
1804 +
1805 +_export(bcm947xx_sbh)
1806 +
1807 +_export(sb_attach)
1808 +_export(sb_kattach)
1809 +_export(sb_boardtype)
1810 +_export(sb_boardvendor)
1811 +_export(sb_btcgpiowar)
1812 +_export(sb_bus)
1813 +_export(sb_chip)
1814 +_export(sb_chiprev)
1815 +_export(sb_chipcrev)
1816 +_export(sb_chippkg)
1817 +_export(sb_clkctl_clk)
1818 +_export(sb_clkctl_fast_pwrup_delay)
1819 +_export(sb_clkctl_init)
1820 +_export(sb_clkctl_xtal)
1821 +_export(sb_core_disable)
1822 +_export(sb_core_reset)
1823 +_export(sb_core_tofixup)
1824 +_export(sb_coreflags)
1825 +_export(sb_coreflagshi)
1826 +_export(sb_coreidx)
1827 +_export(sb_corerev)
1828 +_export(sb_coreunit)
1829 +_export(sb_detach)
1830 +_export(sb_deviceremoved)
1831 +_export(sb_gpiosetcore)
1832 +_export(sb_gpiocontrol)
1833 +_export(sb_gpioled)
1834 +_export(sb_gpioin)
1835 +_export(sb_gpioout)
1836 +_export(sb_gpioouten)
1837 +_export(sb_gpiotimerval)
1838 +_export(sb_iscoreup)
1839 +_export(sb_pci_setup)
1840 +_export(sb_pcirev)
1841 +_export(sb_pcmcia_init)
1842 +_export(sb_pcmciarev)
1843 +_export(sb_register_intr_callback)
1844 +_export(sb_setcore)
1845 +_export(sb_war16165)
1846 +_export(sb_osh)
1847 +
1848 +_export(getvar)
1849 +_export(getintvar)
1850 +_export(bcm_strtoul)
1851 +_export(bcm_ctype)
1852 +_export(bcm_toupper)
1853 +_export(bcm_ether_ntoa)
1854 +
1855 +_export(nvram_get)
1856 +_export(nvram_getall)
1857 +_export(nvram_set)
1858 +_export(nvram_unset)
1859 +_export(nvram_commit)
1860 +
1861 +_export(srom_read)
1862 +_export(srom_write)
1863 +
1864 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
1865 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
1866 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2006-04-27 19:24:19.000000000 +0200
1867 @@ -0,0 +1,15 @@
1868 +#
1869 +# Makefile for the BCM947xx specific kernel interface routines
1870 +# under Linux.
1871 +#
1872 +
1873 +.S.s:
1874 + $(CPP) $(AFLAGS) $< -o $*.s
1875 +.S.o:
1876 + $(CC) $(AFLAGS) -c $< -o $*.o
1877 +
1878 +O_TARGET := brcm.o
1879 +
1880 +obj-y := int-handler.o irq.o
1881 +
1882 +include $(TOPDIR)/Rules.make
1883 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
1884 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
1885 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2006-04-27 19:24:19.000000000 +0200
1886 @@ -0,0 +1,51 @@
1887 +/*
1888 + * Generic interrupt handler for Broadcom MIPS boards
1889 + *
1890 + * Copyright 2004, Broadcom Corporation
1891 + * All Rights Reserved.
1892 + *
1893 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1894 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1895 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1896 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1897 + *
1898 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
1899 + */
1900 +
1901 +#include <linux/config.h>
1902 +
1903 +#include <asm/asm.h>
1904 +#include <asm/mipsregs.h>
1905 +#include <asm/regdef.h>
1906 +#include <asm/stackframe.h>
1907 +
1908 +/*
1909 + * MIPS IRQ Source
1910 + * -------- ------
1911 + * 0 Software (ignored)
1912 + * 1 Software (ignored)
1913 + * 2 Combined hardware interrupt (hw0)
1914 + * 3 Hardware
1915 + * 4 Hardware
1916 + * 5 Hardware
1917 + * 6 Hardware
1918 + * 7 R4k timer
1919 + */
1920 +
1921 + .text
1922 + .set noreorder
1923 + .set noat
1924 + .align 5
1925 + NESTED(brcmIRQ, PT_SIZE, sp)
1926 + SAVE_ALL
1927 + CLI
1928 + .set at
1929 + .set noreorder
1930 +
1931 + jal brcm_irq_dispatch
1932 + move a0, sp
1933 +
1934 + j ret_from_irq
1935 + nop
1936 +
1937 + END(brcmIRQ)
1938 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
1939 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
1940 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2006-04-27 19:24:19.000000000 +0200
1941 @@ -0,0 +1,130 @@
1942 +/*
1943 + * Generic interrupt control functions for Broadcom MIPS boards
1944 + *
1945 + * Copyright 2004, Broadcom Corporation
1946 + * All Rights Reserved.
1947 + *
1948 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1949 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1950 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1951 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1952 + *
1953 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
1954 + */
1955 +
1956 +#include <linux/config.h>
1957 +#include <linux/init.h>
1958 +#include <linux/kernel.h>
1959 +#include <linux/types.h>
1960 +#include <linux/interrupt.h>
1961 +#include <linux/irq.h>
1962 +
1963 +#include <asm/irq.h>
1964 +#include <asm/mipsregs.h>
1965 +#include <asm/gdb-stub.h>
1966 +
1967 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
1968 +
1969 +extern asmlinkage void brcmIRQ(void);
1970 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
1971 +
1972 +void
1973 +brcm_irq_dispatch(struct pt_regs *regs)
1974 +{
1975 + u32 cause;
1976 +
1977 + cause = read_c0_cause() &
1978 + read_c0_status() &
1979 + CAUSEF_IP;
1980 +
1981 +#ifdef CONFIG_KERNPROF
1982 + change_c0_status(cause | 1, 1);
1983 +#else
1984 + clear_c0_status(cause);
1985 +#endif
1986 +
1987 + if (cause & CAUSEF_IP7)
1988 + do_IRQ(7, regs);
1989 + if (cause & CAUSEF_IP2)
1990 + do_IRQ(2, regs);
1991 + if (cause & CAUSEF_IP3)
1992 + do_IRQ(3, regs);
1993 + if (cause & CAUSEF_IP4)
1994 + do_IRQ(4, regs);
1995 + if (cause & CAUSEF_IP5)
1996 + do_IRQ(5, regs);
1997 + if (cause & CAUSEF_IP6)
1998 + do_IRQ(6, regs);
1999 +}
2000 +
2001 +static void
2002 +enable_brcm_irq(unsigned int irq)
2003 +{
2004 + if (irq < 8)
2005 + set_c0_status(1 << (irq + 8));
2006 + else
2007 + set_c0_status(IE_IRQ0);
2008 +}
2009 +
2010 +static void
2011 +disable_brcm_irq(unsigned int irq)
2012 +{
2013 + if (irq < 8)
2014 + clear_c0_status(1 << (irq + 8));
2015 + else
2016 + clear_c0_status(IE_IRQ0);
2017 +}
2018 +
2019 +static void
2020 +ack_brcm_irq(unsigned int irq)
2021 +{
2022 + /* Already done in brcm_irq_dispatch */
2023 +}
2024 +
2025 +static unsigned int
2026 +startup_brcm_irq(unsigned int irq)
2027 +{
2028 + enable_brcm_irq(irq);
2029 +
2030 + return 0; /* never anything pending */
2031 +}
2032 +
2033 +static void
2034 +end_brcm_irq(unsigned int irq)
2035 +{
2036 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
2037 + enable_brcm_irq(irq);
2038 +}
2039 +
2040 +static struct hw_interrupt_type brcm_irq_type = {
2041 + typename: "MIPS",
2042 + startup: startup_brcm_irq,
2043 + shutdown: disable_brcm_irq,
2044 + enable: enable_brcm_irq,
2045 + disable: disable_brcm_irq,
2046 + ack: ack_brcm_irq,
2047 + end: end_brcm_irq,
2048 + NULL
2049 +};
2050 +
2051 +void __init
2052 +init_IRQ(void)
2053 +{
2054 + int i;
2055 +
2056 + for (i = 0; i < NR_IRQS; i++) {
2057 + irq_desc[i].status = IRQ_DISABLED;
2058 + irq_desc[i].action = 0;
2059 + irq_desc[i].depth = 1;
2060 + irq_desc[i].handler = &brcm_irq_type;
2061 + }
2062 +
2063 + set_except_vector(0, brcmIRQ);
2064 + change_c0_status(ST0_IM, ALLINTS);
2065 +
2066 +#ifdef CONFIG_REMOTE_DEBUG
2067 + printk("Breaking into debugger...\n");
2068 + set_debug_traps();
2069 + breakpoint();
2070 +#endif
2071 +}
2072 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
2073 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
2074 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2006-04-27 23:09:33.000000000 +0200
2075 @@ -0,0 +1,159 @@
2076 +/*
2077 + * GPIO char driver
2078 + *
2079 + * Copyright 2005, Broadcom Corporation
2080 + * All Rights Reserved.
2081 + *
2082 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2083 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2084 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2085 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2086 + *
2087 + * $Id$
2088 + */
2089 +
2090 +#include <linux/module.h>
2091 +#include <linux/init.h>
2092 +#include <linux/fs.h>
2093 +#include <linux/miscdevice.h>
2094 +#include <asm/uaccess.h>
2095 +
2096 +#include <typedefs.h>
2097 +#include <osl.h>
2098 +#include <bcmutils.h>
2099 +#include <sbutils.h>
2100 +#include <bcmdevs.h>
2101 +
2102 +static sb_t *gpio_sbh;
2103 +static int gpio_major;
2104 +static devfs_handle_t gpio_dir;
2105 +static struct {
2106 + char *name;
2107 + devfs_handle_t handle;
2108 +} gpio_file[] = {
2109 + { "in", NULL },
2110 + { "out", NULL },
2111 + { "outen", NULL },
2112 + { "control", NULL }
2113 +};
2114 +
2115 +static int
2116 +gpio_open(struct inode *inode, struct file * file)
2117 +{
2118 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
2119 + return -ENODEV;
2120 +
2121 + MOD_INC_USE_COUNT;
2122 + return 0;
2123 +}
2124 +
2125 +static int
2126 +gpio_release(struct inode *inode, struct file * file)
2127 +{
2128 + MOD_DEC_USE_COUNT;
2129 + return 0;
2130 +}
2131 +
2132 +static ssize_t
2133 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2134 +{
2135 + u32 val;
2136 +
2137 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2138 + case 0:
2139 + val = sb_gpioin(gpio_sbh);
2140 + break;
2141 + case 1:
2142 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2143 + break;
2144 + case 2:
2145 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2146 + break;
2147 + case 3:
2148 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
2149 + break;
2150 + default:
2151 + return -ENODEV;
2152 + }
2153 +
2154 + if (put_user(val, (u32 *) buf))
2155 + return -EFAULT;
2156 +
2157 + return sizeof(val);
2158 +}
2159 +
2160 +static ssize_t
2161 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
2162 +{
2163 + u32 val;
2164 +
2165 + if (get_user(val, (u32 *) buf))
2166 + return -EFAULT;
2167 +
2168 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
2169 + case 0:
2170 + return -EACCES;
2171 + case 1:
2172 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2173 + break;
2174 + case 2:
2175 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2176 + break;
2177 + case 3:
2178 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
2179 + break;
2180 + default:
2181 + return -ENODEV;
2182 + }
2183 +
2184 + return sizeof(val);
2185 +}
2186 +
2187 +static struct file_operations gpio_fops = {
2188 + owner: THIS_MODULE,
2189 + open: gpio_open,
2190 + release: gpio_release,
2191 + read: gpio_read,
2192 + write: gpio_write,
2193 +};
2194 +
2195 +static int __init
2196 +gpio_init(void)
2197 +{
2198 + int i;
2199 +
2200 + if (!(gpio_sbh = sb_kattach()))
2201 + return -ENODEV;
2202 +
2203 + sb_gpiosetcore(gpio_sbh);
2204 +
2205 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
2206 + return gpio_major;
2207 +
2208 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
2209 +
2210 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
2211 + gpio_file[i].handle = devfs_register(gpio_dir,
2212 + gpio_file[i].name,
2213 + DEVFS_FL_DEFAULT, gpio_major, i,
2214 + S_IFCHR | S_IRUGO | S_IWUGO,
2215 + &gpio_fops, NULL);
2216 + }
2217 +
2218 + return 0;
2219 +}
2220 +
2221 +static void __exit
2222 +gpio_exit(void)
2223 +{
2224 + int i;
2225 +
2226 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
2227 + devfs_unregister(gpio_file[i].handle);
2228 + devfs_unregister(gpio_dir);
2229 + devfs_unregister_chrdev(gpio_major, "gpio");
2230 + sb_detach(gpio_sbh);
2231 +}
2232 +
2233 +module_init(gpio_init);
2234 +module_exit(gpio_exit);
2235 diff -urN linux.old/arch/mips/bcm947xx/hndchipc.c linux.dev/arch/mips/bcm947xx/hndchipc.c
2236 --- linux.old/arch/mips/bcm947xx/hndchipc.c 1970-01-01 01:00:00.000000000 +0100
2237 +++ linux.dev/arch/mips/bcm947xx/hndchipc.c 2006-04-28 00:33:05.000000000 +0200
2238 @@ -0,0 +1,158 @@
2239 +/*
2240 + * BCM47XX support code for some chipcommon (old extif) facilities (uart)
2241 + *
2242 + * Copyright 2006, Broadcom Corporation
2243 + * All Rights Reserved.
2244 + *
2245 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2246 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2247 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2248 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2249 + *
2250 + * $Id: hndchipc.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
2251 + */
2252 +
2253 +#include <typedefs.h>
2254 +#include <bcmdefs.h>
2255 +#include <osl.h>
2256 +#include <bcmutils.h>
2257 +#include <sbutils.h>
2258 +#include <bcmdevs.h>
2259 +#include <bcmnvram.h>
2260 +#include <sbconfig.h>
2261 +#include <sbextif.h>
2262 +#include <sbchipc.h>
2263 +#include <hndcpu.h>
2264 +
2265 +/*
2266 + * Returns TRUE if an external UART exists at the given base
2267 + * register.
2268 + */
2269 +static bool
2270 +BCMINITFN(serial_exists)(osl_t *osh, uint8 *regs)
2271 +{
2272 + uint8 save_mcr, status1;
2273 +
2274 + save_mcr = R_REG(osh, &regs[UART_MCR]);
2275 + W_REG(osh, &regs[UART_MCR], UART_MCR_LOOP | 0x0a);
2276 + status1 = R_REG(osh, &regs[UART_MSR]) & 0xf0;
2277 + W_REG(osh, &regs[UART_MCR], save_mcr);
2278 +
2279 + return (status1 == 0x90);
2280 +}
2281 +
2282 +/*
2283 + * Initializes UART access. The callback function will be called once
2284 + * per found UART.
2285 + */
2286 +void
2287 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base,
2288 + uint reg_shift))
2289 +{
2290 + osl_t *osh;
2291 + void *regs;
2292 + ulong base;
2293 + uint irq;
2294 + int i, n;
2295 +
2296 + osh = sb_osh(sbh);
2297 +
2298 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
2299 + extifregs_t *eir = (extifregs_t *) regs;
2300 + sbconfig_t *sb;
2301 +
2302 + /* Determine external UART register base */
2303 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
2304 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(osh, &sb->sbadmatch1)));
2305 +
2306 + /* Determine IRQ */
2307 + irq = sb_irq(sbh);
2308 +
2309 + /* Disable GPIO interrupt initially */
2310 + W_REG(osh, &eir->gpiointpolarity, 0);
2311 + W_REG(osh, &eir->gpiointmask, 0);
2312 +
2313 + /* Search for external UARTs */
2314 + n = 2;
2315 + for (i = 0; i < 2; i++) {
2316 + regs = (void *) REG_MAP(base + (i * 8), 8);
2317 + if (serial_exists(osh, regs)) {
2318 + /* Set GPIO 1 to be the external UART IRQ */
2319 + W_REG(osh, &eir->gpiointmask, 2);
2320 + /* XXXDetermine external UART clock */
2321 + if (add)
2322 + add(regs, irq, 13500000, 0);
2323 + }
2324 + }
2325 +
2326 + /* Add internal UART if enabled */
2327 + if (R_REG(osh, &eir->corecontrol) & CC_UE)
2328 + if (add)
2329 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
2330 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
2331 + chipcregs_t *cc = (chipcregs_t *) regs;
2332 + uint32 rev, cap, pll, baud_base, div;
2333 +
2334 + /* Determine core revision and capabilities */
2335 + rev = sb_corerev(sbh);
2336 + cap = R_REG(osh, &cc->capabilities);
2337 + pll = cap & CAP_PLL_MASK;
2338 +
2339 + /* Determine IRQ */
2340 + irq = sb_irq(sbh);
2341 +
2342 + if (pll == PLL_TYPE1) {
2343 + /* PLL clock */
2344 + baud_base = sb_clock_rate(pll,
2345 + R_REG(osh, &cc->clockcontrol_n),
2346 + R_REG(osh, &cc->clockcontrol_m2));
2347 + div = 1;
2348 + } else {
2349 + /* Fixed ALP clock */
2350 + if (rev >= 11 && rev != 15) {
2351 + baud_base = 20000000;
2352 + div = 1;
2353 + /* Set the override bit so we don't divide it */
2354 + W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
2355 + }
2356 + /* Internal backplane clock */
2357 + else if (rev >= 3) {
2358 + baud_base = sb_clock(sbh);
2359 + div = 2; /* Minimum divisor */
2360 + W_REG(osh, &cc->clkdiv,
2361 + ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
2362 + }
2363 + /* Fixed internal backplane clock */
2364 + else {
2365 + baud_base = 88000000;
2366 + div = 48;
2367 + }
2368 +
2369 + /* Clock source depends on strapping if UartClkOverride is unset */
2370 + if ((rev > 0) &&
2371 + ((R_REG(osh, &cc->corecontrol) & CC_UARTCLKO) == 0)) {
2372 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
2373 + /* Internal divided backplane clock */
2374 + baud_base /= div;
2375 + } else {
2376 + /* Assume external clock of 1.8432 MHz */
2377 + baud_base = 1843200;
2378 + }
2379 + }
2380 + }
2381 +
2382 + /* Add internal UARTs */
2383 + n = cap & CAP_UARTS_MASK;
2384 + for (i = 0; i < n; i++) {
2385 + /* Register offset changed after revision 0 */
2386 + if (rev)
2387 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
2388 + else
2389 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
2390 +
2391 + if (add)
2392 + add(regs, irq, baud_base, 0);
2393 + }
2394 + }
2395 +}
2396 +
2397 diff -urN linux.old/arch/mips/bcm947xx/include/bcm4710.h linux.dev/arch/mips/bcm947xx/include/bcm4710.h
2398 --- linux.old/arch/mips/bcm947xx/include/bcm4710.h 1970-01-01 01:00:00.000000000 +0100
2399 +++ linux.dev/arch/mips/bcm947xx/include/bcm4710.h 2006-04-27 22:30:01.000000000 +0200
2400 @@ -0,0 +1,91 @@
2401 +/*
2402 + * BCM4710 address space map and definitions
2403 + * Think twice before adding to this file, this is not the kitchen sink
2404 + * These definitions are not guaranteed for all 47xx chips, only the 4710
2405 + *
2406 + * Copyright 2004, Broadcom Corporation
2407 + * All Rights Reserved.
2408 + *
2409 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2410 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2411 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2412 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2413 + *
2414 + * $Id: bcm4710.h,v 1.3 2004/09/27 07:23:30 tallest Exp $
2415 + */
2416 +
2417 +#ifndef _bcm4710_h_
2418 +#define _bcm4710_h_
2419 +
2420 +/* Address map */
2421 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
2422 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
2423 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
2424 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
2425 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
2426 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
2427 +
2428 +/* Core register space */
2429 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
2430 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
2431 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
2432 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
2433 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
2434 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
2435 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
2436 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
2437 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
2438 +
2439 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
2440 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
2441 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
2442 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
2443 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
2444 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
2445 +
2446 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
2447 +
2448 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
2449 +
2450 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
2451 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
2452 +
2453 +#define SBFLAG_PCI 0
2454 +#define SBFLAG_ENET0 1
2455 +#define SBFLAG_ILINE20 2
2456 +#define SBFLAG_CODEC 3
2457 +#define SBFLAG_USB 4
2458 +#define SBFLAG_EXTIF 5
2459 +#define SBFLAG_ENET1 6
2460 +
2461 +#ifdef CONFIG_HWSIM
2462 +#define BCM4710_TRACE(trval) do { *((int *)0xa0000f18) = (trval); } while (0)
2463 +#else
2464 +#define BCM4710_TRACE(trval)
2465 +#endif
2466 +
2467 +
2468 +/* BCM94702 CPCI -ExtIF used for LocalBus devs */
2469 +
2470 +#define BCM94702_CPCI_RESET_ADDR BCM4710_EXTIF
2471 +#define BCM94702_CPCI_BOARDID_ADDR (BCM4710_EXTIF | 0x4000)
2472 +#define BCM94702_CPCI_DOC_ADDR (BCM4710_EXTIF | 0x6000)
2473 +#define BCM94702_DOC_ADDR BCM94702_CPCI_DOC_ADDR
2474 +#define BCM94702_CPCI_LED_ADDR (BCM4710_EXTIF | 0xc000)
2475 +#define BCM94702_CPCI_NVRAM_ADDR (BCM4710_EXTIF | 0xe000)
2476 +#define BCM94702_CPCI_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
2477 +#define BCM94702_CPCI_TOD_REG_BASE (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
2478 +
2479 +#define LED_REG(x) \
2480 + (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
2481 +
2482 +/*
2483 + * Reset function implemented in PLD. Read or write should trigger hard reset
2484 + */
2485 +#define SYS_HARD_RESET() \
2486 + { for (;;) \
2487 + *( (volatile unsigned char *)\
2488 + KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
2489 + }
2490 +
2491 +#endif /* _bcm4710_h_ */
2492 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdefs.h linux.dev/arch/mips/bcm947xx/include/bcmdefs.h
2493 --- linux.old/arch/mips/bcm947xx/include/bcmdefs.h 1970-01-01 01:00:00.000000000 +0100
2494 +++ linux.dev/arch/mips/bcm947xx/include/bcmdefs.h 2006-04-27 20:12:21.000000000 +0200
2495 @@ -0,0 +1,106 @@
2496 +/*
2497 + * Misc system wide definitions
2498 + *
2499 + * Copyright 2006, Broadcom Corporation
2500 + * All Rights Reserved.
2501 + *
2502 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2503 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2504 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2505 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2506 + * $Id: bcmdefs.h,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
2507 + */
2508 +
2509 +#ifndef _bcmdefs_h_
2510 +#define _bcmdefs_h_
2511 +
2512 +/*
2513 + * One doesn't need to include this file explicitly, gets included automatically if
2514 + * typedefs.h is included.
2515 + */
2516 +
2517 +/* Reclaiming text and data :
2518 + * The following macros specify special linker sections that can be reclaimed
2519 + * after a system is considered 'up'.
2520 + */
2521 +#if defined(__GNUC__) && defined(BCMRECLAIM)
2522 +extern bool bcmreclaimed;
2523 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data
2524 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn
2525 +#else /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2526 +#define BCMINITDATA(_data) _data
2527 +#define BCMINITFN(_fn) _fn
2528 +#define bcmreclaimed 0
2529 +#endif /* #if defined(__GNUC__) && defined(BCMRECLAIM) */
2530 +
2531 +/* Reclaim uninit functions if BCMNODOWN is defined */
2532 +/* and if they are not already removed by -gc-sections */
2533 +#ifdef BCMNODOWN
2534 +#define BCMUNINITFN(_fn) BCMINITFN(_fn)
2535 +#else
2536 +#define BCMUNINITFN(_fn) _fn
2537 +#endif
2538 +
2539 +#ifdef BCMRECLAIM
2540 +#define CONST
2541 +#else
2542 +#define CONST const
2543 +#endif /* BCMRECLAIM */
2544 +
2545 +/* Compatibility with old-style BCMRECLAIM */
2546 +#define BCMINIT(_id) _id
2547 +
2548 +
2549 +/* Put some library data/code into ROM to reduce RAM requirements */
2550 +#if defined(__GNUC__) && defined(BCMROMOFFLOAD)
2551 +#define BCMROMDATA(_data) __attribute__ ((__section__ (".datarom." #_data))) _data
2552 +#define BCMROMFN(_fn) __attribute__ ((__section__ (".textrom." #_fn))) _fn
2553 +#else
2554 +#define BCMROMDATA(_data) _data
2555 +#define BCMROMFN(_fn) _fn
2556 +#endif
2557 +
2558 +/* Bus types */
2559 +#define SB_BUS 0 /* Silicon Backplane */
2560 +#define PCI_BUS 1 /* PCI target */
2561 +#define PCMCIA_BUS 2 /* PCMCIA target */
2562 +#define SDIO_BUS 3 /* SDIO target */
2563 +#define JTAG_BUS 4 /* JTAG */
2564 +#define NO_BUS 0xFF /* Bus that does not support R/W REG */
2565 +
2566 +/* Allows optimization for single-bus support */
2567 +#ifdef BCMBUSTYPE
2568 +#define BUSTYPE(bus) (BCMBUSTYPE)
2569 +#else
2570 +#define BUSTYPE(bus) (bus)
2571 +#endif
2572 +
2573 +/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
2574 +#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
2575 +#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
2576 +#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
2577 +
2578 +#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
2579 +#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
2580 +#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
2581 +#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
2582 +
2583 +/* packet headroom necessary to accomodate the largest header in the system, (i.e TXOFF).
2584 + * By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
2585 + * There is a compile time check in wlc.c which ensure that this value is at least as big
2586 + * as TXOFF. This value is used in dma_rxfill (hnddma.c).
2587 + */
2588 +#define BCMEXTRAHDROOM 160
2589 +
2590 +/* Headroom required for dongle-to-host communication. Packets allocated
2591 + * locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
2592 + * leave this much room in front for low-level message headers which may
2593 + * be needed to get across the dongle bus to the host. (These messages
2594 + * don't go over the network, so room for the full WL header above would
2595 + * be a waste.)
2596 + */
2597 +#define BCMDONGLEHDRSZ 8
2598 +
2599 +
2600 +
2601 +#endif /* _bcmdefs_h_ */
2602 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
2603 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
2604 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2006-04-27 22:30:25.000000000 +0200
2605 @@ -0,0 +1,369 @@
2606 +/*
2607 + * Broadcom device-specific manifest constants.
2608 + *
2609 + * Copyright 2006, Broadcom Corporation
2610 + * All Rights Reserved.
2611 + *
2612 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2613 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2614 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2615 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2616 + * $Id: bcmdevs.h,v 1.1.1.17 2006/04/15 01:29:08 michael Exp $
2617 + */
2618 +
2619 +#ifndef _BCMDEVS_H
2620 +#define _BCMDEVS_H
2621 +
2622 +#include "bcm4710.h"
2623 +
2624 +/* Known PCI vendor Id's */
2625 +#define VENDOR_EPIGRAM 0xfeda
2626 +#define VENDOR_BROADCOM 0x14e4
2627 +#define VENDOR_3COM 0x10b7
2628 +#define VENDOR_NETGEAR 0x1385
2629 +#define VENDOR_DIAMOND 0x1092
2630 +#define VENDOR_DELL 0x1028
2631 +#define VENDOR_HP 0x0e11
2632 +#define VENDOR_APPLE 0x106b
2633 +
2634 +/* PCI Device Id's */
2635 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
2636 +#define BCM4211_DEVICE_ID 0x4211
2637 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
2638 +#define BCM4231_DEVICE_ID 0x4231
2639 +
2640 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
2641 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
2642 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
2643 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
2644 +
2645 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
2646 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
2647 +
2648 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
2649 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
2650 +
2651 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
2652 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
2653 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
2654 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
2655 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
2656 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
2657 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
2658 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
2659 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
2660 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
2661 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
2662 +#define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
2663 +#define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
2664 +#define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
2665 +
2666 +#define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
2667 +#define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
2668 +
2669 +#define BCM4710_CHIP_ID 0x4710 /* 4710 chipid returned by sb_chip() */
2670 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
2671 +
2672 +#define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
2673 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
2674 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
2675 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
2676 +
2677 +#define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
2678 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
2679 +#define BCM4306_D11G_ID2 0x4325
2680 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
2681 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
2682 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
2683 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
2684 +
2685 +#define BCM4309_PKG_ID 1 /* 4309 package id */
2686 +
2687 +#define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
2688 +#define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
2689 +#define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
2690 +#define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
2691 +
2692 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
2693 +#define BCM4303_PKG_ID 2 /* 4303 package id */
2694 +
2695 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
2696 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
2697 +
2698 +#define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
2699 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
2700 +
2701 +#define BCM4318_CHIP_ID 0x4318 /* 4318 chip common chipid */
2702 +#define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
2703 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
2704 +#define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
2705 +
2706 +#define BCM4321_CHIP_ID 0x4321 /* 4321 chip common chipid */
2707 +#define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
2708 +#define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Hgz band id */
2709 +#define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
2710 +
2711 +#define BCM4331_CHIP_ID 0x4331 /* 4331 chip common chipid */
2712 +#define BCM4331_D11N2G_ID 0x4330 /* 4331 802.11n 2.4Ghz band id */
2713 +#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
2714 +#define BCM4331_D11N5G_ID 0x4332 /* 4331 802.11n 5Ghz band id */
2715 +
2716 +#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
2717 +#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
2718 +#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
2719 +
2720 +#define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
2721 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
2722 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
2723 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
2724 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
2725 +
2726 +#define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
2727 +#define BCM5350_CHIP_ID 0x5350 /* bcm5350 chipcommon chipid */
2728 +#define BCM5352_CHIP_ID 0x5352 /* bcm5352 chipcommon chipid */
2729 +
2730 +#define BCM4320_CHIP_ID 0x4320 /* bcm4320 chipcommon chipid */
2731 +
2732 +#define BCM4328_CHIP_ID 0x4328 /* bcm4328 chipcommon chipid */
2733 +
2734 +#define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
2735 +#define BCM43XX_JTAGM_ID 0x43f1 /* 43xx jtagm device id */
2736 +#define BCM43XXOLD_JTAGM_ID 0x4331 /* 43xx old jtagm device id */
2737 +
2738 +#define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
2739 +#define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
2740 +
2741 +#define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
2742 +
2743 +#define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
2744 +
2745 +/* PCMCIA vendor Id's */
2746 +
2747 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
2748 +
2749 +/* SDIO vendor Id's */
2750 +#define VENDOR_BROADCOM_SDIO 0x00BF
2751 +
2752 +
2753 +/* boardflags */
2754 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
2755 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
2756 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
2757 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
2758 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
2759 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
2760 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
2761 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
2762 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
2763 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
2764 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
2765 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
2766 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
2767 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
2768 +
2769 +/* boardflags2 */
2770 +#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* This board has an external rxbb regulator */
2771 +#define BFL2_SSWITCH_AVAIL 0x00000002 /* This board has a superswitch for > 2 antennas */
2772 +#define BFL2_TXPWRCTRL_EN 0x00000004 /* This board permits TX Power Control to be enabled */
2773 +
2774 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
2775 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
2776 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
2777 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
2778 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
2779 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
2780 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
2781 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
2782 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
2783 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
2784 +
2785 +/* power control defines */
2786 +#define PLL_DELAY 150 /* us pll on delay */
2787 +#define FREF_DELAY 200 /* us fref change delay */
2788 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
2789 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
2790 +
2791 +/* Reference Board Types */
2792 +
2793 +#define BU4710_BOARD 0x0400
2794 +#define VSIM4710_BOARD 0x0401
2795 +#define QT4710_BOARD 0x0402
2796 +
2797 +#define BU4309_BOARD 0x040a
2798 +#define BCM94309CB_BOARD 0x040b
2799 +#define BCM94309MP_BOARD 0x040c
2800 +#define BCM4309AP_BOARD 0x040d
2801 +
2802 +#define BCM94302MP_BOARD 0x040e
2803 +
2804 +#define BU4306_BOARD 0x0416
2805 +#define BCM94306CB_BOARD 0x0417
2806 +#define BCM94306MP_BOARD 0x0418
2807 +
2808 +#define BCM94710D_BOARD 0x041a
2809 +#define BCM94710R1_BOARD 0x041b
2810 +#define BCM94710R4_BOARD 0x041c
2811 +#define BCM94710AP_BOARD 0x041d
2812 +
2813 +#define BU2050_BOARD 0x041f
2814 +
2815 +
2816 +#define BCM94309G_BOARD 0x0421
2817 +
2818 +#define BU4704_BOARD 0x0423
2819 +#define BU4702_BOARD 0x0424
2820 +
2821 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
2822 +
2823 +
2824 +#define BCM94702MN_BOARD 0x0428
2825 +
2826 +/* BCM4702 1U CompactPCI Board */
2827 +#define BCM94702CPCI_BOARD 0x0429
2828 +
2829 +/* BCM4702 with BCM95380 VLAN Router */
2830 +#define BCM95380RR_BOARD 0x042a
2831 +
2832 +/* cb4306 with SiGe PA */
2833 +#define BCM94306CBSG_BOARD 0x042b
2834 +
2835 +/* cb4306 with SiGe PA */
2836 +#define PCSG94306_BOARD 0x042d
2837 +
2838 +/* bu4704 with sdram */
2839 +#define BU4704SD_BOARD 0x042e
2840 +
2841 +/* Dual 11a/11g Router */
2842 +#define BCM94704AGR_BOARD 0x042f
2843 +
2844 +/* 11a-only minipci */
2845 +#define BCM94308MP_BOARD 0x0430
2846 +
2847 +
2848 +
2849 +#define BU4712_BOARD 0x0444
2850 +#define BU4712SD_BOARD 0x045d
2851 +#define BU4712L_BOARD 0x045f
2852 +
2853 +/* BCM4712 boards */
2854 +#define BCM94712AP_BOARD 0x0445
2855 +#define BCM94712P_BOARD 0x0446
2856 +
2857 +/* BCM4318 boards */
2858 +#define BU4318_BOARD 0x0447
2859 +#define CB4318_BOARD 0x0448
2860 +#define MPG4318_BOARD 0x0449
2861 +#define MP4318_BOARD 0x044a
2862 +#define SD4318_BOARD 0x044b
2863 +
2864 +/* BCM63XX boards */
2865 +#define BCM96338_BOARD 0x6338
2866 +#define BCM96348_BOARD 0x6348
2867 +
2868 +/* Another mp4306 with SiGe */
2869 +#define BCM94306P_BOARD 0x044c
2870 +
2871 +/* mp4303 */
2872 +#define BCM94303MP_BOARD 0x044e
2873 +
2874 +/* mpsgh4306 */
2875 +#define BCM94306MPSGH_BOARD 0x044f
2876 +
2877 +/* BRCM 4306 w/ Front End Modules */
2878 +#define BCM94306MPM 0x0450
2879 +#define BCM94306MPL 0x0453
2880 +
2881 +/* 4712agr */
2882 +#define BCM94712AGR_BOARD 0x0451
2883 +
2884 +/* pcmcia 4303 */
2885 +#define PC4303_BOARD 0x0454
2886 +
2887 +/* 5350K */
2888 +#define BCM95350K_BOARD 0x0455
2889 +
2890 +/* 5350R */
2891 +#define BCM95350R_BOARD 0x0456
2892 +
2893 +/* 4306mplna */
2894 +#define BCM94306MPLNA_BOARD 0x0457
2895 +
2896 +/* 4320 boards */
2897 +#define BU4320_BOARD 0x0458
2898 +#define BU4320S_BOARD 0x0459
2899 +#define BCM94320PH_BOARD 0x045a
2900 +
2901 +/* 4306mph */
2902 +#define BCM94306MPH_BOARD 0x045b
2903 +
2904 +/* 4306pciv */
2905 +#define BCM94306PCIV_BOARD 0x045c
2906 +
2907 +#define BU4712SD_BOARD 0x045d
2908 +
2909 +#define BCM94320PFLSH_BOARD 0x045e
2910 +
2911 +#define BU4712L_BOARD 0x045f
2912 +#define BCM94712LGR_BOARD 0x0460
2913 +#define BCM94320R_BOARD 0x0461
2914 +
2915 +#define BU5352_BOARD 0x0462
2916 +
2917 +#define BCM94318MPGH_BOARD 0x0463
2918 +
2919 +#define BU4311_BOARD 0x0464
2920 +#define BCM94311MC_BOARD 0x0465
2921 +#define BCM94311MCAG_BOARD 0x0466
2922 +
2923 +#define BCM95352GR_BOARD 0x0467
2924 +
2925 +/* bcm95351agr */
2926 +#define BCM95351AGR_BOARD 0x0470
2927 +
2928 +/* bcm94704mpcb */
2929 +#define BCM94704MPCB_BOARD 0x0472
2930 +
2931 +/* 4785 boards */
2932 +#define BU4785_BOARD 0x0478
2933 +
2934 +/* 4321 boards */
2935 +#define BU4321_BOARD 0x046b
2936 +#define BU4321E_BOARD 0x047c
2937 +#define MP4321_BOARD 0x046c
2938 +#define CB2_4321_BOARD 0x046d
2939 +#define MC4321_BOARD 0x046e
2940 +
2941 +/* # of GPIO pins */
2942 +#define GPIO_NUMPINS 16
2943 +
2944 +/* radio ID codes */
2945 +#define NORADIO_ID 0xe4f5
2946 +#define NORADIO_IDCODE 0x4e4f5246
2947 +
2948 +#define BCM2050_ID 0x2050
2949 +#define BCM2050_IDCODE 0x02050000
2950 +#define BCM2050A0_IDCODE 0x1205017f
2951 +#define BCM2050A1_IDCODE 0x2205017f
2952 +#define BCM2050R8_IDCODE 0x8205017f
2953 +
2954 +#define BCM2055_ID 0x2055
2955 +#define BCM2055_IDCODE 0x02055000
2956 +#define BCM2055A0_IDCODE 0x1205517f
2957 +
2958 +#define BCM2060_ID 0x2060
2959 +#define BCM2060_IDCODE 0x02060000
2960 +#define BCM2060WW_IDCODE 0x1206017f
2961 +
2962 +#define BCM2062_ID 0x2062
2963 +#define BCM2062_IDCODE 0x02062000
2964 +#define BCM2062A0_IDCODE 0x0206217f
2965 +
2966 +/* parts of an idcode: */
2967 +#define IDCODE_MFG_MASK 0x00000fff
2968 +#define IDCODE_MFG_SHIFT 0
2969 +#define IDCODE_ID_MASK 0x0ffff000
2970 +#define IDCODE_ID_SHIFT 12
2971 +#define IDCODE_REV_MASK 0xf0000000
2972 +#define IDCODE_REV_SHIFT 28
2973 +
2974 +#endif /* _BCMDEVS_H */
2975 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs1.h linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h
2976 --- linux.old/arch/mips/bcm947xx/include/bcmdevs1.h 1970-01-01 01:00:00.000000000 +0100
2977 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs1.h 2006-05-02 04:32:03.000000000 +0200
2978 @@ -0,0 +1,391 @@
2979 +/*
2980 + * Broadcom device-specific manifest constants.
2981 + *
2982 + * Copyright 2005, Broadcom Corporation
2983 + * All Rights Reserved.
2984 + *
2985 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2986 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2987 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2988 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2989 + * $Id$
2990 + */
2991 +
2992 +#ifndef _BCMDEVS_H
2993 +#define _BCMDEVS_H
2994 +
2995 +
2996 +/* Known PCI vendor Id's */
2997 +#define VENDOR_EPIGRAM 0xfeda
2998 +#define VENDOR_BROADCOM 0x14e4
2999 +#define VENDOR_3COM 0x10b7
3000 +#define VENDOR_NETGEAR 0x1385
3001 +#define VENDOR_DIAMOND 0x1092
3002 +#define VENDOR_DELL 0x1028
3003 +#define VENDOR_HP 0x0e11
3004 +#define VENDOR_APPLE 0x106b
3005 +
3006 +/* PCI Device Id's */
3007 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
3008 +#define BCM4211_DEVICE_ID 0x4211
3009 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
3010 +#define BCM4231_DEVICE_ID 0x4231
3011 +
3012 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
3013 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
3014 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
3015 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
3016 +
3017 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
3018 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
3019 +
3020 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
3021 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
3022 +
3023 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
3024 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
3025 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
3026 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
3027 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
3028 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
3029 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
3030 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
3031 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
3032 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
3033 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
3034 +
3035 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
3036 +
3037 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
3038 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
3039 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
3040 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
3041 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
3042 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
3043 +
3044 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
3045 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
3046 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
3047 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
3048 +
3049 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
3050 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
3051 +
3052 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
3053 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
3054 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
3055 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
3056 +
3057 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
3058 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
3059 +#define BCM4306_D11G_ID2 0x4325
3060 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
3061 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
3062 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
3063 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
3064 +
3065 +#define BCM4309_PKG_ID 1 /* 4309 package id */
3066 +
3067 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
3068 +#define BCM4303_PKG_ID 2 /* 4303 package id */
3069 +
3070 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
3071 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
3072 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
3073 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
3074 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
3075 +
3076 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
3077 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
3078 +
3079 +
3080 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
3081 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
3082 +
3083 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
3084 +
3085 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
3086 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
3087 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
3088 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
3089 +
3090 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
3091 +
3092 +/* Address map */
3093 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
3094 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
3095 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
3096 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
3097 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
3098 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
3099 +
3100 +/* Core register space */
3101 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
3102 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
3103 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
3104 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
3105 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
3106 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
3107 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
3108 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
3109 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
3110 +
3111 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
3112 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
3113 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
3114 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
3115 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
3116 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
3117 +
3118 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
3119 +
3120 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
3121 +
3122 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
3123 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
3124 +
3125 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
3126 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
3127 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
3128 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
3129 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
3130 +
3131 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
3132 +
3133 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
3134 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
3135 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
3136 +
3137 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
3138 +
3139 +/* PCMCIA vendor Id's */
3140 +
3141 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
3142 +
3143 +/* SDIO vendor Id's */
3144 +#define VENDOR_BROADCOM_SDIO 0x00BF
3145 +
3146 +
3147 +/* boardflags */
3148 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
3149 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
3150 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
3151 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
3152 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
3153 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
3154 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
3155 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
3156 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
3157 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
3158 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
3159 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
3160 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
3161 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
3162 +
3163 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
3164 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
3165 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
3166 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
3167 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
3168 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
3169 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
3170 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
3171 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
3172 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
3173 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
3174 +
3175 +/* Bus types */
3176 +#define SB_BUS 0 /* Silicon Backplane */
3177 +#define PCI_BUS 1 /* PCI target */
3178 +#define PCMCIA_BUS 2 /* PCMCIA target */
3179 +#define SDIO_BUS 3 /* SDIO target */
3180 +#define JTAG_BUS 4 /* JTAG */
3181 +
3182 +/* Allows optimization for single-bus support */
3183 +#ifdef BCMBUSTYPE
3184 +#define BUSTYPE(bus) (BCMBUSTYPE)
3185 +#else
3186 +#define BUSTYPE(bus) (bus)
3187 +#endif
3188 +
3189 +/* power control defines */
3190 +#define PLL_DELAY 150 /* us pll on delay */
3191 +#define FREF_DELAY 200 /* us fref change delay */
3192 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
3193 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
3194 +
3195 +/* Reference Board Types */
3196 +
3197 +#define BU4710_BOARD 0x0400
3198 +#define VSIM4710_BOARD 0x0401
3199 +#define QT4710_BOARD 0x0402
3200 +
3201 +#define BU4610_BOARD 0x0403
3202 +#define VSIM4610_BOARD 0x0404
3203 +
3204 +#define BU4307_BOARD 0x0405
3205 +#define BCM94301CB_BOARD 0x0406
3206 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
3207 +#define BCM94301MP_BOARD 0x0407
3208 +#define BCM94307MP_BOARD 0x0408
3209 +#define BCMAP4307_BOARD 0x0409
3210 +
3211 +#define BU4309_BOARD 0x040a
3212 +#define BCM94309CB_BOARD 0x040b
3213 +#define BCM94309MP_BOARD 0x040c
3214 +#define BCM4309AP_BOARD 0x040d
3215 +
3216 +#define BCM94302MP_BOARD 0x040e
3217 +
3218 +#define VSIM4310_BOARD 0x040f
3219 +#define BU4711_BOARD 0x0410
3220 +#define BCM94310U_BOARD 0x0411
3221 +#define BCM94310AP_BOARD 0x0412
3222 +#define BCM94310MP_BOARD 0x0414
3223 +
3224 +#define BU4306_BOARD 0x0416
3225 +#define BCM94306CB_BOARD 0x0417
3226 +#define BCM94306MP_BOARD 0x0418
3227 +
3228 +#define BCM94710D_BOARD 0x041a
3229 +#define BCM94710R1_BOARD 0x041b
3230 +#define BCM94710R4_BOARD 0x041c
3231 +#define BCM94710AP_BOARD 0x041d
3232 +
3233 +
3234 +#define BU2050_BOARD 0x041f
3235 +
3236 +
3237 +#define BCM94309G_BOARD 0x0421
3238 +
3239 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
3240 +
3241 +#define BU4704_BOARD 0x0423
3242 +#define BU4702_BOARD 0x0424
3243 +
3244 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
3245 +
3246 +#define BU4317_BOARD 0x0426
3247 +
3248 +
3249 +#define BCM94702MN_BOARD 0x0428
3250 +
3251 +/* BCM4702 1U CompactPCI Board */
3252 +#define BCM94702CPCI_BOARD 0x0429
3253 +
3254 +/* BCM4702 with BCM95380 VLAN Router */
3255 +#define BCM95380RR_BOARD 0x042a
3256 +
3257 +/* cb4306 with SiGe PA */
3258 +#define BCM94306CBSG_BOARD 0x042b
3259 +
3260 +/* mp4301 with 2050 radio */
3261 +#define BCM94301MPL_BOARD 0x042c
3262 +
3263 +/* cb4306 with SiGe PA */
3264 +#define PCSG94306_BOARD 0x042d
3265 +
3266 +/* bu4704 with sdram */
3267 +#define BU4704SD_BOARD 0x042e
3268 +
3269 +/* Dual 11a/11g Router */
3270 +#define BCM94704AGR_BOARD 0x042f
3271 +
3272 +/* 11a-only minipci */
3273 +#define BCM94308MP_BOARD 0x0430
3274 +
3275 +
3276 +
3277 +/* BCM94317 boards */
3278 +#define BCM94317CB_BOARD 0x0440
3279 +#define BCM94317MP_BOARD 0x0441
3280 +#define BCM94317PCMCIA_BOARD 0x0442
3281 +#define BCM94317SDIO_BOARD 0x0443
3282 +
3283 +#define BU4712_BOARD 0x0444
3284 +#define BU4712SD_BOARD 0x045d
3285 +#define BU4712L_BOARD 0x045f
3286 +
3287 +/* BCM4712 boards */
3288 +#define BCM94712AP_BOARD 0x0445
3289 +#define BCM94712P_BOARD 0x0446
3290 +
3291 +/* BCM4318 boards */
3292 +#define BU4318_BOARD 0x0447
3293 +#define CB4318_BOARD 0x0448
3294 +#define MPG4318_BOARD 0x0449
3295 +#define MP4318_BOARD 0x044a
3296 +#define SD4318_BOARD 0x044b
3297 +
3298 +/* BCM63XX boards */
3299 +#define BCM96338_BOARD 0x6338
3300 +#define BCM96345_BOARD 0x6345
3301 +#define BCM96348_BOARD 0x6348
3302 +
3303 +/* Another mp4306 with SiGe */
3304 +#define BCM94306P_BOARD 0x044c
3305 +
3306 +/* CF-like 4317 modules */
3307 +#define BCM94317CF_BOARD 0x044d
3308 +
3309 +/* mp4303 */
3310 +#define BCM94303MP_BOARD 0x044e
3311 +
3312 +/* mpsgh4306 */
3313 +#define BCM94306MPSGH_BOARD 0x044f
3314 +
3315 +/* BRCM 4306 w/ Front End Modules */
3316 +#define BCM94306MPM 0x0450
3317 +#define BCM94306MPL 0x0453
3318 +
3319 +/* 4712agr */
3320 +#define BCM94712AGR_BOARD 0x0451
3321 +
3322 +/* The real CF 4317 board */
3323 +#define CFI4317_BOARD 0x0452
3324 +
3325 +/* pcmcia 4303 */
3326 +#define PC4303_BOARD 0x0454
3327 +
3328 +/* 5350K */
3329 +#define BCM95350K_BOARD 0x0455
3330 +
3331 +/* 5350R */
3332 +#define BCM95350R_BOARD 0x0456
3333 +
3334 +/* 4306mplna */
3335 +#define BCM94306MPLNA_BOARD 0x0457
3336 +
3337 +/* 4320 boards */
3338 +#define BU4320_BOARD 0x0458
3339 +#define BU4320S_BOARD 0x0459
3340 +#define BCM94320PH_BOARD 0x045a
3341 +
3342 +/* 4306mph */
3343 +#define BCM94306MPH_BOARD 0x045b
3344 +
3345 +/* 4306pciv */
3346 +#define BCM94306PCIV_BOARD 0x045c
3347 +
3348 +#define BU4712SD_BOARD 0x045d
3349 +
3350 +#define BCM94320PFLSH_BOARD 0x045e
3351 +
3352 +#define BU4712L_BOARD 0x045f
3353 +#define BCM94712LGR_BOARD 0x0460
3354 +#define BCM94320R_BOARD 0x0461
3355 +
3356 +#define BU5352_BOARD 0x0462
3357 +
3358 +#define BCM94318MPGH_BOARD 0x0463
3359 +
3360 +
3361 +#define BCM95352GR_BOARD 0x0467
3362 +
3363 +/* bcm95351agr */
3364 +#define BCM95351AGR_BOARD 0x0470
3365 +
3366 +/* # of GPIO pins */
3367 +#define GPIO_NUMPINS 16
3368 +
3369 +#endif /* _BCMDEVS_H */
3370 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
3371 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
3372 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2006-04-27 20:08:35.000000000 +0200
3373 @@ -0,0 +1,198 @@
3374 +/*
3375 + * local version of endian.h - byte order defines
3376 + *
3377 + * Copyright 2006, Broadcom Corporation
3378 + * All Rights Reserved.
3379 + *
3380 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3381 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3382 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3383 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3384 + *
3385 + * $Id: bcmendian.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
3386 +*/
3387 +
3388 +#ifndef _BCMENDIAN_H_
3389 +#define _BCMENDIAN_H_
3390 +
3391 +#include <typedefs.h>
3392 +
3393 +/* Byte swap a 16 bit value */
3394 +#define BCMSWAP16(val) \
3395 + ((uint16)(\
3396 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
3397 + (((uint16)(val) & (uint16)0xff00U) >> 8)))
3398 +
3399 +/* Byte swap a 32 bit value */
3400 +#define BCMSWAP32(val) \
3401 + ((uint32)(\
3402 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
3403 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
3404 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
3405 + (((uint32)(val) & (uint32)0xff000000UL) >> 24)))
3406 +
3407 +/* 2 Byte swap a 32 bit value */
3408 +#define BCMSWAP32BY16(val) \
3409 + ((uint32)(\
3410 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
3411 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16)))
3412 +
3413 +
3414 +static INLINE uint16
3415 +bcmswap16(uint16 val)
3416 +{
3417 + return BCMSWAP16(val);
3418 +}
3419 +
3420 +static INLINE uint32
3421 +bcmswap32(uint32 val)
3422 +{
3423 + return BCMSWAP32(val);
3424 +}
3425 +
3426 +static INLINE uint32
3427 +bcmswap32by16(uint32 val)
3428 +{
3429 + return BCMSWAP32BY16(val);
3430 +}
3431 +
3432 +/* buf - start of buffer of shorts to swap */
3433 +/* len - byte length of buffer */
3434 +static INLINE void
3435 +bcmswap16_buf(uint16 *buf, uint len)
3436 +{
3437 + len = len/2;
3438 +
3439 + while (len--) {
3440 + *buf = bcmswap16(*buf);
3441 + buf++;
3442 + }
3443 +}
3444 +
3445 +#ifndef hton16
3446 +#ifndef IL_BIGENDIAN
3447 +#define HTON16(i) BCMSWAP16(i)
3448 +#define hton16(i) bcmswap16(i)
3449 +#define hton32(i) bcmswap32(i)
3450 +#define ntoh16(i) bcmswap16(i)
3451 +#define ntoh32(i) bcmswap32(i)
3452 +#define ltoh16(i) (i)
3453 +#define ltoh32(i) (i)
3454 +#define htol16(i) (i)
3455 +#define htol32(i) (i)
3456 +#else
3457 +#define HTON16(i) (i)
3458 +#define hton16(i) (i)
3459 +#define hton32(i) (i)
3460 +#define ntoh16(i) (i)
3461 +#define ntoh32(i) (i)
3462 +#define ltoh16(i) bcmswap16(i)
3463 +#define ltoh32(i) bcmswap32(i)
3464 +#define htol16(i) bcmswap16(i)
3465 +#define htol32(i) bcmswap32(i)
3466 +#endif /* IL_BIGENDIAN */
3467 +#endif /* hton16 */
3468 +
3469 +#ifndef IL_BIGENDIAN
3470 +#define ltoh16_buf(buf, i)
3471 +#define htol16_buf(buf, i)
3472 +#else
3473 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3474 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
3475 +#endif /* IL_BIGENDIAN */
3476 +
3477 +/*
3478 +* store 16-bit value to unaligned little endian byte array.
3479 +*/
3480 +static INLINE void
3481 +htol16_ua_store(uint16 val, uint8 *bytes)
3482 +{
3483 + bytes[0] = val&0xff;
3484 + bytes[1] = val>>8;
3485 +}
3486 +
3487 +/*
3488 +* store 32-bit value to unaligned little endian byte array.
3489 +*/
3490 +static INLINE void
3491 +htol32_ua_store(uint32 val, uint8 *bytes)
3492 +{
3493 + bytes[0] = val&0xff;
3494 + bytes[1] = (val>>8)&0xff;
3495 + bytes[2] = (val>>16)&0xff;
3496 + bytes[3] = val>>24;
3497 +}
3498 +
3499 +/*
3500 +* store 16-bit value to unaligned network(big) endian byte array.
3501 +*/
3502 +static INLINE void
3503 +hton16_ua_store(uint16 val, uint8 *bytes)
3504 +{
3505 + bytes[1] = val&0xff;
3506 + bytes[0] = val>>8;
3507 +}
3508 +
3509 +/*
3510 +* store 32-bit value to unaligned network(big) endian byte array.
3511 +*/
3512 +static INLINE void
3513 +hton32_ua_store(uint32 val, uint8 *bytes)
3514 +{
3515 + bytes[3] = val&0xff;
3516 + bytes[2] = (val>>8)&0xff;
3517 + bytes[1] = (val>>16)&0xff;
3518 + bytes[0] = val>>24;
3519 +}
3520 +
3521 +/*
3522 +* load 16-bit value from unaligned little endian byte array.
3523 +*/
3524 +static INLINE uint16
3525 +ltoh16_ua(void *bytes)
3526 +{
3527 + return (((uint8*)bytes)[1]<<8)+((uint8 *)bytes)[0];
3528 +}
3529 +
3530 +/*
3531 +* load 32-bit value from unaligned little endian byte array.
3532 +*/
3533 +static INLINE uint32
3534 +ltoh32_ua(void *bytes)
3535 +{
3536 + return (((uint8*)bytes)[3]<<24)+(((uint8*)bytes)[2]<<16)+
3537 + (((uint8*)bytes)[1]<<8)+((uint8*)bytes)[0];
3538 +}
3539 +
3540 +/*
3541 +* load 16-bit value from unaligned big(network) endian byte array.
3542 +*/
3543 +static INLINE uint16
3544 +ntoh16_ua(void *bytes)
3545 +{
3546 + return (((uint8*)bytes)[0]<<8)+((uint8*)bytes)[1];
3547 +}
3548 +
3549 +/*
3550 +* load 32-bit value from unaligned big(network) endian byte array.
3551 +*/
3552 +static INLINE uint32
3553 +ntoh32_ua(void *bytes)
3554 +{
3555 + return (((uint8*)bytes)[0]<<24)+(((uint8*)bytes)[1]<<16)+
3556 + (((uint8*)bytes)[2]<<8)+((uint8*)bytes)[3];
3557 +}
3558 +
3559 +#define ltoh_ua(ptr) (\
3560 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3561 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
3562 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
3563 +)
3564 +
3565 +#define ntoh_ua(ptr) (\
3566 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
3567 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
3568 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
3569 +)
3570 +
3571 +#endif /* _BCMENDIAN_H_ */
3572 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
3573 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
3574 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2006-04-27 23:29:18.000000000 +0200
3575 @@ -0,0 +1,159 @@
3576 +/*
3577 + * NVRAM variable manipulation
3578 + *
3579 + * Copyright 2006, Broadcom Corporation
3580 + * All Rights Reserved.
3581 + *
3582 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3583 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3584 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3585 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3586 + *
3587 + * $Id: bcmnvram.h,v 1.17 2006/03/02 12:33:44 honor Exp $
3588 + */
3589 +
3590 +#ifndef _bcmnvram_h_
3591 +#define _bcmnvram_h_
3592 +
3593 +#ifndef _LANGUAGE_ASSEMBLY
3594 +
3595 +#include <typedefs.h>
3596 +#include <bcmdefs.h>
3597 +
3598 +struct nvram_header {
3599 + uint32 magic;
3600 + uint32 len;
3601 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
3602 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
3603 + uint32 config_ncdl; /* ncdl values for memc */
3604 +};
3605 +
3606 +struct nvram_tuple {
3607 + char *name;
3608 + char *value;
3609 + struct nvram_tuple *next;
3610 +};
3611 +
3612 +/*
3613 + * Initialize NVRAM access. May be unnecessary or undefined on certain
3614 + * platforms.
3615 + */
3616 +extern int nvram_init(void *sbh);
3617 +
3618 +/*
3619 + * Disable NVRAM access. May be unnecessary or undefined on certain
3620 + * platforms.
3621 + */
3622 +extern void nvram_exit(void *sbh);
3623 +
3624 +/*
3625 + * Get the value of an NVRAM variable. The pointer returned may be
3626 + * invalid after a set.
3627 + * @param name name of variable to get
3628 + * @return value of variable or NULL if undefined
3629 + */
3630 +extern char * nvram_get(const char *name);
3631 +
3632 +/*
3633 + * Read the reset GPIO value from the nvram and set the GPIO
3634 + * as input
3635 + */
3636 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
3637 +extern int BCMINITFN(nvram_gpio_init)(const char *name, void *sbh);
3638 +extern int BCMINITFN(nvram_gpio_set)(const char *name, void *sbh, int type);
3639 +
3640 +/*
3641 + * Get the value of an NVRAM variable.
3642 + * @param name name of variable to get
3643 + * @return value of variable or NUL if undefined
3644 + */
3645 +#define nvram_safe_get(name) (nvram_get(name) ? : "")
3646 +
3647 +#define nvram_safe_unset(name) ({ \
3648 + if(nvram_get(name)) \
3649 + nvram_unset(name); \
3650 +})
3651 +
3652 +#define nvram_safe_set(name, value) ({ \
3653 + if(!nvram_get(name) || strcmp(nvram_get(name), value)) \
3654 + nvram_set(name, value); \
3655 +})
3656 +
3657 +/*
3658 + * Match an NVRAM variable.
3659 + * @param name name of variable to match
3660 + * @param match value to compare against value of variable
3661 + * @return TRUE if variable is defined and its value is string equal
3662 + * to match or FALSE otherwise
3663 + */
3664 +static INLINE int
3665 +nvram_match(char *name, char *match) {
3666 + const char *value = nvram_get(name);
3667 + return (value && !strcmp(value, match));
3668 +}
3669 +
3670 +/*
3671 + * Inversely match an NVRAM variable.
3672 + * @param name name of variable to match
3673 + * @param match value to compare against value of variable
3674 + * @return TRUE if variable is defined and its value is not string
3675 + * equal to invmatch or FALSE otherwise
3676 + */
3677 +static INLINE int
3678 +nvram_invmatch(char *name, char *invmatch) {
3679 + const char *value = nvram_get(name);
3680 + return (value && strcmp(value, invmatch));
3681 +}
3682 +
3683 +/*
3684 + * Set the value of an NVRAM variable. The name and value strings are
3685 + * copied into private storage. Pointers to previously set values
3686 + * may become invalid. The new value may be immediately
3687 + * retrieved but will not be permanently stored until a commit.
3688 + * @param name name of variable to set
3689 + * @param value value of variable
3690 + * @return 0 on success and errno on failure
3691 + */
3692 +extern int nvram_set(const char *name, const char *value);
3693 +
3694 +/*
3695 + * Unset an NVRAM variable. Pointers to previously set values
3696 + * remain valid until a set.
3697 + * @param name name of variable to unset
3698 + * @return 0 on success and errno on failure
3699 + * NOTE: use nvram_commit to commit this change to flash.
3700 + */
3701 +extern int nvram_unset(const char *name);
3702 +
3703 +/*
3704 + * Commit NVRAM variables to permanent storage. All pointers to values
3705 + * may be invalid after a commit.
3706 + * NVRAM values are undefined after a commit.
3707 + * @return 0 on success and errno on failure
3708 + */
3709 +extern int nvram_commit(void);
3710 +
3711 +/*
3712 + * Get all NVRAM variables (format name=value\0 ... \0\0).
3713 + * @param buf buffer to store variables
3714 + * @param count size of buffer in bytes
3715 + * @return 0 on success and errno on failure
3716 + */
3717 +extern int nvram_getall(char *buf, int count);
3718 +
3719 +extern int file2nvram(char *filename, char *varname);
3720 +extern int nvram2file(char *varname, char *filename);
3721 +
3722 +#endif /* _LANGUAGE_ASSEMBLY */
3723 +
3724 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
3725 +#define NVRAM_CLEAR_MAGIC 0x0
3726 +#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
3727 +#define NVRAM_VERSION 1
3728 +#define NVRAM_HEADER_SIZE 20
3729 +#define NVRAM_SPACE 0x8000
3730 +
3731 +#define NVRAM_MAX_VALUE_LEN 255
3732 +#define NVRAM_MAX_PARAM_LEN 64
3733 +
3734 +#endif /* _bcmnvram_h_ */
3735 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
3736 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
3737 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2006-04-27 20:27:33.000000000 +0200
3738 @@ -0,0 +1,108 @@
3739 +/*
3740 + * Misc useful routines to access NIC local SROM/OTP .
3741 + *
3742 + * Copyright 2006, Broadcom Corporation
3743 + * All Rights Reserved.
3744 + *
3745 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3746 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3747 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3748 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3749 + *
3750 + * $Id: bcmsrom.h,v 1.1.1.13 2006/04/15 01:29:08 michael Exp $
3751 + */
3752 +
3753 +#ifndef _bcmsrom_h_
3754 +#define _bcmsrom_h_
3755 +
3756 +/* Maximum srom: 4 Kilobits == 512 bytes */
3757 +#define SROM_MAX 512
3758 +
3759 +/* SROM Rev 4: Reallocate the software part of the srom to accomodate
3760 + * MIMO features. It assumes up to two PCIE functions and 440 bytes
3761 + * of useable srom i.e. the useable storage in chips with OTP that
3762 + * implements hardware redundancy.
3763 + */
3764 +
3765 +#define SROM4_WORDS 220
3766 +
3767 +#define SROM4_SIGN 32
3768 +#define SROM4_SIGNATURE 0x5372
3769 +
3770 +#define SROM4_BREV 33
3771 +
3772 +#define SROM4_BFL0 34
3773 +#define SROM4_BFL1 35
3774 +#define SROM4_BFL2 36
3775 +#define SROM4_BFL3 37
3776 +
3777 +#define SROM4_MACHI 38
3778 +#define SROM4_MACMID 39
3779 +#define SROM4_MACLO 40
3780 +
3781 +#define SROM4_CCODE 41
3782 +#define SROM4_REGREV 42
3783 +
3784 +#define SROM4_LEDBH10 43
3785 +#define SROM4_LEDBH32 44
3786 +
3787 +#define SROM4_LEDDC 45
3788 +
3789 +#define SROM4_AA 46
3790 +#define SROM4_AA2G_MASK 0x00ff
3791 +#define SROM4_AA2G_SHIFT 0
3792 +#define SROM4_AA5G_MASK 0xff00
3793 +#define SROM4_AA5G_SHIFT 8
3794 +
3795 +#define SROM4_AG10 47
3796 +#define SROM4_AG32 48
3797 +
3798 +#define SROM4_TXPID2G 49
3799 +#define SROM4_TXPID5G 51
3800 +#define SROM4_TXPID5GL 53
3801 +#define SROM4_TXPID5GH 55
3802 +
3803 +/* Per-path fields */
3804 +#define MAX_PATH 4
3805 +#define SROM4_PATH0 64
3806 +#define SROM4_PATH1 87
3807 +#define SROM4_PATH2 110
3808 +#define SROM4_PATH3 133
3809 +
3810 +#define SROM4_2G_ITT_MAXP 0
3811 +#define SROM4_2G_PA 1
3812 +#define SROM4_5G_ITT_MAXP 5
3813 +#define SROM4_5GLH_MAXP 6
3814 +#define SROM4_5G_PA 7
3815 +#define SROM4_5GL_PA 11
3816 +#define SROM4_5GH_PA 15
3817 +
3818 +/* Fields in the ITT_MAXP and 5GLH_MAXP words */
3819 +#define B2G_MAXP_MASK 0xff
3820 +#define B2G_ITT_SHIFT 8
3821 +#define B5G_MAXP_MASK 0xff
3822 +#define B5G_ITT_SHIFT 8
3823 +#define B5GH_MAXP_MASK 0xff
3824 +#define B5GL_MAXP_SHIFT 8
3825 +
3826 +/* All the miriad power offsets */
3827 +#define SROM4_2G_CCKPO 156
3828 +#define SROM4_2G_OFDMPO 157
3829 +#define SROM4_5G_OFDMPO 159
3830 +#define SROM4_5GL_OFDMPO 161
3831 +#define SROM4_5GH_OFDMPO 163
3832 +#define SROM4_2G_MCSPO 165
3833 +#define SROM4_5G_MCSPO 173
3834 +#define SROM4_5GL_MCSPO 181
3835 +#define SROM4_5GH_MCSPO 189
3836 +#define SROM4_CCDPO 197
3837 +#define SROM4_STBCPO 198
3838 +#define SROM4_BW40PO 199
3839 +#define SROM4_BWDUPPO 200
3840 +
3841 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, uint *count);
3842 +
3843 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3844 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
3845 +
3846 +#endif /* _bcmsrom_h_ */
3847 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
3848 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
3849 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2006-05-02 01:52:12.000000000 +0200
3850 @@ -0,0 +1,433 @@
3851 +/*
3852 + * Misc useful os-independent macros and functions.
3853 + *
3854 + * Copyright 2006, Broadcom Corporation
3855 + * All Rights Reserved.
3856 + *
3857 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3858 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3859 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3860 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3861 + * $Id: bcmutils.h,v 1.1.1.16 2006/04/08 06:13:39 honor Exp $
3862 + */
3863 +
3864 +#ifndef _bcmutils_h_
3865 +#define _bcmutils_h_
3866 +
3867 +/* ** driver-only section ** */
3868 +#ifdef BCMDRIVER
3869 +
3870 +#define _BCM_U 0x01 /* upper */
3871 +#define _BCM_L 0x02 /* lower */
3872 +#define _BCM_D 0x04 /* digit */
3873 +#define _BCM_C 0x08 /* cntrl */
3874 +#define _BCM_P 0x10 /* punct */
3875 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
3876 +#define _BCM_X 0x40 /* hex digit */
3877 +#define _BCM_SP 0x80 /* hard space (0x20) */
3878 +
3879 +#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
3880 +
3881 +extern unsigned char bcm_ctype[];
3882 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
3883 +
3884 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
3885 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
3886 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
3887 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
3888 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
3889 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
3890 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
3891 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
3892 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
3893 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
3894 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
3895 +
3896 +/*
3897 + * Spin at most 'us' microseconds while 'exp' is true.
3898 + * Caller should explicitly test 'exp' when this completes
3899 + * and take appropriate error action if 'exp' is still true.
3900 + */
3901 +#define SPINWAIT(exp, us) { \
3902 + uint countdown = (us) + 9; \
3903 + while ((exp) && (countdown >= 10)) {\
3904 + OSL_DELAY(10); \
3905 + countdown -= 10; \
3906 + } \
3907 +}
3908 +
3909 +struct ether_addr {
3910 + uint8 octet[6];
3911 +} __attribute__((packed));
3912 +
3913 +/* string */
3914 +extern uchar bcm_toupper(uchar c);
3915 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
3916 +extern char *bcmstrstr(char *haystack, char *needle);
3917 +extern char *bcmstrcat(char *dest, const char *src);
3918 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
3919 +/* ethernet address */
3920 +extern char *bcm_ether_ntoa(struct ether_addr *ea, char *buf);
3921 +/* variable access */
3922 +extern char *getvar(char *vars, char *name);
3923 +extern int getintvar(char *vars, char *name);
3924 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
3925 +#ifdef BCMPERFSTATS
3926 +extern void bcm_perf_enable(void);
3927 +extern void bcmstats(char *fmt);
3928 +extern void bcmlog(char *fmt, uint a1, uint a2);
3929 +extern void bcmdumplog(char *buf, int size);
3930 +extern int bcmdumplogent(char *buf, uint idx);
3931 +#else
3932 +#define bcm_perf_enable()
3933 +#define bcmstats(fmt)
3934 +#define bcmlog(fmt, a1, a2)
3935 +#define bcmdumplog(buf, size) *buf = '\0'
3936 +#define bcmdumplogent(buf, idx) -1
3937 +#endif /* BCMPERFSTATS */
3938 +extern char *bcm_nvram_vars(uint *length);
3939 +extern int bcm_nvram_cache(void *sbh);
3940 +
3941 +/* Support for sharing code across in-driver iovar implementations.
3942 + * The intent is that a driver use this structure to map iovar names
3943 + * to its (private) iovar identifiers, and the lookup function to
3944 + * find the entry. Macros are provided to map ids and get/set actions
3945 + * into a single number space for a switch statement.
3946 + */
3947 +
3948 +/* iovar structure */
3949 +typedef struct bcm_iovar {
3950 + const char *name; /* name for lookup and display */
3951 + uint16 varid; /* id for switch */
3952 + uint16 flags; /* driver-specific flag bits */
3953 + uint16 type; /* base type of argument */
3954 + uint16 minlen; /* min length for buffer vars */
3955 +} bcm_iovar_t;
3956 +
3957 +/* varid definitions are per-driver, may use these get/set bits */
3958 +
3959 +/* IOVar action bits for id mapping */
3960 +#define IOV_GET 0 /* Get an iovar */
3961 +#define IOV_SET 1 /* Set an iovar */
3962 +
3963 +/* Varid to actionid mapping */
3964 +#define IOV_GVAL(id) ((id)*2)
3965 +#define IOV_SVAL(id) (((id)*2)+IOV_SET)
3966 +#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
3967 +
3968 +/* flags are per-driver based on driver attributes */
3969 +
3970 +/* Base type definitions */
3971 +#define IOVT_VOID 0 /* no value (implictly set only) */
3972 +#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
3973 +#define IOVT_INT8 2 /* integer values are range-checked */
3974 +#define IOVT_UINT8 3 /* unsigned int 8 bits */
3975 +#define IOVT_INT16 4 /* int 16 bits */
3976 +#define IOVT_UINT16 5 /* unsigned int 16 bits */
3977 +#define IOVT_INT32 6 /* int 32 bits */
3978 +#define IOVT_UINT32 7 /* unsigned int 32 bits */
3979 +#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
3980 +
3981 +extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
3982 +extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
3983 +
3984 +#endif /* #ifdef BCMDRIVER */
3985 +
3986 +/* ** driver/apps-shared section ** */
3987 +
3988 +#define BCME_STRLEN 64 /* Max string length for BCM errors */
3989 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
3990 +
3991 +
3992 +/*
3993 + * error codes could be added but the defined ones shouldn't be changed/deleted
3994 + * these error codes are exposed to the user code
3995 + * when ever a new error code is added to this list
3996 + * please update errorstring table with the related error string and
3997 + * update osl files with os specific errorcode map
3998 +*/
3999 +
4000 +#define BCME_OK 0 /* Success */
4001 +#define BCME_ERROR -1 /* Error generic */
4002 +#define BCME_BADARG -2 /* Bad Argument */
4003 +#define BCME_BADOPTION -3 /* Bad option */
4004 +#define BCME_NOTUP -4 /* Not up */
4005 +#define BCME_NOTDOWN -5 /* Not down */
4006 +#define BCME_NOTAP -6 /* Not AP */
4007 +#define BCME_NOTSTA -7 /* Not STA */
4008 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
4009 +#define BCME_RADIOOFF -9 /* Radio Off */
4010 +#define BCME_NOTBANDLOCKED -10 /* Not band locked */
4011 +#define BCME_NOCLK -11 /* No Clock */
4012 +#define BCME_BADRATESET -12 /* BAD Rate valueset */
4013 +#define BCME_BADBAND -13 /* BAD Band */
4014 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
4015 +#define BCME_BUFTOOLONG -15 /* Buffer too long */
4016 +#define BCME_BUSY -16 /* Busy */
4017 +#define BCME_NOTASSOCIATED -17 /* Not Associated */
4018 +#define BCME_BADSSIDLEN -18 /* Bad SSID len */
4019 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
4020 +#define BCME_BADCHAN -20 /* Bad Channel */
4021 +#define BCME_BADADDR -21 /* Bad Address */
4022 +#define BCME_NORESOURCE -22 /* Not Enough Resources */
4023 +#define BCME_UNSUPPORTED -23 /* Unsupported */
4024 +#define BCME_BADLEN -24 /* Bad length */
4025 +#define BCME_NOTREADY -25 /* Not Ready */
4026 +#define BCME_EPERM -26 /* Not Permitted */
4027 +#define BCME_NOMEM -27 /* No Memory */
4028 +#define BCME_ASSOCIATED -28 /* Associated */
4029 +#define BCME_RANGE -29 /* Not In Range */
4030 +#define BCME_NOTFOUND -30 /* Not Found */
4031 +#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
4032 +#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
4033 +#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
4034 +#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
4035 +#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
4036 +#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
4037 +#define BCME_LAST BCME_DONGLE_DOWN
4038 +
4039 +/* These are collection of BCME Error strings */
4040 +#define BCMERRSTRINGTABLE { \
4041 + "OK", \
4042 + "Undefined error", \
4043 + "Bad Argument", \
4044 + "Bad Option", \
4045 + "Not up", \
4046 + "Not down", \
4047 + "Not AP", \
4048 + "Not STA", \
4049 + "Bad Key Index", \
4050 + "Radio Off", \
4051 + "Not band locked", \
4052 + "No clock", \
4053 + "Bad Rate valueset", \
4054 + "Bad Band", \
4055 + "Buffer too short", \
4056 + "Buffer too long", \
4057 + "Busy", \
4058 + "Not Associated", \
4059 + "Bad SSID len", \
4060 + "Out of Range Channel", \
4061 + "Bad Channel", \
4062 + "Bad Address", \
4063 + "Not Enough Resources", \
4064 + "Unsupported", \
4065 + "Bad length", \
4066 + "Not Ready", \
4067 + "Not Permitted", \
4068 + "No Memory", \
4069 + "Associated", \
4070 + "Not In Range", \
4071 + "Not Found", \
4072 + "WME Not Enabled", \
4073 + "TSPEC Not Found", \
4074 + "ACM Not Supported", \
4075 + "Not WME Association", \
4076 + "SDIO Bus Error", \
4077 + "Dongle Not Accessible" \
4078 +}
4079 +
4080 +#ifndef ABS
4081 +#define ABS(a) (((a) < 0)?-(a):(a))
4082 +#endif /* ABS */
4083 +
4084 +#ifndef MIN
4085 +#define MIN(a, b) (((a) < (b))?(a):(b))
4086 +#endif /* MIN */
4087 +
4088 +#ifndef MAX
4089 +#define MAX(a, b) (((a) > (b))?(a):(b))
4090 +#endif /* MAX */
4091 +
4092 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
4093 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
4094 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
4095 +#define ISPOWEROF2(x) ((((x)-1)&(x)) == 0)
4096 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
4097 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
4098 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
4099 +
4100 +/* bit map related macros */
4101 +#ifndef setbit
4102 +#ifndef NBBY /* the BSD family defines NBBY */
4103 +#define NBBY 8 /* 8 bits per byte */
4104 +#endif /* #ifndef NBBY */
4105 +#define setbit(a, i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
4106 +#define clrbit(a, i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
4107 +#define isset(a, i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
4108 +#define isclr(a, i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
4109 +#endif /* setbit */
4110 +
4111 +#define NBITS(type) (sizeof(type) * 8)
4112 +#define NBITVAL(nbits) (1 << (nbits))
4113 +#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
4114 +#define NBITMASK(nbits) MAXBITVAL(nbits)
4115 +#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
4116 +
4117 +/* basic mux operation - can be optimized on several architectures */
4118 +#define MUX(pred, true, false) ((pred) ? (true) : (false))
4119 +
4120 +/* modulo inc/dec - assumes x E [0, bound - 1] */
4121 +#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
4122 +#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
4123 +
4124 +/* modulo inc/dec, bound = 2^k */
4125 +#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
4126 +#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
4127 +
4128 +/* modulo add/sub - assumes x, y E [0, bound - 1] */
4129 +#define MODADD(x, y, bound) \
4130 + MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
4131 +#define MODSUB(x, y, bound) \
4132 + MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
4133 +
4134 +/* module add/sub, bound = 2^k */
4135 +#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
4136 +#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
4137 +
4138 +/* crc defines */
4139 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
4140 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
4141 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
4142 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
4143 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
4144 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
4145 +
4146 +/* bcm_format_flags() bit description structure */
4147 +typedef struct bcm_bit_desc {
4148 + uint32 bit;
4149 + char* name;
4150 +} bcm_bit_desc_t;
4151 +
4152 +/* tag_ID/length/value_buffer tuple */
4153 +typedef struct bcm_tlv {
4154 + uint8 id;
4155 + uint8 len;
4156 + uint8 data[1];
4157 +} bcm_tlv_t;
4158 +
4159 +/* Check that bcm_tlv_t fits into the given buflen */
4160 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
4161 +
4162 +/* buffer length for ethernet address from bcm_ether_ntoa() */
4163 +#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
4164 +
4165 +/* unaligned load and store macros */
4166 +#ifdef IL_BIGENDIAN
4167 +static INLINE uint32
4168 +load32_ua(uint8 *a)
4169 +{
4170 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
4171 +}
4172 +
4173 +static INLINE void
4174 +store32_ua(uint8 *a, uint32 v)
4175 +{
4176 + a[0] = (v >> 24) & 0xff;
4177 + a[1] = (v >> 16) & 0xff;
4178 + a[2] = (v >> 8) & 0xff;
4179 + a[3] = v & 0xff;
4180 +}
4181 +
4182 +static INLINE uint16
4183 +load16_ua(uint8 *a)
4184 +{
4185 + return ((a[0] << 8) | a[1]);
4186 +}
4187 +
4188 +static INLINE void
4189 +store16_ua(uint8 *a, uint16 v)
4190 +{
4191 + a[0] = (v >> 8) & 0xff;
4192 + a[1] = v & 0xff;
4193 +}
4194 +
4195 +#else
4196 +
4197 +static INLINE uint32
4198 +load32_ua(uint8 *a)
4199 +{
4200 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
4201 +}
4202 +
4203 +static INLINE void
4204 +store32_ua(uint8 *a, uint32 v)
4205 +{
4206 + a[3] = (v >> 24) & 0xff;
4207 + a[2] = (v >> 16) & 0xff;
4208 + a[1] = (v >> 8) & 0xff;
4209 + a[0] = v & 0xff;
4210 +}
4211 +
4212 +static INLINE uint16
4213 +load16_ua(uint8 *a)
4214 +{
4215 + return ((a[1] << 8) | a[0]);
4216 +}
4217 +
4218 +static INLINE void
4219 +store16_ua(uint8 *a, uint16 v)
4220 +{
4221 + a[1] = (v >> 8) & 0xff;
4222 + a[0] = v & 0xff;
4223 +}
4224 +
4225 +#endif /* IL_BIGENDIAN */
4226 +
4227 +/* externs */
4228 +/* crc */
4229 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
4230 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
4231 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
4232 +/* format/print */
4233 +extern void printfbig(char *buf);
4234 +
4235 +/* IE parsing */
4236 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
4237 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
4238 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
4239 +
4240 +/* bcmerror */
4241 +extern const char *bcmerrorstr(int bcmerror);
4242 +
4243 +/* multi-bool data type: set of bools, mbool is true if any is set */
4244 +typedef uint32 mbool;
4245 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
4246 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
4247 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
4248 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
4249 +
4250 +/* power conversion */
4251 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
4252 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
4253 +
4254 +/* generic datastruct to help dump routines */
4255 +struct fielddesc {
4256 + char *nameandfmt;
4257 + uint32 offset;
4258 + uint32 len;
4259 +};
4260 +
4261 +/* Buffer structure for collecting string-formatted data
4262 +* using bcm_bprintf() API.
4263 +* Use bcm_binit() to initialize before use
4264 +*/
4265 +struct bcmstrbuf
4266 +{
4267 + char *buf; /* pointer to current position in origbuf */
4268 + uint size; /* current (residual) size in bytes */
4269 + char *origbuf; /* unmodified pointer to orignal buffer */
4270 + uint origsize; /* unmodified orignal buffer size in bytes */
4271 +};
4272 +
4273 +extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
4274 +extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
4275 +
4276 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
4277 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str,
4278 + char *buf, uint32 bufsize);
4279 +
4280 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
4281 +extern uint bcm_bitcount(uint8 *bitmap, uint bytelength);
4282 +
4283 +#endif /* _bcmutils_h_ */
4284 diff -urN linux.old/arch/mips/bcm947xx/include/hndcpu.h linux.dev/arch/mips/bcm947xx/include/hndcpu.h
4285 --- linux.old/arch/mips/bcm947xx/include/hndcpu.h 1970-01-01 01:00:00.000000000 +0100
4286 +++ linux.dev/arch/mips/bcm947xx/include/hndcpu.h 2006-04-27 22:14:38.000000000 +0200
4287 @@ -0,0 +1,28 @@
4288 +/*
4289 + * HND SiliconBackplane MIPS/ARM cores software interface.
4290 + *
4291 + * Copyright 2006, Broadcom Corporation
4292 + * All Rights Reserved.
4293 + *
4294 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4295 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4296 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4297 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4298 + *
4299 + * $Id: hndcpu.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4300 + */
4301 +
4302 +#ifndef _hndcpu_h_
4303 +#define _hndcpu_h_
4304 +
4305 +#if defined(mips)
4306 +#include <hndmips.h>
4307 +#elif defined(__ARM_ARCH_4T__)
4308 +#include <hndarm.h>
4309 +#endif
4310 +
4311 +extern uint sb_irq(sb_t *sbh);
4312 +extern uint32 sb_cpu_clock(sb_t *sbh);
4313 +extern void sb_cpu_wait(void);
4314 +
4315 +#endif /* _hndcpu_h_ */
4316 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
4317 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
4318 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2006-04-27 20:43:42.000000000 +0200
4319 @@ -0,0 +1,45 @@
4320 +/*
4321 + * HND SiliconBackplane MIPS core software interface.
4322 + *
4323 + * Copyright 2006, Broadcom Corporation
4324 + * All Rights Reserved.
4325 + *
4326 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4327 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4328 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4329 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4330 + *
4331 + * $Id: hndmips.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
4332 + */
4333 +
4334 +#ifndef _hndmips_h_
4335 +#define _hndmips_h_
4336 +
4337 +extern void sb_mips_init(sb_t *sbh, uint shirq_map_base);
4338 +extern bool sb_mips_setclock(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
4339 +extern void enable_pfc(uint32 mode);
4340 +extern uint32 sb_memc_get_ncdl(sb_t *sbh);
4341 +
4342 +#if defined(BCMPERFSTATS)
4343 +/* enable counting - exclusive version. Only one set of counters allowed at a time */
4344 +extern void hndmips_perf_instrcount_enable(void);
4345 +extern void hndmips_perf_icachecount_enable(void);
4346 +extern void hndmips_perf_dcachecount_enable(void);
4347 +/* start and stop counting */
4348 +#define hndmips_perf_start01() \
4349 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) | 0x80008000)
4350 +#define hndmips_perf_stop01() \
4351 + MTC0(C0_PERFORMANCE, 4, MFC0(C0_PERFORMANCE, 4) & ~0x80008000)
4352 +/* retrieve coutners - counters *decrement* */
4353 +#define hndmips_perf_read0() -(long)(MFC0(C0_PERFORMANCE, 0))
4354 +#define hndmips_perf_read1() -(long)(MFC0(C0_PERFORMANCE, 1))
4355 +#define hndmips_perf_read2() -(long)(MFC0(C0_PERFORMANCE, 2))
4356 +/* enable counting - modular version. Each counters can be enabled separately. */
4357 +extern void hndmips_perf_icache_hit_enable(void);
4358 +extern void hndmips_perf_icache_miss_enable(void);
4359 +extern uint32 hndmips_perf_read_instrcount(void);
4360 +extern uint32 hndmips_perf_read_cache_miss(void);
4361 +extern uint32 hndmips_perf_read_cache_hit(void);
4362 +#endif /* defined(BCMINTERNAL) || defined (BCMPERFSTATS) */
4363 +
4364 +#endif /* _hndmips_h_ */
4365 diff -urN linux.old/arch/mips/bcm947xx/include/hndpci.h linux.dev/arch/mips/bcm947xx/include/hndpci.h
4366 --- linux.old/arch/mips/bcm947xx/include/hndpci.h 1970-01-01 01:00:00.000000000 +0100
4367 +++ linux.dev/arch/mips/bcm947xx/include/hndpci.h 2006-04-27 20:36:48.000000000 +0200
4368 @@ -0,0 +1,30 @@
4369 +/*
4370 + * HND SiliconBackplane PCI core software interface.
4371 + *
4372 + * $Id: hndpci.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
4373 + * Copyright 2006, Broadcom Corporation
4374 + * All Rights Reserved.
4375 + *
4376 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4377 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4378 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4379 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4380 + */
4381 +
4382 +#ifndef _hndpci_h_
4383 +#define _hndpci_h_
4384 +
4385 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4386 + int len);
4387 +extern int extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4388 + int len);
4389 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4390 + int len);
4391 +extern int extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf,
4392 + int len);
4393 +extern void sbpci_ban(uint16 core);
4394 +extern int sbpci_init(sb_t *sbh);
4395 +extern int sbpci_init_pci(sb_t *sbh);
4396 +extern void sbpci_check(sb_t *sbh);
4397 +
4398 +#endif /* _hndpci_h_ */
4399 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
4400 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
4401 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2006-04-27 20:10:08.000000000 +0200
4402 @@ -0,0 +1,417 @@
4403 +/*
4404 + * Linux-specific abstractions to gain some independence from linux kernel versions.
4405 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
4406 + *
4407 + * Copyright 2006, Broadcom Corporation
4408 + * All Rights Reserved.
4409 + *
4410 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4411 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4412 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4413 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4414 + *
4415 + * $Id: linuxver.h,v 1.1.1.10 2006/02/27 03:43:16 honor Exp $
4416 + */
4417 +
4418 +#ifndef _linuxver_h_
4419 +#define _linuxver_h_
4420 +
4421 +#include <linux/config.h>
4422 +#include <linux/version.h>
4423 +
4424 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
4425 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
4426 +#ifdef __UNDEF_NO_VERSION__
4427 +#undef __NO_VERSION__
4428 +#else
4429 +#define __NO_VERSION__
4430 +#endif
4431 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0) */
4432 +
4433 +#if defined(MODULE) && defined(MODVERSIONS)
4434 +#include <linux/modversions.h>
4435 +#endif
4436 +
4437 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 0)
4438 +#include <linux/moduleparam.h>
4439 +#endif
4440 +
4441 +
4442 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
4443 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
4444 +#define module_param_string(_name_, _string_, _size_, _perm_) \
4445 + MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
4446 +#endif
4447 +
4448 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
4449 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
4450 +#include <linux/malloc.h>
4451 +#else
4452 +#include <linux/slab.h>
4453 +#endif
4454 +
4455 +#include <linux/types.h>
4456 +#include <linux/init.h>
4457 +#include <linux/mm.h>
4458 +#include <linux/string.h>
4459 +#include <linux/pci.h>
4460 +#include <linux/interrupt.h>
4461 +#include <linux/netdevice.h>
4462 +#include <asm/io.h>
4463 +
4464 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
4465 +#include <linux/workqueue.h>
4466 +#else
4467 +#include <linux/tqueue.h>
4468 +#ifndef work_struct
4469 +#define work_struct tq_struct
4470 +#endif
4471 +#ifndef INIT_WORK
4472 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
4473 +#endif
4474 +#ifndef schedule_work
4475 +#define schedule_work(_work) schedule_task((_work))
4476 +#endif
4477 +#ifndef flush_scheduled_work
4478 +#define flush_scheduled_work() flush_scheduled_tasks()
4479 +#endif
4480 +#endif /* LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41) */
4481 +
4482 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4483 +/* Some distributions have their own 2.6.x compatibility layers */
4484 +#ifndef IRQ_NONE
4485 +typedef void irqreturn_t;
4486 +#define IRQ_NONE
4487 +#define IRQ_HANDLED
4488 +#define IRQ_RETVAL(x)
4489 +#endif
4490 +#else
4491 +typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
4492 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0) */
4493 +
4494 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
4495 +
4496 +#include <pcmcia/version.h>
4497 +#include <pcmcia/cs_types.h>
4498 +#include <pcmcia/cs.h>
4499 +#include <pcmcia/cistpl.h>
4500 +#include <pcmcia/cisreg.h>
4501 +#include <pcmcia/ds.h>
4502 +
4503 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 69))
4504 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
4505 + * does this, but it's not in 2.4 so we do our own for now.
4506 + */
4507 +static inline void
4508 +cs_error(client_handle_t handle, int func, int ret)
4509 +{
4510 + error_info_t err = { func, ret };
4511 + CardServices(ReportError, handle, &err);
4512 +}
4513 +#endif
4514 +
4515 +#endif /* CONFIG_PCMCIA */
4516 +
4517 +#ifndef __exit
4518 +#define __exit
4519 +#endif
4520 +#ifndef __devexit
4521 +#define __devexit
4522 +#endif
4523 +#ifndef __devinit
4524 +#define __devinit __init
4525 +#endif
4526 +#ifndef __devinitdata
4527 +#define __devinitdata
4528 +#endif
4529 +#ifndef __devexit_p
4530 +#define __devexit_p(x) x
4531 +#endif
4532 +
4533 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
4534 +
4535 +#define pci_get_drvdata(dev) (dev)->sysdata
4536 +#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
4537 +
4538 +/*
4539 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
4540 + */
4541 +
4542 +struct pci_device_id {
4543 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
4544 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
4545 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
4546 + unsigned long driver_data; /* Data private to the driver */
4547 +};
4548 +
4549 +struct pci_driver {
4550 + struct list_head node;
4551 + char *name;
4552 + const struct pci_device_id *id_table; /* NULL if wants all devices */
4553 + int (*probe)(struct pci_dev *dev,
4554 + const struct pci_device_id *id); /* New device inserted */
4555 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug
4556 + * capable driver)
4557 + */
4558 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
4559 + void (*resume)(struct pci_dev *dev); /* Device woken up */
4560 +};
4561 +
4562 +#define MODULE_DEVICE_TABLE(type, name)
4563 +#define PCI_ANY_ID (~0)
4564 +
4565 +/* compatpci.c */
4566 +#define pci_module_init pci_register_driver
4567 +extern int pci_register_driver(struct pci_driver *drv);
4568 +extern void pci_unregister_driver(struct pci_driver *drv);
4569 +
4570 +#endif /* PCI registration */
4571 +
4572 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
4573 +#ifdef MODULE
4574 +#define module_init(x) int init_module(void) { return x(); }
4575 +#define module_exit(x) void cleanup_module(void) { x(); }
4576 +#else
4577 +#define module_init(x) __initcall(x);
4578 +#define module_exit(x) __exitcall(x);
4579 +#endif
4580 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18) */
4581 +
4582 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
4583 +#define list_for_each(pos, head) \
4584 + for (pos = (head)->next; pos != (head); pos = pos->next)
4585 +#endif
4586 +
4587 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
4588 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
4589 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
4590 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
4591 +#endif
4592 +
4593 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
4594 +#define pci_enable_device(dev) do { } while (0)
4595 +#endif
4596 +
4597 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
4598 +#define net_device device
4599 +#endif
4600 +
4601 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
4602 +
4603 +/*
4604 + * DMA mapping
4605 + *
4606 + * See linux/Documentation/DMA-mapping.txt
4607 + */
4608 +
4609 +#ifndef PCI_DMA_TODEVICE
4610 +#define PCI_DMA_TODEVICE 1
4611 +#define PCI_DMA_FROMDEVICE 2
4612 +#endif
4613 +
4614 +typedef u32 dma_addr_t;
4615 +
4616 +/* Pure 2^n version of get_order */
4617 +static inline int get_order(unsigned long size)
4618 +{
4619 + int order;
4620 +
4621 + size = (size-1) >> (PAGE_SHIFT-1);
4622 + order = -1;
4623 + do {
4624 + size >>= 1;
4625 + order++;
4626 + } while (size);
4627 + return order;
4628 +}
4629 +
4630 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
4631 + dma_addr_t *dma_handle)
4632 +{
4633 + void *ret;
4634 + int gfp = GFP_ATOMIC | GFP_DMA;
4635 +
4636 + ret = (void *)__get_free_pages(gfp, get_order(size));
4637 +
4638 + if (ret != NULL) {
4639 + memset(ret, 0, size);
4640 + *dma_handle = virt_to_bus(ret);
4641 + }
4642 + return ret;
4643 +}
4644 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
4645 + void *vaddr, dma_addr_t dma_handle)
4646 +{
4647 + free_pages((unsigned long)vaddr, get_order(size));
4648 +}
4649 +#ifdef ILSIM
4650 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
4651 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
4652 +#else
4653 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
4654 +#define pci_unmap_single(cookie, address, size, dir)
4655 +#endif
4656 +
4657 +#endif /* DMA mapping */
4658 +
4659 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
4660 +
4661 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
4662 +#define netif_down(dev) do { (dev)->start = 0; } while (0)
4663 +
4664 +/* pcmcia-cs provides its own netdevice compatibility layer */
4665 +#ifndef _COMPAT_NETDEVICE_H
4666 +
4667 +/*
4668 + * SoftNet
4669 + *
4670 + * For pre-softnet kernels we need to tell the upper layer not to
4671 + * re-enter start_xmit() while we are in there. However softnet
4672 + * guarantees not to enter while we are in there so there is no need
4673 + * to do the netif_stop_queue() dance unless the transmit queue really
4674 + * gets stuck. This should also improve performance according to tests
4675 + * done by Aman Singla.
4676 + */
4677 +
4678 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
4679 +#define netif_wake_queue(dev) \
4680 + do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
4681 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
4682 +
4683 +static inline void netif_start_queue(struct net_device *dev)
4684 +{
4685 + dev->tbusy = 0;
4686 + dev->interrupt = 0;
4687 + dev->start = 1;
4688 +}
4689 +
4690 +#define netif_queue_stopped(dev) (dev)->tbusy
4691 +#define netif_running(dev) (dev)->start
4692 +
4693 +#endif /* _COMPAT_NETDEVICE_H */
4694 +
4695 +#define netif_device_attach(dev) netif_start_queue(dev)
4696 +#define netif_device_detach(dev) netif_stop_queue(dev)
4697 +
4698 +/* 2.4.x renamed bottom halves to tasklets */
4699 +#define tasklet_struct tq_struct
4700 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
4701 +{
4702 + queue_task(tasklet, &tq_immediate);
4703 + mark_bh(IMMEDIATE_BH);
4704 +}
4705 +
4706 +static inline void tasklet_init(struct tasklet_struct *tasklet,
4707 + void (*func)(unsigned long),
4708 + unsigned long data)
4709 +{
4710 + tasklet->next = NULL;
4711 + tasklet->sync = 0;
4712 + tasklet->routine = (void (*)(void *))func;
4713 + tasklet->data = (void *)data;
4714 +}
4715 +#define tasklet_kill(tasklet) { do{} while (0); }
4716 +
4717 +/* 2.4.x introduced del_timer_sync() */
4718 +#define del_timer_sync(timer) del_timer(timer)
4719 +
4720 +#else
4721 +
4722 +#define netif_down(dev)
4723 +
4724 +#endif /* SoftNet */
4725 +
4726 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
4727 +
4728 +/*
4729 + * Emit code to initialise a tq_struct's routine and data pointers
4730 + */
4731 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
4732 + do { \
4733 + (_tq)->routine = _routine; \
4734 + (_tq)->data = _data; \
4735 + } while (0)
4736 +
4737 +/*
4738 + * Emit code to initialise all of a tq_struct
4739 + */
4740 +#define INIT_TQUEUE(_tq, _routine, _data) \
4741 + do { \
4742 + INIT_LIST_HEAD(&(_tq)->list); \
4743 + (_tq)->sync = 0; \
4744 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
4745 + } while (0)
4746 +
4747 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3) */
4748 +
4749 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
4750 +
4751 +/* Power management related routines */
4752 +
4753 +static inline int
4754 +pci_save_state(struct pci_dev *dev, u32 *buffer)
4755 +{
4756 + int i;
4757 + if (buffer) {
4758 + for (i = 0; i < 16; i++)
4759 + pci_read_config_dword(dev, i * 4, &buffer[i]);
4760 + }
4761 + return 0;
4762 +}
4763 +
4764 +static inline int
4765 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
4766 +{
4767 + int i;
4768 +
4769 + if (buffer) {
4770 + for (i = 0; i < 16; i++)
4771 + pci_write_config_dword(dev, i * 4, buffer[i]);
4772 + }
4773 + /*
4774 + * otherwise, write the context information we know from bootup.
4775 + * This works around a problem where warm-booting from Windows
4776 + * combined with a D3(hot)->D0 transition causes PCI config
4777 + * header data to be forgotten.
4778 + */
4779 + else {
4780 + for (i = 0; i < 6; i ++)
4781 + pci_write_config_dword(dev,
4782 + PCI_BASE_ADDRESS_0 + (i * 4),
4783 + pci_resource_start(dev, i));
4784 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
4785 + }
4786 + return 0;
4787 +}
4788 +
4789 +#endif /* PCI power management */
4790 +
4791 +/* Old cp0 access macros deprecated in 2.4.19 */
4792 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
4793 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
4794 +#endif
4795 +
4796 +/* Module refcount handled internally in 2.6.x */
4797 +#ifndef SET_MODULE_OWNER
4798 +#define SET_MODULE_OWNER(dev) do {} while (0)
4799 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
4800 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
4801 +#else
4802 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
4803 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
4804 +#endif
4805 +
4806 +#ifndef SET_NETDEV_DEV
4807 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
4808 +#endif
4809 +
4810 +#ifndef HAVE_FREE_NETDEV
4811 +#define free_netdev(dev) kfree(dev)
4812 +#endif
4813 +
4814 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
4815 +/* struct packet_type redefined in 2.6.x */
4816 +#define af_packet_priv data
4817 +#endif
4818 +
4819 +#endif /* _linuxver_h_ */
4820 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
4821 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
4822 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2006-04-27 22:12:20.000000000 +0200
4823 @@ -0,0 +1,541 @@
4824 +/*
4825 + * HND Run Time Environment for standalone MIPS programs.
4826 + *
4827 + * Copyright 2006, Broadcom Corporation
4828 + * All Rights Reserved.
4829 + *
4830 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4831 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4832 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4833 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4834 + *
4835 + * $Id: mipsinc.h,v 1.1.1.5 2006/02/27 03:43:16 honor Exp $
4836 + */
4837 +
4838 +#ifndef _MISPINC_H
4839 +#define _MISPINC_H
4840 +
4841 +
4842 +/* MIPS defines */
4843 +
4844 +#ifdef _LANGUAGE_ASSEMBLY
4845 +
4846 +/*
4847 + * Symbolic register names for 32 bit ABI
4848 + */
4849 +#define zero $0 /* wired zero */
4850 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
4851 +#define v0 $2 /* return value */
4852 +#define v1 $3
4853 +#define a0 $4 /* argument registers */
4854 +#define a1 $5
4855 +#define a2 $6
4856 +#define a3 $7
4857 +#define t0 $8 /* caller saved */
4858 +#define t1 $9
4859 +#define t2 $10
4860 +#define t3 $11
4861 +#define t4 $12
4862 +#define t5 $13
4863 +#define t6 $14
4864 +#define t7 $15
4865 +#define s0 $16 /* callee saved */
4866 +#define s1 $17
4867 +#define s2 $18
4868 +#define s3 $19
4869 +#define s4 $20
4870 +#define s5 $21
4871 +#define s6 $22
4872 +#define s7 $23
4873 +#define t8 $24 /* caller saved */
4874 +#define t9 $25
4875 +#define jp $25 /* PIC jump register */
4876 +#define k0 $26 /* kernel scratch */
4877 +#define k1 $27
4878 +#define gp $28 /* global pointer */
4879 +#define sp $29 /* stack pointer */
4880 +#define fp $30 /* frame pointer */
4881 +#define s8 $30 /* same like fp! */
4882 +#define ra $31 /* return address */
4883 +
4884 +
4885 +/* CP0 Registers */
4886 +
4887 +#define C0_INX $0
4888 +#define C0_RAND $1
4889 +#define C0_TLBLO0 $2
4890 +#define C0_TLBLO C0_TLBLO0
4891 +#define C0_TLBLO1 $3
4892 +#define C0_CTEXT $4
4893 +#define C0_PGMASK $5
4894 +#define C0_WIRED $6
4895 +#define C0_BADVADDR $8
4896 +#define C0_COUNT $9
4897 +#define C0_TLBHI $10
4898 +#define C0_COMPARE $11
4899 +#define C0_SR $12
4900 +#define C0_STATUS C0_SR
4901 +#define C0_CAUSE $13
4902 +#define C0_EPC $14
4903 +#define C0_PRID $15
4904 +#define C0_CONFIG $16
4905 +#define C0_LLADDR $17
4906 +#define C0_WATCHLO $18
4907 +#define C0_WATCHHI $19
4908 +#define C0_XCTEXT $20
4909 +#define C0_DIAGNOSTIC $22
4910 +#define C0_BROADCOM C0_DIAGNOSTIC
4911 +#define C0_PERFORMANCE $25
4912 +#define C0_ECC $26
4913 +#define C0_CACHEERR $27
4914 +#define C0_TAGLO $28
4915 +#define C0_TAGHI $29
4916 +#define C0_ERREPC $30
4917 +#define C0_DESAVE $31
4918 +
4919 +/*
4920 + * LEAF - declare leaf routine
4921 + */
4922 +#define LEAF(symbol) \
4923 + .globl symbol; \
4924 + .align 2; \
4925 + .type symbol, @function; \
4926 + .ent symbol, 0; \
4927 +symbol: .frame sp, 0, ra
4928 +
4929 +/*
4930 + * END - mark end of function
4931 + */
4932 +#define END(function) \
4933 + .end function; \
4934 + .size function, . - function
4935 +
4936 +#define _ULCAST_
4937 +
4938 +#define MFC0_SEL(dst, src, sel) \
4939 + .word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
4940 +
4941 +
4942 +#define MTC0_SEL(dst, src, sel) \
4943 + .word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
4944 +
4945 +#else
4946 +
4947 +/*
4948 + * The following macros are especially useful for __asm__
4949 + * inline assembler.
4950 + */
4951 +#ifndef __STR
4952 +#define __STR(x) #x
4953 +#endif
4954 +#ifndef STR
4955 +#define STR(x) __STR(x)
4956 +#endif
4957 +
4958 +#define _ULCAST_ (unsigned long)
4959 +
4960 +
4961 +/* CP0 Registers */
4962 +
4963 +#define C0_INX 0 /* CP0: TLB Index */
4964 +#define C0_RAND 1 /* CP0: TLB Random */
4965 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
4966 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
4967 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
4968 +#define C0_CTEXT 4 /* CP0: Context */
4969 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
4970 +#define C0_WIRED 6 /* CP0: TLB Wired */
4971 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
4972 +#define C0_COUNT 9 /* CP0: Count */
4973 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
4974 +#define C0_COMPARE 11 /* CP0: Compare */
4975 +#define C0_SR 12 /* CP0: Processor Status */
4976 +#define C0_STATUS C0_SR /* CP0: Processor Status */
4977 +#define C0_CAUSE 13 /* CP0: Exception Cause */
4978 +#define C0_EPC 14 /* CP0: Exception PC */
4979 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
4980 +#define C0_CONFIG 16 /* CP0: Config */
4981 +#define C0_LLADDR 17 /* CP0: LLAddr */
4982 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
4983 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
4984 +#define C0_XCTEXT 20 /* CP0: XContext */
4985 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
4986 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
4987 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
4988 +#define C0_ECC 26 /* CP0: ECC */
4989 +#define C0_CACHEERR 27 /* CP0: CacheErr */
4990 +#define C0_TAGLO 28 /* CP0: TagLo */
4991 +#define C0_TAGHI 29 /* CP0: TagHi */
4992 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
4993 +#define C0_DESAVE 31 /* CP0: DebugSave */
4994 +
4995 +#endif /* _LANGUAGE_ASSEMBLY */
4996 +
4997 +/*
4998 + * Memory segments (32bit kernel mode addresses)
4999 + */
5000 +#undef KUSEG
5001 +#undef KSEG0
5002 +#undef KSEG1
5003 +#undef KSEG2
5004 +#undef KSEG3
5005 +#define KUSEG 0x00000000
5006 +#define KSEG0 0x80000000
5007 +#define KSEG1 0xa0000000
5008 +#define KSEG2 0xc0000000
5009 +#define KSEG3 0xe0000000
5010 +#define PHYSADDR_MASK 0x1fffffff
5011 +
5012 +/*
5013 + * Map an address to a certain kernel segment
5014 + */
5015 +#undef PHYSADDR
5016 +#undef KSEG0ADDR
5017 +#undef KSEG1ADDR
5018 +#undef KSEG2ADDR
5019 +#undef KSEG3ADDR
5020 +
5021 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
5022 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
5023 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
5024 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
5025 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
5026 +
5027 +
5028 +#ifndef Index_Invalidate_I
5029 +/*
5030 + * Cache Operations
5031 + */
5032 +#define Index_Invalidate_I 0x00
5033 +#define Index_Writeback_Inv_D 0x01
5034 +#define Index_Invalidate_SI 0x02
5035 +#define Index_Writeback_Inv_SD 0x03
5036 +#define Index_Load_Tag_I 0x04
5037 +#define Index_Load_Tag_D 0x05
5038 +#define Index_Load_Tag_SI 0x06
5039 +#define Index_Load_Tag_SD 0x07
5040 +#define Index_Store_Tag_I 0x08
5041 +#define Index_Store_Tag_D 0x09
5042 +#define Index_Store_Tag_SI 0x0A
5043 +#define Index_Store_Tag_SD 0x0B
5044 +#define Create_Dirty_Excl_D 0x0d
5045 +#define Create_Dirty_Excl_SD 0x0f
5046 +#define Hit_Invalidate_I 0x10
5047 +#define Hit_Invalidate_D 0x11
5048 +#define Hit_Invalidate_SI 0x12
5049 +#define Hit_Invalidate_SD 0x13
5050 +#define Fill_I 0x14
5051 +#define Hit_Writeback_Inv_D 0x15
5052 + /* 0x16 is unused */
5053 +#define Hit_Writeback_Inv_SD 0x17
5054 +#define R5K_Page_Invalidate_S 0x17
5055 +#define Hit_Writeback_I 0x18
5056 +#define Hit_Writeback_D 0x19
5057 + /* 0x1a is unused */
5058 +#define Hit_Writeback_SD 0x1b
5059 + /* 0x1c is unused */
5060 + /* 0x1e is unused */
5061 +#define Hit_Set_Virtual_SI 0x1e
5062 +#define Hit_Set_Virtual_SD 0x1f
5063 +#endif /* !Index_Invalidate_I */
5064 +
5065 +
5066 +/*
5067 + * R4x00 interrupt enable / cause bits
5068 + */
5069 +#define IE_SW0 (_ULCAST_(1) << 8)
5070 +#define IE_SW1 (_ULCAST_(1) << 9)
5071 +#define IE_IRQ0 (_ULCAST_(1) << 10)
5072 +#define IE_IRQ1 (_ULCAST_(1) << 11)
5073 +#define IE_IRQ2 (_ULCAST_(1) << 12)
5074 +#define IE_IRQ3 (_ULCAST_(1) << 13)
5075 +#define IE_IRQ4 (_ULCAST_(1) << 14)
5076 +#define IE_IRQ5 (_ULCAST_(1) << 15)
5077 +
5078 +#ifndef ST0_UM
5079 +/*
5080 + * Bitfields in the mips32 cp0 status register
5081 + */
5082 +#define ST0_IE 0x00000001
5083 +#define ST0_EXL 0x00000002
5084 +#define ST0_ERL 0x00000004
5085 +#define ST0_UM 0x00000010
5086 +#define ST0_SWINT0 0x00000100
5087 +#define ST0_SWINT1 0x00000200
5088 +#define ST0_HWINT0 0x00000400
5089 +#define ST0_HWINT1 0x00000800
5090 +#define ST0_HWINT2 0x00001000
5091 +#define ST0_HWINT3 0x00002000
5092 +#define ST0_HWINT4 0x00004000
5093 +#define ST0_HWINT5 0x00008000
5094 +#define ST0_IM 0x0000ff00
5095 +#define ST0_NMI 0x00080000
5096 +#define ST0_SR 0x00100000
5097 +#define ST0_TS 0x00200000
5098 +#define ST0_BEV 0x00400000
5099 +#define ST0_RE 0x02000000
5100 +#define ST0_RP 0x08000000
5101 +#define ST0_CU 0xf0000000
5102 +#define ST0_CU0 0x10000000
5103 +#define ST0_CU1 0x20000000
5104 +#define ST0_CU2 0x40000000
5105 +#define ST0_CU3 0x80000000
5106 +#endif /* !ST0_UM */
5107 +
5108 +
5109 +/*
5110 + * Bitfields in the mips32 cp0 cause register
5111 + */
5112 +#define C_EXC 0x0000007c
5113 +#define C_EXC_SHIFT 2
5114 +#define C_INT 0x0000ff00
5115 +#define C_INT_SHIFT 8
5116 +#define C_SW0 (_ULCAST_(1) << 8)
5117 +#define C_SW1 (_ULCAST_(1) << 9)
5118 +#define C_IRQ0 (_ULCAST_(1) << 10)
5119 +#define C_IRQ1 (_ULCAST_(1) << 11)
5120 +#define C_IRQ2 (_ULCAST_(1) << 12)
5121 +#define C_IRQ3 (_ULCAST_(1) << 13)
5122 +#define C_IRQ4 (_ULCAST_(1) << 14)
5123 +#define C_IRQ5 (_ULCAST_(1) << 15)
5124 +#define C_WP 0x00400000
5125 +#define C_IV 0x00800000
5126 +#define C_CE 0x30000000
5127 +#define C_CE_SHIFT 28
5128 +#define C_BD 0x80000000
5129 +
5130 +/* Values in C_EXC */
5131 +#define EXC_INT 0
5132 +#define EXC_TLBM 1
5133 +#define EXC_TLBL 2
5134 +#define EXC_TLBS 3
5135 +#define EXC_AEL 4
5136 +#define EXC_AES 5
5137 +#define EXC_IBE 6
5138 +#define EXC_DBE 7
5139 +#define EXC_SYS 8
5140 +#define EXC_BPT 9
5141 +#define EXC_RI 10
5142 +#define EXC_CU 11
5143 +#define EXC_OV 12
5144 +#define EXC_TR 13
5145 +#define EXC_WATCH 23
5146 +#define EXC_MCHK 24
5147 +
5148 +
5149 +/*
5150 + * Bits in the cp0 config register.
5151 + */
5152 +#define CONF_CM_CACHABLE_NO_WA 0
5153 +#define CONF_CM_CACHABLE_WA 1
5154 +#define CONF_CM_UNCACHED 2
5155 +#define CONF_CM_CACHABLE_NONCOHERENT 3
5156 +#define CONF_CM_CACHABLE_CE 4
5157 +#define CONF_CM_CACHABLE_COW 5
5158 +#define CONF_CM_CACHABLE_CUW 6
5159 +#define CONF_CM_CACHABLE_ACCELERATED 7
5160 +#define CONF_CM_CMASK 7
5161 +#define CONF_CU (_ULCAST_(1) << 3)
5162 +#define CONF_DB (_ULCAST_(1) << 4)
5163 +#define CONF_IB (_ULCAST_(1) << 5)
5164 +#define CONF_SE (_ULCAST_(1) << 12)
5165 +#ifndef CONF_BE /* duplicate in mipsregs.h */
5166 +#define CONF_BE (_ULCAST_(1) << 15)
5167 +#endif
5168 +#define CONF_SC (_ULCAST_(1) << 17)
5169 +#define CONF_AC (_ULCAST_(1) << 23)
5170 +#define CONF_HALT (_ULCAST_(1) << 25)
5171 +#ifndef CONF_M /* duplicate in mipsregs.h */
5172 +#define CONF_M (_ULCAST_(1) << 31)
5173 +#endif
5174 +
5175 +
5176 +/*
5177 + * Bits in the cp0 config register select 1.
5178 + */
5179 +#define CONF1_FP 0x00000001 /* FPU present */
5180 +#define CONF1_EP 0x00000002 /* EJTAG present */
5181 +#define CONF1_CA 0x00000004 /* mips16 implemented */
5182 +#define CONF1_WR 0x00000008 /* Watch registers present */
5183 +#define CONF1_PC 0x00000010 /* Performance counters present */
5184 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
5185 +#define CONF1_DA_MASK 0x00000380
5186 +#define CONF1_DA_BASE 1
5187 +#define CONF1_DL_SHIFT 10 /* D$ line size */
5188 +#define CONF1_DL_MASK 0x00001c00
5189 +#define CONF1_DL_BASE 2
5190 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
5191 +#define CONF1_DS_MASK 0x0000e000
5192 +#define CONF1_DS_BASE 64
5193 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
5194 +#define CONF1_IA_MASK 0x00070000
5195 +#define CONF1_IA_BASE 1
5196 +#define CONF1_IL_SHIFT 19 /* I$ line size */
5197 +#define CONF1_IL_MASK 0x00380000
5198 +#define CONF1_IL_BASE 2
5199 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
5200 +#define CONF1_IS_MASK 0x01c00000
5201 +#define CONF1_IS_BASE 64
5202 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
5203 +#define CONF1_MS_SHIFT 25
5204 +
5205 +/* PRID register */
5206 +#define PRID_COPT_MASK 0xff000000
5207 +#define PRID_COMP_MASK 0x00ff0000
5208 +#define PRID_IMP_MASK 0x0000ff00
5209 +#define PRID_REV_MASK 0x000000ff
5210 +
5211 +#define PRID_COMP_LEGACY 0x000000
5212 +#define PRID_COMP_MIPS 0x010000
5213 +#define PRID_COMP_BROADCOM 0x020000
5214 +#define PRID_COMP_ALCHEMY 0x030000
5215 +#define PRID_COMP_SIBYTE 0x040000
5216 +#define PRID_IMP_BCM4710 0x4000
5217 +#define PRID_IMP_BCM3302 0x9000
5218 +#define PRID_IMP_BCM3303 0x9100
5219 +
5220 +#define PRID_IMP_UNKNOWN 0xff00
5221 +
5222 +#define BCM330X(id) \
5223 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5224 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
5225 + ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
5226 + (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
5227 +
5228 +/* Bits in C0_BROADCOM */
5229 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
5230 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
5231 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
5232 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
5233 +#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
5234 +
5235 +/* PreFetch Cache aka Read Ahead Cache */
5236 +
5237 +#define PFC_CR0 0xff400000 /* control reg 0 */
5238 +#define PFC_CR1 0xff400004 /* control reg 1 */
5239 +
5240 +/* PFC operations */
5241 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
5242 +#define PFC_D 0x00000002 /* Enable PFC use for data */
5243 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
5244 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
5245 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
5246 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
5247 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
5248 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
5249 +#define PFC_BRR 0x40000000 /* Bus error indication */
5250 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
5251 +
5252 +/* Handy defaults */
5253 +#define PFC_DISABLED 0
5254 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
5255 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
5256 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
5257 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
5258 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
5259 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
5260 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
5261 +
5262 +#ifndef _LANGUAGE_ASSEMBLY
5263 +
5264 +/*
5265 + * Macros to access the system control coprocessor
5266 + */
5267 +
5268 +#define MFC0(source, sel) \
5269 +({ \
5270 + int __res; \
5271 + __asm__ __volatile__(" \
5272 + .set\tnoreorder; \
5273 + .set\tnoat; \
5274 + .word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
5275 + move\t%0, $1; \
5276 + .set\tat; \
5277 + .set\treorder" \
5278 + :"=r" (__res) \
5279 + : \
5280 + :"$1"); \
5281 + __res; \
5282 +})
5283 +
5284 +#define MTC0(source, sel, value) \
5285 +do { \
5286 + __asm__ __volatile__(" \
5287 + .set\tnoreorder; \
5288 + .set\tnoat; \
5289 + move\t$1, %z0; \
5290 + .word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
5291 + .set\tat; \
5292 + .set\treorder" \
5293 + : \
5294 + :"jr" (value) \
5295 + :"$1"); \
5296 +} while (0)
5297 +
5298 +#define get_c0_count() \
5299 +({ \
5300 + int __res; \
5301 + __asm__ __volatile__(" \
5302 + .set\tnoreorder; \
5303 + .set\tnoat; \
5304 + mfc0\t%0, $9; \
5305 + .set\tat; \
5306 + .set\treorder" \
5307 + :"=r" (__res)); \
5308 + __res; \
5309 +})
5310 +
5311 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
5312 +{
5313 + uint lsz, sets, ways;
5314 +
5315 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
5316 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
5317 + lsz = CONF1_IL_BASE << lsz;
5318 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
5319 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
5320 + *size = lsz * sets * ways;
5321 + *lsize = lsz;
5322 +}
5323 +
5324 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
5325 +{
5326 + uint lsz, sets, ways;
5327 +
5328 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
5329 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
5330 + lsz = CONF1_DL_BASE << lsz;
5331 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
5332 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
5333 + *size = lsz * sets * ways;
5334 + *lsize = lsz;
5335 +}
5336 +
5337 +#define cache_op(base, op) \
5338 + __asm__ __volatile__(" \
5339 + .set noreorder; \
5340 + .set mips3; \
5341 + cache %1, (%0); \
5342 + .set mips0; \
5343 + .set reorder" \
5344 + : \
5345 + : "r" (base), \
5346 + "i" (op));
5347 +
5348 +#define cache_unroll4(base, delta, op) \
5349 + __asm__ __volatile__(" \
5350 + .set noreorder; \
5351 + .set mips3; \
5352 + cache %1, 0(%0); \
5353 + cache %1, delta(%0); \
5354 + cache %1, (2 * delta)(%0); \
5355 + cache %1, (3 * delta)(%0); \
5356 + .set mips0; \
5357 + .set reorder" \
5358 + : \
5359 + : "r" (base), \
5360 + "i" (op));
5361 +
5362 +#endif /* !_LANGUAGE_ASSEMBLY */
5363 +
5364 +#endif /* _MISPINC_H */
5365 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
5366 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
5367 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2006-05-02 17:40:43.000000000 +0200
5368 @@ -0,0 +1,179 @@
5369 +#ifndef __osl_h
5370 +#define __osl_h
5371 +
5372 +#include <linux/delay.h>
5373 +#include <typedefs.h>
5374 +#include <linuxver.h>
5375 +#include <bcmutils.h>
5376 +#include <pcicfg.h>
5377 +
5378 +#define ASSERT(n)
5379 +
5380 +/* Pkttag flag should be part of public information */
5381 +struct osl_pubinfo {
5382 + bool pkttag;
5383 + uint pktalloced; /* Number of allocated packet buffers */
5384 +};
5385 +
5386 +struct osl_info {
5387 + struct osl_pubinfo pub;
5388 + uint magic;
5389 + void *pdev;
5390 + uint malloced;
5391 + uint failed;
5392 + void *dbgmem_list;
5393 +};
5394 +
5395 +typedef struct osl_info osl_t;
5396 +
5397 +#define PCI_CFG_RETRY 10
5398 +
5399 +/* map/unmap direction */
5400 +#define DMA_TX 1 /* TX direction for DMA */
5401 +#define DMA_RX 2 /* RX direction for DMA */
5402 +
5403 +#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
5404 +#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
5405 +#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
5406 +
5407 +/* bcopy, bcmp, and bzero */
5408 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
5409 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
5410 +#define bzero(b, len) memset((b), '\0', (len))
5411 +
5412 +/* uncached virtual address */
5413 +#ifdef mips
5414 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
5415 +#include <asm/addrspace.h>
5416 +#else
5417 +#define OSL_UNCACHED(va) (va)
5418 +#endif /* mips */
5419 +
5420 +
5421 +#ifndef IL_BIGENDIAN
5422 +#define R_REG(osh, r) (\
5423 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
5424 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
5425 + readl((volatile uint32*)(r)) \
5426 +)
5427 +#define W_REG(osh, r, v) do { \
5428 + switch (sizeof(*(r))) { \
5429 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
5430 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
5431 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5432 + } \
5433 +} while (0)
5434 +#else /* IL_BIGENDIAN */
5435 +#define R_REG(osh, r) ({ \
5436 + __typeof(*(r)) __osl_v; \
5437 + switch (sizeof(*(r))) { \
5438 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
5439 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
5440 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
5441 + } \
5442 + __osl_v; \
5443 +})
5444 +#define W_REG(osh, r, v) do { \
5445 + switch (sizeof(*(r))) { \
5446 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
5447 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
5448 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
5449 + } \
5450 +} while (0)
5451 +#endif /* IL_BIGENDIAN */
5452 +
5453 +/* dereference an address that may cause a bus exception */
5454 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
5455 +#include <asm/paccess.h>
5456 +
5457 +/* map/unmap physical to virtual I/O */
5458 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
5459 +#define REG_UNMAP(va) iounmap((void *)(va))
5460 +
5461 +/* shared (dma-able) memory access macros */
5462 +#define R_SM(r) *(r)
5463 +#define W_SM(r, v) (*(r) = (v))
5464 +#define BZERO_SM(r, len) memset((r), '\0', (len))
5465 +
5466 +#define MALLOC(osh, size) kmalloc((size), GFP_ATOMIC)
5467 +#define MFREE(osh, addr, size) kfree((addr))
5468 +#define MALLOCED(osh) (0)
5469 +
5470 +#define osl_delay OSL_DELAY
5471 +static inline void OSL_DELAY(uint usec)
5472 +{
5473 + uint d;
5474 +
5475 + while (usec > 0) {
5476 + d = MIN(usec, 1000);
5477 + udelay(d);
5478 + usec -= d;
5479 + }
5480 +}
5481 +
5482 +static inline void
5483 +bcm_mdelay(uint ms)
5484 +{
5485 + uint i;
5486 +
5487 + for (i = 0; i < ms; i++) {
5488 + OSL_DELAY(1000);
5489 + }
5490 +}
5491 +
5492 +
5493 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size)
5494 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
5495 +
5496 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
5497 + osl_pci_read_config((osh), (offset), (size))
5498 +
5499 +static inline uint32
5500 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
5501 +{
5502 + uint val;
5503 + uint retry = PCI_CFG_RETRY;
5504 +
5505 + do {
5506 + pci_read_config_dword(osh->pdev, offset, &val);
5507 + if (val != 0xffffffff)
5508 + break;
5509 + } while (retry--);
5510 +
5511 + return (val);
5512 +}
5513 +
5514 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
5515 + osl_pci_write_config((osh), (offset), (size), (val))
5516 +static inline void
5517 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
5518 +{
5519 + uint retry = PCI_CFG_RETRY;
5520 +
5521 + do {
5522 + pci_write_config_dword(osh->pdev, offset, val);
5523 + if (offset != PCI_BAR0_WIN)
5524 + break;
5525 + if (osl_pci_read_config(osh, offset, size) == val)
5526 + break;
5527 + } while (retry--);
5528 +}
5529 +
5530 +
5531 +/* return bus # for the pci device pointed by osh->pdev */
5532 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
5533 +static inline uint
5534 +osl_pci_bus(osl_t *osh)
5535 +{
5536 + return ((struct pci_dev *)osh->pdev)->bus->number;
5537 +}
5538 +
5539 +/* return slot # for the pci device pointed by osh->pdev */
5540 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
5541 +static inline uint
5542 +osl_pci_slot(osl_t *osh)
5543 +{
5544 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
5545 +}
5546 +
5547 +#endif
5548 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
5549 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
5550 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2006-04-27 20:31:41.000000000 +0200
5551 @@ -0,0 +1,495 @@
5552 +/*
5553 + * pcicfg.h: PCI configuration constants and structures.
5554 + *
5555 + * Copyright 2006, Broadcom Corporation
5556 + * All Rights Reserved.
5557 + *
5558 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5559 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5560 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5561 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5562 + *
5563 + * $Id: pcicfg.h,v 1.1.1.11 2006/04/08 06:13:40 honor Exp $
5564 + */
5565 +
5566 +#ifndef _h_pcicfg_
5567 +#define _h_pcicfg_
5568 +
5569 +/* The following inside ifndef's so we don't collide with NTDDK.H */
5570 +#ifndef PCI_MAX_BUS
5571 +#define PCI_MAX_BUS 0x100
5572 +#endif
5573 +#ifndef PCI_MAX_DEVICES
5574 +#define PCI_MAX_DEVICES 0x20
5575 +#endif
5576 +#ifndef PCI_MAX_FUNCTION
5577 +#define PCI_MAX_FUNCTION 0x8
5578 +#endif
5579 +
5580 +#ifndef PCI_INVALID_VENDORID
5581 +#define PCI_INVALID_VENDORID 0xffff
5582 +#endif
5583 +#ifndef PCI_INVALID_DEVICEID
5584 +#define PCI_INVALID_DEVICEID 0xffff
5585 +#endif
5586 +
5587 +
5588 +/* Convert between bus-slot-function-register and config addresses */
5589 +
5590 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
5591 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
5592 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
5593 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
5594 +
5595 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
5596 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
5597 +#define PCICFG_FUN_MASK 7 /* Function mask */
5598 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
5599 +
5600 +#define PCI_CONFIG_ADDR(b, s, f, o) \
5601 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
5602 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
5603 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
5604 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
5605 +
5606 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
5607 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
5608 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
5609 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
5610 +
5611 +/* PCIE Config space accessing MACROS */
5612 +
5613 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
5614 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
5615 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
5616 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
5617 +
5618 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
5619 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
5620 +#define PCIECFG_FUN_MASK 7 /* Function mask */
5621 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
5622 +
5623 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
5624 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
5625 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
5626 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
5627 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
5628 +
5629 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
5630 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
5631 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
5632 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
5633 +
5634 +/* The actual config space */
5635 +
5636 +#define PCI_BAR_MAX 6
5637 +
5638 +#define PCI_ROM_BAR 8
5639 +
5640 +#define PCR_RSVDA_MAX 2
5641 +
5642 +/* Bits in PCI bars' flags */
5643 +
5644 +#define PCIBAR_FLAGS 0xf
5645 +#define PCIBAR_IO 0x1
5646 +#define PCIBAR_MEM1M 0x2
5647 +#define PCIBAR_MEM64 0x4
5648 +#define PCIBAR_PREFETCH 0x8
5649 +#define PCIBAR_MEM32_MASK 0xFFFFFF80
5650 +
5651 +/* pci config status reg has a bit to indicate that capability ptr is present */
5652 +
5653 +#define PCI_CAPPTR_PRESENT 0x0010
5654 +
5655 +typedef struct _pci_config_regs {
5656 + unsigned short vendor;
5657 + unsigned short device;
5658 + unsigned short command;
5659 + unsigned short status;
5660 + unsigned char rev_id;
5661 + unsigned char prog_if;
5662 + unsigned char sub_class;
5663 + unsigned char base_class;
5664 + unsigned char cache_line_size;
5665 + unsigned char latency_timer;
5666 + unsigned char header_type;
5667 + unsigned char bist;
5668 + unsigned long base[PCI_BAR_MAX];
5669 + unsigned long cardbus_cis;
5670 + unsigned short subsys_vendor;
5671 + unsigned short subsys_id;
5672 + unsigned long baserom;
5673 + unsigned long rsvd_a[PCR_RSVDA_MAX];
5674 + unsigned char int_line;
5675 + unsigned char int_pin;
5676 + unsigned char min_gnt;
5677 + unsigned char max_lat;
5678 + unsigned char dev_dep[192];
5679 +} pci_config_regs;
5680 +
5681 +#define SZPCR (sizeof (pci_config_regs))
5682 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
5683 +
5684 +/* A structure for the config registers is nice, but in most
5685 + * systems the config space is not memory mapped, so we need
5686 + * filed offsetts. :-(
5687 + */
5688 +#define PCI_CFG_VID 0
5689 +#define PCI_CFG_DID 2
5690 +#define PCI_CFG_CMD 4
5691 +#define PCI_CFG_STAT 6
5692 +#define PCI_CFG_REV 8
5693 +#define PCI_CFG_PROGIF 9
5694 +#define PCI_CFG_SUBCL 0xa
5695 +#define PCI_CFG_BASECL 0xb
5696 +#define PCI_CFG_CLSZ 0xc
5697 +#define PCI_CFG_LATTIM 0xd
5698 +#define PCI_CFG_HDR 0xe
5699 +#define PCI_CFG_BIST 0xf
5700 +#define PCI_CFG_BAR0 0x10
5701 +#define PCI_CFG_BAR1 0x14
5702 +#define PCI_CFG_BAR2 0x18
5703 +#define PCI_CFG_BAR3 0x1c
5704 +#define PCI_CFG_BAR4 0x20
5705 +#define PCI_CFG_BAR5 0x24
5706 +#define PCI_CFG_CIS 0x28
5707 +#define PCI_CFG_SVID 0x2c
5708 +#define PCI_CFG_SSID 0x2e
5709 +#define PCI_CFG_ROMBAR 0x30
5710 +#define PCI_CFG_CAPPTR 0x34
5711 +#define PCI_CFG_INT 0x3c
5712 +#define PCI_CFG_PIN 0x3d
5713 +#define PCI_CFG_MINGNT 0x3e
5714 +#define PCI_CFG_MAXLAT 0x3f
5715 +
5716 +#ifdef __NetBSD__
5717 +#undef PCI_CLASS_DISPLAY
5718 +#undef PCI_CLASS_MEMORY
5719 +#undef PCI_CLASS_BRIDGE
5720 +#undef PCI_CLASS_INPUT
5721 +#undef PCI_CLASS_DOCK
5722 +#endif /* __NetBSD__ */
5723 +
5724 +/* Classes and subclasses */
5725 +
5726 +typedef enum {
5727 + PCI_CLASS_OLD = 0,
5728 + PCI_CLASS_DASDI,
5729 + PCI_CLASS_NET,
5730 + PCI_CLASS_DISPLAY,
5731 + PCI_CLASS_MMEDIA,
5732 + PCI_CLASS_MEMORY,
5733 + PCI_CLASS_BRIDGE,
5734 + PCI_CLASS_COMM,
5735 + PCI_CLASS_BASE,
5736 + PCI_CLASS_INPUT,
5737 + PCI_CLASS_DOCK,
5738 + PCI_CLASS_CPU,
5739 + PCI_CLASS_SERIAL,
5740 + PCI_CLASS_INTELLIGENT = 0xe,
5741 + PCI_CLASS_SATELLITE,
5742 + PCI_CLASS_CRYPT,
5743 + PCI_CLASS_DSP,
5744 + PCI_CLASS_XOR = 0xfe
5745 +} pci_classes;
5746 +
5747 +typedef enum {
5748 + PCI_DASDI_SCSI,
5749 + PCI_DASDI_IDE,
5750 + PCI_DASDI_FLOPPY,
5751 + PCI_DASDI_IPI,
5752 + PCI_DASDI_RAID,
5753 + PCI_DASDI_OTHER = 0x80
5754 +} pci_dasdi_subclasses;
5755 +
5756 +typedef enum {
5757 + PCI_NET_ETHER,
5758 + PCI_NET_TOKEN,
5759 + PCI_NET_FDDI,
5760 + PCI_NET_ATM,
5761 + PCI_NET_OTHER = 0x80
5762 +} pci_net_subclasses;
5763 +
5764 +typedef enum {
5765 + PCI_DISPLAY_VGA,
5766 + PCI_DISPLAY_XGA,
5767 + PCI_DISPLAY_3D,
5768 + PCI_DISPLAY_OTHER = 0x80
5769 +} pci_display_subclasses;
5770 +
5771 +typedef enum {
5772 + PCI_MMEDIA_VIDEO,
5773 + PCI_MMEDIA_AUDIO,
5774 + PCI_MMEDIA_PHONE,
5775 + PCI_MEDIA_OTHER = 0x80
5776 +} pci_mmedia_subclasses;
5777 +
5778 +typedef enum {
5779 + PCI_MEMORY_RAM,
5780 + PCI_MEMORY_FLASH,
5781 + PCI_MEMORY_OTHER = 0x80
5782 +} pci_memory_subclasses;
5783 +
5784 +typedef enum {
5785 + PCI_BRIDGE_HOST,
5786 + PCI_BRIDGE_ISA,
5787 + PCI_BRIDGE_EISA,
5788 + PCI_BRIDGE_MC,
5789 + PCI_BRIDGE_PCI,
5790 + PCI_BRIDGE_PCMCIA,
5791 + PCI_BRIDGE_NUBUS,
5792 + PCI_BRIDGE_CARDBUS,
5793 + PCI_BRIDGE_RACEWAY,
5794 + PCI_BRIDGE_OTHER = 0x80
5795 +} pci_bridge_subclasses;
5796 +
5797 +typedef enum {
5798 + PCI_COMM_UART,
5799 + PCI_COMM_PARALLEL,
5800 + PCI_COMM_MULTIUART,
5801 + PCI_COMM_MODEM,
5802 + PCI_COMM_OTHER = 0x80
5803 +} pci_comm_subclasses;
5804 +
5805 +typedef enum {
5806 + PCI_BASE_PIC,
5807 + PCI_BASE_DMA,
5808 + PCI_BASE_TIMER,
5809 + PCI_BASE_RTC,
5810 + PCI_BASE_PCI_HOTPLUG,
5811 + PCI_BASE_OTHER = 0x80
5812 +} pci_base_subclasses;
5813 +
5814 +typedef enum {
5815 + PCI_INPUT_KBD,
5816 + PCI_INPUT_PEN,
5817 + PCI_INPUT_MOUSE,
5818 + PCI_INPUT_SCANNER,
5819 + PCI_INPUT_GAMEPORT,
5820 + PCI_INPUT_OTHER = 0x80
5821 +} pci_input_subclasses;
5822 +
5823 +typedef enum {
5824 + PCI_DOCK_GENERIC,
5825 + PCI_DOCK_OTHER = 0x80
5826 +} pci_dock_subclasses;
5827 +
5828 +typedef enum {
5829 + PCI_CPU_386,
5830 + PCI_CPU_486,
5831 + PCI_CPU_PENTIUM,
5832 + PCI_CPU_ALPHA = 0x10,
5833 + PCI_CPU_POWERPC = 0x20,
5834 + PCI_CPU_MIPS = 0x30,
5835 + PCI_CPU_COPROC = 0x40,
5836 + PCI_CPU_OTHER = 0x80
5837 +} pci_cpu_subclasses;
5838 +
5839 +typedef enum {
5840 + PCI_SERIAL_IEEE1394,
5841 + PCI_SERIAL_ACCESS,
5842 + PCI_SERIAL_SSA,
5843 + PCI_SERIAL_USB,
5844 + PCI_SERIAL_FIBER,
5845 + PCI_SERIAL_SMBUS,
5846 + PCI_SERIAL_OTHER = 0x80
5847 +} pci_serial_subclasses;
5848 +
5849 +typedef enum {
5850 + PCI_INTELLIGENT_I2O
5851 +} pci_intelligent_subclasses;
5852 +
5853 +typedef enum {
5854 + PCI_SATELLITE_TV,
5855 + PCI_SATELLITE_AUDIO,
5856 + PCI_SATELLITE_VOICE,
5857 + PCI_SATELLITE_DATA,
5858 + PCI_SATELLITE_OTHER = 0x80
5859 +} pci_satellite_subclasses;
5860 +
5861 +typedef enum {
5862 + PCI_CRYPT_NETWORK,
5863 + PCI_CRYPT_ENTERTAINMENT,
5864 + PCI_CRYPT_OTHER = 0x80
5865 +} pci_crypt_subclasses;
5866 +
5867 +typedef enum {
5868 + PCI_DSP_DPIO,
5869 + PCI_DSP_OTHER = 0x80
5870 +} pci_dsp_subclasses;
5871 +
5872 +typedef enum {
5873 + PCI_XOR_QDMA,
5874 + PCI_XOR_OTHER = 0x80
5875 +} pci_xor_subclasses;
5876 +
5877 +/* Header types */
5878 +typedef enum {
5879 + PCI_HEADER_NORMAL,
5880 + PCI_HEADER_BRIDGE,
5881 + PCI_HEADER_CARDBUS
5882 +} pci_header_types;
5883 +
5884 +
5885 +/* Overlay for a PCI-to-PCI bridge */
5886 +
5887 +#define PPB_RSVDA_MAX 2
5888 +#define PPB_RSVDD_MAX 8
5889 +
5890 +typedef struct _ppb_config_regs {
5891 + unsigned short vendor;
5892 + unsigned short device;
5893 + unsigned short command;
5894 + unsigned short status;
5895 + unsigned char rev_id;
5896 + unsigned char prog_if;
5897 + unsigned char sub_class;
5898 + unsigned char base_class;
5899 + unsigned char cache_line_size;
5900 + unsigned char latency_timer;
5901 + unsigned char header_type;
5902 + unsigned char bist;
5903 + unsigned long rsvd_a[PPB_RSVDA_MAX];
5904 + unsigned char prim_bus;
5905 + unsigned char sec_bus;
5906 + unsigned char sub_bus;
5907 + unsigned char sec_lat;
5908 + unsigned char io_base;
5909 + unsigned char io_lim;
5910 + unsigned short sec_status;
5911 + unsigned short mem_base;
5912 + unsigned short mem_lim;
5913 + unsigned short pf_mem_base;
5914 + unsigned short pf_mem_lim;
5915 + unsigned long pf_mem_base_hi;
5916 + unsigned long pf_mem_lim_hi;
5917 + unsigned short io_base_hi;
5918 + unsigned short io_lim_hi;
5919 + unsigned short subsys_vendor;
5920 + unsigned short subsys_id;
5921 + unsigned long rsvd_b;
5922 + unsigned char rsvd_c;
5923 + unsigned char int_pin;
5924 + unsigned short bridge_ctrl;
5925 + unsigned char chip_ctrl;
5926 + unsigned char diag_ctrl;
5927 + unsigned short arb_ctrl;
5928 + unsigned long rsvd_d[PPB_RSVDD_MAX];
5929 + unsigned char dev_dep[192];
5930 +} ppb_config_regs;
5931 +
5932 +
5933 +/* PCI CAPABILITY DEFINES */
5934 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
5935 +#define PCI_CAP_MSICAP_ID 0x05
5936 +#define PCI_CAP_PCIECAP_ID 0x10
5937 +
5938 +/* Data structure to define the Message Signalled Interrupt facility
5939 + * Valid for PCI and PCIE configurations
5940 + */
5941 +typedef struct _pciconfig_cap_msi {
5942 + unsigned char capID;
5943 + unsigned char nextptr;
5944 + unsigned short msgctrl;
5945 + unsigned int msgaddr;
5946 +} pciconfig_cap_msi;
5947 +
5948 +/* Data structure to define the Power managment facility
5949 + * Valid for PCI and PCIE configurations
5950 + */
5951 +typedef struct _pciconfig_cap_pwrmgmt {
5952 + unsigned char capID;
5953 + unsigned char nextptr;
5954 + unsigned short pme_cap;
5955 + unsigned short pme_sts_ctrl;
5956 + unsigned char pme_bridge_ext;
5957 + unsigned char data;
5958 +} pciconfig_cap_pwrmgmt;
5959 +
5960 +/* Data structure to define the PCIE capability */
5961 +typedef struct _pciconfig_cap_pcie {
5962 + unsigned char capID;
5963 + unsigned char nextptr;
5964 + unsigned short pcie_cap;
5965 + unsigned int dev_cap;
5966 + unsigned short dev_ctrl;
5967 + unsigned short dev_status;
5968 + unsigned int link_cap;
5969 + unsigned short link_ctrl;
5970 + unsigned short link_status;
5971 +} pciconfig_cap_pcie;
5972 +
5973 +/* PCIE Enhanced CAPABILITY DEFINES */
5974 +#define PCIE_EXTCFG_OFFSET 0x100
5975 +#define PCIE_ADVERRREP_CAPID 0x0001
5976 +#define PCIE_VC_CAPID 0x0002
5977 +#define PCIE_DEVSNUM_CAPID 0x0003
5978 +#define PCIE_PWRBUDGET_CAPID 0x0004
5979 +
5980 +/* Header to define the PCIE specific capabilities in the extended config space */
5981 +typedef struct _pcie_enhanced_caphdr {
5982 + unsigned short capID;
5983 + unsigned short cap_ver : 4;
5984 + unsigned short next_ptr : 12;
5985 +} pcie_enhanced_caphdr;
5986 +
5987 +
5988 +/* Everything below is BRCM HND proprietary */
5989 +
5990 +
5991 +/* Brcm PCI configuration registers */
5992 +#define cap_list rsvd_a[0]
5993 +#define bar0_window dev_dep[0x80 - 0x40]
5994 +#define bar1_window dev_dep[0x84 - 0x40]
5995 +#define sprom_control dev_dep[0x88 - 0x40]
5996 +
5997 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
5998 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
5999 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
6000 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
6001 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
6002 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
6003 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
6004 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
6005 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address */
6006 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
6007 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
6008 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
6009 +
6010 +#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
6011 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
6012 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
6013 +#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
6014 + * 8KB window, so their address is the "regular"
6015 + * address plus 4K
6016 + */
6017 +#define PCI_BAR0_WINSZ 8192 /* bar0 window size */
6018 +
6019 +/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
6020 +#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
6021 +#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
6022 +#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
6023 +
6024 +/* PCI_INT_STATUS */
6025 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
6026 +
6027 +/* PCI_INT_MASK */
6028 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
6029 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
6030 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
6031 +
6032 +/* PCI_SPROM_CONTROL */
6033 +#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
6034 +#define SPROM_LOCKED 0x08 /* SPROM Locked */
6035 +#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
6036 +#define SPROM_WRITEEN 0x10 /* SPROM write enable */
6037 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
6038 +#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
6039 +
6040 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
6041 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
6042 +
6043 +/* PCI_CFG_CMD_STAT */
6044 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
6045 +
6046 +#endif /* _h_pcicfg_ */
6047 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
6048 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6049 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2006-04-27 22:11:01.000000000 +0200
6050 @@ -0,0 +1,516 @@
6051 +/*
6052 + * SiliconBackplane Chipcommon core hardware definitions.
6053 + *
6054 + * The chipcommon core provides chip identification, SB control,
6055 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6056 + * gpio interface, extbus, and support for serial and parallel flashes.
6057 + *
6058 + * $Id: sbchipc.h,v 1.1.1.14 2006/04/15 01:29:08 michael Exp $
6059 + * Copyright 2006, Broadcom Corporation
6060 + * All Rights Reserved.
6061 + *
6062 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6063 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6064 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6065 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6066 + *
6067 + */
6068 +
6069 +#ifndef _SBCHIPC_H
6070 +#define _SBCHIPC_H
6071 +
6072 +
6073 +#ifndef _LANGUAGE_ASSEMBLY
6074 +
6075 +/* cpp contortions to concatenate w/arg prescan */
6076 +#ifndef PAD
6077 +#define _PADLINE(line) pad ## line
6078 +#define _XSTR(line) _PADLINE(line)
6079 +#define PAD _XSTR(__LINE__)
6080 +#endif /* PAD */
6081 +
6082 +typedef volatile struct {
6083 + uint32 chipid; /* 0x0 */
6084 + uint32 capabilities;
6085 + uint32 corecontrol; /* corerev >= 1 */
6086 + uint32 bist;
6087 +
6088 + /* OTP */
6089 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6090 + uint32 otpcontrol;
6091 + uint32 otpprog;
6092 + uint32 PAD;
6093 +
6094 + /* Interrupt control */
6095 + uint32 intstatus; /* 0x20 */
6096 + uint32 intmask;
6097 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6098 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6099 +
6100 + /* Jtag Master */
6101 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6102 + uint32 jtagir;
6103 + uint32 jtagdr;
6104 + uint32 jtagctrl;
6105 +
6106 + /* serial flash interface registers */
6107 + uint32 flashcontrol; /* 0x40 */
6108 + uint32 flashaddress;
6109 + uint32 flashdata;
6110 + uint32 PAD[1];
6111 +
6112 + /* Silicon backplane configuration broadcast control */
6113 + uint32 broadcastaddress; /* 0x50 */
6114 + uint32 broadcastdata;
6115 + uint32 PAD[2];
6116 +
6117 + /* gpio - cleared only by power-on-reset */
6118 + uint32 gpioin; /* 0x60 */
6119 + uint32 gpioout;
6120 + uint32 gpioouten;
6121 + uint32 gpiocontrol;
6122 + uint32 gpiointpolarity;
6123 + uint32 gpiointmask;
6124 + uint32 PAD[2];
6125 +
6126 + /* Watchdog timer */
6127 + uint32 watchdog; /* 0x80 */
6128 + uint32 PAD[1];
6129 +
6130 + /* GPIO based LED powersave registers corerev >= 16 */
6131 + uint32 gpiotimerval; /* 0x88 */
6132 + uint32 gpiotimeroutmask;
6133 +
6134 + /* clock control */
6135 + uint32 clockcontrol_n; /* 0x90 */
6136 + uint32 clockcontrol_sb; /* aka m0 */
6137 + uint32 clockcontrol_pci; /* aka m1 */
6138 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6139 + uint32 clockcontrol_m3; /* cpu */
6140 + uint32 clkdiv; /* corerev >= 3 */
6141 + uint32 PAD[2];
6142 +
6143 + /* pll delay registers (corerev >= 4) */
6144 + uint32 pll_on_delay; /* 0xb0 */
6145 + uint32 fref_sel_delay;
6146 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6147 + uint32 PAD[1];
6148 +
6149 + /* Instaclock registers (corerev >= 10) */
6150 + uint32 system_clk_ctl; /* 0xc0 */
6151 + uint32 clkstatestretch;
6152 + uint32 PAD[14];
6153 +
6154 + /* ExtBus control registers (corerev >= 3) */
6155 + uint32 pcmcia_config; /* 0x100 */
6156 + uint32 pcmcia_memwait;
6157 + uint32 pcmcia_attrwait;
6158 + uint32 pcmcia_iowait;
6159 + uint32 ide_config;
6160 + uint32 ide_memwait;
6161 + uint32 ide_attrwait;
6162 + uint32 ide_iowait;
6163 + uint32 prog_config;
6164 + uint32 prog_waitcount;
6165 + uint32 flash_config;
6166 + uint32 flash_waitcount;
6167 + uint32 PAD[44];
6168 +
6169 + /* Clock control and hardware workarounds */
6170 + uint32 clk_ctl_st;
6171 + uint32 hw_war;
6172 + uint32 PAD[70];
6173 +
6174 + /* uarts */
6175 + uint8 uart0data; /* 0x300 */
6176 + uint8 uart0imr;
6177 + uint8 uart0fcr;
6178 + uint8 uart0lcr;
6179 + uint8 uart0mcr;
6180 + uint8 uart0lsr;
6181 + uint8 uart0msr;
6182 + uint8 uart0scratch;
6183 + uint8 PAD[248]; /* corerev >= 1 */
6184 +
6185 + uint8 uart1data; /* 0x400 */
6186 + uint8 uart1imr;
6187 + uint8 uart1fcr;
6188 + uint8 uart1lcr;
6189 + uint8 uart1mcr;
6190 + uint8 uart1lsr;
6191 + uint8 uart1msr;
6192 + uint8 uart1scratch;
6193 +} chipcregs_t;
6194 +
6195 +#endif /* _LANGUAGE_ASSEMBLY */
6196 +
6197 +#define CC_CHIPID 0
6198 +#define CC_CAPABILITIES 4
6199 +#define CC_JTAGCMD 0x30
6200 +#define CC_JTAGIR 0x34
6201 +#define CC_JTAGDR 0x38
6202 +#define CC_JTAGCTRL 0x3c
6203 +#define CC_WATCHDOG 0x80
6204 +#define CC_CLKC_N 0x90
6205 +#define CC_CLKC_M0 0x94
6206 +#define CC_CLKC_M1 0x98
6207 +#define CC_CLKC_M2 0x9c
6208 +#define CC_CLKC_M3 0xa0
6209 +#define CC_CLKDIV 0xa4
6210 +#define CC_SYS_CLK_CTL 0xc0
6211 +#define CC_OTP 0x800
6212 +
6213 +/* chipid */
6214 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6215 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6216 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6217 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6218 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6219 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6220 +#define CID_CC_SHIFT 24
6221 +
6222 +/* capabilities */
6223 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6224 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6225 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6226 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6227 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6228 +#define CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
6229 +#define CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
6230 +#define CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
6231 +#define CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
6232 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6233 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6234 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6235 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6236 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6237 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6238 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6239 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6240 +#define CAP_BKPLN64 0x08000000 /* 64-bit backplane */
6241 +
6242 +/* PLL type */
6243 +#define PLL_NONE 0x00000000
6244 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6245 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6246 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6247 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6248 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6249 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6250 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6251 +
6252 +/* corecontrol */
6253 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6254 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6255 +
6256 +/* chipcontrol */
6257 +#define CHIPCTRL_4321A0_DEFAULT 0x3a4
6258 +#define CHIPCTRL_4321A1_DEFAULT 0x0a4
6259 +
6260 +/* Fields in the otpstatus register */
6261 +#define OTPS_PROGFAIL 0x80000000
6262 +#define OTPS_PROTECT 0x00000007
6263 +#define OTPS_HW_PROTECT 0x00000001
6264 +#define OTPS_SW_PROTECT 0x00000002
6265 +#define OTPS_CID_PROTECT 0x00000004
6266 +
6267 +/* Fields in the otpcontrol register */
6268 +#define OTPC_RECWAIT 0xff000000
6269 +#define OTPC_PROGWAIT 0x00ffff00
6270 +#define OTPC_PRW_SHIFT 8
6271 +#define OTPC_MAXFAIL 0x00000038
6272 +#define OTPC_VSEL 0x00000006
6273 +#define OTPC_SELVL 0x00000001
6274 +
6275 +/* Fields in otpprog */
6276 +#define OTPP_COL_MASK 0x000000ff
6277 +#define OTPP_ROW_MASK 0x0000ff00
6278 +#define OTPP_ROW_SHIFT 8
6279 +#define OTPP_READERR 0x10000000
6280 +#define OTPP_VALUE 0x20000000
6281 +#define OTPP_VALUE_SHIFT 29
6282 +#define OTPP_READ 0x40000000
6283 +#define OTPP_START 0x80000000
6284 +#define OTPP_BUSY 0x80000000
6285 +
6286 +/* jtagcmd */
6287 +#define JCMD_START 0x80000000
6288 +#define JCMD_BUSY 0x80000000
6289 +#define JCMD_PAUSE 0x40000000
6290 +#define JCMD0_ACC_MASK 0x0000f000
6291 +#define JCMD0_ACC_IRDR 0x00000000
6292 +#define JCMD0_ACC_DR 0x00001000
6293 +#define JCMD0_ACC_IR 0x00002000
6294 +#define JCMD0_ACC_RESET 0x00003000
6295 +#define JCMD0_ACC_IRPDR 0x00004000
6296 +#define JCMD0_ACC_PDR 0x00005000
6297 +#define JCMD0_IRW_MASK 0x00000f00
6298 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6299 +#define JCMD_ACC_IRDR 0x00000000
6300 +#define JCMD_ACC_DR 0x00010000
6301 +#define JCMD_ACC_IR 0x00020000
6302 +#define JCMD_ACC_RESET 0x00030000
6303 +#define JCMD_ACC_IRPDR 0x00040000
6304 +#define JCMD_ACC_PDR 0x00050000
6305 +#define JCMD_IRW_MASK 0x00001f00
6306 +#define JCMD_IRW_SHIFT 8
6307 +#define JCMD_DRW_MASK 0x0000003f
6308 +
6309 +/* jtagctrl */
6310 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6311 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6312 +#define JCTRL_EN 1 /* Enable Jtag master */
6313 +
6314 +/* Fields in clkdiv */
6315 +#define CLKD_SFLASH 0x0f000000
6316 +#define CLKD_SFLASH_SHIFT 24
6317 +#define CLKD_OTP 0x000f0000
6318 +#define CLKD_OTP_SHIFT 16
6319 +#define CLKD_JTAG 0x00000f00
6320 +#define CLKD_JTAG_SHIFT 8
6321 +#define CLKD_UART 0x000000ff
6322 +
6323 +/* intstatus/intmask */
6324 +#define CI_GPIO 0x00000001 /* gpio intr */
6325 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6326 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6327 +
6328 +/* slow_clk_ctl */
6329 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6330 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6331 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6332 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6333 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6334 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
6335 + * 0: LPO is enabled
6336 + */
6337 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
6338 + * 0: power logic control
6339 + */
6340 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
6341 + * PLL clock disable requests from core
6342 + */
6343 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
6344 + * disable crystal when appropriate
6345 + */
6346 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6347 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6348 +#define SCC_CD_SHIFT 16
6349 +
6350 +/* system_clk_ctl */
6351 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6352 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6353 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6354 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6355 +#define SYCC_HR 0x00000010 /* Force HT */
6356 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
6357 +#define SYCC_CD_SHIFT 16
6358 +
6359 +/* gpiotimerval */
6360 +#define GPIO_ONTIME_SHIFT 16
6361 +
6362 +/* clockcontrol_n */
6363 +#define CN_N1_MASK 0x3f /* n1 control */
6364 +#define CN_N2_MASK 0x3f00 /* n2 control */
6365 +#define CN_N2_SHIFT 8
6366 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6367 +#define CN_PLLC_SHIFT 16
6368 +
6369 +/* clockcontrol_sb/pci/uart */
6370 +#define CC_M1_MASK 0x3f /* m1 control */
6371 +#define CC_M2_MASK 0x3f00 /* m2 control */
6372 +#define CC_M2_SHIFT 8
6373 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6374 +#define CC_M3_SHIFT 16
6375 +#define CC_MC_MASK 0x1f000000 /* mux control */
6376 +#define CC_MC_SHIFT 24
6377 +
6378 +/* N3M Clock control magic field values */
6379 +#define CC_F6_2 0x02 /* A factor of 2 in */
6380 +#define CC_F6_3 0x03 /* 6-bit fields like */
6381 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6382 +#define CC_F6_5 0x09
6383 +#define CC_F6_6 0x11
6384 +#define CC_F6_7 0x21
6385 +
6386 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6387 +
6388 +#define CC_MC_BYPASS 0x08
6389 +#define CC_MC_M1 0x04
6390 +#define CC_MC_M1M2 0x02
6391 +#define CC_MC_M1M2M3 0x01
6392 +#define CC_MC_M1M3 0x11
6393 +
6394 +/* Type 2 Clock control magic field values */
6395 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6396 +#define CC_T2M2_BIAS 3 /* m2 bias */
6397 +
6398 +#define CC_T2MC_M1BYP 1
6399 +#define CC_T2MC_M2BYP 2
6400 +#define CC_T2MC_M3BYP 4
6401 +
6402 +/* Type 6 Clock control magic field values */
6403 +#define CC_T6_MMASK 1 /* bits of interest in m */
6404 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6405 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6406 +#define SB2MIPS_T6(sb) (2 * (sb))
6407 +
6408 +/* Common clock base */
6409 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6410 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6411 +
6412 +/* Clock control values for 200Mhz in 5350 */
6413 +#define CLKC_5350_N 0x0311
6414 +#define CLKC_5350_M 0x04020009
6415 +
6416 +/* Flash types in the chipcommon capabilities register */
6417 +#define FLASH_NONE 0x000 /* No flash */
6418 +#define SFLASH_ST 0x100 /* ST serial flash */
6419 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6420 +#define PFLASH 0x700 /* Parallel flash */
6421 +
6422 +/* Bits in the ExtBus config registers */
6423 +#define CC_CFG_EN 0x0001 /* Enable */
6424 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6425 +#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
6426 +#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
6427 +#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
6428 +#define CC_CFG_EM_IDE 0x0006 /* IDE */
6429 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6430 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6431 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6432 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6433 +
6434 +/* ExtBus address space */
6435 +#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
6436 +#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
6437 +#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
6438 +#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
6439 +#define CC_EB_IDE 0x1a800000 /* IDE memory base */
6440 +#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
6441 +#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
6442 +#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
6443 +#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
6444 +
6445 +
6446 +/* Start/busy bit in flashcontrol */
6447 +#define SFLASH_OPCODE 0x000000ff
6448 +#define SFLASH_ACTION 0x00000700
6449 +#define SFLASH_START 0x80000000
6450 +#define SFLASH_BUSY SFLASH_START
6451 +
6452 +/* flashcontrol action codes */
6453 +#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
6454 +#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
6455 +#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
6456 +#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
6457 +#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
6458 +#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
6459 +#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
6460 +
6461 +/* flashcontrol action+opcodes for ST flashes */
6462 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6463 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6464 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6465 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6466 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6467 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6468 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6469 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6470 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6471 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6472 +
6473 +/* Status register bits for ST flashes */
6474 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6475 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6476 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6477 +#define SFLASH_ST_BP_SHIFT 2
6478 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6479 +
6480 +/* flashcontrol action+opcodes for Atmel flashes */
6481 +#define SFLASH_AT_READ 0x07e8
6482 +#define SFLASH_AT_PAGE_READ 0x07d2
6483 +#define SFLASH_AT_BUF1_READ
6484 +#define SFLASH_AT_BUF2_READ
6485 +#define SFLASH_AT_STATUS 0x01d7
6486 +#define SFLASH_AT_BUF1_WRITE 0x0384
6487 +#define SFLASH_AT_BUF2_WRITE 0x0387
6488 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6489 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6490 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6491 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6492 +#define SFLASH_AT_PAGE_ERASE 0x0281
6493 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6494 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6495 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6496 +#define SFLASH_AT_BUF1_LOAD 0x0253
6497 +#define SFLASH_AT_BUF2_LOAD 0x0255
6498 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6499 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6500 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6501 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6502 +
6503 +/* Status register bits for Atmel flashes */
6504 +#define SFLASH_AT_READY 0x80
6505 +#define SFLASH_AT_MISMATCH 0x40
6506 +#define SFLASH_AT_ID_MASK 0x38
6507 +#define SFLASH_AT_ID_SHIFT 3
6508 +
6509 +/* OTP regions */
6510 +#define OTP_HW_REGION OTPS_HW_PROTECT
6511 +#define OTP_SW_REGION OTPS_SW_PROTECT
6512 +#define OTP_CID_REGION OTPS_CID_PROTECT
6513 +
6514 +/* OTP regions (Byte offsets from otp size) */
6515 +#define OTP_SWLIM_OFF (-8)
6516 +#define OTP_CIDBASE_OFF 0
6517 +#define OTP_CIDLIM_OFF 8
6518 +
6519 +/* Predefined OTP words (Word offset from otp size) */
6520 +#define OTP_BOUNDARY_OFF (-4)
6521 +#define OTP_HWSIGN_OFF (-3)
6522 +#define OTP_SWSIGN_OFF (-2)
6523 +#define OTP_CIDSIGN_OFF (-1)
6524 +
6525 +#define OTP_CID_OFF 0
6526 +#define OTP_PKG_OFF 1
6527 +#define OTP_FID_OFF 2
6528 +#define OTP_RSV_OFF 3
6529 +#define OTP_LIM_OFF 4
6530 +
6531 +#define OTP_SIGNATURE 0x578a
6532 +#define OTP_MAGIC 0x4e56
6533 +
6534 +/*
6535 + * These are the UART port assignments, expressed as offsets from the base
6536 + * register. These assignments should hold for any serial port based on
6537 + * a 8250, 16450, or 16550(A).
6538 + */
6539 +
6540 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
6541 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
6542 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
6543 +#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
6544 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
6545 +#define UART_IIR 2 /* In: Interrupt Identity Register */
6546 +#define UART_FCR 2 /* Out: FIFO Control Register */
6547 +#define UART_LCR 3 /* Out: Line Control Register */
6548 +#define UART_MCR 4 /* Out: Modem Control Register */
6549 +#define UART_LSR 5 /* In: Line Status Register */
6550 +#define UART_MSR 6 /* In: Modem Status Register */
6551 +#define UART_SCR 7 /* I/O: Scratch Register */
6552 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
6553 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
6554 +#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
6555 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
6556 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
6557 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
6558 +#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
6559 +
6560 +/* Interrupt Enable Register (IER) bits */
6561 +#define UART_IER_EDSSI 8 /* enable modem status interrupt */
6562 +#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
6563 +#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
6564 +#define UART_IER_ERBFI 1 /* enable data available interrupt */
6565 +
6566 +#endif /* _SBCHIPC_H */
6567 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
6568 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
6569 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2006-04-27 22:14:11.000000000 +0200
6570 @@ -0,0 +1,369 @@
6571 +/*
6572 + * Broadcom SiliconBackplane hardware register definitions.
6573 + *
6574 + * Copyright 2006, Broadcom Corporation
6575 + * All Rights Reserved.
6576 + *
6577 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6578 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6579 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6580 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6581 + *
6582 + * $Id: sbconfig.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
6583 + */
6584 +
6585 +#ifndef _SBCONFIG_H
6586 +#define _SBCONFIG_H
6587 +
6588 +/* cpp contortions to concatenate w/arg prescan */
6589 +#ifndef PAD
6590 +#define _PADLINE(line) pad ## line
6591 +#define _XSTR(line) _PADLINE(line)
6592 +#define PAD _XSTR(__LINE__)
6593 +#endif
6594 +
6595 +/*
6596 + * SiliconBackplane Address Map.
6597 + * All regions may not exist on all chips.
6598 + */
6599 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
6600 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
6601 +#define SB_PCI_MEM_SZ (64 * 1024 * 1024)
6602 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
6603 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
6604 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
6605 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
6606 +
6607 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
6608 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
6609 +
6610 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
6611 +#define SB_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
6612 +#define SB_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
6613 +
6614 +#define SB_ROM 0x20000000 /* ARM ROM */
6615 +#define SB_SRAM2 0x80000000 /* ARM SRAM Region 2 */
6616 +#define SB_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
6617 +#define SB_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
6618 +
6619 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
6620 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
6621 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
6622 + * (2 ZettaBytes), low 32 bits
6623 + */
6624 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
6625 + * (2 ZettaBytes), high 32 bits
6626 + */
6627 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
6628 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
6629 +
6630 +
6631 +/* enumeration space related defs */
6632 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
6633 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
6634 +#define SB_MAXFUNCS 4 /* max. # functions per core */
6635 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
6636 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
6637 +
6638 +/* mips address */
6639 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
6640 +
6641 +/*
6642 + * Sonics Configuration Space Registers.
6643 + */
6644 +#define SBIPSFLAG 0x08
6645 +#define SBTPSFLAG 0x18
6646 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
6647 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
6648 +#define SBADMATCH3 0x60
6649 +#define SBADMATCH2 0x68
6650 +#define SBADMATCH1 0x70
6651 +#define SBIMSTATE 0x90
6652 +#define SBINTVEC 0x94
6653 +#define SBTMSTATELOW 0x98
6654 +#define SBTMSTATEHIGH 0x9c
6655 +#define SBBWA0 0xa0
6656 +#define SBIMCONFIGLOW 0xa8
6657 +#define SBIMCONFIGHIGH 0xac
6658 +#define SBADMATCH0 0xb0
6659 +#define SBTMCONFIGLOW 0xb8
6660 +#define SBTMCONFIGHIGH 0xbc
6661 +#define SBBCONFIG 0xc0
6662 +#define SBBSTATE 0xc8
6663 +#define SBACTCNFG 0xd8
6664 +#define SBFLAGST 0xe8
6665 +#define SBIDLOW 0xf8
6666 +#define SBIDHIGH 0xfc
6667 +
6668 +/* All the previous registers are above SBCONFIGOFF, but with Sonics 2.3, we have
6669 + * a few registers *below* that line. I think it would be very confusing to try
6670 + * and change the value of SBCONFIGOFF, so I'm definig them as absolute offsets here,
6671 + */
6672 +
6673 +#define SBIMERRLOGA 0xea8
6674 +#define SBIMERRLOG 0xeb0
6675 +#define SBTMPORTCONNID0 0xed8
6676 +#define SBTMPORTLOCK0 0xef8
6677 +
6678 +#ifndef _LANGUAGE_ASSEMBLY
6679 +
6680 +typedef volatile struct _sbconfig {
6681 + uint32 PAD[2];
6682 + uint32 sbipsflag; /* initiator port ocp slave flag */
6683 + uint32 PAD[3];
6684 + uint32 sbtpsflag; /* target port ocp slave flag */
6685 + uint32 PAD[11];
6686 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
6687 + uint32 PAD;
6688 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
6689 + uint32 PAD[3];
6690 + uint32 sbadmatch3; /* address match3 */
6691 + uint32 PAD;
6692 + uint32 sbadmatch2; /* address match2 */
6693 + uint32 PAD;
6694 + uint32 sbadmatch1; /* address match1 */
6695 + uint32 PAD[7];
6696 + uint32 sbimstate; /* initiator agent state */
6697 + uint32 sbintvec; /* interrupt mask */
6698 + uint32 sbtmstatelow; /* target state */
6699 + uint32 sbtmstatehigh; /* target state */
6700 + uint32 sbbwa0; /* bandwidth allocation table0 */
6701 + uint32 PAD;
6702 + uint32 sbimconfiglow; /* initiator configuration */
6703 + uint32 sbimconfighigh; /* initiator configuration */
6704 + uint32 sbadmatch0; /* address match0 */
6705 + uint32 PAD;
6706 + uint32 sbtmconfiglow; /* target configuration */
6707 + uint32 sbtmconfighigh; /* target configuration */
6708 + uint32 sbbconfig; /* broadcast configuration */
6709 + uint32 PAD;
6710 + uint32 sbbstate; /* broadcast state */
6711 + uint32 PAD[3];
6712 + uint32 sbactcnfg; /* activate configuration */
6713 + uint32 PAD[3];
6714 + uint32 sbflagst; /* current sbflags */
6715 + uint32 PAD[3];
6716 + uint32 sbidlow; /* identification */
6717 + uint32 sbidhigh; /* identification */
6718 +} sbconfig_t;
6719 +
6720 +#endif /* _LANGUAGE_ASSEMBLY */
6721 +
6722 +/* sbipsflag */
6723 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
6724 +#define SBIPS_INT1_SHIFT 0
6725 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
6726 +#define SBIPS_INT2_SHIFT 8
6727 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
6728 +#define SBIPS_INT3_SHIFT 16
6729 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
6730 +#define SBIPS_INT4_SHIFT 24
6731 +
6732 +/* sbtpsflag */
6733 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
6734 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
6735 +
6736 +/* sbtmerrlog */
6737 +#define SBTMEL_CM 0x00000007 /* command */
6738 +#define SBTMEL_CI 0x0000ff00 /* connection id */
6739 +#define SBTMEL_EC 0x0f000000 /* error code */
6740 +#define SBTMEL_ME 0x80000000 /* multiple error */
6741 +
6742 +/* sbimstate */
6743 +#define SBIM_PC 0xf /* pipecount */
6744 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
6745 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
6746 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
6747 +#define SBIM_AP_TK 0x20 /* use token only */
6748 +#define SBIM_AP_RSV 0x30 /* reserved */
6749 +#define SBIM_IBE 0x20000 /* inbanderror */
6750 +#define SBIM_TO 0x40000 /* timeout */
6751 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
6752 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
6753 +
6754 +/* sbtmstatelow */
6755 +#define SBTML_RESET 0x1 /* reset */
6756 +#define SBTML_REJ_MASK 0x6 /* reject */
6757 +#define SBTML_REJ_SHIFT 1
6758 +#define SBTML_CLK 0x10000 /* clock enable */
6759 +#define SBTML_FGC 0x20000 /* force gated clocks on */
6760 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
6761 +#define SBTML_PE 0x40000000 /* pme enable */
6762 +#define SBTML_BE 0x80000000 /* bist enable */
6763 +
6764 +/* sbtmstatehigh */
6765 +#define SBTMH_SERR 0x1 /* serror */
6766 +#define SBTMH_INT 0x2 /* interrupt */
6767 +#define SBTMH_BUSY 0x4 /* busy */
6768 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
6769 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
6770 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
6771 +#define SBTMH_GCR 0x20000000 /* gated clock request */
6772 +#define SBTMH_BISTF 0x40000000 /* bist failed */
6773 +#define SBTMH_BISTD 0x80000000 /* bist done */
6774 +
6775 +
6776 +/* sbbwa0 */
6777 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
6778 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
6779 +#define SBBWA_TAB1_SHIFT 16
6780 +
6781 +/* sbimconfiglow */
6782 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
6783 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
6784 +#define SBIMCL_RTO_SHIFT 4
6785 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
6786 +#define SBIMCL_CID_SHIFT 16
6787 +
6788 +/* sbimconfighigh */
6789 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
6790 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
6791 +#define SBIMCH_TEM_SHIFT 4
6792 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
6793 +#define SBIMCH_BEM_SHIFT 6
6794 +
6795 +/* sbadmatch0 */
6796 +#define SBAM_TYPE_MASK 0x3 /* address type */
6797 +#define SBAM_AD64 0x4 /* reserved */
6798 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
6799 +#define SBAM_ADINT0_SHIFT 3
6800 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
6801 +#define SBAM_ADINT1_SHIFT 3
6802 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
6803 +#define SBAM_ADINT2_SHIFT 3
6804 +#define SBAM_ADEN 0x400 /* enable */
6805 +#define SBAM_ADNEG 0x800 /* negative decode */
6806 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
6807 +#define SBAM_BASE0_SHIFT 8
6808 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
6809 +#define SBAM_BASE1_SHIFT 12
6810 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
6811 +#define SBAM_BASE2_SHIFT 16
6812 +
6813 +/* sbtmconfiglow */
6814 +#define SBTMCL_CD_MASK 0xff /* clock divide */
6815 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
6816 +#define SBTMCL_CO_SHIFT 11
6817 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
6818 +#define SBTMCL_IF_SHIFT 18
6819 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
6820 +#define SBTMCL_IM_SHIFT 24
6821 +
6822 +/* sbtmconfighigh */
6823 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
6824 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
6825 +#define SBTMCH_RM_SHIFT 2
6826 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
6827 +#define SBTMCH_SM_SHIFT 4
6828 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
6829 +#define SBTMCH_EM_SHIFT 8
6830 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
6831 +#define SBTMCH_IM_SHIFT 10
6832 +
6833 +/* sbbconfig */
6834 +#define SBBC_LAT_MASK 0x3 /* sb latency */
6835 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
6836 +#define SBBC_MAX0_SHIFT 16
6837 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
6838 +#define SBBC_MAX1_SHIFT 20
6839 +
6840 +/* sbbstate */
6841 +#define SBBS_SRD 0x1 /* st reg disable */
6842 +#define SBBS_HRD 0x2 /* hold reg disable */
6843 +
6844 +/* sbidlow */
6845 +#define SBIDL_CS_MASK 0x3 /* config space */
6846 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
6847 +#define SBIDL_AR_SHIFT 3
6848 +#define SBIDL_SYNCH 0x40 /* sync */
6849 +#define SBIDL_INIT 0x80 /* initiator */
6850 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
6851 +#define SBIDL_MINLAT_SHIFT 8
6852 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
6853 +#define SBIDL_MAXLAT_SHIFT 12
6854 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
6855 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
6856 +#define SBIDL_CW_SHIFT 18
6857 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
6858 +#define SBIDL_TP_SHIFT 20
6859 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
6860 +#define SBIDL_IP_SHIFT 24
6861 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
6862 +#define SBIDL_RV_SHIFT 28
6863 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
6864 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
6865 +
6866 +/* sbidhigh */
6867 +#define SBIDH_RC_MASK 0x000f /* revision code */
6868 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
6869 +#define SBIDH_RCE_SHIFT 8
6870 +#define SBCOREREV(sbidh) \
6871 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
6872 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
6873 +#define SBIDH_CC_SHIFT 4
6874 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
6875 +#define SBIDH_VC_SHIFT 16
6876 +
6877 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
6878 +
6879 +/* vendor codes */
6880 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
6881 +
6882 +/* core codes */
6883 +#define SB_NODEV 0x700 /* Invalid coreid */
6884 +#define SB_CC 0x800 /* chipcommon core */
6885 +#define SB_ILINE20 0x801 /* iline20 core */
6886 +#define SB_SDRAM 0x803 /* sdram core */
6887 +#define SB_PCI 0x804 /* pci core */
6888 +#define SB_MIPS 0x805 /* mips core */
6889 +#define SB_ENET 0x806 /* enet mac core */
6890 +#define SB_CODEC 0x807 /* v90 codec core */
6891 +#define SB_USB 0x808 /* usb 1.1 host/device core */
6892 +#define SB_ADSL 0x809 /* ADSL core */
6893 +#define SB_ILINE100 0x80a /* iline100 core */
6894 +#define SB_IPSEC 0x80b /* ipsec core */
6895 +#define SB_PCMCIA 0x80d /* pcmcia core */
6896 +#define SB_SDIOD SB_PCMCIA /* pcmcia core has sdio device */
6897 +#define SB_SOCRAM 0x80e /* internal memory core */
6898 +#define SB_MEMC 0x80f /* memc sdram core */
6899 +#define SB_EXTIF 0x811 /* external interface core */
6900 +#define SB_D11 0x812 /* 802.11 MAC core */
6901 +#define SB_MIPS33 0x816 /* mips3302 core */
6902 +#define SB_USB11H 0x817 /* usb 1.1 host core */
6903 +#define SB_USB11D 0x818 /* usb 1.1 device core */
6904 +#define SB_USB20H 0x819 /* usb 2.0 host core */
6905 +#define SB_USB20D 0x81a /* usb 2.0 device core */
6906 +#define SB_SDIOH 0x81b /* sdio host core */
6907 +#define SB_ROBO 0x81c /* roboswitch core */
6908 +#define SB_ATA100 0x81d /* parallel ATA core */
6909 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
6910 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
6911 +#define SB_PCIE 0x820 /* pci express core */
6912 +#define SB_MIMO 0x821 /* MIMO phy core */
6913 +#define SB_SRAMC 0x822 /* SRAM controller core */
6914 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
6915 +#define SB_ARM11 0x824 /* ARM 1176 core */
6916 +#define SB_ARM7 0x825 /* ARM 7tdmi core */
6917 +
6918 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
6919 +
6920 +/* Not really related to Silicon Backplane, but a couple of software
6921 + * conventions for the use the flash space:
6922 + */
6923 +
6924 +/* Minumum amount of flash we support */
6925 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
6926 +
6927 +/* A boot/binary may have an embedded block that describes its size */
6928 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
6929 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
6930 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
6931 +#define BISZ_TXTST_IDX 1 /* 1: text start */
6932 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
6933 +#define BISZ_DATAST_IDX 3 /* 3: text start */
6934 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
6935 +#define BISZ_BSSST_IDX 5 /* 5: text start */
6936 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
6937 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
6938 +
6939 +#endif /* _SBCONFIG_H */
6940 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
6941 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
6942 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2006-04-27 22:13:03.000000000 +0200
6943 @@ -0,0 +1,243 @@
6944 +/*
6945 + * Hardware-specific External Interface I/O core definitions
6946 + * for the BCM47xx family of SiliconBackplane-based chips.
6947 + *
6948 + * The External Interface core supports a total of three external chip selects
6949 + * supporting external interfaces. One of the external chip selects is
6950 + * used for Flash, one is used for PCMCIA, and the other may be
6951 + * programmed to support either a synchronous interface or an
6952 + * asynchronous interface. The asynchronous interface can be used to
6953 + * support external devices such as UARTs and the BCM2019 Bluetooth
6954 + * baseband processor.
6955 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
6956 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
6957 + *
6958 + * Copyright 2006, Broadcom Corporation
6959 + * All Rights Reserved.
6960 + *
6961 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6962 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6963 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6964 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6965 + *
6966 + * $Id: sbextif.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
6967 + */
6968 +
6969 +#ifndef _SBEXTIF_H
6970 +#define _SBEXTIF_H
6971 +
6972 +/* external interface address space */
6973 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
6974 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
6975 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
6976 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
6977 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
6978 +
6979 +/* cpp contortions to concatenate w/arg prescan */
6980 +#ifndef PAD
6981 +#define _PADLINE(line) pad ## line
6982 +#define _XSTR(line) _PADLINE(line)
6983 +#define PAD _XSTR(__LINE__)
6984 +#endif /* PAD */
6985 +
6986 +/*
6987 + * The multiple instances of output and output enable registers
6988 + * are present to allow driver software for multiple cores to control
6989 + * gpio outputs without needing to share a single register pair.
6990 + */
6991 +struct gpiouser {
6992 + uint32 out;
6993 + uint32 outen;
6994 +};
6995 +#define NGPIOUSER 5
6996 +
6997 +typedef volatile struct {
6998 + uint32 corecontrol;
6999 + uint32 extstatus;
7000 + uint32 PAD[2];
7001 +
7002 + /* pcmcia control registers */
7003 + uint32 pcmcia_config;
7004 + uint32 pcmcia_memwait;
7005 + uint32 pcmcia_attrwait;
7006 + uint32 pcmcia_iowait;
7007 +
7008 + /* programmable interface control registers */
7009 + uint32 prog_config;
7010 + uint32 prog_waitcount;
7011 +
7012 + /* flash control registers */
7013 + uint32 flash_config;
7014 + uint32 flash_waitcount;
7015 + uint32 PAD[4];
7016 +
7017 + uint32 watchdog;
7018 +
7019 + /* clock control */
7020 + uint32 clockcontrol_n;
7021 + uint32 clockcontrol_sb;
7022 + uint32 clockcontrol_pci;
7023 + uint32 clockcontrol_mii;
7024 + uint32 PAD[3];
7025 +
7026 + /* gpio */
7027 + uint32 gpioin;
7028 + struct gpiouser gpio[NGPIOUSER];
7029 + uint32 PAD;
7030 + uint32 ejtagouten;
7031 + uint32 gpiointpolarity;
7032 + uint32 gpiointmask;
7033 + uint32 PAD[153];
7034 +
7035 + uint8 uartdata;
7036 + uint8 PAD[3];
7037 + uint8 uartimer;
7038 + uint8 PAD[3];
7039 + uint8 uartfcr;
7040 + uint8 PAD[3];
7041 + uint8 uartlcr;
7042 + uint8 PAD[3];
7043 + uint8 uartmcr;
7044 + uint8 PAD[3];
7045 + uint8 uartlsr;
7046 + uint8 PAD[3];
7047 + uint8 uartmsr;
7048 + uint8 PAD[3];
7049 + uint8 uartscratch;
7050 + uint8 PAD[3];
7051 +} extifregs_t;
7052 +
7053 +/* corecontrol */
7054 +#define CC_UE (1 << 0) /* uart enable */
7055 +
7056 +/* extstatus */
7057 +#define ES_EM (1 << 0) /* endian mode (ro) */
7058 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7059 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7060 +
7061 +/* gpio bit mask */
7062 +#define GPIO_BIT0 (1 << 0)
7063 +#define GPIO_BIT1 (1 << 1)
7064 +#define GPIO_BIT2 (1 << 2)
7065 +#define GPIO_BIT3 (1 << 3)
7066 +#define GPIO_BIT4 (1 << 4)
7067 +#define GPIO_BIT5 (1 << 5)
7068 +#define GPIO_BIT6 (1 << 6)
7069 +#define GPIO_BIT7 (1 << 7)
7070 +
7071 +
7072 +/* pcmcia/prog/flash_config */
7073 +#define CF_EN (1 << 0) /* enable */
7074 +#define CF_EM_MASK 0xe /* mode */
7075 +#define CF_EM_SHIFT 1
7076 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7077 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7078 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7079 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7080 +#define CF_BS (1 << 5) /* byteswap */
7081 +#define CF_CD_MASK 0xc0 /* clock divider */
7082 +#define CF_CD_SHIFT 6
7083 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7084 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7085 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7086 +#define CF_CE (1 << 8) /* clock enable */
7087 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7088 +
7089 +/* pcmcia_memwait */
7090 +#define PM_W0_MASK 0x3f /* waitcount0 */
7091 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7092 +#define PM_W1_SHIFT 8
7093 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7094 +#define PM_W2_SHIFT 16
7095 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7096 +#define PM_W3_SHIFT 24
7097 +
7098 +/* pcmcia_attrwait */
7099 +#define PA_W0_MASK 0x3f /* waitcount0 */
7100 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7101 +#define PA_W1_SHIFT 8
7102 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7103 +#define PA_W2_SHIFT 16
7104 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7105 +#define PA_W3_SHIFT 24
7106 +
7107 +/* pcmcia_iowait */
7108 +#define PI_W0_MASK 0x3f /* waitcount0 */
7109 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7110 +#define PI_W1_SHIFT 8
7111 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7112 +#define PI_W2_SHIFT 16
7113 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7114 +#define PI_W3_SHIFT 24
7115 +
7116 +/* prog_waitcount */
7117 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7118 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7119 +#define PW_W1_SHIFT 8
7120 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7121 +#define PW_W2_SHIFT 16
7122 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7123 +#define PW_W3_SHIFT 24
7124 +
7125 +#define PW_W0 0x0000000c
7126 +#define PW_W1 0x00000a00
7127 +#define PW_W2 0x00020000
7128 +#define PW_W3 0x01000000
7129 +
7130 +/* flash_waitcount */
7131 +#define FW_W0_MASK 0x1f /* waitcount0 */
7132 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7133 +#define FW_W1_SHIFT 8
7134 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7135 +#define FW_W2_SHIFT 16
7136 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7137 +#define FW_W3_SHIFT 24
7138 +
7139 +/* watchdog */
7140 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7141 +
7142 +/* clockcontrol_n */
7143 +#define CN_N1_MASK 0x3f /* n1 control */
7144 +#define CN_N2_MASK 0x3f00 /* n2 control */
7145 +#define CN_N2_SHIFT 8
7146 +
7147 +/* clockcontrol_sb/pci/mii */
7148 +#define CC_M1_MASK 0x3f /* m1 control */
7149 +#define CC_M2_MASK 0x3f00 /* m2 control */
7150 +#define CC_M2_SHIFT 8
7151 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7152 +#define CC_M3_SHIFT 16
7153 +#define CC_MC_MASK 0x1f000000 /* mux control */
7154 +#define CC_MC_SHIFT 24
7155 +
7156 +/* Clock control default values */
7157 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7158 +#define CC_DEF_100 0x04020011
7159 +#define CC_DEF_33 0x11030011
7160 +#define CC_DEF_25 0x11050011
7161 +
7162 +/* Clock control values for 125Mhz */
7163 +#define CC_125_N 0x0802
7164 +#define CC_125_M 0x04020009
7165 +#define CC_125_M25 0x11090009
7166 +#define CC_125_M33 0x11090005
7167 +
7168 +/* Clock control magic field values */
7169 +#define CC_F6_2 0x02 /* A factor of 2 in */
7170 +#define CC_F6_3 0x03 /* 6-bit fields like */
7171 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7172 +#define CC_F6_5 0x09
7173 +#define CC_F6_6 0x11
7174 +#define CC_F6_7 0x21
7175 +
7176 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7177 +
7178 +#define CC_MC_BYPASS 0x08
7179 +#define CC_MC_M1 0x04
7180 +#define CC_MC_M1M2 0x02
7181 +#define CC_MC_M1M2M3 0x01
7182 +#define CC_MC_M1M3 0x11
7183 +
7184 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7185 +
7186 +#endif /* _SBEXTIF_H */
7187 diff -urN linux.old/arch/mips/bcm947xx/include/sbhndmips.h linux.dev/arch/mips/bcm947xx/include/sbhndmips.h
7188 --- linux.old/arch/mips/bcm947xx/include/sbhndmips.h 1970-01-01 01:00:00.000000000 +0100
7189 +++ linux.dev/arch/mips/bcm947xx/include/sbhndmips.h 2006-04-27 20:43:56.000000000 +0200
7190 @@ -0,0 +1,47 @@
7191 +/*
7192 + * Broadcom SiliconBackplane MIPS definitions
7193 + *
7194 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
7195 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
7196 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7197 + * interface. The core revision is stored in the SB ID register in SB
7198 + * configuration space.
7199 + *
7200 + * Copyright 2006, Broadcom Corporation
7201 + * All Rights Reserved.
7202 + *
7203 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7204 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7205 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7206 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7207 + *
7208 + * $Id: sbhndmips.h,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
7209 + */
7210 +
7211 +#ifndef _sbhndmips_h_
7212 +#define _sbhndmips_h_
7213 +
7214 +#include <mipsinc.h>
7215 +
7216 +#ifndef _LANGUAGE_ASSEMBLY
7217 +
7218 +/* cpp contortions to concatenate w/arg prescan */
7219 +#ifndef PAD
7220 +#define _PADLINE(line) pad ## line
7221 +#define _XSTR(line) _PADLINE(line)
7222 +#define PAD _XSTR(__LINE__)
7223 +#endif /* PAD */
7224 +
7225 +typedef volatile struct {
7226 + uint32 corecontrol;
7227 + uint32 PAD[2];
7228 + uint32 biststatus;
7229 + uint32 PAD[4];
7230 + uint32 intstatus;
7231 + uint32 intmask;
7232 + uint32 timer;
7233 +} mipsregs_t;
7234 +
7235 +#endif /* _LANGUAGE_ASSEMBLY */
7236 +
7237 +#endif /* _sbhndmips_h_ */
7238 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7239 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7240 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2006-04-27 22:12:41.000000000 +0200
7241 @@ -0,0 +1,147 @@
7242 +/*
7243 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7244 + *
7245 + * Copyright 2006, Broadcom Corporation
7246 + * All Rights Reserved.
7247 + *
7248 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7249 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7250 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7251 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7252 + *
7253 + * $Id: sbmemc.h,v 1.6 2006/03/02 12:33:44 honor Exp $
7254 + */
7255 +
7256 +#ifndef _SBMEMC_H
7257 +#define _SBMEMC_H
7258 +
7259 +#ifdef _LANGUAGE_ASSEMBLY
7260 +
7261 +#define MEMC_CONTROL 0x00
7262 +#define MEMC_CONFIG 0x04
7263 +#define MEMC_REFRESH 0x08
7264 +#define MEMC_BISTSTAT 0x0c
7265 +#define MEMC_MODEBUF 0x10
7266 +#define MEMC_BKCLS 0x14
7267 +#define MEMC_PRIORINV 0x18
7268 +#define MEMC_DRAMTIM 0x1c
7269 +#define MEMC_INTSTAT 0x20
7270 +#define MEMC_INTMASK 0x24
7271 +#define MEMC_INTINFO 0x28
7272 +#define MEMC_NCDLCTL 0x30
7273 +#define MEMC_RDNCDLCOR 0x34
7274 +#define MEMC_WRNCDLCOR 0x38
7275 +#define MEMC_MISCDLYCTL 0x3c
7276 +#define MEMC_DQSGATENCDL 0x40
7277 +#define MEMC_SPARE 0x44
7278 +#define MEMC_TPADDR 0x48
7279 +#define MEMC_TPDATA 0x4c
7280 +#define MEMC_BARRIER 0x50
7281 +#define MEMC_CORE 0x54
7282 +
7283 +#else /* !_LANGUAGE_ASSEMBLY */
7284 +
7285 +/* Sonics side: MEMC core registers */
7286 +typedef volatile struct sbmemcregs {
7287 + uint32 control;
7288 + uint32 config;
7289 + uint32 refresh;
7290 + uint32 biststat;
7291 + uint32 modebuf;
7292 + uint32 bkcls;
7293 + uint32 priorinv;
7294 + uint32 dramtim;
7295 + uint32 intstat;
7296 + uint32 intmask;
7297 + uint32 intinfo;
7298 + uint32 reserved1;
7299 + uint32 ncdlctl;
7300 + uint32 rdncdlcor;
7301 + uint32 wrncdlcor;
7302 + uint32 miscdlyctl;
7303 + uint32 dqsgatencdl;
7304 + uint32 spare;
7305 + uint32 tpaddr;
7306 + uint32 tpdata;
7307 + uint32 barrier;
7308 + uint32 core;
7309 +} sbmemcregs_t;
7310 +
7311 +#endif /* _LANGUAGE_ASSEMBLY */
7312 +
7313 +/* MEMC Core Init values (OCP ID 0x80f) */
7314 +
7315 +/* For sdr: */
7316 +#define MEMC_SD_CONFIG_INIT 0x00048000
7317 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
7318 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
7319 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
7320 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
7321 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
7322 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
7323 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
7324 +#define MEMC_SD_CONTROL_INIT0 0x00000002
7325 +#define MEMC_SD_CONTROL_INIT1 0x00000008
7326 +#define MEMC_SD_CONTROL_INIT2 0x00000004
7327 +#define MEMC_SD_CONTROL_INIT3 0x00000010
7328 +#define MEMC_SD_CONTROL_INIT4 0x00000001
7329 +#define MEMC_SD_MODEBUF_INIT 0x00000000
7330 +#define MEMC_SD_REFRESH_INIT 0x0000840f
7331 +
7332 +
7333 +/* This is for SDRM8X8X4 */
7334 +#define MEMC_SDR_INIT 0x0008
7335 +#define MEMC_SDR_MODE 0x32
7336 +#define MEMC_SDR_NCDL 0x00020032
7337 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
7338 +
7339 +/* For ddr: */
7340 +#define MEMC_CONFIG_INIT 0x00048000
7341 +#define MEMC_DRAMTIM2_INIT 0x000754d8
7342 +#define MEMC_DRAMTIM25_INIT 0x000754d9
7343 +#define MEMC_RDNCDLCOR_INIT 0x00000000
7344 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
7345 +#define MEMC_WRNCDLCOR_INIT 0x49351200
7346 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
7347 +#define MEMC_DQSGATENCDL_INIT 0x00030000
7348 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
7349 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
7350 +#define MEMC_NCDLCTL_INIT 0x00002001
7351 +#define MEMC_CONTROL_INIT0 0x00000002
7352 +#define MEMC_CONTROL_INIT1 0x00000008
7353 +#define MEMC_MODEBUF_INIT0 0x00004000
7354 +#define MEMC_CONTROL_INIT2 0x00000010
7355 +#define MEMC_MODEBUF_INIT1 0x00000100
7356 +#define MEMC_CONTROL_INIT3 0x00000010
7357 +#define MEMC_CONTROL_INIT4 0x00000008
7358 +#define MEMC_REFRESH_INIT 0x0000840f
7359 +#define MEMC_CONTROL_INIT5 0x00000004
7360 +#define MEMC_MODEBUF_INIT2 0x00000000
7361 +#define MEMC_CONTROL_INIT6 0x00000010
7362 +#define MEMC_CONTROL_INIT7 0x00000001
7363 +
7364 +
7365 +/* This is for DDRM16X16X2 */
7366 +#define MEMC_DDR_INIT 0x0009
7367 +#define MEMC_DDR_MODE 0x62
7368 +#define MEMC_DDR_NCDL 0x0005050a
7369 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
7370 +
7371 +/* mask for sdr/ddr calibration registers */
7372 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
7373 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
7374 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
7375 +
7376 +/* masks for miscdlyctl registers */
7377 +#define MEMC_MISC_SM_MASK 0x30000000
7378 +#define MEMC_MISC_SM_SHIFT 28
7379 +#define MEMC_MISC_SD_MASK 0x0f000000
7380 +#define MEMC_MISC_SD_SHIFT 24
7381 +
7382 +/* hw threshhold for calculating wr/rd for sdr memc */
7383 +#define MEMC_CD_THRESHOLD 128
7384 +
7385 +/* Low bit of init register says if memc is ddr or sdr */
7386 +#define MEMC_CONFIG_DDR 0x00000001
7387 +
7388 +#endif /* _SBMEMC_H */
7389 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
7390 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
7391 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2006-05-02 17:20:14.000000000 +0200
7392 @@ -0,0 +1,114 @@
7393 +/*
7394 + * HND SiliconBackplane PCI core hardware definitions.
7395 + *
7396 + * Copyright 2006, Broadcom Corporation
7397 + * All Rights Reserved.
7398 + *
7399 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7400 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7401 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7402 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7403 + *
7404 + * $Id: sbpci.h,v 1.1.1.11 2006/02/27 03:43:16 honor Exp $
7405 + */
7406 +
7407 +#ifndef _sbpci_h_
7408 +#define _sbpci_h_
7409 +
7410 +#ifndef _LANGUAGE_ASSEMBLY
7411 +
7412 +/* cpp contortions to concatenate w/arg prescan */
7413 +#ifndef PAD
7414 +#define _PADLINE(line) pad ## line
7415 +#define _XSTR(line) _PADLINE(line)
7416 +#define PAD _XSTR(__LINE__)
7417 +#endif
7418 +
7419 +/* Sonics side: PCI core and host control registers */
7420 +typedef struct sbpciregs {
7421 + uint32 control; /* PCI control */
7422 + uint32 PAD[3];
7423 + uint32 arbcontrol; /* PCI arbiter control */
7424 + uint32 PAD[3];
7425 + uint32 intstatus; /* Interrupt status */
7426 + uint32 intmask; /* Interrupt mask */
7427 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
7428 + uint32 PAD[9];
7429 + uint32 bcastaddr; /* Sonics broadcast address */
7430 + uint32 bcastdata; /* Sonics broadcast data */
7431 + uint32 PAD[2];
7432 + uint32 gpioin; /* ro: gpio input (>=rev2) */
7433 + uint32 gpioout; /* rw: gpio output (>=rev2) */
7434 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
7435 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
7436 + uint32 PAD[36];
7437 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
7438 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
7439 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
7440 + uint32 PAD[189];
7441 + uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
7442 + uint16 sprom[36]; /* SPROM shadow Area */
7443 + uint32 PAD[46];
7444 +} sbpciregs_t;
7445 +
7446 +#endif /* _LANGUAGE_ASSEMBLY */
7447 +
7448 +/* PCI control */
7449 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
7450 +#define PCI_RST 0x02 /* Value driven out to pin */
7451 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
7452 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
7453 +
7454 +/* PCI arbiter control */
7455 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
7456 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
7457 +/* ParkID - for PCI corerev >= 8 */
7458 +#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
7459 +#define PCI_PARKID_SHIFT 2
7460 +#define PCI_PARKID_EXT0 0 /* External master 0 */
7461 +#define PCI_PARKID_EXT1 1 /* External master 1 */
7462 +#define PCI_PARKID_EXT2 2 /* External master 2 */
7463 +#define PCI_PARKID_INT 3 /* Internal master */
7464 +#define PCI_PARKID_LAST 4 /* Last active master */
7465 +
7466 +/* Interrupt status/mask */
7467 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
7468 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
7469 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
7470 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
7471 +#define PCI_PME 0x10 /* PCI PME# is asserted */
7472 +
7473 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
7474 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
7475 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
7476 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
7477 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
7478 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
7479 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
7480 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
7481 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
7482 +
7483 +/* Sonics broadcast address */
7484 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
7485 +
7486 +/* Sonics to PCI translation types */
7487 +#define SBTOPCI0_MASK 0xfc000000
7488 +#define SBTOPCI1_MASK 0xfc000000
7489 +#define SBTOPCI2_MASK 0xc0000000
7490 +#define SBTOPCI_MEM 0
7491 +#define SBTOPCI_IO 1
7492 +#define SBTOPCI_CFG0 2
7493 +#define SBTOPCI_CFG1 3
7494 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
7495 +#define SBTOPCI_BURST 0x8 /* burst enable */
7496 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
7497 +#define SBTOPCI_RC_READ 0x00 /* memory read */
7498 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
7499 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
7500 +
7501 +/* PCI core index in SROM shadow area */
7502 +#define SRSH_PI_OFFSET 0 /* first word */
7503 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
7504 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
7505 +
7506 +#endif /* _sbpci_h_ */
7507 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
7508 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
7509 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2006-04-27 20:42:22.000000000 +0200
7510 @@ -0,0 +1,200 @@
7511 +/*
7512 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
7513 + *
7514 + * Copyright 2006, Broadcom Corporation
7515 + * All Rights Reserved.
7516 + *
7517 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7518 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7519 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7520 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7521 + *
7522 + * $Id: sbpcie.h,v 1.1.1.2 2006/02/27 03:43:16 honor Exp $
7523 + */
7524 +
7525 +#ifndef _SBPCIE_H
7526 +#define _SBPCIE_H
7527 +
7528 +/* cpp contortions to concatenate w/arg prescan */
7529 +#ifndef PAD
7530 +#define _PADLINE(line) pad ## line
7531 +#define _XSTR(line) _PADLINE(line)
7532 +#define PAD _XSTR(__LINE__)
7533 +#endif
7534 +
7535 +/* PCIE Enumeration space offsets */
7536 +#define PCIE_CORE_CONFIG_OFFSET 0x0
7537 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
7538 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
7539 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
7540 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
7541 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
7542 +#define PCIE_SBCONFIG_OFFSET 0xE00
7543 +
7544 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
7545 +#define PCIE_DEV_BAR0_SIZE 0x4000
7546 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
7547 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
7548 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
7549 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
7550 +
7551 +/* SB side: PCIE core and host control registers */
7552 +typedef struct sbpcieregs {
7553 + uint32 PAD[3];
7554 + uint32 biststatus; /* bist Status: 0x00C */
7555 + uint32 PAD[6];
7556 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
7557 + uint32 PAD[54];
7558 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
7559 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
7560 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
7561 + uint32 PAD[4];
7562 +
7563 + /* pcie core supports in direct access to config space */
7564 + uint32 configaddr; /* pcie config space access: Address field: 0x120 */
7565 + uint32 configdata; /* pcie config space access: Data field: 0x124 */
7566 +
7567 + /* mdio access to serdes */
7568 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
7569 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
7570 +
7571 + /* pcie protocol phy/dllp/tlp register access mechanism */
7572 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
7573 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
7574 +
7575 + uint32 PAD[434];
7576 + uint16 sprom[36]; /* SPROM shadow Area */
7577 +} sbpcieregs_t;
7578 +
7579 +/* SB to PCIE translation masks */
7580 +#define SBTOPCIE0_MASK 0xfc000000
7581 +#define SBTOPCIE1_MASK 0xfc000000
7582 +#define SBTOPCIE2_MASK 0xc0000000
7583 +
7584 +/* Access type bits (0:1) */
7585 +#define SBTOPCIE_MEM 0
7586 +#define SBTOPCIE_IO 1
7587 +#define SBTOPCIE_CFG0 2
7588 +#define SBTOPCIE_CFG1 3
7589 +
7590 +/* Prefetch enable bit 2 */
7591 +#define SBTOPCIE_PF 4
7592 +
7593 +/* Write Burst enable for memory write bit 3 */
7594 +#define SBTOPCIE_WR_BURST 8
7595 +
7596 +/* config access */
7597 +#define CONFIGADDR_FUNC_MASK 0x7000
7598 +#define CONFIGADDR_FUNC_SHF 12
7599 +#define CONFIGADDR_REG_MASK 0x0FFF
7600 +#define CONFIGADDR_REG_SHF 0
7601 +
7602 +/* PCIE protocol regs Indirect Address */
7603 +#define PCIEADDR_PROT_MASK 0x300
7604 +#define PCIEADDR_PROT_SHF 8
7605 +#define PCIEADDR_PL_TLP 0
7606 +#define PCIEADDR_PL_DLLP 1
7607 +#define PCIEADDR_PL_PLP 2
7608 +
7609 +/* PCIE protocol PHY diagnostic registers */
7610 +#define PCIE_PLP_MODEREG 0x200 /* Mode */
7611 +#define PCIE_PLP_STATUSREG 0x204 /* Status */
7612 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
7613 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
7614 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
7615 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
7616 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
7617 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
7618 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
7619 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
7620 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
7621 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
7622 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
7623 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
7624 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
7625 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
7626 +
7627 +/* PCIE protocol DLLP diagnostic registers */
7628 +#define PCIE_DLLP_LCREG 0x100 /* Link Control */
7629 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
7630 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
7631 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
7632 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
7633 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
7634 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
7635 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
7636 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
7637 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
7638 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
7639 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
7640 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
7641 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
7642 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
7643 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
7644 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
7645 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
7646 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
7647 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
7648 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
7649 +
7650 +/* PCIE protocol TLP diagnostic registers */
7651 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
7652 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
7653 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
7654 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
7655 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
7656 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
7657 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
7658 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
7659 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
7660 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
7661 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
7662 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
7663 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
7664 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
7665 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
7666 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
7667 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
7668 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
7669 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
7670 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
7671 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
7672 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
7673 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
7674 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
7675 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
7676 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
7677 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
7678 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
7679 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
7680 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
7681 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
7682 +
7683 +/* MDIO control */
7684 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
7685 +#define MDIOCTL_DIVISOR_VAL 0x2
7686 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
7687 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
7688 +
7689 +/* MDIO Data */
7690 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
7691 +#define MDIODATA_TA 0x00020000 /* Turnaround */
7692 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
7693 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
7694 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
7695 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
7696 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
7697 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
7698 +#define MDIODATA_START 0x40000000 /* start of Transaction */
7699 +
7700 +/* MDIO devices (SERDES modules) */
7701 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
7702 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
7703 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
7704 +
7705 +/* SERDES registers */
7706 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
7707 +#define SERDES_RX_CDR 6 /* CDR */
7708 +#define SERDES_RX_CDRBW 7 /* CDR BW */
7709 +
7710 +#endif /* _SBPCIE_H */
7711 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
7712 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
7713 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2006-04-27 20:29:47.000000000 +0200
7714 @@ -0,0 +1,147 @@
7715 +/*
7716 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
7717 + *
7718 + * Copyright 2006, Broadcom Corporation
7719 + * All Rights Reserved.
7720 + *
7721 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7722 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7723 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7724 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7725 + *
7726 + * $Id: sbpcmcia.h,v 1.1.1.9 2006/02/27 03:43:16 honor Exp $
7727 + */
7728 +
7729 +#ifndef _SBPCMCIA_H
7730 +#define _SBPCMCIA_H
7731 +
7732 +
7733 +/* All the addresses that are offsets in attribute space are divided
7734 + * by two to account for the fact that odd bytes are invalid in
7735 + * attribute space and our read/write routines make the space appear
7736 + * as if they didn't exist. Still we want to show the original numbers
7737 + * as documented in the hnd_pcmcia core manual.
7738 + */
7739 +
7740 +/* PCMCIA Function Configuration Registers */
7741 +#define PCMCIA_FCR (0x700 / 2)
7742 +
7743 +#define FCR0_OFF 0
7744 +#define FCR1_OFF (0x40 / 2)
7745 +#define FCR2_OFF (0x80 / 2)
7746 +#define FCR3_OFF (0xc0 / 2)
7747 +
7748 +#define PCMCIA_FCR0 (0x700 / 2)
7749 +#define PCMCIA_FCR1 (0x740 / 2)
7750 +#define PCMCIA_FCR2 (0x780 / 2)
7751 +#define PCMCIA_FCR3 (0x7c0 / 2)
7752 +
7753 +/* Standard PCMCIA FCR registers */
7754 +
7755 +#define PCMCIA_COR 0
7756 +
7757 +#define COR_RST 0x80
7758 +#define COR_LEV 0x40
7759 +#define COR_IRQEN 0x04
7760 +#define COR_BLREN 0x01
7761 +#define COR_FUNEN 0x01
7762 +
7763 +
7764 +#define PCICIA_FCSR (2 / 2)
7765 +#define PCICIA_PRR (4 / 2)
7766 +#define PCICIA_SCR (6 / 2)
7767 +#define PCICIA_ESR (8 / 2)
7768 +
7769 +
7770 +#define PCM_MEMOFF 0x0000
7771 +#define F0_MEMOFF 0x1000
7772 +#define F1_MEMOFF 0x2000
7773 +#define F2_MEMOFF 0x3000
7774 +#define F3_MEMOFF 0x4000
7775 +
7776 +/* Memory base in the function fcr's */
7777 +#define MEM_ADDR0 (0x728 / 2)
7778 +#define MEM_ADDR1 (0x72a / 2)
7779 +#define MEM_ADDR2 (0x72c / 2)
7780 +
7781 +/* PCMCIA base plus Srom access in fcr0: */
7782 +#define PCMCIA_ADDR0 (0x072e / 2)
7783 +#define PCMCIA_ADDR1 (0x0730 / 2)
7784 +#define PCMCIA_ADDR2 (0x0732 / 2)
7785 +
7786 +#define MEM_SEG (0x0734 / 2)
7787 +#define SROM_CS (0x0736 / 2)
7788 +#define SROM_DATAL (0x0738 / 2)
7789 +#define SROM_DATAH (0x073a / 2)
7790 +#define SROM_ADDRL (0x073c / 2)
7791 +#define SROM_ADDRH (0x073e / 2)
7792 +
7793 +/* Values for srom_cs: */
7794 +#define SROM_IDLE 0
7795 +#define SROM_WRITE 1
7796 +#define SROM_READ 2
7797 +#define SROM_WEN 4
7798 +#define SROM_WDS 7
7799 +#define SROM_DONE 8
7800 +
7801 +/* CIS stuff */
7802 +
7803 +/* The CIS stops where the FCRs start */
7804 +#define CIS_SIZE PCMCIA_FCR
7805 +
7806 +/* Standard tuples we know about */
7807 +
7808 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
7809 +#define CISTPL_FUNCE 0x22 /* Function extensions */
7810 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
7811 +
7812 +/* Function extensions for LANs */
7813 +
7814 +#define LAN_TECH 1 /* Technology type */
7815 +#define LAN_SPEED 2 /* Raw bit rate */
7816 +#define LAN_MEDIA 3 /* Transmission media */
7817 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
7818 +#define LAN_CONN 5 /* Connector standard */
7819 +
7820 +
7821 +/* CFTable */
7822 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
7823 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
7824 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
7825 +
7826 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
7827 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
7828 + */
7829 +
7830 +#define CISTPL_BRCM_HNBU 0x80
7831 +
7832 +/* Subtypes of BRCM_HNBU: */
7833 +
7834 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
7835 +#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
7836 +#define HNBU_BOARDREV 0x02 /* One byte board revision */
7837 +#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
7838 + * or 9 (sromrev > 1) bytes
7839 + */
7840 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
7841 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
7842 +#define HNBU_AA 0x06 /* Antennas available */
7843 +#define HNBU_AG 0x07 /* Antenna gain */
7844 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
7845 +#define HNBU_LEDS 0x09 /* LED set */
7846 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
7847 + * in rev 2
7848 + */
7849 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
7850 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
7851 +#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
7852 +
7853 +
7854 +/* sbtmstatelow */
7855 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
7856 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
7857 +
7858 +/* sbtmstatehigh */
7859 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
7860 +
7861 +#endif /* _SBPCMCIA_H */
7862 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
7863 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
7864 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2006-04-27 20:36:08.000000000 +0200
7865 @@ -0,0 +1,85 @@
7866 +/*
7867 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
7868 + *
7869 + * Copyright 2006, Broadcom Corporation
7870 + * All Rights Reserved.
7871 + *
7872 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7873 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7874 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7875 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7876 + *
7877 + * $Id: sbsdram.h,v 1.1.1.9 2006/03/02 13:03:52 honor Exp $
7878 + */
7879 +
7880 +#ifndef _SBSDRAM_H
7881 +#define _SBSDRAM_H
7882 +
7883 +#ifndef _LANGUAGE_ASSEMBLY
7884 +
7885 +/* Sonics side: SDRAM core registers */
7886 +typedef volatile struct sbsdramregs {
7887 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
7888 + uint32 config; /* Initializes external SDRAM mode register */
7889 + uint32 refresh; /* Controls external SDRAM refresh rate */
7890 + uint32 pad1;
7891 + uint32 pad2;
7892 +} sbsdramregs_t;
7893 +
7894 +/* SDRAM simulation */
7895 +#ifdef RAMSZ
7896 +#define SDRAMSZ RAMSZ
7897 +#else
7898 +#define SDRAMSZ (4 * 1024 * 1024)
7899 +#endif
7900 +
7901 +extern uchar sdrambuf[SDRAMSZ];
7902 +
7903 +#endif /* _LANGUAGE_ASSEMBLY */
7904 +
7905 +/* SDRAM initialization control (initcontrol) register bits */
7906 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
7907 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
7908 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
7909 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
7910 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
7911 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
7912 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
7913 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
7914 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
7915 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
7916 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
7917 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
7918 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
7919 +
7920 +/* SDRAM configuration (config) register bits */
7921 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
7922 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
7923 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
7924 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
7925 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
7926 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
7927 +
7928 +/* SDRAM refresh control (refresh) register bits */
7929 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
7930 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
7931 +
7932 +/* SDRAM Core default Init values (OCP ID 0x803) */
7933 +#define SDRAM_INIT MEM4MX16X2
7934 +#define SDRAM_CONFIG SDRAM_BURSTFULL
7935 +#define SDRAM_REFRESH SDRAM_REF(0x40)
7936 +
7937 +#define MEM1MX16 0x009 /* 2 MB */
7938 +#define MEM1MX16X2 0x409 /* 4 MB */
7939 +#define MEM2MX8X2 0x809 /* 4 MB */
7940 +#define MEM2MX8X4 0xc09 /* 8 MB */
7941 +#define MEM2MX32 0x439 /* 8 MB */
7942 +#define MEM4MX16 0x019 /* 8 MB */
7943 +#define MEM4MX16X2 0x419 /* 16 MB */
7944 +#define MEM8MX8X2 0x819 /* 16 MB */
7945 +#define MEM8MX16 0x829 /* 16 MB */
7946 +#define MEM4MX32 0x429 /* 16 MB */
7947 +#define MEM8MX8X4 0xc19 /* 32 MB */
7948 +#define MEM8MX16X2 0xc29 /* 32 MB */
7949 +
7950 +#endif /* _SBSDRAM_H */
7951 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
7952 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
7953 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2006-04-27 22:13:19.000000000 +0200
7954 @@ -0,0 +1,64 @@
7955 +/*
7956 + * BCM47XX Sonics SiliconBackplane embedded ram core
7957 + *
7958 + * Copyright 2006, Broadcom Corporation
7959 + * All Rights Reserved.
7960 + *
7961 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7962 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7963 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7964 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7965 + *
7966 + * $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
7967 + */
7968 +
7969 +#ifndef _SBSOCRAM_H
7970 +#define _SBSOCRAM_H
7971 +
7972 +#define SR_COREINFO 0x00
7973 +#define SR_BWALLOC 0x04
7974 +#define SR_BISTSTAT 0x0c
7975 +#define SR_BANKINDEX 0x10
7976 +#define SR_BANKSTBYCTL 0x14
7977 +
7978 +
7979 +#ifndef _LANGUAGE_ASSEMBLY
7980 +
7981 +/* Memcsocram core registers */
7982 +typedef volatile struct sbsocramregs {
7983 + uint32 coreinfo;
7984 + uint32 bwalloc;
7985 + uint32 PAD;
7986 + uint32 biststat;
7987 + uint32 bankidx;
7988 + uint32 standbyctrl;
7989 +} sbsocramregs_t;
7990 +
7991 +#endif
7992 +
7993 +/* Coreinfo register */
7994 +#define SRCI_PT_MASK 0x30000
7995 +#define SRCI_PT_SHIFT 16
7996 +
7997 +/* In corerev 0, the memory size is 2 to the power of the
7998 + * base plus 16 plus to the contents of the memsize field plus 1.
7999 + */
8000 +#define SRCI_MS0_MASK 0xf
8001 +#define SR_MS0_BASE 16
8002 +
8003 +/*
8004 + * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
8005 + * the memory size is number of banks times bank size.
8006 + * The same applies to rom size.
8007 + */
8008 +#define SRCI_ROMNB_MASK 0xf000
8009 +#define SRCI_ROMNB_SHIFT 12
8010 +#define SRCI_ROMBSZ_MASK 0xf00
8011 +#define SRCI_ROMBSZ_SHIFT 8
8012 +#define SRCI_SRNB_MASK 0xf0
8013 +#define SRCI_SRNB_SHIFT 4
8014 +#define SRCI_SRBSZ_MASK 0xf
8015 +#define SRCI_SRBSZ_SHIFT 0
8016 +
8017 +#define SR_BSZ_BASE 14
8018 +#endif /* _SBSOCRAM_H */
8019 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
8020 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
8021 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2006-04-27 23:09:25.000000000 +0200
8022 @@ -0,0 +1,150 @@
8023 +/*
8024 + * Misc utility routines for accessing chip-specific features
8025 + * of Broadcom HNBU SiliconBackplane-based chips.
8026 + *
8027 + * Copyright 2006, Broadcom Corporation
8028 + * All Rights Reserved.
8029 + *
8030 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8031 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8032 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8033 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8034 + *
8035 + * $Id: sbutils.h,v 1.4 2006/04/08 07:12:42 honor Exp $
8036 + */
8037 +
8038 +#ifndef _sbutils_h_
8039 +#define _sbutils_h_
8040 +
8041 +/*
8042 + * Datastructure to export all chip specific common variables
8043 + * public (read-only) portion of sbutils handle returned by
8044 + * sb_attach()/sb_kattach()
8045 +*/
8046 +
8047 +struct sb_pub {
8048 +
8049 + uint bustype; /* SB_BUS, PCI_BUS */
8050 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE */
8051 + uint buscorerev; /* buscore rev */
8052 + uint buscoreidx; /* buscore index */
8053 + int ccrev; /* chip common core rev */
8054 + uint boardtype; /* board type */
8055 + uint boardvendor; /* board vendor */
8056 + uint chip; /* chip number */
8057 + uint chiprev; /* chip revision */
8058 + uint chippkg; /* chip package option */
8059 + uint sonicsrev; /* sonics backplane rev */
8060 +};
8061 +
8062 +typedef const struct sb_pub sb_t;
8063 +
8064 +/*
8065 + * Many of the routines below take an 'sbh' handle as their first arg.
8066 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8067 + * At any one time, the sbh is logically focused on one particular sb core
8068 + * (the "current core").
8069 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8070 + */
8071 +
8072 +#define SB_OSH NULL /* Use for sb_kattach when no osh is available */
8073 +/* exported externs */
8074 +extern sb_t *sb_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
8075 + void *sdh, char **vars, uint *varsz);
8076 +extern sb_t *sb_kattach(void);
8077 +extern void sb_detach(sb_t *sbh);
8078 +extern uint sb_chip(sb_t *sbh);
8079 +extern uint sb_chiprev(sb_t *sbh);
8080 +extern uint sb_chipcrev(sb_t *sbh);
8081 +extern uint sb_chippkg(sb_t *sbh);
8082 +extern uint sb_pcirev(sb_t *sbh);
8083 +extern bool sb_war16165(sb_t *sbh);
8084 +extern uint sb_pcmciarev(sb_t *sbh);
8085 +extern uint sb_boardvendor(sb_t *sbh);
8086 +extern uint sb_boardtype(sb_t *sbh);
8087 +extern uint sb_bus(sb_t *sbh);
8088 +extern uint sb_buscoretype(sb_t *sbh);
8089 +extern uint sb_buscorerev(sb_t *sbh);
8090 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8091 +extern uint sb_coreid(sb_t *sbh);
8092 +extern uint sb_coreidx(sb_t *sbh);
8093 +extern uint sb_coreunit(sb_t *sbh);
8094 +extern uint sb_corevendor(sb_t *sbh);
8095 +extern uint sb_corerev(sb_t *sbh);
8096 +extern void *sb_osh(sb_t *sbh);
8097 +extern void sb_setosh(sb_t *sbh, osl_t *osh);
8098 +extern void *sb_coreregs(sb_t *sbh);
8099 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8100 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8101 +extern bool sb_iscoreup(sb_t *sbh);
8102 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8103 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8104 +extern int sb_corebist(sb_t *sbh);
8105 +extern void sb_commit(sb_t *sbh);
8106 +extern uint32 sb_base(uint32 admatch);
8107 +extern uint32 sb_size(uint32 admatch);
8108 +extern void sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits);
8109 +extern void sb_core_tofixup(sb_t *sbh);
8110 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8111 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8112 +extern uint32 sb_clock(sb_t *sbh);
8113 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8114 +extern void sb_pcmcia_init(sb_t *sbh);
8115 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8116 +extern void *sb_gpiosetcore(sb_t *sbh);
8117 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8118 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8119 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8120 +extern uint32 sb_gpioin(sb_t *sbh);
8121 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8122 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8123 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8124 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8125 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8126 +
8127 +extern void sb_clkctl_init(sb_t *sbh);
8128 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8129 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8130 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8131 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
8132 + void *intrsenabled_fn, void *intr_arg);
8133 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8134 +extern int sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
8135 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
8136 + uint8 *pciheader);
8137 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8138 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8139 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8140 +extern bool sb_backplane64(sb_t *sbh);
8141 +extern void sb_btcgpiowar(sb_t *sbh);
8142 +
8143 +
8144 +
8145 +
8146 +extern bool sb_deviceremoved(sb_t *sbh);
8147 +extern uint32 sb_socram_size(sb_t *sbh);
8148 +
8149 +/*
8150 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8151 +* The returned path is NULL terminated and has trailing '/'.
8152 +* Return 0 on success, nonzero otherwise.
8153 +*/
8154 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8155 +
8156 +/* clkctl xtal what flags */
8157 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8158 +#define PLL 0x2 /* main chip pll */
8159 +
8160 +/* clkctl clk mode */
8161 +#define CLK_FAST 0 /* force fast (pll) clock */
8162 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8163 +
8164 +
8165 +/* GPIO usage priorities */
8166 +#define GPIO_DRV_PRIORITY 0 /* Driver */
8167 +#define GPIO_APP_PRIORITY 1 /* Application */
8168 +
8169 +/* device path */
8170 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8171 +
8172 +#endif /* _sbutils_h_ */
8173 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8174 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8175 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2006-04-27 22:13:51.000000000 +0200
8176 @@ -0,0 +1,36 @@
8177 +/*
8178 + * Broadcom SiliconBackplane chipcommon serial flash interface
8179 + *
8180 + * Copyright 2006, Broadcom Corporation
8181 + * All Rights Reserved.
8182 + *
8183 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8184 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8185 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8186 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8187 + *
8188 + * $Id: sflash.h,v 1.1.1.8 2006/02/27 03:43:16 honor Exp $
8189 + */
8190 +
8191 +#ifndef _sflash_h_
8192 +#define _sflash_h_
8193 +
8194 +#include <typedefs.h>
8195 +#include <sbchipc.h>
8196 +
8197 +struct sflash {
8198 + uint blocksize; /* Block size */
8199 + uint numblocks; /* Number of blocks */
8200 + uint32 type; /* Type */
8201 + uint size; /* Total size in bytes */
8202 +};
8203 +
8204 +/* Utility functions */
8205 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8206 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8207 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8208 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8209 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8210 +extern struct sflash * sflash_init(chipcregs_t *cc);
8211 +
8212 +#endif /* _sflash_h_ */
8213 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8214 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8215 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2006-04-27 19:24:19.000000000 +0200
8216 @@ -0,0 +1,33 @@
8217 +/*
8218 + * TRX image file header format.
8219 + *
8220 + * Copyright 2005, Broadcom Corporation
8221 + * All Rights Reserved.
8222 + *
8223 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8224 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8225 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8226 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8227 + *
8228 + * $Id$
8229 + */
8230 +
8231 +#include <typedefs.h>
8232 +
8233 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8234 +#define TRX_VERSION 1
8235 +#define TRX_MAX_LEN 0x3A0000
8236 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8237 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8238 +#define TRX_MAX_OFFSET 3
8239 +
8240 +struct trx_header {
8241 + uint32 magic; /* "HDR0" */
8242 + uint32 len; /* Length of file including header */
8243 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8244 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8245 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8246 +};
8247 +
8248 +/* Compatibility */
8249 +typedef struct trx_header TRXHDR, *PTRXHDR;
8250 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8251 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8252 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2006-04-27 23:47:30.000000000 +0200
8253 @@ -0,0 +1,361 @@
8254 +/*
8255 + * Copyright 2006, Broadcom Corporation
8256 + * All Rights Reserved.
8257 + *
8258 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8259 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8260 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8261 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8262 + * $Id: typedefs.h,v 1.1.1.12 2006/04/08 06:13:40 honor Exp $
8263 + */
8264 +
8265 +#ifndef _TYPEDEFS_H_
8266 +#define _TYPEDEFS_H_
8267 +
8268 +
8269 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8270 + * typedef file "site_typedefs.h".
8271 + *
8272 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8273 + * section of this file makes inferences about the compile environment
8274 + * based on defined symbols and possibly compiler pragmas.
8275 + *
8276 + * Following these two sections is the "Default Typedefs"
8277 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8278 + * defined. This section has a default set of typedefs and a few
8279 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8280 + */
8281 +
8282 +#ifdef SITE_TYPEDEFS
8283 +
8284 +/*
8285 + * Site Specific Typedefs
8286 + *
8287 + */
8288 +
8289 +#include "site_typedefs.h"
8290 +
8291 +#else
8292 +
8293 +/*
8294 + * Inferred Typedefs
8295 + *
8296 + */
8297 +
8298 +/* Infer the compile environment based on preprocessor symbols and pramas.
8299 + * Override type definitions as needed, and include configuration dependent
8300 + * header files to define types.
8301 + */
8302 +
8303 +#ifdef __cplusplus
8304 +
8305 +#define TYPEDEF_BOOL
8306 +#ifndef FALSE
8307 +#define FALSE false
8308 +#endif
8309 +#ifndef TRUE
8310 +#define TRUE true
8311 +#endif
8312 +
8313 +#else /* ! __cplusplus */
8314 +
8315 +#if defined(_WIN32)
8316 +
8317 +#define TYPEDEF_BOOL
8318 +typedef unsigned char bool; /* consistent w/BOOL */
8319 +
8320 +#endif /* _WIN32 */
8321 +
8322 +#endif /* ! __cplusplus */
8323 +
8324 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
8325 +#if defined(_WIN64)
8326 +#include <basetsd.h>
8327 +#define TYPEDEF_UINTPTR
8328 +typedef ULONG_PTR uintptr;
8329 +#endif
8330 +
8331 +
8332 +#if defined(_MINOSL_)
8333 +#define _NEED_SIZE_T_
8334 +#endif
8335 +
8336 +#if defined(_NEED_SIZE_T_)
8337 +typedef long unsigned int size_t;
8338 +#endif
8339 +
8340 +#ifdef __DJGPP__
8341 +typedef long unsigned int size_t;
8342 +#endif /* __DJGPP__ */
8343 +
8344 +#ifdef _MSC_VER /* Microsoft C */
8345 +#define TYPEDEF_INT64
8346 +#define TYPEDEF_UINT64
8347 +typedef signed __int64 int64;
8348 +typedef unsigned __int64 uint64;
8349 +#endif
8350 +
8351 +#if defined(MACOSX)
8352 +#define TYPEDEF_BOOL
8353 +#endif
8354 +
8355 +#if defined(__NetBSD__)
8356 +#define TYPEDEF_ULONG
8357 +#endif
8358 +
8359 +
8360 +#if defined(linux)
8361 +#define TYPEDEF_UINT
8362 +#define TYPEDEF_USHORT
8363 +#define TYPEDEF_ULONG
8364 +#endif
8365 +
8366 +#if !defined(linux) && !defined(_WIN32) && !defined(_CFE_) && \
8367 + !defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__)
8368 +#define TYPEDEF_UINT
8369 +#define TYPEDEF_USHORT
8370 +#endif
8371 +
8372 +
8373 +/* Do not support the (u)int64 types with strict ansi for GNU C */
8374 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
8375 +#define TYPEDEF_INT64
8376 +#define TYPEDEF_UINT64
8377 +#endif
8378 +
8379 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
8380 + * for singned or unsigned
8381 + */
8382 +#if defined(__ICL)
8383 +
8384 +#define TYPEDEF_INT64
8385 +
8386 +#if defined(__STDC__)
8387 +#define TYPEDEF_UINT64
8388 +#endif
8389 +
8390 +#endif /* __ICL */
8391 +
8392 +#if !defined(_WIN32) && !defined(_CFE_) && !defined(_MINOSL_) && \
8393 + !defined(__DJGPP__)
8394 +
8395 +/* pick up ushort & uint from standard types.h */
8396 +#if defined(linux) && defined(__KERNEL__)
8397 +
8398 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
8399 +
8400 +#else
8401 +
8402 +#include <sys/types.h>
8403 +
8404 +#endif
8405 +
8406 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
8407 +
8408 +#if defined(MACOSX)
8409 +
8410 +#ifdef __BIG_ENDIAN__
8411 +#define IL_BIGENDIAN
8412 +#else
8413 +#ifdef IL_BIGENDIAN
8414 +#error "IL_BIGENDIAN was defined for a little-endian compile"
8415 +#endif
8416 +#endif /* __BIG_ENDIAN__ */
8417 +
8418 +#if !defined(__cplusplus)
8419 +
8420 +#if defined(__i386__)
8421 +typedef unsigned char bool;
8422 +#else
8423 +typedef unsigned int bool;
8424 +#endif
8425 +#define TYPE_BOOL 1
8426 +enum {
8427 + false = 0,
8428 + true = 1
8429 +};
8430 +
8431 +#if defined(KERNEL)
8432 +#include <IOKit/IOTypes.h>
8433 +#endif /* KERNEL */
8434 +
8435 +#endif /* __cplusplus */
8436 +
8437 +#endif /* MACOSX */
8438 +
8439 +
8440 +/* use the default typedefs in the next section of this file */
8441 +#define USE_TYPEDEF_DEFAULTS
8442 +
8443 +#endif /* SITE_TYPEDEFS */
8444 +
8445 +
8446 +/*
8447 + * Default Typedefs
8448 + *
8449 + */
8450 +
8451 +#ifdef USE_TYPEDEF_DEFAULTS
8452 +#undef USE_TYPEDEF_DEFAULTS
8453 +
8454 +#ifndef TYPEDEF_BOOL
8455 +typedef /* @abstract@ */ unsigned char bool;
8456 +#endif
8457 +
8458 +/* define uchar, ushort, uint, ulong */
8459 +
8460 +#ifndef TYPEDEF_UCHAR
8461 +typedef unsigned char uchar;
8462 +#endif
8463 +
8464 +#ifndef TYPEDEF_USHORT
8465 +typedef unsigned short ushort;
8466 +#endif
8467 +
8468 +#ifndef TYPEDEF_UINT
8469 +typedef unsigned int uint;
8470 +#endif
8471 +
8472 +#ifndef TYPEDEF_ULONG
8473 +typedef unsigned long ulong;
8474 +#endif
8475 +
8476 +/* define [u]int8/16/32/64, uintptr */
8477 +
8478 +#ifndef TYPEDEF_UINT8
8479 +typedef unsigned char uint8;
8480 +#endif
8481 +
8482 +#ifndef TYPEDEF_UINT16
8483 +typedef unsigned short uint16;
8484 +#endif
8485 +
8486 +#ifndef TYPEDEF_UINT32
8487 +typedef unsigned int uint32;
8488 +#endif
8489 +
8490 +#ifndef TYPEDEF_UINT64
8491 +typedef unsigned long long uint64;
8492 +#endif
8493 +
8494 +#ifndef TYPEDEF_UINTPTR
8495 +typedef unsigned int uintptr;
8496 +#endif
8497 +
8498 +#ifndef TYPEDEF_INT8
8499 +typedef signed char int8;
8500 +#endif
8501 +
8502 +#ifndef TYPEDEF_INT16
8503 +typedef signed short int16;
8504 +#endif
8505 +
8506 +#ifndef TYPEDEF_INT32
8507 +typedef signed int int32;
8508 +#endif
8509 +
8510 +#ifndef TYPEDEF_INT64
8511 +typedef signed long long int64;
8512 +#endif
8513 +
8514 +/* define float32/64, float_t */
8515 +
8516 +#ifndef TYPEDEF_FLOAT32
8517 +typedef float float32;
8518 +#endif
8519 +
8520 +#ifndef TYPEDEF_FLOAT64
8521 +typedef double float64;
8522 +#endif
8523 +
8524 +/*
8525 + * abstracted floating point type allows for compile time selection of
8526 + * single or double precision arithmetic. Compiling with -DFLOAT32
8527 + * selects single precision; the default is double precision.
8528 + */
8529 +
8530 +#ifndef TYPEDEF_FLOAT_T
8531 +
8532 +#if defined(FLOAT32)
8533 +typedef float32 float_t;
8534 +#else /* default to double precision floating point */
8535 +typedef float64 float_t;
8536 +#endif
8537 +
8538 +#endif /* TYPEDEF_FLOAT_T */
8539 +
8540 +/* define macro values */
8541 +
8542 +#ifndef FALSE
8543 +#define FALSE 0
8544 +#endif
8545 +
8546 +#ifndef TRUE
8547 +#define TRUE 1 /* TRUE */
8548 +#endif
8549 +
8550 +#ifndef NULL
8551 +#define NULL 0
8552 +#endif
8553 +
8554 +#ifndef OFF
8555 +#define OFF 0
8556 +#endif
8557 +
8558 +#ifndef ON
8559 +#define ON 1 /* ON = 1 */
8560 +#endif
8561 +
8562 +#define AUTO (-1) /* Auto = -1 */
8563 +
8564 +/* define PTRSZ, INLINE */
8565 +
8566 +#ifndef PTRSZ
8567 +#define PTRSZ sizeof(char*)
8568 +#endif
8569 +
8570 +#ifndef INLINE
8571 +
8572 +#ifdef _MSC_VER
8573 +
8574 +#define INLINE __inline
8575 +
8576 +#elif __GNUC__
8577 +
8578 +#define INLINE __inline__
8579 +
8580 +#else
8581 +
8582 +#define INLINE
8583 +
8584 +#endif /* _MSC_VER */
8585 +
8586 +#endif /* INLINE */
8587 +
8588 +#undef TYPEDEF_BOOL
8589 +#undef TYPEDEF_UCHAR
8590 +#undef TYPEDEF_USHORT
8591 +#undef TYPEDEF_UINT
8592 +#undef TYPEDEF_ULONG
8593 +#undef TYPEDEF_UINT8
8594 +#undef TYPEDEF_UINT16
8595 +#undef TYPEDEF_UINT32
8596 +#undef TYPEDEF_UINT64
8597 +#undef TYPEDEF_UINTPTR
8598 +#undef TYPEDEF_INT8
8599 +#undef TYPEDEF_INT16
8600 +#undef TYPEDEF_INT32
8601 +#undef TYPEDEF_INT64
8602 +#undef TYPEDEF_FLOAT32
8603 +#undef TYPEDEF_FLOAT64
8604 +#undef TYPEDEF_FLOAT_T
8605 +
8606 +#endif /* USE_TYPEDEF_DEFAULTS */
8607 +
8608 +/*
8609 + * Including the bcmdefs.h here, to make sure everyone including typedefs.h
8610 + * gets this automatically
8611 +*/
8612 +#include "bcmdefs.h"
8613 +
8614 +#endif /* _TYPEDEFS_H_ */
8615 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
8616 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
8617 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2006-04-27 23:11:58.000000000 +0200
8618 @@ -0,0 +1,315 @@
8619 +/*
8620 + * NVRAM variable manipulation (common)
8621 + *
8622 + * Copyright 2004, Broadcom Corporation
8623 + * All Rights Reserved.
8624 + *
8625 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8626 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8627 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8628 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8629 + *
8630 + */
8631 +
8632 +#include <typedefs.h>
8633 +#include <osl.h>
8634 +#include <bcmendian.h>
8635 +#include <bcmnvram.h>
8636 +#include <bcmutils.h>
8637 +#include <sbsdram.h>
8638 +
8639 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
8640 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
8641 +extern int BCMINIT(_nvram_read)(void *buf);
8642 +
8643 +char * BCMINIT(_nvram_get)(const char *name);
8644 +int BCMINIT(_nvram_set)(const char *name, const char *value);
8645 +int BCMINIT(_nvram_unset)(const char *name);
8646 +int BCMINIT(_nvram_getall)(char *buf, int count);
8647 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
8648 +int BCMINIT(_nvram_init)(void);
8649 +void BCMINIT(_nvram_exit)(void);
8650 +
8651 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
8652 +static struct nvram_tuple * nvram_dead;
8653 +
8654 +/* Free all tuples. Should be locked. */
8655 +static void
8656 +BCMINITFN(nvram_free)(void)
8657 +{
8658 + uint i;
8659 + struct nvram_tuple *t, *next;
8660 +
8661 + /* Free hash table */
8662 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8663 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
8664 + next = t->next;
8665 + BCMINIT(_nvram_free)(t);
8666 + }
8667 + BCMINIT(nvram_hash)[i] = NULL;
8668 + }
8669 +
8670 + /* Free dead table */
8671 + for (t = nvram_dead; t; t = next) {
8672 + next = t->next;
8673 + BCMINIT(_nvram_free)(t);
8674 + }
8675 + nvram_dead = NULL;
8676 +
8677 + /* Indicate to per-port code that all tuples have been freed */
8678 + BCMINIT(_nvram_free)(NULL);
8679 +}
8680 +
8681 +/* String hash */
8682 +static INLINE uint
8683 +hash(const char *s)
8684 +{
8685 + uint hash = 0;
8686 +
8687 + while (*s)
8688 + hash = 31 * hash + *s++;
8689 +
8690 + return hash;
8691 +}
8692 +
8693 +/* (Re)initialize the hash table. Should be locked. */
8694 +static int
8695 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
8696 +{
8697 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
8698 +
8699 + /* (Re)initialize hash table */
8700 + BCMINIT(nvram_free)();
8701 +
8702 + /* Parse and set "name=value\0 ... \0\0" */
8703 + name = (char *) &header[1];
8704 + end = (char *) header + NVRAM_SPACE - 2;
8705 + end[0] = end[1] = '\0';
8706 + for (; *name; name = value + strlen(value) + 1) {
8707 + if (!(eq = strchr(name, '=')))
8708 + break;
8709 + *eq = '\0';
8710 + value = eq + 1;
8711 + BCMINIT(_nvram_set)(name, value);
8712 + *eq = '=';
8713 + }
8714 +
8715 + /* Set special SDRAM parameters */
8716 + if (!BCMINIT(_nvram_get)("sdram_init")) {
8717 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
8718 + BCMINIT(_nvram_set)("sdram_init", buf);
8719 + }
8720 + if (!BCMINIT(_nvram_get)("sdram_config")) {
8721 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
8722 + BCMINIT(_nvram_set)("sdram_config", buf);
8723 + }
8724 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
8725 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
8726 + BCMINIT(_nvram_set)("sdram_refresh", buf);
8727 + }
8728 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
8729 + sprintf(buf, "0x%08X", header->config_ncdl);
8730 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
8731 + }
8732 +
8733 + return 0;
8734 +}
8735 +
8736 +/* Get the value of an NVRAM variable. Should be locked. */
8737 +char *
8738 +BCMINITFN(_nvram_get)(const char *name)
8739 +{
8740 + uint i;
8741 + struct nvram_tuple *t;
8742 + char *value;
8743 +
8744 + if (!name)
8745 + return NULL;
8746 +
8747 + /* Hash the name */
8748 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8749 +
8750 + /* Find the associated tuple in the hash table */
8751 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
8752 +
8753 + value = t ? t->value : NULL;
8754 +
8755 + return value;
8756 +}
8757 +
8758 +/* Get the value of an NVRAM variable. Should be locked. */
8759 +int
8760 +BCMINITFN(_nvram_set)(const char *name, const char *value)
8761 +{
8762 + uint i;
8763 + struct nvram_tuple *t, *u, **prev;
8764 +
8765 + /* Hash the name */
8766 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8767 +
8768 + /* Find the associated tuple in the hash table */
8769 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8770 +
8771 + /* (Re)allocate tuple */
8772 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
8773 + return -12; /* -ENOMEM */
8774 +
8775 + /* Value reallocated */
8776 + if (t && t == u)
8777 + return 0;
8778 +
8779 + /* Move old tuple to the dead table */
8780 + if (t) {
8781 + *prev = t->next;
8782 + t->next = nvram_dead;
8783 + nvram_dead = t;
8784 + }
8785 +
8786 + /* Add new tuple to the hash table */
8787 + u->next = BCMINIT(nvram_hash)[i];
8788 + BCMINIT(nvram_hash)[i] = u;
8789 +
8790 + return 0;
8791 +}
8792 +
8793 +/* Unset the value of an NVRAM variable. Should be locked. */
8794 +int
8795 +BCMINITFN(_nvram_unset)(const char *name)
8796 +{
8797 + uint i;
8798 + struct nvram_tuple *t, **prev;
8799 +
8800 + if (!name)
8801 + return 0;
8802 +
8803 + /* Hash the name */
8804 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
8805 +
8806 + /* Find the associated tuple in the hash table */
8807 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
8808 +
8809 + /* Move it to the dead table */
8810 + if (t) {
8811 + *prev = t->next;
8812 + t->next = nvram_dead;
8813 + nvram_dead = t;
8814 + }
8815 +
8816 + return 0;
8817 +}
8818 +
8819 +/* Get all NVRAM variables. Should be locked. */
8820 +int
8821 +BCMINITFN(_nvram_getall)(char *buf, int count)
8822 +{
8823 + uint i;
8824 + struct nvram_tuple *t;
8825 + int len = 0;
8826 +
8827 + bzero(buf, count);
8828 +
8829 + /* Write name=value\0 ... \0\0 */
8830 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8831 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8832 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
8833 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
8834 + else
8835 + break;
8836 + }
8837 + }
8838 +
8839 + return 0;
8840 +}
8841 +
8842 +/* Regenerate NVRAM. Should be locked. */
8843 +int
8844 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
8845 +{
8846 + char *init, *config, *refresh, *ncdl;
8847 + char *ptr, *end;
8848 + int i;
8849 + struct nvram_tuple *t;
8850 + struct nvram_header tmp;
8851 + uint8 crc;
8852 +
8853 + /* Regenerate header */
8854 + header->magic = NVRAM_MAGIC;
8855 + header->crc_ver_init = (NVRAM_VERSION << 8);
8856 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
8857 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
8858 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
8859 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
8860 + header->crc_ver_init |= SDRAM_INIT << 16;
8861 + header->config_refresh = SDRAM_CONFIG;
8862 + header->config_refresh |= SDRAM_REFRESH << 16;
8863 + header->config_ncdl = 0;
8864 + } else {
8865 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
8866 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
8867 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
8868 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
8869 + }
8870 +
8871 + /* Clear data area */
8872 + ptr = (char *) header + sizeof(struct nvram_header);
8873 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
8874 +
8875 + /* Leave space for a double NUL at the end */
8876 + end = (char *) header + NVRAM_SPACE - 2;
8877 +
8878 + /* Write out all tuples */
8879 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
8880 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
8881 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
8882 + break;
8883 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
8884 + }
8885 + }
8886 +
8887 + /* End with a double NUL */
8888 + ptr += 2;
8889 +
8890 + /* Set new length */
8891 + header->len = ROUNDUP(ptr - (char *) header, 4);
8892 +
8893 + /* Little-endian CRC8 over the last 11 bytes of the header */
8894 + tmp.crc_ver_init = htol32(header->crc_ver_init);
8895 + tmp.config_refresh = htol32(header->config_refresh);
8896 + tmp.config_ncdl = htol32(header->config_ncdl);
8897 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
8898 +
8899 + /* Continue CRC8 over data bytes */
8900 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
8901 +
8902 + /* Set new CRC8 */
8903 + header->crc_ver_init |= crc;
8904 +
8905 + /* Reinitialize hash table */
8906 + return BCMINIT(nvram_rehash)(header);
8907 +}
8908 +
8909 +/* Initialize hash table. Should be locked. */
8910 +int
8911 +BCMINITFN(_nvram_init)(void)
8912 +{
8913 + struct nvram_header *header;
8914 + int ret;
8915 +
8916 + if (!(header = (struct nvram_header *) kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
8917 + return -12; /* -ENOMEM */
8918 + }
8919 +
8920 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
8921 + header->magic == NVRAM_MAGIC)
8922 + BCMINIT(nvram_rehash)(header);
8923 +
8924 + kfree(header);
8925 + return ret;
8926 +}
8927 +
8928 +/* Free hash table. Should be locked. */
8929 +void
8930 +BCMINITFN(_nvram_exit)(void)
8931 +{
8932 + BCMINIT(nvram_free)();
8933 +}
8934 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
8935 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
8936 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2006-04-27 23:30:07.000000000 +0200
8937 @@ -0,0 +1,723 @@
8938 +/*
8939 + * NVRAM variable manipulation (Linux kernel half)
8940 + *
8941 + * Copyright 2006, Broadcom Corporation
8942 + * All Rights Reserved.
8943 + *
8944 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8945 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8946 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8947 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8948 + *
8949 + * $Id: nvram_linux.c,v 1.19 2006/04/08 07:12:42 honor Exp $
8950 + */
8951 +
8952 +#include <linux/config.h>
8953 +#include <linux/init.h>
8954 +#include <linux/module.h>
8955 +#include <linux/kernel.h>
8956 +#include <linux/string.h>
8957 +#include <linux/interrupt.h>
8958 +#include <linux/spinlock.h>
8959 +#include <linux/slab.h>
8960 +#include <linux/bootmem.h>
8961 +#include <linux/wrapper.h>
8962 +#include <linux/fs.h>
8963 +#include <linux/miscdevice.h>
8964 +#include <linux/mtd/mtd.h>
8965 +#include <asm/addrspace.h>
8966 +#include <asm/io.h>
8967 +#include <asm/uaccess.h>
8968 +
8969 +#include <typedefs.h>
8970 +#include <osl.h>
8971 +#include <bcmendian.h>
8972 +#include <bcmnvram.h>
8973 +#include <bcmutils.h>
8974 +#include <sbconfig.h>
8975 +#include <sbchipc.h>
8976 +#include <sbutils.h>
8977 +#include <hndmips.h>
8978 +#include <sflash.h>
8979 +
8980 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
8981 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
8982 +
8983 +#ifdef MODULE
8984 +
8985 +#define early_nvram_get(name) nvram_get(name)
8986 +
8987 +#else /* !MODULE */
8988 +
8989 +/* Global SB handle */
8990 +extern void *bcm947xx_sbh;
8991 +extern spinlock_t bcm947xx_sbh_lock;
8992 +
8993 +static int cfe_env;
8994 +extern char *cfe_env_get(char *nv_buf, const char *name);
8995 +
8996 +/* Convenience */
8997 +#define sbh bcm947xx_sbh
8998 +#define sbh_lock bcm947xx_sbh_lock
8999 +#define KB * 1024
9000 +#define MB * 1024 * 1024
9001 +
9002 +/* Probe for NVRAM header */
9003 +static void __init
9004 +early_nvram_init(void)
9005 +{
9006 + struct nvram_header *header;
9007 + chipcregs_t *cc;
9008 + struct sflash *info = NULL;
9009 + int i;
9010 + uint32 base, off, lim;
9011 + u32 *src, *dst;
9012 +
9013 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
9014 + base = KSEG1ADDR(SB_FLASH2);
9015 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
9016 + case PFLASH:
9017 + lim = SB_FLASH2_SZ;
9018 + break;
9019 +
9020 + case SFLASH_ST:
9021 + case SFLASH_AT:
9022 + if ((info = sflash_init(cc)) == NULL)
9023 + return;
9024 + lim = info->size;
9025 + break;
9026 +
9027 + case FLASH_NONE:
9028 + default:
9029 + return;
9030 + }
9031 + } else {
9032 + /* extif assumed, Stop at 4 MB */
9033 + base = KSEG1ADDR(SB_FLASH1);
9034 + lim = SB_FLASH1_SZ;
9035 + }
9036 +
9037 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
9038 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
9039 + dst = (u32 *) nvram_buf;
9040 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
9041 + printk("early_nvram_init: WGT634U NVRAM found.\n");
9042 +
9043 + for (i = 0; i < 0x1ff0; i++) {
9044 + if (*src == 0xFFFFFFFF)
9045 + break;
9046 + *dst++ = *src++;
9047 + }
9048 + cfe_env = 1;
9049 + return;
9050 + }
9051 +
9052 + off = FLASH_MIN;
9053 + while (off <= lim) {
9054 + /* Windowed flash access */
9055 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
9056 + if (header->magic == NVRAM_MAGIC)
9057 + goto found;
9058 + off <<= 1;
9059 + }
9060 +
9061 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
9062 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
9063 + if (header->magic == NVRAM_MAGIC)
9064 + goto found;
9065 +
9066 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
9067 + if (header->magic == NVRAM_MAGIC)
9068 + goto found;
9069 +
9070 + printk("early_nvram_init: NVRAM not found\n");
9071 + return;
9072 +
9073 +found:
9074 + src = (u32 *) header;
9075 + dst = (u32 *) nvram_buf;
9076 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
9077 + *dst++ = *src++;
9078 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
9079 + *dst++ = ltoh32(*src++);
9080 +}
9081 +
9082 +/* Early (before mm or mtd) read-only access to NVRAM */
9083 +static char * __init
9084 +early_nvram_get(const char *name)
9085 +{
9086 + char *var, *value, *end, *eq;
9087 +
9088 + if (!name)
9089 + return NULL;
9090 +
9091 + /* Too early? */
9092 + if (sbh == NULL)
9093 + return NULL;
9094 +
9095 + if (!nvram_buf[0])
9096 + early_nvram_init();
9097 +
9098 + if (cfe_env)
9099 + return cfe_env_get(nvram_buf, name);
9100 +
9101 + /* Look for name=value and return value */
9102 + var = &nvram_buf[sizeof(struct nvram_header)];
9103 + end = nvram_buf + sizeof(nvram_buf) - 2;
9104 + end[0] = end[1] = '\0';
9105 + for (; *var; var = value + strlen(value) + 1) {
9106 + if (!(eq = strchr(var, '=')))
9107 + break;
9108 + value = eq + 1;
9109 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
9110 + return value;
9111 + }
9112 +
9113 + return NULL;
9114 +}
9115 +
9116 +static int __init
9117 +early_nvram_getall(char *buf, int count)
9118 +{
9119 + char *var, *end;
9120 + int len = 0;
9121 +
9122 + /* Too early? */
9123 + if (sbh == NULL)
9124 + return -1;
9125 +
9126 + if (!nvram_buf[0])
9127 + early_nvram_init();
9128 +
9129 + bzero(buf, count);
9130 +
9131 + /* Write name=value\0 ... \0\0 */
9132 + var = &nvram_buf[sizeof(struct nvram_header)];
9133 + end = nvram_buf + sizeof(nvram_buf) - 2;
9134 + end[0] = end[1] = '\0';
9135 + for (; *var; var += strlen(var) + 1) {
9136 + if ((count - len) <= (strlen(var) + 1))
9137 + break;
9138 + len += sprintf(buf + len, "%s", var) + 1;
9139 + }
9140 +
9141 + return 0;
9142 +}
9143 +#endif /* !MODULE */
9144 +
9145 +extern char * _nvram_get(const char *name);
9146 +extern int _nvram_set(const char *name, const char *value);
9147 +extern int _nvram_unset(const char *name);
9148 +extern int _nvram_getall(char *buf, int count);
9149 +extern int _nvram_commit(struct nvram_header *header);
9150 +extern int _nvram_init(void *sbh);
9151 +extern void _nvram_exit(void);
9152 +
9153 +/* Globals */
9154 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
9155 +static struct semaphore nvram_sem;
9156 +static unsigned long nvram_offset = 0;
9157 +static int nvram_major = -1;
9158 +static devfs_handle_t nvram_handle = NULL;
9159 +static struct mtd_info *nvram_mtd = NULL;
9160 +
9161 +int
9162 +_nvram_read(char *buf)
9163 +{
9164 + struct nvram_header *header = (struct nvram_header *) buf;
9165 + size_t len;
9166 +
9167 + if (!nvram_mtd ||
9168 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
9169 + len != NVRAM_SPACE ||
9170 + header->magic != NVRAM_MAGIC) {
9171 + /* Maybe we can recover some data from early initialization */
9172 + memcpy(buf, nvram_buf, NVRAM_SPACE);
9173 + }
9174 +
9175 + return 0;
9176 +}
9177 +
9178 +struct nvram_tuple *
9179 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
9180 +{
9181 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
9182 + return NULL;
9183 +
9184 + if (!t) {
9185 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
9186 + return NULL;
9187 +
9188 + /* Copy name */
9189 + t->name = (char *) &t[1];
9190 + strcpy(t->name, name);
9191 +
9192 + t->value = NULL;
9193 + }
9194 +
9195 + /* Copy value */
9196 + if (!t->value || strcmp(t->value, value)) {
9197 + t->value = &nvram_buf[nvram_offset];
9198 + strcpy(t->value, value);
9199 + nvram_offset += strlen(value) + 1;
9200 + }
9201 +
9202 + return t;
9203 +}
9204 +
9205 +void
9206 +_nvram_free(struct nvram_tuple *t)
9207 +{
9208 + if (!t)
9209 + nvram_offset = 0;
9210 + else
9211 + kfree(t);
9212 +}
9213 +
9214 +int
9215 +nvram_set(const char *name, const char *value)
9216 +{
9217 + unsigned long flags;
9218 + int ret;
9219 + struct nvram_header *header;
9220 +
9221 + spin_lock_irqsave(&nvram_lock, flags);
9222 + if ((ret = _nvram_set(name, value))) {
9223 + /* Consolidate space and try again */
9224 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
9225 + if (_nvram_commit(header) == 0)
9226 + ret = _nvram_set(name, value);
9227 + kfree(header);
9228 + }
9229 + }
9230 + spin_unlock_irqrestore(&nvram_lock, flags);
9231 +
9232 + return ret;
9233 +}
9234 +
9235 +char *
9236 +real_nvram_get(const char *name)
9237 +{
9238 + unsigned long flags;
9239 + char *value;
9240 +
9241 + spin_lock_irqsave(&nvram_lock, flags);
9242 + value = _nvram_get(name);
9243 + spin_unlock_irqrestore(&nvram_lock, flags);
9244 +
9245 + return value;
9246 +}
9247 +
9248 +char *
9249 +nvram_get(const char *name)
9250 +{
9251 + if (nvram_major >= 0)
9252 + return real_nvram_get(name);
9253 + else
9254 + return early_nvram_get(name);
9255 +}
9256 +
9257 +int
9258 +nvram_unset(const char *name)
9259 +{
9260 + unsigned long flags;
9261 + int ret;
9262 +
9263 + spin_lock_irqsave(&nvram_lock, flags);
9264 + ret = _nvram_unset(name);
9265 + spin_unlock_irqrestore(&nvram_lock, flags);
9266 +
9267 + return ret;
9268 +}
9269 +
9270 +static void
9271 +erase_callback(struct erase_info *done)
9272 +{
9273 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
9274 + wake_up(wait_q);
9275 +}
9276 +
9277 +int
9278 +nvram_commit(void)
9279 +{
9280 + char *buf;
9281 + size_t erasesize, len, magic_len;
9282 + unsigned int i;
9283 + int ret;
9284 + struct nvram_header *header;
9285 + unsigned long flags;
9286 + u_int32_t offset;
9287 + DECLARE_WAITQUEUE(wait, current);
9288 + wait_queue_head_t wait_q;
9289 + struct erase_info erase;
9290 + u_int32_t magic_offset = 0; /* Offset for writing MAGIC # */
9291 +
9292 + if (!nvram_mtd) {
9293 + printk("nvram_commit: NVRAM not found\n");
9294 + return -ENODEV;
9295 + }
9296 +
9297 + if (in_interrupt()) {
9298 + printk("nvram_commit: not committing in interrupt\n");
9299 + return -EINVAL;
9300 + }
9301 +
9302 + /* Backup sector blocks to be erased */
9303 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
9304 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
9305 + printk("nvram_commit: out of memory\n");
9306 + return -ENOMEM;
9307 + }
9308 +
9309 + down(&nvram_sem);
9310 +
9311 + if ((i = erasesize - NVRAM_SPACE) > 0) {
9312 + offset = nvram_mtd->size - erasesize;
9313 + len = 0;
9314 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
9315 + if (ret || len != i) {
9316 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
9317 + ret = -EIO;
9318 + goto done;
9319 + }
9320 + header = (struct nvram_header *)(buf + i);
9321 + magic_offset = i + ((void *)&header->magic - (void *)header);
9322 + } else {
9323 + offset = nvram_mtd->size - NVRAM_SPACE;
9324 + magic_offset = ((void *)&header->magic - (void *)header);
9325 + header = (struct nvram_header *)buf;
9326 + }
9327 +
9328 + /* clear the existing magic # to mark the NVRAM as unusable
9329 + we can pull MAGIC bits low without erase */
9330 + header->magic = NVRAM_CLEAR_MAGIC; /* All zeros magic */
9331 +
9332 + /* Unlock sector blocks (for Intel 28F320C3B flash) , 20060309 */
9333 + if(nvram_mtd->unlock)
9334 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9335 +
9336 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9337 + &magic_len, (char *)&header->magic);
9338 + if (ret || magic_len != sizeof(header->magic)) {
9339 + printk("nvram_commit: clear MAGIC error\n");
9340 + ret = -EIO;
9341 + goto done;
9342 + }
9343 +
9344 + header->magic = NVRAM_MAGIC; /* reset MAGIC before we regenerate the NVRAM,
9345 + otherwise we'll have an incorrect CRC */
9346 + /* Regenerate NVRAM */
9347 + spin_lock_irqsave(&nvram_lock, flags);
9348 + ret = _nvram_commit(header);
9349 + spin_unlock_irqrestore(&nvram_lock, flags);
9350 + if (ret)
9351 + goto done;
9352 +
9353 + /* Erase sector blocks */
9354 + init_waitqueue_head(&wait_q);
9355 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
9356 + erase.mtd = nvram_mtd;
9357 + erase.addr = offset;
9358 + erase.len = nvram_mtd->erasesize;
9359 + erase.callback = erase_callback;
9360 + erase.priv = (u_long) &wait_q;
9361 +
9362 + set_current_state(TASK_INTERRUPTIBLE);
9363 + add_wait_queue(&wait_q, &wait);
9364 +
9365 + /* Unlock sector blocks */
9366 + if (nvram_mtd->unlock)
9367 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
9368 +
9369 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
9370 + set_current_state(TASK_RUNNING);
9371 + remove_wait_queue(&wait_q, &wait);
9372 + printk("nvram_commit: erase error\n");
9373 + goto done;
9374 + }
9375 +
9376 + /* Wait for erase to finish */
9377 + schedule();
9378 + remove_wait_queue(&wait_q, &wait);
9379 + }
9380 +
9381 + /* Write partition up to end of data area */
9382 + header->magic = NVRAM_INVALID_MAGIC; /* All ones magic */
9383 + offset = nvram_mtd->size - erasesize;
9384 + i = erasesize - NVRAM_SPACE + header->len;
9385 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
9386 + if (ret || len != i) {
9387 + printk("nvram_commit: write error\n");
9388 + ret = -EIO;
9389 + goto done;
9390 + }
9391 +
9392 + /* Now mark the NVRAM in flash as "valid" by setting the correct
9393 + MAGIC # */
9394 + header->magic = NVRAM_MAGIC;
9395 + ret = MTD_WRITE(nvram_mtd, offset + magic_offset, sizeof(header->magic),
9396 + &magic_len, (char *)&header->magic);
9397 + if (ret || magic_len != sizeof(header->magic)) {
9398 + printk("nvram_commit: write MAGIC error\n");
9399 + ret = -EIO;
9400 + goto done;
9401 + }
9402 +
9403 + /*
9404 + * Reading a few bytes back here will put the device
9405 + * back to the correct mode on certain flashes */
9406 + offset = nvram_mtd->size - erasesize;
9407 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
9408 +
9409 + done:
9410 + up(&nvram_sem);
9411 + kfree(buf);
9412 +
9413 + return ret;
9414 +}
9415 +
9416 +int
9417 +nvram_getall(char *buf, int count)
9418 +{
9419 + unsigned long flags;
9420 + int ret;
9421 +
9422 + spin_lock_irqsave(&nvram_lock, flags);
9423 + if (nvram_major >= 0)
9424 + ret = _nvram_getall(buf, count);
9425 + else
9426 + ret = early_nvram_getall(buf, count);
9427 + spin_unlock_irqrestore(&nvram_lock, flags);
9428 +
9429 + return ret;
9430 +}
9431 +
9432 +
9433 +
9434 +
9435 +
9436 +
9437 +
9438 +/* User mode interface below */
9439 +
9440 +static ssize_t
9441 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
9442 +{
9443 + char tmp[100], *name = tmp, *value;
9444 + ssize_t ret;
9445 + unsigned long off;
9446 +
9447 + if (count > sizeof(tmp)) {
9448 + if (!(name = kmalloc(count, GFP_KERNEL)))
9449 + return -ENOMEM;
9450 + }
9451 +
9452 + if (copy_from_user(name, buf, count)) {
9453 + ret = -EFAULT;
9454 + goto done;
9455 + }
9456 +
9457 + if (*name == '\0') {
9458 + /* Get all variables */
9459 + ret = nvram_getall(name, count);
9460 + if (ret == 0) {
9461 + if (copy_to_user(buf, name, count)) {
9462 + ret = -EFAULT;
9463 + goto done;
9464 + }
9465 + ret = count;
9466 + }
9467 + } else {
9468 + if (!(value = nvram_get(name))) {
9469 + ret = 0;
9470 + goto done;
9471 + }
9472 +
9473 + /* Provide the offset into mmap() space */
9474 + off = (unsigned long) value - (unsigned long) nvram_buf;
9475 +
9476 + if (put_user(off, (unsigned long *) buf)) {
9477 + ret = -EFAULT;
9478 + goto done;
9479 + }
9480 +
9481 + ret = sizeof(unsigned long);
9482 + }
9483 +
9484 + flush_cache_all();
9485 +
9486 +done:
9487 + if (name != tmp)
9488 + kfree(name);
9489 +
9490 + return ret;
9491 +}
9492 +
9493 +static ssize_t
9494 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
9495 +{
9496 + char tmp[100], *name = tmp, *value;
9497 + ssize_t ret;
9498 +
9499 + if (count > sizeof(tmp)) {
9500 + if (!(name = kmalloc(count, GFP_KERNEL)))
9501 + return -ENOMEM;
9502 + }
9503 +
9504 + if (copy_from_user(name, buf, count)) {
9505 + ret = -EFAULT;
9506 + goto done;
9507 + }
9508 +
9509 + value = name;
9510 + name = strsep(&value, "=");
9511 + if (value)
9512 + ret = nvram_set(name, value) ? : count;
9513 + else
9514 + ret = nvram_unset(name) ? : count;
9515 +
9516 + done:
9517 + if (name != tmp)
9518 + kfree(name);
9519 +
9520 + return ret;
9521 +}
9522 +
9523 +static int
9524 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
9525 +{
9526 + if (cmd != NVRAM_MAGIC)
9527 + return -EINVAL;
9528 +
9529 + return nvram_commit();
9530 +}
9531 +
9532 +static int
9533 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
9534 +{
9535 + unsigned long offset = virt_to_phys(nvram_buf);
9536 +
9537 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
9538 + vma->vm_page_prot))
9539 + return -EAGAIN;
9540 +
9541 + return 0;
9542 +}
9543 +
9544 +static int
9545 +dev_nvram_open(struct inode *inode, struct file * file)
9546 +{
9547 + MOD_INC_USE_COUNT;
9548 + return 0;
9549 +}
9550 +
9551 +static int
9552 +dev_nvram_release(struct inode *inode, struct file * file)
9553 +{
9554 + MOD_DEC_USE_COUNT;
9555 + return 0;
9556 +}
9557 +
9558 +static struct file_operations dev_nvram_fops = {
9559 + owner: THIS_MODULE,
9560 + open: dev_nvram_open,
9561 + release: dev_nvram_release,
9562 + read: dev_nvram_read,
9563 + write: dev_nvram_write,
9564 + ioctl: dev_nvram_ioctl,
9565 + mmap: dev_nvram_mmap,
9566 +};
9567 +
9568 +static void
9569 +dev_nvram_exit(void)
9570 +{
9571 + int order = 0;
9572 + struct page *page, *end;
9573 +
9574 + if (nvram_handle)
9575 + devfs_unregister(nvram_handle);
9576 +
9577 + if (nvram_major >= 0)
9578 + devfs_unregister_chrdev(nvram_major, "nvram");
9579 +
9580 + if (nvram_mtd)
9581 + put_mtd_device(nvram_mtd);
9582 +
9583 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9584 + order++;
9585 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9586 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9587 + mem_map_unreserve(page);
9588 +
9589 + _nvram_exit();
9590 +}
9591 +
9592 +static int __init
9593 +dev_nvram_init(void)
9594 +{
9595 + int order = 0, ret = 0;
9596 + struct page *page, *end;
9597 + unsigned int i;
9598 +
9599 + /* Allocate and reserve memory to mmap() */
9600 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
9601 + order++;
9602 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
9603 + for (page = virt_to_page(nvram_buf); page <= end; page++)
9604 + mem_map_reserve(page);
9605 +
9606 +#ifdef CONFIG_MTD
9607 + /* Find associated MTD device */
9608 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
9609 + nvram_mtd = get_mtd_device(NULL, i);
9610 + if (nvram_mtd) {
9611 + if (!strcmp(nvram_mtd->name, "nvram") &&
9612 + nvram_mtd->size >= NVRAM_SPACE)
9613 + break;
9614 + put_mtd_device(nvram_mtd);
9615 + }
9616 + }
9617 + if (i >= MAX_MTD_DEVICES)
9618 + nvram_mtd = NULL;
9619 +#endif
9620 +
9621 + /* Initialize hash table lock */
9622 + spin_lock_init(&nvram_lock);
9623 +
9624 + /* Initialize commit semaphore */
9625 + init_MUTEX(&nvram_sem);
9626 +
9627 + /* Register char device */
9628 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
9629 + ret = nvram_major;
9630 + goto err;
9631 + }
9632 +
9633 + /* Initialize hash table */
9634 + _nvram_init(sbh);
9635 +
9636 + /* Create /dev/nvram handle */
9637 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
9638 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
9639 +
9640 + /* Set the SDRAM NCDL value into NVRAM if not already done */
9641 + if (getintvar(NULL, "sdram_ncdl") == 0) {
9642 + unsigned int ncdl;
9643 + char buf[] = "0x00000000";
9644 +
9645 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
9646 + sprintf(buf, "0x%08x", ncdl);
9647 + nvram_set("sdram_ncdl", buf);
9648 + nvram_commit();
9649 + }
9650 + }
9651 +
9652 + return 0;
9653 +
9654 + err:
9655 + dev_nvram_exit();
9656 + return ret;
9657 +}
9658 +
9659 +module_init(dev_nvram_init);
9660 +module_exit(dev_nvram_exit);
9661 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
9662 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
9663 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2006-04-27 23:42:50.000000000 +0200
9664 @@ -0,0 +1,380 @@
9665 +/*
9666 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
9667 + *
9668 + * Copyright 2006, Broadcom Corporation
9669 + * All Rights Reserved.
9670 + *
9671 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9672 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9673 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9674 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9675 + *
9676 + * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
9677 + */
9678 +
9679 +#include <linux/config.h>
9680 +#include <linux/types.h>
9681 +#include <linux/kernel.h>
9682 +#include <linux/sched.h>
9683 +#include <linux/pci.h>
9684 +#include <linux/init.h>
9685 +#include <linux/delay.h>
9686 +#include <asm/io.h>
9687 +#include <asm/irq.h>
9688 +#include <asm/paccess.h>
9689 +
9690 +#include <typedefs.h>
9691 +#include <osl.h>
9692 +#include <bcmutils.h>
9693 +#include <sbconfig.h>
9694 +#include <sbutils.h>
9695 +#include <hndpci.h>
9696 +#include <pcicfg.h>
9697 +#include <bcmdevs.h>
9698 +#include <bcmnvram.h>
9699 +
9700 +/* Global SB handle */
9701 +extern sb_t *bcm947xx_sbh;
9702 +extern spinlock_t bcm947xx_sbh_lock;
9703 +
9704 +/* Convenience */
9705 +#define sbh bcm947xx_sbh
9706 +#define sbh_lock bcm947xx_sbh_lock
9707 +
9708 +static int
9709 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
9710 +{
9711 + unsigned long flags;
9712 + int ret;
9713 +
9714 + spin_lock_irqsave(&sbh_lock, flags);
9715 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9716 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9717 + spin_unlock_irqrestore(&sbh_lock, flags);
9718 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9719 +}
9720 +
9721 +static int
9722 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
9723 +{
9724 + unsigned long flags;
9725 + int ret;
9726 +
9727 + spin_lock_irqsave(&sbh_lock, flags);
9728 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9729 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9730 + spin_unlock_irqrestore(&sbh_lock, flags);
9731 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9732 +}
9733 +
9734 +static int
9735 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
9736 +{
9737 + unsigned long flags;
9738 + int ret;
9739 +
9740 + spin_lock_irqsave(&sbh_lock, flags);
9741 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9742 + PCI_FUNC(dev->devfn), where, value, sizeof(*value));
9743 + spin_unlock_irqrestore(&sbh_lock, flags);
9744 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9745 +}
9746 +
9747 +static int
9748 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
9749 +{
9750 + unsigned long flags;
9751 + int ret;
9752 +
9753 + spin_lock_irqsave(&sbh_lock, flags);
9754 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9755 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9756 + spin_unlock_irqrestore(&sbh_lock, flags);
9757 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9758 +}
9759 +
9760 +static int
9761 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
9762 +{
9763 + unsigned long flags;
9764 + int ret;
9765 +
9766 + spin_lock_irqsave(&sbh_lock, flags);
9767 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9768 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9769 + spin_unlock_irqrestore(&sbh_lock, flags);
9770 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9771 +}
9772 +
9773 +static int
9774 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
9775 +{
9776 + unsigned long flags;
9777 + int ret;
9778 +
9779 + spin_lock_irqsave(&sbh_lock, flags);
9780 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
9781 + PCI_FUNC(dev->devfn), where, &value, sizeof(value));
9782 + spin_unlock_irqrestore(&sbh_lock, flags);
9783 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
9784 +}
9785 +
9786 +static struct pci_ops pcibios_ops = {
9787 + sbpci_read_config_byte,
9788 + sbpci_read_config_word,
9789 + sbpci_read_config_dword,
9790 + sbpci_write_config_byte,
9791 + sbpci_write_config_word,
9792 + sbpci_write_config_dword
9793 +};
9794 +
9795 +
9796 +void __init
9797 +pcibios_init(void)
9798 +{
9799 + ulong flags;
9800 +
9801 + if (!(sbh = sb_kattach()))
9802 + panic("sb_kattach failed");
9803 + spin_lock_init(&sbh_lock);
9804 +
9805 + spin_lock_irqsave(&sbh_lock, flags);
9806 + sbpci_init(sbh);
9807 + spin_unlock_irqrestore(&sbh_lock, flags);
9808 +
9809 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
9810 +
9811 + /* Scan the SB bus */
9812 + pci_scan_bus(0, &pcibios_ops, NULL);
9813 +
9814 +}
9815 +
9816 +char * __init
9817 +pcibios_setup(char *str)
9818 +{
9819 + if (!strncmp(str, "ban=", 4)) {
9820 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
9821 + return NULL;
9822 + }
9823 +
9824 + return (str);
9825 +}
9826 +
9827 +static u32 pci_iobase = 0x100;
9828 +static u32 pci_membase = SB_PCI_DMA;
9829 +
9830 +void __init
9831 +pcibios_fixup_bus(struct pci_bus *b)
9832 +{
9833 + struct list_head *ln;
9834 + struct pci_dev *d;
9835 + struct resource *res;
9836 + int pos, size;
9837 + u32 *base;
9838 + u8 irq;
9839 +
9840 + printk("PCI: Fixing up bus %d\n", b->number);
9841 +
9842 + /* Fix up SB */
9843 + if (b->number == 0) {
9844 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9845 + d = pci_dev_b(ln);
9846 + /* Fix up interrupt lines */
9847 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
9848 + d->irq = irq + 2;
9849 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9850 + }
9851 + }
9852 +
9853 + /* Fix up external PCI */
9854 + else {
9855 + for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
9856 + d = pci_dev_b(ln);
9857 + /* Fix up resource bases */
9858 + for (pos = 0; pos < 6; pos++) {
9859 + res = &d->resource[pos];
9860 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
9861 + if (res->end) {
9862 + size = res->end - res->start + 1;
9863 + if (*base & (size - 1))
9864 + *base = (*base + size) & ~(size - 1);
9865 + res->start = *base;
9866 + res->end = res->start + size - 1;
9867 + *base += size;
9868 + pci_write_config_dword(d,
9869 + PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
9870 + }
9871 + /* Fix up PCI bridge BAR0 only */
9872 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
9873 + break;
9874 + }
9875 + /* Fix up interrupt lines */
9876 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
9877 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
9878 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
9879 + }
9880 + }
9881 +}
9882 +
9883 +unsigned int
9884 +pcibios_assign_all_busses(void)
9885 +{
9886 + return 1;
9887 +}
9888 +
9889 +void
9890 +pcibios_align_resource(void *data, struct resource *res,
9891 + unsigned long size, unsigned long align)
9892 +{
9893 +}
9894 +
9895 +int
9896 +pcibios_enable_resources(struct pci_dev *dev)
9897 +{
9898 + u16 cmd, old_cmd;
9899 + int idx;
9900 + struct resource *r;
9901 +
9902 + /* External PCI only */
9903 + if (dev->bus->number == 0)
9904 + return 0;
9905 +
9906 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
9907 + old_cmd = cmd;
9908 + for (idx = 0; idx < 6; idx++) {
9909 + r = &dev->resource[idx];
9910 + if (r->flags & IORESOURCE_IO)
9911 + cmd |= PCI_COMMAND_IO;
9912 + if (r->flags & IORESOURCE_MEM)
9913 + cmd |= PCI_COMMAND_MEMORY;
9914 + }
9915 + if (dev->resource[PCI_ROM_RESOURCE].start)
9916 + cmd |= PCI_COMMAND_MEMORY;
9917 + if (cmd != old_cmd) {
9918 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
9919 + pci_write_config_word(dev, PCI_COMMAND, cmd);
9920 + }
9921 + return 0;
9922 +}
9923 +
9924 +int
9925 +pcibios_enable_device(struct pci_dev *dev, int mask)
9926 +{
9927 + ulong flags;
9928 + uint coreidx;
9929 + void *regs;
9930 +
9931 + /* External PCI device enable */
9932 + if (dev->bus->number != 0)
9933 + return pcibios_enable_resources(dev);
9934 +
9935 + /* These cores come out of reset enabled */
9936 + if (dev->device == SB_MIPS ||
9937 + dev->device == SB_MIPS33 ||
9938 + dev->device == SB_EXTIF ||
9939 + dev->device == SB_CC)
9940 + return 0;
9941 +
9942 + spin_lock_irqsave(&sbh_lock, flags);
9943 + coreidx = sb_coreidx(sbh);
9944 + regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
9945 + if (!regs)
9946 + return PCIBIOS_DEVICE_NOT_FOUND;
9947 +
9948 + /*
9949 + * The USB core requires a special bit to be set during core
9950 + * reset to enable host (OHCI) mode. Resetting the SB core in
9951 + * pcibios_enable_device() is a hack for compatibility with
9952 + * vanilla usb-ohci so that it does not have to know about
9953 + * SB. A driver that wants to use the USB core in device mode
9954 + * should know about SB and should reset the bit back to 0
9955 + * after calling pcibios_enable_device().
9956 + */
9957 + if (sb_coreid(sbh) == SB_USB) {
9958 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
9959 + sb_core_reset(sbh, 1 << 29, 0);
9960 + }
9961 + /*
9962 + * USB 2.0 special considerations:
9963 + *
9964 + * 1. Since the core supports both OHCI and EHCI functions, it must
9965 + * only be reset once.
9966 + *
9967 + * 2. In addition to the standard SB reset sequence, the Host Control
9968 + * Register must be programmed to bring the USB core and various
9969 + * phy components out of reset.
9970 + */
9971 + else if (sb_coreid(sbh) == SB_USB20H) {
9972 + if (!sb_iscoreup(sbh)) {
9973 + sb_core_reset(sbh, 0, 0);
9974 + writel(0x7FF, (ulong)regs + 0x200);
9975 + udelay(1);
9976 + }
9977 + } else
9978 + sb_core_reset(sbh, 0, 0);
9979 +
9980 + sb_setcoreidx(sbh, coreidx);
9981 + spin_unlock_irqrestore(&sbh_lock, flags);
9982 +
9983 + return 0;
9984 +}
9985 +
9986 +void
9987 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
9988 + struct resource *res, int resource)
9989 +{
9990 + unsigned long where, size;
9991 + u32 reg;
9992 +
9993 + /* External PCI only */
9994 + if (dev->bus->number == 0)
9995 + return;
9996 +
9997 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
9998 + size = res->end - res->start;
9999 + pci_read_config_dword(dev, where, &reg);
10000 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
10001 + pci_write_config_dword(dev, where, reg);
10002 +}
10003 +
10004 +static void __init
10005 +quirk_sbpci_bridge(struct pci_dev *dev)
10006 +{
10007 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
10008 + return;
10009 +
10010 + printk("PCI: Fixing up bridge\n");
10011 +
10012 + /* Enable PCI bridge bus mastering and memory space */
10013 + pci_set_master(dev);
10014 + pcibios_enable_resources(dev);
10015 +
10016 + /* Enable PCI bridge BAR1 prefetch and burst */
10017 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
10018 +}
10019 +
10020 +struct pci_fixup pcibios_fixups[] = {
10021 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
10022 + { 0 }
10023 +};
10024 +
10025 +/*
10026 + * If we set up a device for bus mastering, we need to check the latency
10027 + * timer as certain crappy BIOSes forget to set it properly.
10028 + */
10029 +unsigned int pcibios_max_latency = 255;
10030 +
10031 +void pcibios_set_master(struct pci_dev *dev)
10032 +{
10033 + u8 lat;
10034 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
10035 + if (lat < 16)
10036 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
10037 + else if (lat > pcibios_max_latency)
10038 + lat = pcibios_max_latency;
10039 + else
10040 + return;
10041 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
10042 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
10043 +}
10044 +
10045 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
10046 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
10047 +++ linux.dev/arch/mips/bcm947xx/prom.c 2006-04-27 19:24:19.000000000 +0200
10048 @@ -0,0 +1,41 @@
10049 +/*
10050 + * Early initialization code for BCM94710 boards
10051 + *
10052 + * Copyright 2004, Broadcom Corporation
10053 + * All Rights Reserved.
10054 + *
10055 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10056 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10057 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10058 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10059 + *
10060 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
10061 + */
10062 +
10063 +#include <linux/config.h>
10064 +#include <linux/init.h>
10065 +#include <linux/kernel.h>
10066 +#include <linux/types.h>
10067 +#include <asm/bootinfo.h>
10068 +
10069 +void __init
10070 +prom_init(int argc, const char **argv)
10071 +{
10072 + unsigned long mem;
10073 +
10074 + mips_machgroup = MACH_GROUP_BRCM;
10075 + mips_machtype = MACH_BCM947XX;
10076 +
10077 + /* Figure out memory size by finding aliases */
10078 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
10079 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
10080 + *(unsigned long *)(prom_init))
10081 + break;
10082 + }
10083 + add_memory_region(0, mem, BOOT_MEM_RAM);
10084 +}
10085 +
10086 +void __init
10087 +prom_free_prom_memory(void)
10088 +{
10089 +}
10090 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
10091 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
10092 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2006-05-02 04:43:13.000000000 +0200
10093 @@ -0,0 +1,1132 @@
10094 +/*
10095 + * BCM47XX Sonics SiliconBackplane MIPS core routines
10096 + *
10097 + * Copyright 2006, Broadcom Corporation
10098 + * All Rights Reserved.
10099 + *
10100 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10101 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10102 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10103 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10104 + *
10105 + * $Id: hndmips.c,v 1.1.1.1 2006/02/27 03:43:16 honor Exp $
10106 + */
10107 +
10108 +#include <typedefs.h>
10109 +#include <bcmdefs.h>
10110 +#include <osl.h>
10111 +#include <bcmutils.h>
10112 +#include <sbutils.h>
10113 +#include <bcmdevs.h>
10114 +#include <bcmnvram.h>
10115 +#include <sbconfig.h>
10116 +#include <sbextif.h>
10117 +#include <sbchipc.h>
10118 +#include <sbmemc.h>
10119 +#include <mipsinc.h>
10120 +#include <sbhndmips.h>
10121 +#include <hndcpu.h>
10122 +
10123 +/* sbipsflag register format, indexed by irq. */
10124 +static const uint32 sbips_int_mask[] = {
10125 + 0, /* placeholder */
10126 + SBIPS_INT1_MASK,
10127 + SBIPS_INT2_MASK,
10128 + SBIPS_INT3_MASK,
10129 + SBIPS_INT4_MASK
10130 +};
10131 +
10132 +static const uint32 sbips_int_shift[] = {
10133 + 0, /* placeholder */
10134 + SBIPS_INT1_SHIFT,
10135 + SBIPS_INT2_SHIFT,
10136 + SBIPS_INT3_SHIFT,
10137 + SBIPS_INT4_SHIFT
10138 +};
10139 +
10140 +/*
10141 + * Map SB cores sharing the MIPS hardware IRQ0 to virtual dedicated OS IRQs.
10142 + * Per-port BSP code is required to provide necessary translations between
10143 + * the shared MIPS IRQ and the virtual OS IRQs based on SB core flag.
10144 + *
10145 + * See sb_irq() for the mapping.
10146 + */
10147 +static uint shirq_map_base = 0;
10148 +
10149 +/* Returns the SB interrupt flag of the current core. */
10150 +static uint32
10151 +sb_getflag(sb_t *sbh)
10152 +{
10153 + osl_t *osh;
10154 + void *regs;
10155 + sbconfig_t *sb;
10156 +
10157 + osh = sb_osh(sbh);
10158 + regs = sb_coreregs(sbh);
10159 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10160 +
10161 + return (R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK);
10162 +}
10163 +
10164 +/*
10165 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
10166 + * 0 is returned.
10167 + */
10168 +uint
10169 +sb_irq(sb_t *sbh)
10170 +{
10171 + osl_t *osh;
10172 + uint idx;
10173 + void *regs;
10174 + sbconfig_t *sb;
10175 + uint32 flag, sbipsflag;
10176 + uint irq = 0;
10177 +
10178 + osh = sb_osh(sbh);
10179 + flag = sb_getflag(sbh);
10180 +
10181 + idx = sb_coreidx(sbh);
10182 +
10183 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
10184 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
10185 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10186 +
10187 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
10188 + sbipsflag = R_REG(osh, &sb->sbipsflag);
10189 + for (irq = 1; irq <= 4; irq++) {
10190 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
10191 + break;
10192 + }
10193 + if (irq == 5)
10194 + irq = 0;
10195 + }
10196 +
10197 + sb_setcoreidx(sbh, idx);
10198 +
10199 + return irq;
10200 +}
10201 +
10202 +/* Clears the specified MIPS IRQ. */
10203 +static void
10204 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
10205 +{
10206 + osl_t *osh;
10207 + void *regs;
10208 + sbconfig_t *sb;
10209 +
10210 + osh = sb_osh(sbh);
10211 +
10212 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10213 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10214 + ASSERT(regs);
10215 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10216 +
10217 + if (irq == 0)
10218 + W_REG(osh, &sb->sbintvec, 0);
10219 + else
10220 + OR_REG(osh, &sb->sbipsflag, sbips_int_mask[irq]);
10221 +}
10222 +
10223 +/*
10224 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
10225 + * IRQ 0 may be assigned more than once.
10226 + *
10227 + * The old assignment to the specified core is removed first.
10228 + */
10229 +static void
10230 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
10231 +{
10232 + osl_t *osh;
10233 + void *regs;
10234 + sbconfig_t *sb;
10235 + uint32 flag;
10236 + uint oldirq;
10237 +
10238 + osh = sb_osh(sbh);
10239 +
10240 + regs = sb_setcore(sbh, coreid, coreunit);
10241 + ASSERT(regs);
10242 + flag = sb_getflag(sbh);
10243 + oldirq = sb_irq(sbh);
10244 + if (oldirq)
10245 + sb_clearirq(sbh, oldirq);
10246 +
10247 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
10248 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
10249 + ASSERT(regs);
10250 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
10251 +
10252 + if (!oldirq)
10253 + AND_REG(osh, &sb->sbintvec, ~(1 << flag));
10254 +
10255 + if (irq == 0)
10256 + OR_REG(osh, &sb->sbintvec, 1 << flag);
10257 + else {
10258 + flag <<= sbips_int_shift[irq];
10259 + ASSERT(!(flag & ~sbips_int_mask[irq]));
10260 + flag |= R_REG(osh, &sb->sbipsflag) & ~sbips_int_mask[irq];
10261 + W_REG(osh, &sb->sbipsflag, flag);
10262 + }
10263 +}
10264 +
10265 +/*
10266 + * Initializes clocks and interrupts. SB and NVRAM access must be
10267 + * initialized prior to calling.
10268 + *
10269 + * 'shirqmap' enables virtual dedicated OS IRQ mapping if non-zero.
10270 + */
10271 +void
10272 +BCMINITFN(sb_mips_init)(sb_t *sbh, uint shirqmap)
10273 +{
10274 + osl_t *osh;
10275 + ulong hz, ns, tmp;
10276 + extifregs_t *eir;
10277 + chipcregs_t *cc;
10278 + char *value;
10279 + uint irq;
10280 +
10281 + osh = sb_osh(sbh);
10282 +
10283 + /* Figure out current SB clock speed */
10284 + if ((hz = sb_clock(sbh)) == 0)
10285 + hz = 100000000;
10286 + ns = 1000000000 / hz;
10287 +
10288 + /* Setup external interface timing */
10289 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
10290 + /* Initialize extif so we can get to the LEDs and external UART */
10291 + W_REG(osh, &eir->prog_config, CF_EN);
10292 +
10293 + /* Set timing for the flash */
10294 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10295 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
10296 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10297 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10298 +
10299 + /* Set programmable interface timing for external uart */
10300 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10301 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
10302 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
10303 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
10304 + W_REG(osh, &eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
10305 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
10306 + /* Set timing for the flash */
10307 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
10308 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
10309 + tmp |= CEIL(120, ns); /* W0 = 120nS */
10310 + if ((sb_corerev(sbh) < 9) ||
10311 + (BCMINIT(sb_chip)(sbh) == 0x5365))
10312 + W_REG(osh, &cc->flash_waitcount, tmp);
10313 +
10314 + if ((sb_corerev(sbh) < 9) ||
10315 + ((sb_chip(sbh) == BCM5350_CHIP_ID) && sb_chiprev(sbh) == 0) ||
10316 + (BCMINIT(sb_chip)(sbh) == 0x5365)) {
10317 + W_REG(osh, &cc->pcmcia_memwait, tmp);
10318 + }
10319 +
10320 + /* Save shared IRQ mapping base */
10321 + shirq_map_base = shirqmap;
10322 + }
10323 +
10324 + /* Chip specific initialization */
10325 + switch (sb_chip(sbh)) {
10326 + case BCM4710_CHIP_ID:
10327 + /* Clear interrupt map */
10328 + for (irq = 0; irq <= 4; irq++)
10329 + sb_clearirq(sbh, irq);
10330 + sb_setirq(sbh, 0, SB_CODEC, 0);
10331 + sb_setirq(sbh, 0, SB_EXTIF, 0);
10332 + sb_setirq(sbh, 2, SB_ENET, 1);
10333 + sb_setirq(sbh, 3, SB_ILINE20, 0);
10334 + sb_setirq(sbh, 4, SB_PCI, 0);
10335 + ASSERT(eir);
10336 + value = nvram_get("et0phyaddr");
10337 + if (value && !strcmp(value, "31")) {
10338 + /* Enable internal UART */
10339 + W_REG(osh, &eir->corecontrol, CC_UE);
10340 + /* Give USB its own interrupt */
10341 + sb_setirq(sbh, 1, SB_USB, 0);
10342 + } else {
10343 + /* Disable internal UART */
10344 + W_REG(osh, &eir->corecontrol, 0);
10345 + /* Give Ethernet its own interrupt */
10346 + sb_setirq(sbh, 1, SB_ENET, 0);
10347 + sb_setirq(sbh, 0, SB_USB, 0);
10348 + }
10349 + break;
10350 + case BCM5350_CHIP_ID:
10351 + /* Clear interrupt map */
10352 + for (irq = 0; irq <= 4; irq++)
10353 + sb_clearirq(sbh, irq);
10354 + sb_setirq(sbh, 0, SB_CC, 0);
10355 + sb_setirq(sbh, 0, SB_MIPS33, 0);
10356 + sb_setirq(sbh, 1, SB_D11, 0);
10357 + sb_setirq(sbh, 2, SB_ENET, 0);
10358 + sb_setirq(sbh, 3, SB_PCI, 0);
10359 + sb_setirq(sbh, 4, SB_USB, 0);
10360 + break;
10361 + case BCM4785_CHIP_ID:
10362 + /* Reassign PCI to irq 4 */
10363 + sb_setirq(sbh, 4, SB_PCI, 0);
10364 + break;
10365 + }
10366 +}
10367 +
10368 +uint32
10369 +BCMINITFN(sb_cpu_clock)(sb_t *sbh)
10370 +{
10371 + extifregs_t *eir;
10372 + chipcregs_t *cc;
10373 + uint32 n, m;
10374 + uint idx;
10375 + uint32 pll_type, rate = 0;
10376 +
10377 + /* get index of the current core */
10378 + idx = sb_coreidx(sbh);
10379 + pll_type = PLL_TYPE1;
10380 +
10381 + /* switch to extif or chipc core */
10382 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10383 + n = R_REG(osh, &eir->clockcontrol_n);
10384 + m = R_REG(osh, &eir->clockcontrol_sb);
10385 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10386 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10387 + n = R_REG(osh, &cc->clockcontrol_n);
10388 + if ((pll_type == PLL_TYPE2) ||
10389 + (pll_type == PLL_TYPE4) ||
10390 + (pll_type == PLL_TYPE6) ||
10391 + (pll_type == PLL_TYPE7))
10392 + m = R_REG(osh, &cc->clockcontrol_m3);
10393 + else if (pll_type == PLL_TYPE5) {
10394 + rate = 200000000;
10395 + goto out;
10396 + }
10397 + else if (pll_type == PLL_TYPE3) {
10398 + if (sb_chip(sbh) == BCM5365_CHIP_ID) {
10399 + rate = 200000000;
10400 + goto out;
10401 + }
10402 + /* 5350 uses m2 to control mips */
10403 + else
10404 + m = R_REG(osh, &cc->clockcontrol_m2);
10405 + } else
10406 + m = R_REG(osh, &cc->clockcontrol_sb);
10407 + } else
10408 + goto out;
10409 +
10410 +
10411 + /* calculate rate */
10412 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
10413 + rate = 100000000;
10414 + else
10415 + rate = sb_clock_rate(pll_type, n, m);
10416 +
10417 + if (pll_type == PLL_TYPE6)
10418 + rate = SB2MIPS_T6(rate);
10419 +
10420 +out:
10421 + /* switch back to previous core */
10422 + sb_setcoreidx(sbh, idx);
10423 +
10424 + return rate;
10425 +}
10426 +
10427 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
10428 +
10429 +static void
10430 +BCMINITFN(handler)(void)
10431 +{
10432 + __asm__(
10433 + ".set\tmips32\n\t"
10434 + "ssnop\n\t"
10435 + "ssnop\n\t"
10436 + /* Disable interrupts */
10437 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
10438 + "mfc0 $15, $12\n\t"
10439 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
10440 + "li $14, -31746\n\t"
10441 + "and $15, $15, $14\n\t"
10442 + "mtc0 $15, $12\n\t"
10443 + "eret\n\t"
10444 + "nop\n\t"
10445 + "nop\n\t"
10446 + ".set\tmips0");
10447 +}
10448 +
10449 +/* The following MUST come right after handler() */
10450 +static void
10451 +BCMINITFN(afterhandler)(void)
10452 +{
10453 +}
10454 +
10455 +/*
10456 + * Set the MIPS, backplane and PCI clocks as closely as possible.
10457 + *
10458 + * MIPS clocks synchronization function has been moved from PLL in chipcommon
10459 + * core rev. 15 to a DLL inside the MIPS core in 4785.
10460 + */
10461 +bool
10462 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
10463 +{
10464 + extifregs_t *eir = NULL;
10465 + chipcregs_t *cc = NULL;
10466 + mipsregs_t *mipsr = NULL;
10467 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
10468 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
10469 + uint32 pll_type, sync_mode;
10470 + uint ic_size, ic_lsize;
10471 + uint idx, i;
10472 +
10473 + /* PLL configuration: type 1 */
10474 + typedef struct {
10475 + uint32 mipsclock;
10476 + uint16 n;
10477 + uint32 sb;
10478 + uint32 pci33;
10479 + uint32 pci25;
10480 + } n3m_table_t;
10481 + static n3m_table_t BCMINITDATA(type1_table)[] = {
10482 + /* 96.000 32.000 24.000 */
10483 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 },
10484 + /* 100.000 33.333 25.000 */
10485 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 },
10486 + /* 104.000 31.200 24.960 */
10487 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 },
10488 + /* 108.000 32.400 24.923 */
10489 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 },
10490 + /* 112.000 32.000 24.889 */
10491 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 },
10492 + /* 115.200 32.000 24.000 */
10493 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 },
10494 + /* 120.000 30.000 24.000 */
10495 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 },
10496 + /* 124.800 31.200 24.960 */
10497 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 },
10498 + /* 128.000 32.000 24.000 */
10499 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 },
10500 + /* 132.000 33.000 24.750 */
10501 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 },
10502 + /* 136.000 32.640 24.727 */
10503 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 },
10504 + /* 140.000 30.000 24.706 */
10505 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 },
10506 + /* 144.000 30.857 24.686 */
10507 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 },
10508 + /* 150.857 33.000 24.000 */
10509 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 },
10510 + /* 152.000 32.571 24.000 */
10511 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 },
10512 + /* 156.000 31.200 24.960 */
10513 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 },
10514 + /* 160.000 32.000 24.000 */
10515 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 },
10516 + /* 163.200 32.640 24.727 */
10517 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 },
10518 + /* 168.000 32.000 24.889 */
10519 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 },
10520 + /* 176.000 33.000 24.000 */
10521 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 },
10522 + };
10523 +
10524 + /* PLL configuration: type 3 */
10525 + typedef struct {
10526 + uint32 mipsclock;
10527 + uint16 n;
10528 + uint32 m2; /* that is the clockcontrol_m2 */
10529 + } type3_table_t;
10530 + static type3_table_t type3_table[] = {
10531 + /* for 5350, mips clock is always double sb clock */
10532 + { 150000000, 0x311, 0x4020005 },
10533 + { 200000000, 0x311, 0x4020003 },
10534 + };
10535 +
10536 + /* PLL configuration: type 2, 4, 7 */
10537 + typedef struct {
10538 + uint32 mipsclock;
10539 + uint32 sbclock;
10540 + uint16 n;
10541 + uint32 sb;
10542 + uint32 pci33;
10543 + uint32 m2;
10544 + uint32 m3;
10545 + uint32 ratio_cfg;
10546 + uint32 ratio_parm;
10547 + uint32 d11_r1;
10548 + uint32 d11_r2;
10549 + } n4m_table_t;
10550 + static n4m_table_t BCMINITDATA(type2_table)[] = {
10551 + { 120000000, 60000000, 0x0303, 0x01000200, 0x01000600, 0x01000200, 0x05000200, 11,
10552 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10553 + { 150000000, 75000000, 0x0303, 0x01000100, 0x01000600, 0x01000100, 0x05000100, 11,
10554 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10555 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8,
10556 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10557 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11,
10558 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10559 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11,
10560 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10561 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10562 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10563 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11,
10564 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10565 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10566 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10567 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8,
10568 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10569 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11,
10570 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10571 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11,
10572 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10573 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11,
10574 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10575 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10576 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10577 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10578 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10579 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10580 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10581 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8,
10582 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10583 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11,
10584 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10585 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01010100, 0x05000100, 8,
10586 + 0x012a00a9, 9 /* ratio 4/9 */, 0x012a00a9 },
10587 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01010100, 0x05000100, 11,
10588 + 0x0aaa0555, 8 /* ratio 4/8 */, 0x00aa0055 },
10589 + { 330000000, 132000000, 0x0903, 0x01000200, 0x00020200, 0x01010100, 0x05000100, 0,
10590 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10591 + { 330000000, 146666666, 0x0903, 0x01010000, 0x00020200, 0x01010100, 0x05000100, 0,
10592 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10593 + { 330000000, 165000000, 0x0903, 0x01000100, 0x00020200, 0x01010100, 0x05000100, 0,
10594 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10595 + { 360000000, 120000000, 0x0a03, 0x01000300, 0x00010201, 0x01010200, 0x05000100, 0,
10596 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10597 + { 360000000, 144000000, 0x0a03, 0x01000200, 0x00010201, 0x01010200, 0x05000100, 0,
10598 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10599 + { 360000000, 160000000, 0x0a03, 0x01010000, 0x00010201, 0x01010200, 0x05000100, 0,
10600 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10601 + { 360000000, 180000000, 0x0a03, 0x01000100, 0x00010201, 0x01010200, 0x05000100, 0,
10602 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10603 + { 390000000, 130000000, 0x0b03, 0x01010100, 0x00020101, 0x01020100, 0x05000100, 0,
10604 + 0, 12 /* ratio 4/12 */, 0x04920492 },
10605 + { 390000000, 156000000, 0x0b03, 0x01000200, 0x00020101, 0x01020100, 0x05000100, 0,
10606 + 0, 10 /* ratio 4/10 */, 0x02520129 },
10607 + { 390000000, 173000000, 0x0b03, 0x01010000, 0x00020101, 0x01020100, 0x05000100, 0,
10608 + 0, 9 /* ratio 4/9 */, 0x012a00a9 },
10609 + { 390000000, 195000000, 0x0b03, 0x01000100, 0x00020101, 0x01020100, 0x05000100, 0,
10610 + 0, 8 /* ratio 4/8 */, 0x00aa0055 },
10611 + };
10612 + static n4m_table_t BCMINITDATA(type4_table)[] = {
10613 + { 120000000, 60000000, 0x0009, 0x11020009, 0x01030203, 0x11020009, 0x04000009, 11,
10614 + 0x0aaa0555 },
10615 + { 150000000, 75000000, 0x0009, 0x11050002, 0x01030203, 0x11050002, 0x04000005, 11,
10616 + 0x0aaa0555 },
10617 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10618 + 0x0aaa0555 },
10619 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11,
10620 + 0x0aaa0555 },
10621 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10622 + 0x0aaa0555 },
10623 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10624 + 0x0aaa0555 },
10625 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11,
10626 + 0x0aaa0555 },
10627 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10628 + 0x0aaa0555 },
10629 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10630 + 0x0aaa0555 },
10631 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11,
10632 + 0x0aaa0555 },
10633 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8,
10634 + 0x012a00a9 },
10635 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10636 + 0x0aaa0555 },
10637 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13,
10638 + 0x254a14a9 },
10639 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11,
10640 + 0x0aaa0555 },
10641 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9,
10642 + 0x02520129 },
10643 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10644 + 0x0aaa0555 },
10645 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11,
10646 + 0x0aaa0555 },
10647 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13,
10648 + 0x254a14a9 },
10649 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10650 + 0x254a14a9 },
10651 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13,
10652 + 0x254a14a9 },
10653 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9,
10654 + 0x02520129 },
10655 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11,
10656 + 0x0aaa0555 }
10657 + };
10658 + static n4m_table_t BCMINITDATA(type7_table)[] = {
10659 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10660 + 0x0aaa0555 },
10661 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11,
10662 + 0x0aaa0555 },
10663 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10664 + 0x0aaa0555 },
10665 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11,
10666 + 0x0aaa0555 },
10667 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11,
10668 + 0x0aaa0555 },
10669 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11,
10670 + 0x0aaa0555 },
10671 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11,
10672 + 0x0aaa0555 },
10673 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11,
10674 + 0x0aaa0555 },
10675 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10676 + 0x0aaa0555 },
10677 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10678 + 0x0aaa0555 },
10679 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11,
10680 + 0x0aaa0555 },
10681 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11,
10682 + 0x0aaa0555 },
10683 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11,
10684 + 0x0aaa0555 },
10685 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11,
10686 + 0x0aaa0555 }
10687 + };
10688 +
10689 + ulong start, end, dst;
10690 + bool ret = FALSE;
10691 +
10692 + volatile uint32 *dll_ctrl = (volatile uint32 *)0xff400008;
10693 + volatile uint32 *dll_r1 = (volatile uint32 *)0xff400010;
10694 + volatile uint32 *dll_r2 = (volatile uint32 *)0xff400018;
10695 +
10696 + /* get index of the current core */
10697 + idx = sb_coreidx(sbh);
10698 + clockcontrol_m2 = NULL;
10699 +
10700 + /* switch to extif or chipc core */
10701 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
10702 + pll_type = PLL_TYPE1;
10703 + clockcontrol_n = &eir->clockcontrol_n;
10704 + clockcontrol_sb = &eir->clockcontrol_sb;
10705 + clockcontrol_pci = &eir->clockcontrol_pci;
10706 + clockcontrol_m2 = &cc->clockcontrol_m2;
10707 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
10708 + pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
10709 + if (pll_type == PLL_TYPE6) {
10710 + clockcontrol_n = NULL;
10711 + clockcontrol_sb = NULL;
10712 + clockcontrol_pci = NULL;
10713 + } else {
10714 + clockcontrol_n = &cc->clockcontrol_n;
10715 + clockcontrol_sb = &cc->clockcontrol_sb;
10716 + clockcontrol_pci = &cc->clockcontrol_pci;
10717 + clockcontrol_m2 = &cc->clockcontrol_m2;
10718 + }
10719 + } else
10720 + goto done;
10721 +
10722 + if (pll_type == PLL_TYPE6) {
10723 + /* Silence compilers */
10724 + orig_n = orig_sb = orig_pci = 0;
10725 + } else {
10726 + /* Store the current clock register values */
10727 + orig_n = R_REG(osh, clockcontrol_n);
10728 + orig_sb = R_REG(osh, clockcontrol_sb);
10729 + orig_pci = R_REG(osh, clockcontrol_pci);
10730 + }
10731 +
10732 + if (pll_type == PLL_TYPE1) {
10733 + /* Keep the current PCI clock if not specified */
10734 + if (pciclock == 0) {
10735 + pciclock = sb_clock_rate(pll_type, R_REG(osh, clockcontrol_n),
10736 + R_REG(osh, clockcontrol_pci));
10737 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
10738 + }
10739 +
10740 + /* Search for the closest MIPS clock less than or equal to a preferred value */
10741 + for (i = 0; i < ARRAYSIZE(type1_table); i++) {
10742 + ASSERT(type1_table[i].mipsclock ==
10743 + sb_clock_rate(pll_type, type1_table[i].n,
10744 + type1_table[i].sb));
10745 + if (type1_table[i].mipsclock > mipsclock)
10746 + break;
10747 + }
10748 + if (i == 0) {
10749 + ret = FALSE;
10750 + goto done;
10751 + } else {
10752 + ret = TRUE;
10753 + i--;
10754 + }
10755 + ASSERT(type1_table[i].mipsclock <= mipsclock);
10756 +
10757 + /* No PLL change */
10758 + if ((orig_n == type1_table[i].n) &&
10759 + (orig_sb == type1_table[i].sb) &&
10760 + (orig_pci == type1_table[i].pci33))
10761 + goto done;
10762 +
10763 + /* Set the PLL controls */
10764 + W_REG(osh, clockcontrol_n, type1_table[i].n);
10765 + W_REG(osh, clockcontrol_sb, type1_table[i].sb);
10766 + if (pciclock == 25000000)
10767 + W_REG(osh, clockcontrol_pci, type1_table[i].pci25);
10768 + else
10769 + W_REG(osh, clockcontrol_pci, type1_table[i].pci33);
10770 +
10771 + /* Reset */
10772 + sb_watchdog(sbh, 1);
10773 + while (1);
10774 + } else if (pll_type == PLL_TYPE3) {
10775 + /* 5350 */
10776 + if (sb_chip(sbh) != BCM5365_CHIP_ID) {
10777 + /*
10778 + * Search for the closest MIPS clock less than or equal to
10779 + * a preferred value.
10780 + */
10781 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
10782 + if (type3_table[i].mipsclock > mipsclock)
10783 + break;
10784 + }
10785 + if (i == 0) {
10786 + ret = FALSE;
10787 + goto done;
10788 + } else {
10789 + ret = TRUE;
10790 + i--;
10791 + }
10792 + ASSERT(type3_table[i].mipsclock <= mipsclock);
10793 +
10794 + /* No PLL change */
10795 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10796 + if ((orig_n == type3_table[i].n) &&
10797 + (orig_m2 == type3_table[i].m2)) {
10798 + goto done;
10799 + }
10800 +
10801 + /* Set the PLL controls */
10802 + W_REG(osh, clockcontrol_n, type3_table[i].n);
10803 + W_REG(osh, clockcontrol_m2, type3_table[i].m2);
10804 +
10805 + /* Reset */
10806 + sb_watchdog(sbh, 1);
10807 + while (1);
10808 + }
10809 + } else if ((pll_type == PLL_TYPE2) ||
10810 + (pll_type == PLL_TYPE4) ||
10811 + (pll_type == PLL_TYPE6) ||
10812 + (pll_type == PLL_TYPE7)) {
10813 + n4m_table_t *table = NULL, *te;
10814 + uint tabsz = 0;
10815 +
10816 + ASSERT(cc);
10817 +
10818 + orig_mips = R_REG(osh, &cc->clockcontrol_m3);
10819 +
10820 + switch (pll_type) {
10821 + case PLL_TYPE6: {
10822 + uint32 new_mips = 0;
10823 +
10824 + ret = TRUE;
10825 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
10826 + new_mips = CC_T6_MMASK;
10827 +
10828 + if (orig_mips == new_mips)
10829 + goto done;
10830 +
10831 + W_REG(osh, &cc->clockcontrol_m3, new_mips);
10832 + goto end_fill;
10833 + }
10834 + case PLL_TYPE2:
10835 + table = type2_table;
10836 + tabsz = ARRAYSIZE(type2_table);
10837 + break;
10838 + case PLL_TYPE4:
10839 + table = type4_table;
10840 + tabsz = ARRAYSIZE(type4_table);
10841 + break;
10842 + case PLL_TYPE7:
10843 + table = type7_table;
10844 + tabsz = ARRAYSIZE(type7_table);
10845 + break;
10846 + default:
10847 + ASSERT("No table for plltype" == NULL);
10848 + break;
10849 + }
10850 +
10851 + /* Store the current clock register values */
10852 + orig_m2 = R_REG(osh, &cc->clockcontrol_m2);
10853 + orig_ratio_parm = 0;
10854 + orig_ratio_cfg = 0;
10855 +
10856 + /* Look up current ratio */
10857 + for (i = 0; i < tabsz; i++) {
10858 + if ((orig_n == table[i].n) &&
10859 + (orig_sb == table[i].sb) &&
10860 + (orig_pci == table[i].pci33) &&
10861 + (orig_m2 == table[i].m2) &&
10862 + (orig_mips == table[i].m3)) {
10863 + orig_ratio_parm = table[i].ratio_parm;
10864 + orig_ratio_cfg = table[i].ratio_cfg;
10865 + break;
10866 + }
10867 + }
10868 +
10869 + /* Search for the closest MIPS clock greater or equal to a preferred value */
10870 + for (i = 0; i < tabsz; i++) {
10871 + ASSERT(table[i].mipsclock ==
10872 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
10873 + if ((mipsclock <= table[i].mipsclock) &&
10874 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
10875 + break;
10876 + }
10877 + if (i == tabsz) {
10878 + ret = FALSE;
10879 + goto done;
10880 + } else {
10881 + te = &table[i];
10882 + ret = TRUE;
10883 + }
10884 +
10885 + /* No PLL change */
10886 + if ((orig_n == te->n) &&
10887 + (orig_sb == te->sb) &&
10888 + (orig_pci == te->pci33) &&
10889 + (orig_m2 == te->m2) &&
10890 + (orig_mips == te->m3))
10891 + goto done;
10892 +
10893 + /* Set the PLL controls */
10894 + W_REG(osh, clockcontrol_n, te->n);
10895 + W_REG(osh, clockcontrol_sb, te->sb);
10896 + W_REG(osh, clockcontrol_pci, te->pci33);
10897 + W_REG(osh, &cc->clockcontrol_m2, te->m2);
10898 + W_REG(osh, &cc->clockcontrol_m3, te->m3);
10899 +
10900 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
10901 + if ((pll_type == PLL_TYPE7) && (te->sb != te->m2) &&
10902 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
10903 + W_REG(osh, &cc->chipcontrol,
10904 + R_REG(osh, &cc->chipcontrol) | 0x100);
10905 +
10906 + /* No ratio change */
10907 + if (sb_chip(sbh) != BCM4785_CHIP_ID) {
10908 + if (orig_ratio_parm == te->ratio_parm)
10909 + goto end_fill;
10910 + }
10911 +
10912 + /* Preload the code into the cache */
10913 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
10914 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10915 + start = ((ulong) &&start_fill_4785) & ~(ic_lsize - 1);
10916 + end = ((ulong) &&end_fill_4785 + (ic_lsize - 1)) & ~(ic_lsize - 1);
10917 + }
10918 + else {
10919 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
10920 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
10921 + }
10922 + while (start < end) {
10923 + cache_op(start, Fill_I);
10924 + start += ic_lsize;
10925 + }
10926 +
10927 + /* Copy the handler */
10928 + start = (ulong) &handler;
10929 + end = (ulong) &afterhandler;
10930 + dst = KSEG1ADDR(0x180);
10931 + for (i = 0; i < (end - start); i += 4)
10932 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
10933 +
10934 + /* Preload the handler into the cache one line at a time */
10935 + for (i = 0; i < (end - start); i += ic_lsize)
10936 + cache_op(dst + i, Fill_I);
10937 +
10938 + /* Clear BEV bit */
10939 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
10940 +
10941 + /* Enable interrupts */
10942 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
10943 +
10944 + /* 4785 clock freq change procedures */
10945 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
10946 + start_fill_4785:
10947 + /* Switch to async */
10948 + MTC0(C0_BROADCOM, 4, (1 << 22));
10949 +
10950 + /* Set clock ratio in MIPS */
10951 + *dll_r1 = (*dll_r1 & 0xfffffff0) | (te->d11_r1 - 1);
10952 + *dll_r2 = te->d11_r2;
10953 +
10954 + /* Enable new settings in MIPS */
10955 + *dll_r1 = *dll_r1 | 0xc0000000;
10956 +
10957 + /* Set active cfg */
10958 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) | (1 << 3) | 1);
10959 +
10960 + /* Fake soft reset (clock cfg registers not reset) */
10961 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
10962 +
10963 + /* Clear active cfg */
10964 + MTC0(C0_BROADCOM, 2, MFC0(C0_BROADCOM, 2) & ~(1 << 3));
10965 +
10966 + /* set watchdog timer */
10967 + W_REG(osh, &cc->watchdog, 20);
10968 + (void) R_REG(osh, &cc->chipid);
10969 +
10970 + /* wait for timer interrupt */
10971 + __asm__ __volatile__(
10972 + ".set\tmips3\n\t"
10973 + "sync\n\t"
10974 + "wait\n\t"
10975 + ".set\tmips0");
10976 + end_fill_4785:
10977 + while (1);
10978 + }
10979 + /* Generic clock freq change procedures */
10980 + else {
10981 + /* Enable MIPS timer interrupt */
10982 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
10983 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
10984 + ASSERT(mipsr);
10985 + W_REG(osh, &mipsr->intmask, 1);
10986 +
10987 + start_fill:
10988 + /* step 1, set clock ratios */
10989 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
10990 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
10991 +
10992 + /* step 2: program timer intr */
10993 + W_REG(osh, &mipsr->timer, 100);
10994 + (void) R_REG(osh, &mipsr->timer);
10995 +
10996 + /* step 3, switch to async */
10997 + sync_mode = MFC0(C0_BROADCOM, 4);
10998 + MTC0(C0_BROADCOM, 4, 1 << 22);
10999 +
11000 + /* step 4, set cfg active */
11001 + MTC0(C0_BROADCOM, 2, (1 << 3) | 1);
11002 +
11003 + /* steps 5 & 6 */
11004 + __asm__ __volatile__(
11005 + ".set\tmips3\n\t"
11006 + "wait\n\t"
11007 + ".set\tmips0");
11008 +
11009 + /* step 7, clear cfg active */
11010 + MTC0(C0_BROADCOM, 2, 0);
11011 +
11012 + /* Additional Step: set back to orig sync mode */
11013 + MTC0(C0_BROADCOM, 4, sync_mode);
11014 +
11015 + /* step 8, fake soft reset */
11016 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | (1 << 2));
11017 +
11018 + end_fill:
11019 + /* set watchdog timer */
11020 + W_REG(osh, &cc->watchdog, 20);
11021 + (void) R_REG(osh, &cc->chipid);
11022 +
11023 + /* wait for timer interrupt */
11024 + __asm__ __volatile__(
11025 + ".set\tmips3\n\t"
11026 + "sync\n\t"
11027 + "wait\n\t"
11028 + ".set\tmips0");
11029 + while (1);
11030 + }
11031 + }
11032 +
11033 +done:
11034 + /* Enable 4785 DLL */
11035 + if (sb_chip(sbh) == BCM4785_CHIP_ID) {
11036 + uint32 tmp;
11037 +
11038 + /* set mask to 1e, enable DLL (bit 0) */
11039 + *dll_ctrl |= 0x0041e021;
11040 +
11041 + /* enable aggressive hardware mode */
11042 + *dll_ctrl |= 0x00000080;
11043 +
11044 + /* wait for lock flag to clear */
11045 + while ((*dll_ctrl & 0x2) == 0);
11046 +
11047 + /* clear sticky flags (clear on write 1) */
11048 + tmp = *dll_ctrl;
11049 + *dll_ctrl = tmp;
11050 +
11051 + /* set mask to 5b'10001 */
11052 + *dll_ctrl = (*dll_ctrl & 0xfffc1fff) | 0x00022000;
11053 +
11054 + /* enable sync mode */
11055 + MTC0(C0_BROADCOM, 4, MFC0(C0_BROADCOM, 4) & 0xfe3fffff);
11056 + (void)MFC0(C0_BROADCOM, 4);
11057 + }
11058 +
11059 + /* switch back to previous core */
11060 + sb_setcoreidx(sbh, idx);
11061 +
11062 + return ret;
11063 +}
11064 +
11065 +void
11066 +BCMINITFN(enable_pfc)(uint32 mode)
11067 +{
11068 + ulong start, end;
11069 + uint ic_size, ic_lsize;
11070 +
11071 + /* If auto then choose the correct mode for this
11072 + * platform, currently we only ever select one mode
11073 + */
11074 + if (mode == PFC_AUTO)
11075 + mode = PFC_INST;
11076 +
11077 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
11078 +
11079 + /* enable prefetch cache if available */
11080 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
11081 + start = ((ulong) &&setpfc_start) & ~(ic_lsize - 1);
11082 + end = ((ulong) &&setpfc_end + (ic_lsize - 1)) & ~(ic_lsize - 1);
11083 +
11084 + /* Preload setpfc code into the cache one line at a time */
11085 + while (start < end) {
11086 + cache_op(start, Fill_I);
11087 + start += ic_lsize;
11088 + }
11089 +
11090 + /* Now set the pfc */
11091 + setpfc_start:
11092 + /* write range */
11093 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
11094 +
11095 + /* enable */
11096 + *(volatile uint32 *)PFC_CR0 = mode;
11097 + setpfc_end:
11098 + /* Compiler foder */
11099 + ic_size = 0;
11100 + }
11101 +}
11102 +
11103 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
11104 +uint32
11105 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
11106 +{
11107 + osl_t *osh;
11108 + sbmemcregs_t *memc;
11109 + uint32 ret = 0;
11110 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
11111 + uint idx, rev;
11112 +
11113 + osh = sb_osh(sbh);
11114 +
11115 + idx = sb_coreidx(sbh);
11116 +
11117 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
11118 + if (memc == 0)
11119 + goto out;
11120 +
11121 + rev = sb_corerev(sbh);
11122 +
11123 + config = R_REG(osh, &memc->config);
11124 + wr = R_REG(osh, &memc->wrncdlcor);
11125 + rd = R_REG(osh, &memc->rdncdlcor);
11126 + misc = R_REG(osh, &memc->miscdlyctl);
11127 + dqsg = R_REG(osh, &memc->dqsgatencdl);
11128 +
11129 + rd &= MEMC_RDNCDLCOR_RD_MASK;
11130 + wr &= MEMC_WRNCDLCOR_WR_MASK;
11131 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
11132 +
11133 + if (config & MEMC_CONFIG_DDR) {
11134 + ret = (wr << 16) | (rd << 8) | dqsg;
11135 + } else {
11136 + if (rev > 0)
11137 + cd = rd;
11138 + else
11139 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
11140 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
11141 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
11142 + ret = (sm << 16) | (sd << 8) | cd;
11143 + }
11144 +
11145 +out:
11146 + /* switch back to previous core */
11147 + sb_setcoreidx(sbh, idx);
11148 +
11149 + return ret;
11150 +}
11151 +
11152 +#if defined(BCMPERFSTATS)
11153 +/*
11154 + * CP0 Register 25 supports 4 semi-independent 32bit performance counters.
11155 + * $25 select 0, 1, 2, and 3 are the counters. The counters *decrement* (who thought this one up?)
11156 + * $25 select 4 and 5 each contain 2-16bit control fields, one for each of the 4 counters
11157 + * $25 select 6 is the global perf control register.
11158 + */
11159 +/* enable and start instruction counting */
11160 +
11161 +void
11162 +hndmips_perf_instrcount_enable()
11163 +{
11164 + MTC0(C0_PERFORMANCE, 6, 0x80000200); /* global enable perf counters */
11165 + MTC0(C0_PERFORMANCE, 4,
11166 + 0x8044 | MFC0(C0_PERFORMANCE, 4)); /* enable instruction counting for counter 0 */
11167 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter zero */
11168 +}
11169 +
11170 +/* enable and start I$ hit and I$ miss counting */
11171 +void
11172 +hndmips_perf_icachecount_enable(void)
11173 +{
11174 + MTC0(C0_PERFORMANCE, 6, 0x80000218); /* enable I$ counting */
11175 + MTC0(C0_PERFORMANCE, 4, 0x80148018); /* count I$ hits in cntr 0 and misses in cntr 1 */
11176 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # I$ hits */
11177 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # I$ misses */
11178 +}
11179 +
11180 +/* enable and start D$ hit and I$ miss counting */
11181 +void
11182 +hndmips_perf_dcachecount_enable(void)
11183 +{
11184 + MTC0(C0_PERFORMANCE, 6, 0x80000211); /* enable D$ counting */
11185 + MTC0(C0_PERFORMANCE, 4, 0x80248028); /* count D$ hits in cntr 0 and misses in cntr 1 */
11186 + MTC0(C0_PERFORMANCE, 0, 0); /* zero counter 0 - # D$ hits */
11187 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter 1 - # D$ misses */
11188 +}
11189 +
11190 +void
11191 +hndmips_perf_icache_miss_enable()
11192 +{
11193 + MTC0(C0_PERFORMANCE, 4,
11194 + 0x80140000 | MFC0(C0_PERFORMANCE, 4)); /* enable cache misses counting for counter 1 */
11195 + MTC0(C0_PERFORMANCE, 1, 0); /* zero counter one */
11196 +}
11197 +
11198 +
11199 +void
11200 +hndmips_perf_icache_hit_enable()
11201 +{
11202 + MTC0(C0_PERFORMANCE, 5, 0x8018 | MFC0(C0_PERFORMANCE, 5));
11203 + /* enable cache hits counting for counter 2 */
11204 + MTC0(C0_PERFORMANCE, 2, 0); /* zero counter 2 */
11205 +}
11206 +
11207 +uint32
11208 +hndmips_perf_read_instrcount()
11209 +{
11210 + return -(long)(MFC0(C0_PERFORMANCE, 0));
11211 +}
11212 +
11213 +uint32
11214 +hndmips_perf_read_cache_miss()
11215 +{
11216 + return -(long)(MFC0(C0_PERFORMANCE, 1));
11217 +}
11218 +
11219 +uint32
11220 +hndmips_perf_read_cache_hit()
11221 +{
11222 + return -(long)(MFC0(C0_PERFORMANCE, 2));
11223 +}
11224 +
11225 +#endif /* BCMINTERNAL | BCMPERFSTATS */
11226 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
11227 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
11228 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2006-05-02 17:37:13.000000000 +0200
11229 @@ -0,0 +1,768 @@
11230 +/*
11231 + * Low-Level PCI and SB support for BCM47xx
11232 + *
11233 + * Copyright 2006, Broadcom Corporation
11234 + * All Rights Reserved.
11235 + *
11236 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11237 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11238 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11239 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11240 + *
11241 + * $Id: hndpci.c,v 1.1.1.3 2006/04/08 06:13:39 honor Exp $
11242 + */
11243 +
11244 +#include <typedefs.h>
11245 +#include <osl.h>
11246 +#include <pcicfg.h>
11247 +#include <bcmdevs.h>
11248 +#include <sbconfig.h>
11249 +#include <bcmutils.h>
11250 +#include <sbutils.h>
11251 +#include <sbpci.h>
11252 +#include <bcmendian.h>
11253 +#include <bcmnvram.h>
11254 +#include <hndcpu.h>
11255 +#include <hndmips.h>
11256 +#include <hndpci.h>
11257 +
11258 +/* debug/trace */
11259 +#ifdef BCMDBG_PCI
11260 +#define PCI_MSG(args) printf args
11261 +#else
11262 +#define PCI_MSG(args)
11263 +#endif /* BCMDBG_PCI */
11264 +
11265 +/* Can free sbpci_init() memory after boot */
11266 +#ifndef linux
11267 +#define __init
11268 +#endif /* linux */
11269 +
11270 +/* Emulated configuration space */
11271 +typedef struct {
11272 + int n;
11273 + uint size0;
11274 + uint size1;
11275 + uint size2;
11276 + uint size3;
11277 +} sb_bar_cfg_t;
11278 +static pci_config_regs sb_config_regs[SB_MAXCORES];
11279 +static sb_bar_cfg_t sb_bar_cfg[SB_MAXCORES];
11280 +
11281 +/* Links to emulated and real PCI configuration spaces */
11282 +#define MAXFUNCS 2
11283 +typedef struct {
11284 + pci_config_regs *emu; /* emulated PCI config */
11285 + pci_config_regs *pci; /* real PCI config */
11286 + sb_bar_cfg_t *bar; /* region sizes */
11287 +} sb_pci_cfg_t;
11288 +static sb_pci_cfg_t sb_pci_cfg[SB_MAXCORES][MAXFUNCS];
11289 +
11290 +/* Special emulated config space for non-existing device */
11291 +static pci_config_regs sb_pci_null = { 0xffff, 0xffff };
11292 +
11293 +/* Banned cores */
11294 +static uint16 pci_ban[SB_MAXCORES] = { 0 };
11295 +static uint pci_banned = 0;
11296 +
11297 +/* CardBus mode */
11298 +static bool cardbus = FALSE;
11299 +
11300 +/* Disable PCI host core */
11301 +static bool pci_disabled = FALSE;
11302 +
11303 +/* Host bridge slot #, default to 0 */
11304 +static uint8 pci_hbslot = 0;
11305 +
11306 +/* Internal macros */
11307 +#define PCI_SLOTAD_MAP 16 /* SLOT<n> mapps to AD<n+16> */
11308 +#define PCI_HBSBCFG_REV 8 /* MIN. core rev. required to
11309 + * access host bridge PCI cfg space
11310 + * from SB
11311 + */
11312 +
11313 +/*
11314 + * Functions for accessing external PCI configuration space
11315 + */
11316 +
11317 +/* Assume one-hot slot wiring */
11318 +#define PCI_SLOT_MAX 16 /* Max. PCI Slots */
11319 +
11320 +static uint32
11321 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
11322 +{
11323 + uint coreidx;
11324 + sbpciregs_t *regs;
11325 + uint32 addr = 0;
11326 + osl_t *osh;
11327 +
11328 + /* CardBusMode supports only one device */
11329 + if (cardbus && dev > 1)
11330 + return 0;
11331 +
11332 + osh = sb_osh(sbh);
11333 +
11334 + coreidx = sb_coreidx(sbh);
11335 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
11336 +
11337 + /* Type 0 transaction */
11338 + if (bus == 1) {
11339 + /* Skip unwired slots */
11340 + if (dev < PCI_SLOT_MAX) {
11341 + uint32 win;
11342 +
11343 + /* Slide the PCI window to the appropriate slot */
11344 + win = (SBTOPCI_CFG0 | ((1 << (dev + PCI_SLOTAD_MAP)) & SBTOPCI1_MASK));
11345 + W_REG(osh, &regs->sbtopci1, win);
11346 + addr = SB_PCI_CFG |
11347 + ((1 << (dev + PCI_SLOTAD_MAP)) & ~SBTOPCI1_MASK) |
11348 + (func << PCICFG_FUN_SHIFT) |
11349 + (off & ~3);
11350 + }
11351 + } else {
11352 + /* Type 1 transaction */
11353 + W_REG(osh, &regs->sbtopci1, SBTOPCI_CFG1);
11354 + addr = SB_PCI_CFG |
11355 + (bus << PCICFG_BUS_SHIFT) |
11356 + (dev << PCICFG_SLOT_SHIFT) |
11357 + (func << PCICFG_FUN_SHIFT) |
11358 + (off & ~3);
11359 + }
11360 +
11361 + sb_setcoreidx(sbh, coreidx);
11362 +
11363 + return addr;
11364 +}
11365 +
11366 +/*
11367 + * Read host bridge PCI config registers from Silicon Backplane (>=rev8).
11368 + *
11369 + * It returns TRUE to indicate that access to the host bridge's pci config
11370 + * from SB is ok, and values in 'addr' and 'val' are valid.
11371 + *
11372 + * It can only read registers at multiple of 4-bytes. Callers must pick up
11373 + * needed bytes from 'val' based on 'off' value. Value in 'addr' reflects
11374 + * the register address where value in 'val' is read.
11375 + */
11376 +static bool
11377 +sb_pcihb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off,
11378 + uint32 **addr, uint32 *val)
11379 +{
11380 + sbpciregs_t *regs;
11381 + osl_t *osh;
11382 + uint coreidx;
11383 + bool ret = FALSE;
11384 +
11385 + /* sanity check */
11386 + ASSERT(bus == 1);
11387 + ASSERT(dev == pci_hbslot);
11388 + ASSERT(func == 0);
11389 +
11390 + osh = sb_osh(sbh);
11391 +
11392 + /* read pci config when core rev >= 8 */
11393 + coreidx = sb_coreidx(sbh);
11394 + regs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
11395 + if (regs && sb_corerev(sbh) >= PCI_HBSBCFG_REV) {
11396 + *addr = (uint32 *)&regs->pcicfg[func][off >> 2];
11397 + *val = R_REG(osh, *addr);
11398 + ret = TRUE;
11399 + }
11400 + sb_setcoreidx(sbh, coreidx);
11401 +
11402 + return ret;
11403 +}
11404 +
11405 +int
11406 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11407 +{
11408 + uint32 addr = 0, *reg = NULL, val;
11409 + int ret = 0;
11410 +
11411 + /*
11412 + * Set value to -1 when:
11413 + * flag 'pci_disabled' is true;
11414 + * value of 'addr' is zero;
11415 + * REG_MAP() fails;
11416 + * BUSPROBE() fails;
11417 + */
11418 + if (pci_disabled)
11419 + val = 0xffffffff;
11420 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11421 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11422 + ;
11423 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11424 + ((reg = (uint32 *)REG_MAP(addr, len)) == 0) ||
11425 + (BUSPROBE(val, reg) != 0))
11426 + val = 0xffffffff;
11427 +
11428 + PCI_MSG(("%s: 0x%x <= 0x%p(0x%x), len %d, off 0x%x, buf 0x%p\n",
11429 + __FUNCTION__, val, reg, addr, len, off, buf));
11430 +
11431 + val >>= 8 * (off & 3);
11432 + if (len == 4)
11433 + *((uint32 *) buf) = val;
11434 + else if (len == 2)
11435 + *((uint16 *) buf) = (uint16) val;
11436 + else if (len == 1)
11437 + *((uint8 *) buf) = (uint8) val;
11438 + else
11439 + ret = -1;
11440 +
11441 + if (reg && addr)
11442 + REG_UNMAP(reg);
11443 +
11444 + return ret;
11445 +}
11446 +
11447 +int
11448 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11449 +{
11450 + osl_t *osh;
11451 + uint32 addr = 0, *reg = NULL, val;
11452 + int ret = 0;
11453 +
11454 + osh = sb_osh(sbh);
11455 +
11456 + /*
11457 + * Ignore write attempt when:
11458 + * flag 'pci_disabled' is true;
11459 + * value of 'addr' is zero;
11460 + * REG_MAP() fails;
11461 + * BUSPROBE() fails;
11462 + */
11463 + if (pci_disabled)
11464 + return 0;
11465 + else if (bus == 1 && dev == pci_hbslot && func == 0 &&
11466 + sb_pcihb_read_config(sbh, bus, dev, func, off, &reg, &val))
11467 + ;
11468 + else if (((addr = config_cmd(sbh, bus, dev, func, off)) == 0) ||
11469 + ((reg = (uint32 *) REG_MAP(addr, len)) == 0) ||
11470 + (BUSPROBE(val, reg) != 0))
11471 + goto done;
11472 +
11473 + if (len == 4)
11474 + val = *((uint32 *) buf);
11475 + else if (len == 2) {
11476 + val &= ~(0xffff << (8 * (off & 3)));
11477 + val |= *((uint16 *) buf) << (8 * (off & 3));
11478 + } else if (len == 1) {
11479 + val &= ~(0xff << (8 * (off & 3)));
11480 + val |= *((uint8 *) buf) << (8 * (off & 3));
11481 + } else {
11482 + ret = -1;
11483 + goto done;
11484 + }
11485 +
11486 + PCI_MSG(("%s: 0x%x => 0x%p\n", __FUNCTION__, val, reg));
11487 +
11488 + W_REG(osh, reg, val);
11489 +
11490 +done:
11491 + if (reg && addr)
11492 + REG_UNMAP(reg);
11493 +
11494 + return ret;
11495 +}
11496 +
11497 +/*
11498 + * Must access emulated PCI configuration at these locations even when
11499 + * the real PCI config space exists and is accessible.
11500 + *
11501 + * PCI_CFG_VID (0x00)
11502 + * PCI_CFG_DID (0x02)
11503 + * PCI_CFG_PROGIF (0x09)
11504 + * PCI_CFG_SUBCL (0x0a)
11505 + * PCI_CFG_BASECL (0x0b)
11506 + * PCI_CFG_HDR (0x0e)
11507 + * PCI_CFG_INT (0x3c)
11508 + * PCI_CFG_PIN (0x3d)
11509 + */
11510 +#define FORCE_EMUCFG(off, len) \
11511 + ((off == PCI_CFG_VID) || (off == PCI_CFG_DID) || \
11512 + (off == PCI_CFG_PROGIF) || \
11513 + (off == PCI_CFG_SUBCL) || (off == PCI_CFG_BASECL) || \
11514 + (off == PCI_CFG_HDR) || \
11515 + (off == PCI_CFG_INT) || (off == PCI_CFG_PIN))
11516 +
11517 +/* Sync the emulation registers and the real PCI config registers. */
11518 +static void
11519 +sb_pcid_read_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11520 + uint off, uint len)
11521 +{
11522 + osl_t *osh;
11523 + uint oldidx;
11524 +
11525 + ASSERT(cfg);
11526 + ASSERT(cfg->emu);
11527 + ASSERT(cfg->pci);
11528 +
11529 + /* decide if real PCI config register access is necessary */
11530 + if (FORCE_EMUCFG(off, len))
11531 + return;
11532 +
11533 + osh = sb_osh(sbh);
11534 +
11535 + /* access to the real pci config space only when the core is up */
11536 + oldidx = sb_coreidx(sbh);
11537 + sb_setcoreidx(sbh, coreidx);
11538 + if (sb_iscoreup(sbh)) {
11539 + if (len == 4)
11540 + *(uint32 *)((ulong)cfg->emu + off) =
11541 + htol32(R_REG(osh, (uint32 *)((ulong)cfg->pci + off)));
11542 + else if (len == 2)
11543 + *(uint16 *)((ulong)cfg->emu + off) =
11544 + htol16(R_REG(osh, (uint16 *)((ulong)cfg->pci + off)));
11545 + else if (len == 1)
11546 + *(uint8 *)((ulong)cfg->emu + off) =
11547 + R_REG(osh, (uint8 *)((ulong)cfg->pci + off));
11548 + }
11549 + sb_setcoreidx(sbh, oldidx);
11550 +}
11551 +
11552 +static void
11553 +sb_pcid_write_config(sb_t *sbh, uint coreidx, sb_pci_cfg_t *cfg,
11554 + uint off, uint len)
11555 +{
11556 + osl_t *osh;
11557 + uint oldidx;
11558 +
11559 + ASSERT(cfg);
11560 + ASSERT(cfg->emu);
11561 + ASSERT(cfg->pci);
11562 +
11563 + osh = sb_osh(sbh);
11564 +
11565 + /* decide if real PCI config register access is necessary */
11566 + if (FORCE_EMUCFG(off, len))
11567 + return;
11568 +
11569 + /* access to the real pci config space only when the core is up */
11570 + oldidx = sb_coreidx(sbh);
11571 + sb_setcoreidx(sbh, coreidx);
11572 + if (sb_iscoreup(sbh)) {
11573 + if (len == 4)
11574 + W_REG(osh, (uint32 *)((ulong)cfg->pci + off),
11575 + ltoh32(*(uint32 *)((ulong)cfg->emu + off)));
11576 + else if (len == 2)
11577 + W_REG(osh, (uint16 *)((ulong)cfg->pci + off),
11578 + ltoh16(*(uint16 *)((ulong)cfg->emu + off)));
11579 + else if (len == 1)
11580 + W_REG(osh, (uint8 *)((ulong)cfg->pci + off),
11581 + *(uint8 *)((ulong)cfg->emu + off));
11582 + }
11583 + sb_setcoreidx(sbh, oldidx);
11584 +}
11585 +
11586 +/*
11587 + * Functions for accessing translated SB configuration space
11588 + */
11589 +static int
11590 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11591 +{
11592 + pci_config_regs *cfg;
11593 +
11594 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11595 + return -1;
11596 + cfg = sb_pci_cfg[dev][func].emu;
11597 +
11598 + ASSERT(ISALIGNED(off, len));
11599 + ASSERT(ISALIGNED((uintptr)buf, len));
11600 +
11601 + /* use special config space if the device does not exist */
11602 + if (!cfg)
11603 + cfg = &sb_pci_null;
11604 + /* sync emulation with real PCI config if necessary */
11605 + else if (sb_pci_cfg[dev][func].pci)
11606 + sb_pcid_read_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11607 +
11608 + if (len == 4)
11609 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
11610 + else if (len == 2)
11611 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
11612 + else if (len == 1)
11613 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
11614 + else
11615 + return -1;
11616 +
11617 + return 0;
11618 +}
11619 +
11620 +static int
11621 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11622 +{
11623 + uint coreidx;
11624 + void *regs;
11625 + pci_config_regs *cfg;
11626 + osl_t *osh;
11627 + sb_bar_cfg_t *bar;
11628 +
11629 + if (dev >= SB_MAXCORES || func >= MAXFUNCS || (off + len) > sizeof(pci_config_regs))
11630 + return -1;
11631 + cfg = sb_pci_cfg[dev][func].emu;
11632 + if (!cfg)
11633 + return -1;
11634 +
11635 + ASSERT(ISALIGNED(off, len));
11636 + ASSERT(ISALIGNED((uintptr)buf, len));
11637 +
11638 + osh = sb_osh(sbh);
11639 +
11640 + /* Emulate BAR sizing */
11641 + if (off >= OFFSETOF(pci_config_regs, base[0]) &&
11642 + off <= OFFSETOF(pci_config_regs, base[3]) &&
11643 + len == 4 && *((uint32 *) buf) == ~0) {
11644 + coreidx = sb_coreidx(sbh);
11645 + if ((regs = sb_setcoreidx(sbh, dev))) {
11646 + bar = sb_pci_cfg[dev][func].bar;
11647 + /* Highest numbered address match register */
11648 + if (off == OFFSETOF(pci_config_regs, base[0]))
11649 + cfg->base[0] = ~(bar->size0 - 1);
11650 + else if (off == OFFSETOF(pci_config_regs, base[1]) && bar->n >= 1)
11651 + cfg->base[1] = ~(bar->size1 - 1);
11652 + else if (off == OFFSETOF(pci_config_regs, base[2]) && bar->n >= 2)
11653 + cfg->base[2] = ~(bar->size2 - 1);
11654 + else if (off == OFFSETOF(pci_config_regs, base[3]) && bar->n >= 3)
11655 + cfg->base[3] = ~(bar->size3 - 1);
11656 + }
11657 + sb_setcoreidx(sbh, coreidx);
11658 + }
11659 + else if (len == 4)
11660 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
11661 + else if (len == 2)
11662 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
11663 + else if (len == 1)
11664 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
11665 + else
11666 + return -1;
11667 +
11668 + /* sync emulation with real PCI config if necessary */
11669 + if (sb_pci_cfg[dev][func].pci)
11670 + sb_pcid_write_config(sbh, dev, &sb_pci_cfg[dev][func], off, len);
11671 +
11672 + return 0;
11673 +}
11674 +
11675 +int
11676 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11677 +{
11678 + if (bus == 0)
11679 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
11680 + else
11681 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
11682 +}
11683 +
11684 +int
11685 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
11686 +{
11687 + if (bus == 0)
11688 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
11689 + else
11690 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
11691 +}
11692 +
11693 +void
11694 +sbpci_ban(uint16 core)
11695 +{
11696 + if (pci_banned < ARRAYSIZE(pci_ban))
11697 + pci_ban[pci_banned++] = core;
11698 +}
11699 +
11700 +/*
11701 + * Initiliaze PCI core. Return 0 after a successful initialization.
11702 + * Otherwise return -1 to indicate there is no PCI core and return 1
11703 + * to indicate PCI core is disabled.
11704 + */
11705 +int __init
11706 +sbpci_init_pci(sb_t *sbh)
11707 +{
11708 + uint chip, chiprev, chippkg, host;
11709 + uint32 boardflags;
11710 + sbpciregs_t *pci;
11711 + sbconfig_t *sb;
11712 + uint32 val;
11713 + int ret = 0;
11714 + char *hbslot;
11715 + osl_t *osh;
11716 +
11717 + chip = sb_chip(sbh);
11718 + chiprev = sb_chiprev(sbh);
11719 + chippkg = sb_chippkg(sbh);
11720 +
11721 + osh = sb_osh(sbh);
11722 +
11723 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
11724 + printk("PCI: no core\n");
11725 + pci_disabled = TRUE;
11726 + return -1;
11727 + }
11728 +
11729 + if ((chip == 0x4310) && (chiprev == 0))
11730 + pci_disabled = TRUE;
11731 +
11732 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
11733 +
11734 + boardflags = (uint32) getintvar(NULL, "boardflags");
11735 +
11736 + /*
11737 + * The 200-pin BCM4712 package does not bond out PCI. Even when
11738 + * PCI is bonded out, some boards may leave the pins
11739 + * floating.
11740 + */
11741 + if (((chip == BCM4712_CHIP_ID) &&
11742 + ((chippkg == BCM4712SMALL_PKG_ID) ||
11743 + (chippkg == BCM4712MID_PKG_ID))) ||
11744 + (boardflags & BFL_NOPCI))
11745 + pci_disabled = TRUE;
11746 +
11747 + /* Enable the core */
11748 + sb_core_reset(sbh, 0, 0);
11749 +
11750 + /*
11751 + * If the PCI core should not be touched (disabled, not bonded
11752 + * out, or pins floating), do not even attempt to access core
11753 + * registers. Otherwise, try to determine if it is in host
11754 + * mode.
11755 + */
11756 + if (pci_disabled)
11757 + host = 0;
11758 + else
11759 + host = !BUSPROBE(val, &pci->control);
11760 +
11761 + if (!host) {
11762 + ret = 1;
11763 +
11764 + /* Disable PCI interrupts in client mode */
11765 + W_REG(osh, &sb->sbintvec, 0);
11766 +
11767 + /* Disable the PCI bridge in client mode */
11768 + sbpci_ban(SB_PCI);
11769 + sb_core_disable(sbh, 0);
11770 +
11771 + printk("PCI: Disabled\n");
11772 + } else {
11773 + printk("PCI: Initializing host\n");
11774 +
11775 + /* Disable PCI SBReqeustTimeout for BCM4785 */
11776 + if (chip == BCM4785_CHIP_ID) {
11777 + AND_REG(osh, &sb->sbimconfiglow, ~0x00000070);
11778 + sb_commit(sbh);
11779 + }
11780 +
11781 + /* Reset the external PCI bus and enable the clock */
11782 + W_REG(osh, &pci->control, 0x5); /* enable the tristate drivers */
11783 + W_REG(osh, &pci->control, 0xd); /* enable the PCI clock */
11784 + OSL_DELAY(150); /* delay > 100 us */
11785 + W_REG(osh, &pci->control, 0xf); /* deassert PCI reset */
11786 + /* Use internal arbiter and park REQ/GRNT at external master 0 */
11787 + W_REG(osh, &pci->arbcontrol, PCI_INT_ARB);
11788 + OSL_DELAY(1); /* delay 1 us */
11789 + if (sb_corerev(sbh) >= 8) {
11790 + val = getintvar(NULL, "parkid");
11791 + ASSERT(val <= PCI_PARKID_LAST);
11792 + OR_REG(osh, &pci->arbcontrol, val << PCI_PARKID_SHIFT);
11793 + OSL_DELAY(1);
11794 + }
11795 +
11796 + /* Enable CardBusMode */
11797 + cardbus = getintvar(NULL, "cardbus") == 1;
11798 + if (cardbus) {
11799 + printk("PCI: Enabling CardBus\n");
11800 + /* GPIO 1 resets the CardBus device on bcm94710ap */
11801 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
11802 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
11803 + W_REG(osh, &pci->sprom[0], R_REG(osh, &pci->sprom[0]) | 0x400);
11804 + }
11805 +
11806 + /* 64 MB I/O access window */
11807 + W_REG(osh, &pci->sbtopci0, SBTOPCI_IO);
11808 + /* 64 MB configuration access window */
11809 + W_REG(osh, &pci->sbtopci1, SBTOPCI_CFG0);
11810 + /* 1 GB memory access window */
11811 + W_REG(osh, &pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
11812 +
11813 + /* Host bridge slot # nvram overwrite */
11814 + if ((hbslot = nvram_get("pcihbslot"))) {
11815 + pci_hbslot = bcm_strtoul(hbslot, NULL, 0);
11816 + ASSERT(pci_hbslot < PCI_MAX_DEVICES);
11817 + }
11818 +
11819 + /* Enable PCI bridge BAR0 prefetch and burst */
11820 + val = 6;
11821 + sbpci_write_config(sbh, 1, pci_hbslot, 0, PCI_CFG_CMD, &val, sizeof(val));
11822 +
11823 + /* Enable PCI interrupts */
11824 + W_REG(osh, &pci->intmask, PCI_INTA);
11825 + }
11826 +
11827 + return ret;
11828 +}
11829 +
11830 +/*
11831 + * Get the PCI region address and size information.
11832 + */
11833 +static void __init
11834 +sbpci_init_regions(sb_t *sbh, uint func, pci_config_regs *cfg, sb_bar_cfg_t *bar)
11835 +{
11836 + osl_t *osh;
11837 + uint16 coreid;
11838 + void *regs;
11839 + sbconfig_t *sb;
11840 + uint32 base;
11841 +
11842 + osh = sb_osh(sbh);
11843 + coreid = sb_coreid(sbh);
11844 + regs = sb_coreregs(sbh);
11845 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11846 +
11847 + switch (coreid) {
11848 + case SB_USB20H:
11849 + base = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11850 +
11851 + cfg->base[0] = func == 0 ? base : base + 0x800; /* OHCI/EHCI */
11852 + cfg->base[1] = 0;
11853 + cfg->base[2] = 0;
11854 + cfg->base[3] = 0;
11855 + cfg->base[4] = 0;
11856 + cfg->base[5] = 0;
11857 + bar->n = 1;
11858 + bar->size0 = func == 0 ? 0x200 : 0x100; /* OHCI/EHCI */
11859 + bar->size1 = 0;
11860 + bar->size2 = 0;
11861 + bar->size3 = 0;
11862 + break;
11863 + default:
11864 + cfg->base[0] = htol32(sb_base(R_REG(osh, &sb->sbadmatch0)));
11865 + cfg->base[1] = htol32(sb_base(R_REG(osh, &sb->sbadmatch1)));
11866 + cfg->base[2] = htol32(sb_base(R_REG(osh, &sb->sbadmatch2)));
11867 + cfg->base[3] = htol32(sb_base(R_REG(osh, &sb->sbadmatch3)));
11868 + cfg->base[4] = 0;
11869 + cfg->base[5] = 0;
11870 + bar->n = (R_REG(osh, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
11871 + bar->size0 = sb_size(R_REG(osh, &sb->sbadmatch0));
11872 + bar->size1 = sb_size(R_REG(osh, &sb->sbadmatch1));
11873 + bar->size2 = sb_size(R_REG(osh, &sb->sbadmatch2));
11874 + bar->size3 = sb_size(R_REG(osh, &sb->sbadmatch3));
11875 + break;
11876 + }
11877 +}
11878 +
11879 +/*
11880 + * Construct PCI config spaces for SB cores so that they
11881 + * can be accessed as if they were PCI devices.
11882 + */
11883 +static void __init
11884 +sbpci_init_cores(sb_t *sbh)
11885 +{
11886 + uint chiprev, coreidx, i;
11887 + sbconfig_t *sb;
11888 + pci_config_regs *cfg, *pci;
11889 + sb_bar_cfg_t *bar;
11890 + void *regs;
11891 + osl_t *osh;
11892 + uint16 vendor, device;
11893 + uint16 coreid;
11894 + uint8 class, subclass, progif;
11895 + uint dev;
11896 + uint8 header;
11897 + uint func;
11898 +
11899 + chiprev = sb_chiprev(sbh);
11900 + coreidx = sb_coreidx(sbh);
11901 +
11902 + osh = sb_osh(sbh);
11903 +
11904 + /* Scan the SB bus */
11905 + bzero(sb_config_regs, sizeof(sb_config_regs));
11906 + bzero(sb_bar_cfg, sizeof(sb_bar_cfg));
11907 + bzero(sb_pci_cfg, sizeof(sb_pci_cfg));
11908 + memset(&sb_pci_null, -1, sizeof(sb_pci_null));
11909 + cfg = sb_config_regs;
11910 + bar = sb_bar_cfg;
11911 + for (dev = 0; dev < SB_MAXCORES; dev ++) {
11912 + /* Check if the core exists */
11913 + if (!(regs = sb_setcoreidx(sbh, dev)))
11914 + continue;
11915 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11916 +
11917 + /* Check if this core is banned */
11918 + coreid = sb_coreid(sbh);
11919 + for (i = 0; i < pci_banned; i++)
11920 + if (coreid == pci_ban[i])
11921 + break;
11922 + if (i < pci_banned)
11923 + continue;
11924 +
11925 + for (func = 0; func < MAXFUNCS; ++func) {
11926 + /* Make sure we won't go beyond the limit */
11927 + if (cfg >= &sb_config_regs[SB_MAXCORES]) {
11928 + printk("PCI: too many emulated devices\n");
11929 + goto done;
11930 + }
11931 +
11932 + /* Convert core id to pci id */
11933 + if (sb_corepciid(sbh, func, &vendor, &device, &class, &subclass,
11934 + &progif, &header))
11935 + continue;
11936 +
11937 + /*
11938 + * Differentiate real PCI config from emulated.
11939 + * non zero 'pci' indicate there is a real PCI config space
11940 + * for this device.
11941 + */
11942 + switch (device) {
11943 + case BCM47XX_GIGETH_ID:
11944 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11945 + break;
11946 + case BCM47XX_SATAXOR_ID:
11947 + pci = (pci_config_regs *)((uint32)regs + 0x400);
11948 + break;
11949 + case BCM47XX_ATA100_ID:
11950 + pci = (pci_config_regs *)((uint32)regs + 0x800);
11951 + break;
11952 + default:
11953 + pci = NULL;
11954 + break;
11955 + }
11956 + /* Supported translations */
11957 + cfg->vendor = htol16(vendor);
11958 + cfg->device = htol16(device);
11959 + cfg->rev_id = chiprev;
11960 + cfg->prog_if = progif;
11961 + cfg->sub_class = subclass;
11962 + cfg->base_class = class;
11963 + cfg->header_type = header;
11964 + sbpci_init_regions(sbh, func, cfg, bar);
11965 + /* Save core interrupt flag */
11966 + cfg->int_pin = R_REG(osh, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
11967 + /* Save core interrupt assignment */
11968 + cfg->int_line = sb_irq(sbh);
11969 + /* Indicate there is no SROM */
11970 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
11971 +
11972 + /* Point to the PCI config spaces */
11973 + sb_pci_cfg[dev][func].emu = cfg;
11974 + sb_pci_cfg[dev][func].pci = pci;
11975 + sb_pci_cfg[dev][func].bar = bar;
11976 + cfg ++;
11977 + bar ++;
11978 + }
11979 + }
11980 +
11981 +done:
11982 + sb_setcoreidx(sbh, coreidx);
11983 +}
11984 +
11985 +/*
11986 + * Initialize PCI core and construct PCI config spaces for SB cores.
11987 + * Must propagate sbpci_init_pci() return value to the caller to let
11988 + * them know the PCI core initialization status.
11989 + */
11990 +int __init
11991 +sbpci_init(sb_t *sbh)
11992 +{
11993 + int status = sbpci_init_pci(sbh);
11994 + sbpci_init_cores(sbh);
11995 + return status;
11996 +}
11997 +
11998 diff -urN linux.old/arch/mips/bcm947xx/sbutils.c linux.dev/arch/mips/bcm947xx/sbutils.c
11999 --- linux.old/arch/mips/bcm947xx/sbutils.c 1970-01-01 01:00:00.000000000 +0100
12000 +++ linux.dev/arch/mips/bcm947xx/sbutils.c 2006-05-02 04:33:16.000000000 +0200
12001 @@ -0,0 +1,3081 @@
12002 +/*
12003 + * Misc utility routines for accessing chip-specific features
12004 + * of the SiliconBackplane-based Broadcom chips.
12005 + *
12006 + * Copyright 2006, Broadcom Corporation
12007 + * All Rights Reserved.
12008 + *
12009 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12010 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12011 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12012 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12013 + * $Id: sbutils.c,v 1.10 2006/04/08 07:12:42 honor Exp $
12014 + */
12015 +
12016 +#include <typedefs.h>
12017 +#include <bcmdefs.h>
12018 +#include <osl.h>
12019 +#include <bcmutils.h>
12020 +#include <sbutils.h>
12021 +#include <bcmdevs.h>
12022 +#include <sbconfig.h>
12023 +#include <sbchipc.h>
12024 +#include <sbpci.h>
12025 +#include <sbpcie.h>
12026 +#include <pcicfg.h>
12027 +#include <sbpcmcia.h>
12028 +#include <sbextif.h>
12029 +#include <sbsocram.h>
12030 +#include <bcmsrom.h>
12031 +#ifdef __mips__
12032 +#include <mipsinc.h>
12033 +#endif /* __mips__ */
12034 +
12035 +/* debug/trace */
12036 +#define SB_ERROR(args)
12037 +
12038 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
12039 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
12040 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
12041 +
12042 +/* misc sb info needed by some of the routines */
12043 +typedef struct sb_info {
12044 +
12045 + struct sb_pub sb; /* back plane public state (must be first field) */
12046 +
12047 + void *osh; /* osl os handle */
12048 + void *sdh; /* bcmsdh handle */
12049 +
12050 + void *curmap; /* current regs va */
12051 + void *regs[SB_MAXCORES]; /* other regs va */
12052 +
12053 + uint curidx; /* current core index */
12054 + uint dev_coreid; /* the core provides driver functions */
12055 +
12056 + bool memseg; /* flag to toggle MEM_SEG register */
12057 +
12058 + uint gpioidx; /* gpio control core index */
12059 + uint gpioid; /* gpio control coretype */
12060 +
12061 + uint numcores; /* # discovered cores */
12062 + uint coreid[SB_MAXCORES]; /* id of each core */
12063 +
12064 + void *intr_arg; /* interrupt callback function arg */
12065 + sb_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
12066 + sb_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
12067 + sb_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
12068 +
12069 +} sb_info_t;
12070 +
12071 +/* local prototypes */
12072 +static sb_info_t * sb_doattach(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12073 + uint bustype, void *sdh, char **vars, uint *varsz);
12074 +static void sb_scan(sb_info_t *si);
12075 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
12076 +static uint _sb_coreidx(sb_info_t *si);
12077 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
12078 +static uint sb_pcidev2chip(uint pcidev);
12079 +static uint sb_chip2numcores(uint chip);
12080 +static bool sb_ispcie(sb_info_t *si);
12081 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
12082 +static int sb_pci_fixcfg(sb_info_t *si);
12083 +
12084 +/* routines to access mdio slave device registers */
12085 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
12086 +static void sb_war30841(sb_info_t *si);
12087 +
12088 +/* delay needed between the mdio control/ mdiodata register data access */
12089 +#define PR28829_DELAY() OSL_DELAY(10)
12090 +
12091 +/* size that can take bitfielddump */
12092 +#define BITFIELD_DUMP_SIZE 32
12093 +
12094 +/* global variable to indicate reservation/release of gpio's */
12095 +static uint32 sb_gpioreservation = 0;
12096 +
12097 +#define SB_INFO(sbh) (sb_info_t*)sbh
12098 +#define SET_SBREG(si, r, mask, val) \
12099 + W_SBREG((si), (r), ((R_SBREG((si), (r)) & ~(mask)) | (val)))
12100 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && \
12101 + ISALIGNED((x), SB_CORE_SIZE))
12102 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
12103 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
12104 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
12105 +#define BADIDX (SB_MAXCORES+1)
12106 +#define NOREV -1 /* Invalid rev */
12107 +
12108 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
12109 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
12110 +
12111 +/* sonicsrev */
12112 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
12113 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
12114 +
12115 +#define R_SBREG(si, sbr) sb_read_sbreg((si), (sbr))
12116 +#define W_SBREG(si, sbr, v) sb_write_sbreg((si), (sbr), (v))
12117 +#define AND_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) & (v)))
12118 +#define OR_SBREG(si, sbr, v) W_SBREG((si), (sbr), (R_SBREG((si), (sbr)) | (v)))
12119 +
12120 +/*
12121 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
12122 + * after core switching to avoid invalid register accesss inside ISR.
12123 + */
12124 +#define INTR_OFF(si, intr_val) \
12125 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12126 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
12127 +#define INTR_RESTORE(si, intr_val) \
12128 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
12129 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
12130 +
12131 +/* dynamic clock control defines */
12132 +#define LPOMINFREQ 25000 /* low power oscillator min */
12133 +#define LPOMAXFREQ 43000 /* low power oscillator max */
12134 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
12135 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
12136 +#define PCIMINFREQ 25000000 /* 25 MHz */
12137 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
12138 +
12139 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
12140 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
12141 +
12142 +/* different register spaces to access thr'u pcie indirect access */
12143 +#define PCIE_CONFIGREGS 1 /* Access to config space */
12144 +#define PCIE_PCIEREGS 2 /* Access to pcie registers */
12145 +
12146 +/* GPIO Based LED powersave defines */
12147 +#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
12148 +#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
12149 +
12150 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
12151 +
12152 +static uint32
12153 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
12154 +{
12155 + uint8 tmp;
12156 + uint32 val, intr_val = 0;
12157 +
12158 +
12159 + /*
12160 + * compact flash only has 11 bits address, while we needs 12 bits address.
12161 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12162 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12163 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12164 + */
12165 + if (si->memseg) {
12166 + INTR_OFF(si, intr_val);
12167 + tmp = 1;
12168 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12169 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12170 + }
12171 +
12172 + val = R_REG(si->osh, sbr);
12173 +
12174 + if (si->memseg) {
12175 + tmp = 0;
12176 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12177 + INTR_RESTORE(si, intr_val);
12178 + }
12179 +
12180 + return (val);
12181 +}
12182 +
12183 +static void
12184 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
12185 +{
12186 + uint8 tmp;
12187 + volatile uint32 dummy;
12188 + uint32 intr_val = 0;
12189 +
12190 +
12191 + /*
12192 + * compact flash only has 11 bits address, while we needs 12 bits address.
12193 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
12194 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
12195 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
12196 + */
12197 + if (si->memseg) {
12198 + INTR_OFF(si, intr_val);
12199 + tmp = 1;
12200 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12201 + sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
12202 + }
12203 +
12204 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12205 +#ifdef IL_BIGENDIAN
12206 + dummy = R_REG(si->osh, sbr);
12207 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12208 + dummy = R_REG(si->osh, sbr);
12209 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12210 +#else
12211 + dummy = R_REG(si->osh, sbr);
12212 + W_REG(si->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
12213 + dummy = R_REG(si->osh, sbr);
12214 + W_REG(si->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
12215 +#endif /* IL_BIGENDIAN */
12216 + } else
12217 + W_REG(si->osh, sbr, v);
12218 +
12219 + if (si->memseg) {
12220 + tmp = 0;
12221 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
12222 + INTR_RESTORE(si, intr_val);
12223 + }
12224 +}
12225 +
12226 +/*
12227 + * Allocate a sb handle.
12228 + * devid - pci device id (used to determine chip#)
12229 + * osh - opaque OS handle
12230 + * regs - virtual address of initial core registers
12231 + * bustype - pci/pcmcia/sb/sdio/etc
12232 + * vars - pointer to a pointer area for "environment" variables
12233 + * varsz - pointer to int to return the size of the vars
12234 + */
12235 +sb_t *
12236 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
12237 + uint bustype, void *sdh, char **vars, uint *varsz)
12238 +{
12239 + sb_info_t *si;
12240 +
12241 + /* alloc sb_info_t */
12242 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
12243 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
12244 + return (NULL);
12245 + }
12246 +
12247 + if (sb_doattach(si, devid, osh, regs, bustype, sdh, vars, (uint*)varsz) == NULL) {
12248 + MFREE(osh, si, sizeof(sb_info_t));
12249 + return (NULL);
12250 + }
12251 +
12252 + return (sb_t *)si;
12253 +}
12254 +
12255 +/* Using sb_kattach depends on SB_BUS support, either implicit */
12256 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
12257 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12258 +
12259 +/* global kernel resource */
12260 +static sb_info_t ksi;
12261 +static bool ksi_attached = FALSE;
12262 +
12263 +/* generic kernel variant of sb_attach() */
12264 +sb_t *
12265 +BCMINITFN(sb_kattach)(void)
12266 +{
12267 + osl_t *osh = NULL;
12268 + uint32 *regs;
12269 +
12270 + if (!ksi_attached) {
12271 + uint32 cid;
12272 +
12273 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
12274 + cid = R_REG(osh, (uint32 *)regs);
12275 + if (((cid & CID_ID_MASK) == BCM4712_CHIP_ID) &&
12276 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
12277 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
12278 + uint32 *scc, val;
12279 +
12280 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
12281 + val = R_REG(osh, scc);
12282 + SB_ERROR((" initial scc = 0x%x\n", val));
12283 + val |= SCC_SS_XTAL;
12284 + W_REG(osh, scc, val);
12285 + }
12286 +
12287 + if (sb_doattach(&ksi, BCM4710_DEVICE_ID, osh, (void*)regs,
12288 + SB_BUS, NULL, NULL, NULL) == NULL) {
12289 + return NULL;
12290 + }
12291 + else
12292 + ksi_attached = TRUE;
12293 + }
12294 +
12295 + return (sb_t *)&ksi;
12296 +}
12297 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12298 +
12299 +static sb_info_t *
12300 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
12301 + uint bustype, void *sdh, char **vars, uint *varsz)
12302 +{
12303 + uint origidx;
12304 + chipcregs_t *cc;
12305 + sbconfig_t *sb;
12306 + uint32 w;
12307 +
12308 + ASSERT(GOODREGS(regs));
12309 +
12310 + bzero((uchar*)si, sizeof(sb_info_t));
12311 +
12312 + si->sb.buscoreidx = si->gpioidx = BADIDX;
12313 +
12314 + si->curmap = regs;
12315 + si->sdh = sdh;
12316 + si->osh = osh;
12317 +
12318 + /* check to see if we are a sb core mimic'ing a pci core */
12319 + if (bustype == PCI_BUS) {
12320 + if (OSL_PCI_READ_CONFIG(si->osh, PCI_SPROM_CONTROL, sizeof(uint32)) == 0xffffffff) {
12321 + SB_ERROR(("%s: incoming bus is PCI but it's a lie, switching to SB "
12322 + "devid:0x%x\n", __FUNCTION__, devid));
12323 + bustype = SB_BUS;
12324 + }
12325 + }
12326 +
12327 + si->sb.bustype = bustype;
12328 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
12329 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
12330 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
12331 + return NULL;
12332 + }
12333 +
12334 + /* need to set memseg flag for CF card first before any sb registers access */
12335 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
12336 + si->memseg = TRUE;
12337 +
12338 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
12339 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
12340 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
12341 +
12342 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12343 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12344 + if (!GOODCOREADDR(w))
12345 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32), SB_ENUM_BASE);
12346 + }
12347 +
12348 + /* initialize current core index value */
12349 + si->curidx = _sb_coreidx(si);
12350 +
12351 + if (si->curidx == BADIDX) {
12352 + SB_ERROR(("sb_doattach: bad core index\n"));
12353 + return NULL;
12354 + }
12355 +
12356 + /* get sonics backplane revision */
12357 + sb = REGS2SB(si->curmap);
12358 + si->sb.sonicsrev = (R_SBREG(si, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
12359 +
12360 + /* keep and reuse the initial register mapping */
12361 + origidx = si->curidx;
12362 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12363 + si->regs[origidx] = regs;
12364 +
12365 + /* is core-0 a chipcommon core? */
12366 + si->numcores = 1;
12367 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
12368 + if (sb_coreid(&si->sb) != SB_CC)
12369 + cc = NULL;
12370 +
12371 + /* determine chip id and rev */
12372 + if (cc) {
12373 + /* chip common core found! */
12374 + si->sb.chip = R_REG(si->osh, &cc->chipid) & CID_ID_MASK;
12375 + si->sb.chiprev = (R_REG(si->osh, &cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
12376 + si->sb.chippkg = (R_REG(si->osh, &cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
12377 + } else {
12378 + /* no chip common core -- must convert device id to chip id */
12379 + if ((si->sb.chip = sb_pcidev2chip(devid)) == 0) {
12380 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
12381 + sb_setcoreidx(&si->sb, origidx);
12382 + return NULL;
12383 + }
12384 + }
12385 +
12386 + /* get chipcommon rev */
12387 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
12388 +
12389 + /* determine numcores */
12390 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
12391 + si->numcores = (R_REG(si->osh, &cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
12392 + else
12393 + si->numcores = sb_chip2numcores(si->sb.chip);
12394 +
12395 + /* return to original core */
12396 + sb_setcoreidx(&si->sb, origidx);
12397 +
12398 + /* sanity checks */
12399 + ASSERT(si->sb.chip);
12400 +
12401 + /* scan for cores */
12402 + sb_scan(si);
12403 +
12404 + /* fixup necessary chip/core configurations */
12405 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12406 + if (sb_pci_fixcfg(si)) {
12407 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
12408 + return NULL;
12409 + }
12410 + }
12411 +
12412 + /* srom_var_init() depends on sb_scan() info */
12413 + if (srom_var_init(si, si->sb.bustype, si->curmap, si->osh, vars, varsz)) {
12414 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
12415 + return (NULL);
12416 + }
12417 +
12418 + if (cc == NULL) {
12419 + /*
12420 + * The chip revision number is hardwired into all
12421 + * of the pci function config rev fields and is
12422 + * independent from the individual core revision numbers.
12423 + * For example, the "A0" silicon of each chip is chip rev 0.
12424 + * For PCMCIA we get it from the CIS instead.
12425 + */
12426 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12427 + ASSERT(vars);
12428 + si->sb.chiprev = getintvar(*vars, "chiprev");
12429 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
12430 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_REV, sizeof(uint32));
12431 + si->sb.chiprev = w & 0xff;
12432 + } else
12433 + si->sb.chiprev = 0;
12434 + }
12435 +
12436 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
12437 + w = getintvar(*vars, "regwindowsz");
12438 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
12439 + }
12440 +
12441 + /* gpio control core is required */
12442 + if (!GOODIDX(si->gpioidx)) {
12443 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
12444 + return NULL;
12445 + }
12446 +
12447 + /* get boardtype and boardrev */
12448 + switch (BUSTYPE(si->sb.bustype)) {
12449 + case PCI_BUS:
12450 + /* do a pci config read to get subsystem id and subvendor id */
12451 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_SVID, sizeof(uint32));
12452 + si->sb.boardvendor = w & 0xffff;
12453 + si->sb.boardtype = (w >> 16) & 0xffff;
12454 + break;
12455 +
12456 + case PCMCIA_BUS:
12457 + case SDIO_BUS:
12458 + si->sb.boardvendor = getintvar(*vars, "manfid");
12459 + si->sb.boardtype = getintvar(*vars, "prodid");
12460 + break;
12461 +
12462 + case SB_BUS:
12463 + case JTAG_BUS:
12464 + si->sb.boardvendor = VENDOR_BROADCOM;
12465 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
12466 + si->sb.boardtype = 0xffff;
12467 + break;
12468 + }
12469 +
12470 + if (si->sb.boardtype == 0) {
12471 + SB_ERROR(("sb_doattach: unknown board type\n"));
12472 + ASSERT(si->sb.boardtype);
12473 + }
12474 +
12475 + /* setup the GPIO based LED powersave register */
12476 + if (si->sb.ccrev >= 16) {
12477 + if ((vars == NULL) || ((w = getintvar(*vars, "leddc")) == 0))
12478 + w = DEFAULT_GPIOTIMERVAL;
12479 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
12480 + }
12481 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1)) {
12482 + /* set proper clk setup delays before forcing HT */
12483 + sb_clkctl_init((void *)si);
12484 + sb_corereg((void*)si, SB_CC_IDX, OFFSETOF(chipcregs_t, system_clk_ctl),
12485 + SYCC_HR, SYCC_HR);
12486 + }
12487 +
12488 +
12489 + return (si);
12490 +}
12491 +
12492 +uint
12493 +sb_coreid(sb_t *sbh)
12494 +{
12495 + sb_info_t *si;
12496 + sbconfig_t *sb;
12497 +
12498 + si = SB_INFO(sbh);
12499 + sb = REGS2SB(si->curmap);
12500 +
12501 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
12502 +}
12503 +
12504 +uint
12505 +sb_coreidx(sb_t *sbh)
12506 +{
12507 + sb_info_t *si;
12508 +
12509 + si = SB_INFO(sbh);
12510 + return (si->curidx);
12511 +}
12512 +
12513 +/* return current index of core */
12514 +static uint
12515 +_sb_coreidx(sb_info_t *si)
12516 +{
12517 + sbconfig_t *sb;
12518 + uint32 sbaddr = 0;
12519 +
12520 + ASSERT(si);
12521 +
12522 + switch (BUSTYPE(si->sb.bustype)) {
12523 + case SB_BUS:
12524 + sb = REGS2SB(si->curmap);
12525 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
12526 + break;
12527 +
12528 + case PCI_BUS:
12529 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32));
12530 + break;
12531 +
12532 + case PCMCIA_BUS: {
12533 + uint8 tmp = 0;
12534 +
12535 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
12536 + sbaddr = (uint)tmp << 12;
12537 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
12538 + sbaddr |= (uint)tmp << 16;
12539 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
12540 + sbaddr |= (uint)tmp << 24;
12541 + break;
12542 + }
12543 +
12544 +#ifdef BCMJTAG
12545 + case JTAG_BUS:
12546 + sbaddr = (uint32)si->curmap;
12547 + break;
12548 +#endif /* BCMJTAG */
12549 +
12550 + default:
12551 + ASSERT(0);
12552 + }
12553 +
12554 + if (!GOODCOREADDR(sbaddr))
12555 + return BADIDX;
12556 +
12557 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
12558 +}
12559 +
12560 +uint
12561 +sb_corevendor(sb_t *sbh)
12562 +{
12563 + sb_info_t *si;
12564 + sbconfig_t *sb;
12565 +
12566 + si = SB_INFO(sbh);
12567 + sb = REGS2SB(si->curmap);
12568 +
12569 + return ((R_SBREG(si, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
12570 +}
12571 +
12572 +uint
12573 +sb_corerev(sb_t *sbh)
12574 +{
12575 + sb_info_t *si;
12576 + sbconfig_t *sb;
12577 + uint sbidh;
12578 +
12579 + si = SB_INFO(sbh);
12580 + sb = REGS2SB(si->curmap);
12581 + sbidh = R_SBREG(si, &sb->sbidhigh);
12582 +
12583 + return (SBCOREREV(sbidh));
12584 +}
12585 +
12586 +void *
12587 +sb_osh(sb_t *sbh)
12588 +{
12589 + sb_info_t *si;
12590 +
12591 + si = SB_INFO(sbh);
12592 + return si->osh;
12593 +}
12594 +
12595 +void
12596 +sb_setosh(sb_t *sbh, osl_t *osh)
12597 +{
12598 + sb_info_t *si;
12599 +
12600 + si = SB_INFO(sbh);
12601 + if (si->osh != NULL) {
12602 + SB_ERROR(("osh is already set....\n"));
12603 + ASSERT(!si->osh);
12604 + }
12605 + si->osh = osh;
12606 +}
12607 +
12608 +/* set/clear sbtmstatelow core-specific flags */
12609 +uint32
12610 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
12611 +{
12612 + sb_info_t *si;
12613 + sbconfig_t *sb;
12614 + uint32 w;
12615 +
12616 + si = SB_INFO(sbh);
12617 + sb = REGS2SB(si->curmap);
12618 +
12619 + ASSERT((val & ~mask) == 0);
12620 +
12621 + /* mask and set */
12622 + if (mask || val) {
12623 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
12624 + W_SBREG(si, &sb->sbtmstatelow, w);
12625 + }
12626 +
12627 + /* return the new value */
12628 + return (R_SBREG(si, &sb->sbtmstatelow));
12629 +}
12630 +
12631 +/* set/clear sbtmstatehigh core-specific flags */
12632 +uint32
12633 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
12634 +{
12635 + sb_info_t *si;
12636 + sbconfig_t *sb;
12637 + uint32 w;
12638 +
12639 + si = SB_INFO(sbh);
12640 + sb = REGS2SB(si->curmap);
12641 +
12642 + ASSERT((val & ~mask) == 0);
12643 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
12644 +
12645 + /* mask and set */
12646 + if (mask || val) {
12647 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
12648 + W_SBREG(si, &sb->sbtmstatehigh, w);
12649 + }
12650 +
12651 + /* return the new value */
12652 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
12653 +}
12654 +
12655 +/* Run bist on current core. Caller needs to take care of core-specific bist hazards */
12656 +int
12657 +sb_corebist(sb_t *sbh)
12658 +{
12659 + uint32 sblo;
12660 + sb_info_t *si;
12661 + sbconfig_t *sb;
12662 + int result = 0;
12663 +
12664 + si = SB_INFO(sbh);
12665 + sb = REGS2SB(si->curmap);
12666 +
12667 + sblo = R_SBREG(si, &sb->sbtmstatelow);
12668 + W_SBREG(si, &sb->sbtmstatelow, (sblo | SBTML_FGC | SBTML_BE));
12669 +
12670 + SPINWAIT(((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTD) == 0), 100000);
12671 +
12672 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BISTF)
12673 + result = BCME_ERROR;
12674 +
12675 + W_SBREG(si, &sb->sbtmstatelow, sblo);
12676 +
12677 + return result;
12678 +}
12679 +
12680 +bool
12681 +sb_iscoreup(sb_t *sbh)
12682 +{
12683 + sb_info_t *si;
12684 + sbconfig_t *sb;
12685 +
12686 + si = SB_INFO(sbh);
12687 + sb = REGS2SB(si->curmap);
12688 +
12689 + return ((R_SBREG(si, &sb->sbtmstatelow) &
12690 + (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
12691 +}
12692 +
12693 +/*
12694 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
12695 + * switch back to the original core, and return the new value.
12696 + *
12697 + * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
12698 + *
12699 + * Also, when using pci/pcie, we can optimize away the core switching for pci registers
12700 + * and (on newer pci cores) chipcommon registers.
12701 + */
12702 +static uint
12703 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
12704 +{
12705 + uint origidx = 0;
12706 + uint32 *r = NULL;
12707 + uint w;
12708 + uint intr_val = 0;
12709 + bool fast = FALSE;
12710 +
12711 + ASSERT(GOODIDX(coreidx));
12712 + ASSERT(regoff < SB_CORE_SIZE);
12713 + ASSERT((val & ~mask) == 0);
12714 +
12715 +#ifdef notyet
12716 + if (si->sb.bustype == SB_BUS) {
12717 + /* If internal bus, we can always get at everything */
12718 + fast = TRUE;
12719 + r = (uint32 *)((uchar *)si->regs[coreidx] + regoff);
12720 + } else if (si->sb.bustype == PCI_BUS) {
12721 + /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
12722 +
12723 + if ((si->coreid[coreidx] == SB_CC) &&
12724 + ((si->sb.buscoretype == SB_PCIE) ||
12725 + (si->sb.buscorerev >= 13))) {
12726 + /* Chipc registers are mapped at 12KB */
12727 +
12728 + fast = TRUE;
12729 + r = (uint32 *)((char *)si->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
12730 + } else if (si->sb.buscoreidx == coreidx) {
12731 + /* pci registers are at either in the last 2KB of an 8KB window
12732 + * or, in pcie and pci rev 13 at 8KB
12733 + */
12734 + fast = TRUE;
12735 + if ((si->sb.buscoretype == SB_PCIE) ||
12736 + (si->sb.buscorerev >= 13))
12737 + r = (uint32 *)((char *)si->curmap +
12738 + PCI_16KB0_PCIREGS_OFFSET + regoff);
12739 + else
12740 + r = (uint32 *)((char *)si->curmap +
12741 + ((regoff >= SBCONFIGOFF) ?
12742 + PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
12743 + regoff);
12744 + }
12745 + }
12746 +#endif /* notyet */
12747 +
12748 + if (!fast) {
12749 + INTR_OFF(si, intr_val);
12750 +
12751 + /* save current core index */
12752 + origidx = sb_coreidx(&si->sb);
12753 +
12754 + /* switch core */
12755 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
12756 + }
12757 + ASSERT(r);
12758 +
12759 + /* mask and set */
12760 + if (mask || val) {
12761 + if (regoff >= SBCONFIGOFF) {
12762 + w = (R_SBREG(si, r) & ~mask) | val;
12763 + W_SBREG(si, r, w);
12764 + } else {
12765 + w = (R_REG(si->osh, r) & ~mask) | val;
12766 + W_REG(si->osh, r, w);
12767 + }
12768 + }
12769 +
12770 + /* readback */
12771 + if (regoff >= SBCONFIGOFF)
12772 + w = R_SBREG(si, r);
12773 + else
12774 + w = R_REG(si->osh, r);
12775 +
12776 + if (!fast) {
12777 + /* restore core index */
12778 + if (origidx != coreidx)
12779 + sb_setcoreidx(&si->sb, origidx);
12780 +
12781 + INTR_RESTORE(si, intr_val);
12782 + }
12783 +
12784 + return (w);
12785 +}
12786 +
12787 +#define DWORD_ALIGN(x) (x & ~(0x03))
12788 +#define BYTE_POS(x) (x & 0x3)
12789 +#define WORD_POS(x) (x & 0x1)
12790 +
12791 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
12792 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
12793 +
12794 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
12795 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
12796 +
12797 +#define read_pci_cfg_byte(a) \
12798 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
12799 +
12800 +#define read_pci_cfg_write(a) \
12801 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
12802 +
12803 +
12804 +/* return TRUE if requested capability exists in the PCI config space */
12805 +static bool
12806 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
12807 +{
12808 + uint8 cap_id;
12809 + uint8 cap_ptr;
12810 + uint32 bufsize;
12811 + uint8 byte_val;
12812 +
12813 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
12814 + return FALSE;
12815 +
12816 + /* check for Header type 0 */
12817 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
12818 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
12819 + return FALSE;
12820 +
12821 + /* check if the capability pointer field exists */
12822 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
12823 + if (!(byte_val & PCI_CAPPTR_PRESENT))
12824 + return FALSE;
12825 +
12826 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
12827 + /* check if the capability pointer is 0x00 */
12828 + if (cap_ptr == 0x00)
12829 + return FALSE;
12830 +
12831 +
12832 + /* loop thr'u the capability list and see if the pcie capabilty exists */
12833 +
12834 + cap_id = read_pci_cfg_byte(cap_ptr);
12835 +
12836 + while (cap_id != req_cap_id) {
12837 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
12838 + if (cap_ptr == 0x00) break;
12839 + cap_id = read_pci_cfg_byte(cap_ptr);
12840 + }
12841 + if (cap_id != req_cap_id) {
12842 + return FALSE;
12843 + }
12844 + /* found the caller requested capability */
12845 + if ((buf != NULL) && (buflen != NULL)) {
12846 + bufsize = *buflen;
12847 + if (!bufsize) goto end;
12848 + *buflen = 0;
12849 + /* copy the cpability data excluding cap ID and next ptr */
12850 + cap_ptr += 2;
12851 + if ((bufsize + cap_ptr) > SZPCR)
12852 + bufsize = SZPCR - cap_ptr;
12853 + *buflen = bufsize;
12854 + while (bufsize--) {
12855 + *buf = read_pci_cfg_byte(cap_ptr);
12856 + cap_ptr++;
12857 + buf++;
12858 + }
12859 + }
12860 +end:
12861 + return TRUE;
12862 +}
12863 +
12864 +/* return TRUE if PCIE capability exists the pci config space */
12865 +static inline bool
12866 +sb_ispcie(sb_info_t *si)
12867 +{
12868 + return (sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
12869 +}
12870 +
12871 +/* scan the sb enumerated space to identify all cores */
12872 +static void
12873 +BCMINITFN(sb_scan)(sb_info_t *si)
12874 +{
12875 + uint origidx;
12876 + uint i;
12877 + bool pci;
12878 + bool pcie;
12879 + uint pciidx;
12880 + uint pcieidx;
12881 + uint pcirev;
12882 + uint pcierev;
12883 +
12884 +
12885 + /* numcores should already be set */
12886 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
12887 +
12888 + /* save current core index */
12889 + origidx = sb_coreidx(&si->sb);
12890 +
12891 + si->sb.buscorerev = NOREV;
12892 + si->sb.buscoreidx = BADIDX;
12893 +
12894 + si->gpioidx = BADIDX;
12895 +
12896 + pci = pcie = FALSE;
12897 + pcirev = pcierev = NOREV;
12898 + pciidx = pcieidx = BADIDX;
12899 +
12900 + for (i = 0; i < si->numcores; i++) {
12901 + sb_setcoreidx(&si->sb, i);
12902 + si->coreid[i] = sb_coreid(&si->sb);
12903 +
12904 + if (si->coreid[i] == SB_PCI) {
12905 + pciidx = i;
12906 + pcirev = sb_corerev(&si->sb);
12907 + pci = TRUE;
12908 + } else if (si->coreid[i] == SB_PCIE) {
12909 + pcieidx = i;
12910 + pcierev = sb_corerev(&si->sb);
12911 + pcie = TRUE;
12912 + } else if (si->coreid[i] == SB_PCMCIA) {
12913 + si->sb.buscorerev = sb_corerev(&si->sb);
12914 + si->sb.buscoretype = si->coreid[i];
12915 + si->sb.buscoreidx = i;
12916 + }
12917 + }
12918 + if (pci && pcie) {
12919 + if (sb_ispcie(si))
12920 + pci = FALSE;
12921 + else
12922 + pcie = FALSE;
12923 + }
12924 + if (pci) {
12925 + si->sb.buscoretype = SB_PCI;
12926 + si->sb.buscorerev = pcirev;
12927 + si->sb.buscoreidx = pciidx;
12928 + } else if (pcie) {
12929 + si->sb.buscoretype = SB_PCIE;
12930 + si->sb.buscorerev = pcierev;
12931 + si->sb.buscoreidx = pcieidx;
12932 + }
12933 +
12934 + /*
12935 + * Find the gpio "controlling core" type and index.
12936 + * Precedence:
12937 + * - if there's a chip common core - use that
12938 + * - else if there's a pci core (rev >= 2) - use that
12939 + * - else there had better be an extif core (4710 only)
12940 + */
12941 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
12942 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
12943 + si->gpioid = SB_CC;
12944 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
12945 + si->gpioidx = si->sb.buscoreidx;
12946 + si->gpioid = SB_PCI;
12947 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
12948 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
12949 + si->gpioid = SB_EXTIF;
12950 + } else
12951 + ASSERT(si->gpioidx != BADIDX);
12952 +
12953 + /* return to original core index */
12954 + sb_setcoreidx(&si->sb, origidx);
12955 +}
12956 +
12957 +/* may be called with core in reset */
12958 +void
12959 +sb_detach(sb_t *sbh)
12960 +{
12961 + sb_info_t *si;
12962 + uint idx;
12963 +
12964 + si = SB_INFO(sbh);
12965 +
12966 + if (si == NULL)
12967 + return;
12968 +
12969 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
12970 + for (idx = 0; idx < SB_MAXCORES; idx++)
12971 + if (si->regs[idx]) {
12972 + REG_UNMAP(si->regs[idx]);
12973 + si->regs[idx] = NULL;
12974 + }
12975 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
12976 + if (si != &ksi)
12977 +#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SB_BUS) */
12978 + MFREE(si->osh, si, sizeof(sb_info_t));
12979 +
12980 +}
12981 +
12982 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
12983 +static uint
12984 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
12985 +{
12986 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
12987 + return (BCM4710_CHIP_ID);
12988 + if ((pcidev >= BCM4402_ENET_ID) && (pcidev <= BCM4402_V90_ID))
12989 + return (BCM4402_CHIP_ID);
12990 + if (pcidev == BCM4401_ENET_ID)
12991 + return (BCM4402_CHIP_ID);
12992 +
12993 + return (0);
12994 +}
12995 +
12996 +/* convert chip number to number of i/o cores */
12997 +static uint
12998 +BCMINITFN(sb_chip2numcores)(uint chip)
12999 +{
13000 + if (chip == BCM4710_CHIP_ID)
13001 + return (9);
13002 + if (chip == BCM4402_CHIP_ID)
13003 + return (3);
13004 + if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
13005 + return (6);
13006 + if (chip == BCM4704_CHIP_ID)
13007 + return (9);
13008 + if (chip == BCM5365_CHIP_ID)
13009 + return (7);
13010 +
13011 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
13012 + ASSERT(0);
13013 + return (1);
13014 +}
13015 +
13016 +/* return index of coreid or BADIDX if not found */
13017 +static uint
13018 +sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit)
13019 +{
13020 + uint found;
13021 + uint i;
13022 +
13023 + found = 0;
13024 +
13025 + for (i = 0; i < si->numcores; i++)
13026 + if (si->coreid[i] == coreid) {
13027 + if (found == coreunit)
13028 + return (i);
13029 + found++;
13030 + }
13031 +
13032 + return (BADIDX);
13033 +}
13034 +
13035 +/*
13036 + * this function changes logical "focus" to the indiciated core,
13037 + * must be called with interrupt off.
13038 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13039 + */
13040 +void*
13041 +sb_setcoreidx(sb_t *sbh, uint coreidx)
13042 +{
13043 + sb_info_t *si;
13044 + uint32 sbaddr;
13045 + uint8 tmp;
13046 +
13047 + si = SB_INFO(sbh);
13048 +
13049 + if (coreidx >= si->numcores)
13050 + return (NULL);
13051 +
13052 + /*
13053 + * If the user has provided an interrupt mask enabled function,
13054 + * then assert interrupts are disabled before switching the core.
13055 + */
13056 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
13057 +
13058 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
13059 +
13060 + switch (BUSTYPE(si->sb.bustype)) {
13061 + case SB_BUS:
13062 + /* map new one */
13063 + if (!si->regs[coreidx]) {
13064 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
13065 + ASSERT(GOODREGS(si->regs[coreidx]));
13066 + }
13067 + si->curmap = si->regs[coreidx];
13068 + break;
13069 +
13070 + case PCI_BUS:
13071 + /* point bar0 window */
13072 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
13073 + break;
13074 +
13075 + case PCMCIA_BUS:
13076 + tmp = (sbaddr >> 12) & 0x0f;
13077 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
13078 + tmp = (sbaddr >> 16) & 0xff;
13079 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
13080 + tmp = (sbaddr >> 24) & 0xff;
13081 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
13082 + break;
13083 +#ifdef BCMJTAG
13084 + case JTAG_BUS:
13085 + /* map new one */
13086 + if (!si->regs[coreidx]) {
13087 + si->regs[coreidx] = (void *)sbaddr;
13088 + ASSERT(GOODREGS(si->regs[coreidx]));
13089 + }
13090 + si->curmap = si->regs[coreidx];
13091 + break;
13092 +#endif /* BCMJTAG */
13093 + }
13094 +
13095 + si->curidx = coreidx;
13096 +
13097 + return (si->curmap);
13098 +}
13099 +
13100 +/*
13101 + * this function changes logical "focus" to the indiciated core,
13102 + * must be called with interrupt off.
13103 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
13104 + */
13105 +void*
13106 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
13107 +{
13108 + sb_info_t *si;
13109 + uint idx;
13110 +
13111 + si = SB_INFO(sbh);
13112 + idx = sb_findcoreidx(si, coreid, coreunit);
13113 + if (!GOODIDX(idx))
13114 + return (NULL);
13115 +
13116 + return (sb_setcoreidx(sbh, idx));
13117 +}
13118 +
13119 +/* return chip number */
13120 +uint
13121 +sb_chip(sb_t *sbh)
13122 +{
13123 + sb_info_t *si;
13124 +
13125 + si = SB_INFO(sbh);
13126 + return (si->sb.chip);
13127 +}
13128 +
13129 +/* return chip revision number */
13130 +uint
13131 +sb_chiprev(sb_t *sbh)
13132 +{
13133 + sb_info_t *si;
13134 +
13135 + si = SB_INFO(sbh);
13136 + return (si->sb.chiprev);
13137 +}
13138 +
13139 +/* return chip common revision number */
13140 +uint
13141 +sb_chipcrev(sb_t *sbh)
13142 +{
13143 + sb_info_t *si;
13144 +
13145 + si = SB_INFO(sbh);
13146 + return (si->sb.ccrev);
13147 +}
13148 +
13149 +/* return chip package option */
13150 +uint
13151 +sb_chippkg(sb_t *sbh)
13152 +{
13153 + sb_info_t *si;
13154 +
13155 + si = SB_INFO(sbh);
13156 + return (si->sb.chippkg);
13157 +}
13158 +
13159 +/* return PCI core rev. */
13160 +uint
13161 +sb_pcirev(sb_t *sbh)
13162 +{
13163 + sb_info_t *si;
13164 +
13165 + si = SB_INFO(sbh);
13166 + return (si->sb.buscorerev);
13167 +}
13168 +
13169 +bool
13170 +BCMINITFN(sb_war16165)(sb_t *sbh)
13171 +{
13172 + sb_info_t *si;
13173 +
13174 + si = SB_INFO(sbh);
13175 +
13176 + return (PCI(si) && (si->sb.buscorerev <= 10));
13177 +}
13178 +
13179 +static void
13180 +BCMINITFN(sb_war30841)(sb_info_t *si)
13181 +{
13182 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
13183 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
13184 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
13185 +}
13186 +
13187 +/* return PCMCIA core rev. */
13188 +uint
13189 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
13190 +{
13191 + sb_info_t *si;
13192 +
13193 + si = SB_INFO(sbh);
13194 + return (si->sb.buscorerev);
13195 +}
13196 +
13197 +/* return board vendor id */
13198 +uint
13199 +sb_boardvendor(sb_t *sbh)
13200 +{
13201 + sb_info_t *si;
13202 +
13203 + si = SB_INFO(sbh);
13204 + return (si->sb.boardvendor);
13205 +}
13206 +
13207 +/* return boardtype */
13208 +uint
13209 +sb_boardtype(sb_t *sbh)
13210 +{
13211 + sb_info_t *si;
13212 + char *var;
13213 +
13214 + si = SB_INFO(sbh);
13215 +
13216 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
13217 + /* boardtype format is a hex string */
13218 + si->sb.boardtype = getintvar(NULL, "boardtype");
13219 +
13220 + /* backward compatibility for older boardtype string format */
13221 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
13222 + if (!strcmp(var, "bcm94710dev"))
13223 + si->sb.boardtype = BCM94710D_BOARD;
13224 + else if (!strcmp(var, "bcm94710ap"))
13225 + si->sb.boardtype = BCM94710AP_BOARD;
13226 + else if (!strcmp(var, "bu4710"))
13227 + si->sb.boardtype = BU4710_BOARD;
13228 + else if (!strcmp(var, "bcm94702mn"))
13229 + si->sb.boardtype = BCM94702MN_BOARD;
13230 + else if (!strcmp(var, "bcm94710r1"))
13231 + si->sb.boardtype = BCM94710R1_BOARD;
13232 + else if (!strcmp(var, "bcm94710r4"))
13233 + si->sb.boardtype = BCM94710R4_BOARD;
13234 + else if (!strcmp(var, "bcm94702cpci"))
13235 + si->sb.boardtype = BCM94702CPCI_BOARD;
13236 + else if (!strcmp(var, "bcm95380_rr"))
13237 + si->sb.boardtype = BCM95380RR_BOARD;
13238 + }
13239 + }
13240 +
13241 + return (si->sb.boardtype);
13242 +}
13243 +
13244 +/* return bus type of sbh device */
13245 +uint
13246 +sb_bus(sb_t *sbh)
13247 +{
13248 + sb_info_t *si;
13249 +
13250 + si = SB_INFO(sbh);
13251 + return (si->sb.bustype);
13252 +}
13253 +
13254 +/* return bus core type */
13255 +uint
13256 +sb_buscoretype(sb_t *sbh)
13257 +{
13258 + sb_info_t *si;
13259 +
13260 + si = SB_INFO(sbh);
13261 +
13262 + return (si->sb.buscoretype);
13263 +}
13264 +
13265 +/* return bus core revision */
13266 +uint
13267 +sb_buscorerev(sb_t *sbh)
13268 +{
13269 + sb_info_t *si;
13270 + si = SB_INFO(sbh);
13271 +
13272 + return (si->sb.buscorerev);
13273 +}
13274 +
13275 +/* return list of found cores */
13276 +uint
13277 +sb_corelist(sb_t *sbh, uint coreid[])
13278 +{
13279 + sb_info_t *si;
13280 +
13281 + si = SB_INFO(sbh);
13282 +
13283 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof(uint)));
13284 + return (si->numcores);
13285 +}
13286 +
13287 +/* return current register mapping */
13288 +void *
13289 +sb_coreregs(sb_t *sbh)
13290 +{
13291 + sb_info_t *si;
13292 +
13293 + si = SB_INFO(sbh);
13294 + ASSERT(GOODREGS(si->curmap));
13295 +
13296 + return (si->curmap);
13297 +}
13298 +
13299 +
13300 +/* do buffered registers update */
13301 +void
13302 +sb_commit(sb_t *sbh)
13303 +{
13304 + sb_info_t *si;
13305 + uint origidx;
13306 + uint intr_val = 0;
13307 +
13308 + si = SB_INFO(sbh);
13309 +
13310 + origidx = si->curidx;
13311 + ASSERT(GOODIDX(origidx));
13312 +
13313 + INTR_OFF(si, intr_val);
13314 +
13315 + /* switch over to chipcommon core if there is one, else use pci */
13316 + if (si->sb.ccrev != NOREV) {
13317 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
13318 +
13319 + /* do the buffer registers update */
13320 + W_REG(si->osh, &ccregs->broadcastaddress, SB_COMMIT);
13321 + W_REG(si->osh, &ccregs->broadcastdata, 0x0);
13322 + } else if (PCI(si)) {
13323 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
13324 +
13325 + /* do the buffer registers update */
13326 + W_REG(si->osh, &pciregs->bcastaddr, SB_COMMIT);
13327 + W_REG(si->osh, &pciregs->bcastdata, 0x0);
13328 + } else
13329 + ASSERT(0);
13330 +
13331 + /* restore core index */
13332 + sb_setcoreidx(sbh, origidx);
13333 + INTR_RESTORE(si, intr_val);
13334 +}
13335 +
13336 +/* reset and re-enable a core
13337 + * inputs:
13338 + * bits - core specific bits that are set during and after reset sequence
13339 + * resetbits - core specific bits that are set only during reset sequence
13340 + */
13341 +void
13342 +sb_core_reset(sb_t *sbh, uint32 bits, uint32 resetbits)
13343 +{
13344 + sb_info_t *si;
13345 + sbconfig_t *sb;
13346 + volatile uint32 dummy;
13347 +
13348 + si = SB_INFO(sbh);
13349 + ASSERT(GOODREGS(si->curmap));
13350 + sb = REGS2SB(si->curmap);
13351 +
13352 + /*
13353 + * Must do the disable sequence first to work for arbitrary current core state.
13354 + */
13355 + sb_core_disable(sbh, (bits | resetbits));
13356 +
13357 + /*
13358 + * Now do the initialization sequence.
13359 + */
13360 +
13361 + /* set reset while enabling the clock and forcing them on throughout the core */
13362 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits | resetbits));
13363 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13364 + OSL_DELAY(1);
13365 +
13366 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
13367 + W_SBREG(si, &sb->sbtmstatehigh, 0);
13368 + }
13369 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
13370 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
13371 + }
13372 +
13373 + /* clear reset and allow it to propagate throughout the core */
13374 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
13375 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13376 + OSL_DELAY(1);
13377 +
13378 + /* leave clock enabled */
13379 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
13380 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13381 + OSL_DELAY(1);
13382 +}
13383 +
13384 +void
13385 +sb_core_tofixup(sb_t *sbh)
13386 +{
13387 + sb_info_t *si;
13388 + sbconfig_t *sb;
13389 +
13390 + si = SB_INFO(sbh);
13391 +
13392 + if ((BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) ||
13393 + (PCI(si) && (si->sb.buscorerev >= 5)))
13394 + return;
13395 +
13396 + ASSERT(GOODREGS(si->curmap));
13397 + sb = REGS2SB(si->curmap);
13398 +
13399 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
13400 + SET_SBREG(si, &sb->sbimconfiglow,
13401 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13402 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
13403 + } else {
13404 + if (sb_coreid(sbh) == SB_PCI) {
13405 + SET_SBREG(si, &sb->sbimconfiglow,
13406 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13407 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13408 + } else {
13409 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
13410 + }
13411 + }
13412 +
13413 + sb_commit(sbh);
13414 +}
13415 +
13416 +/*
13417 + * Set the initiator timeout for the "master core".
13418 + * The master core is defined to be the core in control
13419 + * of the chip and so it issues accesses to non-memory
13420 + * locations (Because of dma *any* core can access memeory).
13421 + *
13422 + * The routine uses the bus to decide who is the master:
13423 + * SB_BUS => mips
13424 + * JTAG_BUS => chipc
13425 + * PCI_BUS => pci or pcie
13426 + * PCMCIA_BUS => pcmcia
13427 + * SDIO_BUS => pcmcia
13428 + *
13429 + * This routine exists so callers can disable initiator
13430 + * timeouts so accesses to very slow devices like otp
13431 + * won't cause an abort. The routine allows arbitrary
13432 + * settings of the service and request timeouts, though.
13433 + *
13434 + * Returns the timeout state before changing it or -1
13435 + * on error.
13436 + */
13437 +
13438 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
13439 +
13440 +uint32
13441 +sb_set_initiator_to(sb_t *sbh, uint32 to)
13442 +{
13443 + sb_info_t *si;
13444 + uint origidx, idx;
13445 + uint intr_val = 0;
13446 + uint32 tmp, ret = 0xffffffff;
13447 + sbconfig_t *sb;
13448 +
13449 + si = SB_INFO(sbh);
13450 +
13451 + if ((to & ~TO_MASK) != 0)
13452 + return ret;
13453 +
13454 + /* Figure out the master core */
13455 + idx = BADIDX;
13456 + switch (BUSTYPE(si->sb.bustype)) {
13457 + case PCI_BUS:
13458 + idx = si->sb.buscoreidx;
13459 + break;
13460 + case JTAG_BUS:
13461 + idx = SB_CC_IDX;
13462 + break;
13463 + case PCMCIA_BUS:
13464 + case SDIO_BUS:
13465 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
13466 + break;
13467 + case SB_BUS:
13468 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
13469 + idx = sb_findcoreidx(si, SB_MIPS, 0);
13470 + break;
13471 + default:
13472 + ASSERT(0);
13473 + }
13474 + if (idx == BADIDX)
13475 + return ret;
13476 +
13477 + INTR_OFF(si, intr_val);
13478 + origidx = sb_coreidx(sbh);
13479 +
13480 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
13481 +
13482 + tmp = R_SBREG(si, &sb->sbimconfiglow);
13483 + ret = tmp & TO_MASK;
13484 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
13485 +
13486 + sb_commit(sbh);
13487 + sb_setcoreidx(sbh, origidx);
13488 + INTR_RESTORE(si, intr_val);
13489 + return ret;
13490 +}
13491 +
13492 +void
13493 +sb_core_disable(sb_t *sbh, uint32 bits)
13494 +{
13495 + sb_info_t *si;
13496 + volatile uint32 dummy;
13497 + uint32 rej;
13498 + sbconfig_t *sb;
13499 +
13500 + si = SB_INFO(sbh);
13501 +
13502 + ASSERT(GOODREGS(si->curmap));
13503 + sb = REGS2SB(si->curmap);
13504 +
13505 + /* if core is already in reset, just return */
13506 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
13507 + return;
13508 +
13509 + /* reject value changed between sonics 2.2 and 2.3 */
13510 + if (si->sb.sonicsrev == SONICS_2_2)
13511 + rej = (1 << SBTML_REJ_SHIFT);
13512 + else
13513 + rej = (2 << SBTML_REJ_SHIFT);
13514 +
13515 + /* if clocks are not enabled, put into reset and return */
13516 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
13517 + goto disable;
13518 +
13519 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
13520 + OR_SBREG(si, &sb->sbtmstatelow, rej);
13521 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13522 + OSL_DELAY(1);
13523 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
13524 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY)
13525 + SB_ERROR(("%s: target state still busy\n", __FUNCTION__));
13526 +
13527 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
13528 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
13529 + dummy = R_SBREG(si, &sb->sbimstate);
13530 + OSL_DELAY(1);
13531 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
13532 + }
13533 +
13534 + /* set reset and reject while enabling the clocks */
13535 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
13536 + dummy = R_SBREG(si, &sb->sbtmstatelow);
13537 + OSL_DELAY(10);
13538 +
13539 + /* don't forget to clear the initiator reject bit */
13540 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
13541 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
13542 +
13543 +disable:
13544 + /* leave reset and reject asserted */
13545 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
13546 + OSL_DELAY(1);
13547 +}
13548 +
13549 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
13550 +void
13551 +sb_watchdog(sb_t *sbh, uint ticks)
13552 +{
13553 + sb_info_t *si = SB_INFO(sbh);
13554 +
13555 + /* make sure we come up in fast clock mode */
13556 + sb_clkctl_clk(sbh, CLK_FAST);
13557 +
13558 + /* instant NMI */
13559 + switch (si->gpioid) {
13560 + case SB_CC:
13561 +#ifdef __mips__
13562 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1)
13563 + MTC0(C0_BROADCOM, 4, (1 << 22));
13564 +#endif /* __mips__ */
13565 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
13566 +#ifdef __mips__
13567 + if (sb_chip(sbh) == BCM4785_CHIP_ID && ticks <= 1) {
13568 + __asm__ __volatile__ (
13569 + ".set\tmips3\n\t"
13570 + "sync\n\t"
13571 + "wait\n\t"
13572 + ".set\tmips0"
13573 + );
13574 + while (1);
13575 + }
13576 +#endif /* __mips__ */
13577 + break;
13578 + case SB_EXTIF:
13579 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
13580 + break;
13581 + }
13582 +}
13583 +
13584 +/* initialize the pcmcia core */
13585 +void
13586 +sb_pcmcia_init(sb_t *sbh)
13587 +{
13588 + sb_info_t *si;
13589 + uint8 cor = 0;
13590 +
13591 + si = SB_INFO(sbh);
13592 +
13593 + /* enable d11 mac interrupts */
13594 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13595 + cor |= COR_IRQEN | COR_FUNEN;
13596 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
13597 +
13598 +}
13599 +
13600 +
13601 +/*
13602 + * Configure the pci core for pci client (NIC) action
13603 + * coremask is the bitvec of cores by index to be enabled.
13604 + */
13605 +void
13606 +BCMINITFN(sb_pci_setup)(sb_t *sbh, uint coremask)
13607 +{
13608 + sb_info_t *si;
13609 + sbconfig_t *sb;
13610 + sbpciregs_t *pciregs;
13611 + uint32 sbflag;
13612 + uint32 w;
13613 + uint idx;
13614 + int reg_val;
13615 +
13616 + si = SB_INFO(sbh);
13617 +
13618 + /* if not pci bus, we're done */
13619 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
13620 + return;
13621 +
13622 + ASSERT(PCI(si) || PCIE(si));
13623 + ASSERT(si->sb.buscoreidx != BADIDX);
13624 +
13625 + /* get current core index */
13626 + idx = si->curidx;
13627 +
13628 + /* we interrupt on this backplane flag number */
13629 + ASSERT(GOODREGS(si->curmap));
13630 + sb = REGS2SB(si->curmap);
13631 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
13632 +
13633 + /* switch over to pci core */
13634 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
13635 + sb = REGS2SB(pciregs);
13636 +
13637 + /*
13638 + * Enable sb->pci interrupts. Assume
13639 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
13640 + */
13641 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
13642 + /* pci config write to set this core bit in PCIIntMask */
13643 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
13644 + w |= (coremask << PCI_SBIM_SHIFT);
13645 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
13646 + } else {
13647 + /* set sbintvec bit for our flag number */
13648 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
13649 + }
13650 +
13651 + if (PCI(si)) {
13652 + OR_REG(si->osh, &pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
13653 + if (si->sb.buscorerev >= 11)
13654 + OR_REG(si->osh, &pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
13655 + if (si->sb.buscorerev < 5) {
13656 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
13657 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
13658 + sb_commit(sbh);
13659 + }
13660 + }
13661 +
13662 +#ifdef PCIE_SUPPOER
13663 + /* PCIE workarounds */
13664 + if (PCIE(si)) {
13665 + if ((si->sb.buscorerev == 0) || (si->sb.buscorerev == 1)) {
13666 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13667 + PCIE_TLP_WORKAROUNDSREG);
13668 + reg_val |= 0x8;
13669 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS,
13670 + PCIE_TLP_WORKAROUNDSREG, reg_val);
13671 + }
13672 +
13673 + if (si->sb.buscorerev == 1) {
13674 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS,
13675 + PCIE_DLLP_LCREG);
13676 + reg_val |= (0x40);
13677 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
13678 + }
13679 +
13680 + if (si->sb.buscorerev == 0)
13681 + sb_war30841(si);
13682 + }
13683 +#endif
13684 +
13685 + /* switch back to previous core */
13686 + sb_setcoreidx(sbh, idx);
13687 +}
13688 +
13689 +uint32
13690 +sb_base(uint32 admatch)
13691 +{
13692 + uint32 base;
13693 + uint type;
13694 +
13695 + type = admatch & SBAM_TYPE_MASK;
13696 + ASSERT(type < 3);
13697 +
13698 + base = 0;
13699 +
13700 + if (type == 0) {
13701 + base = admatch & SBAM_BASE0_MASK;
13702 + } else if (type == 1) {
13703 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13704 + base = admatch & SBAM_BASE1_MASK;
13705 + } else if (type == 2) {
13706 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13707 + base = admatch & SBAM_BASE2_MASK;
13708 + }
13709 +
13710 + return (base);
13711 +}
13712 +
13713 +uint32
13714 +sb_size(uint32 admatch)
13715 +{
13716 + uint32 size;
13717 + uint type;
13718 +
13719 + type = admatch & SBAM_TYPE_MASK;
13720 + ASSERT(type < 3);
13721 +
13722 + size = 0;
13723 +
13724 + if (type == 0) {
13725 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
13726 + } else if (type == 1) {
13727 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13728 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
13729 + } else if (type == 2) {
13730 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
13731 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
13732 + }
13733 +
13734 + return (size);
13735 +}
13736 +
13737 +/* return the core-type instantiation # of the current core */
13738 +uint
13739 +sb_coreunit(sb_t *sbh)
13740 +{
13741 + sb_info_t *si;
13742 + uint idx;
13743 + uint coreid;
13744 + uint coreunit;
13745 + uint i;
13746 +
13747 + si = SB_INFO(sbh);
13748 + coreunit = 0;
13749 +
13750 + idx = si->curidx;
13751 +
13752 + ASSERT(GOODREGS(si->curmap));
13753 + coreid = sb_coreid(sbh);
13754 +
13755 + /* count the cores of our type */
13756 + for (i = 0; i < idx; i++)
13757 + if (si->coreid[i] == coreid)
13758 + coreunit++;
13759 +
13760 + return (coreunit);
13761 +}
13762 +
13763 +static INLINE uint32
13764 +factor6(uint32 x)
13765 +{
13766 + switch (x) {
13767 + case CC_F6_2: return 2;
13768 + case CC_F6_3: return 3;
13769 + case CC_F6_4: return 4;
13770 + case CC_F6_5: return 5;
13771 + case CC_F6_6: return 6;
13772 + case CC_F6_7: return 7;
13773 + default: return 0;
13774 + }
13775 +}
13776 +
13777 +/* calculate the speed the SB would run at given a set of clockcontrol values */
13778 +uint32
13779 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
13780 +{
13781 + uint32 n1, n2, clock, m1, m2, m3, mc;
13782 +
13783 + n1 = n & CN_N1_MASK;
13784 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
13785 +
13786 + if (pll_type == PLL_TYPE6) {
13787 + if (m & CC_T6_MMASK)
13788 + return CC_T6_M1;
13789 + else
13790 + return CC_T6_M0;
13791 + } else if ((pll_type == PLL_TYPE1) ||
13792 + (pll_type == PLL_TYPE3) ||
13793 + (pll_type == PLL_TYPE4) ||
13794 + (pll_type == PLL_TYPE7)) {
13795 + n1 = factor6(n1);
13796 + n2 += CC_F5_BIAS;
13797 + } else if (pll_type == PLL_TYPE2) {
13798 + n1 += CC_T2_BIAS;
13799 + n2 += CC_T2_BIAS;
13800 + ASSERT((n1 >= 2) && (n1 <= 7));
13801 + ASSERT((n2 >= 5) && (n2 <= 23));
13802 + } else if (pll_type == PLL_TYPE5) {
13803 + return (100000000);
13804 + } else
13805 + ASSERT(0);
13806 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
13807 + if ((pll_type == PLL_TYPE3) ||
13808 + (pll_type == PLL_TYPE7)) {
13809 + clock = CC_CLOCK_BASE2 * n1 * n2;
13810 + } else
13811 + clock = CC_CLOCK_BASE1 * n1 * n2;
13812 +
13813 + if (clock == 0)
13814 + return 0;
13815 +
13816 + m1 = m & CC_M1_MASK;
13817 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
13818 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
13819 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
13820 +
13821 + if ((pll_type == PLL_TYPE1) ||
13822 + (pll_type == PLL_TYPE3) ||
13823 + (pll_type == PLL_TYPE4) ||
13824 + (pll_type == PLL_TYPE7)) {
13825 + m1 = factor6(m1);
13826 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
13827 + m2 += CC_F5_BIAS;
13828 + else
13829 + m2 = factor6(m2);
13830 + m3 = factor6(m3);
13831 +
13832 + switch (mc) {
13833 + case CC_MC_BYPASS: return (clock);
13834 + case CC_MC_M1: return (clock / m1);
13835 + case CC_MC_M1M2: return (clock / (m1 * m2));
13836 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
13837 + case CC_MC_M1M3: return (clock / (m1 * m3));
13838 + default: return (0);
13839 + }
13840 + } else {
13841 + ASSERT(pll_type == PLL_TYPE2);
13842 +
13843 + m1 += CC_T2_BIAS;
13844 + m2 += CC_T2M2_BIAS;
13845 + m3 += CC_T2_BIAS;
13846 + ASSERT((m1 >= 2) && (m1 <= 7));
13847 + ASSERT((m2 >= 3) && (m2 <= 10));
13848 + ASSERT((m3 >= 2) && (m3 <= 7));
13849 +
13850 + if ((mc & CC_T2MC_M1BYP) == 0)
13851 + clock /= m1;
13852 + if ((mc & CC_T2MC_M2BYP) == 0)
13853 + clock /= m2;
13854 + if ((mc & CC_T2MC_M3BYP) == 0)
13855 + clock /= m3;
13856 +
13857 + return (clock);
13858 + }
13859 +}
13860 +
13861 +/* returns the current speed the SB is running at */
13862 +uint32
13863 +sb_clock(sb_t *sbh)
13864 +{
13865 + sb_info_t *si;
13866 + extifregs_t *eir;
13867 + chipcregs_t *cc;
13868 + uint32 n, m;
13869 + uint idx;
13870 + uint32 pll_type, rate;
13871 + uint intr_val = 0;
13872 +
13873 + si = SB_INFO(sbh);
13874 + idx = si->curidx;
13875 + pll_type = PLL_TYPE1;
13876 +
13877 + INTR_OFF(si, intr_val);
13878 +
13879 + /* switch to extif or chipc core */
13880 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
13881 + n = R_REG(si->osh, &eir->clockcontrol_n);
13882 + m = R_REG(si->osh, &eir->clockcontrol_sb);
13883 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
13884 + pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
13885 + if (pll_type == PLL_NONE) {
13886 + INTR_RESTORE(si, intr_val);
13887 + return 80000000;
13888 + }
13889 + n = R_REG(si->osh, &cc->clockcontrol_n);
13890 + if (pll_type == PLL_TYPE6)
13891 + m = R_REG(si->osh, &cc->clockcontrol_m3);
13892 + else if ((pll_type == PLL_TYPE3) && !(BCMINIT(sb_chip)(sbh) == 0x5365))
13893 + m = R_REG(si->osh, &cc->clockcontrol_m2);
13894 + else
13895 + m = R_REG(si->osh, &cc->clockcontrol_sb);
13896 + } else {
13897 + INTR_RESTORE(si, intr_val);
13898 + return 0;
13899 + }
13900 +
13901 + /* calculate rate */
13902 + if (BCMINIT(sb_chip)(sbh) == 0x5365)
13903 + rate = 100000000;
13904 + else {
13905 + rate = sb_clock_rate(pll_type, n, m);
13906 +
13907 + if (pll_type == PLL_TYPE3)
13908 + rate = rate / 2;
13909 + }
13910 +
13911 + /* switch back to previous core */
13912 + sb_setcoreidx(sbh, idx);
13913 +
13914 + INTR_RESTORE(si, intr_val);
13915 +
13916 + return rate;
13917 +}
13918 +
13919 +/* change logical "focus" to the gpio core for optimized access */
13920 +void*
13921 +sb_gpiosetcore(sb_t *sbh)
13922 +{
13923 + sb_info_t *si;
13924 +
13925 + si = SB_INFO(sbh);
13926 +
13927 + return (sb_setcoreidx(sbh, si->gpioidx));
13928 +}
13929 +
13930 +/* mask&set gpiocontrol bits */
13931 +uint32
13932 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13933 +{
13934 + sb_info_t *si;
13935 + uint regoff;
13936 +
13937 + si = SB_INFO(sbh);
13938 + regoff = 0;
13939 +
13940 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13941 +
13942 + /* gpios could be shared on router platforms */
13943 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13944 + mask = priority ? (sb_gpioreservation & mask) :
13945 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13946 + val &= mask;
13947 + }
13948 +
13949 + switch (si->gpioid) {
13950 + case SB_CC:
13951 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
13952 + break;
13953 +
13954 + case SB_PCI:
13955 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
13956 + break;
13957 +
13958 + case SB_EXTIF:
13959 + return (0);
13960 + }
13961 +
13962 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13963 +}
13964 +
13965 +/* mask&set gpio output enable bits */
13966 +uint32
13967 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
13968 +{
13969 + sb_info_t *si;
13970 + uint regoff;
13971 +
13972 + si = SB_INFO(sbh);
13973 + regoff = 0;
13974 +
13975 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
13976 +
13977 + /* gpios could be shared on router platforms */
13978 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
13979 + mask = priority ? (sb_gpioreservation & mask) :
13980 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
13981 + val &= mask;
13982 + }
13983 +
13984 + switch (si->gpioid) {
13985 + case SB_CC:
13986 + regoff = OFFSETOF(chipcregs_t, gpioouten);
13987 + break;
13988 +
13989 + case SB_PCI:
13990 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
13991 + break;
13992 +
13993 + case SB_EXTIF:
13994 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
13995 + break;
13996 + }
13997 +
13998 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
13999 +}
14000 +
14001 +/* mask&set gpio output bits */
14002 +uint32
14003 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14004 +{
14005 + sb_info_t *si;
14006 + uint regoff;
14007 +
14008 + si = SB_INFO(sbh);
14009 + regoff = 0;
14010 +
14011 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14012 +
14013 + /* gpios could be shared on router platforms */
14014 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14015 + mask = priority ? (sb_gpioreservation & mask) :
14016 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14017 + val &= mask;
14018 + }
14019 +
14020 + switch (si->gpioid) {
14021 + case SB_CC:
14022 + regoff = OFFSETOF(chipcregs_t, gpioout);
14023 + break;
14024 +
14025 + case SB_PCI:
14026 + regoff = OFFSETOF(sbpciregs_t, gpioout);
14027 + break;
14028 +
14029 + case SB_EXTIF:
14030 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
14031 + break;
14032 + }
14033 +
14034 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14035 +}
14036 +
14037 +/* reserve one gpio */
14038 +uint32
14039 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14040 +{
14041 + sb_info_t *si;
14042 +
14043 + si = SB_INFO(sbh);
14044 +
14045 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14046 +
14047 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14048 + * reserve/release GPIO
14049 + */
14050 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14051 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14052 + return -1;
14053 + }
14054 + /* make sure only one bit is set */
14055 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14056 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14057 + return -1;
14058 + }
14059 +
14060 + /* already reserved */
14061 + if (sb_gpioreservation & gpio_bitmask)
14062 + return -1;
14063 + /* set reservation */
14064 + sb_gpioreservation |= gpio_bitmask;
14065 +
14066 + return sb_gpioreservation;
14067 +}
14068 +
14069 +/* release one gpio */
14070 +/*
14071 + * releasing the gpio doesn't change the current value on the GPIO last write value
14072 + * persists till some one overwrites it
14073 +*/
14074 +
14075 +uint32
14076 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
14077 +{
14078 + sb_info_t *si;
14079 +
14080 + si = SB_INFO(sbh);
14081 +
14082 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14083 +
14084 + /* only cores on SB_BUS share GPIO's and only applcation users need to
14085 + * reserve/release GPIO
14086 + */
14087 + if ((BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
14088 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
14089 + return -1;
14090 + }
14091 + /* make sure only one bit is set */
14092 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
14093 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
14094 + return -1;
14095 + }
14096 +
14097 + /* already released */
14098 + if (!(sb_gpioreservation & gpio_bitmask))
14099 + return -1;
14100 +
14101 + /* clear reservation */
14102 + sb_gpioreservation &= ~gpio_bitmask;
14103 +
14104 + return sb_gpioreservation;
14105 +}
14106 +
14107 +/* return the current gpioin register value */
14108 +uint32
14109 +sb_gpioin(sb_t *sbh)
14110 +{
14111 + sb_info_t *si;
14112 + uint regoff;
14113 +
14114 + si = SB_INFO(sbh);
14115 + regoff = 0;
14116 +
14117 + switch (si->gpioid) {
14118 + case SB_CC:
14119 + regoff = OFFSETOF(chipcregs_t, gpioin);
14120 + break;
14121 +
14122 + case SB_PCI:
14123 + regoff = OFFSETOF(sbpciregs_t, gpioin);
14124 + break;
14125 +
14126 + case SB_EXTIF:
14127 + regoff = OFFSETOF(extifregs_t, gpioin);
14128 + break;
14129 + }
14130 +
14131 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
14132 +}
14133 +
14134 +/* mask&set gpio interrupt polarity bits */
14135 +uint32
14136 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14137 +{
14138 + sb_info_t *si;
14139 + uint regoff;
14140 +
14141 + si = SB_INFO(sbh);
14142 + regoff = 0;
14143 +
14144 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14145 +
14146 + /* gpios could be shared on router platforms */
14147 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14148 + mask = priority ? (sb_gpioreservation & mask) :
14149 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14150 + val &= mask;
14151 + }
14152 +
14153 + switch (si->gpioid) {
14154 + case SB_CC:
14155 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
14156 + break;
14157 +
14158 + case SB_PCI:
14159 + /* pci gpio implementation does not support interrupt polarity */
14160 + ASSERT(0);
14161 + break;
14162 +
14163 + case SB_EXTIF:
14164 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
14165 + break;
14166 + }
14167 +
14168 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14169 +}
14170 +
14171 +/* mask&set gpio interrupt mask bits */
14172 +uint32
14173 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
14174 +{
14175 + sb_info_t *si;
14176 + uint regoff;
14177 +
14178 + si = SB_INFO(sbh);
14179 + regoff = 0;
14180 +
14181 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
14182 +
14183 + /* gpios could be shared on router platforms */
14184 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
14185 + mask = priority ? (sb_gpioreservation & mask) :
14186 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
14187 + val &= mask;
14188 + }
14189 +
14190 + switch (si->gpioid) {
14191 + case SB_CC:
14192 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
14193 + break;
14194 +
14195 + case SB_PCI:
14196 + /* pci gpio implementation does not support interrupt mask */
14197 + ASSERT(0);
14198 + break;
14199 +
14200 + case SB_EXTIF:
14201 + regoff = OFFSETOF(extifregs_t, gpiointmask);
14202 + break;
14203 + }
14204 +
14205 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
14206 +}
14207 +
14208 +/* assign the gpio to an led */
14209 +uint32
14210 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
14211 +{
14212 + sb_info_t *si;
14213 +
14214 + si = SB_INFO(sbh);
14215 + if (si->sb.ccrev < 16)
14216 + return -1;
14217 +
14218 + /* gpio led powersave reg */
14219 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
14220 +}
14221 +
14222 +/* mask & set gpio timer val */
14223 +uint32
14224 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
14225 +{
14226 + sb_info_t *si;
14227 + si = SB_INFO(sbh);
14228 +
14229 + if (si->sb.ccrev < 16)
14230 + return -1;
14231 +
14232 + return (sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
14233 +}
14234 +
14235 +
14236 +/* return the slow clock source - LPO, XTAL, or PCI */
14237 +static uint
14238 +sb_slowclk_src(sb_info_t *si)
14239 +{
14240 + chipcregs_t *cc;
14241 +
14242 +
14243 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14244 +
14245 + if (si->sb.ccrev < 6) {
14246 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS) &&
14247 + (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32)) &
14248 + PCI_CFG_GPIO_SCS))
14249 + return (SCC_SS_PCI);
14250 + else
14251 + return (SCC_SS_XTAL);
14252 + } else if (si->sb.ccrev < 10) {
14253 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14254 + return (R_REG(si->osh, &cc->slow_clk_ctl) & SCC_SS_MASK);
14255 + } else /* Insta-clock */
14256 + return (SCC_SS_XTAL);
14257 +}
14258 +
14259 +/* return the ILP (slowclock) min or max frequency */
14260 +static uint
14261 +sb_slowclk_freq(sb_info_t *si, bool max)
14262 +{
14263 + chipcregs_t *cc;
14264 + uint32 slowclk;
14265 + uint div;
14266 +
14267 +
14268 + ASSERT(sb_coreid(&si->sb) == SB_CC);
14269 +
14270 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
14271 +
14272 + /* shouldn't be here unless we've established the chip has dynamic clk control */
14273 + ASSERT(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL);
14274 +
14275 + slowclk = sb_slowclk_src(si);
14276 + if (si->sb.ccrev < 6) {
14277 + if (slowclk == SCC_SS_PCI)
14278 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
14279 + else
14280 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
14281 + } else if (si->sb.ccrev < 10) {
14282 + div = 4 * (((R_REG(si->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
14283 + if (slowclk == SCC_SS_LPO)
14284 + return (max? LPOMAXFREQ : LPOMINFREQ);
14285 + else if (slowclk == SCC_SS_XTAL)
14286 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
14287 + else if (slowclk == SCC_SS_PCI)
14288 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
14289 + else
14290 + ASSERT(0);
14291 + } else {
14292 + /* Chipc rev 10 is InstaClock */
14293 + div = R_REG(si->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
14294 + div = 4 * (div + 1);
14295 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
14296 + }
14297 + return (0);
14298 +}
14299 +
14300 +static void
14301 +BCMINITFN(sb_clkctl_setdelay)(sb_info_t *si, void *chipcregs)
14302 +{
14303 + chipcregs_t * cc;
14304 + uint slowmaxfreq, pll_delay, slowclk;
14305 + uint pll_on_delay, fref_sel_delay;
14306 +
14307 + pll_delay = PLL_DELAY;
14308 +
14309 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
14310 + * since the xtal will also be powered down by dynamic clk control logic.
14311 + */
14312 +
14313 + slowclk = sb_slowclk_src(si);
14314 + if (slowclk != SCC_SS_XTAL)
14315 + pll_delay += XTAL_ON_DELAY;
14316 +
14317 + /* Starting with 4318 it is ILP that is used for the delays */
14318 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
14319 +
14320 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
14321 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
14322 +
14323 + cc = (chipcregs_t *)chipcregs;
14324 + W_REG(si->osh, &cc->pll_on_delay, pll_on_delay);
14325 + W_REG(si->osh, &cc->fref_sel_delay, fref_sel_delay);
14326 +}
14327 +
14328 +/* initialize power control delay registers */
14329 +void
14330 +BCMINITFN(sb_clkctl_init)(sb_t *sbh)
14331 +{
14332 + sb_info_t *si;
14333 + uint origidx;
14334 + chipcregs_t *cc;
14335 +
14336 + si = SB_INFO(sbh);
14337 +
14338 + origidx = si->curidx;
14339 +
14340 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14341 + return;
14342 +
14343 + if ((si->sb.chip == BCM4321_CHIP_ID) && (si->sb.chiprev < 2))
14344 + W_REG(si->osh, &cc->chipcontrol,
14345 + (si->sb.chiprev == 0) ? CHIPCTRL_4321A0_DEFAULT : CHIPCTRL_4321A1_DEFAULT);
14346 +
14347 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14348 + goto done;
14349 +
14350 + /* set all Instaclk chip ILP to 1 MHz */
14351 + else if (si->sb.ccrev >= 10)
14352 + SET_REG(si->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
14353 + (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
14354 +
14355 + sb_clkctl_setdelay(si, (void *)cc);
14356 +
14357 +done:
14358 + sb_setcoreidx(sbh, origidx);
14359 +}
14360 +
14361 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
14362 +uint16
14363 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
14364 +{
14365 + sb_info_t *si;
14366 + uint origidx;
14367 + chipcregs_t *cc;
14368 + uint slowminfreq;
14369 + uint16 fpdelay;
14370 + uint intr_val = 0;
14371 +
14372 + si = SB_INFO(sbh);
14373 + fpdelay = 0;
14374 + origidx = si->curidx;
14375 +
14376 + INTR_OFF(si, intr_val);
14377 +
14378 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
14379 + goto done;
14380 +
14381 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14382 + goto done;
14383 +
14384 + slowminfreq = sb_slowclk_freq(si, FALSE);
14385 + fpdelay = (((R_REG(si->osh, &cc->pll_on_delay) + 2) * 1000000) +
14386 + (slowminfreq - 1)) / slowminfreq;
14387 +
14388 +done:
14389 + sb_setcoreidx(sbh, origidx);
14390 + INTR_RESTORE(si, intr_val);
14391 + return (fpdelay);
14392 +}
14393 +
14394 +/* turn primary xtal and/or pll off/on */
14395 +int
14396 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
14397 +{
14398 + sb_info_t *si;
14399 + uint32 in, out, outen;
14400 +
14401 + si = SB_INFO(sbh);
14402 +
14403 + switch (BUSTYPE(si->sb.bustype)) {
14404 +
14405 +
14406 + case PCMCIA_BUS:
14407 + return (0);
14408 +
14409 +
14410 + case PCI_BUS:
14411 +
14412 + /* pcie core doesn't have any mapping to control the xtal pu */
14413 + if (PCIE(si))
14414 + return -1;
14415 +
14416 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof(uint32));
14417 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32));
14418 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32));
14419 +
14420 + /*
14421 + * Avoid glitching the clock if GPRS is already using it.
14422 + * We can't actually read the state of the PLLPD so we infer it
14423 + * by the value of XTAL_PU which *is* readable via gpioin.
14424 + */
14425 + if (on && (in & PCI_CFG_GPIO_XTAL))
14426 + return (0);
14427 +
14428 + if (what & XTAL)
14429 + outen |= PCI_CFG_GPIO_XTAL;
14430 + if (what & PLL)
14431 + outen |= PCI_CFG_GPIO_PLL;
14432 +
14433 + if (on) {
14434 + /* turn primary xtal on */
14435 + if (what & XTAL) {
14436 + out |= PCI_CFG_GPIO_XTAL;
14437 + if (what & PLL)
14438 + out |= PCI_CFG_GPIO_PLL;
14439 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14440 + sizeof(uint32), out);
14441 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN,
14442 + sizeof(uint32), outen);
14443 + OSL_DELAY(XTAL_ON_DELAY);
14444 + }
14445 +
14446 + /* turn pll on */
14447 + if (what & PLL) {
14448 + out &= ~PCI_CFG_GPIO_PLL;
14449 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT,
14450 + sizeof(uint32), out);
14451 + OSL_DELAY(2000);
14452 + }
14453 + } else {
14454 + if (what & XTAL)
14455 + out &= ~PCI_CFG_GPIO_XTAL;
14456 + if (what & PLL)
14457 + out |= PCI_CFG_GPIO_PLL;
14458 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof(uint32), out);
14459 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof(uint32),
14460 + outen);
14461 + }
14462 +
14463 + default:
14464 + return (-1);
14465 + }
14466 +
14467 + return (0);
14468 +}
14469 +
14470 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
14471 +/* returns true if we are forcing fast clock */
14472 +bool
14473 +sb_clkctl_clk(sb_t *sbh, uint mode)
14474 +{
14475 + sb_info_t *si;
14476 + uint origidx;
14477 + chipcregs_t *cc;
14478 + uint32 scc;
14479 + uint intr_val = 0;
14480 +
14481 + si = SB_INFO(sbh);
14482 +
14483 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
14484 + if (si->sb.ccrev < 6)
14485 + return (FALSE);
14486 +
14487 +
14488 + /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
14489 + ASSERT(si->sb.ccrev != 10);
14490 +
14491 + INTR_OFF(si, intr_val);
14492 +
14493 + origidx = si->curidx;
14494 +
14495 + if (sb_setcore(sbh, SB_MIPS33, 0) && (sb_corerev(&si->sb) <= 7) &&
14496 + (BUSTYPE(si->sb.bustype) == SB_BUS) && (si->sb.ccrev >= 10))
14497 + goto done;
14498 +
14499 + /* PR32414WAR "Force HT clock on" all the time, no dynamic clk ctl */
14500 + if ((si->sb.chip == BCM4311_CHIP_ID) && (si->sb.chiprev <= 1))
14501 + goto done;
14502 +
14503 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
14504 + ASSERT(cc != NULL);
14505 +
14506 + if (!(R_REG(si->osh, &cc->capabilities) & CAP_PWR_CTL))
14507 + goto done;
14508 +
14509 + switch (mode) {
14510 + case CLK_FAST: /* force fast (pll) clock */
14511 + if (si->sb.ccrev < 10) {
14512 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
14513 + sb_clkctl_xtal(&si->sb, XTAL, ON);
14514 +
14515 + SET_REG(si->osh, &cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
14516 + } else
14517 + OR_REG(si->osh, &cc->system_clk_ctl, SYCC_HR);
14518 + /* wait for the PLL */
14519 + OSL_DELAY(PLL_DELAY);
14520 + break;
14521 +
14522 + case CLK_DYNAMIC: /* enable dynamic clock control */
14523 +
14524 + if (si->sb.ccrev < 10) {
14525 + scc = R_REG(si->osh, &cc->slow_clk_ctl);
14526 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
14527 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
14528 + scc |= SCC_XC;
14529 + W_REG(si->osh, &cc->slow_clk_ctl, scc);
14530 +
14531 + /* for dynamic control, we have to release our xtal_pu "force on" */
14532 + if (scc & SCC_XC)
14533 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
14534 + } else {
14535 + /* Instaclock */
14536 + AND_REG(si->osh, &cc->system_clk_ctl, ~SYCC_HR);
14537 + }
14538 + break;
14539 +
14540 + default:
14541 + ASSERT(0);
14542 + }
14543 +
14544 +done:
14545 + sb_setcoreidx(sbh, origidx);
14546 + INTR_RESTORE(si, intr_val);
14547 + return (mode == CLK_FAST);
14548 +}
14549 +
14550 +/* register driver interrupt disabling and restoring callback functions */
14551 +void
14552 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn,
14553 + void *intrsenabled_fn, void *intr_arg)
14554 +{
14555 + sb_info_t *si;
14556 +
14557 + si = SB_INFO(sbh);
14558 + si->intr_arg = intr_arg;
14559 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
14560 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
14561 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
14562 + /* save current core id. when this function called, the current core
14563 + * must be the core which provides driver functions(il, et, wl, etc.)
14564 + */
14565 + si->dev_coreid = si->coreid[si->curidx];
14566 +}
14567 +
14568 +
14569 +int
14570 +sb_corepciid(sb_t *sbh, uint func, uint16 *pcivendor, uint16 *pcidevice,
14571 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif,
14572 + uint8 *pciheader)
14573 +{
14574 + uint16 vendor = 0xffff, device = 0xffff;
14575 + uint core, unit;
14576 + uint chip, chippkg;
14577 + uint nfunc;
14578 + char varname[SB_DEVPATH_BUFSZ + 8];
14579 + uint8 class, subclass, progif;
14580 + char devpath[SB_DEVPATH_BUFSZ];
14581 + uint8 header;
14582 +
14583 + core = sb_coreid(sbh);
14584 + unit = sb_coreunit(sbh);
14585 +
14586 + chip = sb_chip(sbh);
14587 + chippkg = sb_chippkg(sbh);
14588 +
14589 + progif = 0;
14590 + header = PCI_HEADER_NORMAL;
14591 +
14592 + /* Verify whether the function exists for the core */
14593 + nfunc = (core == SB_USB20H) ? 2 : 1;
14594 + if (func >= nfunc)
14595 + return BCME_ERROR;
14596 +
14597 + /* Known vendor translations */
14598 + switch (sb_corevendor(sbh)) {
14599 + case SB_VEND_BCM:
14600 + vendor = VENDOR_BROADCOM;
14601 + break;
14602 + default:
14603 + return BCME_ERROR;
14604 + }
14605 +
14606 + /* Determine class based on known core codes */
14607 + switch (core) {
14608 + case SB_ILINE20:
14609 + class = PCI_CLASS_NET;
14610 + subclass = PCI_NET_ETHER;
14611 + device = BCM47XX_ILINE_ID;
14612 + break;
14613 + case SB_ENET:
14614 + class = PCI_CLASS_NET;
14615 + subclass = PCI_NET_ETHER;
14616 + device = BCM47XX_ENET_ID;
14617 + break;
14618 + case SB_GIGETH:
14619 + class = PCI_CLASS_NET;
14620 + subclass = PCI_NET_ETHER;
14621 + device = BCM47XX_GIGETH_ID;
14622 + break;
14623 + case SB_SDRAM:
14624 + case SB_MEMC:
14625 + class = PCI_CLASS_MEMORY;
14626 + subclass = PCI_MEMORY_RAM;
14627 + device = (uint16)core;
14628 + break;
14629 + case SB_PCI:
14630 + case SB_PCIE:
14631 + class = PCI_CLASS_BRIDGE;
14632 + subclass = PCI_BRIDGE_PCI;
14633 + device = (uint16)core;
14634 + header = PCI_HEADER_BRIDGE;
14635 + break;
14636 + case SB_MIPS:
14637 + case SB_MIPS33:
14638 + class = PCI_CLASS_CPU;
14639 + subclass = PCI_CPU_MIPS;
14640 + device = (uint16)core;
14641 + break;
14642 + case SB_CODEC:
14643 + class = PCI_CLASS_COMM;
14644 + subclass = PCI_COMM_MODEM;
14645 + device = BCM47XX_V90_ID;
14646 + break;
14647 + case SB_USB:
14648 + class = PCI_CLASS_SERIAL;
14649 + subclass = PCI_SERIAL_USB;
14650 + progif = 0x10; /* OHCI */
14651 + device = BCM47XX_USB_ID;
14652 + break;
14653 + case SB_USB11H:
14654 + class = PCI_CLASS_SERIAL;
14655 + subclass = PCI_SERIAL_USB;
14656 + progif = 0x10; /* OHCI */
14657 + device = BCM47XX_USBH_ID;
14658 + break;
14659 + case SB_USB20H:
14660 + class = PCI_CLASS_SERIAL;
14661 + subclass = PCI_SERIAL_USB;
14662 + progif = func == 0 ? 0x10 : 0x20; /* OHCI/EHCI */
14663 + device = BCM47XX_USB20H_ID;
14664 + header = 0x80; /* multifunction */
14665 + break;
14666 + case SB_USB11D:
14667 + class = PCI_CLASS_SERIAL;
14668 + subclass = PCI_SERIAL_USB;
14669 + device = BCM47XX_USBD_ID;
14670 + break;
14671 + case SB_USB20D:
14672 + class = PCI_CLASS_SERIAL;
14673 + subclass = PCI_SERIAL_USB;
14674 + device = BCM47XX_USB20D_ID;
14675 + break;
14676 + case SB_IPSEC:
14677 + class = PCI_CLASS_CRYPT;
14678 + subclass = PCI_CRYPT_NETWORK;
14679 + device = BCM47XX_IPSEC_ID;
14680 + break;
14681 + case SB_ROBO:
14682 + class = PCI_CLASS_NET;
14683 + subclass = PCI_NET_OTHER;
14684 + device = BCM47XX_ROBO_ID;
14685 + break;
14686 + case SB_EXTIF:
14687 + case SB_CC:
14688 + class = PCI_CLASS_MEMORY;
14689 + subclass = PCI_MEMORY_FLASH;
14690 + device = (uint16)core;
14691 + break;
14692 + case SB_D11:
14693 + class = PCI_CLASS_NET;
14694 + subclass = PCI_NET_OTHER;
14695 + /* Let nvram variable override core ID */
14696 + sb_devpath(sbh, devpath, sizeof(devpath));
14697 + sprintf(varname, "%sdevid", devpath);
14698 + if ((device = (uint16)getintvar(NULL, varname)))
14699 + break;
14700 + /*
14701 + * no longer support wl%did, but keep the code
14702 + * here for backward compatibility.
14703 + */
14704 + sprintf(varname, "wl%did", unit);
14705 + if ((device = (uint16)getintvar(NULL, varname)))
14706 + break;
14707 + /* Chip specific conversion */
14708 + if (chip == BCM4712_CHIP_ID) {
14709 + if (chippkg == BCM4712SMALL_PKG_ID)
14710 + device = BCM4306_D11G_ID;
14711 + else
14712 + device = BCM4306_D11DUAL_ID;
14713 + break;
14714 + }
14715 + /* ignore it */
14716 + device = 0xffff;
14717 + break;
14718 + case SB_SATAXOR:
14719 + class = PCI_CLASS_XOR;
14720 + subclass = PCI_XOR_QDMA;
14721 + device = BCM47XX_SATAXOR_ID;
14722 + break;
14723 + case SB_ATA100:
14724 + class = PCI_CLASS_DASDI;
14725 + subclass = PCI_DASDI_IDE;
14726 + device = BCM47XX_ATA100_ID;
14727 + break;
14728 +
14729 + default:
14730 + class = subclass = progif = 0xff;
14731 + device = (uint16)core;
14732 + break;
14733 + }
14734 +
14735 + *pcivendor = vendor;
14736 + *pcidevice = device;
14737 + *pciclass = class;
14738 + *pcisubclass = subclass;
14739 + *pciprogif = progif;
14740 + *pciheader = header;
14741 +
14742 + return 0;
14743 +}
14744 +
14745 +
14746 +
14747 +/* use the mdio interface to write to mdio slaves */
14748 +static int
14749 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
14750 +{
14751 + uint mdiodata;
14752 + uint i = 0;
14753 + sbpcieregs_t *pcieregs;
14754 +
14755 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
14756 + ASSERT(pcieregs);
14757 +
14758 + /* enable mdio access to SERDES */
14759 + W_REG(si->osh, (&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
14760 +
14761 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
14762 + (physmedia << MDIODATA_DEVADDR_SHF) |
14763 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
14764 +
14765 + W_REG(si->osh, (&pcieregs->mdiodata), mdiodata);
14766 +
14767 + PR28829_DELAY();
14768 +
14769 + /* retry till the transaction is complete */
14770 + while (i < 10) {
14771 + if (R_REG(si->osh, &(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
14772 + /* Disable mdio access to SERDES */
14773 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14774 + return 0;
14775 + }
14776 + OSL_DELAY(1000);
14777 + i++;
14778 + }
14779 +
14780 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
14781 + /* Disable mdio access to SERDES */
14782 + W_REG(si->osh, (&pcieregs->mdiocontrol), 0);
14783 + ASSERT(0);
14784 + return 1;
14785 +
14786 +}
14787 +
14788 +/* indirect way to read pcie config regs */
14789 +uint
14790 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
14791 +{
14792 + sb_info_t *si;
14793 + sb_t *sbh;
14794 + uint retval = 0xFFFFFFFF;
14795 + sbpcieregs_t *pcieregs;
14796 + uint addrtype;
14797 +
14798 + sbh = (sb_t *)sb;
14799 + si = SB_INFO(sbh);
14800 + ASSERT(PCIE(si));
14801 +
14802 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14803 + ASSERT(pcieregs);
14804 +
14805 + addrtype = (uint)((uintptr)arg1);
14806 + switch (addrtype) {
14807 + case PCIE_CONFIGREGS:
14808 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14809 + retval = R_REG(si->osh, &(pcieregs->configdata));
14810 + break;
14811 + case PCIE_PCIEREGS:
14812 + W_REG(si->osh, &(pcieregs->pcieaddr), offset);
14813 + retval = R_REG(si->osh, &(pcieregs->pciedata));
14814 + break;
14815 + default:
14816 + ASSERT(0);
14817 + break;
14818 + }
14819 + return retval;
14820 +}
14821 +
14822 +/* indirect way to write pcie config/mdio/pciecore regs */
14823 +uint
14824 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
14825 +{
14826 + sb_info_t *si;
14827 + sbpcieregs_t *pcieregs;
14828 + uint addrtype;
14829 +
14830 + si = SB_INFO(sbh);
14831 + ASSERT(PCIE(si));
14832 +
14833 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
14834 + ASSERT(pcieregs);
14835 +
14836 + addrtype = (uint)((uintptr)arg1);
14837 +
14838 + switch (addrtype) {
14839 + case PCIE_CONFIGREGS:
14840 + W_REG(si->osh, (&pcieregs->configaddr), offset);
14841 + W_REG(si->osh, (&pcieregs->configdata), val);
14842 + break;
14843 + case PCIE_PCIEREGS:
14844 + W_REG(si->osh, (&pcieregs->pcieaddr), offset);
14845 + W_REG(si->osh, (&pcieregs->pciedata), val);
14846 + break;
14847 + default:
14848 + ASSERT(0);
14849 + break;
14850 + }
14851 + return 0;
14852 +}
14853 +
14854 +/* Build device path. Support SB, PCI, and JTAG for now. */
14855 +int
14856 +sb_devpath(sb_t *sbh, char *path, int size)
14857 +{
14858 + ASSERT(path);
14859 + ASSERT(size >= SB_DEVPATH_BUFSZ);
14860 +
14861 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
14862 + case SB_BUS:
14863 + case JTAG_BUS:
14864 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
14865 + break;
14866 + case PCI_BUS:
14867 + ASSERT((SB_INFO(sbh))->osh);
14868 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
14869 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
14870 + break;
14871 + case PCMCIA_BUS:
14872 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
14873 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
14874 + sprintf(path, "pc/%u/%u/", 1, 1);
14875 + break;
14876 + case SDIO_BUS:
14877 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
14878 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
14879 + break;
14880 + default:
14881 + ASSERT(0);
14882 + break;
14883 + }
14884 +
14885 + return 0;
14886 +}
14887 +
14888 +/*
14889 + * Fixup SROMless PCI device's configuration.
14890 + * The current core may be changed upon return.
14891 + */
14892 +static int
14893 +sb_pci_fixcfg(sb_info_t *si)
14894 +{
14895 + uint origidx, pciidx;
14896 + sbpciregs_t *pciregs;
14897 + sbpcieregs_t *pcieregs;
14898 + uint16 val16, *reg16;
14899 + char name[SB_DEVPATH_BUFSZ+16], *value;
14900 + char devpath[SB_DEVPATH_BUFSZ];
14901 +
14902 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
14903 +
14904 + /* Fixup PI in SROM shadow area to enable the correct PCI core access */
14905 + /* save the current index */
14906 + origidx = sb_coreidx(&si->sb);
14907 +
14908 + /* check 'pi' is correct and fix it if not */
14909 + if (si->sb.buscoretype == SB_PCIE) {
14910 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
14911 + ASSERT(pcieregs);
14912 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
14913 + } else if (si->sb.buscoretype == SB_PCI) {
14914 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
14915 + ASSERT(pciregs);
14916 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
14917 + } else {
14918 + ASSERT(0);
14919 + return -1;
14920 + }
14921 + pciidx = sb_coreidx(&si->sb);
14922 + val16 = R_REG(si->osh, reg16);
14923 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
14924 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
14925 + W_REG(si->osh, reg16, val16);
14926 + }
14927 +
14928 + /* restore the original index */
14929 + sb_setcoreidx(&si->sb, origidx);
14930 +
14931 + /*
14932 + * Fixup bar0window in PCI config space to make the core indicated
14933 + * by the nvram variable the current core.
14934 + * !Do it last, it may change the current core!
14935 + */
14936 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
14937 + return -1;
14938 + sprintf(name, "%sb0w", devpath);
14939 + if ((value = getvar(NULL, name))) {
14940 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
14941 + bcm_strtoul(value, NULL, 16));
14942 + /* update curidx since the current core is changed */
14943 + si->curidx = _sb_coreidx(si);
14944 + if (si->curidx == BADIDX) {
14945 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
14946 + return -1;
14947 + }
14948 + }
14949 +
14950 + return 0;
14951 +}
14952 +
14953 +static uint
14954 +sb_chipc_capability(sb_t *sbh)
14955 +{
14956 + sb_info_t *si;
14957 +
14958 + si = SB_INFO(sbh);
14959 +
14960 + /* Make sure that there is ChipCommon core present */
14961 + if (si->coreid[SB_CC_IDX] == SB_CC)
14962 + return (sb_corereg(si, SB_CC_IDX, OFFSETOF(chipcregs_t, capabilities),
14963 + 0, 0));
14964 + return 0;
14965 +}
14966 +
14967 +/* Return ADDR64 capability of the backplane */
14968 +bool
14969 +sb_backplane64(sb_t *sbh)
14970 +{
14971 + return ((sb_chipc_capability(sbh) & CAP_BKPLN64) != 0);
14972 +}
14973 +
14974 +void
14975 +sb_btcgpiowar(sb_t *sbh)
14976 +{
14977 + sb_info_t *si;
14978 + uint origidx;
14979 + uint intr_val = 0;
14980 + chipcregs_t *cc;
14981 + si = SB_INFO(sbh);
14982 +
14983 + /* Make sure that there is ChipCommon core present &&
14984 + * UART_TX is strapped to 1
14985 + */
14986 + if (!(sb_chipc_capability(sbh) & CAP_UARTGPIO))
14987 + return;
14988 +
14989 + /* sb_corereg cannot be used as we have to guarantee 8-bit read/writes */
14990 + INTR_OFF(si, intr_val);
14991 +
14992 + origidx = sb_coreidx(sbh);
14993 +
14994 + cc = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
14995 + if (cc == NULL)
14996 + goto end;
14997 +
14998 + W_REG(si->osh, &cc->uart0mcr, R_REG(si->osh, &cc->uart0mcr) | 0x04);
14999 +
15000 +end:
15001 + /* restore the original index */
15002 + sb_setcoreidx(sbh, origidx);
15003 +
15004 + INTR_RESTORE(si, intr_val);
15005 +}
15006 +
15007 +/* check if the device is removed */
15008 +bool
15009 +sb_deviceremoved(sb_t *sbh)
15010 +{
15011 + uint32 w;
15012 + sb_info_t *si;
15013 +
15014 + si = SB_INFO(sbh);
15015 +
15016 + switch (BUSTYPE(si->sb.bustype)) {
15017 + case PCI_BUS:
15018 + ASSERT(si->osh);
15019 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_CFG_VID, sizeof(uint32));
15020 + if ((w & 0xFFFF) != VENDOR_BROADCOM)
15021 + return TRUE;
15022 + else
15023 + return FALSE;
15024 + default:
15025 + return FALSE;
15026 + }
15027 + return FALSE;
15028 +}
15029 +
15030 +/* Return the RAM size of the SOCRAM core */
15031 +uint32
15032 +sb_socram_size(sb_t *sbh)
15033 +{
15034 + sb_info_t *si;
15035 + uint origidx;
15036 + uint intr_val = 0;
15037 +
15038 + sbsocramregs_t *regs;
15039 + bool wasup;
15040 + uint corerev;
15041 + uint32 coreinfo;
15042 + uint memsize = 0;
15043 +
15044 + si = SB_INFO(sbh);
15045 + ASSERT(si);
15046 +
15047 + /* Block ints and save current core */
15048 + INTR_OFF(si, intr_val);
15049 + origidx = sb_coreidx(sbh);
15050 +
15051 + /* Switch to SOCRAM core */
15052 + if (!(regs = sb_setcore(sbh, SB_SOCRAM, 0)))
15053 + goto done;
15054 +
15055 + /* Get info for determining size */
15056 + if (!(wasup = sb_iscoreup(sbh)))
15057 + sb_core_reset(sbh, 0, 0);
15058 + corerev = sb_corerev(sbh);
15059 + coreinfo = R_REG(si->osh, &regs->coreinfo);
15060 +
15061 + /* Calculate size from coreinfo based on rev */
15062 + switch (corerev) {
15063 + case 0:
15064 + memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
15065 + break;
15066 + default: /* rev >= 1 */
15067 + memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
15068 + memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
15069 + break;
15070 + }
15071 +
15072 + /* Return to previous state and core */
15073 + if (!wasup)
15074 + sb_core_disable(sbh, 0);
15075 + sb_setcoreidx(sbh, origidx);
15076 +
15077 +done:
15078 + INTR_RESTORE(si, intr_val);
15079 + return memsize;
15080 +}
15081 +
15082 +
15083 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
15084 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
15085 +++ linux.dev/arch/mips/bcm947xx/setup.c 2006-04-27 23:22:53.000000000 +0200
15086 @@ -0,0 +1,241 @@
15087 +/*
15088 + * Generic setup routines for Broadcom MIPS boards
15089 + *
15090 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
15091 + *
15092 + * This program is free software; you can redistribute it and/or modify it
15093 + * under the terms of the GNU General Public License as published by the
15094 + * Free Software Foundation; either version 2 of the License, or (at your
15095 + * option) any later version.
15096 + *
15097 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15098 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15099 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15100 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15101 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15102 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15103 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
15104 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15105 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
15106 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15107 + *
15108 + * You should have received a copy of the GNU General Public License along
15109 + * with this program; if not, write to the Free Software Foundation, Inc.,
15110 + * 675 Mass Ave, Cambridge, MA 02139, USA.
15111 + *
15112 + *
15113 + * Copyright 2005, Broadcom Corporation
15114 + * All Rights Reserved.
15115 + *
15116 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15117 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15118 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15119 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15120 + *
15121 + */
15122 +
15123 +#include <linux/config.h>
15124 +#include <linux/init.h>
15125 +#include <linux/kernel.h>
15126 +#include <linux/module.h>
15127 +#include <linux/serialP.h>
15128 +#include <linux/ide.h>
15129 +#include <asm/bootinfo.h>
15130 +#include <asm/cpu.h>
15131 +#include <asm/time.h>
15132 +#include <asm/reboot.h>
15133 +
15134 +#include <typedefs.h>
15135 +#include <osl.h>
15136 +#include <sbutils.h>
15137 +#include <bcmutils.h>
15138 +#include <bcmnvram.h>
15139 +#include <sbhndmips.h>
15140 +#include <hndmips.h>
15141 +#include <trxhdr.h>
15142 +
15143 +/* Virtual IRQ base, after last hw IRQ */
15144 +#define SBMIPS_VIRTIRQ_BASE 6
15145 +
15146 +/* # IRQs, hw and sw IRQs */
15147 +#define SBMIPS_NUMIRQS 8
15148 +
15149 +/* Global SB handle */
15150 +sb_t *bcm947xx_sbh = NULL;
15151 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
15152 +
15153 +/* Convenience */
15154 +#define sbh bcm947xx_sbh
15155 +#define sbh_lock bcm947xx_sbh_lock
15156 +
15157 +extern void bcm947xx_time_init(void);
15158 +extern void bcm947xx_timer_setup(struct irqaction *irq);
15159 +
15160 +#ifdef CONFIG_REMOTE_DEBUG
15161 +extern void set_debug_traps(void);
15162 +extern void rs_kgdb_hook(struct serial_state *);
15163 +extern void breakpoint(void);
15164 +#endif
15165 +
15166 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15167 +extern struct ide_ops std_ide_ops;
15168 +#endif
15169 +
15170 +/* Kernel command line */
15171 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
15172 +extern void sb_serial_init(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
15173 +
15174 +void
15175 +bcm947xx_machine_restart(char *command)
15176 +{
15177 + printk("Please stand by while rebooting the system...\n");
15178 +
15179 + /* Set the watchdog timer to reset immediately */
15180 + __cli();
15181 + sb_watchdog(sbh, 1);
15182 + while (1);
15183 +}
15184 +
15185 +void
15186 +bcm947xx_machine_halt(void)
15187 +{
15188 + printk("System halted\n");
15189 +
15190 + /* Disable interrupts and watchdog and spin forever */
15191 + __cli();
15192 + sb_watchdog(sbh, 0);
15193 + while (1);
15194 +}
15195 +
15196 +#ifdef CONFIG_SERIAL
15197 +
15198 +static int ser_line = 0;
15199 +
15200 +typedef struct {
15201 + void *regs;
15202 + uint irq;
15203 + uint baud_base;
15204 + uint reg_shift;
15205 +} serial_port;
15206 +
15207 +static serial_port ports[4];
15208 +static int num_ports = 0;
15209 +
15210 +static void
15211 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
15212 +{
15213 + ports[num_ports].regs = regs;
15214 + ports[num_ports].irq = irq;
15215 + ports[num_ports].baud_base = baud_base;
15216 + ports[num_ports].reg_shift = reg_shift;
15217 + num_ports++;
15218 +}
15219 +
15220 +static void
15221 +do_serial_add(serial_port *port)
15222 +{
15223 + void *regs;
15224 + uint irq;
15225 + uint baud_base;
15226 + uint reg_shift;
15227 + struct serial_struct s;
15228 +
15229 + regs = port->regs;
15230 + irq = port->irq;
15231 + baud_base = port->baud_base;
15232 + reg_shift = port->reg_shift;
15233 +
15234 + memset(&s, 0, sizeof(s));
15235 +
15236 + s.line = ser_line++;
15237 + s.iomem_base = regs;
15238 + s.irq = irq + 2;
15239 + s.baud_base = baud_base / 16;
15240 + s.flags = ASYNC_BOOT_AUTOCONF;
15241 + s.io_type = SERIAL_IO_MEM;
15242 + s.iomem_reg_shift = reg_shift;
15243 +
15244 + if (early_serial_setup(&s) != 0) {
15245 + printk(KERN_ERR "Serial setup failed!\n");
15246 + }
15247 +}
15248 +
15249 +#endif /* CONFIG_SERIAL */
15250 +
15251 +void __init
15252 +brcm_setup(void)
15253 +{
15254 + char *s;
15255 + int i;
15256 + char *value;
15257 +
15258 + /* Get global SB handle */
15259 + sbh = sb_kattach();
15260 +
15261 + /* Initialize clocks and interrupts */
15262 + sb_mips_init(sbh, SBMIPS_VIRTIRQ_BASE);
15263 +
15264 + if (BCM330X(current_cpu_data.processor_id) &&
15265 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
15266 + /*
15267 + * Now that the sbh is inited set the proper PFC value
15268 + */
15269 + printk("Setting the PFC to its default value\n");
15270 + enable_pfc(PFC_AUTO);
15271 + }
15272 +
15273 +
15274 +#ifdef CONFIG_SERIAL
15275 + sb_serial_init(sbh, serial_add);
15276 +
15277 + /* reverse serial ports if nvram variable starts with console=ttyS1 */
15278 + /* Initialize UARTs */
15279 + s = nvram_get("kernel_args");
15280 + if (!s) s = "";
15281 + if (!strncmp(s, "console=ttyS1", 13)) {
15282 + for (i = num_ports; i; i--)
15283 + do_serial_add(&ports[i - 1]);
15284 + } else {
15285 + for (i = 0; i < num_ports; i++)
15286 + do_serial_add(&ports[i]);
15287 + }
15288 +#endif
15289 +
15290 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
15291 + ide_ops = &std_ide_ops;
15292 +#endif
15293 +
15294 + /* Override default command line arguments */
15295 + value = nvram_get("kernel_cmdline");
15296 + if (value && strlen(value) && strncmp(value, "empty", 5))
15297 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
15298 +
15299 +
15300 + /* Generic setup */
15301 + _machine_restart = bcm947xx_machine_restart;
15302 + _machine_halt = bcm947xx_machine_halt;
15303 + _machine_power_off = bcm947xx_machine_halt;
15304 +
15305 + board_time_init = bcm947xx_time_init;
15306 + board_timer_setup = bcm947xx_timer_setup;
15307 +}
15308 +
15309 +const char *
15310 +get_system_type(void)
15311 +{
15312 + static char s[32];
15313 +
15314 + if (bcm947xx_sbh) {
15315 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
15316 + sb_chiprev(bcm947xx_sbh));
15317 + return s;
15318 + }
15319 + else
15320 + return "Broadcom BCM947XX";
15321 +}
15322 +
15323 +void __init
15324 +bus_error_init(void)
15325 +{
15326 +}
15327 +
15328 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
15329 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
15330 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2006-04-27 22:11:27.000000000 +0200
15331 @@ -0,0 +1,422 @@
15332 +/*
15333 + * Broadcom SiliconBackplane chipcommon serial flash interface
15334 + *
15335 + * Copyright 2006, Broadcom Corporation
15336 + * All Rights Reserved.
15337 + *
15338 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15339 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15340 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15341 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15342 + *
15343 + * $Id: sflash.c,v 1.1.1.13 2006/02/27 03:43:16 honor Exp $
15344 + */
15345 +
15346 +#include <osl.h>
15347 +#include <typedefs.h>
15348 +#include <sbconfig.h>
15349 +#include <sbchipc.h>
15350 +#include <mipsinc.h>
15351 +#include <bcmutils.h>
15352 +#include <bcmdevs.h>
15353 +#include <sflash.h>
15354 +
15355 +/* Private global state */
15356 +static struct sflash sflash;
15357 +
15358 +/* Issue a serial flash command */
15359 +static INLINE void
15360 +sflash_cmd(chipcregs_t *cc, uint opcode)
15361 +{
15362 + W_REG(NULL, &cc->flashcontrol, SFLASH_START | opcode);
15363 + while (R_REG(NULL, &cc->flashcontrol) & SFLASH_BUSY);
15364 +}
15365 +
15366 +/* Initialize serial flash access */
15367 +struct sflash *
15368 +sflash_init(chipcregs_t *cc)
15369 +{
15370 + uint32 id, id2;
15371 +
15372 + bzero(&sflash, sizeof(sflash));
15373 +
15374 + sflash.type = R_REG(NULL, &cc->capabilities) & CAP_FLASH_MASK;
15375 +
15376 + switch (sflash.type) {
15377 + case SFLASH_ST:
15378 + /* Probe for ST chips */
15379 + sflash_cmd(cc, SFLASH_ST_DP);
15380 + sflash_cmd(cc, SFLASH_ST_RES);
15381 + id = R_REG(NULL, &cc->flashdata);
15382 + switch (id) {
15383 + case 0x11:
15384 + /* ST M25P20 2 Mbit Serial Flash */
15385 + sflash.blocksize = 64 * 1024;
15386 + sflash.numblocks = 4;
15387 + break;
15388 + case 0x12:
15389 + /* ST M25P40 4 Mbit Serial Flash */
15390 + sflash.blocksize = 64 * 1024;
15391 + sflash.numblocks = 8;
15392 + break;
15393 + case 0x13:
15394 + /* ST M25P80 8 Mbit Serial Flash */
15395 + sflash.blocksize = 64 * 1024;
15396 + sflash.numblocks = 16;
15397 + break;
15398 + case 0x14:
15399 + /* ST M25P16 16 Mbit Serial Flash */
15400 + sflash.blocksize = 64 * 1024;
15401 + sflash.numblocks = 32;
15402 + break;
15403 + case 0x15:
15404 + /* ST M25P32 32 Mbit Serial Flash */
15405 + sflash.blocksize = 64 * 1024;
15406 + sflash.numblocks = 64;
15407 + break;
15408 + case 0x16:
15409 + /* ST M25P64 64 Mbit Serial Flash */
15410 + sflash.blocksize = 64 * 1024;
15411 + sflash.numblocks = 128;
15412 + break;
15413 + case 0xbf:
15414 + W_REG(NULL, &cc->flashaddress, 1);
15415 + sflash_cmd(cc, SFLASH_ST_RES);
15416 + id2 = R_REG(NULL, &cc->flashdata);
15417 + if (id2 == 0x44) {
15418 + /* SST M25VF80 4 Mbit Serial Flash */
15419 + sflash.blocksize = 64 * 1024;
15420 + sflash.numblocks = 8;
15421 + }
15422 + break;
15423 + }
15424 + break;
15425 +
15426 + case SFLASH_AT:
15427 + /* Probe for Atmel chips */
15428 + sflash_cmd(cc, SFLASH_AT_STATUS);
15429 + id = R_REG(NULL, &cc->flashdata) & 0x3c;
15430 + switch (id) {
15431 + case 0xc:
15432 + /* Atmel AT45DB011 1Mbit Serial Flash */
15433 + sflash.blocksize = 256;
15434 + sflash.numblocks = 512;
15435 + break;
15436 + case 0x14:
15437 + /* Atmel AT45DB021 2Mbit Serial Flash */
15438 + sflash.blocksize = 256;
15439 + sflash.numblocks = 1024;
15440 + break;
15441 + case 0x1c:
15442 + /* Atmel AT45DB041 4Mbit Serial Flash */
15443 + sflash.blocksize = 256;
15444 + sflash.numblocks = 2048;
15445 + break;
15446 + case 0x24:
15447 + /* Atmel AT45DB081 8Mbit Serial Flash */
15448 + sflash.blocksize = 256;
15449 + sflash.numblocks = 4096;
15450 + break;
15451 + case 0x2c:
15452 + /* Atmel AT45DB161 16Mbit Serial Flash */
15453 + sflash.blocksize = 512;
15454 + sflash.numblocks = 4096;
15455 + break;
15456 + case 0x34:
15457 + /* Atmel AT45DB321 32Mbit Serial Flash */
15458 + sflash.blocksize = 512;
15459 + sflash.numblocks = 8192;
15460 + break;
15461 + case 0x3c:
15462 + /* Atmel AT45DB642 64Mbit Serial Flash */
15463 + sflash.blocksize = 1024;
15464 + sflash.numblocks = 8192;
15465 + break;
15466 + }
15467 + break;
15468 + }
15469 +
15470 + sflash.size = sflash.blocksize * sflash.numblocks;
15471 + return sflash.size ? &sflash : NULL;
15472 +}
15473 +
15474 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
15475 +int
15476 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
15477 +{
15478 + int cnt;
15479 + uint32 *from, *to;
15480 +
15481 + if (!len)
15482 + return 0;
15483 +
15484 + if ((offset + len) > sflash.size)
15485 + return -22;
15486 +
15487 + if ((len >= 4) && (offset & 3))
15488 + cnt = 4 - (offset & 3);
15489 + else if ((len >= 4) && ((uint32)buf & 3))
15490 + cnt = 4 - ((uint32)buf & 3);
15491 + else
15492 + cnt = len;
15493 +
15494 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
15495 + to = (uint32 *)buf;
15496 +
15497 + if (cnt < 4) {
15498 + bcopy(from, to, cnt);
15499 + return cnt;
15500 + }
15501 +
15502 + while (cnt >= 4) {
15503 + *to++ = *from++;
15504 + cnt -= 4;
15505 + }
15506 +
15507 + return (len - cnt);
15508 +}
15509 +
15510 +/* Poll for command completion. Returns zero when complete. */
15511 +int
15512 +sflash_poll(chipcregs_t *cc, uint offset)
15513 +{
15514 + if (offset >= sflash.size)
15515 + return -22;
15516 +
15517 + switch (sflash.type) {
15518 + case SFLASH_ST:
15519 + /* Check for ST Write In Progress bit */
15520 + sflash_cmd(cc, SFLASH_ST_RDSR);
15521 + return R_REG(NULL, &cc->flashdata) & SFLASH_ST_WIP;
15522 + case SFLASH_AT:
15523 + /* Check for Atmel Ready bit */
15524 + sflash_cmd(cc, SFLASH_AT_STATUS);
15525 + return !(R_REG(NULL, &cc->flashdata) & SFLASH_AT_READY);
15526 + }
15527 +
15528 + return 0;
15529 +}
15530 +
15531 +/* Write len bytes starting at offset into buf. Returns number of bytes
15532 + * written. Caller should poll for completion.
15533 + */
15534 +int
15535 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15536 +{
15537 + struct sflash *sfl;
15538 + int ret = 0;
15539 + bool is4712b0;
15540 + uint32 page, byte, mask;
15541 +
15542 + if (!len)
15543 + return 0;
15544 +
15545 + if ((offset + len) > sflash.size)
15546 + return -22;
15547 +
15548 + sfl = &sflash;
15549 + switch (sfl->type) {
15550 + case SFLASH_ST:
15551 + mask = R_REG(NULL, &cc->chipid);
15552 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_CHIP_ID) &&
15553 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
15554 + /* Enable writes */
15555 + sflash_cmd(cc, SFLASH_ST_WREN);
15556 + if (is4712b0) {
15557 + mask = 1 << 14;
15558 + W_REG(NULL, &cc->flashaddress, offset);
15559 + W_REG(NULL, &cc->flashdata, *buf++);
15560 + /* Set chip select */
15561 + OR_REG(NULL, &cc->gpioout, mask);
15562 + /* Issue a page program with the first byte */
15563 + sflash_cmd(cc, SFLASH_ST_PP);
15564 + ret = 1;
15565 + offset++;
15566 + len--;
15567 + while (len > 0) {
15568 + if ((offset & 255) == 0) {
15569 + /* Page boundary, drop cs and return */
15570 + AND_REG(NULL, &cc->gpioout, ~mask);
15571 + if (!sflash_poll(cc, offset)) {
15572 + /* Flash rejected command */
15573 + return -11;
15574 + }
15575 + return ret;
15576 + } else {
15577 + /* Write single byte */
15578 + sflash_cmd(cc, *buf++);
15579 + }
15580 + ret++;
15581 + offset++;
15582 + len--;
15583 + }
15584 + /* All done, drop cs if needed */
15585 + if ((offset & 255) != 1) {
15586 + /* Drop cs */
15587 + AND_REG(NULL, &cc->gpioout, ~mask);
15588 + if (!sflash_poll(cc, offset)) {
15589 + /* Flash rejected command */
15590 + return -12;
15591 + }
15592 + }
15593 + } else {
15594 + ret = 1;
15595 + W_REG(NULL, &cc->flashaddress, offset);
15596 + W_REG(NULL, &cc->flashdata, *buf);
15597 + /* Page program */
15598 + sflash_cmd(cc, SFLASH_ST_PP);
15599 + }
15600 + break;
15601 + case SFLASH_AT:
15602 + mask = sfl->blocksize - 1;
15603 + page = (offset & ~mask) << 1;
15604 + byte = offset & mask;
15605 + /* Read main memory page into buffer 1 */
15606 + if (byte || (len < sfl->blocksize)) {
15607 + W_REG(NULL, &cc->flashaddress, page);
15608 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
15609 + /* 250 us for AT45DB321B */
15610 + SPINWAIT(sflash_poll(cc, offset), 1000);
15611 + ASSERT(!sflash_poll(cc, offset));
15612 + }
15613 + /* Write into buffer 1 */
15614 + for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
15615 + W_REG(NULL, &cc->flashaddress, byte++);
15616 + W_REG(NULL, &cc->flashdata, *buf++);
15617 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
15618 + }
15619 + /* Write buffer 1 into main memory page */
15620 + W_REG(NULL, &cc->flashaddress, page);
15621 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
15622 + break;
15623 + }
15624 +
15625 + return ret;
15626 +}
15627 +
15628 +/* Erase a region. Returns number of bytes scheduled for erasure.
15629 + * Caller should poll for completion.
15630 + */
15631 +int
15632 +sflash_erase(chipcregs_t *cc, uint offset)
15633 +{
15634 + struct sflash *sfl;
15635 +
15636 + if (offset >= sflash.size)
15637 + return -22;
15638 +
15639 + sfl = &sflash;
15640 + switch (sfl->type) {
15641 + case SFLASH_ST:
15642 + sflash_cmd(cc, SFLASH_ST_WREN);
15643 + W_REG(NULL, &cc->flashaddress, offset);
15644 + sflash_cmd(cc, SFLASH_ST_SE);
15645 + return sfl->blocksize;
15646 + case SFLASH_AT:
15647 + W_REG(NULL, &cc->flashaddress, offset << 1);
15648 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
15649 + return sfl->blocksize;
15650 + }
15651 +
15652 + return 0;
15653 +}
15654 +
15655 +/*
15656 + * writes the appropriate range of flash, a NULL buf simply erases
15657 + * the region of flash
15658 + */
15659 +int
15660 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
15661 +{
15662 + struct sflash *sfl;
15663 + uchar *block = NULL, *cur_ptr, *blk_ptr;
15664 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
15665 + uint blk_offset, blk_len, copied;
15666 + int bytes, ret = 0;
15667 +
15668 + /* Check address range */
15669 + if (len <= 0)
15670 + return 0;
15671 +
15672 + sfl = &sflash;
15673 + if ((offset + len) > sfl->size)
15674 + return -1;
15675 +
15676 + blocksize = sfl->blocksize;
15677 + mask = blocksize - 1;
15678 +
15679 + /* Allocate a block of mem */
15680 + if (!(block = MALLOC(NULL, blocksize)))
15681 + return -1;
15682 +
15683 + while (len) {
15684 + /* Align offset */
15685 + cur_offset = offset & ~mask;
15686 + cur_length = blocksize;
15687 + cur_ptr = block;
15688 +
15689 + remainder = blocksize - (offset & mask);
15690 + if (len < remainder)
15691 + cur_retlen = len;
15692 + else
15693 + cur_retlen = remainder;
15694 +
15695 + /* buf == NULL means erase only */
15696 + if (buf) {
15697 + /* Copy existing data into holding block if necessary */
15698 + if ((offset & mask) || (len < blocksize)) {
15699 + blk_offset = cur_offset;
15700 + blk_len = cur_length;
15701 + blk_ptr = cur_ptr;
15702 +
15703 + /* Copy entire block */
15704 + while (blk_len) {
15705 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
15706 + blk_offset += copied;
15707 + blk_len -= copied;
15708 + blk_ptr += copied;
15709 + }
15710 + }
15711 +
15712 + /* Copy input data into holding block */
15713 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
15714 + }
15715 +
15716 + /* Erase block */
15717 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
15718 + goto done;
15719 + while (sflash_poll(cc, (uint) cur_offset));
15720 +
15721 + /* buf == NULL means erase only */
15722 + if (!buf) {
15723 + offset += cur_retlen;
15724 + len -= cur_retlen;
15725 + continue;
15726 + }
15727 +
15728 + /* Write holding block */
15729 + while (cur_length > 0) {
15730 + if ((bytes = sflash_write(cc,
15731 + (uint) cur_offset,
15732 + (uint) cur_length,
15733 + (uchar *) cur_ptr)) < 0) {
15734 + ret = bytes;
15735 + goto done;
15736 + }
15737 + while (sflash_poll(cc, (uint) cur_offset));
15738 + cur_offset += bytes;
15739 + cur_length -= bytes;
15740 + cur_ptr += bytes;
15741 + }
15742 +
15743 + offset += cur_retlen;
15744 + len -= cur_retlen;
15745 + buf += cur_retlen;
15746 + }
15747 +
15748 + ret = len;
15749 +done:
15750 + if (block)
15751 + MFREE(NULL, block, blocksize);
15752 + return ret;
15753 +}
15754 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
15755 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
15756 +++ linux.dev/arch/mips/bcm947xx/time.c 2006-04-28 00:45:40.000000000 +0200
15757 @@ -0,0 +1,104 @@
15758 +/*
15759 + * Copyright 2006, Broadcom Corporation
15760 + * All Rights Reserved.
15761 + *
15762 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15763 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15764 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15765 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15766 + *
15767 + * $Id: time.c,v 1.1.1.10 2006/02/27 03:42:55 honor Exp $
15768 + */
15769 +#include <linux/config.h>
15770 +#include <linux/init.h>
15771 +#include <linux/kernel.h>
15772 +#include <linux/sched.h>
15773 +#include <linux/serial_reg.h>
15774 +#include <linux/interrupt.h>
15775 +#include <asm/addrspace.h>
15776 +#include <asm/io.h>
15777 +#include <asm/time.h>
15778 +
15779 +#include <typedefs.h>
15780 +#include <osl.h>
15781 +#include <bcmnvram.h>
15782 +#include <sbconfig.h>
15783 +#include <sbextif.h>
15784 +#include <sbutils.h>
15785 +#include <hndmips.h>
15786 +#include <mipsinc.h>
15787 +#include <hndcpu.h>
15788 +
15789 +/* Global SB handle */
15790 +extern void *bcm947xx_sbh;
15791 +extern spinlock_t bcm947xx_sbh_lock;
15792 +
15793 +/* Convenience */
15794 +#define sbh bcm947xx_sbh
15795 +#define sbh_lock bcm947xx_sbh_lock
15796 +
15797 +extern int panic_timeout;
15798 +static int watchdog = 0;
15799 +static u8 *mcr = NULL;
15800 +
15801 +void __init
15802 +bcm947xx_time_init(void)
15803 +{
15804 + unsigned int hz;
15805 + extifregs_t *eir;
15806 +
15807 + /*
15808 + * Use deterministic values for initial counter interrupt
15809 + * so that calibrate delay avoids encountering a counter wrap.
15810 + */
15811 + write_c0_count(0);
15812 + write_c0_compare(0xffff);
15813 +
15814 + if (!(hz = sb_cpu_clock(sbh)))
15815 + hz = 100000000;
15816 +
15817 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
15818 + (hz + 500000) / 1000000);
15819 +
15820 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
15821 + mips_hpt_frequency = hz / 2;
15822 +
15823 + /* Set watchdog interval in ms */
15824 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
15825 +
15826 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
15827 + if (watchdog > 0) {
15828 + if (watchdog < 3000)
15829 + watchdog = 3000;
15830 + }
15831 +
15832 + /* Set panic timeout in seconds */
15833 + panic_timeout = watchdog / 1000;
15834 +}
15835 +
15836 +static void
15837 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
15838 +{
15839 + /* Generic MIPS timer code */
15840 + timer_interrupt(irq, dev_id, regs);
15841 +
15842 + /* Set the watchdog timer to reset after the specified number of ms */
15843 + if (watchdog > 0)
15844 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
15845 +}
15846 +
15847 +static struct irqaction bcm947xx_timer_irqaction = {
15848 + bcm947xx_timer_interrupt,
15849 + SA_INTERRUPT,
15850 + 0,
15851 + "timer",
15852 + NULL,
15853 + NULL
15854 +};
15855 +
15856 +void __init
15857 +bcm947xx_timer_setup(struct irqaction *irq)
15858 +{
15859 + /* Enable the timer interrupt */
15860 + setup_irq(7, &bcm947xx_timer_irqaction);
15861 +}
15862 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
15863 --- linux.old/arch/mips/config-shared.in 2006-04-27 18:04:37.000000000 +0200
15864 +++ linux.dev/arch/mips/config-shared.in 2006-04-27 19:24:19.000000000 +0200
15865 @@ -208,6 +208,14 @@
15866 fi
15867 define_bool CONFIG_MIPS_RTC y
15868 fi
15869 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
15870 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
15871 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15872 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
15873 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
15874 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
15875 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
15876 +fi
15877 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
15878 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
15879 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
15880 @@ -229,6 +237,11 @@
15881 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
15882
15883 #
15884 +# Provide an option for a default kernel command line
15885 +#
15886 +string 'Default kernel command string' CONFIG_CMDLINE ""
15887 +
15888 +#
15889 # Select some configuration options automatically based on user selections.
15890 #
15891 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
15892 @@ -554,6 +567,12 @@
15893 define_bool CONFIG_SWAP_IO_SPACE_L y
15894 define_bool CONFIG_BOOT_ELF32 y
15895 fi
15896 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15897 + define_bool CONFIG_PCI y
15898 + define_bool CONFIG_NONCOHERENT_IO y
15899 + define_bool CONFIG_NEW_TIME_C y
15900 + define_bool CONFIG_NEW_IRQ y
15901 +fi
15902 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
15903 define_bool CONFIG_ARC32 y
15904 define_bool CONFIG_ARC_MEMORY y
15905 @@ -1042,7 +1062,11 @@
15906
15907 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
15908 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
15909 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
15910 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
15911 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
15912 +else
15913 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
15914 +fi
15915 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
15916 if [ "$CONFIG_KGDB" = "y" ]; then
15917 define_bool CONFIG_DEBUG_INFO y
15918 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
15919 --- linux.old/arch/mips/kernel/cpu-probe.c 2006-04-27 18:04:37.000000000 +0200
15920 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2006-04-27 19:24:19.000000000 +0200
15921 @@ -162,7 +162,7 @@
15922
15923 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
15924 {
15925 - switch (c->processor_id & 0xff00) {
15926 + switch (c->processor_id & PRID_IMP_MASK) {
15927 case PRID_IMP_R2000:
15928 c->cputype = CPU_R2000;
15929 c->isa_level = MIPS_CPU_ISA_I;
15930 @@ -172,7 +172,7 @@
15931 c->tlbsize = 64;
15932 break;
15933 case PRID_IMP_R3000:
15934 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
15935 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
15936 if (cpu_has_confreg())
15937 c->cputype = CPU_R3081E;
15938 else
15939 @@ -187,12 +187,12 @@
15940 break;
15941 case PRID_IMP_R4000:
15942 if (read_c0_config() & CONF_SC) {
15943 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15944 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15945 c->cputype = CPU_R4400PC;
15946 else
15947 c->cputype = CPU_R4000PC;
15948 } else {
15949 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
15950 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
15951 c->cputype = CPU_R4400SC;
15952 else
15953 c->cputype = CPU_R4000SC;
15954 @@ -438,7 +438,7 @@
15955 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
15956 {
15957 decode_config1(c);
15958 - switch (c->processor_id & 0xff00) {
15959 + switch (c->processor_id & PRID_IMP_MASK) {
15960 case PRID_IMP_4KC:
15961 c->cputype = CPU_4KC;
15962 c->isa_level = MIPS_CPU_ISA_M32;
15963 @@ -479,10 +479,10 @@
15964 {
15965 decode_config1(c);
15966 c->options |= MIPS_CPU_PREFETCH;
15967 - switch (c->processor_id & 0xff00) {
15968 + switch (c->processor_id & PRID_IMP_MASK) {
15969 case PRID_IMP_AU1_REV1:
15970 case PRID_IMP_AU1_REV2:
15971 - switch ((c->processor_id >> 24) & 0xff) {
15972 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
15973 case 0:
15974 c->cputype = CPU_AU1000;
15975 break;
15976 @@ -510,10 +510,34 @@
15977 }
15978 }
15979
15980 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
15981 +{
15982 + decode_config1(c);
15983 + c->options |= MIPS_CPU_PREFETCH;
15984 + switch (c->processor_id & PRID_IMP_MASK) {
15985 + case PRID_IMP_BCM4710:
15986 + c->cputype = CPU_BCM4710;
15987 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15988 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15989 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15990 + break;
15991 + case PRID_IMP_4KC:
15992 + case PRID_IMP_BCM3302:
15993 + c->cputype = CPU_BCM3302;
15994 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
15995 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
15996 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
15997 + break;
15998 + default:
15999 + c->cputype = CPU_UNKNOWN;
16000 + break;
16001 + }
16002 +}
16003 +
16004 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
16005 {
16006 decode_config1(c);
16007 - switch (c->processor_id & 0xff00) {
16008 + switch (c->processor_id & PRID_IMP_MASK) {
16009 case PRID_IMP_SB1:
16010 c->cputype = CPU_SB1;
16011 c->isa_level = MIPS_CPU_ISA_M64;
16012 @@ -535,7 +559,7 @@
16013 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
16014 {
16015 decode_config1(c);
16016 - switch (c->processor_id & 0xff00) {
16017 + switch (c->processor_id & PRID_IMP_MASK) {
16018 case PRID_IMP_SR71000:
16019 c->cputype = CPU_SR71000;
16020 c->isa_level = MIPS_CPU_ISA_M64;
16021 @@ -560,7 +584,7 @@
16022 c->cputype = CPU_UNKNOWN;
16023
16024 c->processor_id = read_c0_prid();
16025 - switch (c->processor_id & 0xff0000) {
16026 + switch (c->processor_id & PRID_COMP_MASK) {
16027
16028 case PRID_COMP_LEGACY:
16029 cpu_probe_legacy(c);
16030 @@ -571,6 +595,9 @@
16031 case PRID_COMP_ALCHEMY:
16032 cpu_probe_alchemy(c);
16033 break;
16034 + case PRID_COMP_BROADCOM:
16035 + cpu_probe_broadcom(c);
16036 + break;
16037 case PRID_COMP_SIBYTE:
16038 cpu_probe_sibyte(c);
16039 break;
16040 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
16041 --- linux.old/arch/mips/kernel/head.S 2006-04-27 18:04:37.000000000 +0200
16042 +++ linux.dev/arch/mips/kernel/head.S 2006-04-27 19:24:19.000000000 +0200
16043 @@ -28,12 +28,20 @@
16044 #include <asm/mipsregs.h>
16045 #include <asm/stackframe.h>
16046
16047 +#ifdef CONFIG_BCM4710
16048 +#undef eret
16049 +#define eret nop; nop; eret
16050 +#endif
16051 +
16052 .text
16053 + j kernel_entry
16054 + nop
16055 +
16056 /*
16057 * Reserved space for exception handlers.
16058 * Necessary for machines which link their kernels at KSEG0.
16059 */
16060 - .fill 0x400
16061 + .fill 0x3f4
16062
16063 /* The following two symbols are used for kernel profiling. */
16064 EXPORT(stext)
16065 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
16066 --- linux.old/arch/mips/kernel/proc.c 2006-04-27 18:04:37.000000000 +0200
16067 +++ linux.dev/arch/mips/kernel/proc.c 2006-04-27 19:24:19.000000000 +0200
16068 @@ -78,9 +78,10 @@
16069 [CPU_AU1550] "Au1550",
16070 [CPU_24K] "MIPS 24K",
16071 [CPU_AU1200] "Au1200",
16072 + [CPU_BCM4710] "BCM4710",
16073 + [CPU_BCM3302] "BCM3302",
16074 };
16075
16076 -
16077 static int show_cpuinfo(struct seq_file *m, void *v)
16078 {
16079 unsigned int version = current_cpu_data.processor_id;
16080 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
16081 --- linux.old/arch/mips/kernel/setup.c 2006-04-27 18:04:37.000000000 +0200
16082 +++ linux.dev/arch/mips/kernel/setup.c 2006-04-27 19:24:19.000000000 +0200
16083 @@ -493,6 +493,7 @@
16084 void swarm_setup(void);
16085 void hp_setup(void);
16086 void au1x00_setup(void);
16087 + void brcm_setup(void);
16088 void frame_info_init(void);
16089
16090 frame_info_init();
16091 @@ -691,6 +692,11 @@
16092 pmc_yosemite_setup();
16093 break;
16094 #endif
16095 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
16096 + case MACH_GROUP_BRCM:
16097 + brcm_setup();
16098 + break;
16099 +#endif
16100 default:
16101 panic("Unsupported architecture");
16102 }
16103 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
16104 --- linux.old/arch/mips/kernel/traps.c 2006-04-27 18:04:37.000000000 +0200
16105 +++ linux.dev/arch/mips/kernel/traps.c 2006-04-27 19:24:19.000000000 +0200
16106 @@ -920,6 +920,7 @@
16107 void __init trap_init(void)
16108 {
16109 extern char except_vec1_generic;
16110 + extern char except_vec2_generic;
16111 extern char except_vec3_generic, except_vec3_r4000;
16112 extern char except_vec_ejtag_debug;
16113 extern char except_vec4;
16114 @@ -927,6 +928,7 @@
16115
16116 /* Copy the generic exception handler code to it's final destination. */
16117 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
16118 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
16119
16120 /*
16121 * Setup default vectors
16122 @@ -985,6 +987,12 @@
16123 set_except_vector(13, handle_tr);
16124 set_except_vector(22, handle_mdmx);
16125
16126 + if (current_cpu_data.cputype == CPU_SB1) {
16127 + /* Enable timer interrupt and scd mapped interrupt */
16128 + clear_c0_status(0xf000);
16129 + set_c0_status(0xc00);
16130 + }
16131 +
16132 if (cpu_has_fpu && !cpu_has_nofpuex)
16133 set_except_vector(15, handle_fpe);
16134
16135 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
16136 --- linux.old/arch/mips/mm/c-r4k.c 2006-04-27 18:04:37.000000000 +0200
16137 +++ linux.dev/arch/mips/mm/c-r4k.c 2006-04-27 19:24:19.000000000 +0200
16138 @@ -1166,3 +1166,47 @@
16139 build_clear_page();
16140 build_copy_page();
16141 }
16142 +
16143 +#ifdef CONFIG_BCM4704
16144 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
16145 +{
16146 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
16147 + int i;
16148 + for (i = 0; i < nbytes; i += ic_lsize)
16149 + fill_icache_line((addr + i));
16150 +}
16151 +
16152 +/*
16153 + * This must be run from the cache on 4704A0
16154 + * so there are no mips core BIU ops in progress
16155 + * when the PFC is enabled.
16156 + */
16157 +#define PFC_CR0 0xff400000 /* control reg 0 */
16158 +#define PFC_CR1 0xff400004 /* control reg 1 */
16159 +static void __init enable_pfc(u32 mode)
16160 +{
16161 + /* write range */
16162 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
16163 +
16164 + /* enable */
16165 + *(volatile u32 *)PFC_CR0 = mode;
16166 +}
16167 +#endif
16168 +
16169 +
16170 +void check_enable_mips_pfc(int val)
16171 +{
16172 +
16173 +#ifdef CONFIG_BCM4704
16174 + struct cpuinfo_mips *c = &current_cpu_data;
16175 +
16176 + /* enable prefetch cache */
16177 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
16178 + && (read_c0_diag() & (1 << 29))) {
16179 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
16180 + enable_pfc(val);
16181 + }
16182 +#endif
16183 +}
16184 +
16185 +
16186 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
16187 --- linux.old/arch/mips/pci/Makefile 2006-04-27 18:04:37.000000000 +0200
16188 +++ linux.dev/arch/mips/pci/Makefile 2006-04-27 19:24:19.000000000 +0200
16189 @@ -13,7 +13,9 @@
16190 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
16191 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
16192 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
16193 +ifndef CONFIG_BCM947XX
16194 obj-y += pci.o
16195 +endif
16196 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
16197
16198 include $(TOPDIR)/Rules.make
16199 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
16200 --- linux.old/drivers/char/serial.c 2006-04-27 18:04:37.000000000 +0200
16201 +++ linux.dev/drivers/char/serial.c 2006-04-27 19:24:19.000000000 +0200
16202 @@ -444,6 +444,10 @@
16203 return inb(info->port+1);
16204 #endif
16205 case SERIAL_IO_MEM:
16206 +#ifdef CONFIG_BCM4310
16207 + readb((unsigned long) info->iomem_base +
16208 + (UART_SCR<<info->iomem_reg_shift));
16209 +#endif
16210 return readb((unsigned long) info->iomem_base +
16211 (offset<<info->iomem_reg_shift));
16212 default:
16213 @@ -464,6 +468,9 @@
16214 case SERIAL_IO_MEM:
16215 writeb(value, (unsigned long) info->iomem_base +
16216 (offset<<info->iomem_reg_shift));
16217 +#ifdef CONFIG_BCM4704
16218 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
16219 +#endif
16220 break;
16221 default:
16222 outb(value, info->port+offset);
16223 @@ -1728,7 +1735,7 @@
16224 /* Special case since 134 is really 134.5 */
16225 quot = (2*baud_base / 269);
16226 else if (baud)
16227 - quot = baud_base / baud;
16228 + quot = (baud_base + (baud / 2)) / baud;
16229 }
16230 /* If the quotient is zero refuse the change */
16231 if (!quot && old_termios) {
16232 @@ -1745,12 +1752,12 @@
16233 /* Special case since 134 is really 134.5 */
16234 quot = (2*baud_base / 269);
16235 else if (baud)
16236 - quot = baud_base / baud;
16237 + quot = (baud_base + (baud / 2)) / baud;
16238 }
16239 }
16240 /* As a last resort, if the quotient is zero, default to 9600 bps */
16241 if (!quot)
16242 - quot = baud_base / 9600;
16243 + quot = (baud_base + 4800) / 9600;
16244 /*
16245 * Work around a bug in the Oxford Semiconductor 952 rev B
16246 * chip which causes it to seriously miscalculate baud rates
16247 @@ -5994,6 +6001,13 @@
16248 * Divisor, bytesize and parity
16249 */
16250 state = rs_table + co->index;
16251 + /*
16252 + * Safe guard: state structure must have been initialized
16253 + */
16254 + if (state->iomem_base == NULL) {
16255 + printk("!unable to setup serial console!\n");
16256 + return -1;
16257 + }
16258 if (doflow)
16259 state->flags |= ASYNC_CONS_FLOW;
16260 info = &async_sercons;
16261 @@ -6007,7 +6021,7 @@
16262 info->io_type = state->io_type;
16263 info->iomem_base = state->iomem_base;
16264 info->iomem_reg_shift = state->iomem_reg_shift;
16265 - quot = state->baud_base / baud;
16266 + quot = (state->baud_base + (baud / 2)) / baud;
16267 cval = cflag & (CSIZE | CSTOPB);
16268 #if defined(__powerpc__) || defined(__alpha__)
16269 cval >>= 8;
16270 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
16271 --- linux.old/drivers/net/Makefile 2006-04-27 18:04:38.000000000 +0200
16272 +++ linux.dev/drivers/net/Makefile 2006-05-04 01:41:03.000000000 +0200
16273 @@ -3,6 +3,8 @@
16274 # Makefile for the Linux network (ethercard) device drivers.
16275 #
16276
16277 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
16278 +
16279 obj-y :=
16280 obj-m :=
16281 obj-n :=
16282 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
16283 --- linux.old/drivers/parport/Config.in 2006-04-27 18:04:38.000000000 +0200
16284 +++ linux.dev/drivers/parport/Config.in 2006-04-27 19:24:19.000000000 +0200
16285 @@ -11,6 +11,7 @@
16286 tristate 'Parallel port support' CONFIG_PARPORT
16287 if [ "$CONFIG_PARPORT" != "n" ]; then
16288 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
16289 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
16290 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
16291 if [ "$CONFIG_SERIAL" = "m" ]; then
16292 define_tristate CONFIG_PARPORT_PC_CML1 m
16293 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
16294 --- linux.old/drivers/parport/Makefile 2006-04-27 18:04:38.000000000 +0200
16295 +++ linux.dev/drivers/parport/Makefile 2006-04-27 19:24:19.000000000 +0200
16296 @@ -22,6 +22,7 @@
16297
16298 obj-$(CONFIG_PARPORT) += parport.o
16299 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
16300 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
16301 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
16302 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
16303 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
16304 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
16305 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
16306 +++ linux.dev/drivers/parport/parport_splink.c 2006-04-27 19:24:19.000000000 +0200
16307 @@ -0,0 +1,345 @@
16308 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
16309 + *
16310 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
16311 + * Based on parport_pc source
16312 + */
16313 +
16314 +#include <linux/config.h>
16315 +#include <linux/module.h>
16316 +#include <linux/init.h>
16317 +#include <linux/ioport.h>
16318 +#include <linux/kernel.h>
16319 +#include <linux/slab.h>
16320 +#include <linux/parport.h>
16321 +#include <linux/parport_pc.h>
16322 +
16323 +#define SPLINK_ADDRESS 0xBF800010
16324 +
16325 +#undef DEBUG
16326 +
16327 +#ifdef DEBUG
16328 +#define DPRINTK printk
16329 +#else
16330 +#define DPRINTK(stuff...)
16331 +#endif
16332 +
16333 +
16334 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
16335 + * it doesn't do any extra masking. */
16336 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
16337 + unsigned char mask,
16338 + unsigned char val)
16339 +{
16340 + struct parport_pc_private *priv = p->physport->private_data;
16341 + unsigned char *io = (unsigned char *) p->base;
16342 + unsigned char ctr = priv->ctr;
16343 +#ifdef DEBUG_PARPORT
16344 + printk (KERN_DEBUG
16345 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
16346 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
16347 +#endif
16348 + ctr = (ctr & ~mask) ^ val;
16349 + ctr &= priv->ctr_writable; /* only write writable bits. */
16350 + *(io+2) = ctr;
16351 + priv->ctr = ctr; /* Update soft copy */
16352 + return ctr;
16353 +}
16354 +
16355 +
16356 +
16357 +static void parport_splink_data_forward (struct parport *p)
16358 +{
16359 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16360 + __parport_splink_frob_control (p, 0x20, 0);
16361 +}
16362 +
16363 +static void parport_splink_data_reverse (struct parport *p)
16364 +{
16365 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
16366 + __parport_splink_frob_control (p, 0x20, 0x20);
16367 +}
16368 +
16369 +/*
16370 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
16371 +{
16372 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
16373 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
16374 +}
16375 +*/
16376 +
16377 +static void parport_splink_enable_irq(struct parport *p)
16378 +{
16379 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
16380 + __parport_splink_frob_control (p, 0x10, 0x10);
16381 +}
16382 +
16383 +static void parport_splink_disable_irq(struct parport *p)
16384 +{
16385 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
16386 + __parport_splink_frob_control (p, 0x10, 0);
16387 +}
16388 +
16389 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
16390 +{
16391 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
16392 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
16393 + if (dev->irq_func &&
16394 + dev->port->irq != PARPORT_IRQ_NONE)
16395 + /* Set ackIntEn */
16396 + s->u.pc.ctr |= 0x10;
16397 +}
16398 +
16399 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
16400 +{
16401 + const struct parport_pc_private *priv = p->physport->private_data;
16402 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
16403 + s->u.pc.ctr = priv->ctr;
16404 +}
16405 +
16406 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
16407 +{
16408 + struct parport_pc_private *priv = p->physport->private_data;
16409 + unsigned char *io = (unsigned char *) p->base;
16410 + unsigned char ctr = s->u.pc.ctr;
16411 +
16412 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
16413 + *(io+2) = ctr;
16414 + priv->ctr = ctr;
16415 +}
16416 +
16417 +static void parport_splink_setup_interrupt(void) {
16418 + return;
16419 +}
16420 +
16421 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
16422 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
16423 + unsigned char *io = (unsigned char *) p->base;
16424 + *io = d;
16425 +}
16426 +
16427 +static unsigned char parport_splink_read_data(struct parport *p) {
16428 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
16429 + unsigned char *io = (unsigned char *) p->base;
16430 + return *io;
16431 +}
16432 +
16433 +static void parport_splink_write_control(struct parport *p, unsigned char d)
16434 +{
16435 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16436 + PARPORT_CONTROL_AUTOFD |
16437 + PARPORT_CONTROL_INIT |
16438 + PARPORT_CONTROL_SELECT);
16439 +
16440 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
16441 + /* Take this out when drivers have adapted to the newer interface. */
16442 + if (d & 0x20) {
16443 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
16444 + p->name, p->cad->name);
16445 + parport_splink_data_reverse (p);
16446 + }
16447 +
16448 + __parport_splink_frob_control (p, wm, d & wm);
16449 +}
16450 +
16451 +static unsigned char parport_splink_read_control(struct parport *p)
16452 +{
16453 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16454 + PARPORT_CONTROL_AUTOFD |
16455 + PARPORT_CONTROL_INIT |
16456 + PARPORT_CONTROL_SELECT);
16457 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
16458 + const struct parport_pc_private *priv = p->physport->private_data;
16459 + return priv->ctr & wm; /* Use soft copy */
16460 +}
16461 +
16462 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
16463 + unsigned char val)
16464 +{
16465 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
16466 + PARPORT_CONTROL_AUTOFD |
16467 + PARPORT_CONTROL_INIT |
16468 + PARPORT_CONTROL_SELECT);
16469 +
16470 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
16471 + /* Take this out when drivers have adapted to the newer interface. */
16472 + if (mask & 0x20) {
16473 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
16474 + p->name, p->cad->name,
16475 + (val & 0x20) ? "reverse" : "forward");
16476 + if (val & 0x20)
16477 + parport_splink_data_reverse (p);
16478 + else
16479 + parport_splink_data_forward (p);
16480 + }
16481 +
16482 + /* Restrict mask and val to control lines. */
16483 + mask &= wm;
16484 + val &= wm;
16485 +
16486 + return __parport_splink_frob_control (p, mask, val);
16487 +}
16488 +
16489 +static unsigned char parport_splink_read_status(struct parport *p)
16490 +{
16491 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
16492 + unsigned char *io = (unsigned char *) p->base;
16493 + return *(io+1);
16494 +}
16495 +
16496 +static void parport_splink_inc_use_count(void)
16497 +{
16498 +#ifdef MODULE
16499 + MOD_INC_USE_COUNT;
16500 +#endif
16501 +}
16502 +
16503 +static void parport_splink_dec_use_count(void)
16504 +{
16505 +#ifdef MODULE
16506 + MOD_DEC_USE_COUNT;
16507 +#endif
16508 +}
16509 +
16510 +static struct parport_operations parport_splink_ops =
16511 +{
16512 + parport_splink_write_data,
16513 + parport_splink_read_data,
16514 +
16515 + parport_splink_write_control,
16516 + parport_splink_read_control,
16517 + parport_splink_frob_control,
16518 +
16519 + parport_splink_read_status,
16520 +
16521 + parport_splink_enable_irq,
16522 + parport_splink_disable_irq,
16523 +
16524 + parport_splink_data_forward,
16525 + parport_splink_data_reverse,
16526 +
16527 + parport_splink_init_state,
16528 + parport_splink_save_state,
16529 + parport_splink_restore_state,
16530 +
16531 + parport_splink_inc_use_count,
16532 + parport_splink_dec_use_count,
16533 +
16534 + parport_ieee1284_epp_write_data,
16535 + parport_ieee1284_epp_read_data,
16536 + parport_ieee1284_epp_write_addr,
16537 + parport_ieee1284_epp_read_addr,
16538 +
16539 + parport_ieee1284_ecp_write_data,
16540 + parport_ieee1284_ecp_read_data,
16541 + parport_ieee1284_ecp_write_addr,
16542 +
16543 + parport_ieee1284_write_compat,
16544 + parport_ieee1284_read_nibble,
16545 + parport_ieee1284_read_byte,
16546 +};
16547 +
16548 +/* --- Initialisation code -------------------------------- */
16549 +
16550 +static struct parport *parport_splink_probe_port (unsigned long int base)
16551 +{
16552 + struct parport_pc_private *priv;
16553 + struct parport_operations *ops;
16554 + struct parport *p;
16555 +
16556 + if (check_mem_region(base, 3)) {
16557 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
16558 + return NULL;
16559 + }
16560 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
16561 + if (!priv) {
16562 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
16563 + return NULL;
16564 + }
16565 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
16566 + if (!ops) {
16567 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
16568 + base);
16569 + kfree (priv);
16570 + return NULL;
16571 + }
16572 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
16573 + priv->ctr = 0xc;
16574 + priv->ctr_writable = 0xff;
16575 +
16576 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
16577 + PARPORT_DMA_NONE, ops))) {
16578 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
16579 + base);
16580 + kfree (priv);
16581 + kfree (ops);
16582 + return NULL;
16583 + }
16584 +
16585 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
16586 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
16587 + p->private_data = priv;
16588 +
16589 + parport_proc_register(p);
16590 + request_mem_region (p->base, 3, p->name);
16591 +
16592 + /* Done probing. Now put the port into a sensible start-up state. */
16593 + parport_splink_write_data(p, 0);
16594 + parport_splink_data_forward (p);
16595 +
16596 + /* Now that we've told the sharing engine about the port, and
16597 + found out its characteristics, let the high-level drivers
16598 + know about it. */
16599 + parport_announce_port (p);
16600 +
16601 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
16602 + base);
16603 + return p;
16604 +}
16605 +
16606 +static void parport_splink_unregister_port(struct parport *p) {
16607 + struct parport_pc_private *priv = p->private_data;
16608 + struct parport_operations *ops = p->ops;
16609 +
16610 + if (p->irq != PARPORT_IRQ_NONE)
16611 + free_irq(p->irq, p);
16612 + release_mem_region(p->base, 3);
16613 + parport_proc_unregister(p);
16614 + kfree (priv);
16615 + parport_unregister_port(p);
16616 + kfree (ops);
16617 +}
16618 +
16619 +
16620 +int parport_splink_init(void)
16621 +{
16622 + int ret;
16623 +
16624 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
16625 + parport_splink_setup_interrupt();
16626 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
16627 +
16628 + return ret;
16629 +}
16630 +
16631 +void parport_splink_cleanup(void) {
16632 + struct parport *p = parport_enumerate(), *tmp;
16633 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
16634 + if (p->size) {
16635 + if (p->modes & PARPORT_MODE_PCSPP) {
16636 + while(p) {
16637 + tmp = p->next;
16638 + parport_splink_unregister_port(p);
16639 + p = tmp;
16640 + }
16641 + }
16642 + }
16643 +}
16644 +
16645 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
16646 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
16647 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
16648 +MODULE_LICENSE("GPL");
16649 +
16650 +module_init(parport_splink_init)
16651 +module_exit(parport_splink_cleanup)
16652 +
16653 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
16654 --- linux.old/include/asm-mips/bootinfo.h 2006-04-27 18:04:38.000000000 +0200
16655 +++ linux.dev/include/asm-mips/bootinfo.h 2006-04-27 19:24:19.000000000 +0200
16656 @@ -37,6 +37,7 @@
16657 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
16658 #define MACH_GROUP_LASAT 21
16659 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
16660 +#define MACH_GROUP_BRCM 23 /* Broadcom */
16661
16662 /*
16663 * Valid machtype values for group unknown (low order halfword of mips_machtype)
16664 @@ -197,6 +198,15 @@
16665 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
16666
16667 /*
16668 + * Valid machtypes for group Broadcom
16669 + */
16670 +#define MACH_BCM93725 0
16671 +#define MACH_BCM93725_VJ 1
16672 +#define MACH_BCM93730 2
16673 +#define MACH_BCM947XX 3
16674 +#define MACH_BCM933XX 4
16675 +
16676 +/*
16677 * Valid machtype for group TITAN
16678 */
16679 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
16680 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
16681 --- linux.old/include/asm-mips/cpu.h 2006-04-27 18:04:38.000000000 +0200
16682 +++ linux.dev/include/asm-mips/cpu.h 2006-04-27 19:24:19.000000000 +0200
16683 @@ -22,6 +22,11 @@
16684 spec.
16685 */
16686
16687 +#define PRID_COPT_MASK 0xff000000
16688 +#define PRID_COMP_MASK 0x00ff0000
16689 +#define PRID_IMP_MASK 0x0000ff00
16690 +#define PRID_REV_MASK 0x000000ff
16691 +
16692 #define PRID_COMP_LEGACY 0x000000
16693 #define PRID_COMP_MIPS 0x010000
16694 #define PRID_COMP_BROADCOM 0x020000
16695 @@ -58,6 +63,7 @@
16696 #define PRID_IMP_RM7000 0x2700
16697 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
16698 #define PRID_IMP_RM9000 0x3400
16699 +#define PRID_IMP_BCM4710 0x4000
16700 #define PRID_IMP_R5432 0x5400
16701 #define PRID_IMP_R5500 0x5500
16702 #define PRID_IMP_4KC 0x8000
16703 @@ -66,10 +72,16 @@
16704 #define PRID_IMP_4KEC 0x8400
16705 #define PRID_IMP_4KSC 0x8600
16706 #define PRID_IMP_25KF 0x8800
16707 +#define PRID_IMP_BCM3302 0x9000
16708 +#define PRID_IMP_BCM3303 0x9100
16709 #define PRID_IMP_24K 0x9300
16710
16711 #define PRID_IMP_UNKNOWN 0xff00
16712
16713 +#define BCM330X(id) \
16714 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
16715 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
16716 +
16717 /*
16718 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
16719 */
16720 @@ -174,7 +186,9 @@
16721 #define CPU_AU1550 57
16722 #define CPU_24K 58
16723 #define CPU_AU1200 59
16724 -#define CPU_LAST 59
16725 +#define CPU_BCM4710 60
16726 +#define CPU_BCM3302 61
16727 +#define CPU_LAST 61
16728
16729 /*
16730 * ISA Level encodings
16731 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
16732 --- linux.old/include/asm-mips/r4kcache.h 2006-04-27 18:04:38.000000000 +0200
16733 +++ linux.dev/include/asm-mips/r4kcache.h 2006-04-27 19:24:19.000000000 +0200
16734 @@ -658,4 +658,17 @@
16735 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
16736 }
16737
16738 +extern inline void fill_icache_line(unsigned long addr)
16739 +{
16740 + __asm__ __volatile__(
16741 + ".set noreorder\n\t"
16742 + ".set mips3\n\t"
16743 + "cache %1, (%0)\n\t"
16744 + ".set mips0\n\t"
16745 + ".set reorder"
16746 + :
16747 + : "r" (addr),
16748 + "i" (Fill));
16749 +}
16750 +
16751 #endif /* __ASM_R4KCACHE_H */
16752 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
16753 --- linux.old/include/asm-mips/serial.h 2006-04-27 18:04:38.000000000 +0200
16754 +++ linux.dev/include/asm-mips/serial.h 2006-04-27 19:24:19.000000000 +0200
16755 @@ -223,6 +223,13 @@
16756 #define TXX927_SERIAL_PORT_DEFNS
16757 #endif
16758
16759 +#ifdef CONFIG_BCM947XX
16760 +/* reserve 4 ports to be configured at runtime */
16761 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
16762 +#else
16763 +#define BCM947XX_SERIAL_PORT_DEFNS
16764 +#endif
16765 +
16766 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
16767 #define STD_SERIAL_PORT_DEFNS \
16768 /* UART CLK PORT IRQ FLAGS */ \
16769 @@ -470,6 +477,7 @@
16770 #define SERIAL_PORT_DFNS \
16771 ATLAS_SERIAL_PORT_DEFNS \
16772 AU1000_SERIAL_PORT_DEFNS \
16773 + BCM947XX_SERIAL_PORT_DEFNS \
16774 COBALT_SERIAL_PORT_DEFNS \
16775 DDB5477_SERIAL_PORT_DEFNS \
16776 EV96100_SERIAL_PORT_DEFNS \
16777 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
16778 --- linux.old/init/do_mounts.c 2006-04-27 18:04:38.000000000 +0200
16779 +++ linux.dev/init/do_mounts.c 2006-04-27 19:24:19.000000000 +0200
16780 @@ -254,7 +254,13 @@
16781 { "ftlb", 0x2c08 },
16782 { "ftlc", 0x2c10 },
16783 { "ftld", 0x2c18 },
16784 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
16785 { "mtdblock", 0x1f00 },
16786 + { "mtdblock0",0x1f00 },
16787 + { "mtdblock1",0x1f01 },
16788 + { "mtdblock2",0x1f02 },
16789 + { "mtdblock3",0x1f03 },
16790 +#endif
16791 { "nb", 0x2b00 },
16792 { NULL, 0 }
16793 };
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