finally move buildroot-ng to trunk
[openwrt/staging/dedeckeh.git] / target / linux / ar7-2.4 / patches / 004-atm_driver.patch
1 diff -urN linux.old/drivers/atm/Config.in linux.dev/drivers/atm/Config.in
2 --- linux.old/drivers/atm/Config.in 2005-08-22 23:18:37.773532032 +0200
3 +++ linux.dev/drivers/atm/Config.in 2005-08-23 04:46:50.076846888 +0200
4 @@ -99,4 +99,10 @@
5 bool 'Use S/UNI PHY driver' CONFIG_ATM_HE_USE_SUNI
6 fi
7 fi
8 +#
9 +# Texas Instruments SANGAM ADSL/ATM support
10 +#
11 +if [ "$CONFIG_AR7" = "y" ]; then
12 + tristate 'Texas Instruments SANGAM ATM/ADSL support' CONFIG_MIPS_SANGAM_ATM
13 +fi
14 endmenu
15 diff -urN linux.old/drivers/atm/Makefile linux.dev/drivers/atm/Makefile
16 --- linux.old/drivers/atm/Makefile 2005-08-22 23:18:37.773532032 +0200
17 +++ linux.dev/drivers/atm/Makefile 2005-08-23 04:46:50.077846736 +0200
18 @@ -14,6 +14,32 @@
19 obj-$(CONFIG_ATM_NICSTAR) += nicstar.o
20 obj-$(CONFIG_ATM_IDT77252) += idt77252.o
21
22 +ifeq ($(CONFIG_AR7),y)
23 +
24 +subdir-$(CONFIG_MIPS_SANGAM_ATM) += sangam_atm
25 +
26 +EXTRA_CFLAGS += -DEL -I$(TOPDIR)/drivers/atm/sangam_atm -DPOST_SILICON -DCOMMON_NSP -DCONFIG_LED_MODULE -DDEREGISTER_LED -DNO_ACT
27 +#EXTRA_CFLAGS += -DEL -I$(TOPDIR)/drivers/atm/sangam_atm -DPOST_SILICON -DCOMMON_NSP
28 +
29 +ifeq ($(ANNEX),B)
30 +EXTRA_CFLAGS += -DANNEX_B -DB
31 +else
32 +ifeq ($(ANNEX),C)
33 +EXTRA_CFLAGS += -DANNEX_C -DC
34 +else
35 +EXTRA_CFLAGS += -DANNEX_A -DP
36 +endif
37 +endif
38 +
39 +list-multi := tiatm.o
40 +tiatm-objs := sangam_atm/tn7atm.o sangam_atm/tn7dsl.o sangam_atm/tn7sar.o \
41 + sangam_atm/dsl_hal_api.o sangam_atm/dsl_hal_support.o sangam_atm/cpsar.o \
42 + sangam_atm/aal5sar.o
43 +
44 +obj-$(CONFIG_MIPS_SANGAM_ATM) += sangam_atm/tiatm.o
45 +
46 +endif
47 +
48 ifeq ($(CONFIG_ATM_NICSTAR_USE_SUNI),y)
49 obj-$(CONFIG_ATM_NICSTAR) += suni.o
50 endif
51 diff -urN linux.old/drivers/atm/sangam_atm/aal5sar.c linux.dev/drivers/atm/sangam_atm/aal5sar.c
52 --- linux.old/drivers/atm/sangam_atm/aal5sar.c 1970-01-01 01:00:00.000000000 +0100
53 +++ linux.dev/drivers/atm/sangam_atm/aal5sar.c 2005-08-23 04:46:50.080846280 +0200
54 @@ -0,0 +1,2962 @@
55 +
56 +/**
57 + *
58 + * aal5sar.c
59 + *
60 + * TNETDxxxx Software Support\n
61 + * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
62 + *
63 + * version
64 + * 28Feb02 Greg 1.00 Original Version created.\n
65 + * 06Mar02 Greg 1.01 Documentation (Doxygen-style) enhanced
66 + * 06May02 Greg 1.02 AAL2 added
67 + * 06Jun02 Greg 1.03 Multiple API and bug fixes from emulation
68 + * 12Jul02 Greg 1.04 API Update
69 + */
70 +
71 +/**
72 +@defgroup CPHAL_Functions CPHAL Functions
73 +
74 +These are the CPHAL Functions.
75 +*/
76 +
77 +/**
78 +@page CPHAL_Implementation_Details
79 +
80 +@section cphal_intro Introduction
81 +
82 +The CPHAL API described above is generally applicable to all modules. Any
83 +implementation differences will be described in the following module-specific
84 +appendix sections.
85 +
86 +Included for your reference is a diagram showing the internal architecture
87 +of the CPHAL:
88 +
89 +@image html SangamSoftware.jpg "HAL Architecture"
90 +@image latex SangamSoftware.jpg "HAL Architecture" height=2.8in
91 +
92 +*/
93 +
94 +/**
95 +@defgroup AAL5_Functions Additional Functions for AAL5 Implementation
96 +
97 +These functions are used only by the AAL5 module.
98 +*/
99 +
100 +/*
101 +@defgroup CPMAC_Functions Additional Functions for CPMAC Implementation
102 +
103 +No additional functions currently defined.
104 +*/
105 +
106 +/**
107 +@page VDMA_Implementation_Details
108 +
109 +@section vdma_intro Introduction
110 +
111 +The VDMA-VT module facilitates efficient transfer of data (especially voice)
112 +between two devices, as shown in the figure below.
113 +
114 +@image html vdma.jpg "VDMA System Block Diagram"
115 +@image latex vdma.jpg "VDMA System Block Diagram" height=1in
116 +
117 +The VDMA-VT module supports two modes of operation: mirror mode and credit mode.
118 +Mirror mode is intended for systems in which the remote device does not have a
119 +VDMA-based module. Credit mode is intended for highest performance when VDMA-based
120 +modules exist on both ends of an interface.
121 +
122 +For more detailed information on the operation of the VDMA module, please
123 +reference the VDMA Module Guide.
124 +
125 +@section vdma_channels VDMA Channels
126 +
127 +The VDMA-VT module is a single channel, single transmit queue device. Therefore,
128 +when using the CHANNEL_INFO structure, the correct value for @c Ch is always 0.
129 +Correspondingly, the correct value for the @c Ch parameter in @c ChannelTeardown() is
130 +always 0. Further, when calling @c Send(), the driver should always supply the value
131 +of 0 for both the @c Ch and @c Queue parameters.
132 +
133 +For the VDMA-VT, configuring the channel requires the configuration of either 2 FIFO
134 +elements (in credit mode) or 4 FIFO elements (in mirror mode). For credit mode, the
135 +driver must configure just the local Tx and Rx FIFOs. For mirror mode, the driver must
136 +configure the Tx and Rx FIFOs for both the remote and local ends of the interface.
137 +
138 +This channel configuration is accomplished through multiple calls to @c ChannelSetup().
139 +Each call configures a single FIFO, according to the parameters in the CHANNEL_INFO
140 +structure. The members of VDMA-VT's CHANNEL_INFO structure are defined below.
141 +
142 +
143 +- int RemFifoAddr; Address of remote FIFO (mirror mode only). Set to 0 for credit mode.
144 +- int FifoAddr; Address of the local FIFO. If 0, the CPHAL will allocate the FIFO.
145 +- int FifoSize; Size of the FIFO.
146 +- int PollInt; Polling interval for the FIFO.
147 +- int Endianness; Endianness of the FIFO. If 1, big endian. If 0, little endian.
148 +- int RemAddr; Used only in credit mode. This is the base address of the remote
149 + remote VDMA-based device (VDMA-VT or AAL2)
150 +- int RemDevID; Used only in credit mode. Identifies the type of remote VDMA-based device.
151 + 0=VDMAVT, 1=AAL2 Ch0, 2=AAL2 Ch1, 3=AAL2 Ch2, 4= AAL2 Ch3.
152 +
153 +For the VDMA-VT module, the driver must make all calls to @c ChannelSetup() prior to calling
154 +@c Open(). This is because several of the channel specific parameters may not be changed
155 +while the VDMA-VT module is operational.
156 +
157 +@section vdma_params VDMA Parameters
158 +
159 +Defined here are the set of parameters for the VDMA-VT module. Default settings for
160 +each parameter should be represented in the device configuration file (options.conf).
161 +During @c Init(), the CPHAL will reference the device configuration file and load all
162 +default settings. The @c Control() interface gives the driver an opportunity to
163 +modify any default settings before the module becomes operational during the @c Open()
164 +call.
165 +
166 +@param NoTxIndication If 1, the CPHAL will not call @c SendComplete(). 0 is default.
167 +@param NoRxIndication If 1, the CPHAL will not call @c Receive(). 0 is default.
168 +@param RemoteCPU If 1, the CPHAL will not directly manipulate data in FIFO's, leaving
169 + that task for a remote CPU. 0 is default.
170 +@param RxIntEn If 1, enables Rx interrupts. 0 is default.
171 +@param TxIntEn If 1, enables Tx interrupts. 0 is default.
172 +@param Mirror If 1, enables mirror mode. 0 selects credit mode (default).
173 +@param RxIntCtl Valid only in mirror mode. If 1, interrupts will occur when the Rx FIFO
174 + RdIndex is updated. If 0, interrupts occur when the Rx FIFO WrIndex
175 + is updated.
176 +@param TxIntCtl Valid only in mirror mode. If 1, interrupts will occur when the Rx FIFO
177 + RdIndex is updated. If 0, interrupts occur when the Rx FIFO WrIndex
178 + is updated.
179 +@param RBigEn Remote big endian mode. If 1, remote is big endian.
180 +@param LBigEn Local big endian mode. If 1, local is big endian.
181 +
182 +@section vdma_polling Using VDMA-VT without interrupts
183 +
184 +If your system configuration does not utilize VDMA interrupts, the ability to process the
185 +Tx and Rx FIFOs is supported. To process the Tx FIFO, call @c CheckTx(). If the CPHAL is
186 +able to process any complete data transmissions, it will call @c SendComplete() as usual.
187 +To process the Rx FIFO, call @c CheckRx(). If the CPHAL has received any data, it will
188 +call @c Receive() to pass the driver the data. Please reference @ref VDMA_Functions for more
189 +information on these interfaces.
190 +
191 +@section vdma_details VDMA Implementation Details
192 +
193 +The following functions are not defined for use with VDMA: @c Status(), @c Tick(), @c StatsGet(),
194 +and @c StatsClear().
195 +
196 +*/
197 +
198 +/**
199 +@page AAL5_Implementation_Details
200 +
201 +@section aal5_ver Version
202 +
203 +@copydoc AAL5_Version
204 +
205 +@section aal5_intro Introduction
206 +
207 +The AAL5 implementation will support 16 channels for transmit and 16 channels for
208 +receive. Each of the transmit channels may have up to two transmit queues
209 +associated with it. If two queues are used, Queue 0 is the high priority queue,
210 +and Queue 1 is the low priority queue.
211 +
212 +@section aal5_params AAL5 Configuration Parameters
213 +
214 +AAL5 requires two device entries to be available in the configuration repository, named
215 +@p "aal5" and @p "sar". The @p aal5 device entry must contain @p base (base address)
216 +and @p int_line (interrupt number). The @p sar device entry must have both @p base
217 +(base address) and @p reset_bit (reset bit).
218 +
219 +@par Device Level Configuration Parameters
220 +
221 +The following parameters are device-level parameters, which apply across all
222 +channels. The value for these parameters may be modified by changing the value in the
223 +configuration repository.
224 +
225 +- "UniNni":
226 +AAL5 network setting. 0 = UNI (default), 1 = NNI.
227 +
228 +@par Channel Configuration Parameters
229 +
230 +All AAL5 channel parameters may also be configured through the @c ChannelSetup() interface.
231 +Following is the list of @p CHANNEL_INFO members that may be modified by the driver when
232 +calling @c ChannelSetup(). The driver may provide a value of 0xFFFFFFFF for any channel
233 +parameter to select a default value for the parameter. The driver should at a minimum
234 +configure @p Vci and @p Vpi. The usage of all parameters beginning with TxVc_,
235 +TxVp_, RxVc_, RxVp_ is described in greater detail in the SAR Firmware Spec.
236 +These parameters are mainly associated with QoS and OAM functionality.
237 +
238 +- "RxNumBuffers":
239 +The number of Rx buffer descriptors to allocate for Ch.
240 +- "RxBufSize":
241 +Size (in bytes) for each Rx buffer.
242 +- "RxBufferOffset":
243 +Number of bytes to offset rx data from start of buffer (must be less than buffer size).
244 +- "RxServiceMax":
245 +Maximum number of packets to service at one time.
246 +- "TxNumBuffers":
247 +The number of Tx buffer descriptors to allocate for Ch.
248 +- "TxNumQueues":
249 +Number of Tx queues for this channel (1-2). Choosing 2 enables a low priority SAR queue.
250 +- "TxServiceMax":
251 +Maximum number of packets to service at one time.
252 +- "CpcsUU":
253 +The 2-byte CPCS UU and CPI information.
254 +- "Gfc":
255 +Generic Flow Control. Used in ATM header of Tx packets.
256 +- "Clp":
257 +Cell Loss Priority. Used in ATM header of Tx packets.
258 +- "Pti":
259 +Payload Type Indication. Used in ATM header of Tx packets.
260 +- "DaMask":
261 +Specifies whether credit issuance is paused when Tx data not available.
262 +- "Priority":
263 +Priority bin this channel will be scheduled within.
264 +- "PktType":
265 +0=AAL5,1=Null AAL,2=OAM,3=Transparent,4=AAL2.
266 +- "Vci":
267 +Virtual Channel Identifier.
268 +- "Vpi":
269 +Virtual Path Identifier.
270 +- "TxVc_AtmHeader":
271 +In firmware OAM mode, this
272 +is the ATM header to be appended to front of firmware generated VC OAM cells for
273 +this channel. Note: To generate host OAM cells, call @c Send() with
274 +the appropriate mode.
275 +- "TxVc_CellRate":
276 +Tx rate, set as clock ticks between transmissions (SCR for VBR, CBR for CBR).
277 +- "TxVc_QosType":
278 +0=CBR,1=VBR,2=UBR,3=UBRmcr.
279 +- "TxVc_Mbs":
280 +Min Burst Size in cells.
281 +- "TxVc_Pcr":
282 +Peak Cell Rate for VBR in clock ticks between transmissions.
283 +- "TxVc_OamTc":
284 +TC Path to transmit OAM cells for TX connections (0,1).
285 +- "TxVc_VpOffset":
286 +Offset to the OAM VP state table for TX connections. Channels with the same
287 +VPI must have the same VpOffset value. Channels with different VPIs
288 +must have unique VpOffset values.
289 +- "RxVc_OamCh":
290 +Channel to which to terminate received OAM cells to be forwarded to the Host
291 +for either Host OAM mode, or when RxVc_OamToHost is enabled during Firmware
292 +OAM mode.
293 +- "RxVc_OamToHost":
294 +Indicates whether to pass received unmatched OAM loopback cells to the host;
295 +0=do not pass, 1=pass.
296 +- "RxVc_AtmHeader":
297 +ATM Header placed on firmware gen'd OAM cells for this channel on a Rx
298 +connection (must be big endian with 0 PTI).
299 +- "RxVc_OamTc":
300 +TC Path to transmit OAM cells for RX connections (0,1).
301 +- "RxVc_VpOffset":
302 +Offset to the OAM VP state table for RX connections. Channels with the same
303 +VPI must have the same VpOffset value. Channels with different VPIs
304 +must have unique VpOffset values.
305 +- "TxVp_OamTc":
306 +TC Path to transmit OAM cells for TX VP connections (0,1).
307 +- "TxVp_AtmHeader":
308 +ATM Header placed on firmware gen'd VP OAM cells for this channel on a Tx VP
309 +connection (must be big endian with 0 VCI).
310 +- "RxVp_OamCh":
311 +Channel to which to terminate received OAM cells to be forwarded to the Host
312 +for either Host OAM mode, or when RxVc_OamToHost is enabled during Firmware
313 +OAM mode.
314 +- "RxVp_OamToHost":
315 +Indicates whether to pass received unmatched OAM loopback cells to the host;
316 +0=do not pass, 1=pass.
317 +- "RxVp_AtmHeader":
318 +In firmware OAM mode, this
319 +is the ATM header to be appended to front of firmware generated VP OAM cells for
320 +this channel. Note: To generate host OAM cells, call @c Send() with
321 +the appropriate mode.
322 +- "RxVp_OamTc":
323 +TC Path to transmit OAM cells for RX VP connections (0,1).
324 +- "RxVp_OamVcList":
325 +This 32-bit field is one-hot encoded to indicate all the VC channels that are
326 +associated with this VP channel. A value of 21 will indicate that VC
327 +channels 0, 2, and 4 are associated with this VP channel.
328 +- "FwdUnkVc":
329 +Indicates whether or not to forward unknown VCI/VPI cells to the host. This
330 +parameter only takes effect if the channel's PktType is Transparent(3).
331 +1=forwarding enabled, 0=forwarding disabled.
332 +
333 +@section aal5_details API Implementation Details
334 +
335 +ATTENTION: Documentation given here supplements the documentation given in the general
336 +CPHAL API section. The following details are crucial to correct usage of the
337 +AAL5 CPHAL.
338 +
339 +@par Receive()
340 +The least significant byte of @p Mode contains the channel number. Bit 31
341 +indicates whether or not the ATM header is present in the first fragment of
342 +the packet. If bit 31 is set, the 4 byte ATM header (minus HEC) will be provided
343 +in the first fragment, with the payload beginning in the second fragment. Currently,
344 +this is the default behavior for host OAM and transparent mode packets.
345 +Bits 17-16 indicate the packet type that is being received.
346 +Mode Parameter Breakdown: <BR>
347 +- 31 ATM Header In First Fragment (1=true, 0=false) <BR>
348 +- 30-18 Unused. <BR>
349 +- 17-16 Pkt Type. <BR>
350 + - 0=AAL5 <BR>
351 + - 1=PTI Based Null AAL <BR>
352 + - 2=OAM <BR>
353 + - 3=Transparent <BR>
354 +- 15-08 Unused. <BR>
355 +- 07-00 Channel Number.
356 +
357 +@par Send()
358 +The most significant 16 bits of the first fragment 'len' is used as the Offset
359 +to be added to the packet. @c Send() will reserve this many bytes at the
360 +beginning of the transmit buffer prior to the first byte of valid data.
361 +For the @p Mode parameter, Bit 31 must be set if the user has sent a packet with
362 +the ATM Header (minus HEC) embedded in the first 4 bytes of the first fragment data buffer.
363 +The OS has the option of using a 4 byte first fragment containing only ATM header,
364 +or concatenating the ATM Header in front of the data payload.
365 +If Bit 31 is set, the ATM Header in the buffer is preserved and sent with
366 +each cell of the packet. Otherwise, Send() will build the ATM header based on the
367 +values of the Pti, Gfc, Clp, Vpi, and Vci parameters for the given channel.
368 +Bits 17-16 are defined as the packet type. Bits 15-08 may be used to specify the
369 +transmit queue to send the packet on. Only values 0 (high priority) and 1 (low
370 +priority) are accepted. Bits 07-00 should be used to indicate the channel number
371 +for the @c Send() operation. Valid channel numbers are 0-15.
372 +Mode Parameter Breakdown: <BR>
373 +- 31 ATM Header In Packet (1=true, 0=false) <BR>
374 +- 30-18 Unused. <BR>
375 +- 17-16 Pkt Type. <BR>
376 + - 0=AAL5 <BR>
377 + - 1=PTI Based Null AAL <BR>
378 + - 2=OAM <BR>
379 + - 3=Transparent <BR>
380 +- 15-08 Transmit Queue. <BR>
381 +- 07-00 Channel Number.
382 +
383 +@par ChannelSetup()
384 +The AAL5 @c ChannelSetup() always configures both the Tx and Rx side of the channel
385 +connection in the same call.
386 +
387 +@par ChannelTeardown()
388 +Regardless of the channel teardown direction selected, the AAL5 CPHAL will always
389 +teardown both the Tx and Rx side of the channel connection.
390 +
391 +@par TeardownComplete()
392 +The value for the @p Direction parameter should be ignored for the AAL5 implementation,
393 +since both directions (Tx and Rx) are always torndown in response to a @c ChannelTeardown()
394 +command.
395 +
396 +@par Control() (HAL version)
397 +Defined keys and actions. Unless otherwise stated, the data type
398 +for Value is pointer to unsigned integer. The list is broken into
399 +three groups, one group which can be used anytime, one group that should
400 +be used before halOpen(), and one group which can only be used after
401 +halOpen() (but before halClose()). For channelized parameters, replace
402 +'Ch' with the integer number of a channel (ex. "Gfc.4" can be used to set
403 +Gfc for channel 4).
404 +
405 +MAY USE ANYTIME AFTER INIT (after halInit() is called):
406 +
407 +- "Gfc.Ch". The OS may "Set" this value. Changing this value causes
408 +the Gfc in each Tx ATM header for this channel to take on the new Gfc value.
409 +
410 +- "Clp.Ch". The OS may "Set" this value. Changing this value causes
411 +the Clp in each Tx ATM header for this channel to take on the new Clp value.
412 +
413 +- "Pti.Ch". The OS may "Set" this value. Changing this value causes
414 +the Pti in each Tx ATM header for this channel to take on the new Pti value.
415 +
416 +- "CpcsUU.Ch". The OS may "Set" this value. Changing this value causes
417 +the CpcsUU in each Tx ATM header for this channel to take on the new CpcsUU value.
418 +
419 +- "OamMode". Specifies if host or firmware is performing OAM functions; 0 = Host OAM,
420 +1 = Firmware OAM. When set, all SAR channels will be configured for
421 +the selection, including AAL2 channels.
422 +
423 +- "OamLbTimeout". Specifies the firmware OAM loopback timeout, in milliseconds.
424 +
425 +- "DeviceCPID". The OS may "Set" this value. This is the OAM connection
426 +point identifier. The OS should provide a pointer to an array of 4 32-bit
427 +integers. Each word must be configured in big endian format.
428 +
429 +- "FwdUnkVc.Ch". Indicates whether or not to forward unknown VCI/VPI cells to the host.
430 +This parameter only takes effect if the channel's PktType is Transparent(3).
431 +1=forwarding enabled, 0=forwarding disabled.
432 +
433 +MAY USE ONLY BEFORE HAL IS OPEN (before halOpen() call):
434 +- "StrictPriority". The OS may "Set" this value. Setting to 1 causes
435 +a different interrupt processing routine to be used, which gives strict
436 +priority to channels with lower numbers (channel 0 has highest priority).
437 +The default handler gives equal priority to all channels.
438 +
439 +- "MaxFrags". The OS may "Set" or "Get" this value. This defines the maximum
440 +number of fragments that can be received by the AAL5 Rx port. The default
441 +value for AAL5 is 46. This provides enough space to receive a maximum
442 +length AAL5 packet (65,568 bytes) with the default buffer size of 1518 bytes, and
443 +any amount of RxBufferOffset. If the buffer size is configured to be smaller,
444 +the OS *MUST* modify this parameter according to the following formula:
445 +((System Max AAL5 packet length)/(RxBufSize)) + 2. (The extra two fragments in
446 +the formula allow for RxBufferOffset and one fragment for the ATM Header, used
447 +when receiving host OAM or transparent mode packets)
448 +
449 +MAY USE ONLY AFTER HAL IS 'OPEN' (after halOpen() call):
450 +- "Stats;Level;Ch;Queue". The OS may "Get" Stats groups with this key, where
451 +'Level' is an integer from 0-4, Ch is an integer from 0-15, and Queue is
452 +an integer from 0-1. Note that Ch is not required for Level 4 stats, and Queue
453 +is not required for Level 0, 3, and 4. The statistics functionality and return
454 +value is described in the appendix entitled "Configuration and Control".
455 +
456 +- "TxVc_CellRate.Ch". The OS may "Set" this value. Can be used to modify
457 +CellRate for a channel on the fly.
458 +
459 +- "TxVc_Mbs.Ch". The OS may "Set" this value. Can be used to modify
460 +Mbs for a channel on the fly.
461 +
462 +- "TxVc_Pcr.Ch". The OS may "Set" this value. Can be used to modify
463 +Pcr for a channel on the fly.
464 +
465 +- "PdspEnable". The OS may "Set" this value. Value 0 disables the PDSP.
466 +Value 1 enables to PDSP.
467 +
468 +- "DeviceCPID". The OS may "Set" this value. The Value should be an array
469 +of 4 32-bit integers that comprise the CPID.
470 +
471 +- "RxVc_RDICount.Ch". The OS may "Get" or "Set" this value. Get returns
472 +the current RDI count for the VC channel. Set clears the counter, and the Value
473 +is ignored.
474 +
475 +- "RxVp_RDICount.Ch". The OS may "Get" or "Set" this value. Get returns
476 +the current RDI count for the VP channel. Set clears the counter, and the Value
477 +is ignored.
478 +
479 +- "RxVc_AISseg.Ch". The OS may "Get" this value. This is an indication of
480 +AIS segment error for the VC channel.
481 +
482 +- "RxVp_AISseg.Ch". The OS may "Get" this value. This is an indication of
483 +AIS segment error for the VP channel.
484 +
485 +- "RxVc_AISetoe.Ch". The OS may "Get" this value. This is an indication of
486 +AIS end-to-end error for the VC channel.
487 +
488 +- "RxVp_AISetoe.Ch". The OS may "Get" this value. This is an indication of
489 +AIS end-to-end error for the VP channel.
490 +
491 +- "RxVc_OamCh.Ch". The OS may "Set" this value. Channel to which to terminate
492 +received OAM cells to be forwarded to the Host for either Host OAM mode, or when
493 +RxVc_OamToHost is enabled during Firmware OAM mode.
494 +
495 +- "RxVp_OamCh.Ch". The OS may "Set" this value. Channel to which to terminate
496 +received OAM cells to be forwarded to the Host for either Host OAM mode, or when
497 +RxVp_OamToHost is enabled during Firmware OAM mode.
498 +
499 +- "F4_LB_Counter". The OS may "Get" this value. This is a count of the number
500 + of near-end F4 loopbacks performed by the PDSP in firmware OAM mode.
501 +
502 +- "F5_LB_Counter". The OS may "Get" this value. This is a count of the number
503 + of near-end F5 loopbacks performed by the PDSP in firmware OAM mode.
504 +
505 +- "TxVc_AtmHeader.Ch". The OS may "Set" this value. In firmware OAM mode, this
506 +is the ATM header to be appended to front of firmware generated VC OAM cells for
507 +this channel. In host OAM mode, this is used as the ATM header to be appended
508 +to front of host generated VC OAM cells for this channel. It must be configured
509 +as big endian with PTI=0. Note: To generate host OAM cells, call @c Send() with
510 +the appropriate mode.
511 +
512 +- "TxVp_AtmHeader.Ch". The OS may "Set" this value. In firmware OAM mode, this
513 +is the ATM header to be appended to front of firmware generated VP OAM cells for
514 +this channel. In host OAM mode, this is used as the ATM header to be appended
515 +to front of host generated VP OAM cells for this channel. It must be configured
516 +as big endian with VCI=0. Note: To generate host OAM cells, call @c Send() with
517 +the appropriate mode.
518 +
519 +- "PdspEnable". The OS may "Set" this value. Controls whether or not the PDSP is
520 +allowed to fetch new instructions. The PDSP is enabled by the CPHAL during Open(),
521 +and disabled during Close(). 0 = disabled, 1 = enabled.
522 +
523 +@par Control() (OS version)
524 +Defined keys and actions:
525 +
526 +- "Firmware". The CPHAL will perform a "Get" action for the key "Firmware". A pointer
527 +to a pointer is passed in @p Value. The OS must modify the referenced pointer to point
528 +to the firmware.
529 +
530 +- "FirmwareSize". The CPHAL will perform a "Get" action for the key "FirmwareSize".
531 +The OS must place the firmware size in the memory pointed at by @p Value.
532 +
533 +- "OamLbResult". When a channel that is in firmware OAM mode is commanded to perform
534 +a loopback function, the result of the loopback generates an interrupt that is handled
535 +by the OS like any other interrupt. The CPHAL, upon servicing the interrupt, will call
536 +osControl with this key, and an action of "Set". The @p Value parameter will be a
537 +pointer to the integer result. 1 = pass, 0 = fail.
538 +
539 +- "SarFreq". The CPHAL will perform a "Get" action for this key. The OS should place
540 +the SAR frequency (in Hz) in the memory pointed at by @p Value.
541 +
542 +@section aal5_stats AAL5 Specific Statistics
543 +
544 +Statistics level '0' contains all AAL5 specific statistics. The following values will
545 +be obtained when requesting stats level 0:
546 +
547 +- "Crc Errors". Number of CRC errors reported by SAR hardware. Incremented for received
548 +packets that contain CRC errors.
549 +
550 +- "Len Errors". Number of length errors reported by SAR hardware. Incremented for received
551 +packets that are in excess of 1366 cells.
552 +
553 +- "Abort Errors". Number of abort errors reported by SAR hardware.
554 +
555 +- "Starv Errors". Number of buffer starvation errors reported by SAR hardware. Incremented
556 +when a part or all of a buffer cannot be received due to lack of RX buffer resources. The SAR
557 +drops all cells associated with the packet for each buffer starvation error that occurs.
558 +
559 +*/
560 +
561 +/* register files */
562 +#include "cp_sar_reg.h"
563 +
564 +#define _CPHAL_AAL5
565 +#define _CPHAL
566 +#define _CPPI_TEST /** @todo remove for release */
567 +#define __CPHAL_CPPI_OFFSET /* support use of offset */
568 +
569 +/* OS Data Structure definitions */
570 +
571 +typedef void OS_PRIVATE;
572 +typedef void OS_DEVICE;
573 +typedef void OS_SENDINFO;
574 +typedef void OS_RECEIVEINFO;
575 +typedef void OS_SETUP;
576 +
577 +/* CPHAL Data Structure definitions */
578 +
579 +typedef struct hal_device HAL_DEVICE;
580 +typedef struct hal_private HAL_PRIVATE;
581 +typedef struct hal_private HAL_RECEIVEINFO;
582 +
583 +/* include CPHAL header files here */
584 +#include "cpcommon_cpaal5.h"
585 +#include "cpswhal_cpaal5.h"
586 +#include "aal5sar.h"
587 +#include "cpcommon_cpaal5.c"
588 +
589 +#define CR_SERVICE (170-1)
590 +#define UTOPIA_PAUSE_REG (*(volatile bit32u *)0xa4000000)
591 +
592 +/*
593 +these masks are for the mode parameter used in halSend/OsReceive
594 +(may move these elsewhere)
595 +*/
596 +#define CH_MASK 0xff
597 +#define PRI_MASK 0x10000
598 +
599 +/* Rcb/Tcb Constants */
600 +#define CB_SOF_BIT (1<<31)
601 +#define CB_EOF_BIT (1<<30)
602 +#define CB_SOF_AND_EOF_BIT (CB_SOF_BIT|CB_EOF_BIT)
603 +#define CB_OWNERSHIP_BIT (1<<29)
604 +#define CB_EOQ_BIT (1<<28)
605 +#define CB_SIZE_MASK 0x0000ffff
606 +#define CB_OFFSET_MASK 0xffff0000
607 +#define RCB_ERRORS_MASK 0x03fe0000
608 +#define RX_ERROR_MASK 0x000f0000
609 +#define CRC_ERROR_MASK 0x00010000
610 +#define LENGTH_ERROR_MASK 0x00020000
611 +#define ABORT_ERROR_MASK 0x00040000
612 +#define STARV_ERROR_MASK 0x00080000
613 +#define TEARDOWN_VAL 0xfffffffc
614 +
615 +/* interrupt vector masks */
616 +#define TXH_PEND 0x01000000
617 +#define TXL_PEND 0x02000000
618 +#define RX_PEND 0x04000000
619 +#define STS_PEND 0x08000000
620 +#define AAL2_PEND 0x10000000
621 +#define INT_PENDING (TXH_PEND | TXL_PEND | RX_PEND | STS_PEND | AAL2_PEND)
622 +#define STS_PEND_INVEC 0x0001F000
623 +#define RX_PEND_INVEC 0x00000F00
624 +#define TXL_PEND_INVEC 0x000000F0
625 +#define TXH_PEND_INVEC 0x0000000F
626 +#define AIS_SEG_MASK 0x1 /* +01.02.00 */
627 +#define AIS_SEG_SHIFT 0 /* +01.02.00 */
628 +#define AIS_ETOE_MASK 0x20000 /* +01.02.00 */
629 +#define AIS_ETOE_SHIFT 17 /* +01.02.00 */
630 +#define RDI_CNT_MASK 0xffff0000 /* +01.02.00 */
631 +#define RDI_CNT_SHIFT 16 /* +01.02.00 */
632 +
633 +/*
634 + * This function takes a vpi/vci pair and computes the 4 byte atm header
635 + * (minus the HEC).
636 + *
637 + * @param vpi Virtual Path Identifier.
638 + * @param vci Virtual Channel Identifier.
639 + *
640 + * @return A properly formatted ATM header, without the HEC.
641 + */
642 +static int atmheader(int gfc, int vpi, int vci, int pti, int clp)
643 + {
644 + int itmp;
645 +
646 + itmp=0;
647 +
648 + /* UNI Mode uses the GFC field */
649 + itmp |= ((gfc & 0xF) << 28);
650 + itmp |= ((vpi & 0xFF) << 20);
651 +
652 + /* if NNI Mode, no gfc and larger VPI */
653 + /*itmp |= ((vpi & 0xFFF) << 20);*/
654 +
655 + itmp|=((vci & 0xFFFF) << 4);
656 + itmp|=((pti & 0x7) << 1);
657 + itmp|=(clp & 0x1);
658 + return(itmp);
659 + }
660 +
661 +#include "cppi_cpaal5.c"
662 +
663 +/*
664 + * Re-entrancy Issues
665 + * In order to ensure successful re-entrancy certain sections of the
666 + * CPHAL code will be bracketed as Critical.
667 + * The OS will provide the function Os.CriticalSection(BOOL), which
668 + * will be passed a TRUE to enter the Critical Section and FALSE to exit.
669 + */
670 +
671 +/*
672 + * @ingroup CPHAL_Functions
673 + * Clears the statistics information.
674 + *
675 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
676 + *
677 + * @return 0 OK, Non-zero not OK
678 + */
679 +static int StatsClear(HAL_DEVICE *HalDev)
680 + {
681 + int i;
682 +
683 +#ifdef __CPHAL_DEBUG
684 + if (DBG(0))
685 + {
686 + dbgPrintf("[aal5]StatsClear(HalDev:%08x)\n", (bit32u)HalDev);
687 + osfuncSioFlush();
688 + }
689 +#endif
690 +
691 + /* clear stats */
692 + for (i=0; i<NUM_AAL5_CHAN; i++)
693 + {
694 + HalDev->Stats.CrcErrors[i]=0;
695 + HalDev->Stats.LenErrors[i]=0;
696 + HalDev->Stats.DmaLenErrors[i]=0;
697 + HalDev->Stats.AbortErrors[i]=0;
698 + HalDev->Stats.StarvErrors[i]=0;
699 + HalDev->Stats.TxMisQCnt[i][0]=0;
700 + HalDev->Stats.TxMisQCnt[i][1]=0;
701 + HalDev->Stats.RxMisQCnt[i]=0;
702 + HalDev->Stats.RxEOQCnt[i]=0;
703 + HalDev->Stats.TxEOQCnt[i][0]=0;
704 + HalDev->Stats.TxEOQCnt[i][1]=0;
705 + HalDev->Stats.RxPacketsServiced[i]=0;
706 + HalDev->Stats.TxPacketsServiced[i][0]=0;
707 + HalDev->Stats.TxPacketsServiced[i][1]=0;
708 + HalDev->Stats.TxMaxServiced[i][0]=0;
709 + HalDev->Stats.TxMaxServiced[i][1]=0;
710 + }
711 + HalDev->Stats.RxTotal=0;
712 + HalDev->Stats.TxTotal=0;
713 + HalDev->Stats.RxMaxServiced=0;
714 + return (EC_NO_ERRORS);
715 + }
716 +
717 +/*
718 + * Returns statistics information.
719 + *
720 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
721 + *
722 + * @return 0
723 + */
724 +/*
725 +static STAT_INFO* StatsGet(HAL_DEVICE *HalDev)
726 + {
727 + STAT_INFO* MyStats = &HalDev->Stats;
728 +#ifdef __CPHAL_DEBUG
729 + if (DBG(0))
730 + {
731 + dbgPrintf("[aal5]StatsGet(HalDev:%08x)\n", (bit32u)HalDev);
732 + osfuncSioFlush();
733 + }
734 +#endif
735 +
736 + dbgPrintf("HAL Stats:\n");
737 + DispStat(HalDev, "Rx Total",MyStats->RxTotal);
738 + DispStat(HalDev, "Tx Total",MyStats->TxTotal);
739 + DispStat(HalDev, "Rx Peak",MyStats->RxMaxServiced);
740 + DispStat(HalDev, "TxH Peak",MyStats->TxMaxServiced[0][0]);
741 + DispStat(HalDev, "TxL Peak",MyStats->TxMaxServiced[0][1]);
742 + DispChStat(HalDev, "CrcErr",&MyStats->CrcErrors[0],1);
743 + DispChStat(HalDev, "LenErr",&MyStats->LenErrors[0],1);
744 + DispChStat(HalDev, "DmaLenErr",&MyStats->DmaLenErrors[0],1);
745 + DispChStat(HalDev, "AbortErr",&MyStats->AbortErrors[0],1);
746 + DispChStat(HalDev, "StarvErr",&MyStats->StarvErrors[0],1);
747 + DispChStat(HalDev, "TxH MisQ Cnt",&MyStats->TxMisQCnt[0][0],2);
748 + DispChStat(HalDev, "TxL MisQ Cnt",&MyStats->TxMisQCnt[0][1],2);
749 + DispChStat(HalDev, "Rx MisQ Cnt",&MyStats->RxMisQCnt[0],1);
750 + DispChStat(HalDev, "Rx EOQ Cnt",&MyStats->RxEOQCnt[0],1);
751 + DispChStat(HalDev, "TxH EOQ Cnt",&MyStats->TxEOQCnt[0][0],2);
752 + DispChStat(HalDev, "TxL EOQ Cnt",&MyStats->TxEOQCnt[0][1],2);
753 + DispChStat(HalDev, "Rx Pkts",&MyStats->RxPacketsServiced[0],1);
754 + DispChStat(HalDev, "TxH Pkts",&MyStats->TxPacketsServiced[0][0],2);
755 + DispChStat(HalDev, "TxL Pkts",&MyStats->TxPacketsServiced[0][1],2);
756 +
757 + return (&HalDev->Stats);
758 + }
759 +*/
760 +
761 +#ifdef __CPHAL_DEBUG
762 +void dbgChannelConfigDump(HAL_DEVICE *HalDev, int Ch)
763 + {
764 + CHANNEL_INFO *HalCh = &HalDev->ChData[Ch];
765 + dbgPrintf(" [aal5 Inst %d, Ch %d] Config Dump:\n", HalDev->Inst, Ch);
766 + dbgPrintf(" TxNumBuffers :%08d, TxNumQueues :%08d\n",
767 + HalCh->TxNumBuffers, HalCh->TxNumQueues);
768 + dbgPrintf(" RxNumBuffers :%08d, RxBufSize :%08d\n",
769 + HalCh->RxNumBuffers, HalCh->RxBufSize);
770 + dbgPrintf(" TxServiceMax :%08d, RxServiceMax:%08d\n",
771 + HalCh->TxServiceMax, HalCh->RxServiceMax);
772 + dbgPrintf(" RxBufferOffset:%08d, DaMask :%08d\n",
773 + HalCh->RxBufferOffset, HalCh->DaMask);
774 + dbgPrintf(" CpcsUU :%08d, Gfc :%08d\n",
775 + HalCh->CpcsUU, HalCh->Gfc);
776 + dbgPrintf(" Clp :%08d, Pti :%08d\n",
777 + HalCh->Clp, HalCh->Pti);
778 + dbgPrintf(" Priority :%08d, PktType :%08d\n",
779 + HalCh->Priority, HalCh->PktType);
780 + dbgPrintf(" Vci :%08d, Vpi :%08d\n",
781 + HalCh->Vci, HalCh->Vpi);
782 + dbgPrintf(" TxVc_CellRate :%08d, TxVc_QosType:%08d\n",
783 + HalCh->TxVc_CellRate, HalCh->TxVc_QosType);
784 + dbgPrintf(" TxVc_Mbs :%08d, TxVc_Pcr :%08d\n",
785 + HalCh->TxVc_Mbs, HalCh->TxVc_Pcr);
786 + dbgPrintf(" TxVc_AtmHeader:%08d\n",
787 + HalCh->TxVc_AtmHeader);
788 + osfuncSioFlush();
789 + }
790 +#endif
791 +
792 +/*
793 + * Retrieves channel parameters from configuration file. Any parameters
794 + * which are not found are ignored, and the HAL default value will apply,
795 + * unless a new value is given through the channel structure in the call
796 + * to ChannelSetup.
797 + */
798 +static int ChannelConfigGet(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
799 + {
800 + unsigned int Ret, Value, Ch = HalChn->Channel;
801 + OS_FUNCTIONS *OsFunc = HalDev->OsFunc;
802 + void *ChInfo;
803 +
804 +#ifdef __CPHAL_DEBUG
805 + if (DBG(0))
806 + {
807 + dbgPrintf("[aal5]ChannelConfigGet(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
808 + (bit32u)HalChn);
809 + osfuncSioFlush();
810 + }
811 +#endif
812 +
813 + Ret=OsFunc->DeviceFindParmValue(HalDev->DeviceInfo, channel_names[Ch], &ChInfo);
814 + if (Ret) return (EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_CH_INFO_NOT_FOUND);
815 +
816 + /* i don't care if a value is not found because they are optional */
817 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxNumBuffers", &Value);
818 + if (!Ret) HalDev->ChData[Ch].TxNumBuffers = Value;
819 +
820 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxNumQueues", &Value);
821 + if (!Ret) HalDev->ChData[Ch].TxNumQueues = Value;
822 +
823 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxServiceMax", &Value);
824 + if (!Ret) HalDev->ChData[Ch].TxServiceMax = Value;
825 +
826 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxNumBuffers", &Value);
827 + if (!Ret) HalDev->ChData[Ch].RxNumBuffers = Value;
828 +
829 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxBufferOffset", &Value);
830 + if (!Ret) HalDev->ChData[Ch].RxBufferOffset = Value;
831 +
832 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxBufSize", &Value);
833 + if (!Ret) HalDev->ChData[Ch].RxBufSize = Value;
834 +
835 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "RxServiceMax", &Value);
836 + if (!Ret) HalDev->ChData[Ch].RxServiceMax = Value;
837 +
838 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "CpcsUU", &Value);
839 + if (!Ret) HalDev->ChData[Ch].CpcsUU = Value;
840 +
841 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "Gfc", &Value);
842 + if (!Ret) HalDev->ChData[Ch].Gfc = Value;
843 +
844 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "Clp", &Value);
845 + if (!Ret) HalDev->ChData[Ch].Clp = Value;
846 +
847 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "Pti", &Value);
848 + if (!Ret) HalDev->ChData[Ch].Pti = Value;
849 +
850 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "DaMask", &Value);
851 + if (!Ret) HalDev->ChData[Ch].DaMask = Value;
852 +
853 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "Priority", &Value);
854 + if (!Ret) HalDev->ChData[Ch].Priority = Value;
855 +
856 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "PktType", &Value);
857 + if (!Ret) HalDev->ChData[Ch].PktType = Value;
858 +
859 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "Vci", &Value);
860 + if (!Ret) HalDev->ChData[Ch].Vci = Value;
861 +
862 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "Vpi", &Value);
863 + if (!Ret) HalDev->ChData[Ch].Vpi = Value;
864 +
865 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_CellRate", &Value);
866 + if (!Ret) HalDev->ChData[Ch].TxVc_CellRate = Value;
867 +
868 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_QosType", &Value);
869 + if (!Ret) HalDev->ChData[Ch].TxVc_QosType = Value;
870 +
871 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_Mbs", &Value);
872 + if (!Ret) HalDev->ChData[Ch].TxVc_Mbs = Value;
873 +
874 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_Pcr", &Value);
875 + if (!Ret) HalDev->ChData[Ch].TxVc_Pcr = Value;
876 +
877 + Ret=OsFunc->DeviceFindParmUint(ChInfo, "TxVc_AtmHeader", &Value);
878 + if (!Ret) HalDev->ChData[Ch].TxVc_AtmHeader = Value;
879 +
880 + return (EC_NO_ERRORS);
881 + }
882 +
883 +/*
884 + * Sets up channel parameters in the hardware, and initializes the CPPI
885 + * TX and RX buffer descriptors and buffers.
886 + */
887 +static int ChannelConfigApply(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
888 + {
889 + int j, Ch = HalChn->Channel;
890 + volatile bit32u *pTmp;
891 + int Ret; /* +GSG 030410 */
892 +
893 +#ifdef __CPHAL_DEBUG
894 + if (DBG(0))
895 + {
896 + dbgPrintf("[aal5]ChannelConfigApply(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
897 + (bit32u)HalChn);
898 + osfuncSioFlush();
899 + }
900 +#endif
901 +
902 + if ((HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE) || (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE))
903 + {
904 + return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_CH_ALREADY_OPEN);
905 + }
906 +
907 + HalDev->InRxInt[Ch]=FALSE;
908 +
909 + /* Initialize Queue Data */
910 + HalDev->RxActQueueHead[Ch]=0;
911 + HalDev->RxActQueueCount[Ch]=0;
912 + HalDev->TxActQueueHead[Ch][0]=0;
913 + HalDev->TxActQueueHead[Ch][1]=0;
914 + HalDev->TxActQueueCount[Ch][0]=0;
915 + HalDev->TxActQueueCount[Ch][1]=0;
916 + HalDev->RxActive[Ch] = FALSE;
917 + HalDev->TxActive[Ch][0] = FALSE;
918 + HalDev->TxActive[Ch][1] = FALSE;
919 +
920 + /* Clear Rx State RAM */
921 + pTmp = pRX_DMA_STATE_WORD_0(HalDev->dev_base) + (Ch*64);
922 + for (j=0; j<NUM_RX_STATE_WORDS; j++)
923 + *pTmp++ = 0;
924 +
925 + /* Check that Rx DMA State RAM was cleared */
926 + pTmp -= NUM_RX_STATE_WORDS;
927 + for (j=0; j<NUM_RX_STATE_WORDS; j++)
928 + {
929 + if (*pTmp++ != 0)
930 + {
931 + return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_RX_STATE_RAM_NOT_CLEARED);
932 + }
933 + }
934 +
935 + /* Clear Tx State RAM */
936 + pTmp = pTX_DMA_STATE_WORD_0(HalDev->dev_base) + (Ch*64);
937 + for (j=0; j<NUM_TX_STATE_WORDS; j++)
938 + *pTmp++ = 0;
939 +
940 + /* Check that Tx DMA State RAM was cleared */
941 + pTmp -= NUM_TX_STATE_WORDS;
942 + for (j=0; j<NUM_TX_STATE_WORDS; j++)
943 + {
944 + if (*pTmp++ != 0)
945 + {
946 + return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_TX_STATE_RAM_NOT_CLEARED);
947 + }
948 + }
949 +
950 + /* Initialize Tx State RAM (Nothing to do) */
951 +
952 + /* Initialize Rx State RAM */
953 + /* Configure the Rx buffer offset */
954 + pTmp=(pRX_DMA_STATE_WORD_0(HalDev->dev_base) + (Ch*64));
955 + *pTmp |= (HalDev->ChData[Ch].RxBufferOffset & 0xFF);
956 +
957 + /* Initialize buffer memory for the channel */
958 + Ret = InitTcb(HalDev, Ch);
959 + if (Ret) return (Ret);
960 +
961 + Ret = InitRcb(HalDev, Ch);
962 + if (Ret) return (Ret);
963 +
964 + /* setup interrupt mask/enable for the channel */
965 + SAR_TX_MASK_SET(HalDev->dev_base) = (1<<Ch);
966 +
967 + /* if using the low priority queue, set up mask for it */
968 + if (HalDev->ChData[Ch].TxNumQueues == 2) /* +GSG 030421 */
969 + SAR_TX_MASK_SET(HalDev->dev_base) = (1<<Ch)<<16; /* +GSG 030421 */
970 +
971 + SAR_RX_MASK_SET(HalDev->dev_base) = (1<<Ch);
972 +
973 + /* call SAR layer to complete the channel setup - hardware configuration of ch */
974 + Ret = HalDev->SarFunc->ChannelSetup(HalDev->SarDev, &HalDev->ChData[Ch]); /* ~GSG 030410 */
975 + if (Ret) /* +GSG 030410 */
976 + return (Ret); /* +GSG 030410 */
977 +
978 + /* channel officially open for business */
979 + HalDev->ChIsOpen[Ch][DIRECTION_TX] = TRUE;
980 + HalDev->ChIsOpen[Ch][DIRECTION_RX] = TRUE;
981 +
982 + return (EC_NO_ERRORS);
983 + }
984 +
985 +/*
986 + * Sets up HAL default channel configuration parameter values.
987 + */
988 +static void ChannelConfigInit(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
989 + {
990 + int Ch = HalChn->Channel;
991 +
992 +#ifdef __CPHAL_DEBUG
993 + if (DBG(0))
994 + {
995 + dbgPrintf("[aal5]ChannelConfigInit(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
996 + (bit32u)HalChn);
997 + osfuncSioFlush();
998 + }
999 +#endif
1000 +
1001 + HalDev->ChData[Ch].Channel = Ch;
1002 + HalDev->ChData[Ch].TxNumBuffers = cfg_tx_num_bufs[Ch];
1003 + HalDev->ChData[Ch].RxNumBuffers = cfg_rx_num_bufs[Ch];
1004 + HalDev->ChData[Ch].RxBufSize = cfg_rx_buf_size[Ch];
1005 + HalDev->ChData[Ch].RxBufferOffset = cfg_rx_buf_offset[Ch];
1006 + HalDev->ChData[Ch].TxNumQueues = cfg_tx_num_queues[Ch];
1007 + HalDev->ChData[Ch].CpcsUU = cfg_cpcs_uu[Ch];
1008 + HalDev->ChData[Ch].DaMask = cfg_da_mask[Ch];
1009 + HalDev->ChData[Ch].Priority = cfg_priority[Ch];
1010 + HalDev->ChData[Ch].PktType = cfg_pkt_type[Ch];
1011 + HalDev->ChData[Ch].Vci = cfg_vci[Ch];
1012 + HalDev->ChData[Ch].Vpi = cfg_vpi[Ch];
1013 + HalDev->ChData[Ch].TxVc_CellRate = cfg_cell_rate[Ch];
1014 + HalDev->ChData[Ch].TxVc_QosType = cfg_qos_type[Ch];
1015 + HalDev->ChData[Ch].TxVc_Mbs = cfg_mbs[Ch];
1016 + HalDev->ChData[Ch].TxVc_Pcr = cfg_pcr[Ch];
1017 + HalDev->ChData[Ch].Gfc = cfg_gfc[Ch];
1018 + HalDev->ChData[Ch].Clp = cfg_clp[Ch];
1019 + HalDev->ChData[Ch].Pti = cfg_pti[Ch];
1020 + HalDev->ChData[Ch].RxServiceMax = cfg_rx_max_service[Ch];
1021 + HalDev->ChData[Ch].TxServiceMax = cfg_tx_max_service[Ch];
1022 + }
1023 +
1024 +/*
1025 + * Update per channel data in the HalDev based channel structure.
1026 + * If a certain channel parameter has been passed with the HAL_DEFAULT
1027 + * value (0xFFFFFFFF), then do not copy it.
1028 + */
1029 +static void ChannelConfigUpdate(HAL_DEVICE *HalDev, CHANNEL_INFO *HalChn)
1030 + {
1031 + int Ch = HalChn->Channel;
1032 +
1033 +#ifdef __CPHAL_DEBUG
1034 + if (DBG(0))
1035 + {
1036 + dbgPrintf("[aal5]ChannelConfigUpdate(HalDev:%08x, HalChn:%08x)\n", (bit32u)HalDev,
1037 + (bit32u)HalChn);
1038 + osfuncSioFlush();
1039 + }
1040 +#endif
1041 +
1042 + HalDev->ChData[Ch].Channel = Ch;
1043 +
1044 + /* ChannelUpdate is a macro defined in cpcommon.h. It requires
1045 + the presence of the variables named 'Ch' and 'HalChn'.*/
1046 + ChannelUpdate(DaMask);
1047 + ChannelUpdate(Priority);
1048 + ChannelUpdate(PktType);
1049 + ChannelUpdate(Vci);
1050 + ChannelUpdate(Vpi);
1051 + ChannelUpdate(CpcsUU);
1052 + ChannelUpdate(Gfc);
1053 + ChannelUpdate(Clp);
1054 + ChannelUpdate(Pti);
1055 + /* AAL5 Stuff */
1056 + ChannelUpdate(TxNumBuffers);
1057 + ChannelUpdate(RxNumBuffers);
1058 + ChannelUpdate(RxBufSize);
1059 + ChannelUpdate(RxBufferOffset);
1060 + ChannelUpdate(TxNumQueues);
1061 + ChannelUpdate(TxServiceMax);
1062 + ChannelUpdate(RxServiceMax);
1063 + /* PDSP STATE RAM */
1064 + ChannelUpdate(TxVc_CellRate);
1065 + ChannelUpdate(TxVc_QosType);
1066 + ChannelUpdate(TxVc_Mbs);
1067 + ChannelUpdate(TxVc_Pcr);
1068 + /* OAM */
1069 + ChannelUpdate(TxVc_AtmHeader);
1070 + ChannelUpdate(TxVc_OamTc);
1071 + ChannelUpdate(TxVc_VpOffset);
1072 + ChannelUpdate(RxVc_OamCh);
1073 + ChannelUpdate(RxVc_OamToHost);
1074 + ChannelUpdate(RxVc_AtmHeader);
1075 + ChannelUpdate(RxVc_VpOffset);
1076 + ChannelUpdate(RxVc_OamTc);
1077 + ChannelUpdate(TxVp_AtmHeader);
1078 + ChannelUpdate(TxVp_OamTc);
1079 + ChannelUpdate(RxVp_AtmHeader);
1080 + ChannelUpdate(RxVp_OamCh);
1081 + ChannelUpdate(RxVp_OamTc);
1082 + ChannelUpdate(RxVp_OamToHost);
1083 + ChannelUpdate(RxVp_OamVcList);
1084 + ChannelUpdate(FwdUnkVc);
1085 + }
1086 +
1087 +/**
1088 + * @ingroup CPHAL_Functions
1089 + * This function opens the specified channel. The caller must populate
1090 + * the @p HalCh structure. CPHAL default values may be requested for any or all
1091 + * members of the @p HalCh structure by supplying a value of 0xFFFFFFFF for the
1092 + * given member. The @p OsSetup parameter is a pointer to an OS defined
1093 + * data structure. If the CPHAL later calls @c MallocRxBuffer(), this pointer
1094 + * is returned in that call.
1095 + *
1096 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
1097 + * @param HalCh Per channel information structure. Implementation specific.
1098 + * @param OsSetup Pointer to an OS-defined data structure.
1099 + *
1100 + * @return EC_NO_ERRORS (ok). <BR>
1101 + * Possible Error Codes:<BR>
1102 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
1103 + * @ref EC_VAL_NULL_CH_STRUCT "EC_VAL_NULL_CH_STRUCT"<BR>
1104 + * @ref EC_VAL_INVALID_CH "EC_VAL_INVALID_CH"<BR>
1105 + * @ref EC_VAL_CH_ALREADY_OPEN "EC_VAL_CH_ALREADY_OPEN"<BR>
1106 + * @ref EC_VAL_RX_STATE_RAM_NOT_CLEARED "EC_VAL_RX_STATE_RAM_NOT_CLEARED"<BR>
1107 + * @ref EC_VAL_TX_STATE_RAM_NOT_CLEARED "EC_VAL_TX_STATE_RAM_NOT_CLEARED"<BR>
1108 + * @ref EC_VAL_TCB_MALLOC_FAILED "EC_VAL_TCB_MALLOC_FAILED"<BR>
1109 + * @ref EC_VAL_RCB_MALLOC_FAILED "EC_VAL_RCB_MALLOC_FAILED"<BR>
1110 + * @ref EC_VAL_RX_BUFFER_MALLOC_FAILED "EC_VAL_RX_BUFFER_MALLOC_FAILED"<BR>
1111 + * @ref EC_VAL_LUT_NOT_READY "EC_VAL_LUT_NOT_READY"<BR>
1112 + */
1113 +static int halChannelSetup(HAL_DEVICE *HalDev, CHANNEL_INFO *HalCh, OS_SETUP *OsSetup)
1114 + {
1115 + int Ch, Ret;
1116 +
1117 +#ifdef __CPHAL_DEBUG
1118 + if (DBG(0))
1119 + {
1120 + dbgPrintf("[aal5]halChannelSetup(HalDev:%08x, HalCh:%08x, OsSetup:%08x)\n", (bit32u)HalDev,
1121 + (bit32u)HalCh, (bit32u)OsSetup);
1122 + osfuncSioFlush();
1123 + }
1124 +#endif
1125 +
1126 + /* Verify proper device state */
1127 + if (HalDev->State < enInitialized)
1128 + return (EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_INVALID_STATE);
1129 +
1130 + /* We require the channel structure to be passed, even if it only contains
1131 + the channel number */
1132 + if (HalCh == NULL)
1133 + {
1134 + return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_NULL_CH_STRUCT);
1135 + }
1136 +
1137 + Ch = HalCh->Channel;
1138 +
1139 + if ((Ch < 0) || (Ch > MAX_AAL5_CHAN))
1140 + {
1141 + return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_INVALID_CH);
1142 + }
1143 +
1144 + /* if channel is already open, this call is invalid */
1145 + if ((HalDev->ChIsOpen[Ch][DIRECTION_TX] == TRUE) || (HalDev->ChIsOpen[Ch][DIRECTION_RX] == TRUE))
1146 + {
1147 + return(EC_AAL5|EC_FUNC_CHSETUP|EC_VAL_CH_ALREADY_OPEN);
1148 + }
1149 +
1150 + /* channel is closed, but might be setup. If so, reopen the hardware channel. */
1151 + if ((HalDev->ChIsSetup[Ch][DIRECTION_TX] == FALSE) && (HalDev->ChIsSetup[Ch][DIRECTION_RX] == FALSE))
1152 + {
1153 + /* Setup channel configuration */
1154 + /* Store OS_SETUP */
1155 + HalDev->ChData[Ch].OsSetup = OsSetup; /* ~GSG 030508 */
1156 +
1157 + /* setup HAL default values for this channel first */
1158 + ChannelConfigInit(HalDev, HalCh);
1159 +
1160 + /* retrieve options.conf channel parameters */
1161 + /* currently ignoring return value, making the choice that it's okay if
1162 + the user does not supply channel configuration in the data store */
1163 + ChannelConfigGet(HalDev, HalCh);
1164 +
1165 + /* update HalDev with data given in HalCh */
1166 + ChannelConfigUpdate(HalDev, HalCh);
1167 +
1168 +#ifdef __CPHAL_DEBUG
1169 + if (DBG(8))
1170 + {
1171 + dbgChannelConfigDump(HalDev, Ch);
1172 + }
1173 +#endif
1174 +
1175 + /* HalDev->ChIsSetup[Ch][0] = TRUE; */
1176 + HalDev->ChIsSetup[Ch][DIRECTION_TX] = TRUE;
1177 + HalDev->ChIsSetup[Ch][DIRECTION_RX] = TRUE;
1178 +
1179 + /* I don't initialize RcbStart or TcbStart here because their values may be
1180 + reused across several Setup/Teardown calls */
1181 + }
1182 +
1183 + /* If the hardware has been opened (is out of reset), then configure the channel
1184 + in the hardware. NOTE: ChannelConfigApply calls the CPSAR ChannelSetup()! */
1185 + if (HalDev->State == enOpened)
1186 + {
1187 + Ret = ChannelConfigApply(HalDev, HalCh);
1188 + if (Ret) return (Ret);
1189 + }
1190 +
1191 + return (EC_NO_ERRORS);
1192 + }
1193 +
1194 +/*
1195 + * This function configures the rate at which the OAM timer scheduler
1196 + * channels will be scheduled. The value of OamRate is the number of
1197 + * clock ticks between cell transmissions (if OAM function is sourcing
1198 + * cells), or the number of clock ticks between events or absence of events
1199 + * (if OAM function is sinking cells). The value of i indicates
1200 + * which OAM function to apply the rate to. A list is given below.
1201 + *
1202 + * @par Oam Function Values
1203 + * - 0 : Loopback source
1204 + * - 1 : F4 CC source
1205 + * - 2 : F5 CC source
1206 + * - 3 : F4 CC sink
1207 + * - 4 : F5 CC sink
1208 + * - 5 : F4 TX AIS source
1209 + * - 6 : F5 TX AIS source
1210 + * - 7 : F4 RX RDI source
1211 + * - 8 : F5 RX RDI source
1212 + * - 9 : F4 AIS monitor
1213 + * - 10 : F5 AIS monitor
1214 + *
1215 + * The following is information on how to calculate the OAM rate. There
1216 + * is only one OAM timer that is shared among all channels. Therefore, if
1217 + * you wanted an OAM source function (ex. F4 CC source) to generate 1 cell/sec
1218 + * across 8 channels, you would need to configure the OAM timer to schedule 8
1219 + * cells/sec. In addition, the credits are shared between segment and end-to-end
1220 + * type OAM cells, so if you were sending both types of cells, you would
1221 + * need to configure the OAM timer for 16 cells/sec. However, the clock
1222 + * rate must be specified in clock ticks between events. Using an example
1223 + * clock rate of 125 MHz, the rate in clock ticks can be calculated by
1224 + * dividing 125 Mhz by 16 cells/sec. The results is 7812500 ticks. Thus,
1225 + * every 7812500 clock cycles, an OAM cell will be generated for the F4 CC
1226 + * Source function.
1227 + */
1228 +static void OamRateConfig(HAL_DEVICE *HalDev)
1229 + {
1230 + int i;
1231 + bit32u OamRate, Freq = HalDev->SarFrequency;
1232 +
1233 + /* Configure OAM Timer State Block */
1234 + for (i=0; i<NUM_OAM_RATES; i++)
1235 + {
1236 + switch(i)
1237 + {
1238 + case 0: OamRate = ((Freq/1000)*HalDev->OamLbTimeout);
1239 + break;
1240 + case 1:
1241 + case 2:
1242 + case 5:
1243 + case 6:
1244 + case 7:
1245 + case 8: OamRate = (Freq/38);
1246 + break;
1247 + case 3:
1248 + case 4: OamRate = ((Freq*3) + (Freq/2))/38;
1249 + break;
1250 + case 9:
1251 + case 10: OamRate = ((Freq*2) + (Freq/2))/38;
1252 + break;
1253 + default: OamRate = (Freq*5);
1254 + break;
1255 + }
1256 +
1257 + *(pOAM_TIMER_STATE_WORD_0(HalDev->dev_base) + (i*64) + 1) = OamRate;
1258 + }
1259 + }
1260 +
1261 +/**
1262 + * @ingroup AAL5_Functions
1263 + * This function is used to enable OAM functions (other than loopback) for a
1264 + * particular channel. The channel (embedded within OamConfig - see below) must
1265 + * have been configured for firmware OAM (not host OAM) for these configurations
1266 + * to take effect. More than one function may be enabled at one time.
1267 + * If more than one function is enabled, they must all be of the same level, all
1268 + * F4(VP) or all F5(VC).
1269 + *
1270 + * The usage of the OamConfig parameter is described through the table below. To
1271 + * initiate firmware OAM, set one or more bits in OamConfig corresponding to the
1272 + * various OAM functions. To disable firmware OAM functions, set bit 30 along
1273 + * with any other combination of bits to shutdown various OAM functions at once.
1274 + *
1275 + * Acronyms:
1276 + * e2e - end to end, seg - segment, CC - continuity check,
1277 + * AIS - Alarm Indication Signal
1278 + *
1279 + * @par Bit: Function: Description
1280 + * - 31: Reserved:
1281 + * - 30: Setup/Teardown: 0 - enable, 1 - disable (Note 1)
1282 + * - 29: F4 CC Source seg: 0 - no action, 1 - configure
1283 + * - 28: F4 CC Source e2e: 0 - no action, 1 - configure
1284 + * - 27: F4 AIS Source seg: 0 - no action, 1 - configure
1285 + * - 26: F4 AIS Source e2e: 0 - no action, 1 - configure
1286 + * - 25: F5 CC Source seg: 0 - no action, 1 - configure
1287 + * - 24: F5 CC Source e2e: 0 - no action, 1 - configure
1288 + * - 23: F5 AIS Source seg: 0 - no action, 1 - configure
1289 + * - 22: F5 AIS Source e2e: 0 - no action, 1 - configure
1290 + * - 21: F4 CC Sink seg: 0 - no action, 1 - configure
1291 + * - 20: F4 CC Sink e2e: 0 - no action, 1 - configure
1292 + * - 19: F5 CC Sink seg: 0 - no action, 1 - configure
1293 + * - 18: F5 CC Sink e2e: 0 - no action, 1 - configure
1294 + * - 17:8: Reserved:
1295 + * - 7:0: Channel: AAL5/AAL2 VC/VP channel (Note 2)
1296 + *
1297 + *
1298 + * Note 1: This bit must be clear to enable the specified OAM function.
1299 + * Note 2: This must specify the VC channel for F5 functions, and the VP
1300 + * channel for F4 functions.
1301 + *
1302 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
1303 + * @param OamConfig A 32-bit integer field defined as follows:
1304 + */
1305 +static void halOamFuncConfig(HAL_DEVICE *HalDev, unsigned int OamConfig)
1306 + {
1307 + /* GPR 0 */
1308 + SAR_PDSP_HOST_OAM_CONFIG_REG(HalDev->dev_base) = OamConfig;
1309 + }
1310 +
1311 +/**
1312 + * @ingroup AAL5_Functions
1313 + * This function is used to enable OAM loopback functions for a particular
1314 + * channel. The channel (embedded within OamConfig - see below) must have been
1315 + * configured for firmware OAM (not host OAM) for these configurations to take
1316 + * effect. Only one loopback function can be enabled at a time.
1317 + *
1318 + * The LLID is inserted into to the OAM cell's LLID field, and it specifies the
1319 + * LLID of the connection point in the network where the generated loopback cell
1320 + * should be turned around. The LLID is composed of 4 32-bit words, and this
1321 + * function expects the caller to pass an array of 4 words in the LLID field.
1322 + * The CorrelationTag is a 32-bit word that the PDSP uses to correlate loopback
1323 + * commands with loopback responses. It should simply be changed for each
1324 + * call, and there is no restriction on the value used for CorrelationTag.
1325 + *
1326 + * The usage of the OamConfig parameter is described through the table below. To
1327 + * initiate firmware OAM, set one of the bits corresponding to the
1328 + * various loopback OAM functions. Note that only one loopback source may be
1329 + * commanded at a time.
1330 + *
1331 + * Acronyms:
1332 + * e2e - end to end, seg - segment, LB - loopback
1333 + *
1334 + * @par Bit: Function: Description
1335 + * - 31:16: Reserved:
1336 + * - 15: F4 LB Source seg: 0 - no action, 1 - configure (Note 1)
1337 + * - 14: F4 LB Source seg: 0 - no action, 1 - configure (Note 1)
1338 + * - 13: F4 LB Source e2e: 0 - no action, 1 - configure (Note 1)
1339 + * - 12: F4 LB Source e2e: 0 - no action, 1 - configure (Note 1)
1340 + * - 11:8: Reserved:
1341 + * - 7:0: Channel: AAL5/AAL2 VC/VP channel (Note 2)
1342 + *
1343 + *
1344 + * Note 1: Only one LB function may be enabled at one time. Once enabled,
1345 + * the PDSP will time out after 5 seconds. The host must wait until it
1346 + * has received the result of the current LB request before initiating
1347 + * a new request. <BR>
1348 + * Note 2: This must specify the VC channel for F5 functions, and the VP
1349 + * channel for F4 functions.
1350 + *
1351 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
1352 + * @param OamConfig A 32-bit integer field defined as follows:
1353 + * @param LLID Loopback Location Identifier (passed as 4 word array).
1354 + * Must be configured in big endian format.
1355 + * @param CorrelationTag 32-bit tag correlates loopback commands with loopback
1356 + * responses. Must be configured in big endian format.
1357 + *
1358 + */
1359 +static void halOamLoopbackConfig(HAL_DEVICE *HalDev, unsigned int OamConfig, unsigned int *LLID, unsigned int CorrelationTag)
1360 + {
1361 + volatile bit32u *tmp;
1362 +
1363 + /* test to see if this is a loopback command */
1364 + if (OamConfig & 0xf000)
1365 + {
1366 + /* write the OAM correlation tag (GPR 1) */
1367 + SAR_PDSP_OAM_CORR_REG(HalDev->dev_base) = CorrelationTag;
1368 +
1369 + /* write the LLID */
1370 + tmp = pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base);
1371 +
1372 + /* advance past the CPID */
1373 + tmp += 4;
1374 +
1375 + *tmp++ = LLID[0];
1376 + *tmp++ = LLID[1];
1377 + *tmp++ = LLID[2];
1378 + *tmp = LLID[3];
1379 +
1380 + /* GPR 0 */
1381 + SAR_PDSP_HOST_OAM_CONFIG_REG(HalDev->dev_base) = OamConfig;
1382 + }
1383 + }
1384 +
1385 +/*
1386 + * This function allows the host software to access any register directly.
1387 + * Primarily used for debug.
1388 + *
1389 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
1390 + * @param RegOffset Hexadecimal offset to desired register (from device base addr)
1391 + *
1392 + * @return Volatile pointer to desired register.
1393 + */
1394 +static volatile bit32u* halRegAccess(HAL_DEVICE *HalDev, bit32u RegOffset)
1395 + {
1396 + /* compute the register address */
1397 + return ((volatile bit32u *)(HalDev->dev_base + RegOffset));
1398 + }
1399 +
1400 +#ifdef __CPHAL_DEBUG
1401 +static void dbgConfigDump(HAL_DEVICE *HalDev)
1402 + {
1403 + dbgPrintf(" AAL5 Inst %d Config Dump:\n", HalDev->Inst);
1404 + dbgPrintf(" Base :%08x, offset:%08d\n",
1405 + HalDev->dev_base, HalDev->offset);
1406 + dbgPrintf(" Interrupt:%08d, debug :%08d\n",
1407 + HalDev->interrupt, HalDev->debug);
1408 + osfuncSioFlush();
1409 + }
1410 +#endif
1411 +
1412 +/**
1413 + * @ingroup CPHAL_Functions
1414 + * Performs a variety of control functions on the CPHAL module. It is used to
1415 + * modify/read configuration parameters and to initiate internal functions.
1416 + * The @p Key indicates the function to perform or the parameter to access (note
1417 + * that these Keys are identical to those used in accessing the configuration data
1418 + * store). @p Action is applicable to parameters only, and indicates what the
1419 + * CPHAL should do with the parameter (i.e. "Set", "Get", etc..). The actions
1420 + * for each parameter are defined in the module specific documentation.
1421 + *
1422 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
1423 + * @param Key Key specifying the parameter to change or internal function to initiate. See module specific documentation for available keys.
1424 + * @param Action Specifies the action to take. See module specific documentation for available actions.
1425 + * @param Value Pointer to new value for given @p Key parameter ("Set"), or returned value of Key ("Get").
1426 + *
1427 + * @return EC_NO_ERRORS (ok).<BR>
1428 + * Possible Error Codes:<BR>
1429 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
1430 + * @ref EC_VAL_KEY_NOT_FOUND "EC_VAL_KEY_NOT_FOUND"<BR>
1431 + * @ref EC_VAL_ACTION_NOT_FOUND "EC_VAL_ACTION_NOT_FOUND"<BR>
1432 + */
1433 +static int halControl(HAL_DEVICE *HalDev, const char *Key, const char *Action, void *Value)
1434 + {
1435 + int Level, Ch, KeyFound=0, ActionFound=0, rc=EC_NO_ERRORS, Queue;
1436 + char *TmpKey = (char *)Key;
1437 +
1438 +#ifdef __CPHAL_DEBUG
1439 + if (DBG(0))
1440 + {
1441 + dbgPrintf("[aal5]halControl(HalDev:%08x, Key:%s, Action:%s, Value:%08x)\n", (bit32u)HalDev,
1442 + Key, Action, (bit32u)Value);
1443 + osfuncSioFlush();
1444 + }
1445 +#endif
1446 +
1447 + /* Verify proper device state */
1448 + if (HalDev->State < enInitialized)
1449 + return (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_INVALID_STATE);
1450 +
1451 + if (HalDev->OsFunc->Strcmpi(Key, "Debug") == 0)
1452 + {
1453 + KeyFound=1;
1454 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1455 + {
1456 + ActionFound=1;
1457 + HalDev->debug = *(int *)Value;
1458 + /* also setup debug variable in CPSAR module */
1459 + rc = HalDev->SarFunc->Control(HalDev->SarDev, "Debug", "Set", Value);
1460 + }
1461 + }
1462 +
1463 + if (HalDev->OsFunc->Strstr(Key, "FwdUnkVc.") != 0)
1464 + {
1465 + KeyFound=1;
1466 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1467 + {
1468 + ActionFound=1;
1469 +
1470 + /* extract channel number */
1471 + TmpKey += HalDev->OsFunc->Strlen("FwdUnkVc.");
1472 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1473 +
1474 + HalDev->ChData[Ch].FwdUnkVc = *(int *)Value;
1475 +
1476 + if ((HalDev->State == enOpened) && (HalDev->ChData[Ch].PktType == 3))
1477 + rc = HalDev->SarFunc->Control(HalDev->SarDev, Key, Action, Value);
1478 + }
1479 + }
1480 +
1481 + /* +GSG 030407 */
1482 + if (HalDev->OsFunc->Strcmpi(Key, "OamMode") == 0)
1483 + {
1484 + KeyFound=1;
1485 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1486 + {
1487 + ActionFound=1;
1488 + rc = HalDev->SarFunc->Control(HalDev->SarDev, Key, Action, Value);
1489 + }
1490 +
1491 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1492 + {
1493 + ActionFound=1;
1494 + rc = HalDev->SarFunc->Control(HalDev->SarDev, Key, Action, Value);
1495 + }
1496 + }
1497 +
1498 + /* +GSG 030307 */
1499 + if (HalDev->OsFunc->Strcmpi(Key, "Version") == 0)
1500 + {
1501 + KeyFound=1;
1502 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1503 + {
1504 + ActionFound=1;
1505 + *(const char **)Value = pszVersion_CPAAL5;
1506 + }
1507 + }
1508 +
1509 + /* +GSG 030529 */
1510 + if (HalDev->OsFunc->Strcmpi(Key, "TurboDslErrors") == 0)
1511 + {
1512 + KeyFound=1;
1513 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1514 + {
1515 + ActionFound=1;
1516 + *(int *)Value = HalDev->TurboDslErrors;
1517 + }
1518 + }
1519 +
1520 + /* +GSG 030416 */
1521 + if (HalDev->OsFunc->Strcmpi(Key, "F4_LB_Counter") == 0)
1522 + {
1523 + KeyFound=1;
1524 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1525 + {
1526 + ActionFound=1;
1527 + *(int *)Value = SAR_PDSP_OAM_F4_LB_COUNT_REG(HalDev->dev_base);
1528 + }
1529 + }
1530 +
1531 + /* +GSG 030416 */
1532 + if (HalDev->OsFunc->Strcmpi(Key, "F5_LB_Counter") == 0)
1533 + {
1534 + KeyFound=1;
1535 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1536 + {
1537 + ActionFound=1;
1538 + *(int *)Value = SAR_PDSP_OAM_F5_LB_COUNT_REG(HalDev->dev_base);
1539 + }
1540 + }
1541 +
1542 + if (HalDev->OsFunc->Strstr(Key, "Stats;") != 0)
1543 + {
1544 + KeyFound=1;
1545 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1546 + {
1547 + ActionFound=1;
1548 + TmpKey += HalDev->OsFunc->Strlen("Stats;");
1549 + Level = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1550 + TmpKey++;
1551 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1552 + TmpKey++;
1553 + Queue = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1554 + TmpKey++;
1555 + StatsGet(HalDev, (void **)Value, Level, Ch, Queue);
1556 + }
1557 + }
1558 +
1559 + /* +GSG 030306 */
1560 + /* Fixes PITS #100 */
1561 + if (HalDev->OsFunc->Strstr(Key, "Gfc.") != 0)
1562 + {
1563 + KeyFound=1;
1564 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1565 + {
1566 + ActionFound=1;
1567 + /* extract channel number */
1568 + TmpKey += HalDev->OsFunc->Strlen("Gfc.");
1569 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1570 +
1571 + /* first, store new value in our channel structure */
1572 + HalDev->ChData[Ch].Gfc = *(int *)Value;
1573 + }
1574 + }
1575 +
1576 + /* +GSG 030306 */
1577 + /* Fixes PITS #100 */
1578 + if (HalDev->OsFunc->Strstr(Key, "Clp.") != 0)
1579 + {
1580 + KeyFound=1;
1581 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1582 + {
1583 + ActionFound=1;
1584 + /* extract channel number */
1585 + TmpKey += HalDev->OsFunc->Strlen("Clp.");
1586 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1587 +
1588 + /* first, store new value in our channel structure */
1589 + HalDev->ChData[Ch].Clp = *(int *)Value;
1590 + }
1591 + }
1592 +
1593 + /* +GSG 030306 */
1594 + /* Fixes PITS #100 */
1595 + if (HalDev->OsFunc->Strstr(Key, "Pti.") != 0)
1596 + {
1597 + KeyFound=1;
1598 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1599 + {
1600 + ActionFound=1;
1601 + /* extract channel number */
1602 + TmpKey += HalDev->OsFunc->Strlen("Pti.");
1603 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1604 +
1605 + /* first, store new value in our channel structure */
1606 + HalDev->ChData[Ch].Pti = *(int *)Value;
1607 + }
1608 + }
1609 +
1610 + /* +GSG 030306 */
1611 + /* Fixes PITS #100 */
1612 + if (HalDev->OsFunc->Strstr(Key, "CpcsUU.") != 0)
1613 + {
1614 + KeyFound=1;
1615 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1616 + {
1617 + ActionFound=1;
1618 + /* extract channel number */
1619 + TmpKey += HalDev->OsFunc->Strlen("CpcsUU.");
1620 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1621 +
1622 + /* first, store new value in our channel structure */
1623 + HalDev->ChData[Ch].CpcsUU = *(int *)Value;
1624 + }
1625 + }
1626 +
1627 + /* +GSG 030306 */
1628 + /* Fixes PITS #100 */
1629 + if (HalDev->OsFunc->Strstr(Key, "TxVc_CellRate.") != 0)
1630 + {
1631 + KeyFound=1;
1632 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1633 + {
1634 + ActionFound=1;
1635 + /* extract channel number */
1636 + TmpKey += HalDev->OsFunc->Strlen("TxVc_CellRate.");
1637 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1638 +
1639 + /* first, store new value in our channel structure */
1640 + HalDev->ChData[Ch].TxVc_CellRate = *(int *)Value;
1641 +
1642 + /* now, apply to PDSP state RAM */
1643 + if (HalDev->State == enOpened)
1644 + *(pPDSP_AAL5_TX_STATE_WORD_0(HalDev->dev_base)+(Ch*64))= HalDev->ChData[Ch].TxVc_CellRate;
1645 + }
1646 + }
1647 +
1648 + /* +GSG 030306 */
1649 + /* Fixes PITS #100 */
1650 + if (HalDev->OsFunc->Strstr(Key, "TxVc_Mbs.") != 0)
1651 + {
1652 + KeyFound=1;
1653 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1654 + {
1655 + ActionFound=1;
1656 + /* extract channel number */
1657 + TmpKey += HalDev->OsFunc->Strlen("TxVc_Mbs.");
1658 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1659 +
1660 + /* first, store new value in our channel structure */
1661 + HalDev->ChData[Ch].TxVc_Mbs = *(int *)Value;
1662 +
1663 + /* now, apply to PDSP state RAM */
1664 + if (HalDev->State == enOpened)
1665 + *(pPDSP_AAL5_TX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+2)= HalDev->ChData[Ch].TxVc_Mbs;
1666 + }
1667 + }
1668 +
1669 + if (HalDev->OsFunc->Strstr(Key, "TxVc_AtmHeader.") != 0)
1670 + {
1671 + KeyFound=1;
1672 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1673 + {
1674 + ActionFound=1;
1675 + /* extract channel number */
1676 + TmpKey += HalDev->OsFunc->Strlen("TxVc_AtmHeader.");
1677 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1678 +
1679 + /* first, store new value in our channel structure */
1680 + HalDev->ChData[Ch].TxVc_AtmHeader = *(int *)Value;
1681 +
1682 + /* now, apply to PDSP state RAM */
1683 + if (HalDev->State == enOpened)
1684 + *(pPDSP_AAL5_TX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+6)= HalDev->ChData[Ch].TxVc_AtmHeader;
1685 + }
1686 + }
1687 +
1688 + if (HalDev->OsFunc->Strstr(Key, "TxVp_AtmHeader.") != 0)
1689 + {
1690 + KeyFound=1;
1691 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1692 + {
1693 + ActionFound=1;
1694 + /* extract channel number */
1695 + TmpKey += HalDev->OsFunc->Strlen("TxVp_AtmHeader.");
1696 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1697 +
1698 + /* first, store new value in our channel structure */
1699 + HalDev->ChData[Ch].TxVp_AtmHeader = *(int *)Value;
1700 +
1701 + /* now, apply to PDSP state RAM */
1702 + if (HalDev->State == enOpened)
1703 + *(pPDSP_AAL5_TX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64))= HalDev->ChData[Ch].TxVp_AtmHeader;
1704 + }
1705 + }
1706 +
1707 + /* +GSG 030306 */
1708 + /* Fixes PITS #100 */
1709 + if (HalDev->OsFunc->Strstr(Key, "TxVc_Pcr.") != 0)
1710 + {
1711 + KeyFound=1;
1712 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1713 + {
1714 + ActionFound=1;
1715 + /* extract channel number */
1716 + TmpKey += HalDev->OsFunc->Strlen("TxVc_Pcr.");
1717 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1718 +
1719 + /* first, store new value in our channel structure */
1720 + HalDev->ChData[Ch].TxVc_Pcr = *(int *)Value;
1721 +
1722 + /* now, apply to PDSP state RAM */
1723 + if (HalDev->State == enOpened)
1724 + *(pPDSP_AAL5_TX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+4)= HalDev->ChData[Ch].TxVc_Pcr;
1725 + }
1726 + }
1727 +
1728 + /* +GSG 030428 */
1729 + if (HalDev->OsFunc->Strstr(Key, "RxVc_OamCh.") != 0)
1730 + {
1731 + KeyFound=1;
1732 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1733 + {
1734 + ActionFound=1;
1735 + /* extract channel number */
1736 + TmpKey += HalDev->OsFunc->Strlen("RxVc_OamCh.");
1737 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1738 +
1739 + /* first, store new value in our channel structure */
1740 + HalDev->ChData[Ch].RxVc_OamCh = (*(int *)Value) & 0xff;
1741 +
1742 + /* now, apply to PDSP state RAM */
1743 + if (HalDev->State == enOpened)
1744 + *(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)) |= HalDev->ChData[Ch].RxVc_OamCh;
1745 + }
1746 + }
1747 +
1748 + /* +GSG 030428 */
1749 + if (HalDev->OsFunc->Strstr(Key, "RxVp_OamCh.") != 0)
1750 + {
1751 + KeyFound=1;
1752 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1753 + {
1754 + ActionFound=1;
1755 + /* extract channel number */
1756 + TmpKey += HalDev->OsFunc->Strlen("RxVp_OamCh.");
1757 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1758 +
1759 + /* first, store new value in our channel structure */
1760 + HalDev->ChData[Ch].RxVp_OamCh = (*(int *)Value) & 0xff;
1761 +
1762 + /* now, apply to PDSP state RAM */
1763 + if (HalDev->State == enOpened)
1764 + *(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+1) |= HalDev->ChData[Ch].RxVp_OamCh;
1765 + }
1766 + }
1767 +
1768 + /* +GSG 030304 */
1769 + /* Fixes PITS #98 */
1770 + if (HalDev->OsFunc->Strstr(Key, "PdspEnable") != 0)
1771 + {
1772 + KeyFound=1;
1773 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1774 + {
1775 + ActionFound=1;
1776 +
1777 + /* this variable is controlled by the CPSAR module */
1778 + if (HalDev->State == enOpened)
1779 + {
1780 + rc=HalDev->SarFunc->Control(HalDev->SarDev, "PdspEnable", "Set", Value);
1781 + }
1782 + }
1783 + }
1784 +
1785 + if (HalDev->OsFunc->Strstr(Key, "OamLbTimeout") != 0)
1786 + {
1787 + KeyFound=1;
1788 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1789 + {
1790 + ActionFound=1;
1791 +
1792 + HalDev->OamLbTimeout = *(int *)Value;
1793 + /* this variable is controlled by the CPSAR module */
1794 + if (HalDev->State == enOpened)
1795 + {
1796 + *(pOAM_TIMER_STATE_WORD_0(HalDev->dev_base) + 1) =
1797 + ((HalDev->SarFrequency/1000) * HalDev->OamLbTimeout);
1798 + }
1799 + }
1800 + }
1801 +
1802 + /* +GSG 030306 (PITS #114) */
1803 + if (HalDev->OsFunc->Strstr(Key, "DeviceCPID") != 0)
1804 + {
1805 + KeyFound=1;
1806 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1807 + {
1808 + unsigned int* local = (unsigned int *)Value;
1809 + ActionFound=1;
1810 + /* first, store new value in our hal structure */
1811 + HalDev->DeviceCPID[0] = local[0];
1812 + HalDev->DeviceCPID[1] = local[1];
1813 + HalDev->DeviceCPID[2] = local[2];
1814 + HalDev->DeviceCPID[3] = local[3];
1815 +
1816 + /* now, apply to PDSP state RAM */
1817 + if (HalDev->State == enOpened)
1818 + {
1819 + *(bit32u *)(pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base) + 0) = HalDev->DeviceCPID[0];
1820 + *(bit32u *)(pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base) + 1) = HalDev->DeviceCPID[1];
1821 + *(bit32u *)(pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base) + 2) = HalDev->DeviceCPID[2];
1822 + *(bit32u *)(pOAM_CONFIG_BLOCK_WORD_0(HalDev->dev_base) + 3) = HalDev->DeviceCPID[3];
1823 + }
1824 + }
1825 + }
1826 +
1827 + /* +GSG 030304 */
1828 + /* Fixes PITS #99 */
1829 + if (HalDev->OsFunc->Strstr(Key, "StrictPriority") != 0)
1830 + {
1831 + KeyFound=1;
1832 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1833 + {
1834 + ActionFound=1;
1835 +
1836 + /* used in halOpen to decide which interrupt handler to use */
1837 + HalDev->StrictPriority = *(int *)Value;
1838 + }
1839 + }
1840 +
1841 + if (HalDev->OsFunc->Strstr(Key, hcMaxFrags) != 0)
1842 + {
1843 + KeyFound=1;
1844 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1845 + {
1846 + ActionFound=1;
1847 +
1848 + if ((*(int *)Value) > 0)
1849 + HalDev->MaxFrags = *(int *)Value;
1850 + else
1851 + rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_INVALID_VALUE);
1852 + }
1853 +
1854 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1855 + {
1856 + ActionFound=1;
1857 +
1858 + *(int *)Value = HalDev->MaxFrags;
1859 + }
1860 + }
1861 +
1862 + /* +GSG 030306 */
1863 + /* Fixes PITS #103 */
1864 + if (HalDev->OsFunc->Strstr(Key, "RxVc_RDICount.") != 0)
1865 + {
1866 + KeyFound=1;
1867 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1868 + {
1869 + ActionFound=1;
1870 +
1871 + /* extract channel number */
1872 + TmpKey += HalDev->OsFunc->Strlen("RxVc_RDICount.");
1873 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1874 +
1875 + /* PDSP's Rx VC State word 3 contains the value */
1876 + if (HalDev->State == enOpened)
1877 + {
1878 + *(int *)Value = (((*(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64))) & RDI_CNT_MASK)>>RDI_CNT_SHIFT);
1879 + }
1880 + }
1881 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1882 + {
1883 + ActionFound=1;
1884 +
1885 + /* extract channel number */
1886 + TmpKey += HalDev->OsFunc->Strlen("RxVc_RDICount.");
1887 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1888 +
1889 + /* All sets write 0, this action is a clear only */
1890 + if (HalDev->State == enOpened)
1891 + {
1892 + (*(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64))) &=~ RDI_CNT_MASK;
1893 + }
1894 + }
1895 + }
1896 +
1897 + /* +GSG 030306 */
1898 + /* Fixes PITS #103 */
1899 + if (HalDev->OsFunc->Strstr(Key, "RxVc_AISseg.") != 0)
1900 + {
1901 + KeyFound=1;
1902 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1903 + {
1904 + ActionFound=1;
1905 +
1906 + /* extract channel number */
1907 + TmpKey += HalDev->OsFunc->Strlen("RxVc_AISseg.");
1908 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1909 +
1910 + /* PDSP's Rx VC State word 3 contains the value */
1911 + if (HalDev->State == enOpened)
1912 + {
1913 + *(int *)Value = (((*(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+3)) & AIS_SEG_MASK)>>AIS_SEG_SHIFT);
1914 + }
1915 + }
1916 + }
1917 +
1918 + /* +GSG 030306 */
1919 + /* Fixes PITS #103 */
1920 + if (HalDev->OsFunc->Strstr(Key, "RxVc_AISetoe.") != 0)
1921 + {
1922 + KeyFound=1;
1923 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1924 + {
1925 + ActionFound=1;
1926 +
1927 + /* extract channel number */
1928 + TmpKey += HalDev->OsFunc->Strlen("RxVc_AISetoe.");
1929 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1930 +
1931 + /* PDSP's Rx VC State word 3 contains the value */
1932 + if (HalDev->State == enOpened)
1933 + {
1934 + *(int *)Value = (((*(pPDSP_AAL5_RX_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+3)) & AIS_ETOE_MASK)>>AIS_ETOE_SHIFT);
1935 + }
1936 + }
1937 + }
1938 +
1939 + /* +GSG 030306 */
1940 + /* Fixes PITS #103 */
1941 + if (HalDev->OsFunc->Strstr(Key, "RxVp_RDICount.") != 0)
1942 + {
1943 + KeyFound=1;
1944 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1945 + {
1946 + ActionFound=1;
1947 +
1948 + /* extract channel number */
1949 + TmpKey += HalDev->OsFunc->Strlen("RxVp_RDICount.");
1950 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1951 +
1952 + /* PDSP's Rx VC State word 3 contains the value */
1953 + if (HalDev->State == enOpened)
1954 + {
1955 + *(int *)Value = (((*(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+1)) & RDI_CNT_MASK)>>RDI_CNT_SHIFT);
1956 + }
1957 + }
1958 + if (HalDev->OsFunc->Strcmpi(Action, "Set") == 0)
1959 + {
1960 + ActionFound=1;
1961 +
1962 + /* extract channel number */
1963 + TmpKey += HalDev->OsFunc->Strlen("RxVp_RDICount.");
1964 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1965 +
1966 + /* All sets write 0, this action is a clear only */
1967 + if (HalDev->State == enOpened)
1968 + {
1969 + (*(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+1)) &=~ RDI_CNT_MASK;
1970 + }
1971 + }
1972 + }
1973 +
1974 + /* +GSG 030306 */
1975 + /* Fixes PITS #103 */
1976 + if (HalDev->OsFunc->Strstr(Key, "RxVp_AISseg.") != 0)
1977 + {
1978 + KeyFound=1;
1979 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
1980 + {
1981 + ActionFound=1;
1982 +
1983 + /* extract channel number */
1984 + TmpKey += HalDev->OsFunc->Strlen("RxVp_AISseg.");
1985 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
1986 +
1987 + /* PDSP's Rx VC State word 3 contains the value */
1988 + if (HalDev->State == enOpened)
1989 + {
1990 + *(int *)Value = (((*(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+2)) & AIS_SEG_MASK)>>AIS_SEG_SHIFT);
1991 + }
1992 + }
1993 + }
1994 +
1995 + /* +GSG 030306 */
1996 + /* Fixes PITS #103 */
1997 + if (HalDev->OsFunc->Strstr(Key, "RxVp_AISetoe.") != 0)
1998 + {
1999 + KeyFound=1;
2000 + if (HalDev->OsFunc->Strcmpi(Action, "Get") == 0)
2001 + {
2002 + ActionFound=1;
2003 +
2004 + /* extract channel number */
2005 + TmpKey += HalDev->OsFunc->Strlen("RxVp_AISetoe.");
2006 + Ch = HalDev->OsFunc->Strtoul(TmpKey, &TmpKey, 10);
2007 +
2008 + /* PDSP's Rx VC State word 3 contains the value */
2009 + if (HalDev->State == enOpened)
2010 + {
2011 + *(int *)Value = (((*(pPDSP_AAL5_RX_VP_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+2)) & AIS_ETOE_MASK)>>AIS_ETOE_SHIFT);
2012 + }
2013 + }
2014 + }
2015 +
2016 + if (KeyFound == 0)
2017 + rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_KEY_NOT_FOUND);
2018 +
2019 + if (ActionFound == 0)
2020 + rc = (EC_AAL5|EC_FUNC_CONTROL|EC_VAL_ACTION_NOT_FOUND);
2021 +
2022 + return(rc);
2023 + }
2024 +
2025 +/*
2026 + * Sets up HAL default configuration parameter values.
2027 + */
2028 +static void ConfigInit(HAL_DEVICE *HalDev)
2029 + {
2030 +#ifdef __CPHAL_DEBUG
2031 + if (DBG(0))
2032 + {
2033 + dbgPrintf("[aal5]ConfigInit(HalDev:%08x)\n", (bit32u)HalDev);
2034 + osfuncSioFlush();
2035 + }
2036 +#endif
2037 +
2038 + /* configure some defaults with tnetx7300 values */
2039 + HalDev->dev_base = 0xa3000000;
2040 + HalDev->offset = 0;
2041 + HalDev->interrupt = 15;
2042 + HalDev->debug = 0;
2043 + HalDev->MaxFrags = 46;
2044 + HalDev->OamLbTimeout = 5000;
2045 + }
2046 +
2047 +/*
2048 + * Retrieve HAL configuration parameter values.
2049 + */
2050 +static bit32u ConfigGet(HAL_DEVICE *HalDev)
2051 + {
2052 + bit32u Ret;
2053 +
2054 +#ifdef __CPHAL_DEBUG
2055 + if (DBG(0))
2056 + {
2057 + dbgPrintf("[aal5]ConfigGet(HalDev:%08x)\n", (bit32u)HalDev);
2058 + osfuncSioFlush();
2059 + }
2060 +#endif
2061 +
2062 + /* get the configuration parameters common to all modules */
2063 + Ret = ConfigGetCommon(HalDev);
2064 + if (Ret) return (EC_AAL5|Ret);
2065 +
2066 + /* get AAL5 specific configuration parameters here */
2067 + Ret = HalDev->OsFunc->Control(HalDev->OsDev, hcSarFrequency, pszGET, &HalDev->SarFrequency); /* GSG +030416*/
2068 + if (Ret) /* GSG +030416*/
2069 + HalDev->SarFrequency = 200000000; /* 200 Mhz default */ /* GSG +030416*/
2070 +
2071 + return (EC_NO_ERRORS);
2072 + }
2073 +
2074 +/**
2075 + * @ingroup CPHAL_Functions
2076 + * This function initializes the CPHAL module. It gathers all
2077 + * necessary global configuration info from the configuration file, and
2078 + * performs initialization and configuration of the device. Note that
2079 + * the device operation is not started until the OS calls @c Open().
2080 + *
2081 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2082 + *
2083 + * @return EC_NO_ERRORS (ok). <BR>
2084 + * Possible Error Codes:<BR>
2085 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
2086 + * @ref EC_VAL_BASE_ADDR_NOT_FOUND "EC_VAL_BASE_ADDR_NOT_FOUND"<BR>
2087 + * @ref EC_VAL_RESET_BIT_NOT_FOUND "EC_VAL_RESET_BIT_NOT_FOUND"<BR>
2088 + * @ref EC_VAL_INTERRUPT_NOT_FOUND "EC_VAL_INTERRUPT_NOT_FOUND"<BR>
2089 + * @ref EC_VAL_OFFSET_NOT_FOUND "EC_VAL_OFFSET_NOT_FOUND"<BR>
2090 + */
2091 +static int halInit(HAL_DEVICE *HalDev)
2092 + {
2093 + int i;
2094 + bit32u error_code;
2095 +
2096 +#ifdef __CPHAL_DEBUG
2097 + if (DBG(0))
2098 + {
2099 + dbgPrintf("[aal5]halInit(HalDev:%08x)\n", (bit32u)HalDev);
2100 + osfuncSioFlush();
2101 + }
2102 +#endif
2103 +
2104 + /* Verify proper device state */
2105 + if (HalDev->State != enDevFound)
2106 + return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_INVALID_STATE);
2107 +
2108 + /* Configure HAL defaults */
2109 + ConfigInit(HalDev);
2110 +
2111 + /* Retrieve HAL configuration parameters from data store */
2112 + error_code = ConfigGet(HalDev);
2113 + if (error_code) return (error_code);
2114 +
2115 + /* Other items (OAM related) that need to be passed in somehow */
2116 + HalDev->DeviceCPID[0] = 0xffffffff;
2117 + HalDev->DeviceCPID[1] = 0xffffffff;
2118 + HalDev->DeviceCPID[2] = 0xffffffff;
2119 + HalDev->DeviceCPID[3] = 0xffffffff;
2120 + HalDev->LBSourceLLID[0] = 0xffffffff;
2121 + HalDev->LBSourceLLID[1] = 0xffffffff;
2122 + HalDev->LBSourceLLID[2] = 0xffffffff;
2123 + HalDev->LBSourceLLID[3] = 0xffffffff;
2124 +
2125 + /* Initialize SAR layer*/
2126 + error_code = HalDev->SarFunc->Init(HalDev->SarDev);
2127 + if (error_code) return (error_code);
2128 +
2129 + /* Initialize various HalDev members. This is probably overkill, since these
2130 + are initialized in ChannelSetup() and HalDev is cleared in InitModule(). */
2131 + for (i=0; i<NUM_AAL5_CHAN; i++)
2132 + {
2133 + HalDev->InRxInt[i]=FALSE;
2134 + HalDev->ChIsOpen[i][DIRECTION_TX] = FALSE;
2135 + HalDev->ChIsOpen[i][DIRECTION_RX] = FALSE;
2136 + HalDev->TcbStart[i][0] = 0;
2137 + HalDev->TcbStart[i][1] = 0;
2138 + HalDev->RcbStart[i] = 0;
2139 + }
2140 +
2141 + /* initialize SAR stats */
2142 + StatsClear(HalDev);
2143 +
2144 + /* init Stat pointers */
2145 +
2146 + /* even though these statistics may be for multiple channels/queues, i need
2147 + only configure the pointer to the beginning of the array, and I can index
2148 + from there if necessary */
2149 + StatsTable0[0].StatPtr = &HalDev->Stats.CrcErrors[0];
2150 + StatsTable0[1].StatPtr = &HalDev->Stats.LenErrors[0];
2151 + StatsTable0[2].StatPtr = &HalDev->Stats.AbortErrors[0];
2152 + StatsTable0[3].StatPtr = &HalDev->Stats.StarvErrors[0];
2153 +
2154 + StatsTable1[0].StatPtr = &HalDev->Stats.DmaLenErrors[0];
2155 + StatsTable1[1].StatPtr = &HalDev->Stats.TxMisQCnt[0][0];
2156 + StatsTable1[2].StatPtr = &HalDev->Stats.RxMisQCnt[0];
2157 + StatsTable1[3].StatPtr = &HalDev->Stats.TxEOQCnt[0][0];
2158 + StatsTable1[4].StatPtr = &HalDev->Stats.RxEOQCnt[0];
2159 + StatsTable1[5].StatPtr = &HalDev->Stats.RxPacketsServiced[0];
2160 + StatsTable1[6].StatPtr = &HalDev->Stats.TxPacketsServiced[0][0];
2161 + StatsTable1[7].StatPtr = &HalDev->Stats.RxMaxServiced;
2162 + StatsTable1[8].StatPtr = &HalDev->Stats.TxMaxServiced[0][0];
2163 + StatsTable1[9].StatPtr = &HalDev->Stats.RxTotal;
2164 + StatsTable1[10].StatPtr = &HalDev->Stats.TxTotal;
2165 +
2166 + StatsTable2[0].StatPtr = (bit32u *)&HalDev->RcbPool[0];
2167 + StatsTable2[1].StatPtr = &HalDev->RxActQueueCount[0];
2168 + StatsTable2[2].StatPtr = (bit32u *)&HalDev->RxActQueueHead[0];
2169 + StatsTable2[3].StatPtr = (bit32u *)&HalDev->RxActQueueTail[0];
2170 + StatsTable2[4].StatPtr = &HalDev->RxActive[0];
2171 + StatsTable2[5].StatPtr = (bit32u *)&HalDev->RcbStart[0];
2172 + StatsTable2[6].StatPtr = &HalDev->RxTeardownPending[0];
2173 + StatsTable2[7].StatPtr = (bit32u *)&HalDev->TcbPool[0][0];
2174 + StatsTable2[8].StatPtr = &HalDev->TxActQueueCount[0][0];
2175 + StatsTable2[9].StatPtr = (bit32u *)&HalDev->TxActQueueHead[0][0];
2176 + StatsTable2[10].StatPtr = (bit32u *)&HalDev->TxActQueueTail[0][0];
2177 + StatsTable2[11].StatPtr = &HalDev->TxActive[0][0];
2178 + StatsTable2[12].StatPtr = (bit32u *)&HalDev->TcbStart[0][0];
2179 + StatsTable2[13].StatPtr = &HalDev->TxTeardownPending[0];
2180 +
2181 + StatsTable4[0].StatPtr = &HalDev->dev_base;
2182 + StatsTable4[1].StatPtr = &HalDev->offset;
2183 + StatsTable4[2].StatPtr = &HalDev->interrupt;
2184 + StatsTable4[3].StatPtr = &HalDev->debug;
2185 + StatsTable4[4].StatPtr = &HalDev->Inst;
2186 +
2187 + StatsTable3[0].StatPtr = &HalDev->ChData[0].RxBufSize;
2188 + StatsTable3[1].StatPtr = &HalDev->ChData[0].RxBufferOffset;
2189 + StatsTable3[2].StatPtr = &HalDev->ChData[0].RxNumBuffers;
2190 + StatsTable3[3].StatPtr = &HalDev->ChData[0].RxServiceMax;
2191 + StatsTable3[4].StatPtr = &HalDev->ChData[0].TxNumBuffers;
2192 + StatsTable3[5].StatPtr = &HalDev->ChData[0].TxNumQueues;
2193 + StatsTable3[6].StatPtr = &HalDev->ChData[0].TxServiceMax;
2194 + StatsTable3[7].StatPtr = &HalDev->ChData[0].CpcsUU;
2195 + StatsTable3[8].StatPtr = &HalDev->ChData[0].Gfc;
2196 + StatsTable3[9].StatPtr = &HalDev->ChData[0].Clp;
2197 + StatsTable3[10].StatPtr = &HalDev->ChData[0].Pti;
2198 + StatsTable3[11].StatPtr = &HalDev->ChData[0].DaMask;
2199 + StatsTable3[12].StatPtr = &HalDev->ChData[0].Priority;
2200 + StatsTable3[13].StatPtr = &HalDev->ChData[0].PktType;
2201 + StatsTable3[14].StatPtr = &HalDev->ChData[0].Vci;
2202 + StatsTable3[15].StatPtr = &HalDev->ChData[0].Vpi;
2203 + StatsTable3[16].StatPtr = &HalDev->ChData[0].TxVc_CellRate;
2204 + StatsTable3[17].StatPtr = &HalDev->ChData[0].TxVc_QosType;
2205 + StatsTable3[18].StatPtr = &HalDev->ChData[0].TxVc_Mbs;
2206 + StatsTable3[19].StatPtr = &HalDev->ChData[0].TxVc_Pcr;
2207 +
2208 + /* update device state */
2209 + HalDev->State = enInitialized;
2210 +
2211 +#ifdef __CPHAL_DEBUG
2212 + if (DBG(9))
2213 + dbgConfigDump(HalDev);
2214 +#endif
2215 +
2216 + return(EC_NO_ERRORS);
2217 + }
2218 +
2219 +/*
2220 + * Use this function to actually send after queuing multiple packets using
2221 + * Send(). This is a debug only function that should be removed - it was
2222 + * necessary to properly implement my loopback tests.
2223 + *
2224 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2225 + * @param Queue Queue number to kick.
2226 + *
2227 + * @return 0 OK, Non-Zero Not OK
2228 + */
2229 +static int halKick(HAL_DEVICE *HalDev, int Queue)
2230 + {
2231 + int Ch;
2232 +
2233 +#ifdef __CPHAL_DEBUG
2234 + if (DBG(0))
2235 + {
2236 + dbgPrintf("[aal5]halKick(HalDev:%08x. Queue:%d)\n", (bit32u)HalDev, Queue);
2237 + osfuncSioFlush();
2238 + }
2239 +#endif
2240 +
2241 + for (Ch = 0; Ch < 16; Ch ++)
2242 + {
2243 + if ((!HalDev->TxActive[Ch][Queue]) && (HalDev->TxActQueueHead[Ch][Queue] != 0))
2244 + {
2245 + *(pTX_DMA_STATE_WORD_0(HalDev->dev_base)+(Ch*64)+Queue)=
2246 + VirtToPhys(HalDev->TxActQueueHead[Ch][Queue]);
2247 + HalDev->TxActive[Ch][Queue]=TRUE;
2248 + }
2249 + }
2250 +
2251 + return (EC_NO_ERRORS);
2252 + }
2253 +
2254 +/* +GSG 030305 For PITS #99
2255 + * Alternate interrupt handler that uses the INT_VECTOR in order to
2256 + * provide strict priority handling among channels, beginning with Ch 0.
2257 + *
2258 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2259 + * @param MoreWork (Output) When set to 1, indicates that there is more work to do.
2260 + * Caller should ensure that the value pointed at is set to 0
2261 + * prior to the call.
2262 + * @return 0 OK, non-zero error.
2263 + */
2264 +static int DeviceIntAlt(HAL_DEVICE *HalDev, int *MoreWork)
2265 + {
2266 + int tmp, Ch, WorkFlag;
2267 + bit32u rc;
2268 +
2269 +#ifdef __CPHAL_DEBUG
2270 + if (DBG(0))
2271 + {
2272 + dbgPrintf("[aal5]DeviceIntAlt(HalDev:%08x, MoreWork:%08x)\n", (bit32u)HalDev, (bit32u)MoreWork);
2273 + osfuncSioFlush();
2274 + }
2275 +#endif
2276 +
2277 + /* Verify proper device state - important because a call prior to Open would
2278 + result in a lockup */
2279 + if (HalDev->State != enOpened)
2280 + return(EC_AAL5|EC_FUNC_DEVICE_INT_ALT|EC_VAL_INVALID_STATE);
2281 +
2282 + if ((tmp=SAR_INTR_VECTOR(HalDev->dev_base))&INT_PENDING)
2283 + {
2284 + /*printf("\015 %d RxQ",HalDev->RxActQueueCount[0]);
2285 + HalDev->OsFunc->Control(HalDev->OsDev, enSIO_FLUSH, enNULL, 0); */
2286 +
2287 + if (tmp&TXH_PEND)
2288 + {
2289 + /* decide which channel to service */
2290 + Ch = (SAR_INTR_VECTOR(HalDev->dev_base) & TXH_PEND_INVEC);
2291 +
2292 + rc = TxInt(HalDev,Ch,0,&WorkFlag);
2293 + if (rc) return (rc);
2294 +
2295 + if (WorkFlag == 1)
2296 + *MoreWork = 1;
2297 + }
2298 +
2299 + if (tmp&TXL_PEND)
2300 + {
2301 + /* decide which channel to service */
2302 + Ch = ((SAR_INTR_VECTOR(HalDev->dev_base) & TXL_PEND_INVEC) >> 4);
2303 +
2304 + rc = TxInt(HalDev,Ch,1,&WorkFlag);
2305 + if (rc) return (rc);
2306 +
2307 + if (WorkFlag == 1)
2308 + *MoreWork = 1;
2309 + }
2310 +
2311 + if (tmp&RX_PEND)
2312 + {
2313 + /* decide which channel to service */
2314 + Ch = ((SAR_INTR_VECTOR(HalDev->dev_base) & RX_PEND_INVEC) >> 8);
2315 +
2316 + rc = RxInt(HalDev,Ch,&WorkFlag);
2317 + if (rc) return (rc);
2318 +
2319 + if (WorkFlag == 1)
2320 + *MoreWork = 1;
2321 + }
2322 +
2323 + if (tmp&STS_PEND)
2324 + {
2325 + /* GPR 2 code added for PITS 103 */
2326 + /* determine interrupt source */
2327 + Ch = ((SAR_INTR_VECTOR(HalDev->dev_base) & STS_PEND_INVEC) >> 12);
2328 +
2329 + /* only if this is GPR 2 interrupt do we take action */
2330 + if (Ch == 26)
2331 + {
2332 + /* pass loopback result back to OS */
2333 + HalDev->OsFunc->Control(HalDev->OsDev, "OamLbResult", "Set",
2334 + (bit32u *)pSAR_PDSP_OAM_LB_RESULT_REG(HalDev->dev_base));
2335 + }
2336 +
2337 + /* clear the interrupt */
2338 + SAR_STATUS_CLR_REG(HalDev->dev_base) |= 0x04000000;
2339 + }
2340 +
2341 + if (tmp&AAL2_PEND)
2342 + {
2343 + /* no action defined */
2344 + }
2345 +
2346 + SAR_INTR_VECTOR(HalDev->dev_base) = 0;
2347 + }
2348 +
2349 + return (EC_NO_ERRORS);
2350 + }
2351 +
2352 +/*
2353 + * Called to service a module interrupt. This function determines
2354 + * what type of interrupt occurred and dispatches the correct handler.
2355 + *
2356 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2357 + * @param MoreWork (Output) When set to 1, indicates that there is more work to do.
2358 + * Caller should ensure that the value pointed at is set to 0
2359 + * prior to the call.
2360 + * @return 0 OK, non-zero error.
2361 + */
2362 +static int DeviceInt(HAL_DEVICE *HalDev, int *MoreWork)
2363 + {
2364 + /*static int NextRxCh=0;
2365 + static int NextTxCh[2]={0,0};*/
2366 +
2367 + int tmp, Ch, FirstCh, WorkFlag;
2368 + int NextTxLCh, NextTxHCh, NextRxCh;
2369 + bit32u rc;
2370 +
2371 +#ifdef __CPHAL_DEBUG
2372 + if (DBG(0))
2373 + {
2374 + dbgPrintf("[aal5]DeviceInt(HalDev:%08x, MoreWork:%08x)\n", (bit32u)HalDev, (bit32u)MoreWork);
2375 + osfuncSioFlush();
2376 + }
2377 +#endif
2378 +
2379 + /* Verify proper device state - important because a call prior to Open would
2380 + result in a lockup */
2381 + if (HalDev->State != enOpened)
2382 + return(EC_AAL5|EC_FUNC_DEVICE_INT|EC_VAL_INVALID_STATE);
2383 +
2384 + NextTxHCh = HalDev->NextTxCh[0];
2385 + NextTxLCh = HalDev->NextTxCh[1];
2386 + NextRxCh = HalDev->NextRxCh;
2387 +
2388 + /* service interrupts while there is more work to do */
2389 + /*while (((tmp=SAR_INTR_VECTOR(HalDev->dev_base))&INT_PENDING) && (TotalPkts < 500))*/
2390 + if ((tmp=SAR_INTR_VECTOR(HalDev->dev_base))&INT_PENDING)
2391 + {
2392 + /*printf("\015 %d RxQ",HalDev->RxActQueueCount[0]);
2393 + HalDev->OsFunc->Control(HalDev->OsDev, enSIO_FLUSH, enNULL, 0); */
2394 +
2395 + if (tmp&TXH_PEND)
2396 + {
2397 + /* decide which channel to service */
2398 + FirstCh = NextTxHCh;
2399 + while (1)
2400 + {
2401 + Ch = NextTxHCh++;
2402 + if (NextTxHCh == 16)
2403 + NextTxHCh = 0;
2404 + if (SAR_TX_MASKED_STATUS(HalDev->dev_base) & (1<<Ch))
2405 + break;
2406 + if (FirstCh == NextTxHCh)
2407 + {
2408 + /* we checked every channel and still haven't found anything to do */
2409 + return (EC_AAL5|EC_FUNC_DEVICE_INT|EC_VAL_NO_TXH_WORK_TO_DO);
2410 + }
2411 + }
2412 +
2413 + rc = TxInt(HalDev,Ch,0,&WorkFlag);
2414 + if (rc) return (rc);
2415 +
2416 + if (WorkFlag == 1)
2417 + *MoreWork = 1;
2418 + }
2419 +
2420 + if (tmp&TXL_PEND)
2421 + {
2422 + /* decide which channel to service */
2423 + FirstCh = NextTxLCh;
2424 + while (1)
2425 + {
2426 + Ch = NextTxLCh++;
2427 + if (NextTxLCh == 16)
2428 + NextTxLCh = 0;
2429 + if (SAR_TX_MASKED_STATUS(HalDev->dev_base) & (1<<(Ch+16)))
2430 + break;
2431 + if (FirstCh == NextTxLCh)
2432 + {
2433 + /* we checked every channel and still haven't found anything to do */
2434 + return (EC_AAL5|EC_FUNC_DEVICE_INT|EC_VAL_NO_TXL_WORK_TO_DO);
2435 + }
2436 + }
2437 +
2438 + rc = TxInt(HalDev,Ch,1,&WorkFlag);
2439 + if (rc) return (rc);
2440 +
2441 + if (WorkFlag == 1)
2442 + *MoreWork = 1;
2443 + }
2444 +
2445 + if (tmp&RX_PEND)
2446 + {
2447 + FirstCh = NextRxCh;
2448 + while (1)
2449 + {
2450 + Ch = NextRxCh++;
2451 + if (NextRxCh == 16)
2452 + NextRxCh = 0;
2453 + if (SAR_RX_MASKED_STATUS(HalDev->dev_base) & (1 << Ch))
2454 + break; /* found a channel to service */
2455 + if (FirstCh == NextRxCh)
2456 + {
2457 + /* we checked every channel and still haven't found anything to do */
2458 + return (EC_AAL5|EC_FUNC_DEVICE_INT|EC_VAL_NO_RX_WORK_TO_DO);
2459 + }
2460 + }
2461 +
2462 + rc = RxInt(HalDev,Ch, &WorkFlag);
2463 + if (rc) return (rc);
2464 +
2465 + if (WorkFlag == 1)
2466 + *MoreWork = 1;
2467 + }
2468 +
2469 + if (tmp&STS_PEND)
2470 + {
2471 + /* +GSG 030305 */
2472 + /* GPR 2 code added for PITS 103 */
2473 + /* determine interrupt source */
2474 + Ch = ((SAR_INTR_VECTOR(HalDev->dev_base) & STS_PEND_INVEC) >> 12);
2475 +
2476 + /* only if this is GPR 2 interrupt do we take action */
2477 + if (Ch == 26)
2478 + {
2479 + /* pass loopback result back to OS */
2480 + HalDev->OsFunc->Control(HalDev->OsDev, "OamLbResult", "Set",
2481 + (bit32u *)pSAR_PDSP_OAM_LB_RESULT_REG(HalDev->dev_base));
2482 + }
2483 +
2484 + /* clear the interrupt */
2485 + SAR_STATUS_CLR_REG(HalDev->dev_base) |= 0x04000000;
2486 + }
2487 +
2488 + if (tmp&AAL2_PEND)
2489 + {
2490 + /* no action defined */
2491 + }
2492 +
2493 + SAR_INTR_VECTOR(HalDev->dev_base) = 0;
2494 + }
2495 +
2496 + HalDev->NextTxCh[0] = NextTxHCh;
2497 + HalDev->NextTxCh[1] = NextTxLCh;
2498 + HalDev->NextRxCh = NextRxCh;
2499 +
2500 + /* This must be done by the upper layer */
2501 + /* SAR_EOI(HalDev->dev_base) = 0; */
2502 +
2503 + return (EC_NO_ERRORS);
2504 + }
2505 +
2506 +/**
2507 + * @ingroup CPHAL_Functions
2508 + * This function starts the operation of the CPHAL device. It takes the device
2509 + * out of reset, and calls @c IsrRegister(). This function should be called after
2510 + * calling the @c Init() function.
2511 + *
2512 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2513 + *
2514 + * @return EC_NO_ERRORS (ok).<BR>
2515 + * Possible Error Codes:<BR>
2516 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
2517 + * @ref EC_VAL_KEY_NOT_FOUND "EC_VAL_KEY_NOT_FOUND"<BR>
2518 + * @ref EC_VAL_FIRMWARE_TOO_LARGE "EC_VAL_FIRMWARE_TOO_LARGE"<BR>
2519 + * @ref EC_VAL_PDSP_LOAD_FAIL "EC_VAL_PDSP_LOAD_FAIL"<BR>
2520 + * @ref EC_VAL_RX_STATE_RAM_NOT_CLEARED "EC_VAL_RX_STATE_RAM_NOT_CLEARED"<BR>
2521 + * @ref EC_VAL_TX_STATE_RAM_NOT_CLEARED "EC_VAL_TX_STATE_RAM_NOT_CLEARED"<BR>
2522 + * @ref EC_VAL_TCB_MALLOC_FAILED "EC_VAL_TCB_MALLOC_FAILED"<BR>
2523 + * @ref EC_VAL_RCB_MALLOC_FAILED "EC_VAL_RCB_MALLOC_FAILED"<BR>
2524 + * @ref EC_VAL_RX_BUFFER_MALLOC_FAILED "EC_VAL_RX_BUFFER_MALLOC_FAILED"<BR>
2525 + * @ref EC_VAL_LUT_NOT_READY "EC_VAL_LUT_NOT_READY"<BR>
2526 + */
2527 +static int halOpen(HAL_DEVICE *HalDev)
2528 + {
2529 + int i,Ret;
2530 + bit32 SarBase = HalDev->dev_base;
2531 +
2532 +#ifdef __CPHAL_DEBUG
2533 + if (DBG(0))
2534 + {
2535 + dbgPrintf("[aal5]halOpen(HalDev:%08x)\n", (bit32u)HalDev);
2536 + osfuncSioFlush();
2537 + }
2538 +#endif
2539 +
2540 + /* Verify proper device state */
2541 + if (HalDev->State < enInitialized)
2542 + return (EC_AAL5|EC_FUNC_OPEN|EC_VAL_INVALID_STATE);
2543 +
2544 + /* Open the SAR (this brings the whole device out of reset */
2545 + Ret = HalDev->SarFunc->Open(HalDev->SarDev); /* ~GSG 030410 */
2546 + if (Ret) /* +GSG 030410 */
2547 + return (Ret); /* +GSG 030410 */
2548 +
2549 + /* Change device state */
2550 + HalDev->State = enOpened;
2551 +
2552 +
2553 +#ifdef __CPHAL_DEBUG
2554 + /* print out the version information */
2555 + if (DBG(7))
2556 + {
2557 + dbgPrintf("[aal5 halOpen()]Module ID(AAL5-CPSAR):%d, Version:%2d.%02d\n",
2558 + (SAR_ID_REG(SarBase)&0xffff0000)>>16,
2559 + (SAR_ID_REG(SarBase)&0xff00)>>8,
2560 + SAR_ID_REG(SarBase)&0xff);
2561 + osfuncSioFlush();
2562 + }
2563 +#endif
2564 +
2565 + /* GREG 11/1/02: The State RAM clearing code was previously in cpsar.c,
2566 + directly after device reset. I moved it here because I believe it is
2567 + AAL5 specific code. Also the MAX_CHAN was set to 19 in cpsar.c, which
2568 + would have caused this code to clear too much memory! */
2569 +
2570 + /* NOTE: State RAM must be cleared prior to initializing the PDSP!! */
2571 +
2572 + /* GSG 030416: Removed all of this. All PDSP State RAM is cleared
2573 + in CPSAR Open(). On Close(), all channels are torndown, thus all
2574 + AAL5 channel state RAM is cleared. */
2575 +
2576 + /* Clear Rx State RAM */
2577 + /*for (i=0; i<NUM_AAL5_CHAN; i++)
2578 + for (j=0; j<NUM_RX_STATE_WORDS; j++)
2579 + *(pRX_DMA_STATE_WORD_0(SarBase) + (i*64) + j) = 0; */
2580 +
2581 + /* Check that Rx DMA State RAM was cleared */
2582 + /*for (i=0; i<NUM_AAL5_CHAN; i++)
2583 + for (j=0; j<NUM_RX_STATE_WORDS; j++)
2584 + {
2585 + if (*(pRX_DMA_STATE_WORD_0(SarBase) + (i*64) + j) != 0)
2586 + {
2587 + return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_RX_STATE_RAM_NOT_CLEARED);
2588 + }
2589 + }*/
2590 +
2591 + /* Clear Tx State RAM */
2592 + /*for (i=0; i<NUM_AAL5_CHAN; i++)
2593 + for (j=0; j<NUM_TX_STATE_WORDS; j++)
2594 + {
2595 + *(pTX_DMA_STATE_WORD_0(SarBase) + (i*64) + j) = 0;
2596 + }*/
2597 +
2598 + /* Check that Tx DMA State RAM was cleared */
2599 + /*for (i=0; i<NUM_AAL5_CHAN; i++)
2600 + for (j=0; j<NUM_TX_STATE_WORDS; j++)
2601 + {
2602 + if (*(pTX_DMA_STATE_WORD_0(SarBase) + (i*64) + j) != 0)
2603 + {
2604 + return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_TX_STATE_RAM_NOT_CLEARED);
2605 + }
2606 + }*/
2607 +
2608 + /* GSG +030523 Malloc space for the Rx fraglist */
2609 + HalDev->fraglist = HalDev->OsFunc->Malloc(HalDev->MaxFrags * sizeof(FRAGLIST));
2610 +
2611 + /* For any channels that have been pre-initialized, set them up now */
2612 + for (i=0; i<NUM_AAL5_CHAN; i++)
2613 + {
2614 + if ((HalDev->ChIsSetup[i][0]==TRUE) && (HalDev->ChIsOpen[i][0]==FALSE))
2615 + {
2616 + CHANNEL_INFO HalChn;
2617 + HalChn.Channel = i;
2618 + Ret = ChannelConfigApply(HalDev, &HalChn);
2619 + if (Ret) return (Ret);
2620 + }
2621 + }
2622 +
2623 + /* OAM code would be a candidate to go into ConfigApply */
2624 +
2625 + /* Configure OAM Timer State Block */
2626 + OamRateConfig(HalDev); /* +GSG 030416 */
2627 +
2628 + /* Setup OAM Configuration Block */
2629 + for (i=0; i<8; i++) /* ~GSG 030603 4->8 */
2630 + {
2631 + if (i < 4)
2632 + *(pOAM_CONFIG_BLOCK_WORD_0(SarBase) + i) = HalDev->DeviceCPID[i];
2633 + else
2634 + *(pOAM_CONFIG_BLOCK_WORD_0(SarBase) + i) = HalDev->LBSourceLLID[i-4];
2635 + }
2636 +
2637 + /* Setup OAM Padding Block */
2638 + for (i=0; i<12; i++)
2639 + {
2640 + *(pOAM_PADDING_BLOCK_WORD_0(SarBase) + i) = ((i==11)?0x6a6a0000:0x6a6a6a6a);
2641 + }
2642 +
2643 + /* Enable Tx CPPI DMA */
2644 + TX_CPPI_CTL_REG(HalDev->dev_base) = 1;
2645 +
2646 + /* Enable Rx CPPI DMA */
2647 + RX_CPPI_CTL_REG(HalDev->dev_base) = 1;
2648 +
2649 + /* +GSG 030306 */
2650 + /* Fix for PITS 103 */
2651 + /* Enable Host Interrupt for GPR 2 (OAM LB result register) */
2652 + SAR_HOST_INT_EN_SET_REG(HalDev->dev_base) |= 0x04000000;
2653 +
2654 + /* +GSG 030304 to fix PITS 99 (if block is new)*/
2655 + if (HalDev->StrictPriority == 1)
2656 + {
2657 +#ifdef __CPHAL_DEBUG
2658 + if (DBG(1))
2659 + {
2660 + dbgPrintf("[aal5->os]IsrRegister(OsDev:%08x, halIsr:%08x, Interrupt:%d)\n",
2661 + (bit32u)HalDev->OsDev, (bit32u)DeviceIntAlt, HalDev->interrupt);
2662 + osfuncSioFlush();
2663 + }
2664 +#endif
2665 +
2666 + /* "register" the interrupt handler */
2667 + HalDev->OsFunc->IsrRegister(HalDev->OsDev, DeviceIntAlt, HalDev->interrupt);
2668 + }
2669 + else /* +GSG 030306 */
2670 + { /* +GSG 030306 */
2671 +#ifdef __CPHAL_DEBUG
2672 + if (DBG(1))
2673 + {
2674 + dbgPrintf("[aal5->os]IsrRegister(OsDev:%08x, halIsr:%08x, Interrupt:%d)\n",
2675 + (bit32u)HalDev->OsDev, (bit32u)DeviceInt, HalDev->interrupt);
2676 + osfuncSioFlush();
2677 + }
2678 +#endif
2679 +
2680 + /* "register" the interrupt handler */
2681 + HalDev->OsFunc->IsrRegister(HalDev->OsDev, DeviceInt, HalDev->interrupt);
2682 + } /* +GSG 030306 */
2683 +
2684 + return(EC_NO_ERRORS);
2685 + }
2686 +
2687 +/**
2688 + * @ingroup CPHAL_Functions
2689 + * Called to retrigger the interrupt mechanism after packets have been
2690 + * processed. Call this function when the HalISR function indicates that
2691 + * there is no more work to do. Proper use of this function will guarantee
2692 + * that interrupts are never missed.
2693 + *
2694 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2695 + *
2696 + * @return EC_NO_ERRORS (ok). <BR>
2697 + */
2698 +static int halPacketProcessEnd(HAL_DEVICE *HalDev)
2699 + {
2700 +#ifdef __CPHAL_DEBUG
2701 + if (DBG(0))
2702 + {
2703 + dbgPrintf("[aal5]halPacketProcessEnd(HalDev:%08x)\n", (bit32u)HalDev);
2704 + osfuncSioFlush();
2705 + }
2706 +#endif
2707 +
2708 + SAR_EOI(HalDev->dev_base) = 0;
2709 + return (EC_NO_ERRORS);
2710 + }
2711 +
2712 +/**
2713 + * @ingroup CPHAL_Functions
2714 + * This function probes for the instance of the CPHAL module. It will call
2715 + * the OS function @c DeviceFindInfo() to get the information required.
2716 + *
2717 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2718 + *
2719 + * @return EC_NO_ERRORS (ok). <BR>
2720 + * Possible Error Codes:<BR>
2721 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
2722 + * @ref EC_VAL_DEVICE_NOT_FOUND "EC_VAL_DEVICE_NOT_FOUND"<BR>
2723 + */
2724 +static int halProbe(HAL_DEVICE *HalDev)
2725 + {
2726 + int Ret;
2727 +
2728 +#ifdef __CPHAL_DEBUG
2729 + if (DBG(0))
2730 + {
2731 + dbgPrintf("[aal5]halProbe(HalDev:%08x)\n", (bit32u)HalDev);
2732 + osfuncSioFlush();
2733 + }
2734 +#endif
2735 +
2736 + /* Verify hardware state is "enConnected */
2737 + if (HalDev->State != enConnected)
2738 + return (EC_AAL5|EC_FUNC_PROBE|EC_VAL_INVALID_STATE);
2739 +
2740 +#ifdef __CPHAL_DEBUG
2741 + if (DBG(1))
2742 + {
2743 + dbgPrintf("[aal5->os]DeviceFindInfo(Inst:%d, DeviceName:%s, DeviceInfo:%08x)\n",
2744 + HalDev->Inst, "aal5", (bit32u)&HalDev->DeviceInfo);
2745 + osfuncSioFlush();
2746 + }
2747 +#endif
2748 +
2749 + /* Attempt to find the device information */
2750 + Ret = HalDev->OsFunc->DeviceFindInfo(HalDev->Inst, "aal5", &HalDev->DeviceInfo);
2751 + if (Ret)
2752 + return(EC_AAL5|EC_FUNC_PROBE|EC_VAL_DEVICE_NOT_FOUND);
2753 +
2754 + /* Call Probe for supporting CPSAR layer */
2755 + Ret = HalDev->SarFunc->Probe(HalDev->SarDev);
2756 + if (Ret)
2757 + return(Ret);
2758 +
2759 + /* Set device state to DevFound */
2760 + HalDev->State = enDevFound;
2761 +
2762 + return(EC_NO_ERRORS);
2763 + }
2764 +
2765 +/**
2766 + * @ingroup CPHAL_Functions
2767 + * This function shuts down the CPHAL module completely. The caller must call
2768 + * Close() to put the device in reset prior shutting down. This call will free
2769 + * the HalDev and the HAL function pointer structure, effectively ending
2770 + * communications between the driver and the CPHAL. Further use of the module
2771 + * must be initiated by a call to xxxInitModule(), which starts the entire process
2772 + * over again.
2773 + *
2774 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2775 + *
2776 + * @return EC_NO_ERRORS (ok). <BR>
2777 + * Possible Error Codes:<BR>
2778 + * Any error code from halClose().<BR>
2779 + */
2780 +static int halShutdown(HAL_DEVICE *HalDev)
2781 + {
2782 + int Ch, Queue; /*GSG+030514*/
2783 +
2784 +#ifdef __CPHAL_DEBUG
2785 + if (DBG(0))
2786 + {
2787 + dbgPrintf("[aal5]halShutdown(HalDev:%08x)\n", (bit32u)HalDev);
2788 + osfuncSioFlush();
2789 + }
2790 +#endif
2791 +
2792 + /* Verify proper device state */
2793 + if (HalDev->State == enOpened)
2794 + halClose(HalDev, 3); /*GSG+030429*/
2795 +
2796 + /* Buffer/descriptor resources may still need to be freed if a Close
2797 + Mode 1 was performed prior to Shutdown - clean up here */ /*GSG+030514*/
2798 + for (Ch=0; Ch<NUM_AAL5_CHAN; Ch++)
2799 + {
2800 + if (HalDev->RcbStart[Ch] != 0)
2801 + FreeRx(HalDev,Ch);
2802 +
2803 + for(Queue=0; Queue<MAX_QUEUE; Queue++)
2804 + {
2805 + if (HalDev->TcbStart[Ch][Queue] != 0)
2806 + FreeTx(HalDev,Ch,Queue);
2807 + }
2808 + }
2809 +
2810 + /* shutdown the CPSAR layer */
2811 + HalDev->SarFunc->Shutdown(HalDev->SarDev);
2812 +
2813 +#ifdef __CPHAL_DEBUG
2814 + if (DBG(6))
2815 + {
2816 + dbgPrintf(" [aal5 halShutdown()]Free AAL5 function pointers\n");
2817 + osfuncSioFlush();
2818 + }
2819 + if (DBG(1)||DBG(3))
2820 + {
2821 + dbgPrintf("[aal5->os]Free(MemPtr:%08x)\n", (bit32u)HalDev->HalFuncPtr);
2822 + osfuncSioFlush();
2823 + }
2824 +#endif
2825 + /* free the HalFunc */
2826 + HalDev->OsFunc->Free(HalDev->HalFuncPtr);
2827 +
2828 +#ifdef __CPHAL_DEBUG
2829 + if (DBG(6))
2830 + {
2831 + dbgPrintf(" [aal5 halShutdown]Free HalDev\n");
2832 + osfuncSioFlush();
2833 + }
2834 + if (DBG(1)||DBG(3))
2835 + {
2836 + dbgPrintf("[aal5->os]Free(MemPtr:%08x)\n", (bit32u)HalDev);
2837 + osfuncSioFlush();
2838 + }
2839 +#endif
2840 + /* free the HAL device */
2841 + HalDev->OsFunc->FreeDev(HalDev);
2842 +
2843 + return(EC_NO_ERRORS);
2844 + }
2845 +
2846 +/**
2847 + * @ingroup CPHAL_Functions
2848 + * Used to perform regular checks on the device. This function should be
2849 + * called at a regular interval specified by the @c Tick parameter.
2850 + *
2851 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
2852 + *
2853 + * @return EC_NO_ERRORS (ok).<BR>
2854 + * Possible Error Codes:<BR>
2855 + * @ref EC_VAL_INVALID_STATE "EC_VAL_INVALID_STATE"<BR>
2856 + */
2857 +static int halTick(HAL_DEVICE *HalDev)
2858 + {
2859 +#ifdef __CPHAL_DEBUG
2860 + if (DBG(0))
2861 + {
2862 + dbgPrintf("[aal5]halTick(HalDev:%08x)\n", (bit32u)HalDev);
2863 + osfuncSioFlush();
2864 + }
2865 +#endif
2866 +
2867 + if (HalDev->State != enOpened)
2868 + return(EC_AAL5|EC_FUNC_TICK|EC_VAL_INVALID_STATE);
2869 +
2870 + return(EC_NO_ERRORS);
2871 + }
2872 +
2873 +/**
2874 + * @ingroup CPHAL_Functions
2875 + *
2876 + * This function will:
2877 + * -# allocate a HalDev that will be used by the OS for future communications with the device
2878 + * -# save OsDev for use when calling OS functions
2879 + * -# allocate and populate HalFunc with the addresses of CPHAL functions.
2880 + * -# check OsFuncSize to see if it meets the minimum requirement.
2881 + * -# return the size of the HAL_FUNCTIONS structure through the HalFuncSize pointer. The OS
2882 + * should check this value to ensure that the HAL meets its minimum requirement.
2883 + *
2884 + * Version checking between the OS and the CPHAL is done using the OsFuncSize and
2885 + * HalFuncSize. Future versions of the CPHAL may add new functions to either
2886 + * HAL_FUNCTIONS or OS_FUNCTIONS, but will never remove functionality. This enables
2887 + * both the HAL and OS to check the size of the function structure to ensure that
2888 + * the current OS and CPHAL are compatible.
2889 + *
2890 + * Note: This is the only function exported by a CPHAL module.
2891 + *
2892 + * Please refer to the section "@ref hal_init" for example code.
2893 + *
2894 + * @param HalDev Pointer to pointer to CPHAL module information. This will
2895 + * be used by the OS when communicating to this module via
2896 + * CPHAL. Allocated during the call.
2897 + * @param OsDev Pointer to OS device information. This will be saved by
2898 + * the CPHAL and returned to the OS when required.
2899 + * @param HalFunc Pointer to pointer to structure containing function pointers for all CPHAL
2900 + * interfaces. Allocated during the call.
2901 + * @param OsFunc Pointer to structure containing function pointers for all OS
2902 + * provided interfaces. Must be allocated by OS prior to call.
2903 + * @param OsFuncSize Size of OS_FUNCTIONS structure.
2904 + * @param HalFuncSize Pointer to the size of the HAL_FUNCTIONS structure.
2905 + * @param Inst The instance number of the module to initialize. (start at
2906 + * 0).
2907 + *
2908 + * @return EC_NO_ERRORS (ok). <BR>
2909 + * Possible Error Codes:<BR>
2910 + * @ref EC_VAL_OS_VERSION_NOT_SUPPORTED "EC_VAL_OS_VERSION_NOT_SUPPORTED"<BR>
2911 + * @ref EC_VAL_MALLOC_DEV_FAILED "EC_VAL_MALLOC_DEV_FAILED"<BR>
2912 + * @ref EC_VAL_MALLOC_FAILED "EC_VAL_MALLOC_FAILED"<BR>
2913 + */
2914 +int xxxInitModule(HAL_DEVICE **HalDev,
2915 + OS_DEVICE *OsDev,
2916 + HAL_FUNCTIONS **HalFunc,
2917 + OS_FUNCTIONS *OsFunc,
2918 + int OsFuncSize,
2919 + int *HalFuncSize,
2920 + int Inst);
2921 +
2922 +int cpaal5InitModule(HAL_DEVICE **HalDev,
2923 + OS_DEVICE *OsDev,
2924 + HAL_FUNCTIONS **HalFunc,
2925 + OS_FUNCTIONS *OsFunc,
2926 + int OsFuncSize,
2927 + int *HalFuncSize,
2928 + int Inst)
2929 + {
2930 + int rc, SarFuncSize;
2931 + HAL_DEVICE *HalPtr;
2932 + HAL_FUNCTIONS *HalFuncPtr;
2933 +
2934 + /* NEW CODE */
2935 + if (OsFuncSize < sizeof(OS_FUNCTIONS))
2936 + return (EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_OS_VERSION_NOT_SUPPORTED);
2937 +
2938 + HalPtr = (HAL_DEVICE *) OsFunc->MallocDev(sizeof(HAL_DEVICE));
2939 + if (!HalPtr)
2940 + return (EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_DEV_FAILED);
2941 +
2942 + HalFuncPtr = (HAL_FUNCTIONS *) OsFunc->Malloc(sizeof(HAL_FUNCTIONS));
2943 + if (!HalFuncPtr)
2944 + return (EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_MALLOC_FAILED);
2945 +
2946 + /* Initialize the size of hal functions */
2947 + *HalFuncSize = sizeof (HAL_FUNCTIONS);
2948 +
2949 + /* clear the device structure */
2950 + OsFunc->Memset(HalPtr, 0, sizeof(HAL_DEVICE));
2951 +
2952 + /* clear the function pointers */
2953 + OsFunc->Memset(HalFuncPtr, 0, sizeof(HAL_FUNCTIONS));
2954 +
2955 + /* initialize the HAL_DEVICE structure */
2956 + HalPtr->OsDev = OsDev;
2957 + /*HalPtr->OsOpen = OsDev;*/
2958 + HalPtr->Inst = Inst;
2959 + HalPtr->OsFunc = OsFunc;
2960 +
2961 + /* Supply pointers for the CPHAL API functions */
2962 + HalFuncPtr->RxReturn = halRxReturn;
2963 + HalFuncPtr->Init = halInit;
2964 + HalFuncPtr->Close = halClose;
2965 + HalFuncPtr->Send = halSend;
2966 + HalFuncPtr->ChannelSetup = halChannelSetup;
2967 + HalFuncPtr->ChannelTeardown = halChannelTeardown;
2968 + HalFuncPtr->Open = halOpen;
2969 + HalFuncPtr->Kick = halKick;
2970 + HalFuncPtr->RegAccess = halRegAccess;
2971 + HalFuncPtr->Probe = halProbe;
2972 + HalFuncPtr->Control = halControl;
2973 + HalFuncPtr->Tick = halTick;
2974 + HalFuncPtr->Shutdown = halShutdown;
2975 + HalFuncPtr->OamFuncConfig = halOamFuncConfig; /* +GSG 030306 */
2976 + HalFuncPtr->OamLoopbackConfig = halOamLoopbackConfig; /* ~GSG 030416 */
2977 +
2978 + /* Temporary */
2979 + /*HalFuncPtr->StatsGetOld = StatsGet;*/
2980 + HalFuncPtr->PacketProcessEnd = halPacketProcessEnd;
2981 +
2982 + /* Now, AAL5 must connect to the CPSAR layer */
2983 +
2984 + /* Attach to SAR HAL Functions */
2985 + /*
2986 + cpsarInitModule(NULL, NULL, 0, NULL, &SarFuncSize, Inst);
2987 +
2988 + if (SarFuncSize!=sizeof(CPSAR_FUNCTIONS))
2989 + return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_CPSAR_VERSION_NOT_SUPPORTED);
2990 +
2991 + HalPtr->SarFunc = (CPSAR_FUNCTIONS *) OsFunc->Malloc(SarFuncSize);
2992 + */
2993 +
2994 + rc = cpsarInitModule(&HalPtr->SarDev, OsDev, &HalPtr->SarFunc, OsFunc, sizeof(OS_FUNCTIONS), &SarFuncSize, Inst);
2995 +
2996 + /* pass back the error value from the CPSAR layer if necessary */
2997 + if (rc)
2998 + return(rc);
2999 +
3000 + /*
3001 + if (!HalPtr->SarDev)
3002 + return(EC_AAL5|EC_FUNC_HAL_INIT|EC_VAL_NULL_CPSAR_DEV);
3003 + */
3004 +
3005 + /* Initialize the hardware state */
3006 + HalPtr->State = enConnected;
3007 +
3008 + /* keep a reference to HalFuncPtr so I can free it later */
3009 + HalPtr->HalFuncPtr = HalFuncPtr;
3010 +
3011 + /* pass the HalPtr back to the caller */
3012 + *HalDev = HalPtr;
3013 + *HalFunc = HalFuncPtr;
3014 +
3015 + return(EC_NO_ERRORS);
3016 + }
3017 diff -urN linux.old/drivers/atm/sangam_atm/aal5sar.h linux.dev/drivers/atm/sangam_atm/aal5sar.h
3018 --- linux.old/drivers/atm/sangam_atm/aal5sar.h 1970-01-01 01:00:00.000000000 +0100
3019 +++ linux.dev/drivers/atm/sangam_atm/aal5sar.h 2005-08-23 04:46:50.080846280 +0200
3020 @@ -0,0 +1,198 @@
3021 +/**@file************************************************************************
3022 + * TNETDxxxx Software Support
3023 + * Copyright (c) 2002 Texas Instruments Incorporated. All Rights Reserved.
3024 + *
3025 + * FILE: aal5sar.h
3026 + *
3027 + * DESCRIPTION:
3028 + * This file contains data structure definitions for the AAL5 HAL SAR.
3029 + *
3030 + * HISTORY:
3031 + * 28Feb02 Greg 1.00 Original Version created.
3032 + * 06Mar02 Greg 1.01 Documented structures.
3033 + * 18Jul02 Greg 1.02 Major reorganization
3034 + *
3035 + *****************************************************************************/
3036 +#ifndef _INC_AAL5SAR
3037 +#define _INC_AAL5SAR
3038 +
3039 +/** \namespace AAL5_Version
3040 +This documents version 01.06.06 of the AAL5 CPHAL.
3041 +*/
3042 +const char *pszVersion_CPAAL5="CPAAL5 01.06.06 "__DATE__" "__TIME__;
3043 +
3044 +#include "cpsar_cpaal5.h"
3045 +
3046 +#define NUM_AAL5_CHAN 16
3047 +#define MAX_AAL5_CHAN 15
3048 +#define MAX_QUEUE 2
3049 +#define MAX_DIRECTION 2
3050 +
3051 +#define PKT_TYPE_AAL5 0 /* +GSG 030508 */
3052 +#define PKT_TYPE_NULL 1 /* +GSG 030508 */
3053 +#define PKT_TYPE_OAM 2 /* +GSG 030508 */
3054 +#define PKT_TYPE_TRANS 3 /* +GSG 030508 */
3055 +#define ATM_HEADER_SIZE 4 /* +GSG 030508 */
3056 +
3057 +/*
3058 + * HAL Default Parameter Values
3059 + */
3060 +#define CFG_TX_NUM_BUFS {256,256,256,256,256,256,256,256, 256,256,256,256,256,256,256,256}
3061 +#define CFG_RX_NUM_BUFS {256,256,256,256,256,256,256,256, 256,256,256,256,256,256,256,256}
3062 +#define CFG_RX_BUF_SIZE {1518,1518,1518,1518,1518,1518,1518,1518, 1518,1518,1518,1518,1518,1518,1518,1518}
3063 +#define CFG_RX_BUF_OFFSET {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3064 +#define CFG_TX_NUM_QUEUES {1,1,1,1,1,1,1,1, 1,1,1,1,1,1,1,1}
3065 +#define CFG_CPCS_UU {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3066 +#define CFG_DA_MASK {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3067 +#define CFG_PRIORITY {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3068 +#define CFG_PKT_TYPE {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3069 +#define CFG_VCI {100,101,102,103,104,105,106,107, 108,109,110,111,112,113,114,115}
3070 +#define CFG_VPI {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3071 +#define CFG_CELL_RATE {0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4, 0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4,0x30d4}
3072 +#define CFG_QOS_TYPE {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3073 +#define CFG_MBS {8,8,8,8,8,8,8,8, 8,8,8,8,8,8,8,8}
3074 +#define CFG_PCR {1,1,1,1,1,1,1,1, 1,1,1,1,1,1,1,1}
3075 +#define CFG_GFC {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3076 +#define CFG_CLP {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3077 +#define CFG_PTI {0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0}
3078 +#define CFG_RX_MAX_SERVICE {170,170,170,170,170,170,170,170, 170,170,170,170,170,170,170,170}
3079 +#define CFG_TX_MAX_SERVICE {170,170,170,170,170,170,170,170, 170,170,170,170,170,170,170,170}
3080 +
3081 +static int cfg_tx_num_bufs[NUM_AAL5_CHAN] = CFG_TX_NUM_BUFS;
3082 +static int cfg_rx_num_bufs[NUM_AAL5_CHAN] = CFG_RX_NUM_BUFS;
3083 +static int cfg_rx_buf_size[NUM_AAL5_CHAN] = CFG_RX_BUF_SIZE;
3084 +static int cfg_rx_buf_offset[NUM_AAL5_CHAN] = CFG_RX_BUF_OFFSET;
3085 +static int cfg_tx_num_queues[NUM_AAL5_CHAN] = CFG_TX_NUM_QUEUES;
3086 +static bit32u cfg_cpcs_uu[NUM_AAL5_CHAN] = CFG_CPCS_UU;
3087 +static int cfg_da_mask[NUM_AAL5_CHAN] = CFG_DA_MASK;
3088 +static int cfg_priority[NUM_AAL5_CHAN] = CFG_PRIORITY;
3089 +static int cfg_pkt_type[NUM_AAL5_CHAN] = CFG_PKT_TYPE;
3090 +static int cfg_vci[NUM_AAL5_CHAN] = CFG_VCI;
3091 +static int cfg_vpi[NUM_AAL5_CHAN] = CFG_VPI;
3092 +static bit32u cfg_cell_rate[NUM_AAL5_CHAN] = CFG_CELL_RATE;
3093 +static int cfg_qos_type[NUM_AAL5_CHAN] = CFG_QOS_TYPE;
3094 +static int cfg_mbs[NUM_AAL5_CHAN] = CFG_MBS;
3095 +static int cfg_pcr[NUM_AAL5_CHAN] = CFG_PCR;
3096 +static int cfg_gfc[NUM_AAL5_CHAN] = CFG_GFC;
3097 +static int cfg_clp[NUM_AAL5_CHAN] = CFG_CLP;
3098 +static int cfg_pti[NUM_AAL5_CHAN] = CFG_PTI;
3099 +static int cfg_rx_max_service[NUM_AAL5_CHAN]= CFG_RX_MAX_SERVICE;
3100 +static int cfg_tx_max_service[NUM_AAL5_CHAN]= CFG_TX_MAX_SERVICE;
3101 +static char *channel_names[] = CHANNEL_NAMES;
3102 +
3103 +/*
3104 + * The HAL_FUNCTIONS struct defines the function pointers for all HAL functions
3105 + * accessible to upper layer software. It is populated by calling
3106 + * halInitModules().
3107 + *
3108 + * Note that this list is still under definition.
3109 + */
3110 +
3111 +/*
3112 + * This is the data structure for a transmit buffer descriptor. The first
3113 + * four 32-bit words of the BD represent the CPPI 3.0 defined buffer descriptor
3114 + * words. The other words are SAR/HAL implementation specific.
3115 + */
3116 +typedef struct
3117 + {
3118 + bit32 HNext; /**< Hardware's pointer to next buffer descriptor */
3119 + bit32 BufPtr; /**< Pointer to the data buffer */
3120 + bit32 Off_BLen; /**< Contains buffer offset and buffer length */
3121 + bit32 mode; /**< SOP, EOP, Ownership, EOQ, Teardown Complete bits */
3122 + bit32 AtmHeader; /**< Atm Header to be used for each fragment */
3123 + bit32 Word5; /**< General control information for the packet */
3124 + bit32 Res6;
3125 + bit32 Res7;
3126 + void *Next;
3127 + void *OsInfo;
3128 +#ifdef __CPHAL_DEBUG
3129 + bit32 DbgSop;
3130 + bit32 DbgData;
3131 + bit32 DbgFraglist;
3132 +#endif
3133 + void *Eop;
3134 + }HAL_TCB;
3135 +
3136 +/*
3137 + * This is the data structure for a receive buffer descriptor. The first
3138 + * six 32-bit words of the BD represent the CPPI 3.0 defined buffer descriptor
3139 + * words. The other words are HAL implementation specific.
3140 + */
3141 +typedef volatile struct hal_private
3142 + {
3143 + bit32 HNext; /**< Hardware's pointer to next buffer descriptor */
3144 + bit32 BufPtr; /**< Pointer to the data buffer */
3145 + bit32 Off_BLen; /**< Contains buffer offset and buffer length */
3146 + bit32 mode; /**< SOP, EOP, Ownership, EOQ, Teardown, Q Starv, Length */
3147 + bit32 AtmHeader;
3148 + bit32 UuCpi;
3149 + bit32 Res6;
3150 + bit32 Res7;
3151 + void *DatPtr;
3152 + void *Next;
3153 + void *OsInfo;
3154 + void *Eop;
3155 + bit32 FragCount;
3156 + bit32 Ch;
3157 + HAL_DEVICE *HalDev;
3158 + }HAL_RCB;
3159 +
3160 +
3161 +#define MAX_NEEDS 512 /*MJH+030409*/
3162 +/*
3163 + * This is the data structure for a generic HAL device. It contains all device
3164 + * specific data for a single instance of that device. This includes Rx/Tx
3165 + * buffer queues, device base address, reset bit, and other information.
3166 + */
3167 +typedef struct hal_device
3168 + {
3169 + HAL_RCB *RcbPool[NUM_AAL5_CHAN];
3170 + bit32u rxbufseq;
3171 + bit32 RxActQueueCount[NUM_AAL5_CHAN];
3172 + HAL_RCB *RxActQueueHead[NUM_AAL5_CHAN];
3173 + HAL_RCB *RxActQueueTail[NUM_AAL5_CHAN];
3174 + bit32 RxActive[NUM_AAL5_CHAN];
3175 + bit32 dev_base;
3176 + HAL_TCB *TcbPool[NUM_AAL5_CHAN][MAX_QUEUE];
3177 + bit32 offset;
3178 + bit32 TxActQueueCount[NUM_AAL5_CHAN][MAX_QUEUE];
3179 + HAL_TCB *TxActQueueHead[NUM_AAL5_CHAN][MAX_QUEUE];
3180 + HAL_TCB *TxActQueueTail[NUM_AAL5_CHAN][MAX_QUEUE];
3181 + bit32 TxActive[NUM_AAL5_CHAN][MAX_QUEUE];
3182 + bit32 TxTeardownPending[NUM_AAL5_CHAN];
3183 + bit32 RxTeardownPending[NUM_AAL5_CHAN];
3184 + bit32 ChIsOpen[NUM_AAL5_CHAN][MAX_DIRECTION];
3185 + bit32 ChIsSetup[NUM_AAL5_CHAN][MAX_DIRECTION];
3186 + bit32 interrupt;
3187 + bit32 debug;
3188 + OS_DEVICE *OsDev;
3189 + OS_FUNCTIONS *OsFunc;
3190 + CPSAR_FUNCTIONS *SarFunc;
3191 + CPSAR_DEVICE *SarDev;
3192 + /*void *OsOpen;*/
3193 + /*FRAGLIST fraglist[MAX_FRAG];*/
3194 + FRAGLIST *fraglist;
3195 + char *TcbStart[NUM_AAL5_CHAN][MAX_QUEUE];
3196 + char *RcbStart[NUM_AAL5_CHAN];
3197 + /*bit32 RcbSize[NUM_AAL5_CHAN];*/
3198 + bit32 InRxInt[NUM_AAL5_CHAN];
3199 + STAT_INFO Stats;
3200 + bit32 Inst;
3201 + bit32u DeviceCPID[4];
3202 + bit32u LBSourceLLID[4];
3203 + CHANNEL_INFO ChData[NUM_AAL5_CHAN];
3204 + DEVICE_STATE State;
3205 + char *DeviceInfo;
3206 + HAL_FUNCTIONS *HalFuncPtr;
3207 + int NextRxCh;
3208 + int NextTxCh[2];
3209 + int StrictPriority; /* +GSG 030304 */
3210 + bit32u NeedsCount; /*MJH+030409*/
3211 + HAL_RECEIVEINFO *Needs[MAX_NEEDS]; /*MJH+030409*/
3212 + bit32u SarFrequency; /* +GSG 030416 */
3213 + int MaxFrags;
3214 + bit32u TurboDslErrors;
3215 + bit32u OamLbTimeout;
3216 + }HALDEVICE;
3217 +
3218 +#endif
3219 diff -urN linux.old/drivers/atm/sangam_atm/cpcommon_cpaal5.c linux.dev/drivers/atm/sangam_atm/cpcommon_cpaal5.c
3220 --- linux.old/drivers/atm/sangam_atm/cpcommon_cpaal5.c 1970-01-01 01:00:00.000000000 +0100
3221 +++ linux.dev/drivers/atm/sangam_atm/cpcommon_cpaal5.c 2005-08-23 04:46:50.081846128 +0200
3222 @@ -0,0 +1,728 @@
3223 +#ifndef _INC_CPCOMMON_C
3224 +#define _INC_CPCOMMON_C
3225 +
3226 +#ifdef _CPHAL_CPMAC
3227 +#include "cpremap_cpmac.c"
3228 +#endif
3229 +
3230 +#ifdef _CPHAL_AAL5
3231 +#include "cpremap_cpaal5.c"
3232 +#endif
3233 +
3234 +#ifdef _CPHAL_CPSAR
3235 +#include "cpremap_cpsar.c"
3236 +#endif
3237 +
3238 +#ifdef _CPHAL_AAL2
3239 +#include "cpremap_cpaal2.c"
3240 +#endif
3241 +
3242 +/**
3243 +@defgroup Common_Config_Params Common Configuration Parameters
3244 +
3245 +This section documents the configuration parameters that are valid across
3246 +all CPHAL devices.
3247 +@{
3248 +*/
3249 +/** This is the debug level. The field is bit defined, such that the user
3250 +should set to 1 all the bits corresponding to desired debug outputs. The following
3251 +are the meanings for each debug bit:
3252 +- bit0 (LSB): CPHAL Function Trace
3253 +- b1 : OS Function call trace
3254 +- b2 : Critical section entry/exit
3255 +- b3 : Memory allocation/destruction
3256 +- b4 : Detailed information in Rx path
3257 +- b5 : Detailed information in Tx path
3258 +- b6 : Extended error information
3259 +- b7 : General info
3260 +*/
3261 +static const char pszDebug[] = "debug";
3262 +/** CPU Frequency. */
3263 +/*static const char pszCpuFreq[] = "CpuFreq";*/ /*MJH-030403*/
3264 +/** Base address for the module. */
3265 +static const char pszBase[] = "base";
3266 +/** Reset bit for the module. */
3267 +static const char pszResetBit[] = "reset_bit";
3268 +/** Reset base address for the module. */
3269 +static const char pszResetBase[] = "ResetBase";
3270 +/** Interrupt line for the module. */
3271 +static const char pszIntLine[] = "int_line";
3272 +/** VLYNQ offset for the module. Disregard if not using VLYNQ. */
3273 +static const char pszOffset[] = "offset";
3274 +/** The OS may "Get" this parameter, which is a pointer
3275 + to a character string that indicates the version of CPHAL. */
3276 +static const char pszVer[] = "Version";
3277 +/*@}*/
3278 +
3279 +/**
3280 +@defgroup Common_Control_Params Common Keys for [os]Control()
3281 +
3282 +This section documents the keys used with the OS @c Control() interface that
3283 +are required by CPHAL devices.
3284 +
3285 +@{
3286 +*/
3287 +/** Used to wait for an integer number of clock ticks, given as an integer
3288 + pointer in the @p Value parameter. No actions are defined. */
3289 +static const char pszSleep[] = "Sleep";
3290 +/** Requests the OS to flush it's IO buffers. No actions are defined. */
3291 +static const char pszSioFlush[] = "SioFlush";
3292 +/*@}*/
3293 +
3294 +static const char pszStateChange[] = "StateChange";
3295 +static const char pszStatus[] = "Status";
3296 +
3297 +static const char pszGET[] = "Get";
3298 +static const char pszSET[] = "Set";
3299 +static const char pszCLEAR[] = "Clear";
3300 +static const char pszNULL[] = "";
3301 +static const char pszLocator[] = "Locator";
3302 +static const char pszOff[] = "Off";
3303 +static const char pszOn[] = "On";
3304 +static const char hcMaxFrags[] = "MaxFrags";
3305 +
3306 +#ifdef _CPHAL_CPMAC
3307 +
3308 +/* New method for string constants */
3309 +const char hcClear[] = "Clear";
3310 +const char hcGet[] = "Get";
3311 +const char hcSet[] = "Set";
3312 +
3313 +const char hcTick[] = "Tick";
3314 +
3315 +static const CONTROL_KEY KeyCommon[] =
3316 + {
3317 + {"" , enCommonStart},
3318 + {pszStatus , enStatus},
3319 + {pszOff , enOff},
3320 + {pszOn , enOn},
3321 + {pszDebug , enDebug},
3322 + {hcCpuFrequency , enCpuFreq}, /*MJH~030403*/
3323 + {"" , enCommonEnd}
3324 + };
3325 +#endif
3326 +
3327 +/**
3328 +@defgroup Common_Statistics Statistics
3329 +
3330 +A broad array of module statistics is available. Statistics values are accessed
3331 +through the @c Control() interface of the CPHAL. There are 5 different levels
3332 +of statistics, each of which correspond to a unique set of data. Furthermore,
3333 +certain statistics data is indexed by using a channel number and Tx queue number.
3334 +The following is a brief description of each statistics level, along with the
3335 +indexes used for the level:
3336 +
3337 +- Level 0: Hardware Statistics (index with channel)
3338 +- Level 1: CPHAL Software Statistics (channel, queue)
3339 +- Level 2: CPHAL Flags (channel, queue)
3340 +- Level 3: CPHAL Channel Configuration (channel)
3341 +- Level 4: CPHAL General Configuration (no index)
3342 +
3343 +The caller requests statistics information by providing a Key string to the
3344 +@c Control() API in the following format: "Stats;[Level #];[Ch #];[Queue #]".
3345 +The only valid Action parameter for statistics usage is "Get".
3346 +
3347 +Code Examples:
3348 +@code
3349 +unsigned int *StatsData;
3350 +
3351 +# Get Level 0 stats for Channel 1
3352 +HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
3353 +
3354 +# Get Level 2 stats for Channel 0, Queue 0
3355 +HalFunc->Control(OsDev->HalDev, "Stats;2;0;0", "Get", &StatsData);
3356 +
3357 +# Get Level 4 stats
3358 +HalFunc->Control(OsDev->HalDev, "Stats;4", "Get", &StatsData);
3359 +@endcode
3360 +
3361 +The information returned in the Value parameter of @c Control() is an
3362 +array of pointers to strings. The pointers are arranged in pairs.
3363 +The first pointer is a pointer to a name string for a particular statistic.
3364 +The next pointer is a pointer to a string containing the representation of
3365 +the integer statistic value corresponding to the first pointer. This is followed
3366 +by another pair of pointers, and so on, until a NULL pointer is encountered. The
3367 +following is example code for processing the statistics data. Note that the OS
3368 +is responsible for freeing the memory passed back through the Value parameter of
3369 +@c Control().
3370 +
3371 +@code
3372 +unsigned int *StatsData;
3373 +
3374 +# Get Level 0 stats for Channel 1
3375 +HalFunc->Control(OsDev->HalDev, "Stats;0;1", "Get", &StatsData);
3376 +
3377 +# output Statistics data
3378 +PrintStats(StatsData);
3379 +
3380 +# the upper layer is responsible for freeing stats info
3381 +free(&StatsPtr);
3382 +
3383 +...
3384 +
3385 +void PrintStats(unsigned int *StatsPtr)
3386 + {
3387 + while(*StatsPtr)
3388 + {
3389 + printf("%20s:", (char *)*StatsPtr);
3390 + StatsPtr++;
3391 + printf("%11s\n", (char *)*StatsPtr);
3392 + StatsPtr++;
3393 + }
3394 + MySioFlush();
3395 + }
3396 +@endcode
3397 +
3398 +Within each statistics level, there are several statistics defined. The statistics that
3399 +are common to every CPPI module are listed below. In addition, each module may define
3400 +extra statistics in each level, which will be documented within the module-specific
3401 +documentation appendices.
3402 +
3403 +- Level 0 Statistics
3404 + - All level 0 statistics are module-specific.
3405 +- Level 1 Statistics (CPHAL Software Statistics)
3406 + - DmaLenErrors: Incremented when the port DMA's more data than expected (per channel). (AAL5 Only)
3407 + - TxMisQCnt: Incremented when host queues a packet for transmission as the port finishes
3408 +transmitting the previous last packet in the queue (per channel and queue).
3409 + - RxMisQCnt: Incremented when host queues adds buffers to a queue as the port finished the
3410 +reception of the previous last packet in the queue (per channel).
3411 + - TxEOQCnt: Number of times the port has reached the end of the transmit queue (per channel and queue).
3412 + - RxEOQCnt: Number of times the port has reached the end of the receive queue (per channel).
3413 + - RxPacketsServiced: Number of received packets (per channel).
3414 + - TxPacketsServiced: Number of transmitted packets (per channel and queue).
3415 + - RxMaxServiced: Maximum number of packets that the CPHAL receive interrupt has serviced at a time (per channel).
3416 + - TxMaxServiced: Maximum number of packets that the CPHAL transmit interrupt has serviced at a time (per channel and queue).
3417 + - RxTotal: Total number of received packets, all channels.
3418 + - TxTotal: Total number of transmitted packets, all channels and queues.
3419 +- Level 2 Statistics (CPHAL Flags)
3420 + - RcbPool: Pointer to receive descriptor pool (per channel).
3421 + - RxActQueueCount: Number of buffers currently available for receive (per channel).
3422 + - RxActQueueHead: Pointer to first buffer in receive queue (per channel).
3423 + - RxActQueueTail: Pointer to last buffer in receive queue (per channel).
3424 + - RxActive: 0 if inactive (no buffers available), or 1 if active (buffers available).
3425 + - RcbStart: Pointer to block of receive descriptors.
3426 + - RxTeardownPending: 1 if Rx teardown is pending but incomplete, 0 otherwise.
3427 + - TcbPool: Pointer to transmit descriptor pool (per channel and queue).
3428 + - TxActQueueCount: Number of buffers currently queued to be transmitted (per channel and queue).
3429 + - TxActQueueHead: Pointer to first buffer in transmit queue (per channel and queue).
3430 + - TxActQueueTail: Pointer to last buffer in transmit queue (per channel and queue).
3431 + - TxActive: 0 if inactive (no buffers to send), or 1 if active (buffers queued to send).
3432 + - TcbStart: Pointer to block of transmit descriptors.
3433 + - TxTeardownPending: 1 if Tx teardown is pending but incomplete, 0 otherwise.
3434 +- Level 3 Statistics (CPHAL Channel Configuration)
3435 + - RxBufSize: Rx buffer size.
3436 + - RxBufferOffset: Rx buffer offset.
3437 + - RxNumBuffers: Number of Rx buffers.
3438 + - RxServiceMax: Maximum number of receive packets to service at a time.
3439 + - TxNumBuffers: Number of Tx buffer descriptors.
3440 + - TxNumQueues: Number of Tx queues to use.
3441 + - TxServiceMax: Maximum number of transmit packets to service at a time.
3442 +- Level 4 Statistics (CPHAL General Configuration)
3443 + - Base Address: Base address of the module.
3444 + - Offset (VLYNQ): VLYNQ relative module offset.
3445 + - Interrupt Line: Interrupt number.
3446 + - Debug: Debug flag, 1 to enable debug.
3447 + - Inst: Instance number.
3448 +*/
3449 +
3450 +/*
3451 + Data Type 0 = int display
3452 + Data Type 1 = hex display
3453 + Data Type 2 = channel structure, int display
3454 + Data Type 3 = queue index and int display
3455 + Data Type 4 = queue index and hex display
3456 +*/
3457 +#if (defined(_CPHAL_AAL5) || defined(_CPHAL_CPMAC)) /* +GSG 030307 */
3458 +static STATS_TABLE StatsTable0[] =
3459 + {
3460 +#ifdef _CPHAL_AAL5
3461 + /* Name , Data Ptr, Data Type */
3462 + {"Crc Errors", 0, 0},
3463 + {"Len Errors", 0, 0},
3464 + {"Abort Errors", 0, 0},
3465 + {"Starv Errors", 0, 0}
3466 +#endif
3467 +#ifdef _CPHAL_CPMAC
3468 + {"Rx Good Frames", 0, 0}
3469 +#endif
3470 + };
3471 +
3472 +static STATS_TABLE StatsTable1[] =
3473 + {
3474 + /* Name , Data Ptr, Data Type */
3475 + {"DmaLenErrors", 0, 0},
3476 + {"TxMisQCnt", 0, 3},
3477 + {"RxMisQCnt", 0, 0},
3478 + {"TxEOQCnt", 0, 3},
3479 + {"RxEOQCnt", 0, 0},
3480 + {"RxPacketsServiced", 0, 0},
3481 + {"TxPacketsServiced", 0, 3},
3482 + {"RxMaxServiced", 0, 0},
3483 + {"TxMaxServiced", 0, 3},
3484 + {"RxTotal", 0, 0},
3485 + {"TxTotal", 0, 0},
3486 + };
3487 +
3488 +static STATS_TABLE StatsTable2[] =
3489 + {
3490 + /* Name , Data Ptr, Data Type */
3491 + {"RcbPool", 0, 1},
3492 + {"RxActQueueCount", 0, 0},
3493 + {"RxActQueueHead", 0, 1},
3494 + {"RxActQueueTail", 0, 1},
3495 + {"RxActive", 0, 0},
3496 + {"RcbStart", 0, 1},
3497 + {"RxTeardownPending", 0, 0},
3498 + {"TcbPool", 0, 4},
3499 + {"TxActQueueCount", 0, 3},
3500 + {"TxActQueueHead", 0, 4},
3501 + {"TxActQueueTail", 0, 4},
3502 + {"TxActive", 0, 3},
3503 + {"TcbStart", 0, 4},
3504 + {"TxTeardownPending", 0, 0}
3505 + };
3506 +
3507 +static STATS_TABLE StatsTable3[] =
3508 + {
3509 + /* Name , Data Ptr, Data Type */
3510 + {"RxBufSize", 0, 2},
3511 + {"RxBufferOffset", 0, 2},
3512 + {"RxNumBuffers", 0, 2},
3513 + {"RxServiceMax", 0, 2},
3514 + {"TxNumBuffers", 0, 2},
3515 + {"TxNumQueues", 0, 2},
3516 + {"TxServiceMax", 0, 2},
3517 +#ifdef _CPHAL_AAL5
3518 + {"CpcsUU", 0, 2},
3519 + {"Gfc", 0, 2},
3520 + {"Clp", 0, 2},
3521 + {"Pti", 0, 2},
3522 + {"DaMask", 0, 2},
3523 + {"Priority", 0, 2},
3524 + {"PktType", 0, 2},
3525 + {"Vci", 0, 2},
3526 + {"Vpi", 0, 2},
3527 + {"CellRate", 0, 2},
3528 + {"QosType", 0, 2},
3529 + {"Mbs", 0, 2},
3530 + {"Pcr", 0, 2}
3531 +#endif
3532 + };
3533 +
3534 +static STATS_TABLE StatsTable4[] =
3535 + {
3536 + {"Base Address", 0, 1},
3537 + {"Offset (VLYNQ)", 0, 0},
3538 + {"Interrupt Line", 0, 0},
3539 + {"Debug", 0, 0},
3540 + {"Instance", 0, 0},
3541 +#ifdef _CPHAL_AAL5
3542 + {"UniNni", 0, 0}
3543 +#endif
3544 + };
3545 +
3546 +static STATS_DB StatsDb[] =
3547 + {
3548 + {(sizeof(StatsTable0)/sizeof(STATS_TABLE)), StatsTable0},
3549 + {(sizeof(StatsTable1)/sizeof(STATS_TABLE)), StatsTable1},
3550 + {(sizeof(StatsTable2)/sizeof(STATS_TABLE)), StatsTable2},
3551 + {(sizeof(StatsTable3)/sizeof(STATS_TABLE)), StatsTable3},
3552 + {(sizeof(StatsTable4)/sizeof(STATS_TABLE)), StatsTable4}
3553 + };
3554 +#endif /* +GSG 030307 */
3555 +
3556 +#ifdef _CPHAL_CPMAC /* +RC 3.02 */
3557 +static void resetWait(HAL_DEVICE *HalDev)
3558 + { /*+RC3.02*/
3559 + const int TickReset=64;
3560 + osfuncSleep((int*)&TickReset);
3561 + } /*+RC3.02*/
3562 +#endif /* +RC 3.02 */
3563 +
3564 +/* I only define the reset base function for the modules
3565 + that can perform a reset. The AAL5 and AAL2 modules
3566 + do not perform a reset, that is done by the shared module
3567 + CPSAR */
3568 +#if defined(_CPHAL_CPSAR) || defined(_CPHAL_CPMAC) || defined(_CPHAL_VDMAVT)
3569 +/*
3570 + * Determines the reset register address to be used for a particular device.
3571 + * It will search the current device entry for Locator information. If the
3572 + * device is a root device, there will be no Locator information, and the
3573 + * function will find and return the root reset register. If a Locator value
3574 + * is found, the function will search each VLYNQ device entry in the system
3575 + * looking for a matching Locator. Once it finds a VLYNQ device entry with
3576 + * a matching Locator, it will extract the "ResetBase" parameter from that
3577 + * VLYNQ device entry (thus every VLYNQ entry must have the ResetBase parameter).
3578 + *
3579 + * @param HalDev CPHAL module instance. (set by xxxInitModule())
3580 + * @param ResetBase Pointer to integer address of reset register.
3581 + *