target/linux/ar71xx/files/arch/mips/ath79/mach-dr344.c

   1 /*
   2  * Wallys DR344 board support
   3  *
   4  * Copyright (c) 2011 Qualcomm Atheros
   5  * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  * Copyright (c) 2015 Philippe Duchein <wireless-dev@duchein.net>
   7  *
   8  * Permission to use, copy, modify, and/or distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  */
  21
  22 #include <linux/phy.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ath9k_platform.h>
  25 #include <linux/ar8216_platform.h>
  26
  27 #include <asm/mach-ath79/ar71xx_regs.h>
  28
  29 #include "common.h"
  30 #include "pci.h"
  31 #include "dev-ap9x-pci.h"
  32 #include "dev-gpio-buttons.h"
  33 #include "dev-eth.h"
  34 #include "dev-usb.h"
  35 #include "dev-leds-gpio.h"
  36 #include "dev-m25p80.h"
  37 #include "dev-spi.h"
  38 #include "dev-wmac.h"
  39 #include "machtypes.h"
  40
  41 #define DR344_GPIO_LED_SIG1     15
  42 #define DR344_GPIO_LED_SIG2     11
  43 #define DR344_GPIO_LED_SIG3     12
  44 #define DR344_GPIO_LED_SIG4     13
  45 #define DR344_GPIO_EXTERNAL_LNA0       18
  46 #define DR344_GPIO_EXTERNAL_LNA1       19
  47 #define DR344_GPIO_LED_STATUS   14
  48
  49 #define DR344_GPIO_BTN_RESET    12
  50
  51 #define DR344_KEYS_POLL_INTERVAL        20      /* msecs */
  52 #define DR344_KEYS_DEBOUNCE_INTERVAL    (3 * DR344_KEYS_POLL_INTERVAL)
  53
  54 #define DR344_MAC0_OFFSET               0
  55 #define DR344_MAC1_OFFSET               8
  56 #define DR344_WMAC_CALDATA_OFFSET       0x1000
  57 #define DR344_PCIE_CALDATA_OFFSET       0x5000
  58
  59 static struct gpio_led dr344_leds_gpio[] __initdata = {
  60         {
  61                 .name           = "dr344:green:status",
  62                 .gpio           = DR344_GPIO_LED_STATUS,
  63                 .active_low     = 1,
  64         },
  65         {
  66                 .name           = "dr344:red:sig1",
  67                 .gpio           = DR344_GPIO_LED_SIG1,
  68                 .active_low     = 1,
  69         },
  70         {
  71                 .name           = "dr344:yellow:sig2",
  72                 .gpio           = DR344_GPIO_LED_SIG2,
  73                 .active_low     = 1,
  74         },
  75         {
  76                 .name           = "dr344:green:sig3",
  77                 .gpio           = DR344_GPIO_LED_SIG3,
  78                 .active_low     = 1,
  79         },
  80         {
  81                 .name           = "dr344:green:sig4",
  82                 .gpio           = DR344_GPIO_LED_SIG4,
  83                 .active_low     = 1,
  84         }
  85 };
  86
  87 static struct gpio_keys_button dr344_gpio_keys[] __initdata = {
  88         {
  89                 .desc           = "reset",
  90                 .type           = EV_KEY,
  91                 .code           = KEY_RESTART,
  92                 .debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL,
  93                 .gpio           = DR344_GPIO_BTN_RESET,
  94                 .active_low     = 1,
  95         },
  96 };
  97
  98 static struct ar8327_pad_cfg dr344_ar8327_pad0_cfg = {
  99         .mode = AR8327_PAD_MAC_RGMII,
 100         .txclk_delay_en = true,
 101         .rxclk_delay_en = true,
 102         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 103         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 104 };
 105
 106 static struct ar8327_led_cfg dr344_ar8327_led_cfg = {
 107         .led_ctrl0 = 0x00000000,
 108         .led_ctrl1 = 0xc737c737,
 109         .led_ctrl2 = 0x00000000,
 110         .led_ctrl3 = 0x00c30c00,
 111         .open_drain = true,
 112 };
 113
 114 static struct ar8327_platform_data dr344_ar8327_data = {
 115         .pad0_cfg = &dr344_ar8327_pad0_cfg,
 116         .port0_cfg = {
 117                 .force_link = 1,
 118                 .speed = AR8327_PORT_SPEED_1000,
 119                 .duplex = 1,
 120                 .txpause = 1,
 121                 .rxpause = 1,
 122         },
 123         .led_cfg = &dr344_ar8327_led_cfg,
 124 };
 125
 126 static struct mdio_board_info dr344_mdio0_info[] = {
 127         {
 128                 .bus_id = "ag71xx-mdio.0",
 129                 .phy_addr = 0,
 130                 .platform_data = &dr344_ar8327_data,
 131         },
 132 };
 133
 134 static void __init dr344_setup(void)
 135 {
 136         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 137         u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
 138
 139         ath79_register_m25p80(NULL);
 140         ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
 141                                  dr344_leds_gpio);
 142         ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
 143                                         ARRAY_SIZE(dr344_gpio_keys),
 144                                         dr344_gpio_keys);
 145
 146         ath79_register_usb();
 147
 148         ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
 149
 150         ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
 151
 152         ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
 153
 154         ath79_register_pci();
 155
 156         mdiobus_register_board_info(dr344_mdio0_info,
 157                                         ARRAY_SIZE(dr344_mdio0_info));
 158
 159         ath79_register_mdio(1, 0x0);
 160         ath79_register_mdio(0, 0x0);
 161
 162         ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0);
 163         ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0);
 164
 165         ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
 166                                    AR934X_ETH_CFG_SW_ONLY_MODE);
 167
 168         /* GMAC0 is connected to an AR8327 switch */
 169         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 170         ath79_eth0_data.phy_mask = BIT(0);
 171         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 172         ath79_eth0_pll_data.pll_1000 = 0x0e000000;
 173         ath79_eth0_pll_data.pll_100 = 0x0101;
 174         ath79_eth0_pll_data.pll_10 = 0x1313;
 175
 176         /* GMAC1 is connected to the internal switch */
 177         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
 178         ath79_eth1_data.speed = SPEED_1000;
 179         ath79_eth1_data.duplex = DUPLEX_FULL;
 180
 181         ath79_register_eth(0);
 182         ath79_register_eth(1);
 183 }
 184
 185 MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup);