finally move buildroot-ng to trunk
[openwrt/staging/dedeckeh.git] / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.17/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile 2006-06-18 12:44:28.000000000 +0200
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile 2006-06-18 12:44:28.000000000 +0200
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c 2006-06-18 12:44:28.000000000 +0200
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h 2006-06-18 12:44:28.000000000 +0200
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c 2006-06-18 12:44:28.000000000 +0200
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.17/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c 2006-06-18 12:44:28.000000000 +0200
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.17/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c 2006-06-18 12:44:28.000000000 +0200
786 @@ -0,0 +1,134 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/module.h>
827 +#include <linux/mm.h>
828 +#include <linux/sched.h>
829 +#include <linux/irq.h>
830 +#include <asm/bootinfo.h>
831 +#include <asm/io.h>
832 +#include <linux/ioport.h>
833 +#include <asm/mipsregs.h>
834 +#include <asm/pgtable.h>
835 +#include <asm/reboot.h>
836 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
837 +#include <asm/idt-boards/rc32434/rc32434.h>
838 +#include <linux/pm.h>
839 +
840 +extern char *__init prom_getcmdline(void);
841 +
842 +extern void (*board_time_init) (void);
843 +extern void (*board_timer_setup) (struct irqaction * irq);
844 +extern void aruba_time_init(void);
845 +extern void aruba_timer_setup(struct irqaction *irq);
846 +extern void aruba_reset(void);
847 +
848 +#define epldMask ((volatile unsigned char *)0xB900000d)
849 +
850 +static void aruba_machine_restart(char *command)
851 +{
852 + switch (mips_machtype) {
853 + case MACH_ARUBA_AP70:
854 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
855 + break;
856 + case MACH_ARUBA_AP65:
857 + case MACH_ARUBA_AP60:
858 + default:
859 + /* Reset*/
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
863 + udelay(100);
864 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
865 + break;
866 + }
867 +}
868 +
869 +static void aruba_machine_halt(void)
870 +{
871 + for (;;) continue;
872 +}
873 +
874 +extern char * getenv(char *e);
875 +extern void unlock_ap60_70_flash(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + return 0;
899 +}
900 +
901 +int page_is_ram(unsigned long pagenr)
902 +{
903 + return 1;
904 +}
905 +
906 +const char *get_system_type(void)
907 +{
908 + switch (mips_machtype) {
909 + case MACH_ARUBA_AP70:
910 + return "Aruba AP70";
911 + case MACH_ARUBA_AP65:
912 + return "Aruba AP65";
913 + case MACH_ARUBA_AP60:
914 + return "Aruba AP60/AP61";
915 + default:
916 + return "Aruba UNKNOWN";
917 + }
918 +}
919 +
920 +EXPORT_SYMBOL(get_system_type);
921 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
922 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
923 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c 2006-06-18 12:44:28.000000000 +0200
924 @@ -0,0 +1,110 @@
925 +/**************************************************************************
926 + *
927 + * BRIEF MODULE DESCRIPTION
928 + * timer routines for IDT EB434 boards
929 + *
930 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
931 + *
932 + * This program is free software; you can redistribute it and/or modify it
933 + * under the terms of the GNU General Public License as published by the
934 + * Free Software Foundation; either version 2 of the License, or (at your
935 + * option) any later version.
936 + *
937 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
938 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
939 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
940 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
941 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
942 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
943 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
944 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
945 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
946 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
947 + *
948 + * You should have received a copy of the GNU General Public License along
949 + * with this program; if not, write to the Free Software Foundation, Inc.,
950 + * 675 Mass Ave, Cambridge, MA 02139, USA.
951 + *
952 + *
953 + **************************************************************************
954 + * May 2004 rkt, neb
955 + *
956 + * Initial Release
957 + *
958 + *
959 + *
960 + **************************************************************************
961 + */
962 +
963 +#include <linux/config.h>
964 +#include <linux/init.h>
965 +#include <linux/kernel_stat.h>
966 +#include <linux/sched.h>
967 +#include <linux/spinlock.h>
968 +#include <linux/mc146818rtc.h>
969 +#include <linux/irq.h>
970 +#include <linux/timex.h>
971 +
972 +#include <linux/param.h>
973 +#include <asm/mipsregs.h>
974 +#include <asm/ptrace.h>
975 +#include <asm/time.h>
976 +#include <asm/hardirq.h>
977 +
978 +#include <asm/mipsregs.h>
979 +#include <asm/ptrace.h>
980 +#include <asm/debug.h>
981 +#include <asm/time.h>
982 +
983 +#include <asm/idt-boards/rc32434/rc32434.h>
984 +
985 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
986 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
987 +
988 +extern unsigned int idt_cpu_freq;
989 +
990 +static unsigned long __init cal_r4koff(void)
991 +{
992 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
993 + return (mips_hpt_frequency / HZ);
994 +}
995 +
996 +void __init aruba_time_init(void)
997 +{
998 + unsigned int est_freq, flags;
999 + local_irq_save(flags);
1000 +
1001 + printk("calculating r4koff... ");
1002 + r4k_offset = cal_r4koff();
1003 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1004 +
1005 + est_freq = 2 * r4k_offset * HZ;
1006 + est_freq += 5000; /* round */
1007 + est_freq -= est_freq % 10000;
1008 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1009 + (est_freq % 1000000) * 100 / 1000000);
1010 + local_irq_restore(flags);
1011 +
1012 +}
1013 +
1014 +void __init aruba_timer_setup(struct irqaction *irq)
1015 +{
1016 + /* we are using the cpu counter for timer interrupts */
1017 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1018 +
1019 + /* to generate the first timer interrupt */
1020 + r4k_cur = (read_c0_count() + r4k_offset);
1021 + write_c0_compare(r4k_cur);
1022 +
1023 +}
1024 +
1025 +asmlinkage void aruba_timer_interrupt(struct pt_regs *regs)
1026 +{
1027 + int irq = MIPS_CPU_TIMER_IRQ;
1028 +
1029 + irq_enter();
1030 + kstat_this_cpu.irqs[irq]++;
1031 +
1032 + timer_interrupt(irq, NULL, regs);
1033 + irq_exit();
1034 +}
1035 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1036 --- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
1037 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1038 @@ -227,6 +227,17 @@
1039 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1040 a kernel for this platform.
1041
1042 +config MACH_ARUBA
1043 + bool "Support for the ARUBA product line"
1044 + select DMA_NONCOHERENT
1045 + select CPU_HAS_PREFETCH
1046 + select HW_HAS_PCI
1047 + select SWAP_IO_SPACE
1048 + select SYS_SUPPORTS_32BIT_KERNEL
1049 + select SYS_HAS_CPU_MIPS32_R1
1050 + select SYS_SUPPORTS_BIG_ENDIAN
1051 +
1052 +
1053 config MACH_JAZZ
1054 bool "Jazz family of machines"
1055 select ARC
1056 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1057 --- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
1058 +++ linux-2.6.17-owrt/arch/mips/Makefile 2006-06-18 12:44:28.000000000 +0200
1059 @@ -145,6 +145,14 @@
1060 #
1061
1062 #
1063 +# Aruba
1064 +#
1065 +
1066 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1067 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1068 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1069 +
1070 +#
1071 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1072 #
1073 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1074 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
1075 --- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
1076 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 12:48:27.000000000 +0200
1077 @@ -876,7 +876,6 @@
1078 case CPU_R10000:
1079 case CPU_R12000:
1080 case CPU_R14000:
1081 - case CPU_4KC:
1082 case CPU_SB1:
1083 case CPU_SB1A:
1084 case CPU_4KSC:
1085 @@ -904,6 +903,7 @@
1086 tlbw(p);
1087 break;
1088
1089 + case CPU_4KC:
1090 case CPU_4KEC:
1091 case CPU_24K:
1092 case CPU_34K:
1093 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1094 --- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
1095 +++ linux-2.6.17-owrt/drivers/net/Kconfig 2006-06-18 12:44:28.000000000 +0200
1096 @@ -187,6 +187,13 @@
1097
1098 source "drivers/net/arm/Kconfig"
1099
1100 +config IDT_RC32434_ETH
1101 + tristate "IDT RC32434 Local Ethernet support"
1102 + depends on NET_ETHERNET
1103 + help
1104 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1105 + To compile this driver as a module, choose M here.
1106 +
1107 config MACE
1108 tristate "MACE (Power Mac ethernet) support"
1109 depends on NET_ETHERNET && PPC_PMAC && PPC32
1110 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1111 --- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
1112 +++ linux-2.6.17-owrt/drivers/net/Makefile 2006-06-18 12:44:28.000000000 +0200
1113 @@ -38,6 +38,7 @@
1114
1115 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1116
1117 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1118 obj-$(CONFIG_DGRS) += dgrs.o
1119 obj-$(CONFIG_VORTEX) += 3c59x.o
1120 obj-$(CONFIG_TYPHOON) += typhoon.o
1121 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1122 --- linux-2.6.17/drivers/net/natsemi.c 2006-06-18 03:49:35.000000000 +0200
1123 +++ linux-2.6.17-owrt/drivers/net/natsemi.c 2006-06-18 12:44:28.000000000 +0200
1124 @@ -771,6 +771,49 @@
1125 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1126 static struct ethtool_ops ethtool_ops;
1127
1128 +#ifdef CONFIG_MACH_ARUBA
1129 +
1130 +#include <linux/ctype.h>
1131 +
1132 +#ifndef ERR
1133 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1134 +#endif
1135 +
1136 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1137 +{
1138 + int i, j;
1139 + unsigned char result, value;
1140 +
1141 + for (i=0; i<6; i++) {
1142 + result = 0;
1143 + if (i != 5 && *(macstr+2) != ':') {
1144 + ERR("invalid mac address format: %d %c\n",
1145 + i, *(macstr+2));
1146 + return -EINVAL;
1147 + }
1148 + for (j=0; j<2; j++) {
1149 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1150 + toupper(*macstr)-'A'+10) < 16) {
1151 + result = result*16 + value;
1152 + macstr++;
1153 + }
1154 + else {
1155 + ERR("invalid mac address "
1156 + "character: %c\n", *macstr);
1157 + return -EINVAL;
1158 + }
1159 + }
1160 +
1161 + macstr++;
1162 + dev->dev_addr[i] = result;
1163 + }
1164 +
1165 + dev->dev_addr[5]++;
1166 + return 0;
1167 +}
1168 +
1169 +#endif
1170 +
1171 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1172 {
1173 return (void __iomem *) dev->base_addr;
1174 @@ -871,6 +914,7 @@
1175 goto err_ioremap;
1176 }
1177
1178 +#ifndef CONFIG_MACH_ARUBA
1179 /* Work around the dropped serial bit. */
1180 prev_eedata = eeprom_read(ioaddr, 6);
1181 for (i = 0; i < 3; i++) {
1182 @@ -879,6 +923,19 @@
1183 dev->dev_addr[i*2+1] = eedata >> 7;
1184 prev_eedata = eedata;
1185 }
1186 +#else
1187 + {
1188 + char mac[32];
1189 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1190 + extern char *getenv(char *e);
1191 + memset(mac, 0, 32);
1192 + memcpy(mac, getenv("ethaddr"), 17);
1193 + if (parse_mac_addr(dev, mac)){
1194 + printk("%s: MAC address not found\n", __func__);
1195 + memcpy(dev->dev_addr, def_mac, 6);
1196 + }
1197 + }
1198 +#endif
1199
1200 dev->base_addr = (unsigned long __force) ioaddr;
1201 dev->irq = irq;
1202 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1203 --- linux-2.6.17/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1204 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1205 @@ -0,0 +1,1273 @@
1206 +/**************************************************************************
1207 + *
1208 + * BRIEF MODULE DESCRIPTION
1209 + * Driver for the IDT RC32434 on-chip ethernet controller.
1210 + *
1211 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1212 + *
1213 + * This program is free software; you can redistribute it and/or modify it
1214 + * under the terms of the GNU General Public License as published by the
1215 + * Free Software Foundation; either version 2 of the License, or (at your
1216 + * option) any later version.
1217 + *
1218 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1219 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1220 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1221 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1222 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1223 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1224 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1225 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1226 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1227 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1228 + *
1229 + * You should have received a copy of the GNU General Public License along
1230 + * with this program; if not, write to the Free Software Foundation, Inc.,
1231 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1232 + *
1233 + *
1234 + **************************************************************************
1235 + * May 2004 rkt, neb
1236 + *
1237 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1238 + *
1239 + * Aug 2004 Sadik
1240 + *
1241 + * Added NAPI
1242 + *
1243 + **************************************************************************
1244 + */
1245 +
1246 +#include <linux/config.h>
1247 +#include <linux/version.h>
1248 +#include <linux/module.h>
1249 +#include <linux/kernel.h>
1250 +#include <linux/moduleparam.h>
1251 +#include <linux/sched.h>
1252 +#include <linux/ctype.h>
1253 +#include <linux/types.h>
1254 +#include <linux/fcntl.h>
1255 +#include <linux/interrupt.h>
1256 +#include <linux/ptrace.h>
1257 +#include <linux/init.h>
1258 +#include <linux/ioport.h>
1259 +#include <linux/proc_fs.h>
1260 +#include <linux/in.h>
1261 +#include <linux/slab.h>
1262 +#include <linux/string.h>
1263 +#include <linux/delay.h>
1264 +#include <linux/netdevice.h>
1265 +#include <linux/etherdevice.h>
1266 +#include <linux/skbuff.h>
1267 +#include <linux/errno.h>
1268 +#include <asm/bootinfo.h>
1269 +#include <asm/system.h>
1270 +#include <asm/bitops.h>
1271 +#include <asm/pgtable.h>
1272 +#include <asm/segment.h>
1273 +#include <asm/io.h>
1274 +#include <asm/dma.h>
1275 +
1276 +#include "rc32434_eth.h"
1277 +
1278 +#define DRIVER_VERSION "(mar2904)"
1279 +
1280 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1281 +
1282 +
1283 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1284 + ((dev)->dev_addr[1]))
1285 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1286 + ((dev)->dev_addr[3] << 16) | \
1287 + ((dev)->dev_addr[4] << 8) | \
1288 + ((dev)->dev_addr[5]))
1289 +
1290 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1291 +static char mac0[18] = "08:00:06:05:40:01";
1292 +
1293 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
1294 +module_param_string(mac0, mac0, 18, 0);
1295 +#else
1296 +MODULE_PARM(mac0, "c18");
1297 +#endif
1298 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1299 +
1300 +static struct rc32434_if_t {
1301 + char *name;
1302 + struct net_device *dev;
1303 + char* mac_str;
1304 + int weight;
1305 + u32 iobase;
1306 + u32 rxdmabase;
1307 + u32 txdmabase;
1308 + int rx_dma_irq;
1309 + int tx_dma_irq;
1310 + int rx_ovr_irq;
1311 + int tx_und_irq;
1312 +} rc32434_iflist[] =
1313 +{
1314 + {
1315 + "rc32434_eth0", NULL, mac0,
1316 + 64,
1317 + ETH0_PhysicalAddress,
1318 + ETH0_RX_DMA_ADDR,
1319 + ETH0_TX_DMA_ADDR,
1320 + ETH0_DMA_RX_IRQ,
1321 + ETH0_DMA_TX_IRQ,
1322 + ETH0_RX_OVR_IRQ,
1323 + ETH0_TX_UND_IRQ
1324 + }
1325 +};
1326 +
1327 +
1328 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1329 +{
1330 + int i, j;
1331 + unsigned char result, value;
1332 +
1333 + for (i=0; i<6; i++) {
1334 + result = 0;
1335 + if (i != 5 && *(macstr+2) != ':') {
1336 + ERR("invalid mac address format: %d %c\n",
1337 + i, *(macstr+2));
1338 + return -EINVAL;
1339 + }
1340 + for (j=0; j<2; j++) {
1341 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1342 + toupper(*macstr)-'A'+10) < 16) {
1343 + result = result*16 + value;
1344 + macstr++;
1345 + }
1346 + else {
1347 + ERR("invalid mac address "
1348 + "character: %c\n", *macstr);
1349 + return -EINVAL;
1350 + }
1351 + }
1352 +
1353 + macstr++;
1354 + dev->dev_addr[i] = result;
1355 + }
1356 +
1357 + return 0;
1358 +}
1359 +
1360 +
1361 +
1362 +static inline void rc32434_abort_tx(struct net_device *dev)
1363 +{
1364 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1365 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1366 +
1367 +}
1368 +
1369 +static inline void rc32434_abort_rx(struct net_device *dev)
1370 +{
1371 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1372 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1373 +
1374 +}
1375 +
1376 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1377 +{
1378 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1379 +}
1380 +
1381 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1382 +{
1383 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1384 +}
1385 +
1386 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1387 +{
1388 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1389 +}
1390 +
1391 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1392 +{
1393 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1394 +}
1395 +
1396 +#ifdef RC32434_PROC_DEBUG
1397 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1398 + int length, int *eof, void *data)
1399 +{
1400 + struct net_device *dev = (struct net_device *)data;
1401 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1402 + int len = 0;
1403 +
1404 + /* print out header */
1405 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1406 + len += sprintf (buf + len,
1407 + "DMA halt count = %10d, DMA run count = %10d\n",
1408 + lp->dma_halt_cnt, lp->dma_run_cnt);
1409 +
1410 + if (fpos >= len) {
1411 + *start = buf;
1412 + *eof = 1;
1413 + return 0;
1414 + }
1415 + *start = buf + fpos;
1416 +
1417 + if ((len -= fpos) > length)
1418 + return length;
1419 + *eof = 1;
1420 +
1421 + return len;
1422 +
1423 +}
1424 +#endif
1425 +
1426 +
1427 +/*
1428 + * Restart the RC32434 ethernet controller.
1429 + */
1430 +static int rc32434_restart(struct net_device *dev)
1431 +{
1432 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1433 +
1434 + /*
1435 + * Disable interrupts
1436 + */
1437 + disable_irq(lp->rx_irq);
1438 + disable_irq(lp->tx_irq);
1439 +#ifdef RC32434_REVISION
1440 + disable_irq(lp->ovr_irq);
1441 +#endif
1442 + disable_irq(lp->und_irq);
1443 +
1444 + /* Mask F E bit in Tx DMA */
1445 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1446 + /* Mask D H E bit in Rx DMA */
1447 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1448 +
1449 + rc32434_init(dev);
1450 + rc32434_multicast_list(dev);
1451 +
1452 + enable_irq(lp->und_irq);
1453 +#ifdef RC32434_REVISION
1454 + enable_irq(lp->ovr_irq);
1455 +#endif
1456 + enable_irq(lp->tx_irq);
1457 + enable_irq(lp->rx_irq);
1458 +
1459 + return 0;
1460 +}
1461 +
1462 +int rc32434_init_module(void)
1463 +{
1464 +#ifdef CONFIG_MACH_ARUBA
1465 + if (mips_machtype != MACH_ARUBA_AP70)
1466 + return 1;
1467 +#endif
1468 +
1469 + printk(KERN_INFO DRIVER_NAME " \n");
1470 + return rc32434_probe(0);
1471 +}
1472 +
1473 +static int rc32434_probe(int port_num)
1474 +{
1475 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1476 + struct rc32434_local *lp = NULL;
1477 + struct net_device *dev = NULL;
1478 + int i, retval,err;
1479 +
1480 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1481 + if(!dev) {
1482 + ERR("rc32434_eth: alloc_etherdev failed\n");
1483 + return -1;
1484 + }
1485 +
1486 + SET_MODULE_OWNER(dev);
1487 + bif->dev = dev;
1488 +
1489 +#ifdef CONFIG_MACH_ARUBA
1490 + {
1491 + extern char * getenv(char *e);
1492 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1493 + }
1494 +#endif
1495 +
1496 + printk("mac: %s\n", bif->mac_str);
1497 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1498 + ERR("MAC address parse failed\n");
1499 + free_netdev(dev);
1500 + return -1;
1501 + }
1502 +
1503 +
1504 + /* Initialize the device structure. */
1505 + if (dev->priv == NULL) {
1506 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1507 + memset(lp, 0, sizeof(struct rc32434_local));
1508 + }
1509 + else {
1510 + lp = (struct rc32434_local *)dev->priv;
1511 + }
1512 +
1513 + lp->rx_irq = bif->rx_dma_irq;
1514 + lp->tx_irq = bif->tx_dma_irq;
1515 + lp->ovr_irq = bif->rx_ovr_irq;
1516 + lp->und_irq = bif->tx_und_irq;
1517 +
1518 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1519 +
1520 + if (!lp->eth_regs) {
1521 + ERR("Can't remap eth registers\n");
1522 + retval = -ENXIO;
1523 + goto probe_err_out;
1524 + }
1525 +
1526 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1527 +
1528 + if (!lp->rx_dma_regs) {
1529 + ERR("Can't remap Rx DMA registers\n");
1530 + retval = -ENXIO;
1531 + goto probe_err_out;
1532 + }
1533 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1534 +
1535 + if (!lp->tx_dma_regs) {
1536 + ERR("Can't remap Tx DMA registers\n");
1537 + retval = -ENXIO;
1538 + goto probe_err_out;
1539 + }
1540 +
1541 +#ifdef RC32434_PROC_DEBUG
1542 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1543 + rc32434_read_proc, dev);
1544 +#endif
1545 +
1546 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1547 + if (!lp->td_ring) {
1548 + ERR("Can't allocate descriptors\n");
1549 + retval = -ENOMEM;
1550 + goto probe_err_out;
1551 + }
1552 +
1553 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1554 +
1555 + /* now convert TD_RING pointer to KSEG1 */
1556 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1557 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1558 +
1559 +
1560 + spin_lock_init(&lp->lock);
1561 +
1562 + dev->base_addr = bif->iobase;
1563 + /* just use the rx dma irq */
1564 + dev->irq = bif->rx_dma_irq;
1565 +
1566 + dev->priv = lp;
1567 +
1568 + dev->open = rc32434_open;
1569 + dev->stop = rc32434_close;
1570 + dev->hard_start_xmit = rc32434_send_packet;
1571 + dev->get_stats = rc32434_get_stats;
1572 + dev->set_multicast_list = &rc32434_multicast_list;
1573 + dev->tx_timeout = rc32434_tx_timeout;
1574 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1575 +
1576 +#ifdef CONFIG_IDT_USE_NAPI
1577 + dev->poll = rc32434_poll;
1578 + dev->weight = bif->weight;
1579 + printk("Using NAPI with weight %d\n",dev->weight);
1580 +#else
1581 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1582 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1583 +#endif
1584 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1585 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1586 +
1587 + if ((err = register_netdev(dev))) {
1588 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1589 + free_netdev(dev);
1590 + retval = -EINVAL;
1591 + goto probe_err_out;
1592 + }
1593 +
1594 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1595 + for (i = 0; i < 6; i++) {
1596 + printk("%2.2x", dev->dev_addr[i]);
1597 + if (i<5)
1598 + printk(":");
1599 + }
1600 + printk("\n");
1601 +
1602 + return 0;
1603 +
1604 + probe_err_out:
1605 + rc32434_cleanup_module();
1606 + ERR(" failed. Returns %d\n", retval);
1607 + return retval;
1608 +
1609 +}
1610 +
1611 +
1612 +static void rc32434_cleanup_module(void)
1613 +{
1614 + int i;
1615 +
1616 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1617 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1618 + if (bif->dev != NULL) {
1619 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1620 + if (lp != NULL) {
1621 + if (lp->eth_regs)
1622 + iounmap((void*)lp->eth_regs);
1623 + if (lp->rx_dma_regs)
1624 + iounmap((void*)lp->rx_dma_regs);
1625 + if (lp->tx_dma_regs)
1626 + iounmap((void*)lp->tx_dma_regs);
1627 + if (lp->td_ring)
1628 + kfree((void*)KSEG0ADDR(lp->td_ring));
1629 +
1630 +#ifdef RC32434_PROC_DEBUG
1631 + if (lp->ps) {
1632 + remove_proc_entry(bif->name, proc_net);
1633 + }
1634 +#endif
1635 + kfree(lp);
1636 + }
1637 +
1638 + unregister_netdev(bif->dev);
1639 + free_netdev(bif->dev);
1640 + kfree(bif->dev);
1641 + }
1642 + }
1643 +}
1644 +
1645 +
1646 +
1647 +static int rc32434_open(struct net_device *dev)
1648 +{
1649 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1650 +
1651 + /* Initialize */
1652 + if (rc32434_init(dev)) {
1653 + ERR("Error: cannot open the Ethernet device\n");
1654 + return -EAGAIN;
1655 + }
1656 +
1657 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1658 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1659 + SA_SHIRQ | SA_INTERRUPT,
1660 + "rc32434 ethernet Rx", dev)) {
1661 + ERR(": unable to get Rx DMA IRQ %d\n",
1662 + lp->rx_irq);
1663 + return -EAGAIN;
1664 + }
1665 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1666 + SA_SHIRQ | SA_INTERRUPT,
1667 + "rc32434 ethernet Tx", dev)) {
1668 + ERR(": unable to get Tx DMA IRQ %d\n",
1669 + lp->tx_irq);
1670 + free_irq(lp->rx_irq, dev);
1671 + return -EAGAIN;
1672 + }
1673 +
1674 +#ifdef RC32434_REVISION
1675 + /* Install handler for overrun error. */
1676 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1677 + SA_SHIRQ | SA_INTERRUPT,
1678 + "Ethernet Overflow", dev)) {
1679 + ERR(": unable to get OVR IRQ %d\n",
1680 + lp->ovr_irq);
1681 + free_irq(lp->rx_irq, dev);
1682 + free_irq(lp->tx_irq, dev);
1683 + return -EAGAIN;
1684 + }
1685 +#endif
1686 +
1687 + /* Install handler for underflow error. */
1688 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1689 + SA_SHIRQ | SA_INTERRUPT,
1690 + "Ethernet Underflow", dev)) {
1691 + ERR(": unable to get UND IRQ %d\n",
1692 + lp->und_irq);
1693 + free_irq(lp->rx_irq, dev);
1694 + free_irq(lp->tx_irq, dev);
1695 +#ifdef RC32434_REVISION
1696 + free_irq(lp->ovr_irq, dev);
1697 +#endif
1698 + return -EAGAIN;
1699 + }
1700 +
1701 +
1702 + return 0;
1703 +}
1704 +
1705 +
1706 +
1707 +
1708 +static int rc32434_close(struct net_device *dev)
1709 +{
1710 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1711 + u32 tmp;
1712 +
1713 + /* Disable interrupts */
1714 + disable_irq(lp->rx_irq);
1715 + disable_irq(lp->tx_irq);
1716 +#ifdef RC32434_REVISION
1717 + disable_irq(lp->ovr_irq);
1718 +#endif
1719 + disable_irq(lp->und_irq);
1720 +
1721 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1722 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1723 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1724 +
1725 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1726 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1727 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1728 +
1729 + free_irq(lp->rx_irq, dev);
1730 + free_irq(lp->tx_irq, dev);
1731 +#ifdef RC32434_REVISION
1732 + free_irq(lp->ovr_irq, dev);
1733 +#endif
1734 + free_irq(lp->und_irq, dev);
1735 + return 0;
1736 +}
1737 +
1738 +
1739 +/* transmit packet */
1740 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1741 +{
1742 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1743 + unsigned long flags;
1744 + u32 length;
1745 + DMAD_t td;
1746 +
1747 +
1748 + spin_lock_irqsave(&lp->lock, flags);
1749 +
1750 + td = &lp->td_ring[lp->tx_chain_tail];
1751 +
1752 + /* stop queue when full, drop pkts if queue already full */
1753 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1754 + lp->tx_full = 1;
1755 +
1756 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1757 + netif_stop_queue(dev);
1758 + }
1759 + else {
1760 + lp->stats.tx_dropped++;
1761 + dev_kfree_skb_any(skb);
1762 + spin_unlock_irqrestore(&lp->lock, flags);
1763 + return 1;
1764 + }
1765 + }
1766 +
1767 + lp->tx_count ++;
1768 +
1769 + lp->tx_skb[lp->tx_chain_tail] = skb;
1770 +
1771 + length = skb->len;
1772 +
1773 + /* Setup the transmit descriptor. */
1774 + td->ca = CPHYSADDR(skb->data);
1775 +
1776 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1777 + if( lp->tx_chain_status == empty ) {
1778 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1779 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1780 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1781 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1782 + }
1783 + else {
1784 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1785 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1786 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1787 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1788 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1789 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1790 + lp->tx_chain_status = empty;
1791 + }
1792 + }
1793 + else {
1794 + if( lp->tx_chain_status == empty ) {
1795 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1796 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1797 + lp->tx_chain_status = filled;
1798 + }
1799 + else {
1800 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1801 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1802 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1803 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1804 + }
1805 + }
1806 +
1807 + dev->trans_start = jiffies;
1808 +
1809 + spin_unlock_irqrestore(&lp->lock, flags);
1810 +
1811 + return 0;
1812 +}
1813 +
1814 +
1815 +/* Ethernet MII-PHY Handler */
1816 +static void rc32434_mii_handler(unsigned long data)
1817 +{
1818 + struct net_device *dev = (struct net_device *)data;
1819 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1820 + unsigned long flags;
1821 + unsigned long duplex_status;
1822 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1823 +
1824 + spin_lock_irqsave(&lp->lock, flags);
1825 +
1826 + /* Two ports are using the same MII, the difference is the PHY address */
1827 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1828 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1829 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1830 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1831 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1832 +
1833 + ERR("irq:%x port_addr:%x RDD:%x\n",
1834 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1835 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1836 + if(duplex_status != lp->duplex_mode) {
1837 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1838 + lp->duplex_mode = duplex_status;
1839 + rc32434_restart(dev);
1840 + }
1841 +
1842 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1843 + add_timer(&lp->mii_phy_timer);
1844 +
1845 + spin_unlock_irqrestore(&lp->lock, flags);
1846 +
1847 +}
1848 +
1849 +#ifdef RC32434_REVISION
1850 +/* Ethernet Rx Overflow interrupt */
1851 +static irqreturn_t
1852 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1853 +{
1854 + struct net_device *dev = (struct net_device *)dev_id;
1855 + struct rc32434_local *lp;
1856 + unsigned int ovr;
1857 + irqreturn_t retval = IRQ_NONE;
1858 +
1859 + ASSERT(dev != NULL);
1860 +
1861 + lp = (struct rc32434_local *)dev->priv;
1862 + spin_lock(&lp->lock);
1863 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1864 +
1865 + if(ovr & ETHINTFC_ovr_m) {
1866 + netif_stop_queue(dev);
1867 +
1868 + /* clear OVR bit */
1869 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1870 +
1871 + /* Restart interface */
1872 + rc32434_restart(dev);
1873 + retval = IRQ_HANDLED;
1874 + }
1875 + spin_unlock(&lp->lock);
1876 +
1877 + return retval;
1878 +}
1879 +
1880 +#endif
1881 +
1882 +
1883 +/* Ethernet Tx Underflow interrupt */
1884 +static irqreturn_t
1885 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1886 +{
1887 + struct net_device *dev = (struct net_device *)dev_id;
1888 + struct rc32434_local *lp;
1889 + unsigned int und;
1890 + irqreturn_t retval = IRQ_NONE;
1891 +
1892 + ASSERT(dev != NULL);
1893 +
1894 + lp = (struct rc32434_local *)dev->priv;
1895 +
1896 + spin_lock(&lp->lock);
1897 +
1898 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1899 +
1900 + if(und & ETHINTFC_und_m) {
1901 + netif_stop_queue(dev);
1902 +
1903 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1904 +
1905 + /* Restart interface */
1906 + rc32434_restart(dev);
1907 + retval = IRQ_HANDLED;
1908 + }
1909 +
1910 + spin_unlock(&lp->lock);
1911 +
1912 + return retval;
1913 +}
1914 +
1915 +
1916 +/* Ethernet Rx DMA interrupt */
1917 +static irqreturn_t
1918 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1919 +{
1920 + struct net_device *dev = (struct net_device *)dev_id;
1921 + struct rc32434_local* lp;
1922 + volatile u32 dmas,dmasm;
1923 + irqreturn_t retval;
1924 +
1925 + ASSERT(dev != NULL);
1926 +
1927 + lp = (struct rc32434_local *)dev->priv;
1928 +
1929 + spin_lock(&lp->lock);
1930 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1931 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1932 + /* Mask D H E bit in Rx DMA */
1933 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1934 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1935 +#ifdef CONFIG_IDT_USE_NAPI
1936 + if(netif_rx_schedule_prep(dev))
1937 + __netif_rx_schedule(dev);
1938 +#else
1939 + tasklet_hi_schedule(lp->rx_tasklet);
1940 +#endif
1941 +
1942 + if (dmas & DMAS_e_m)
1943 + ERR(": DMA error\n");
1944 +
1945 + retval = IRQ_HANDLED;
1946 + }
1947 + else
1948 + retval = IRQ_NONE;
1949 +
1950 + spin_unlock(&lp->lock);
1951 + return retval;
1952 +}
1953 +
1954 +#ifdef CONFIG_IDT_USE_NAPI
1955 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1956 +#else
1957 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1958 +#endif
1959 +{
1960 + struct net_device *dev = (struct net_device *)rx_data_dev;
1961 + struct rc32434_local* lp = netdev_priv(dev);
1962 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1963 + struct sk_buff *skb, *skb_new;
1964 + u8* pkt_buf;
1965 + u32 devcs, count, pkt_len, pktuncrc_len;
1966 + volatile u32 dmas;
1967 +#ifdef CONFIG_IDT_USE_NAPI
1968 + u32 received = 0;
1969 + int rx_work_limit = min(*budget,dev->quota);
1970 +#else
1971 + unsigned long flags;
1972 + spin_lock_irqsave(&lp->lock, flags);
1973 +#endif
1974 +
1975 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1976 +#ifdef CONFIG_IDT_USE_NAPI
1977 + if(--rx_work_limit <0)
1978 + {
1979 + break;
1980 + }
1981 +#endif
1982 + /* init the var. used for the later operations within the while loop */
1983 + skb_new = NULL;
1984 + devcs = rd->devcs;
1985 + pkt_len = RCVPKT_LENGTH(devcs);
1986 + skb = lp->rx_skb[lp->rx_next_done];
1987 +
1988 + if (count < 64) {
1989 + lp->stats.rx_errors++;
1990 + lp->stats.rx_dropped++;
1991 + }
1992 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1993 + /* check that this is a whole packet */
1994 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1995 + lp->stats.rx_errors++;
1996 + lp->stats.rx_dropped++;
1997 + }
1998 + else if ( (devcs & ETHRX_rok_m) ) {
1999 +
2000 + {
2001 + /* must be the (first and) last descriptor then */
2002 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
2003 +
2004 + pktuncrc_len = pkt_len - 4;
2005 + /* invalidate the cache */
2006 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2007 +
2008 + /* Malloc up new buffer. */
2009 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2010 +
2011 + if (skb_new != NULL){
2012 + /* Make room */
2013 + skb_put(skb, pktuncrc_len);
2014 +
2015 + skb->protocol = eth_type_trans(skb, dev);
2016 +
2017 + /* pass the packet to upper layers */
2018 +#ifdef CONFIG_IDT_USE_NAPI
2019 + netif_receive_skb(skb);
2020 +#else
2021 + netif_rx(skb);
2022 +#endif
2023 +
2024 + dev->last_rx = jiffies;
2025 + lp->stats.rx_packets++;
2026 + lp->stats.rx_bytes += pktuncrc_len;
2027 +
2028 + if (IS_RCV_MP(devcs))
2029 + lp->stats.multicast++;
2030 +
2031 + /* 16 bit align */
2032 + skb_reserve(skb_new, 2);
2033 +
2034 + skb_new->dev = dev;
2035 + lp->rx_skb[lp->rx_next_done] = skb_new;
2036 + }
2037 + else {
2038 + ERR("no memory, dropping rx packet.\n");
2039 + lp->stats.rx_errors++;
2040 + lp->stats.rx_dropped++;
2041 + }
2042 + }
2043 +
2044 + }
2045 + else {
2046 + /* This should only happen if we enable accepting broken packets */
2047 + lp->stats.rx_errors++;
2048 + lp->stats.rx_dropped++;
2049 +
2050 + /* add statistics counters */
2051 + if (IS_RCV_CRC_ERR(devcs)) {
2052 + DBG(2, "RX CRC error\n");
2053 + lp->stats.rx_crc_errors++;
2054 + }
2055 + else if (IS_RCV_LOR_ERR(devcs)) {
2056 + DBG(2, "RX LOR error\n");
2057 + lp->stats.rx_length_errors++;
2058 + }
2059 + else if (IS_RCV_LE_ERR(devcs)) {
2060 + DBG(2, "RX LE error\n");
2061 + lp->stats.rx_length_errors++;
2062 + }
2063 + else if (IS_RCV_OVR_ERR(devcs)) {
2064 + lp->stats.rx_over_errors++;
2065 + }
2066 + else if (IS_RCV_CV_ERR(devcs)) {
2067 + /* code violation */
2068 + DBG(2, "RX CV error\n");
2069 + lp->stats.rx_frame_errors++;
2070 + }
2071 + else if (IS_RCV_CES_ERR(devcs)) {
2072 + DBG(2, "RX Preamble error\n");
2073 + }
2074 + }
2075 +
2076 + rd->devcs = 0;
2077 +
2078 + /* restore descriptor's curr_addr */
2079 + if(skb_new)
2080 + rd->ca = CPHYSADDR(skb_new->data);
2081 + else
2082 + rd->ca = CPHYSADDR(skb->data);
2083 +
2084 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2085 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2086 +
2087 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2088 + rd = &lp->rd_ring[lp->rx_next_done];
2089 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2090 + }
2091 +#ifdef CONFIG_IDT_USE_NAPI
2092 + dev->quota -= received;
2093 + *budget =- received;
2094 + if(rx_work_limit < 0)
2095 + goto not_done;
2096 +#endif
2097 +
2098 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2099 +
2100 + if(dmas & DMAS_h_m) {
2101 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2102 +#ifdef RC32434_PROC_DEBUG
2103 + lp->dma_halt_cnt++;
2104 +#endif
2105 + rd->devcs = 0;
2106 + skb = lp->rx_skb[lp->rx_next_done];
2107 + rd->ca = CPHYSADDR(skb->data);
2108 + rc32434_chain_rx(lp,rd);
2109 + }
2110 +
2111 +#ifdef CONFIG_IDT_USE_NAPI
2112 + netif_rx_complete(dev);
2113 +#endif
2114 + /* Enable D H E bit in Rx DMA */
2115 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2116 +#ifdef CONFIG_IDT_USE_NAPI
2117 + return 0;
2118 + not_done:
2119 + return 1;
2120 +#else
2121 + spin_unlock_irqrestore(&lp->lock, flags);
2122 + return;
2123 +#endif
2124 +
2125 +
2126 +}
2127 +
2128 +
2129 +
2130 +/* Ethernet Tx DMA interrupt */
2131 +static irqreturn_t
2132 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2133 +{
2134 + struct net_device *dev = (struct net_device *)dev_id;
2135 + struct rc32434_local *lp;
2136 + volatile u32 dmas,dmasm;
2137 + irqreturn_t retval;
2138 +
2139 + ASSERT(dev != NULL);
2140 +
2141 + lp = (struct rc32434_local *)dev->priv;
2142 +
2143 + spin_lock(&lp->lock);
2144 +
2145 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2146 +
2147 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2148 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2149 + /* Mask F E bit in Tx DMA */
2150 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2151 +
2152 + tasklet_hi_schedule(lp->tx_tasklet);
2153 +
2154 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2155 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2156 + lp->tx_chain_status = empty;
2157 + lp->tx_chain_head = lp->tx_chain_tail;
2158 + dev->trans_start = jiffies;
2159 + }
2160 +
2161 + if (dmas & DMAS_e_m)
2162 + ERR(": DMA error\n");
2163 +
2164 + retval = IRQ_HANDLED;
2165 + }
2166 + else
2167 + retval = IRQ_NONE;
2168 +
2169 + spin_unlock(&lp->lock);
2170 +
2171 + return retval;
2172 +}
2173 +
2174 +
2175 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2176 +{
2177 + struct net_device *dev = (struct net_device *)tx_data_dev;
2178 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2179 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2180 + u32 devcs;
2181 + unsigned long flags;
2182 + volatile u32 dmas;
2183 +
2184 + spin_lock_irqsave(&lp->lock, flags);
2185 +
2186 + /* process all desc that are done */
2187 + while(IS_DMA_FINISHED(td->control)) {
2188 + if(lp->tx_full == 1) {
2189 + netif_wake_queue(dev);
2190 + lp->tx_full = 0;
2191 + }
2192 +
2193 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2194 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2195 + lp->stats.tx_errors++;
2196 + lp->stats.tx_dropped++;
2197 +
2198 + /* should never happen */
2199 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2200 + }
2201 + else if (IS_TX_TOK(devcs)) {
2202 + lp->stats.tx_packets++;
2203 + }
2204 + else {
2205 + lp->stats.tx_errors++;
2206 + lp->stats.tx_dropped++;
2207 +
2208 + /* underflow */
2209 + if (IS_TX_UND_ERR(devcs))
2210 + lp->stats.tx_fifo_errors++;
2211 +
2212 + /* oversized frame */
2213 + if (IS_TX_OF_ERR(devcs))
2214 + lp->stats.tx_aborted_errors++;
2215 +
2216 + /* excessive deferrals */
2217 + if (IS_TX_ED_ERR(devcs))
2218 + lp->stats.tx_carrier_errors++;
2219 +
2220 + /* collisions: medium busy */
2221 + if (IS_TX_EC_ERR(devcs))
2222 + lp->stats.collisions++;
2223 +
2224 + /* late collision */
2225 + if (IS_TX_LC_ERR(devcs))
2226 + lp->stats.tx_window_errors++;
2227 +
2228 + }
2229 +
2230 + /* We must always free the original skb */
2231 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2232 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2233 + lp->tx_skb[lp->tx_next_done] = NULL;
2234 + }
2235 +
2236 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2237 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2238 + lp->td_ring[lp->tx_next_done].link = 0;
2239 + lp->td_ring[lp->tx_next_done].ca = 0;
2240 + lp->tx_count --;
2241 +
2242 + /* go on to next transmission */
2243 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2244 + td = &lp->td_ring[lp->tx_next_done];
2245 +
2246 + }
2247 +
2248 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2249 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2250 +
2251 + /* Enable F E bit in Tx DMA */
2252 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2253 + spin_unlock_irqrestore(&lp->lock, flags);
2254 +
2255 +}
2256 +
2257 +
2258 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2259 +{
2260 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2261 + return &lp->stats;
2262 +}
2263 +
2264 +
2265 +/*
2266 + * Set or clear the multicast filter for this adaptor.
2267 + */
2268 +static void rc32434_multicast_list(struct net_device *dev)
2269 +{
2270 + /* listen to broadcasts always and to treat */
2271 + /* IFF bits independantly */
2272 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2273 + unsigned long flags;
2274 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2275 +
2276 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2277 + recognise |= ETHARC_pro_m;
2278 +
2279 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2280 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2281 + else if (dev->mc_count > 0) {
2282 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2283 + recognise |= ETHARC_am_m; /* for the time being */
2284 + }
2285 +
2286 + spin_lock_irqsave(&lp->lock, flags);
2287 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2288 + spin_unlock_irqrestore(&lp->lock, flags);
2289 +}
2290 +
2291 +
2292 +static void rc32434_tx_timeout(struct net_device *dev)
2293 +{
2294 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2295 + unsigned long flags;
2296 +
2297 + spin_lock_irqsave(&lp->lock, flags);
2298 + rc32434_restart(dev);
2299 + spin_unlock_irqrestore(&lp->lock, flags);
2300 +
2301 +}
2302 +
2303 +
2304 +/*
2305 + * Initialize the RC32434 ethernet controller.
2306 + */
2307 +static int rc32434_init(struct net_device *dev)
2308 +{
2309 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2310 + int i, j;
2311 +
2312 + /* Disable DMA */
2313 + rc32434_abort_tx(dev);
2314 + rc32434_abort_rx(dev);
2315 +
2316 + /* reset ethernet logic */
2317 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2318 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2319 + dev->trans_start = jiffies;
2320 +
2321 + /* Enable Ethernet Interface */
2322 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2323 +
2324 +#ifndef CONFIG_IDT_USE_NAPI
2325 + tasklet_disable(lp->rx_tasklet);
2326 +#endif
2327 + tasklet_disable(lp->tx_tasklet);
2328 +
2329 + /* Initialize the transmit Descriptors */
2330 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2331 + lp->td_ring[i].control = DMAD_iof_m;
2332 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2333 + lp->td_ring[i].ca = 0;
2334 + lp->td_ring[i].link = 0;
2335 + if (lp->tx_skb[i] != NULL) {
2336 + dev_kfree_skb_any(lp->tx_skb[i]);
2337 + lp->tx_skb[i] = NULL;
2338 + }
2339 + }
2340 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2341 + lp-> tx_chain_status = empty;
2342 +
2343 + /*
2344 + * Initialize the receive descriptors so that they
2345 + * become a circular linked list, ie. let the last
2346 + * descriptor point to the first again.
2347 + */
2348 + for (i=0; i<RC32434_NUM_RDS; i++) {
2349 + struct sk_buff *skb = lp->rx_skb[i];
2350 +
2351 + if (lp->rx_skb[i] == NULL) {
2352 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2353 + if (skb == NULL) {
2354 + ERR("No memory in the system\n");
2355 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2356 + if (lp->rx_skb[j] != NULL)
2357 + dev_kfree_skb_any(lp->rx_skb[j]);
2358 +
2359 + return 1;
2360 + }
2361 + else {
2362 + skb->dev = dev;
2363 + skb_reserve(skb, 2);
2364 + lp->rx_skb[i] = skb;
2365 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2366 +
2367 + }
2368 + }
2369 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2370 + lp->rd_ring[i].devcs = 0;
2371 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2372 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2373 +
2374 + }
2375 + /* loop back */
2376 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2377 + lp->rx_next_done = 0;
2378 +
2379 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2380 + lp->rx_chain_head = 0;
2381 + lp->rx_chain_tail = 0;
2382 + lp->rx_chain_status = empty;
2383 +
2384 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2385 + /* Start Rx DMA */
2386 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2387 +
2388 + /* Enable F E bit in Tx DMA */
2389 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2390 + /* Enable D H E bit in Rx DMA */
2391 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2392 +
2393 + /* Accept only packets destined for this Ethernet device address */
2394 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2395 +
2396 + /* Set all Ether station address registers to their initial values */
2397 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2398 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2399 +
2400 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2401 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2402 +
2403 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2404 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2405 +
2406 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2407 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2408 +
2409 +
2410 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2411 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2412 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2413 +
2414 + /* Back to back inter-packet-gap */
2415 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2416 + /* Non - Back to back inter-packet-gap */
2417 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2418 +
2419 + /* Management Clock Prescaler Divisor */
2420 + /* Clock independent setting */
2421 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2422 + &lp->eth_regs->ethmcp);
2423 +
2424 + /* don't transmit until fifo contains 48b */
2425 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2426 +
2427 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2428 +
2429 +#ifndef CONFIG_IDT_USE_NAPI
2430 + tasklet_enable(lp->rx_tasklet);
2431 +#endif
2432 + tasklet_enable(lp->tx_tasklet);
2433 +
2434 + netif_start_queue(dev);
2435 +
2436 +
2437 + return 0;
2438 +
2439 +}
2440 +
2441 +
2442 +#ifndef MODULE
2443 +
2444 +static int __init rc32434_setup(char *options)
2445 +{
2446 + /* no options yet */
2447 + return 1;
2448 +}
2449 +
2450 +static int __init rc32434_setup_ethaddr0(char *options)
2451 +{
2452 + memcpy(mac0, options, 17);
2453 + mac0[17]= '\0';
2454 + return 1;
2455 +}
2456 +
2457 +__setup("rc32434eth=", rc32434_setup);
2458 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2459 +
2460 +
2461 +#endif /* MODULE */
2462 +
2463 +module_init(rc32434_init_module);
2464 +module_exit(rc32434_cleanup_module);
2465 +
2466 +
2467 +
2468 +
2469 +
2470 +
2471 +
2472 +
2473 +
2474 +
2475 +
2476 +
2477 +
2478 +
2479 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2480 --- linux-2.6.17/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2481 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2482 @@ -0,0 +1,187 @@
2483 +/**************************************************************************
2484 + *
2485 + * BRIEF MODULE DESCRIPTION
2486 + * Definitions for IDT RC32434 on-chip ethernet controller.
2487 + *
2488 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2489 + *
2490 + * This program is free software; you can redistribute it and/or modify it
2491 + * under the terms of the GNU General Public License as published by the
2492 + * Free Software Foundation; either version 2 of the License, or (at your
2493 + * option) any later version.
2494 + *
2495 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2496 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2497 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2498 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2499 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2500 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2501 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2502 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2503 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2504 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2505 + *
2506 + * You should have received a copy of the GNU General Public License along
2507 + * with this program; if not, write to the Free Software Foundation, Inc.,
2508 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2509 + *
2510 + *
2511 + **************************************************************************
2512 + * May 2004 rkt, neb
2513 + *
2514 + * Initial Release
2515 + *
2516 + * Aug 2004
2517 + *
2518 + * Added NAPI
2519 + *
2520 + **************************************************************************
2521 + */
2522 +
2523 +
2524 +#include <asm/idt-boards/rc32434/rc32434.h>
2525 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2526 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2527 +
2528 +#define RC32434_DEBUG 2
2529 +//#define RC32434_PROC_DEBUG
2530 +#undef RC32434_DEBUG
2531 +
2532 +#ifdef RC32434_DEBUG
2533 +
2534 +/* use 0 for production, 1 for verification, >2 for debug */
2535 +static int rc32434_debug = RC32434_DEBUG;
2536 +#define ASSERT(expr) \
2537 + if(!(expr)) { \
2538 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2539 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2540 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2541 +#else
2542 +#define ASSERT(expr) do {} while (0)
2543 +#define DBG(lvl, format, arg...) do {} while (0)
2544 +#endif
2545 +
2546 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2547 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2548 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2549 +
2550 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2551 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2552 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2553 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2554 +
2555 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2556 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2557 +
2558 +/* the following must be powers of two */
2559 +#ifdef CONFIG_IDT_USE_NAPI
2560 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2561 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2562 +#else
2563 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2564 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2565 +#endif
2566 +
2567 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2568 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2569 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2570 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2571 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2572 +
2573 +#define RC32434_TX_TIMEOUT HZ * 100
2574 +
2575 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2576 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2577 +
2578 +enum status { filled, empty};
2579 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2580 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2581 +
2582 +
2583 +/* Information that need to be kept for each board. */
2584 +struct rc32434_local {
2585 + ETH_t eth_regs;
2586 + DMA_Chan_t rx_dma_regs;
2587 + DMA_Chan_t tx_dma_regs;
2588 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2589 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2590 +
2591 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2592 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2593 +
2594 +#ifndef CONFIG_IDT_USE_NAPI
2595 + struct tasklet_struct * rx_tasklet;
2596 +#endif
2597 + struct tasklet_struct * tx_tasklet;
2598 +
2599 + int rx_next_done;
2600 + int rx_chain_head;
2601 + int rx_chain_tail;
2602 + enum status rx_chain_status;
2603 +
2604 + int tx_next_done;
2605 + int tx_chain_head;
2606 + int tx_chain_tail;
2607 + enum status tx_chain_status;
2608 + int tx_count;
2609 + int tx_full;
2610 +
2611 + struct timer_list mii_phy_timer;
2612 + unsigned long duplex_mode;
2613 +
2614 + int rx_irq;
2615 + int tx_irq;
2616 + int ovr_irq;
2617 + int und_irq;
2618 +
2619 + struct net_device_stats stats;
2620 + spinlock_t lock;
2621 +
2622 + /* debug /proc entry */
2623 + struct proc_dir_entry *ps;
2624 + int dma_halt_cnt; int dma_run_cnt;
2625 +};
2626 +
2627 +extern unsigned int idt_cpu_freq;
2628 +
2629 +/* Index to functions, as function prototypes. */
2630 +static int rc32434_open(struct net_device *dev);
2631 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2632 +static void rc32434_mii_handler(unsigned long data);
2633 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2634 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2635 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2636 +#ifdef RC32434_REVISION
2637 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2638 +#endif
2639 +static int rc32434_close(struct net_device *dev);
2640 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2641 +static void rc32434_multicast_list(struct net_device *dev);
2642 +static int rc32434_init(struct net_device *dev);
2643 +static void rc32434_tx_timeout(struct net_device *dev);
2644 +
2645 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2646 +#ifdef CONFIG_IDT_USE_NAPI
2647 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2648 +#else
2649 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2650 +#endif
2651 +static void rc32434_cleanup_module(void);
2652 +static int rc32434_probe(int port_num);
2653 +int rc32434_init_module(void);
2654 +
2655 +
2656 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2657 +{
2658 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2659 + rc32434_writel(0x10, &ch->dmac);
2660 +
2661 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2662 + dev->trans_start = jiffies;
2663 +
2664 + rc32434_writel(0, &ch->dmas);
2665 + }
2666 +
2667 + rc32434_writel(0, &ch->dmadptr);
2668 + rc32434_writel(0, &ch->dmandptr);
2669 +}
2670 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2671 --- linux-2.6.17/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
2672 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h 2006-06-18 12:44:28.000000000 +0200
2673 @@ -218,6 +218,17 @@
2674 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2675 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2676
2677 +
2678 +/*
2679 + * Valid machtype for group ARUBA
2680 + */
2681 +#define MACH_GROUP_ARUBA 23
2682 +#define MACH_ARUBA_UNKNOWN 0
2683 +#define MACH_ARUBA_AP60 1
2684 +#define MACH_ARUBA_AP65 2
2685 +#define MACH_ARUBA_AP70 3
2686 +#define MACH_ARUBA_AP40 4
2687 +
2688 #define CL_SIZE COMMAND_LINE_SIZE
2689
2690 const char *get_system_type(void);
2691 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2692 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2693 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h 2006-06-18 12:45:56.000000000 +0200
2694 @@ -54,6 +54,9 @@
2695 #define PRID_IMP_R14000 0x0f00
2696 #define PRID_IMP_R8000 0x1000
2697 #define PRID_IMP_PR4450 0x1200
2698 +#define PRID_IMP_RC32334 0x1800
2699 +#define PRID_IMP_RC32355 0x1900
2700 +#define PRID_IMP_RC32365 0x1900
2701 #define PRID_IMP_R4600 0x2000
2702 #define PRID_IMP_R4700 0x2100
2703 #define PRID_IMP_TX39 0x2200
2704 @@ -200,7 +203,8 @@
2705 #define CPU_SB1A 62
2706 #define CPU_74K 63
2707 #define CPU_R14000 64
2708 -#define CPU_LAST 64
2709 +#define CPU_RC32300 65
2710 +#define CPU_LAST 65
2711
2712 /*
2713 * ISA Level encodings
2714 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2715 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2716 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-06-18 12:44:28.000000000 +0200
2717 @@ -0,0 +1,142 @@
2718 +/**************************************************************************
2719 + *
2720 + * BRIEF MODULE DESCRIPTION
2721 + * RC32300 helper routines
2722 + *
2723 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2724 + *
2725 + * This program is free software; you can redistribute it and/or modify it
2726 + * under the terms of the GNU General Public License as published by the
2727 + * Free Software Foundation; either version 2 of the License, or (at your
2728 + * option) any later version.
2729 + *
2730 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2731 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2732 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2733 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2734 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2735 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2736 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2737 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2738 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2739 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2740 + *
2741 + * You should have received a copy of the GNU General Public License along
2742 + * with this program; if not, write to the Free Software Foundation, Inc.,
2743 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2744 + *
2745 + *
2746 + **************************************************************************
2747 + * May 2004 P. Sadik.
2748 + *
2749 + * Initial Release
2750 + *
2751 + *
2752 + *
2753 + **************************************************************************
2754 + */
2755 +
2756 +#ifndef __IDT_RC32300_H__
2757 +#define __IDT_RC32300_H__
2758 +
2759 +#include <linux/delay.h>
2760 +#include <asm/io.h>
2761 +
2762 +
2763 +/* cpu pipeline flush */
2764 +static inline void rc32300_sync(void)
2765 +{
2766 + __asm__ volatile ("sync");
2767 +}
2768 +
2769 +static inline void rc32300_sync_udelay(int us)
2770 +{
2771 + __asm__ volatile ("sync");
2772 + udelay(us);
2773 +}
2774 +
2775 +static inline void rc32300_sync_delay(int ms)
2776 +{
2777 + __asm__ volatile ("sync");
2778 + mdelay(ms);
2779 +}
2780 +
2781 +/*
2782 + * Macros to access internal RC32300 registers. No byte
2783 + * swapping should be done when accessing the internal
2784 + * registers.
2785 + */
2786 +
2787 +static inline u8 rc32300_readb(unsigned long pa)
2788 +{
2789 + return *((volatile u8 *)KSEG1ADDR(pa));
2790 +}
2791 +static inline u16 rc32300_readw(unsigned long pa)
2792 +{
2793 + return *((volatile u16 *)KSEG1ADDR(pa));
2794 +}
2795 +static inline u32 rc32300_readl(unsigned long pa)
2796 +{
2797 + return *((volatile u32 *)KSEG1ADDR(pa));
2798 +}
2799 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2800 +{
2801 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2802 +}
2803 +static inline void rc32300_writew(u16 val, unsigned long pa)
2804 +{
2805 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2806 +}
2807 +static inline void rc32300_writel(u32 val, unsigned long pa)
2808 +{
2809 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2810 +}
2811 +
2812 +
2813 +#define local_readb __raw_readb
2814 +#define local_readw __raw_readw
2815 +#define local_readl __raw_readl
2816 +
2817 +#define local_writeb __raw_writeb
2818 +#define local_writew __raw_writew
2819 +#define local_writel __raw_writel
2820 +
2821 +
2822 +/*
2823 + * C access to CLZ and CLO instructions
2824 + * (count leading zeroes/ones).
2825 + */
2826 +static inline int rc32300_clz(unsigned long val)
2827 +{
2828 + int ret;
2829 + __asm__ volatile (
2830 + ".set\tnoreorder\n\t"
2831 + ".set\tnoat\n\t"
2832 + ".set\tmips32\n\t"
2833 + "clz\t%0,%1\n\t"
2834 + ".set\tmips0\n\t"
2835 + ".set\tat\n\t"
2836 + ".set\treorder"
2837 + : "=r" (ret)
2838 + : "r" (val));
2839 +
2840 + return ret;
2841 +}
2842 +static inline int rc32300_clo(unsigned long val)
2843 +{
2844 + int ret;
2845 + __asm__ volatile (
2846 + ".set\tnoreorder\n\t"
2847 + ".set\tnoat\n\t"
2848 + ".set\tmips32\n\t"
2849 + "clo\t%0,%1\n\t"
2850 + ".set\tmips0\n\t"
2851 + ".set\tat\n\t"
2852 + ".set\treorder"
2853 + : "=r" (ret)
2854 + : "r" (val));
2855 +
2856 + return ret;
2857 +}
2858 +
2859 +#endif // __IDT_RC32300_H__
2860 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2861 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2862 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-06-18 12:44:28.000000000 +0200
2863 @@ -0,0 +1,207 @@
2864 +/**************************************************************************
2865 + *
2866 + * BRIEF MODULE DESCRIPTION
2867 + * Definitions for IDT RC32334 CPU.
2868 + *
2869 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2870 + *
2871 + * This program is free software; you can redistribute it and/or modify it
2872 + * under the terms of the GNU General Public License as published by the
2873 + * Free Software Foundation; either version 2 of the License, or (at your
2874 + * option) any later version.
2875 + *
2876 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2877 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2878 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2879 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2880 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2881 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2882 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2883 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2884 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2885 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2886 + *
2887 + * You should have received a copy of the GNU General Public License along
2888 + * with this program; if not, write to the Free Software Foundation, Inc.,
2889 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2890 + *
2891 + *
2892 + **************************************************************************
2893 + * May 2004 P. Sadik.
2894 + *
2895 + * Initial Release
2896 + *
2897 + *
2898 + *
2899 + **************************************************************************
2900 + */
2901 +
2902 +
2903 +#ifndef __IDT_RC32334_H__
2904 +#define __IDT_RC32334_H__
2905 +
2906 +#include <linux/delay.h>
2907 +#include <asm/io.h>
2908 +
2909 +/* Base address of internal registers */
2910 +#define RC32334_REG_BASE 0x18000000
2911 +
2912 +/* CPU and IP Bus Control */
2913 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2914 +#define CPU_BTA 0xffffe204 // virtual!
2915 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2916 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2917 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2918 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2919 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2920 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2921 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2922 +
2923 +/* Memory Controller */
2924 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2925 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2926 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2927 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2928 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2929 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2930 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2931 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2932 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2933 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2934 +
2935 +/* PCI Controller */
2936 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2937 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2938 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2939 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2940 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2941 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2942 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2943 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2944 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2945 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2946 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2947 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2948 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2949 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2950 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2951 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2952 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2953 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2954 +
2955 +/* Timers */
2956 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2957 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2958 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2959 +#define TIMER_REG_OFFSET 0x10
2960 +
2961 +/* Programmable I/O */
2962 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2963 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2964 +
2965 +/*
2966 + * DMA
2967 + *
2968 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2969 + *
2970 + * DMA0: 18001400
2971 + * DMA1: 18001440
2972 + * DMA2: 18001900
2973 + * DMA3: 18001940
2974 + * NB: dma number must be immediate value or variable.
2975 + * It MUST NOT be a function since it would get called twice!
2976 + */
2977 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2978 +
2979 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2980 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2981 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2982 +
2983 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2984 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2985 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2986 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2987 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2988 +
2989 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2990 +
2991 +/* Expansion Interrupt Controller */
2992 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2993 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2994 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2995 +#define IC_GROUP_OFFSET 0x10
2996 +
2997 +#define NUM_INTR_GROUPS 15
2998 +/*
2999 + * The IRQ mapping is as follows:
3000 + *
3001 + * IRQ Mapped To
3002 + * --- -------------------
3003 + * 0 SW0 (IP0) SW0 intr
3004 + * 1 SW1 (IP1) SW1 intr
3005 + * 2 Int0 (IP2) board-specific
3006 + * 3 Int1 (IP3) board-specific
3007 + * 4 Int2 (IP4) board-specific
3008 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
3009 + * 6 Int4 (IP6) board-specific
3010 + * 7 Int5 (IP7) CP0 Timer
3011 + *
3012 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3013 + * internally on the RC32334 is routed to the Expansion
3014 + * Interrupt Controller.
3015 + */
3016 +#define MIPS_CPU_TIMER_IRQ 7
3017 +
3018 +#define GROUP1_IRQ_BASE 8 // bus error
3019 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3020 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3021 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3022 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3023 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3024 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3025 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3026 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3027 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3028 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3029 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3030 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3031 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3032 +
3033 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3034 +
3035 +/* 16550 UARTs */
3036 +#ifdef __MIPSEB__
3037 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3038 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3039 +#else
3040 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3041 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3042 +#endif
3043 +
3044 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3045 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3046 +
3047 +#define IDT_CLOCK_MULT 2
3048 +
3049 +/* NVRAM */
3050 +#define NVRAM_BASE 0x12000000
3051 +#define NVRAM_ENVSIZE_OFF 4
3052 +#define NVRAM_ENVSTART_OFF 0x40
3053 +
3054 +/* LCD 4-digit display */
3055 +#define LCD_CLEAR 0x14000400
3056 +#define LCD_DIGIT0 0x1400000f
3057 +#define LCD_DIGIT1 0x14000008
3058 +#define LCD_DIGIT2 0x14000007
3059 +#define LCD_DIGIT3 0x14000003
3060 +
3061 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3062 +#define RC32334_SCC8530_IRQ 2
3063 +#define RC32334_PCI_INTA_IRQ 3
3064 +#define RC32334_PCI_INTB_IRQ 4
3065 +#define RC32334_PCI_INTC_IRQ 6
3066 +#define RC32334_PCI_INTD_IRQ 7
3067 +
3068 +#define RAM_SIZE (32*1024*1024)
3069 +
3070 +#endif // __IDT_RC32334_H__
3071 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3072 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3073 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3074 @@ -0,0 +1,206 @@
3075 +/**************************************************************************
3076 + *
3077 + * BRIEF MODULE DESCRIPTION
3078 + * DMA controller defines on IDT RC32355
3079 + *
3080 + * Copyright 2004 IDT Inc.
3081 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3082 + *
3083 + *
3084 + * This program is free software; you can redistribute it and/or modify it
3085 + * under the terms of the GNU General Public License as published by the
3086 + * Free Software Foundation; either version 2 of the License, or (at your
3087 + * option) any later version.
3088 + *
3089 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3090 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3091 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3092 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3093 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3094 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3095 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3096 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3097 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3098 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3099 + *
3100 + * You should have received a copy of the GNU General Public License along
3101 + * with this program; if not, write to the Free Software Foundation, Inc.,
3102 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3103 + *
3104 + *
3105 + * May 2004 rkt
3106 + * Initial Release
3107 + *
3108 + **************************************************************************
3109 + */
3110 +
3111 +#ifndef BANYAN_DMA_H
3112 +#define BANYAN_DMA_H
3113 +#include <asm/idt-boards/rc32300/rc32300.h>
3114 +
3115 +/*
3116 + * An image of one RC32355 dma channel registers
3117 + */
3118 +typedef struct {
3119 + u32 dmac;
3120 + u32 dmas;
3121 + u32 dmasm;
3122 + u32 dmadptr;
3123 + u32 dmandptr;
3124 +} rc32355_dma_ch_t;
3125 +
3126 +/*
3127 + * An image of all RC32355 dma channel registers
3128 + */
3129 +typedef struct {
3130 + rc32355_dma_ch_t ch[16];
3131 +} rc32355_dma_regs_t;
3132 +
3133 +
3134 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3135 +
3136 +
3137 +/* DMAC register layout */
3138 +
3139 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3140 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3141 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3142 +
3143 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3144 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3145 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3146 +
3147 +/* DMAS and DMASM register layout */
3148 +
3149 +#define DMAS_F 0x01 /* Finished */
3150 +#define DMAS_D 0x02 /* Done */
3151 +#define DMAS_C 0x04 /* Chain */
3152 +#define DMAS_E 0x08 /* Error */
3153 +#define DMAS_H 0x10 /* Halt */
3154 +
3155 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3156 +#define DMA_HALT_TIMEOUT 500
3157 +
3158 +
3159 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3160 +{
3161 + int timeout=1;
3162 +
3163 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3164 + local_writel(0, &ch->dmac);
3165 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3166 + if (local_readl(&ch->dmas) & DMAS_H) {
3167 + local_writel(0, &ch->dmas);
3168 + break;
3169 + }
3170 + }
3171 + }
3172 +
3173 + return timeout ? 0 : 1;
3174 +}
3175 +
3176 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3177 +{
3178 + local_writel(0, &ch->dmandptr);
3179 + local_writel(dma_addr, &ch->dmadptr);
3180 +}
3181 +
3182 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3183 +{
3184 + local_writel(dma_addr, &ch->dmandptr);
3185 +}
3186 +
3187 +
3188 +/* The following can be used to describe DMA channels 0 to 15, and the */
3189 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3190 +
3191 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3192 +
3193 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3194 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3195 +
3196 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3197 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3198 +
3199 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3200 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3201 +
3202 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3203 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3204 +
3205 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3206 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3207 +#define DMA_DEV_ATMVCC(entry) 0
3208 +
3209 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3210 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3211 +
3212 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3213 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3214 +
3215 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3216 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3217 +
3218 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3219 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3220 +
3221 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3222 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3223 +
3224 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3225 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3226 +
3227 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3228 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3229 +
3230 +#define DMA_CHAN_USBIN 13 /* USB input */
3231 +#define DMA_DEV_USBIN 0 /* USB input */
3232 +
3233 +#define DMA_CHAN_USBOUT 14 /* USB output */
3234 +#define DMA_DEV_USBOUT 0 /* USB output */
3235 +
3236 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3237 +#define DMA_DEV_EXTERN 0 /* External DMA */
3238 +
3239 +/*
3240 + * An RC32355 dma descriptor in system memory
3241 + */
3242 +typedef struct {
3243 + u32 cmdstat; /* control and status */
3244 + u32 curr_addr; /* current address of data */
3245 + u32 devcs; /* peripheral-specific control and status */
3246 + u32 link; /* link to next descriptor */
3247 +} rc32355_dma_desc_t;
3248 +
3249 +/* Values for the descriptor cmdstat word */
3250 +
3251 +#define DMADESC_F 0x80000000u /* Finished bit */
3252 +#define DMADESC_D 0x40000000u /* Done bit */
3253 +#define DMADESC_T 0x20000000u /* Terminated bit */
3254 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3255 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3256 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3257 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3258 +
3259 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3260 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3261 +
3262 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3263 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3264 +
3265 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3266 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3267 +
3268 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3269 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3270 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3271 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3272 +
3273 +#define DMA_DEVCMD(devcmd) \
3274 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3275 +#define DMA_DS(ds) \
3276 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3277 +#define DMA_COUNT(count) \
3278 + ((count) & DMADESC_COUNT_MASK)
3279 +
3280 +#endif /* RC32355_DMA_H */
3281 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3282 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3283 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3284 @@ -0,0 +1,442 @@
3285 +/**************************************************************************
3286 + *
3287 + * BRIEF MODULE DESCRIPTION
3288 + * Ethernet registers on IDT RC32355
3289 + *
3290 + * Copyright 2004 IDT Inc.
3291 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3292 + *
3293 + *
3294 + * This program is free software; you can redistribute it and/or modify it
3295 + * under the terms of the GNU General Public License as published by the
3296 + * Free Software Foundation; either version 2 of the License, or (at your
3297 + * option) any later version.
3298 + *
3299 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3300 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3301 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3302 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3303 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3304 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3305 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3306 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3307 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3308 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3309 + *
3310 + * You should have received a copy of the GNU General Public License along
3311 + * with this program; if not, write to the Free Software Foundation, Inc.,
3312 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3313 + *
3314 + *
3315 + * May 2004 rkt
3316 + * Initial Release
3317 + *
3318 + **************************************************************************
3319 + */
3320 +
3321 +
3322 +#ifndef RC32355_ETHER_H
3323 +#define RC32355_ETHER_H
3324 +
3325 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3326 +
3327 +/*
3328 + * A partial image of the RC32355 ethernet registers
3329 + */
3330 +typedef struct {
3331 + u32 ethintfc;
3332 + u32 ethfifott;
3333 + u32 etharc;
3334 + u32 ethhash0;
3335 + u32 ethhash1;
3336 + u32 ethfifost;
3337 + u32 ethfifos;
3338 + u32 ethodeops;
3339 + u32 ethis;
3340 + u32 ethos;
3341 + u32 ethmcp;
3342 + u32 _u1;
3343 + u32 ethid;
3344 + u32 _u2;
3345 + u32 _u3;
3346 + u32 _u4;
3347 + u32 ethod;
3348 + u32 _u5;
3349 + u32 _u6;
3350 + u32 _u7;
3351 + u32 ethodeop;
3352 + u32 _u8[43];
3353 + u32 ethsal0;
3354 + u32 ethsah0;
3355 + u32 ethsal1;
3356 + u32 ethsah1;
3357 + u32 ethsal2;
3358 + u32 ethsah2;
3359 + u32 ethsal3;
3360 + u32 ethsah3;
3361 + u32 ethrbc;
3362 + u32 ethrpc;
3363 + u32 ethrupc;
3364 + u32 ethrfc;
3365 + u32 ethtbc;
3366 + u32 ethgpf;
3367 + u32 _u9[50];
3368 + u32 ethmac1;
3369 + u32 ethmac2;
3370 + u32 ethipgt;
3371 + u32 ethipgr;
3372 + u32 ethclrt;
3373 + u32 ethmaxf;
3374 + u32 _u10;
3375 + u32 ethmtest;
3376 + u32 miimcfg;
3377 + u32 miimcmd;
3378 + u32 miimaddr;
3379 + u32 miimwtd;
3380 + u32 miimrdd;
3381 + u32 miimind;
3382 + u32 _u11;
3383 + u32 _u12;
3384 + u32 ethcfsa0;
3385 + u32 ethcfsa1;
3386 + u32 ethcfsa2;
3387 +} rc32355_eth_regs_t;
3388 +
3389 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3390 +
3391 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3392 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3393 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3394 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3395 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3396 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3397 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3398 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3399 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3400 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3401 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3402 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3403 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3404 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3405 +
3406 +/* for n in { 0, 1, 2, 3 } */
3407 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3408 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3409 +
3410 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3411 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3412 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3413 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3414 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3415 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3416 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3417 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3418 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3419 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3420 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3421 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3422 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3423 +
3424 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3425 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3426 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3427 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3428 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3429 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3430 +
3431 +/* for n in { 0, 1, 2 } */
3432 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3433 +
3434 +
3435 +/*
3436 + * Register Interpretations follow
3437 + */
3438 +
3439 +/******************************************************************************
3440 + * ETHINTFC register
3441 + *****************************************************************************/
3442 +
3443 +#define ETHERINTFC_EN (1<<0)
3444 +#define ETHERINTFC_ITS (1<<1)
3445 +#define ETHERINTFC_RES (1<<2)
3446 +#define ETHERINTFC_RIP (1<<2)
3447 +#define ETHERINTFC_JAM (1<<3)
3448 +
3449 +/******************************************************************************
3450 + * ETHFIFOTT register
3451 + *****************************************************************************/
3452 +
3453 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3454 +
3455 +/******************************************************************************
3456 + * ETHARC register
3457 + *****************************************************************************/
3458 +
3459 +#define ETHERARC_PRO (1<<0)
3460 +#define ETHERARC_AM (1<<1)
3461 +#define ETHERARC_AFM (1<<2)
3462 +#define ETHERARC_AB (1<<3)
3463 +
3464 +/******************************************************************************
3465 + * ETHHASH registers
3466 + *****************************************************************************/
3467 +
3468 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3469 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3470 +
3471 +/******************************************************************************
3472 + * ETHSA registers
3473 + *****************************************************************************/
3474 +
3475 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3476 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3477 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3478 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3479 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3480 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3481 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3482 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3483 +
3484 +/******************************************************************************
3485 + * ETHFIFOST register
3486 + *****************************************************************************/
3487 +
3488 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3489 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3490 +
3491 +/******************************************************************************
3492 + * ETHFIFOS register
3493 + *****************************************************************************/
3494 +
3495 +#define ETHERFIFOS_IR (1<<0)
3496 +#define ETHERFIFOS_OR (1<<1)
3497 +#define ETHERFIFOS_OVR (1<<2)
3498 +#define ETHERFIFOS_UND (1<<3)
3499 +
3500 +/******************************************************************************
3501 + * DATA registers
3502 + *****************************************************************************/
3503 +
3504 +#define ETHERID(v) (((v)&0xffff)<<0)
3505 +#define ETHEROD(v) (((v)&0xffff)<<0)
3506 +
3507 +/******************************************************************************
3508 + * ETHODEOPS register
3509 + *****************************************************************************/
3510 +
3511 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3512 +
3513 +/******************************************************************************
3514 + * ETHODEOP register
3515 + *****************************************************************************/
3516 +
3517 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3518 +
3519 +/******************************************************************************
3520 + * ETHIS register
3521 + *****************************************************************************/
3522 +
3523 +#define ETHERIS_EOP (1<<0)
3524 +#define ETHERIS_ROK (1<<2)
3525 +#define ETHERIS_FM (1<<3)
3526 +#define ETHERIS_MP (1<<4)
3527 +#define ETHERIS_BP (1<<5)
3528 +#define ETHERIS_VLT (1<<6)
3529 +#define ETHERIS_CF (1<<7)
3530 +#define ETHERIS_OVR (1<<8)
3531 +#define ETHERIS_CRC (1<<9)
3532 +#define ETHERIS_CV (1<<10)
3533 +#define ETHERIS_DB (1<<11)
3534 +#define ETHERIS_LE (1<<12)
3535 +#define ETHERIS_LOR (1<<13)
3536 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3537 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3538 +
3539 +/******************************************************************************
3540 + * ETHOS register
3541 + *****************************************************************************/
3542 +
3543 +#define ETHEROS_T (1<<0)
3544 +#define ETHEROS_TOK (1<<6)
3545 +#define ETHEROS_MP (1<<7)
3546 +#define ETHEROS_BP (1<<8)
3547 +#define ETHEROS_UND (1<<9)
3548 +#define ETHEROS_OF (1<<10)
3549 +#define ETHEROS_ED (1<<11)
3550 +#define ETHEROS_EC (1<<12)
3551 +#define ETHEROS_LC (1<<13)
3552 +#define ETHEROS_TD (1<<14)
3553 +#define ETHEROS_CRC (1<<15)
3554 +#define ETHEROS_LE (1<<16)
3555 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3556 +#define ETHEROS_PFD (1<<21)
3557 +
3558 +/******************************************************************************
3559 + * Statistics registers
3560 + *****************************************************************************/
3561 +
3562 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3563 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3564 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3565 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3566 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3567 +
3568 +/******************************************************************************
3569 + * ETHGPF register
3570 + *****************************************************************************/
3571 +
3572 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3573 +
3574 +/******************************************************************************
3575 + * MAC registers
3576 + *****************************************************************************/
3577 +//ETHMAC1
3578 +#define ETHERMAC1_RE (1<<0)
3579 +#define ETHERMAC1_PAF (1<<1)
3580 +#define ETHERMAC1_RFC (1<<2)
3581 +#define ETHERMAC1_TFC (1<<3)
3582 +#define ETHERMAC1_LB (1<<4)
3583 +#define ETHERMAC1_MR (1<<15)
3584 +
3585 +//ETHMAC2
3586 +#define ETHERMAC2_FD (1<<0)
3587 +#define ETHERMAC2_FLC (1<<1)
3588 +#define ETHERMAC2_HFE (1<<2)
3589 +#define ETHERMAC2_DC (1<<3)
3590 +#define ETHERMAC2_CEN (1<<4)
3591 +#define ETHERMAC2_PE (1<<5)
3592 +#define ETHERMAC2_VPE (1<<6)
3593 +#define ETHERMAC2_APE (1<<7)
3594 +#define ETHERMAC2_PPE (1<<8)
3595 +#define ETHERMAC2_LPE (1<<9)
3596 +#define ETHERMAC2_NB (1<<12)
3597 +#define ETHERMAC2_BP (1<<13)
3598 +#define ETHERMAC2_ED (1<<14)
3599 +
3600 +//ETHIPGT
3601 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3602 +
3603 +//ETHIPGR
3604 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3605 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3606 +
3607 +//ETHCLRT
3608 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3609 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3610 +
3611 +//ETHMAXF
3612 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3613 +
3614 +//ETHMTEST
3615 +#define ETHERMTEST_TB (1<<2)
3616 +
3617 +//ETHMCP
3618 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3619 +
3620 +//MIIMCFG
3621 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3622 +#define ETHERMIIMCFG_R (1<<15)
3623 +
3624 +//MIIMCMD
3625 +#define ETHERMIIMCMD_RD (1<<0)
3626 +#define ETHERMIIMCMD_SCN (1<<1)
3627 +
3628 +//MIIMADDR
3629 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3630 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3631 +
3632 +//MIIMWTD
3633 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3634 +
3635 +//MIIMRDD
3636 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3637 +
3638 +//MIIMIND
3639 +#define ETHERMIIMIND_BSY (1<<0)
3640 +#define ETHERMIIMIND_SCN (1<<1)
3641 +#define ETHERMIIMIND_NV (1<<2)
3642 +
3643 +//DMA DEVCS IN
3644 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3645 +#define ETHERDMA_IN_CES (1<<14)
3646 +#define ETHERDMA_IN_LOR (1<<13)
3647 +#define ETHERDMA_IN_LE (1<<12)
3648 +#define ETHERDMA_IN_DB (1<<11)
3649 +#define ETHERDMA_IN_CV (1<<10)
3650 +#define ETHERDMA_IN_CRC (1<<9)
3651 +#define ETHERDMA_IN_OVR (1<<8)
3652 +#define ETHE