target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcm4710.h

   1 /*
   2  * BCM4710 address space map and definitions
   3  * Think twice before adding to this file, this is not the kitchen sink
   4  * These definitions are not guaranteed for all 47xx chips, only the 4710
   5  *
   6  * Copyright 2004, Broadcom Corporation
   7  * All Rights Reserved.
   8  *
   9  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
  10  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  11  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  12  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  13  *
  14  */
  15
  16 #ifndef _bcm4710_h_
  17 #define _bcm4710_h_
  18
  19 /* Address map */
  20 #define BCM4710_SDRAM           0x00000000      /* Physical SDRAM */
  21 #define BCM4710_PCI_MEM         0x08000000      /* Host Mode PCI memory access space (64 MB) */
  22 #define BCM4710_PCI_CFG         0x0c000000      /* Host Mode PCI configuration space (64 MB) */
  23 #define BCM4710_PCI_DMA         0x40000000      /* Client Mode PCI memory access space (1 GB) */
  24 #define BCM4710_SDRAM_SWAPPED   0x10000000      /* Byteswapped Physical SDRAM */
  25 #define BCM4710_ENUM            0x18000000      /* Beginning of core enumeration space */
  26
  27 /* Core register space */
  28 #define BCM4710_REG_SDRAM       0x18000000      /* SDRAM core registers */
  29 #define BCM4710_REG_ILINE20     0x18001000      /* InsideLine20 core registers */
  30 #define BCM4710_REG_EMAC0       0x18002000      /* Ethernet MAC 0 core registers */
  31 #define BCM4710_REG_CODEC       0x18003000      /* Codec core registers */
  32 #define BCM4710_REG_USB         0x18004000      /* USB core registers */
  33 #define BCM4710_REG_PCI         0x18005000      /* PCI core registers */
  34 #define BCM4710_REG_MIPS        0x18006000      /* MIPS core registers */
  35 #define BCM4710_REG_EXTIF       0x18007000      /* External Interface core registers */
  36 #define BCM4710_REG_EMAC1       0x18008000      /* Ethernet MAC 1 core registers */
  37
  38 #define BCM4710_EXTIF           0x1f000000      /* External Interface base address */
  39 #define BCM4710_PCMCIA_MEM      0x1f000000      /* External Interface PCMCIA memory access */
  40 #define BCM4710_PCMCIA_IO       0x1f100000      /* PCMCIA I/O access */
  41 #define BCM4710_PCMCIA_CONF     0x1f200000      /* PCMCIA configuration */
  42 #define BCM4710_PROG            0x1f800000      /* Programable interface */
  43 #define BCM4710_FLASH           0x1fc00000      /* Flash */
  44
  45 #define BCM4710_EJTAG           0xff200000      /* MIPS EJTAG space (2M) */
  46
  47 #define BCM4710_UART            (BCM4710_REG_EXTIF + 0x00000300)
  48
  49 #define BCM4710_EUART           (BCM4710_EXTIF + 0x00800000)
  50 #define BCM4710_LED             (BCM4710_EXTIF + 0x00900000)
  51
  52 #define SBFLAG_PCI      0
  53 #define SBFLAG_ENET0    1
  54 #define SBFLAG_ILINE20  2
  55 #define SBFLAG_CODEC    3
  56 #define SBFLAG_USB      4
  57 #define SBFLAG_EXTIF    5
  58 #define SBFLAG_ENET1    6
  59
  60 #ifdef  CONFIG_HWSIM
  61 #define BCM4710_TRACE(trval)        do { *((int *)0xa0000f18) = (trval); } while (0)
  62 #else
  63 #define BCM4710_TRACE(trval)
  64 #endif
  65
  66
  67 /* BCM94702 CPCI -ExtIF used for LocalBus devs */
  68
  69 #define BCM94702_CPCI_RESET_ADDR         BCM4710_EXTIF
  70 #define BCM94702_CPCI_BOARDID_ADDR      (BCM4710_EXTIF | 0x4000)
  71 #define BCM94702_CPCI_DOC_ADDR          (BCM4710_EXTIF | 0x6000)
  72 #define BCM94702_DOC_ADDR                BCM94702_CPCI_DOC_ADDR
  73 #define BCM94702_CPCI_LED_ADDR          (BCM4710_EXTIF | 0xc000)
  74 #define BCM94702_CPCI_NVRAM_ADDR        (BCM4710_EXTIF | 0xe000)
  75 #define BCM94702_CPCI_NVRAM_SIZE         0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
  76 #define BCM94702_CPCI_TOD_REG_BASE       (BCM94702_CPCI_NVRAM_ADDR | 0x1ff0)
  77
  78 #define LED_REG(x)      \
  79  (*(volatile unsigned char *) (KSEG1ADDR(BCM94702_CPCI_LED_ADDR) + (x)))
  80
  81 /*
  82  * Reset function implemented in PLD.  Read or write should trigger hard reset
  83  */
  84 #define SYS_HARD_RESET()   \
  85     { for (;;) \
  86      *( (volatile unsigned char *)\
  87       KSEG1ADDR(BCM94702_CPCI_RESET_ADDR) ) = 0x80; \
  88     }
  89
  90 #endif /* _bcm4710_h_ */