finally move buildroot-ng to trunk
[openwrt/staging/dedeckeh.git] / target / linux / brcm-2.6 / patches / 001-bcm947xx.patch
1 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/bcmsrom.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/bcmsrom.c
2 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/bcmsrom.c 2006-06-18 15:29:23.000000000 +0200
4 @@ -0,0 +1,481 @@
5 +/*
6 + * Misc useful routines to access NIC SROM/OTP .
7 + *
8 + * Copyright 2005, Broadcom Corporation
9 + * All Rights Reserved.
10 + *
11 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15 + * $Id$
16 + */
17 +
18 +#include <typedefs.h>
19 +#include <osl.h>
20 +#include <bcmutils.h>
21 +#include <bcmsrom.h>
22 +#include <bcmdevs.h>
23 +#include <bcmendian.h>
24 +#include <pcicfg.h>
25 +#include <sbutils.h>
26 +
27 +#include <proto/ethernet.h> /* for sprom content groking */
28 +
29 +#define VARS_MAX 4096 /* should be reduced */
30 +
31 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
32 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
33 +
34 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
35 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
36 +
37 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
38 +
39 +/*
40 + * Initialize local vars from the right source for this platform.
41 + * Return 0 on success, nonzero on error.
42 + */
43 +int
44 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
45 +{
46 + ASSERT(bustype == BUSTYPE(bustype));
47 + if (vars == NULL || count == NULL)
48 + return (0);
49 +
50 + switch (BUSTYPE(bustype)) {
51 +
52 + case PCI_BUS:
53 + ASSERT(curmap); /* can not be NULL */
54 + return initvars_srom_pci(sbh, curmap, vars, count);
55 +
56 + default:
57 + return 0;
58 + }
59 + return (-1);
60 +}
61 +
62 +/* support only 16-bit word read from srom */
63 +int
64 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
65 +{
66 + void *srom;
67 + uint off, nw;
68 +
69 + ASSERT(bustype == BUSTYPE(bustype));
70 +
71 + /* check input - 16-bit access only */
72 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
73 + return 1;
74 +
75 + off = byteoff / 2;
76 + nw = nbytes / 2;
77 +
78 + if (BUSTYPE(bustype) == PCI_BUS) {
79 + if (!curmap)
80 + return 1;
81 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
82 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
83 + return 1;
84 + } else {
85 + return 1;
86 + }
87 +
88 + return 0;
89 +}
90 +
91 +/* support only 16-bit word write into srom */
92 +int
93 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
94 +{
95 + uint16 *srom;
96 + uint i, off, nw, crc_range;
97 + uint16 image[SPROM_SIZE], *p;
98 + uint8 crc;
99 + volatile uint32 val32;
100 +
101 + ASSERT(bustype == BUSTYPE(bustype));
102 +
103 + /* check input - 16-bit access only */
104 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
105 + return 1;
106 +
107 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
108 +
109 + /* if changes made inside crc cover range */
110 + if (byteoff < crc_range) {
111 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
112 + /* read data including entire first 64 words from srom */
113 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
114 + return 1;
115 + /* make changes */
116 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
117 + /* calculate crc */
118 + htol16_buf(image, crc_range);
119 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
120 + ltoh16_buf(image, crc_range);
121 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
122 + p = image;
123 + off = 0;
124 + } else {
125 + p = buf;
126 + off = byteoff / 2;
127 + nw = nbytes / 2;
128 + }
129 +
130 + if (BUSTYPE(bustype) == PCI_BUS) {
131 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
132 + /* enable writes to the SPROM */
133 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
134 + val32 |= SPROM_WRITEEN;
135 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
136 + bcm_mdelay(WRITE_ENABLE_DELAY);
137 + /* write srom */
138 + for (i = 0; i < nw; i++) {
139 + W_REG(&srom[off + i], p[i]);
140 + bcm_mdelay(WRITE_WORD_DELAY);
141 + }
142 + /* disable writes to the SPROM */
143 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
144 + } else {
145 + return 1;
146 + }
147 +
148 + bcm_mdelay(WRITE_ENABLE_DELAY);
149 + return 0;
150 +}
151 +
152 +
153 +/*
154 + * Read in and validate sprom.
155 + * Return 0 on success, nonzero on error.
156 + */
157 +static int
158 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
159 +{
160 + int err = 0;
161 + uint i;
162 +
163 + /* read the sprom */
164 + for (i = 0; i < nwords; i++)
165 + buf[i] = R_REG(&sprom[wordoff + i]);
166 +
167 + if (check_crc) {
168 + /* fixup the endianness so crc8 will pass */
169 + htol16_buf(buf, nwords * 2);
170 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
171 + err = 1;
172 + /* now correct the endianness of the byte array */
173 + ltoh16_buf(buf, nwords * 2);
174 + }
175 +
176 + return err;
177 +}
178 +
179 +/*
180 +* Create variable table from memory.
181 +* Return 0 on success, nonzero on error.
182 +*/
183 +static int
184 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
185 +{
186 + int c = (int)(end - start);
187 +
188 + /* do it only when there is more than just the null string */
189 + if (c > 1) {
190 + char *vp = MALLOC(osh, c);
191 + ASSERT(vp);
192 + if (!vp)
193 + return BCME_NOMEM;
194 + bcopy(start, vp, c);
195 + *vars = vp;
196 + *count = c;
197 + }
198 + else {
199 + *vars = NULL;
200 + *count = 0;
201 + }
202 +
203 + return 0;
204 +}
205 +
206 +/*
207 + * Initialize nonvolatile variable table from sprom.
208 + * Return 0 on success, nonzero on error.
209 + */
210 +static int
211 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
212 +{
213 + uint16 w, b[64];
214 + uint8 sromrev;
215 + struct ether_addr ea;
216 + char eabuf[32];
217 + uint32 w32;
218 + int woff, i;
219 + char *vp, *base;
220 + osl_t *osh = sb_osh(sbh);
221 + int err;
222 +
223 + /*
224 + * Apply CRC over SROM content regardless SROM is present or not,
225 + * and use variable <devpath>sromrev's existance in flash to decide
226 + * if we should return an error when CRC fails or read SROM variables
227 + * from flash.
228 + */
229 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
230 +
231 + /* top word of sprom contains version and crc8 */
232 + sromrev = b[63] & 0xff;
233 + /* bcm4401 sroms misprogrammed */
234 + if (sromrev == 0x10)
235 + sromrev = 1;
236 +
237 + /* srom version check */
238 + if (sromrev > 3)
239 + return (-2);
240 +
241 + ASSERT(vars);
242 + ASSERT(count);
243 +
244 + base = vp = MALLOC(osh, VARS_MAX);
245 + ASSERT(vp);
246 + if (!vp)
247 + return -2;
248 +
249 + vp += sprintf(vp, "sromrev=%d", sromrev);
250 + vp++;
251 +
252 + if (sromrev >= 3) {
253 + /* New section takes over the 3th hardware function space */
254 +
255 + /* Words 22+23 are 11a (mid) ofdm power offsets */
256 + w32 = ((uint32)b[23] << 16) | b[22];
257 + vp += sprintf(vp, "ofdmapo=%d", w32);
258 + vp++;
259 +
260 + /* Words 24+25 are 11a (low) ofdm power offsets */
261 + w32 = ((uint32)b[25] << 16) | b[24];
262 + vp += sprintf(vp, "ofdmalpo=%d", w32);
263 + vp++;
264 +
265 + /* Words 26+27 are 11a (high) ofdm power offsets */
266 + w32 = ((uint32)b[27] << 16) | b[26];
267 + vp += sprintf(vp, "ofdmahpo=%d", w32);
268 + vp++;
269 +
270 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
271 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
272 + vp += sprintf(vp, "gpiotimerval=%d", w32);
273 +
274 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
275 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
276 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
277 + vp += sprintf(vp, "gpiotimerval=%d", w32);
278 +
279 + vp++;
280 + }
281 +
282 + if (sromrev >= 2) {
283 + /* New section takes over the 4th hardware function space */
284 +
285 + /* Word 29 is max power 11a high/low */
286 + w = b[29];
287 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
288 + vp++;
289 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
290 + vp++;
291 +
292 + /* Words 30-32 set the 11alow pa settings,
293 + * 33-35 are the 11ahigh ones.
294 + */
295 + for (i = 0; i < 3; i++) {
296 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
297 + vp++;
298 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
299 + vp++;
300 + }
301 + w = b[59];
302 + if (w == 0)
303 + vp += sprintf(vp, "ccode=");
304 + else
305 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
306 + vp++;
307 +
308 + }
309 +
310 + /* parameter section of sprom starts at byte offset 72 */
311 + woff = 72/2;
312 +
313 + /* first 6 bytes are il0macaddr */
314 + ea.octet[0] = (b[woff] >> 8) & 0xff;
315 + ea.octet[1] = b[woff] & 0xff;
316 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
317 + ea.octet[3] = b[woff+1] & 0xff;
318 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
319 + ea.octet[5] = b[woff+2] & 0xff;
320 + woff += ETHER_ADDR_LEN/2 ;
321 + bcm_ether_ntoa((uchar*)&ea, eabuf);
322 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
323 + vp++;
324 +
325 + /* next 6 bytes are et0macaddr */
326 + ea.octet[0] = (b[woff] >> 8) & 0xff;
327 + ea.octet[1] = b[woff] & 0xff;
328 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
329 + ea.octet[3] = b[woff+1] & 0xff;
330 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
331 + ea.octet[5] = b[woff+2] & 0xff;
332 + woff += ETHER_ADDR_LEN/2 ;
333 + bcm_ether_ntoa((uchar*)&ea, eabuf);
334 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
335 + vp++;
336 +
337 + /* next 6 bytes are et1macaddr */
338 + ea.octet[0] = (b[woff] >> 8) & 0xff;
339 + ea.octet[1] = b[woff] & 0xff;
340 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
341 + ea.octet[3] = b[woff+1] & 0xff;
342 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
343 + ea.octet[5] = b[woff+2] & 0xff;
344 + woff += ETHER_ADDR_LEN/2 ;
345 + bcm_ether_ntoa((uchar*)&ea, eabuf);
346 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
347 + vp++;
348 +
349 + /*
350 + * Enet phy settings one or two singles or a dual
351 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
352 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
353 + * Bit 14 : Mdio for enet0
354 + * Bit 15 : Mdio for enet1
355 + */
356 + w = b[woff];
357 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
358 + vp++;
359 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
360 + vp++;
361 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
362 + vp++;
363 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
364 + vp++;
365 +
366 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
367 + w = b[46];
368 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
369 + vp++;
370 +
371 + if (sromrev > 1)
372 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
373 + else
374 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
375 + vp++;
376 +
377 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
378 + vp++;
379 +
380 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
381 + vp++;
382 +
383 + /* Words 47-49 set the (wl) pa settings */
384 + woff = 47;
385 +
386 + for (i = 0; i < 3; i++) {
387 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
388 + vp++;
389 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
390 + vp++;
391 + }
392 +
393 + /*
394 + * Words 50-51 set the customer-configured wl led behavior.
395 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
396 + * LED behavior values defined in wlioctl.h .
397 + */
398 + w = b[50];
399 + if ((w != 0) && (w != 0xffff)) {
400 + /* gpio0 */
401 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
402 + vp++;
403 +
404 + /* gpio1 */
405 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
406 + vp++;
407 + }
408 + w = b[51];
409 + if ((w != 0) && (w != 0xffff)) {
410 + /* gpio2 */
411 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
412 + vp++;
413 +
414 + /* gpio3 */
415 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
416 + vp++;
417 + }
418 +
419 + /* Word 52 is max power 0/1 */
420 + w = b[52];
421 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
422 + vp++;
423 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
424 + vp++;
425 +
426 + /* Word 56 is idle tssi target 0/1 */
427 + w = b[56];
428 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
429 + vp++;
430 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
431 + vp++;
432 +
433 + /* Word 57 is boardflags, if not programmed make it zero */
434 + w32 = (uint32)b[57];
435 + if (w32 == 0xffff) w32 = 0;
436 + if (sromrev > 1) {
437 + /* Word 28 is the high bits of boardflags */
438 + w32 |= (uint32)b[28] << 16;
439 + }
440 + vp += sprintf(vp, "boardflags=%d", w32);
441 + vp++;
442 +
443 + /* Word 58 is antenna gain 0/1 */
444 + w = b[58];
445 + vp += sprintf(vp, "ag0=%d", w & 0xff);
446 + vp++;
447 +
448 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
449 + vp++;
450 +
451 + if (sromrev == 1) {
452 + /* set the oem string */
453 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
454 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
455 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
456 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
457 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
458 + vp++;
459 + } else if (sromrev == 2) {
460 + /* Word 60 OFDM tx power offset from CCK level */
461 + /* OFDM Power Offset - opo */
462 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
463 + vp++;
464 + } else {
465 + /* Word 60: cck power offsets */
466 + vp += sprintf(vp, "cckpo=%d", b[60]);
467 + vp++;
468 +
469 + /* Words 61+62: 11g ofdm power offsets */
470 + w32 = ((uint32)b[62] << 16) | b[61];
471 + vp += sprintf(vp, "ofdmgpo=%d", w32);
472 + vp++;
473 + }
474 +
475 + /* final nullbyte terminator */
476 + *vp++ = '\0';
477 +
478 + ASSERT((vp - base) <= VARS_MAX);
479 +
480 + err = initvars_table(osh, base, vp, vars, count);
481 +
482 + MFREE(osh, base, VARS_MAX);
483 + return err;
484 +}
485 +
486 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/bcmutils.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/bcmutils.c
487 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
488 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/bcmutils.c 2006-06-18 15:29:23.000000000 +0200
489 @@ -0,0 +1,356 @@
490 +/*
491 + * Misc useful OS-independent routines.
492 + *
493 + * Copyright 2005, Broadcom Corporation
494 + * All Rights Reserved.
495 + *
496 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
497 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
498 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
499 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
500 + * $Id$
501 + */
502 +
503 +#include <typedefs.h>
504 +#include <osl.h>
505 +#include <sbutils.h>
506 +#include <bcmnvram.h>
507 +#include <bcmutils.h>
508 +#include <bcmendian.h>
509 +#include <bcmdevs.h>
510 +
511 +unsigned char bcm_ctype[] = {
512 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
513 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
514 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
515 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
516 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
517 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
518 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
519 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
520 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
521 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
522 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
523 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
524 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
525 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
526 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
527 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
528 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
529 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
530 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
531 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
532 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
533 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
534 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
535 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
536 +};
537 +
538 +uchar
539 +bcm_toupper(uchar c)
540 +{
541 + if (bcm_islower(c))
542 + c -= 'a'-'A';
543 + return (c);
544 +}
545 +
546 +ulong
547 +bcm_strtoul(char *cp, char **endp, uint base)
548 +{
549 + ulong result, value;
550 + bool minus;
551 +
552 + minus = FALSE;
553 +
554 + while (bcm_isspace(*cp))
555 + cp++;
556 +
557 + if (cp[0] == '+')
558 + cp++;
559 + else if (cp[0] == '-') {
560 + minus = TRUE;
561 + cp++;
562 + }
563 +
564 + if (base == 0) {
565 + if (cp[0] == '0') {
566 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
567 + base = 16;
568 + cp = &cp[2];
569 + } else {
570 + base = 8;
571 + cp = &cp[1];
572 + }
573 + } else
574 + base = 10;
575 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
576 + cp = &cp[2];
577 + }
578 +
579 + result = 0;
580 +
581 + while (bcm_isxdigit(*cp) &&
582 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
583 + result = result*base + value;
584 + cp++;
585 + }
586 +
587 + if (minus)
588 + result = (ulong)(result * -1);
589 +
590 + if (endp)
591 + *endp = (char *)cp;
592 +
593 + return (result);
594 +}
595 +
596 +uint
597 +bcm_atoi(char *s)
598 +{
599 + uint n;
600 +
601 + n = 0;
602 +
603 + while (bcm_isdigit(*s))
604 + n = (n * 10) + *s++ - '0';
605 + return (n);
606 +}
607 +
608 +/* return pointer to location of substring 'needle' in 'haystack' */
609 +char*
610 +bcmstrstr(char *haystack, char *needle)
611 +{
612 + int len, nlen;
613 + int i;
614 +
615 + if ((haystack == NULL) || (needle == NULL))
616 + return (haystack);
617 +
618 + nlen = strlen(needle);
619 + len = strlen(haystack) - nlen + 1;
620 +
621 + for (i = 0; i < len; i++)
622 + if (bcmp(needle, &haystack[i], nlen) == 0)
623 + return (&haystack[i]);
624 + return (NULL);
625 +}
626 +
627 +char*
628 +bcmstrcat(char *dest, const char *src)
629 +{
630 + strcpy(&dest[strlen(dest)], src);
631 + return (dest);
632 +}
633 +
634 +
635 +char*
636 +bcm_ether_ntoa(char *ea, char *buf)
637 +{
638 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
639 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
640 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
641 + return (buf);
642 +}
643 +
644 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
645 +int
646 +bcm_ether_atoe(char *p, char *ea)
647 +{
648 + int i = 0;
649 +
650 + for (;;) {
651 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
652 + if (!*p++ || i == 6)
653 + break;
654 + }
655 +
656 + return (i == 6);
657 +}
658 +
659 +void
660 +bcm_mdelay(uint ms)
661 +{
662 + uint i;
663 +
664 + for (i = 0; i < ms; i++) {
665 + OSL_DELAY(1000);
666 + }
667 +}
668 +
669 +/*
670 + * Search the name=value vars for a specific one and return its value.
671 + * Returns NULL if not found.
672 + */
673 +char*
674 +getvar(char *vars, char *name)
675 +{
676 + char *s;
677 + int len;
678 +
679 + len = strlen(name);
680 +
681 + /* first look in vars[] */
682 + for (s = vars; s && *s; ) {
683 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
684 + return (&s[len+1]);
685 +
686 + while (*s++)
687 + ;
688 + }
689 +
690 + /* then query nvram */
691 + return (BCMINIT(nvram_get)(name));
692 +}
693 +
694 +/*
695 + * Search the vars for a specific one and return its value as
696 + * an integer. Returns 0 if not found.
697 + */
698 +int
699 +getintvar(char *vars, char *name)
700 +{
701 + char *val;
702 +
703 + if ((val = getvar(vars, name)) == NULL)
704 + return (0);
705 +
706 + return (bcm_strtoul(val, NULL, 0));
707 +}
708 +
709 +
710 +/* Search for token in comma separated token-string */
711 +static int
712 +findmatch(char *string, char *name)
713 +{
714 + uint len;
715 + char *c;
716 +
717 + len = strlen(name);
718 + while ((c = strchr(string, ',')) != NULL) {
719 + if (len == (uint)(c - string) && !strncmp(string, name, len))
720 + return 1;
721 + string = c + 1;
722 + }
723 +
724 + return (!strcmp(string, name));
725 +}
726 +
727 +/* Return gpio pin number assigned to the named pin */
728 +/*
729 +* Variable should be in format:
730 +*
731 +* gpio<N>=pin_name,pin_name
732 +*
733 +* This format allows multiple features to share the gpio with mutual
734 +* understanding.
735 +*
736 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
737 +* and if def_pin is not used by others.
738 +*/
739 +uint
740 +getgpiopin(char *vars, char *pin_name, uint def_pin)
741 +{
742 + char name[] = "gpioXXXX";
743 + char *val;
744 + uint pin;
745 +
746 + /* Go thru all possibilities till a match in pin name */
747 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
748 + sprintf(name, "gpio%d", pin);
749 + val = getvar(vars, name);
750 + if (val && findmatch(val, pin_name))
751 + return pin;
752 + }
753 +
754 + if (def_pin != GPIO_PIN_NOTDEFINED) {
755 + /* make sure the default pin is not used by someone else */
756 + sprintf(name, "gpio%d", def_pin);
757 + if (getvar(vars, name)) {
758 + def_pin = GPIO_PIN_NOTDEFINED;
759 + }
760 + }
761 +
762 + return def_pin;
763 +}
764 +
765 +
766 +/*******************************************************************************
767 + * crc8
768 + *
769 + * Computes a crc8 over the input data using the polynomial:
770 + *
771 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
772 + *
773 + * The caller provides the initial value (either CRC8_INIT_VALUE
774 + * or the previous returned value) to allow for processing of
775 + * discontiguous blocks of data. When generating the CRC the
776 + * caller is responsible for complementing the final return value
777 + * and inserting it into the byte stream. When checking, a final
778 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
779 + *
780 + * Reference: Dallas Semiconductor Application Note 27
781 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
782 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
783 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
784 + *
785 + ******************************************************************************/
786 +
787 +static uint8 crc8_table[256] = {
788 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
789 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
790 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
791 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
792 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
793 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
794 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
795 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
796 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
797 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
798 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
799 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
800 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
801 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
802 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
803 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
804 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
805 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
806 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
807 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
808 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
809 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
810 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
811 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
812 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
813 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
814 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
815 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
816 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
817 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
818 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
819 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
820 +};
821 +
822 +#define CRC_INNER_LOOP(n, c, x) \
823 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
824 +
825 +uint8
826 +hndcrc8(
827 + uint8 *pdata, /* pointer to array of data to process */
828 + uint nbytes, /* number of input data bytes to process */
829 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
830 +)
831 +{
832 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
833 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
834 + while (nbytes-- > 0)
835 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
836 +
837 + return crc;
838 +}
839 +
840 +#ifdef notdef
841 +#define CLEN 1499
842 +#define CBUFSIZ (CLEN+4)
843 +#define CNBUFS 5
844 +
845 +#endif
846 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/cfe_env.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/cfe_env.c
847 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
848 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/cfe_env.c 2006-06-18 15:29:23.000000000 +0200
849 @@ -0,0 +1,234 @@
850 +/*
851 + * NVRAM variable manipulation (Linux kernel half)
852 + *
853 + * Copyright 2001-2003, Broadcom Corporation
854 + * All Rights Reserved.
855 + *
856 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
857 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
858 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
859 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
860 + *
861 + * $Id$
862 + */
863 +
864 +#include <linux/config.h>
865 +#include <linux/init.h>
866 +#include <linux/module.h>
867 +#include <linux/kernel.h>
868 +#include <linux/string.h>
869 +#include <asm/io.h>
870 +#include <asm/uaccess.h>
871 +
872 +#include <typedefs.h>
873 +#include <osl.h>
874 +#include <bcmendian.h>
875 +#include <bcmutils.h>
876 +
877 +#define NVRAM_SIZE (0x1ff0)
878 +static char _nvdata[NVRAM_SIZE] __initdata;
879 +static char _valuestr[256] __initdata;
880 +
881 +/*
882 + * TLV types. These codes are used in the "type-length-value"
883 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
884 + *
885 + * The layout of the flash/nvram is as follows:
886 + *
887 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
888 + *
889 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
890 + * The "length" field marks the length of the data section, not
891 + * including the type and length fields.
892 + *
893 + * Environment variables are stored as follows:
894 + *
895 + * <type_env> <length> <flags> <name> = <value>
896 + *
897 + * If bit 0 (low bit) is set, the length is an 8-bit value.
898 + * If bit 0 (low bit) is clear, the length is a 16-bit value
899 + *
900 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
901 + * indicates the size of the length field.
902 + *
903 + * Flags are from the constants below:
904 + *
905 + */
906 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
907 +#define ENV_LENGTH_8BITS 0x01
908 +
909 +#define ENV_TYPE_USER 0x80
910 +
911 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
912 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
913 +
914 +/*
915 + * The actual TLV types we support
916 + */
917 +
918 +#define ENV_TLV_TYPE_END 0x00
919 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
920 +
921 +/*
922 + * Environment variable flags
923 + */
924 +
925 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
926 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
927 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
928 +
929 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
930 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
931 +
932 +
933 +/* *********************************************************************
934 + * _nvram_read(buffer,offset,length)
935 + *
936 + * Read data from the NVRAM device
937 + *
938 + * Input parameters:
939 + * buffer - destination buffer
940 + * offset - offset of data to read
941 + * length - number of bytes to read
942 + *
943 + * Return value:
944 + * number of bytes read, or <0 if error occured
945 + ********************************************************************* */
946 +static int
947 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
948 +{
949 + int i;
950 + if (offset > NVRAM_SIZE)
951 + return -1;
952 +
953 + for ( i = 0; i < length; i++) {
954 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
955 + }
956 + return length;
957 +}
958 +
959 +
960 +static char*
961 +_strnchr(const char *dest,int c,size_t cnt)
962 +{
963 + while (*dest && (cnt > 0)) {
964 + if (*dest == c) return (char *) dest;
965 + dest++;
966 + cnt--;
967 + }
968 + return NULL;
969 +}
970 +
971 +
972 +
973 +/*
974 + * Core support API: Externally visible.
975 + */
976 +
977 +/*
978 + * Get the value of an NVRAM variable
979 + * @param name name of variable to get
980 + * @return value of variable or NULL if undefined
981 + */
982 +
983 +char*
984 +cfe_env_get(unsigned char *nv_buf, char* name)
985 +{
986 + int size;
987 + unsigned char *buffer;
988 + unsigned char *ptr;
989 + unsigned char *envval;
990 + unsigned int reclen;
991 + unsigned int rectype;
992 + int offset;
993 + int flg;
994 +
995 + size = NVRAM_SIZE;
996 + buffer = &_nvdata[0];
997 +
998 + ptr = buffer;
999 + offset = 0;
1000 +
1001 + /* Read the record type and length */
1002 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1003 + goto error;
1004 + }
1005 +
1006 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1007 +
1008 + /* Adjust pointer for TLV type */
1009 + rectype = *(ptr);
1010 + offset++;
1011 + size--;
1012 +
1013 + /*
1014 + * Read the length. It can be either 1 or 2 bytes
1015 + * depending on the code
1016 + */
1017 + if (rectype & ENV_LENGTH_8BITS) {
1018 + /* Read the record type and length - 8 bits */
1019 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1020 + goto error;
1021 + }
1022 + reclen = *(ptr);
1023 + size--;
1024 + offset++;
1025 + }
1026 + else {
1027 + /* Read the record type and length - 16 bits, MSB first */
1028 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1029 + goto error;
1030 + }
1031 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1032 + size -= 2;
1033 + offset += 2;
1034 + }
1035 +
1036 + if (reclen > size)
1037 + break; /* should not happen, bad NVRAM */
1038 +
1039 + switch (rectype) {
1040 + case ENV_TLV_TYPE_ENV:
1041 + /* Read the TLV data */
1042 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1043 + goto error;
1044 + flg = *ptr++;
1045 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1046 + if (envval) {
1047 + *envval++ = '\0';
1048 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1049 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1050 +#if 0
1051 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1052 +#endif
1053 + if(!strcmp(ptr, name)){
1054 + return _valuestr;
1055 + }
1056 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1057 + return _valuestr;
1058 + }
1059 + break;
1060 +
1061 + default:
1062 + /* Unknown TLV type, skip it. */
1063 + break;
1064 + }
1065 +
1066 + /*
1067 + * Advance to next TLV
1068 + */
1069 +
1070 + size -= (int)reclen;
1071 + offset += reclen;
1072 +
1073 + /* Read the next record type */
1074 + ptr = buffer;
1075 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1076 + goto error;
1077 + }
1078 +
1079 +error:
1080 + return NULL;
1081 +
1082 +}
1083 +
1084 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/linux_osl.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/linux_osl.c
1085 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
1086 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/linux_osl.c 2006-06-18 15:29:23.000000000 +0200
1087 @@ -0,0 +1,102 @@
1088 +/*
1089 + * Linux OS Independent Layer
1090 + *
1091 + * Copyright 2005, Broadcom Corporation
1092 + * All Rights Reserved.
1093 + *
1094 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1095 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1096 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1097 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1098 + *
1099 + * $Id$
1100 + */
1101 +
1102 +#define LINUX_OSL
1103 +
1104 +#include <typedefs.h>
1105 +#include <bcmendian.h>
1106 +#include <linux/module.h>
1107 +#include <linuxver.h>
1108 +#include <osl.h>
1109 +#include <bcmutils.h>
1110 +#include <linux/delay.h>
1111 +#ifdef mips
1112 +#include <asm/paccess.h>
1113 +#endif
1114 +#include <pcicfg.h>
1115 +
1116 +#define PCI_CFG_RETRY 10
1117 +
1118 +#define OS_HANDLE_MAGIC 0x1234abcd
1119 +#define BCM_MEM_FILENAME_LEN 24
1120 +
1121 +typedef struct bcm_mem_link {
1122 + struct bcm_mem_link *prev;
1123 + struct bcm_mem_link *next;
1124 + uint size;
1125 + int line;
1126 + char file[BCM_MEM_FILENAME_LEN];
1127 +} bcm_mem_link_t;
1128 +
1129 +struct os_handle {
1130 + uint magic;
1131 + void *pdev;
1132 + uint malloced;
1133 + uint failed;
1134 + bcm_mem_link_t *dbgmem_list;
1135 +};
1136 +
1137 +uint32
1138 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
1139 +{
1140 + uint val;
1141 + uint retry=PCI_CFG_RETRY;
1142 +
1143 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1144 +
1145 + /* only 4byte access supported */
1146 + ASSERT(size == 4);
1147 +
1148 + do {
1149 + pci_read_config_dword(osh->pdev, offset, &val);
1150 + if (val != 0xffffffff)
1151 + break;
1152 + } while (retry--);
1153 +
1154 +
1155 + return (val);
1156 +}
1157 +
1158 +void
1159 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
1160 +{
1161 + uint retry=PCI_CFG_RETRY;
1162 +
1163 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1164 +
1165 + /* only 4byte access supported */
1166 + ASSERT(size == 4);
1167 +
1168 + do {
1169 + pci_write_config_dword(osh->pdev, offset, val);
1170 + if (offset!=PCI_BAR0_WIN)
1171 + break;
1172 + if (osl_pci_read_config(osh,offset,size) == val)
1173 + break;
1174 + } while (retry--);
1175 +
1176 +}
1177 +
1178 +void
1179 +osl_delay(uint usec)
1180 +{
1181 + uint d;
1182 +
1183 + while (usec > 0) {
1184 + d = MIN(usec, 1000);
1185 + udelay(d);
1186 + usec -= d;
1187 + }
1188 +}
1189 +
1190 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/Makefile linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/Makefile
1191 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
1192 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/Makefile 2006-06-18 15:29:23.000000000 +0200
1193 @@ -0,0 +1,6 @@
1194 +#
1195 +# Makefile for the BCM47xx specific kernel interface routines
1196 +# under Linux.
1197 +#
1198 +
1199 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o cfe_env.o
1200 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/nvram.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/nvram.c
1201 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1202 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/nvram.c 2006-06-18 15:29:23.000000000 +0200
1203 @@ -0,0 +1,192 @@
1204 +/*
1205 + * NVRAM variable manipulation (Linux kernel half)
1206 + *
1207 + * Copyright 2005, Broadcom Corporation
1208 + * All Rights Reserved.
1209 + *
1210 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1211 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1212 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1213 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1214 + *
1215 + * $Id$
1216 + */
1217 +
1218 +#include <linux/config.h>
1219 +#include <linux/init.h>
1220 +#include <linux/module.h>
1221 +#include <linux/kernel.h>
1222 +#include <linux/string.h>
1223 +#include <linux/interrupt.h>
1224 +#include <linux/spinlock.h>
1225 +#include <linux/slab.h>
1226 +#include <asm/bootinfo.h>
1227 +#include <asm/addrspace.h>
1228 +#include <asm/io.h>
1229 +#include <asm/uaccess.h>
1230 +
1231 +#include <typedefs.h>
1232 +#include <bcmendian.h>
1233 +#include <bcmnvram.h>
1234 +#include <bcmutils.h>
1235 +#include <sbconfig.h>
1236 +#include <sbchipc.h>
1237 +#include <sbutils.h>
1238 +#include <sbmips.h>
1239 +#include <sflash.h>
1240 +
1241 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1242 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1243 +
1244 +/* Global SB handle */
1245 +extern void *sbh;
1246 +extern spinlock_t bcm947xx_sbh_lock;
1247 +static int cfe_env;
1248 +
1249 +extern char *cfe_env_get(char *nv_buf, const char *name);
1250 +
1251 +
1252 +/* Convenience */
1253 +#define sbh_lock bcm947xx_sbh_lock
1254 +#define KB * 1024
1255 +#define MB * 1024 * 1024
1256 +
1257 +/* Probe for NVRAM header */
1258 +static void __init
1259 +early_nvram_init(void)
1260 +{
1261 + struct nvram_header *header;
1262 + chipcregs_t *cc;
1263 + struct sflash *info = NULL;
1264 + int i;
1265 + uint32 base, off, lim;
1266 + u32 *src, *dst;
1267 +
1268 + cfe_env = 0;
1269 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1270 + base = KSEG1ADDR(SB_FLASH2);
1271 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1272 + case PFLASH:
1273 + lim = SB_FLASH2_SZ;
1274 + break;
1275 +
1276 + case SFLASH_ST:
1277 + case SFLASH_AT:
1278 + if ((info = sflash_init(cc)) == NULL)
1279 + return;
1280 + lim = info->size;
1281 + break;
1282 +
1283 + case FLASH_NONE:
1284 + default:
1285 + return;
1286 + }
1287 + } else {
1288 + /* extif assumed, Stop at 4 MB */
1289 + base = KSEG1ADDR(SB_FLASH1);
1290 + lim = SB_FLASH1_SZ;
1291 + }
1292 +
1293 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
1294 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
1295 + dst = (u32 *) nvram_buf;
1296 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
1297 + printk("early_nvram_init: WGT634U NVRAM found.\n");
1298 +
1299 + for (i = 0; i < 0x1ff0; i++) {
1300 + if (*src == 0xFFFFFFFF)
1301 + break;
1302 + *dst++ = *src++;
1303 + }
1304 + cfe_env = 1;
1305 + return;
1306 + }
1307 +
1308 + off = FLASH_MIN;
1309 + while (off <= lim) {
1310 + /* Windowed flash access */
1311 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1312 + if (header->magic == NVRAM_MAGIC)
1313 + goto found;
1314 + off <<= 1;
1315 + }
1316 +
1317 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1318 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1319 + if (header->magic == NVRAM_MAGIC)
1320 + goto found;
1321 +
1322 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1323 + if (header->magic == NVRAM_MAGIC)
1324 + goto found;
1325 +
1326 + return;
1327 +
1328 +found:
1329 + src = (u32 *) header;
1330 + dst = (u32 *) nvram_buf;
1331 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1332 + *dst++ = *src++;
1333 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1334 + *dst++ = ltoh32(*src++);
1335 +}
1336 +
1337 +/* Early (before mm or mtd) read-only access to NVRAM */
1338 +char * __init early_nvram_get(const char *name)
1339 +{
1340 + char *var, *value, *end, *eq;
1341 +
1342 + if (!name)
1343 + return NULL;
1344 +
1345 + /* Too early? */
1346 + if (sbh == NULL)
1347 + return NULL;
1348 +
1349 + if (!nvram_buf[0])
1350 + early_nvram_init();
1351 +
1352 + if (cfe_env)
1353 + return cfe_env_get(nvram_buf, name);
1354 +
1355 + /* Look for name=value and return value */
1356 + var = &nvram_buf[sizeof(struct nvram_header)];
1357 + end = nvram_buf + sizeof(nvram_buf) - 2;
1358 + end[0] = end[1] = '\0';
1359 + for (; *var; var = value + strlen(value) + 1) {
1360 + if (!(eq = strchr(var, '=')))
1361 + break;
1362 + value = eq + 1;
1363 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1364 + return value;
1365 + }
1366 +
1367 + return NULL;
1368 +}
1369 +
1370 +char *nvram_get(const char *name)
1371 +{
1372 + char *var, *value, *end, *eq;
1373 +
1374 + if (!name)
1375 + return NULL;
1376 +
1377 + if (!nvram_buf[0])
1378 + return NULL;
1379 +
1380 + /* Look for name=value and return value */
1381 + var = &nvram_buf[sizeof(struct nvram_header)];
1382 + end = nvram_buf + sizeof(nvram_buf) - 2;
1383 + end[0] = end[1] = '\0';
1384 + for (; *var; var = value + strlen(value) + 1) {
1385 + if (!(eq = strchr(var, '=')))
1386 + break;
1387 + value = eq + 1;
1388 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1389 + return value;
1390 + }
1391 +
1392 + return NULL;
1393 +}
1394 +
1395 +EXPORT_SYMBOL(nvram_get);
1396 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/sbmips.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbmips.c
1397 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1398 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbmips.c 2006-06-18 15:29:23.000000000 +0200
1399 @@ -0,0 +1,1055 @@
1400 +/*
1401 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1402 + *
1403 + * Copyright 2005, Broadcom Corporation
1404 + * All Rights Reserved.
1405 + *
1406 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1407 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1408 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1409 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1410 + *
1411 + * $Id$
1412 + */
1413 +
1414 +#include <typedefs.h>
1415 +#include <osl.h>
1416 +#include <sbutils.h>
1417 +#include <bcmdevs.h>
1418 +#include <bcmnvram.h>
1419 +#include <bcmutils.h>
1420 +#include <hndmips.h>
1421 +#include <sbconfig.h>
1422 +#include <sbextif.h>
1423 +#include <sbchipc.h>
1424 +#include <sbmemc.h>
1425 +#include <mipsinc.h>
1426 +#include <sbutils.h>
1427 +
1428 +/*
1429 + * Returns TRUE if an external UART exists at the given base
1430 + * register.
1431 + */
1432 +static bool
1433 +BCMINITFN(serial_exists)(uint8 *regs)
1434 +{
1435 + uint8 save_mcr, status1;
1436 +
1437 + save_mcr = R_REG(&regs[UART_MCR]);
1438 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1439 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1440 + W_REG(&regs[UART_MCR], save_mcr);
1441 +
1442 + return (status1 == 0x90);
1443 +}
1444 +
1445 +/*
1446 + * Initializes UART access. The callback function will be called once
1447 + * per found UART.
1448 + */
1449 +void
1450 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1451 +{
1452 + void *regs;
1453 + ulong base;
1454 + uint irq;
1455 + int i, n;
1456 +
1457 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1458 + extifregs_t *eir = (extifregs_t *) regs;
1459 + sbconfig_t *sb;
1460 +
1461 + /* Determine external UART register base */
1462 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1463 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1464 +
1465 + /* Determine IRQ */
1466 + irq = sb_irq(sbh);
1467 +
1468 + /* Disable GPIO interrupt initially */
1469 + W_REG(&eir->gpiointpolarity, 0);
1470 + W_REG(&eir->gpiointmask, 0);
1471 +
1472 + /* Search for external UARTs */
1473 + n = 2;
1474 + for (i = 0; i < 2; i++) {
1475 + regs = (void *) REG_MAP(base + (i * 8), 8);
1476 + if (BCMINIT(serial_exists)(regs)) {
1477 + /* Set GPIO 1 to be the external UART IRQ */
1478 + W_REG(&eir->gpiointmask, 2);
1479 + if (add)
1480 + add(regs, irq, 13500000, 0);
1481 + }
1482 + }
1483 +
1484 + /* Add internal UART if enabled */
1485 + if (R_REG(&eir->corecontrol) & CC_UE)
1486 + if (add)
1487 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1488 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1489 + chipcregs_t *cc = (chipcregs_t *) regs;
1490 + uint32 rev, cap, pll, baud_base, div;
1491 +
1492 + /* Determine core revision and capabilities */
1493 + rev = sb_corerev(sbh);
1494 + cap = R_REG(&cc->capabilities);
1495 + pll = cap & CAP_PLL_MASK;
1496 +
1497 + /* Determine IRQ */
1498 + irq = sb_irq(sbh);
1499 +
1500 + if (pll == PLL_TYPE1) {
1501 + /* PLL clock */
1502 + baud_base = sb_clock_rate(pll,
1503 + R_REG(&cc->clockcontrol_n),
1504 + R_REG(&cc->clockcontrol_m2));
1505 + div = 1;
1506 + } else {
1507 + if (rev >= 11) {
1508 + /* Fixed ALP clock */
1509 + baud_base = 20000000;
1510 + div = 1;
1511 + /* Set the override bit so we don't divide it */
1512 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1513 + } else if (rev >= 3) {
1514 + /* Internal backplane clock */
1515 + baud_base = sb_clock(sbh);
1516 + div = 2; /* Minimum divisor */
1517 + W_REG(&cc->clkdiv,
1518 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1519 + } else {
1520 + /* Fixed internal backplane clock */
1521 + baud_base = 88000000;
1522 + div = 48;
1523 + }
1524 +
1525 + /* Clock source depends on strapping if UartClkOverride is unset */
1526 + if ((rev > 0) &&
1527 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1528 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1529 + /* Internal divided backplane clock */
1530 + baud_base /= div;
1531 + } else {
1532 + /* Assume external clock of 1.8432 MHz */
1533 + baud_base = 1843200;
1534 + }
1535 + }
1536 + }
1537 +
1538 + /* Add internal UARTs */
1539 + n = cap & CAP_UARTS_MASK;
1540 + for (i = 0; i < n; i++) {
1541 + /* Register offset changed after revision 0 */
1542 + if (rev)
1543 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1544 + else
1545 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1546 +
1547 + if (add)
1548 + add(regs, irq, baud_base, 0);
1549 + }
1550 + }
1551 +}
1552 +
1553 +/*
1554 + * Initialize jtag master and return handle for
1555 + * jtag_rwreg. Returns NULL on failure.
1556 + */
1557 +void *
1558 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1559 +{
1560 + void *regs;
1561 +
1562 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1563 + chipcregs_t *cc = (chipcregs_t *) regs;
1564 + uint32 tmp;
1565 +
1566 + /*
1567 + * Determine jtagm availability from
1568 + * core revision and capabilities.
1569 + */
1570 + tmp = sb_corerev(sbh);
1571 + /*
1572 + * Corerev 10 has jtagm, but the only chip
1573 + * with it does not have a mips, and
1574 + * the layout of the jtagcmd register is
1575 + * different. We'll only accept >= 11.
1576 + */
1577 + if (tmp < 11)
1578 + return (NULL);
1579 +
1580 + tmp = R_REG(&cc->capabilities);
1581 + if ((tmp & CAP_JTAGP) == 0)
1582 + return (NULL);
1583 +
1584 + /* Set clock divider if requested */
1585 + if (clkd != 0) {
1586 + tmp = R_REG(&cc->clkdiv);
1587 + tmp = (tmp & ~CLKD_JTAG) |
1588 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1589 + W_REG(&cc->clkdiv, tmp);
1590 + }
1591 +
1592 + /* Enable jtagm */
1593 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1594 + W_REG(&cc->jtagctrl, tmp);
1595 + }
1596 +
1597 + return (regs);
1598 +}
1599 +
1600 +void
1601 +sb_jtagm_disable(void *h)
1602 +{
1603 + chipcregs_t *cc = (chipcregs_t *)h;
1604 +
1605 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1606 +}
1607 +
1608 +/*
1609 + * Read/write a jtag register. Assumes a target with
1610 + * 8 bit IR and 32 bit DR.
1611 + */
1612 +#define IRWIDTH 8
1613 +#define DRWIDTH 32
1614 +uint32
1615 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1616 +{
1617 + chipcregs_t *cc = (chipcregs_t *) h;
1618 + uint32 tmp;
1619 +
1620 + W_REG(&cc->jtagir, ir);
1621 + W_REG(&cc->jtagdr, dr);
1622 + tmp = JCMD_START | JCMD_ACC_IRDR |
1623 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1624 + (DRWIDTH - 1);
1625 + W_REG(&cc->jtagcmd, tmp);
1626 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1627 + /* OSL_DELAY(1); */
1628 + }
1629 +
1630 + tmp = R_REG(&cc->jtagdr);
1631 + return (tmp);
1632 +}
1633 +
1634 +/* Returns the SB interrupt flag of the current core. */
1635 +uint32
1636 +sb_flag(sb_t *sbh)
1637 +{
1638 + void *regs;
1639 + sbconfig_t *sb;
1640 +
1641 + regs = sb_coreregs(sbh);
1642 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1643 +
1644 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1645 +}
1646 +
1647 +static const uint32 sbips_int_mask[] = {
1648 + 0,
1649 + SBIPS_INT1_MASK,
1650 + SBIPS_INT2_MASK,
1651 + SBIPS_INT3_MASK,
1652 + SBIPS_INT4_MASK
1653 +};
1654 +
1655 +static const uint32 sbips_int_shift[] = {
1656 + 0,
1657 + 0,
1658 + SBIPS_INT2_SHIFT,
1659 + SBIPS_INT3_SHIFT,
1660 + SBIPS_INT4_SHIFT
1661 +};
1662 +
1663 +/*
1664 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1665 + * 0 is returned.
1666 + */
1667 +uint
1668 +sb_irq(sb_t *sbh)
1669 +{
1670 + uint idx;
1671 + void *regs;
1672 + sbconfig_t *sb;
1673 + uint32 flag, sbipsflag;
1674 + uint irq = 0;
1675 +
1676 + flag = sb_flag(sbh);
1677 +
1678 + idx = sb_coreidx(sbh);
1679 +
1680 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1681 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1682 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1683 +
1684 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1685 + sbipsflag = R_REG(&sb->sbipsflag);
1686 + for (irq = 1; irq <= 4; irq++) {
1687 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1688 + break;
1689 + }
1690 + if (irq == 5)
1691 + irq = 0;
1692 + }
1693 +
1694 + sb_setcoreidx(sbh, idx);
1695 +
1696 + return irq;
1697 +}
1698 +
1699 +/* Clears the specified MIPS IRQ. */
1700 +static void
1701 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1702 +{
1703 + void *regs;
1704 + sbconfig_t *sb;
1705 +
1706 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1707 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1708 + ASSERT(regs);
1709 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1710 +
1711 + if (irq == 0)
1712 + W_REG(&sb->sbintvec, 0);
1713 + else
1714 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1715 +}
1716 +
1717 +/*
1718 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1719 + * IRQ 0 may be assigned more than once.
1720 + */
1721 +static void
1722 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1723 +{
1724 + void *regs;
1725 + sbconfig_t *sb;
1726 + uint32 flag;
1727 +
1728 + regs = sb_setcore(sbh, coreid, coreunit);
1729 + ASSERT(regs);
1730 + flag = sb_flag(sbh);
1731 +
1732 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1733 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1734 + ASSERT(regs);
1735 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1736 +
1737 + if (irq == 0)
1738 + OR_REG(&sb->sbintvec, 1 << flag);
1739 + else {
1740 + flag <<= sbips_int_shift[irq];
1741 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1742 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1743 + W_REG(&sb->sbipsflag, flag);
1744 + }
1745 +}
1746 +
1747 +/*
1748 + * Initializes clocks and interrupts. SB and NVRAM access must be
1749 + * initialized prior to calling.
1750 + */
1751 +void
1752 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1753 +{
1754 + ulong hz, ns, tmp;
1755 + extifregs_t *eir;
1756 + chipcregs_t *cc;
1757 + char *value;
1758 + uint irq;
1759 +
1760 + /* Figure out current SB clock speed */
1761 + if ((hz = sb_clock(sbh)) == 0)
1762 + hz = 100000000;
1763 + ns = 1000000000 / hz;
1764 +
1765 + /* Setup external interface timing */
1766 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1767 + /* Initialize extif so we can get to the LEDs and external UART */
1768 + W_REG(&eir->prog_config, CF_EN);
1769 +
1770 + /* Set timing for the flash */
1771 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1772 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1773 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1774 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1775 +
1776 + /* Set programmable interface timing for external uart */
1777 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1778 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1779 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1780 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1781 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1782 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1783 + /* set register for external IO to control LED. */
1784 + W_REG(&cc->prog_config, 0x11);
1785 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1786 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1787 + tmp = tmp | CEIL(240, ns); /* W0 = 120nS */
1788 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1789 +
1790 + /* Set timing for the flash */
1791 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1792 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1793 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1794 +
1795 + // Added by Chen-I for 5365
1796 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1797 + {
1798 + W_REG(&cc->flash_waitcount, tmp);
1799 + W_REG(&cc->pcmcia_memwait, tmp);
1800 + }
1801 + else
1802 + {
1803 + if (sb_corerev(sbh) < 9)
1804 + W_REG(&cc->flash_waitcount, tmp);
1805 +
1806 + if ((sb_corerev(sbh) < 9) ||
1807 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1808 + W_REG(&cc->pcmcia_memwait, tmp);
1809 + }
1810 + }
1811 + // Added by Chen-I & Yen for enabling 5350 EXTIF
1812 + if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
1813 + {
1814 + /* Set programmable interface timing for external uart */
1815 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1816 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1817 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1818 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1819 + W_REG(&cc->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1820 + }
1821 + }
1822 +
1823 + /* Chip specific initialization */
1824 + switch (BCMINIT(sb_chip)(sbh)) {
1825 + case BCM4710_DEVICE_ID:
1826 + /* Clear interrupt map */
1827 + for (irq = 0; irq <= 4; irq++)
1828 + BCMINIT(sb_clearirq)(sbh, irq);
1829 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1830 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1831 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1832 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
1833 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1834 + ASSERT(eir);
1835 + value = BCMINIT(early_nvram_get)("et0phyaddr");
1836 + if (value && !strcmp(value, "31")) {
1837 + /* Enable internal UART */
1838 + W_REG(&eir->corecontrol, CC_UE);
1839 + /* Give USB its own interrupt */
1840 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
1841 + } else {
1842 + /* Disable internal UART */
1843 + W_REG(&eir->corecontrol, 0);
1844 + /* Give Ethernet its own interrupt */
1845 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1846 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
1847 + }
1848 + break;
1849 + case BCM5350_DEVICE_ID:
1850 + /* Clear interrupt map */
1851 + for (irq = 0; irq <= 4; irq++)
1852 + BCMINIT(sb_clearirq)(sbh, irq);
1853 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1854 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1855 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1856 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1857 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1858 + break;
1859 + }
1860 +}
1861 +
1862 +uint32
1863 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1864 +{
1865 + extifregs_t *eir;
1866 + chipcregs_t *cc;
1867 + uint32 n, m;
1868 + uint idx;
1869 + uint32 pll_type, rate = 0;
1870 +
1871 + /* get index of the current core */
1872 + idx = sb_coreidx(sbh);
1873 + pll_type = PLL_TYPE1;
1874 +
1875 + /* switch to extif or chipc core */
1876 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1877 + n = R_REG(&eir->clockcontrol_n);
1878 + m = R_REG(&eir->clockcontrol_sb);
1879 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1880 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1881 + n = R_REG(&cc->clockcontrol_n);
1882 + if ((pll_type == PLL_TYPE2) ||
1883 + (pll_type == PLL_TYPE4) ||
1884 + (pll_type == PLL_TYPE6) ||
1885 + (pll_type == PLL_TYPE7))
1886 + m = R_REG(&cc->clockcontrol_mips);
1887 + else if (pll_type == PLL_TYPE5) {
1888 + rate = 200000000;
1889 + goto out;
1890 + }
1891 + else if (pll_type == PLL_TYPE3) {
1892 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1893 + rate = 200000000;
1894 + goto out;
1895 + } else
1896 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1897 + } else
1898 + m = R_REG(&cc->clockcontrol_sb);
1899 + } else
1900 + goto out;
1901 +
1902 + // Added by Chen-I for 5365
1903 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1904 + rate = 100000000;
1905 + else
1906 + /* calculate rate */
1907 + rate = sb_clock_rate(pll_type, n, m);
1908 +
1909 + if (pll_type == PLL_TYPE6)
1910 + rate = SB2MIPS_T6(rate);
1911 +
1912 +out:
1913 + /* switch back to previous core */
1914 + sb_setcoreidx(sbh, idx);
1915 +
1916 + return rate;
1917 +}
1918 +
1919 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1920 +
1921 +static void
1922 +BCMINITFN(handler)(void)
1923 +{
1924 + /* Step 11 */
1925 + __asm__ (
1926 + ".set\tmips32\n\t"
1927 + "ssnop\n\t"
1928 + "ssnop\n\t"
1929 + /* Disable interrupts */
1930 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1931 + "mfc0 $15, $12\n\t"
1932 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1933 + "li $14, -31746\n\t"
1934 + "and $15, $15, $14\n\t"
1935 + "mtc0 $15, $12\n\t"
1936 + "eret\n\t"
1937 + "nop\n\t"
1938 + "nop\n\t"
1939 + ".set\tmips0"
1940 + );
1941 +}
1942 +
1943 +/* The following MUST come right after handler() */
1944 +static void
1945 +BCMINITFN(afterhandler)(void)
1946 +{
1947 +}
1948 +
1949 +/*
1950 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1951 + */
1952 +bool
1953 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
1954 +{
1955 + extifregs_t *eir = NULL;
1956 + chipcregs_t *cc = NULL;
1957 + mipsregs_t *mipsr = NULL;
1958 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
1959 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
1960 + uint32 pll_type, sync_mode;
1961 + uint ic_size, ic_lsize;
1962 + uint idx, i;
1963 + typedef struct {
1964 + uint32 mipsclock;
1965 + uint16 n;
1966 + uint32 sb;
1967 + uint32 pci33;
1968 + uint32 pci25;
1969 + } n3m_table_t;
1970 + static n3m_table_t BCMINITDATA(type1_table)[] = {
1971 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
1972 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
1973 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
1974 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
1975 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
1976 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
1977 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
1978 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
1979 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
1980 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
1981 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
1982 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
1983 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
1984 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
1985 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
1986 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
1987 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
1988 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
1989 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
1990 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
1991 + };
1992 + typedef struct {
1993 + uint32 mipsclock;
1994 + uint16 n;
1995 + uint32 m2; /* that is the clockcontrol_m2 */
1996 + } type3_table_t;
1997 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
1998 + { 150000000, 0x311, 0x4020005 },
1999 + { 200000000, 0x311, 0x4020003 },
2000 + };
2001 + typedef struct {
2002 + uint32 mipsclock;
2003 + uint32 sbclock;
2004 + uint16 n;
2005 + uint32 sb;
2006 + uint32 pci33;
2007 + uint32 m2;
2008 + uint32 m3;
2009 + uint32 ratio_cfg;
2010 + uint32 ratio_parm;
2011 + } n4m_table_t;
2012 +
2013 + static n4m_table_t BCMINITDATA(type2_table)[] = {
2014 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2015 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2016 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
2017 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2018 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2019 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2020 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2021 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2022 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2023 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2024 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2025 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2026 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2027 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2028 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2029 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2030 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
2031 + };
2032 +
2033 + static n4m_table_t BCMINITDATA(type4_table)[] = {
2034 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2035 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2036 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2037 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2038 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2039 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2040 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2041 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2042 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
2043 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2044 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
2045 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2046 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
2047 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2048 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2049 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2050 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2051 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2052 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
2053 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
2054 + };
2055 +
2056 + static n4m_table_t BCMINITDATA(type7_table)[] = {
2057 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2058 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2059 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2060 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
2061 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2062 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2063 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2064 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2065 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2066 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2067 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2068 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2069 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
2070 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
2071 + };
2072 +
2073 + ulong start, end, dst;
2074 + bool ret = FALSE;
2075 +
2076 + /* get index of the current core */
2077 + idx = sb_coreidx(sbh);
2078 + clockcontrol_m2 = NULL;
2079 +
2080 + /* switch to extif or chipc core */
2081 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2082 + pll_type = PLL_TYPE1;
2083 + clockcontrol_n = &eir->clockcontrol_n;
2084 + clockcontrol_sb = &eir->clockcontrol_sb;
2085 + clockcontrol_pci = &eir->clockcontrol_pci;
2086 + clockcontrol_m2 = &cc->clockcontrol_m2;
2087 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2088 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2089 + if (pll_type == PLL_TYPE6) {
2090 + clockcontrol_n = NULL;
2091 + clockcontrol_sb = NULL;
2092 + clockcontrol_pci = NULL;
2093 + } else {
2094 + clockcontrol_n = &cc->clockcontrol_n;
2095 + clockcontrol_sb = &cc->clockcontrol_sb;
2096 + clockcontrol_pci = &cc->clockcontrol_pci;
2097 + clockcontrol_m2 = &cc->clockcontrol_m2;
2098 + }
2099 + } else
2100 + goto done;
2101 +
2102 + if (pll_type == PLL_TYPE6) {
2103 + /* Silence compilers */
2104 + orig_n = orig_sb = orig_pci = 0;
2105 + } else {
2106 + /* Store the current clock register values */
2107 + orig_n = R_REG(clockcontrol_n);
2108 + orig_sb = R_REG(clockcontrol_sb);
2109 + orig_pci = R_REG(clockcontrol_pci);
2110 + }
2111 +
2112 + if (pll_type == PLL_TYPE1) {
2113 + /* Keep the current PCI clock if not specified */
2114 + if (pciclock == 0) {
2115 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
2116 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
2117 + }
2118 +
2119 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2120 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
2121 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
2122 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
2123 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
2124 + break;
2125 + }
2126 + if (i == 0) {
2127 + ret = FALSE;
2128 + goto done;
2129 + } else {
2130 + ret = TRUE;
2131 + i--;
2132 + }
2133 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
2134 +
2135 + /* No PLL change */
2136 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
2137 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
2138 + (orig_pci == BCMINIT(type1_table)[i].pci33))
2139 + goto done;
2140 +
2141 + /* Set the PLL controls */
2142 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
2143 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
2144 + if (pciclock == 25000000)
2145 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
2146 + else
2147 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
2148 +
2149 + /* Reset */
2150 + sb_watchdog(sbh, 1);
2151 +
2152 + while (1);
2153 + } else if ((pll_type == PLL_TYPE3) &&
2154 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
2155 + /* 5350 */
2156 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2157 +
2158 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
2159 + if (type3_table[i].mipsclock > mipsclock)
2160 + break;
2161 + }
2162 + if (i == 0) {
2163 + ret = FALSE;
2164 + goto done;
2165 + } else {
2166 + ret = TRUE;
2167 + i--;
2168 + }
2169 + ASSERT(type3_table[i].mipsclock <= mipsclock);
2170 +
2171 + /* No PLL change */
2172 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2173 + if ((orig_n == type3_table[i].n) &&
2174 + (orig_m2 == type3_table[i].m2)) {
2175 + goto done;
2176 + }
2177 +
2178 + /* Set the PLL controls */
2179 + W_REG(clockcontrol_n, type3_table[i].n);
2180 + W_REG(clockcontrol_m2, type3_table[i].m2);
2181 +
2182 + /* Reset */
2183 + sb_watchdog(sbh, 1);
2184 + while (1);
2185 + } else if ((pll_type == PLL_TYPE2) ||
2186 + (pll_type == PLL_TYPE4) ||
2187 + (pll_type == PLL_TYPE6) ||
2188 + (pll_type == PLL_TYPE7)) {
2189 + n4m_table_t *table = NULL, *te;
2190 + uint tabsz = 0;
2191 +
2192 + ASSERT(cc);
2193 +
2194 + orig_mips = R_REG(&cc->clockcontrol_mips);
2195 +
2196 + if (pll_type == PLL_TYPE6) {
2197 + uint32 new_mips = 0;
2198 +
2199 + ret = TRUE;
2200 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
2201 + new_mips = CC_T6_MMASK;
2202 +
2203 + if (orig_mips == new_mips)
2204 + goto done;
2205 +
2206 + W_REG(&cc->clockcontrol_mips, new_mips);
2207 + goto end_fill;
2208 + }
2209 +
2210 + if (pll_type == PLL_TYPE2) {
2211 + table = BCMINIT(type2_table);
2212 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
2213 + } else if (pll_type == PLL_TYPE4) {
2214 + table = BCMINIT(type4_table);
2215 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
2216 + } else if (pll_type == PLL_TYPE7) {
2217 + table = BCMINIT(type7_table);
2218 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
2219 + } else
2220 + ASSERT("No table for plltype" == NULL);
2221 +
2222 + /* Store the current clock register values */
2223 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2224 + orig_ratio_parm = 0;
2225 + orig_ratio_cfg = 0;
2226 +
2227 + /* Look up current ratio */
2228 + for (i = 0; i < tabsz; i++) {
2229 + if ((orig_n == table[i].n) &&
2230 + (orig_sb == table[i].sb) &&
2231 + (orig_pci == table[i].pci33) &&
2232 + (orig_m2 == table[i].m2) &&
2233 + (orig_mips == table[i].m3)) {
2234 + orig_ratio_parm = table[i].ratio_parm;
2235 + orig_ratio_cfg = table[i].ratio_cfg;
2236 + break;
2237 + }
2238 + }
2239 +
2240 + /* Search for the closest MIPS clock greater or equal to a preferred value */
2241 + for (i = 0; i < tabsz; i++) {
2242 + ASSERT(table[i].mipsclock ==
2243 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
2244 + if ((mipsclock <= table[i].mipsclock) &&
2245 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
2246 + break;
2247 + }
2248 + if (i == tabsz) {
2249 + ret = FALSE;
2250 + goto done;
2251 + } else {
2252 + te = &table[i];
2253 + ret = TRUE;
2254 + }
2255 +
2256 + /* No PLL change */
2257 + if ((orig_n == te->n) &&
2258 + (orig_sb == te->sb) &&
2259 + (orig_pci == te->pci33) &&
2260 + (orig_m2 == te->m2) &&
2261 + (orig_mips == te->m3))
2262 + goto done;
2263 +
2264 + /* Set the PLL controls */
2265 + W_REG(clockcontrol_n, te->n);
2266 + W_REG(clockcontrol_sb, te->sb);
2267 + W_REG(clockcontrol_pci, te->pci33);
2268 + W_REG(&cc->clockcontrol_m2, te->m2);
2269 + W_REG(&cc->clockcontrol_mips, te->m3);
2270 +
2271 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2272 + if ((pll_type == PLL_TYPE7) &&
2273 + (te->sb != te->m2) &&
2274 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2275 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2276 +
2277 + /* No ratio change */
2278 + if (orig_ratio_parm == te->ratio_parm)
2279 + goto end_fill;
2280 +
2281 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2282 +
2283 + /* Preload the code into the cache */
2284 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2285 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2286 + while (start < end) {
2287 + cache_op(start, Fill_I);
2288 + start += ic_lsize;
2289 + }
2290 +
2291 + /* Copy the handler */
2292 + start = (ulong) &BCMINIT(handler);
2293 + end = (ulong) &BCMINIT(afterhandler);
2294 + dst = KSEG1ADDR(0x180);
2295 + for (i = 0; i < (end - start); i += 4)
2296 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2297 +
2298 + /* Preload handler into the cache one line at a time */
2299 + for (i = 0; i < (end - start); i += 4)
2300 + cache_op(dst + i, Fill_I);
2301 +
2302 + /* Clear BEV bit */
2303 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2304 +
2305 + /* Enable interrupts */
2306 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2307 +
2308 + /* Enable MIPS timer interrupt */
2309 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2310 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2311 + ASSERT(mipsr);
2312 + W_REG(&mipsr->intmask, 1);
2313 +
2314 + start_fill:
2315 + /* step 1, set clock ratios */
2316 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2317 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2318 +
2319 + /* step 2: program timer intr */
2320 + W_REG(&mipsr->timer, 100);
2321 + (void) R_REG(&mipsr->timer);
2322 +
2323 + /* step 3, switch to async */
2324 + sync_mode = MFC0(C0_BROADCOM, 4);
2325 + MTC0(C0_BROADCOM, 4, 1 << 22);
2326 +
2327 + /* step 4, set cfg active */
2328 + MTC0(C0_BROADCOM, 2, 0x9);
2329 +
2330 +
2331 + /* steps 5 & 6 */
2332 + __asm__ __volatile__ (
2333 + ".set\tmips3\n\t"
2334 + "wait\n\t"
2335 + ".set\tmips0"
2336 + );
2337 +
2338 + /* step 7, clear cfg_active */
2339 + MTC0(C0_BROADCOM, 2, 0);
2340 +
2341 + /* Additional Step: set back to orig sync mode */
2342 + MTC0(C0_BROADCOM, 4, sync_mode);
2343 +
2344 + /* step 8, fake soft reset */
2345 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2346 +
2347 + end_fill:
2348 + /* step 9 set watchdog timer */
2349 + sb_watchdog(sbh, 20);
2350 + (void) R_REG(&cc->chipid);
2351 +
2352 + /* step 11 */
2353 + __asm__ __volatile__ (
2354 + ".set\tmips3\n\t"
2355 + "sync\n\t"
2356 + "wait\n\t"
2357 + ".set\tmips0"
2358 + );
2359 + while (1);
2360 + }
2361 +
2362 +done:
2363 + /* switch back to previous core */
2364 + sb_setcoreidx(sbh, idx);
2365 +
2366 + return ret;
2367 +}
2368 +
2369 +/*
2370 + * This also must be run from the cache on 47xx
2371 + * so there are no mips core BIU ops in progress
2372 + * when the PFC is enabled.
2373 + */
2374 +
2375 +static void
2376 +BCMINITFN(_enable_pfc)(uint32 mode)
2377 +{
2378 + /* write range */
2379 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2380 +
2381 + /* enable */
2382 + *(volatile uint32 *)PFC_CR0 = mode;
2383 +}
2384 +
2385 +void
2386 +BCMINITFN(enable_pfc)(uint32 mode)
2387 +{
2388 + ulong start, end;
2389 + int i;
2390 +
2391 + /* If auto then choose the correct mode for this
2392 + platform, currently we only ever select one mode */
2393 + if (mode == PFC_AUTO)
2394 + mode = PFC_INST;
2395 +
2396 + /* enable prefetch cache if available */
2397 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2398 + start = (ulong) &BCMINIT(_enable_pfc);
2399 + end = (ulong) &BCMINIT(enable_pfc);
2400 +
2401 + /* Preload handler into the cache one line at a time */
2402 + for (i = 0; i < (end - start); i += 4)
2403 + cache_op(start + i, Fill_I);
2404 +
2405 + BCMINIT(_enable_pfc)(mode);
2406 + }
2407 +}
2408 +
2409 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2410 +uint32
2411 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2412 +{
2413 + sbmemcregs_t *memc;
2414 + uint32 ret = 0;
2415 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2416 + uint idx, rev;
2417 +
2418 + idx = sb_coreidx(sbh);
2419 +
2420 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2421 + if (memc == 0)
2422 + goto out;
2423 +
2424 + rev = sb_corerev(sbh);
2425 +
2426 + config = R_REG(&memc->config);
2427 + wr = R_REG(&memc->wrncdlcor);
2428 + rd = R_REG(&memc->rdncdlcor);
2429 + misc = R_REG(&memc->miscdlyctl);
2430 + dqsg = R_REG(&memc->dqsgatencdl);
2431 +
2432 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2433 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2434 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2435 +
2436 + if (config & MEMC_CONFIG_DDR) {
2437 + ret = (wr << 16) | (rd << 8) | dqsg;
2438 + } else {
2439 + if (rev > 0)
2440 + cd = rd;
2441 + else
2442 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2443 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2444 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2445 + ret = (sm << 16) | (sd << 8) | cd;
2446 + }
2447 +
2448 +out:
2449 + /* switch back to previous core */
2450 + sb_setcoreidx(sbh, idx);
2451 +
2452 + return ret;
2453 +}
2454 +
2455 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/sbpci.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbpci.c
2456 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2457 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbpci.c 2006-06-18 15:29:23.000000000 +0200
2458 @@ -0,0 +1,534 @@
2459 +/*
2460 + * Low-Level PCI and SB support for BCM47xx
2461 + *
2462 + * Copyright 2005, Broadcom Corporation
2463 + * All Rights Reserved.
2464 + *
2465 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2466 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2467 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2468 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2469 + *
2470 + * $Id$
2471 + */
2472 +
2473 +#include <typedefs.h>
2474 +#include <pcicfg.h>
2475 +#include <bcmdevs.h>
2476 +#include <sbconfig.h>
2477 +#include <osl.h>
2478 +#include <sbutils.h>
2479 +#include <sbpci.h>
2480 +#include <bcmendian.h>
2481 +#include <bcmutils.h>
2482 +#include <bcmnvram.h>
2483 +#include <hndmips.h>
2484 +
2485 +/* Can free sbpci_init() memory after boot */
2486 +#ifndef linux
2487 +#define __init
2488 +#endif
2489 +
2490 +/* Emulated configuration space */
2491 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2492 +
2493 +/* Banned cores */
2494 +static uint16 pci_ban[32] = { 0 };
2495 +static uint pci_banned = 0;
2496 +
2497 +/* CardBus mode */
2498 +static bool cardbus = FALSE;
2499 +
2500 +/* Disable PCI host core */
2501 +static bool pci_disabled = FALSE;
2502 +
2503 +/*
2504 + * Functions for accessing external PCI configuration space
2505 + */
2506 +
2507 +/* Assume one-hot slot wiring */
2508 +#define PCI_SLOT_MAX 16
2509 +
2510 +static uint32
2511 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2512 +{
2513 + uint coreidx;
2514 + sbpciregs_t *regs;
2515 + uint32 addr = 0;
2516 +
2517 + /* CardBusMode supports only one device */
2518 + if (cardbus && dev > 1)
2519 + return 0;
2520 +
2521 + coreidx = sb_coreidx(sbh);
2522 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2523 +
2524 + /* Type 0 transaction */
2525 + if (bus == 1) {
2526 + /* Skip unwired slots */
2527 + if (dev < PCI_SLOT_MAX) {
2528 + /* Slide the PCI window to the appropriate slot */
2529 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2530 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2531 + (func << 8) | (off & ~3);
2532 + }
2533 + }
2534 +
2535 + /* Type 1 transaction */
2536 + else {
2537 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2538 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2539 + }
2540 +
2541 + sb_setcoreidx(sbh, coreidx);
2542 +
2543 + return addr;
2544 +}
2545 +
2546 +static int
2547 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2548 +{
2549 + uint32 addr, *reg = NULL, val;
2550 + int ret = 0;
2551 +
2552 + if (pci_disabled ||
2553 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2554 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2555 + BUSPROBE(val, reg))
2556 + val = 0xffffffff;
2557 +
2558 + val >>= 8 * (off & 3);
2559 + if (len == 4)
2560 + *((uint32 *) buf) = val;
2561 + else if (len == 2)
2562 + *((uint16 *) buf) = (uint16) val;
2563 + else if (len == 1)
2564 + *((uint8 *) buf) = (uint8) val;
2565 + else
2566 + ret = -1;
2567 +
2568 + if (reg)
2569 + REG_UNMAP(reg);
2570 +
2571 + return ret;
2572 +}
2573 +
2574 +static int
2575 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2576 +{
2577 + uint32 addr, *reg = NULL, val;
2578 + int ret = 0;
2579 +
2580 + if (pci_disabled ||
2581 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2582 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2583 + BUSPROBE(val, reg))
2584 + goto done;
2585 +
2586 + if (len == 4)
2587 + val = *((uint32 *) buf);
2588 + else if (len == 2) {
2589 + val &= ~(0xffff << (8 * (off & 3)));
2590 + val |= *((uint16 *) buf) << (8 * (off & 3));
2591 + } else if (len == 1) {
2592 + val &= ~(0xff << (8 * (off & 3)));
2593 + val |= *((uint8 *) buf) << (8 * (off & 3));
2594 + } else
2595 + ret = -1;
2596 +
2597 + W_REG(reg, val);
2598 +
2599 + done:
2600 + if (reg)
2601 + REG_UNMAP(reg);
2602 +
2603 + return ret;
2604 +}
2605 +
2606 +/*
2607 + * Functions for accessing translated SB configuration space
2608 + */
2609 +
2610 +static int
2611 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2612 +{
2613 + pci_config_regs *cfg;
2614 +
2615 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2616 + return -1;
2617 + cfg = &sb_config_regs[dev];
2618 +
2619 + ASSERT(ISALIGNED(off, len));
2620 + ASSERT(ISALIGNED((uintptr)buf, len));
2621 +
2622 + if (len == 4)
2623 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2624 + else if (len == 2)
2625 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2626 + else if (len == 1)
2627 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2628 + else
2629 + return -1;
2630 +
2631 + return 0;
2632 +}
2633 +
2634 +static int
2635 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2636 +{
2637 + uint coreidx, n;
2638 + void *regs;
2639 + sbconfig_t *sb;
2640 + pci_config_regs *cfg;
2641 +
2642 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2643 + return -1;
2644 + cfg = &sb_config_regs[dev];
2645 +
2646 + ASSERT(ISALIGNED(off, len));
2647 + ASSERT(ISALIGNED((uintptr)buf, len));
2648 +
2649 + /* Emulate BAR sizing */
2650 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2651 + len == 4 && *((uint32 *) buf) == ~0) {
2652 + coreidx = sb_coreidx(sbh);
2653 + if ((regs = sb_setcoreidx(sbh, dev))) {
2654 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2655 + /* Highest numbered address match register */
2656 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2657 + if (off == OFFSETOF(pci_config_regs, base[0]))
2658 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2659 +#if 0
2660 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2661 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2662 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2663 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2664 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2665 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2666 +#endif
2667 + }
2668 + sb_setcoreidx(sbh, coreidx);
2669 + return 0;
2670 + }
2671 +
2672 + if (len == 4)
2673 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2674 + else if (len == 2)
2675 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2676 + else if (len == 1)
2677 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2678 + else
2679 + return -1;
2680 +
2681 + return 0;
2682 +}
2683 +
2684 +int
2685 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2686 +{
2687 + if (bus == 0)
2688 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2689 + else
2690 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2691 +}
2692 +
2693 +int
2694 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2695 +{
2696 + if (bus == 0)
2697 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2698 + else
2699 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2700 +}
2701 +
2702 +void
2703 +sbpci_ban(uint16 core)
2704 +{
2705 + if (pci_banned < ARRAYSIZE(pci_ban))
2706 + pci_ban[pci_banned++] = core;
2707 +}
2708 +
2709 +static int
2710 +sbpci_init_pci(sb_t *sbh)
2711 +{
2712 + uint chip, chiprev, chippkg, host;
2713 + uint32 boardflags;
2714 + sbpciregs_t *pci;
2715 + sbconfig_t *sb;
2716 + uint32 val;
2717 +
2718 + chip = sb_chip(sbh);
2719 + chiprev = sb_chiprev(sbh);
2720 + chippkg = sb_chippkg(sbh);
2721 +
2722 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2723 + printf("PCI: no core\n");
2724 + pci_disabled = TRUE;
2725 + return -1;
2726 + }
2727 + sb_core_reset(sbh, 0);
2728 +
2729 + boardflags = (uint32) getintvar(NULL, "boardflags");
2730 +
2731 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2732 + pci_disabled = TRUE;
2733 +
2734 + /*
2735 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2736 + * PCI is bonded out, some boards may leave the pins
2737 + * floating.
2738 + */
2739 + if (((chip == BCM4712_DEVICE_ID) &&
2740 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2741 + (chippkg == BCM4712MID_PKG_ID))) ||
2742 + (chip == BCM5350_DEVICE_ID) ||
2743 + (boardflags & BFL_NOPCI))
2744 + pci_disabled = TRUE;
2745 +
2746 + /*
2747 + * If the PCI core should not be touched (disabled, not bonded
2748 + * out, or pins floating), do not even attempt to access core
2749 + * registers. Otherwise, try to determine if it is in host
2750 + * mode.
2751 + */
2752 + if (pci_disabled)
2753 + host = 0;
2754 + else
2755 + host = !BUSPROBE(val, &pci->control);
2756 +
2757 + if (!host) {
2758 + /* Disable PCI interrupts in client mode */
2759 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2760 + W_REG(&sb->sbintvec, 0);
2761 +
2762 + /* Disable the PCI bridge in client mode */
2763 + sbpci_ban(SB_PCI);
2764 + printf("PCI: Disabled\n");
2765 + } else {
2766 + /* Reset the external PCI bus and enable the clock */
2767 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2768 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2769 + OSL_DELAY(150); /* delay > 100 us */
2770 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2771 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2772 + OSL_DELAY(1); /* delay 1 us */
2773 +
2774 + /* Enable CardBusMode */
2775 + cardbus = nvram_match("cardbus", "1");
2776 + if (cardbus) {
2777 + printf("PCI: Enabling CardBus\n");
2778 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2779 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2780 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2781 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2782 + }
2783 +
2784 + /* 64 MB I/O access window */
2785 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2786 + /* 64 MB configuration access window */
2787 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2788 + /* 1 GB memory access window */
2789 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2790 +
2791 + /* Enable PCI bridge BAR0 prefetch and burst */
2792 + val = 6;
2793 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2794 +
2795 + /* Enable PCI interrupts */
2796 + W_REG(&pci->intmask, PCI_INTA);
2797 + }
2798 +
2799 + return 0;
2800 +}
2801 +
2802 +static int
2803 +sbpci_init_cores(sb_t *sbh)
2804 +{
2805 + uint chip, chiprev, chippkg, coreidx, i;
2806 + sbconfig_t *sb;
2807 + pci_config_regs *cfg;
2808 + void *regs;
2809 + char varname[8];
2810 + uint wlidx = 0;
2811 + uint16 vendor, core;
2812 + uint8 class, subclass, progif;
2813 + uint32 val;
2814 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2815 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2816 +
2817 + chip = sb_chip(sbh);
2818 + chiprev = sb_chiprev(sbh);
2819 + chippkg = sb_chippkg(sbh);
2820 + coreidx = sb_coreidx(sbh);
2821 +
2822 + /* Scan the SB bus */
2823 + bzero(sb_config_regs, sizeof(sb_config_regs));
2824 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2825 + cfg->vendor = 0xffff;
2826 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2827 + continue;
2828 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2829 +
2830 + /* Read ID register and parse vendor and core */
2831 + val = R_REG(&sb->sbidhigh);
2832 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2833 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2834 + progif = 0;
2835 +
2836 + /* Check if this core is banned */
2837 + for (i = 0; i < pci_banned; i++)
2838 + if (core == pci_ban[i])
2839 + break;
2840 + if (i < pci_banned)
2841 + continue;
2842 +
2843 + /* Known vendor translations */
2844 + switch (vendor) {
2845 + case SB_VEND_BCM:
2846 + vendor = VENDOR_BROADCOM;
2847 + break;
2848 + }
2849 +
2850 + /* Determine class based on known core codes */
2851 + switch (core) {
2852 + case SB_ILINE20:
2853 + class = PCI_CLASS_NET;
2854 + subclass = PCI_NET_ETHER;
2855 + core = BCM47XX_ILINE_ID;
2856 + break;
2857 + case SB_ILINE100:
2858 + class = PCI_CLASS_NET;
2859 + subclass = PCI_NET_ETHER;
2860 + core = BCM4610_ILINE_ID;
2861 + break;
2862 + case SB_ENET:
2863 + class = PCI_CLASS_NET;
2864 + subclass = PCI_NET_ETHER;
2865 + core = BCM47XX_ENET_ID;
2866 + break;
2867 + case SB_SDRAM:
2868 + case SB_MEMC:
2869 + class = PCI_CLASS_MEMORY;
2870 + subclass = PCI_MEMORY_RAM;
2871 + break;
2872 + case SB_PCI:
2873 +#if 0
2874 + class = PCI_CLASS_BRIDGE;
2875 + subclass = PCI_BRIDGE_PCI;
2876 + break;
2877 +#endif
2878 + case SB_MIPS:
2879 + case SB_MIPS33:
2880 + class = PCI_CLASS_CPU;
2881 + subclass = PCI_CPU_MIPS;
2882 + break;
2883 + case SB_CODEC:
2884 + class = PCI_CLASS_COMM;
2885 + subclass = PCI_COMM_MODEM;
2886 + core = BCM47XX_V90_ID;
2887 + break;
2888 + case SB_USB:
2889 + class = PCI_CLASS_SERIAL;
2890 + subclass = PCI_SERIAL_USB;
2891 + progif = 0x10; /* OHCI */
2892 + core = BCM47XX_USB_ID;
2893 + break;
2894 + case SB_USB11H:
2895 + class = PCI_CLASS_SERIAL;
2896 + subclass = PCI_SERIAL_USB;
2897 + progif = 0x10; /* OHCI */
2898 + core = BCM47XX_USBH_ID;
2899 + break;
2900 + case SB_USB11D:
2901 + class = PCI_CLASS_SERIAL;
2902 + subclass = PCI_SERIAL_USB;
2903 + core = BCM47XX_USBD_ID;
2904 + break;
2905 + case SB_IPSEC:
2906 + class = PCI_CLASS_CRYPT;
2907 + subclass = PCI_CRYPT_NETWORK;
2908 + core = BCM47XX_IPSEC_ID;
2909 + break;
2910 + case SB_ROBO:
2911 + class = PCI_CLASS_NET;
2912 + subclass = PCI_NET_OTHER;
2913 + core = BCM47XX_ROBO_ID;
2914 + break;
2915 + case SB_EXTIF:
2916 + case SB_CC:
2917 + class = PCI_CLASS_MEMORY;
2918 + subclass = PCI_MEMORY_FLASH;
2919 + break;
2920 + case SB_D11:
2921 + class = PCI_CLASS_NET;
2922 + subclass = PCI_NET_OTHER;
2923 + /* Let an nvram variable override this */
2924 + sprintf(varname, "wl%did", wlidx);
2925 + wlidx++;
2926 + if ((core = getintvar(NULL, varname)) == 0) {
2927 + if (chip == BCM4712_DEVICE_ID) {
2928 + if (chippkg == BCM4712SMALL_PKG_ID)
2929 + core = BCM4306_D11G_ID;
2930 + else
2931 + core = BCM4306_D11DUAL_ID;
2932 + } else {
2933 + /* 4310 */
2934 + core = BCM4310_D11B_ID;
2935 + }
2936 + }
2937 + break;
2938 +
2939 + default:
2940 + class = subclass = progif = 0xff;
2941 + break;
2942 + }
2943 +
2944 + /* Supported translations */
2945 + cfg->vendor = htol16(vendor);
2946 + cfg->device = htol16(core);
2947 + cfg->rev_id = chiprev;
2948 + cfg->prog_if = progif;
2949 + cfg->sub_class = subclass;
2950 + cfg->base_class = class;
2951 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
2952 + cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
2953 + cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
2954 + cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
2955 + cfg->base[4] = 0;
2956 + cfg->base[5] = 0;
2957 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
2958 + cfg->header_type = PCI_HEADER_BRIDGE;
2959 + else
2960 + cfg->header_type = PCI_HEADER_NORMAL;
2961 + /* Save core interrupt flag */
2962 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
2963 + /* Default to MIPS shared interrupt 0 */
2964 + cfg->int_line = 0;
2965 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
2966 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
2967 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
2968 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2969 + val = R_REG(&sb->sbipsflag);
2970 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
2971 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
2972 + break;
2973 + }
2974 + if (cfg->int_line > 4)
2975 + cfg->int_line = 0;
2976 + }
2977 + /* Emulated core */
2978 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
2979 + }
2980 +
2981 + sb_setcoreidx(sbh, coreidx);
2982 + return 0;
2983 +}
2984 +
2985 +int __init
2986 +sbpci_init(sb_t *sbh)
2987 +{
2988 + sbpci_init_pci(sbh);
2989 + sbpci_init_cores(sbh);
2990 + return 0;
2991 +}
2992 +
2993 diff -Nur linux-2.6.17/arch/mips/bcm947xx/broadcom/sbutils.c linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbutils.c
2994 --- linux-2.6.17/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
2995 +++ linux-2.6.17-owrt/arch/mips/bcm947xx/broadcom/sbutils.c 2006-06-18 15:29:23.000000000 +0200
2996 @@ -0,0 +1,2370 @@
2997 +/*
2998 + * Misc utility routines for accessing chip-specific features
2999 + * of the SiliconBackplane-based Broadcom chips.
3000 + *
3001 + * Copyright 2005, Broadcom Corporation
3002 + * All Rights Reserved.
3003 + *
3004 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3005 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3006 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3007 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3008 + * $Id$
3009 + */
3010 +
3011 +#include <typedefs.h>
3012 +#include <osl.h>
3013 +#include <sbutils.h>
3014 +#include <bcmutils.h>
3015 +#include <bcmdevs.h>
3016 +#include <sbconfig.h>
3017 +#include <sbchipc.h>
3018 +#include <sbpci.h>
3019 +#include <pcicfg.h>
3020 +#include <sbextif.h>
3021 +#include <bcmsrom.h>
3022 +
3023 +/* debug/trace */
3024 +#define SB_ERROR(args)
3025 +
3026 +
3027 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
3028 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
3029 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
3030 +
3031 +/* misc sb info needed by some of the routines */
3032 +typedef struct sb_info {
3033 +
3034 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
3035 +
3036 + void *osh; /* osl os handle */
3037 + void *sdh; /* bcmsdh handle */
3038 +
3039 + void *curmap; /* current regs va */
3040 + void *regs[SB_MAXCORES]; /* other regs va */
3041 +
3042 + uint curidx; /* current core index */
3043 + uint dev_coreid; /* the core provides driver functions */
3044 +
3045 + uint gpioidx; /* gpio control core index */
3046 + uint gpioid; /* gpio control coretype */
3047 +
3048 + uint numcores; /* # discovered cores */
3049 + uint coreid[SB_MAXCORES]; /* id of each core */
3050 +
3051 + void *intr_arg; /* interrupt callback function arg */
3052 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
3053 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
3054 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
3055 +
3056 +} sb_info_t;
3057 +
3058 +/* local prototypes */
3059 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3060 + uint bustype, void *sdh, char **vars, int *varsz);
3061 +static void BCMINIT(sb_scan)(sb_info_t *si);
3062 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
3063 +static uint _sb_coreidx(sb_info_t *si);
3064 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
3065 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
3066 +static uint BCMINIT(sb_chip2numcores)(uint chip);
3067 +static int sb_pci_fixcfg(sb_info_t *si);
3068 +
3069 +/* delay needed between the mdio control/ mdiodata register data access */
3070 +#define PR28829_DELAY() OSL_DELAY(10)
3071 +
3072 +
3073 +/* global variable to indicate reservation/release of gpio's*/
3074 +static uint32 sb_gpioreservation = 0;
3075 +
3076 +#define SB_INFO(sbh) (sb_info_t*)sbh
3077 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
3078 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
3079 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
3080 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
3081 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
3082 +#define BADIDX (SB_MAXCORES+1)
3083 +#define NOREV -1
3084 +
3085 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
3086 +
3087 +/* sonicsrev */
3088 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
3089 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
3090 +
3091 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
3092 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
3093 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
3094 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
3095 +
3096 +/*
3097 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
3098 + * after core switching to avoid invalid register accesss inside ISR.
3099 + */
3100 +#define INTR_OFF(si, intr_val) \
3101 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3102 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
3103 +#define INTR_RESTORE(si, intr_val) \
3104 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3105 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
3106 +
3107 +/* dynamic clock control defines */
3108 +#define LPOMINFREQ 25000 /* low power oscillator min */
3109 +#define LPOMAXFREQ 43000 /* low power oscillator max */
3110 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
3111 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
3112 +#define PCIMINFREQ 25000000 /* 25 MHz */
3113 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
3114 +
3115 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
3116 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
3117 +
3118 +#define MIN_DUMPBUFLEN 32 /* debug */
3119 +
3120 +/* GPIO Based LED powersave defines */
3121 +#define DEFAULT_GPIO_ONTIME 10
3122 +#define DEFAULT_GPIO_OFFTIME 90
3123 +
3124 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
3125 +
3126 +static uint32
3127 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
3128 +{
3129 + uint32 val = R_REG(sbr);
3130 +
3131 + return (val);
3132 +}
3133 +
3134 +static void
3135 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
3136 +{
3137 + W_REG(sbr, v);
3138 +}
3139 +
3140 +/* Using sb_kattach depends on SB_BUS support, either implicit */
3141 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
3142 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
3143 +
3144 +/* global kernel resource */
3145 +static sb_info_t ksi;
3146 +
3147 +/* generic kernel variant of sb_attach() */
3148 +sb_t *
3149 +BCMINITFN(sb_kattach)()
3150 +{
3151 + uint32 *regs;
3152 +
3153 + if (ksi.curmap == NULL) {
3154 + uint32 cid;
3155 +
3156 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
3157 + cid = R_REG((uint32 *)regs);
3158 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
3159 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
3160 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
3161 + uint32 *scc, val;
3162 +
3163 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
3164 + val = R_REG(scc);
3165 + SB_ERROR((" initial scc = 0x%x\n", val));
3166 + val |= SCC_SS_XTAL;
3167 + W_REG(scc, val);
3168 + }
3169 +
3170 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
3171 + SB_BUS, NULL, NULL, NULL) == NULL) {
3172 + return NULL;
3173 + }
3174 + }
3175 +
3176 + return (sb_t *)&ksi;
3177 +}
3178 +#endif
3179 +
3180 +static sb_info_t *
3181 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3182 + uint bustype, void *sdh, char **vars, int *varsz)
3183 +{
3184 + uint origidx;
3185 + chipcregs_t *cc;
3186 + sbconfig_t *sb;
3187 + uint32 w;
3188 +
3189 + ASSERT(GOODREGS(regs));
3190 +
3191 + bzero((uchar*)si, sizeof (sb_info_t));
3192 +
3193 + si->sb.buscoreidx = si->gpioidx = BADIDX;
3194 +
3195 + si->osh = osh;
3196 + si->curmap = regs;
3197 + si->sdh = sdh;
3198 +
3199 + /* check to see if we are a sb core mimic'ing a pci core */
3200 + if (bustype == PCI_BUS) {
3201 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
3202 + bustype = SB_BUS;
3203 + else
3204 + bustype = PCI_BUS;
3205 + }
3206 +
3207 + si->sb.bustype = bustype;
3208 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
3209 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
3210 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
3211 + return NULL;
3212 + }
3213 +
3214 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
3215 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
3216 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
3217 +
3218 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3219 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
3220 + if (!GOODCOREADDR(w))
3221 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
3222 + }
3223 +
3224 + /* initialize current core index value */
3225 + si->curidx = _sb_coreidx(si);
3226 +
3227 + if (si->curidx == BADIDX) {
3228 + SB_ERROR(("sb_doattach: bad core index\n"));
3229 + return NULL;
3230 + }
3231 +
3232 + /* get sonics backplane revision */
3233 + sb = REGS2SB(si->curmap);
3234 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
3235 +
3236 + /* keep and reuse the initial register mapping */
3237 + origidx = si->curidx;
3238 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3239 + si->regs[origidx] = regs;
3240 +
3241 + /* is core-0 a chipcommon core? */
3242 + si->numcores = 1;
3243 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
3244 + if (sb_coreid(&si->sb) != SB_CC)
3245 + cc = NULL;
3246 +
3247 + /* determine chip id and rev */
3248 + if (cc) {
3249 + /* chip common core found! */
3250 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
3251 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
3252 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
3253 + } else {
3254 + /* no chip common core -- must convert device id to chip id */
3255 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3256 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3257 + sb_setcoreidx(&si->sb, origidx);
3258 + return NULL;
3259 + }
3260 + }
3261 +
3262 + /* get chipcommon rev */
3263 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3264 +
3265 + /* determine numcores */
3266 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3267 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3268 + else
3269 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3270 +
3271 + /* return to original core */
3272 + sb_setcoreidx(&si->sb, origidx);
3273 +
3274 + /* sanity checks */
3275 + ASSERT(si->sb.chip);
3276 +
3277 + /* scan for cores */
3278 + BCMINIT(sb_scan)(si);
3279 +
3280 + /* fixup necessary chip/core configurations */
3281 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3282 + if (sb_pci_fixcfg(si)) {
3283 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3284 + return NULL;
3285 + }
3286 + }
3287 +
3288 + /* srom_var_init() depends on sb_scan() info */
3289 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3290 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3291 + return (NULL);
3292 + }
3293 +
3294 + if (cc == NULL) {
3295 + /*
3296 + * The chip revision number is hardwired into all
3297 + * of the pci function config rev fields and is
3298 + * independent from the individual core revision numbers.
3299 + * For example, the "A0" silicon of each chip is chip rev 0.
3300 + */
3301 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3302 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3303 + si->sb.chiprev = w & 0xff;
3304 + } else
3305 + si->sb.chiprev = 0;
3306 + }
3307 +
3308 + /* gpio control core is required */
3309 + if (!GOODIDX(si->gpioidx)) {
3310 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3311 + return NULL;
3312 + }
3313 +
3314 + /* get boardtype and boardrev */
3315 + switch (BUSTYPE(si->sb.bustype)) {
3316 + case PCI_BUS:
3317 + /* do a pci config read to get subsystem id and subvendor id */
3318 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3319 + si->sb.boardvendor = w & 0xffff;
3320 + si->sb.boardtype = (w >> 16) & 0xffff;
3321 + break;
3322 +
3323 + case SB_BUS:
3324 + case JTAG_BUS:
3325 + si->sb.boardvendor = VENDOR_BROADCOM;
3326 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3327 + si->sb.boardtype = 0xffff;
3328 + break;
3329 + }
3330 +
3331 + if (si->sb.boardtype == 0) {
3332 + SB_ERROR(("sb_doattach: unknown board type\n"));
3333 + ASSERT(si->sb.boardtype);
3334 + }
3335 +
3336 + /* setup the GPIO based LED powersave register */
3337 + if (si->sb.ccrev >= 16) {
3338 + w = getintvar(*vars, "gpiotimerval");
3339 + if (!w)
3340 + w = DEFAULT_GPIOTIMERVAL;
3341 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3342 + }
3343 +
3344 +
3345 + return (si);
3346 +}
3347 +
3348 +uint
3349 +sb_coreid(sb_t *sbh)
3350 +{
3351 + sb_info_t *si;
3352 + sbconfig_t *sb;
3353 +
3354 + si = SB_INFO(sbh);
3355 + sb = REGS2SB(si->curmap);
3356 +
3357 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3358 +}
3359 +
3360 +uint
3361 +sb_coreidx(sb_t *sbh)
3362 +{
3363 + sb_info_t *si;
3364 +
3365 + si = SB_INFO(sbh);
3366 + return (si->curidx);
3367 +}
3368 +
3369 +/* return current index of core */
3370 +static uint
3371 +_sb_coreidx(sb_info_t *si)
3372 +{
3373 + sbconfig_t *sb;
3374 + uint32 sbaddr = 0;
3375 +
3376 + ASSERT(si);
3377 +
3378 + switch (BUSTYPE(si->sb.bustype)) {
3379 + case SB_BUS:
3380 + sb = REGS2SB(si->curmap);
3381 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3382 + break;
3383 +
3384 + case PCI_BUS:
3385 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3386 + break;
3387 +
3388 +#ifdef BCMJTAG
3389 + case JTAG_BUS:
3390 + sbaddr = (uint32)si->curmap;
3391 + break;
3392 +#endif /* BCMJTAG */
3393 +
3394 + default:
3395 + ASSERT(0);
3396 + }
3397 +
3398 + if (!GOODCOREADDR(sbaddr))
3399 + return BADIDX;
3400 +
3401 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3402 +}
3403 +
3404 +uint
3405 +sb_corevendor(sb_t *sbh)
3406 +{
3407 + sb_info_t *si;
3408 + sbconfig_t *sb;
3409 +
3410 + si = SB_INFO(sbh);
3411 + sb = REGS2SB(si->curmap);
3412 +
3413 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3414 +}
3415 +
3416 +uint
3417 +sb_corerev(sb_t *sbh)
3418 +{
3419 + sb_info_t *si;
3420 + sbconfig_t *sb;
3421 + uint sbidh;
3422 +
3423 + si = SB_INFO(sbh);
3424 + sb = REGS2SB(si->curmap);
3425 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3426 +
3427 + return (SBCOREREV(sbidh));
3428 +}
3429 +
3430 +void *
3431 +sb_osh(sb_t *sbh)
3432 +{
3433 + sb_info_t *si;
3434 +
3435 + si = SB_INFO(sbh);
3436 + return si->osh;
3437 +}
3438 +
3439 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3440 +
3441 +/* set/clear sbtmstatelow core-specific flags */
3442 +uint32
3443 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3444 +{
3445 + sb_info_t *si;
3446 + sbconfig_t *sb;
3447 + uint32 w;
3448 +
3449 + si = SB_INFO(sbh);
3450 + sb = REGS2SB(si->curmap);
3451 +
3452 + ASSERT((val & ~mask) == 0);
3453 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3454 +
3455 + /* mask and set */
3456 + if (mask || val) {
3457 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3458 + W_SBREG(si, &sb->sbtmstatelow, w);
3459 + }
3460 +
3461 + /* return the new value */
3462 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3463 +}
3464 +
3465 +/* set/clear sbtmstatehigh core-specific flags */
3466 +uint32
3467 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3468 +{
3469 + sb_info_t *si;
3470 + sbconfig_t *sb;
3471 + uint32 w;
3472 +
3473 + si = SB_INFO(sbh);
3474 + sb = REGS2SB(si->curmap);
3475 +
3476 + ASSERT((val & ~mask) == 0);
3477 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3478 +
3479 + /* mask and set */
3480 + if (mask || val) {
3481 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3482 + W_SBREG(si, &sb->sbtmstatehigh, w);
3483 + }
3484 +
3485 + /* return the new value */
3486 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3487 +}
3488 +
3489 +/* caller needs to take care of core-specific bist hazards */
3490 +int
3491 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3492 +{
3493 + uint32 sblo;
3494 + uint coreidx;
3495 + sb_info_t *si;
3496 + int result = 0;
3497 +
3498 + si = SB_INFO(sbh);
3499 +
3500 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3501 + if (!GOODIDX(coreidx))
3502 + result = BCME_ERROR;
3503 + else {
3504 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3505 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3506 +
3507 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3508 +
3509 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3510 + result = BCME_ERROR;
3511 +
3512 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3513 + }
3514 +
3515 + return result;
3516 +}
3517 +
3518 +bool
3519 +sb_iscoreup(sb_t *sbh)
3520 +{
3521 + sb_info_t *si;
3522 + sbconfig_t *sb;
3523 +
3524 + si = SB_INFO(sbh);
3525 + sb = REGS2SB(si->curmap);
3526 +
3527 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3528 +}
3529 +
3530 +/*
3531 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3532 + * switch back to the original core, and return the new value.
3533 + */
3534 +static uint
3535 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3536 +{
3537 + uint origidx;
3538 + uint32 *r;
3539 + uint w;
3540 + uint intr_val = 0;
3541 +
3542 + ASSERT(GOODIDX(coreidx));
3543 + ASSERT(regoff < SB_CORE_SIZE);
3544 + ASSERT((val & ~mask) == 0);
3545 +
3546 + INTR_OFF(si, intr_val);
3547 +
3548 + /* save current core index */
3549 + origidx = sb_coreidx(&si->sb);
3550 +
3551 + /* switch core */
3552 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3553 +
3554 + /* mask and set */
3555 + if (mask || val) {
3556 + if (regoff >= SBCONFIGOFF) {
3557 + w = (R_SBREG(si, r) & ~mask) | val;
3558 + W_SBREG(si, r, w);
3559 + } else {
3560 + w = (R_REG(r) & ~mask) | val;
3561 + W_REG(r, w);
3562 + }
3563 + }
3564 +
3565 + /* readback */
3566 + if (regoff >= SBCONFIGOFF)
3567 + w = R_SBREG(si, r);
3568 + else
3569 + w = R_REG(r);
3570 +
3571 + /* restore core index */
3572 + if (origidx != coreidx)
3573 + sb_setcoreidx(&si->sb, origidx);
3574 +
3575 + INTR_RESTORE(si, intr_val);
3576 + return (w);
3577 +}
3578 +
3579 +#define DWORD_ALIGN(x) (x & ~(0x03))
3580 +#define BYTE_POS(x) (x & 0x3)
3581 +#define WORD_POS(x) (x & 0x1)
3582 +
3583 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3584 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3585 +
3586 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3587 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3588 +
3589 +#define read_pci_cfg_byte(a) \
3590 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3591 +
3592 +#define read_pci_cfg_write(a) \
3593 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3594 +
3595 +
3596 +/* scan the sb enumerated space to identify all cores */
3597 +static void
3598 +BCMINITFN(sb_scan)(sb_info_t *si)
3599 +{
3600 + uint origidx;
3601 + uint i;
3602 + bool pci;
3603 + uint pciidx;
3604 + uint pcirev;
3605 +
3606 +
3607 +
3608 + /* numcores should already be set */
3609 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3610 +
3611 + /* save current core index */
3612 + origidx = sb_coreidx(&si->sb);
3613 +
3614 + si->sb.buscorerev = NOREV;
3615 + si->sb.buscoreidx = BADIDX;
3616 +
3617 + si->gpioidx = BADIDX;
3618 +
3619 + pci = FALSE;
3620 + pcirev = NOREV;
3621 + pciidx = BADIDX;
3622 +
3623 + for (i = 0; i < si->numcores; i++) {
3624 + sb_setcoreidx(&si->sb, i);
3625 + si->coreid[i] = sb_coreid(&si->sb);
3626 +
3627 + if (si->coreid[i] == SB_PCI) {
3628 + pciidx = i;
3629 + pcirev = sb_corerev(&si->sb);
3630 + pci = TRUE;
3631 + }
3632 + }