target/linux/brcm2708/patches-4.4/0029-Add-dwc_otg-driver.patch

   1 From fceeb5c989e1adda9676270cffca3225b51a15a1 Mon Sep 17 00:00:00 2001
   2 From: popcornmix <popcornmix@gmail.com>
   3 Date: Wed, 1 May 2013 19:46:17 +0100
   4 Subject: [PATCH] Add dwc_otg driver
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Signed-off-by: popcornmix <popcornmix@gmail.com>
  10
  11 usb: dwc: fix lockdep false positive
  12
  13 Signed-off-by: Kari Suvanto <karis79@gmail.com>
  14
  15 usb: dwc: fix inconsistent lock state
  16
  17 Signed-off-by: Kari Suvanto <karis79@gmail.com>
  18
  19 Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance.
  20 Thanks to Gordon and Costas
  21
  22 Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005.
  23
  24 Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh
  25
  26 Make sure we wait for the reset to finish
  27
  28 dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel
  29          memory corruption, escalating to OOPS under high USB load.
  30
  31 dwc_otg: Fix unsafe access of QTD during URB enqueue
  32
  33 In dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the
  34 transaction could complete almost immediately after the qtd was assigned
  35 to a host channel during URB enqueue, which meant the qtd pointer was no
  36 longer valid having been completed and removed. Usually, this resulted in
  37 an OOPS during URB submission. By predetermining whether transactions
  38 need to be queued or not, this unsafe pointer access is avoided.
  39
  40 This bug was only evident on the Pi model A where a device was attached
  41 that had no periodic endpoints (e.g. USB pendrive or some wlan devices).
  42
  43 dwc_otg: Fix incorrect URB allocation error handling
  44
  45 If the memory allocation for a dwc_otg_urb failed, the kernel would OOPS
  46 because for some reason a member of the *unallocated* struct was set to
  47 zero. Error handling changed to fail correctly.
  48
  49 dwc_otg: fix potential use-after-free case in interrupt handler
  50
  51 If a transaction had previously aborted, certain interrupts are
  52 enabled to track error counts and reset where necessary. On IN
  53 endpoints the host generates an ACK interrupt near-simultaneously
  54 with completion of transfer. In the case where this transfer had
  55 previously had an error, this results in a use-after-free on
  56 the QTD memory space with a 1-byte length being overwritten to
  57 0x00.
  58
  59 dwc_otg: add handling of SPLIT transaction data toggle errors
  60
  61 Previously a data toggle error on packets from a USB1.1 device behind
  62 a TT would result in the Pi locking up as the driver never handled
  63 the associated interrupt. Patch adds basic retry mechanism and
  64 interrupt acknowledgement to cater for either a chance toggle error or
  65 for devices that have a broken initial toggle state (FT8U232/FT232BM).
  66
  67 dwc_otg: implement tasklet for returning URBs to usbcore hcd layer
  68
  69 The dwc_otg driver interrupt handler for transfer completion will spend
  70 a very long time with interrupts disabled when a URB is completed -
  71 this is because usb_hcd_giveback_urb is called from within the handler
  72 which for a USB device driver with complicated processing (e.g. webcam)
  73 will take an exorbitant amount of time to complete. This results in
  74 missed completion interrupts for other USB packets which lead to them
  75 being dropped due to microframe overruns.
  76
  77 This patch splits returning the URB to the usb hcd layer into a
  78 high-priority tasklet. This will have most benefit for isochronous IN
  79 transfers but will also have incidental benefit where multiple periodic
  80 devices are active at once.
  81
  82 dwc_otg: fix NAK holdoff and allow on split transactions only
  83
  84 This corrects a bug where if a single active non-periodic endpoint
  85 had at least one transaction in its qh, on frnum == MAX_FRNUM the qh
  86 would get skipped and never get queued again. This would result in
  87 a silent device until error detection (automatic or otherwise) would
  88 either reset the device or flush and requeue the URBs.
  89
  90 Additionally the NAK holdoff was enabled for all transactions - this
  91 would potentially stall a HS endpoint for 1ms if a previous error state
  92 enabled this interrupt and the next response was a NAK. Fix so that
  93 only split transactions get held off.
  94
  95 dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler
  96
  97 usb_hcd_unlink_urb_from_ep must be called with the HCD lock held.  Calling it
  98 asynchronously in the tasklet was not safe (regression in
  99 c4564d4a1a0a9b10d4419e48239f5d99e88d2667).
 100
 101 This change unlinks it from the endpoint prior to queueing it for handling in
 102 the tasklet, and also adds a check to ensure the urb is OK to be unlinked
 103 before doing so.
 104
 105 NULL pointer dereference kernel oopses had been observed in usb_hcd_giveback_urb
 106 when a USB device was unplugged/replugged during data transfer.  This effect
 107 was reproduced using automated USB port power control, hundreds of replug
 108 events were performed during active transfers to confirm that the problem was
 109 eliminated.
 110
 111 USB fix using a FIQ to implement split transactions
 112
 113 This commit adds a FIQ implementaion that schedules
 114 the split transactions using a FIQ so we don't get
 115 held off by the interrupt latency of Linux
 116
 117 dwc_otg: fix device attributes and avoid kernel warnings on boot
 118
 119 dcw_otg: avoid logging function that can cause panics
 120
 121 See: https://github.com/raspberrypi/firmware/issues/21
 122 Thanks to cleverca22 for fix
 123
 124 dwc_otg: mask correct interrupts after transaction error recovery
 125
 126 The dwc_otg driver will unmask certain interrupts on a transaction
 127 that previously halted in the error state in order to reset the
 128 QTD error count. The various fine-grained interrupt handlers do not
 129 consider that other interrupts besides themselves were unmasked.
 130
 131 By disabling the two other interrupts only ever enabled in DMA mode
 132 for this purpose, we can avoid unnecessary function calls in the
 133 IRQ handler. This will also prevent an unneccesary FIQ interrupt
 134 from being generated if the FIQ is enabled.
 135
 136 dwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ
 137
 138 In the case of a transaction to a device that had previously aborted
 139 due to an error, several interrupts are enabled to reset the error
 140 count when a device responds. This has the side-effect of making the
 141 FIQ thrash because the hardware will generate multiple instances of
 142 a NAK on an IN bulk/interrupt endpoint and multiple instances of ACK
 143 on an OUT bulk/interrupt endpoint. Make the FIQ mask and clear the
 144 associated interrupts.
 145
 146 Additionally, on non-split transactions make sure that only unmasked
 147 interrupts are cleared. This caused a hard-to-trigger but serious
 148 race condition when you had the combination of an endpoint awaiting
 149 error recovery and a transaction completed on an endpoint - due to
 150 the sequencing and timing of interrupts generated by the dwc_otg core,
 151 it was possible to confuse the IRQ handler.
 152
 153 Fix function tracing
 154
 155 dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue
 156
 157 dwc_otg: prevent OOPSes during device disconnects
 158
 159 The dwc_otg_urb_enqueue function is thread-unsafe. In particular the
 160 access of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and
 161 friends does not occur within a critical section and so if a device
 162 was unplugged during activity there was a high chance that the
 163 usbcore hub_thread would try to disable the endpoint with partially-
 164 formed entries in the URB queue. This would result in BUG() or null
 165 pointer dereferences.
 166
 167 Fix so that access of urb->hcpriv, enqueuing to the hardware and
 168 adding to usbcore endpoint URB lists is contained within a single
 169 critical section.
 170
 171 dwc_otg: prevent BUG() in TT allocation if hub address is > 16
 172
 173 A fixed-size array is used to track TT allocation. This was
 174 previously set to 16 which caused a crash because
 175 dwc_otg_hcd_allocate_port would read past the end of the array.
 176
 177 This was hit if a hub was plugged in which enumerated as addr > 16,
 178 due to previous device resets or unplugs.
 179
 180 Also add #ifdef FIQ_DEBUG around hcd->hub_port_alloc[], which grows
 181 to a large size if 128 hub addresses are supported. This field is
 182 for debug only for tracking which frame an allocate happened in.
 183
 184 dwc_otg: make channel halts with unknown state less damaging
 185
 186 If the IRQ received a channel halt interrupt through the FIQ
 187 with no other bits set, the IRQ would not release the host
 188 channel and never complete the URB.
 189
 190 Add catchall handling to treat as a transaction error and retry.
 191
 192 dwc_otg: fiq_split: use TTs with more granularity
 193
 194 This fixes certain issues with split transaction scheduling.
 195
 196 - Isochronous multi-packet OUT transactions now hog the TT until
 197   they are completed - this prevents hubs aborting transactions
 198   if they get a periodic start-split out-of-order
 199 - Don't perform TT allocation on non-periodic endpoints - this
 200   allows simultaneous use of the TT's bulk/control and periodic
 201   transaction buffers
 202
 203 This commit will mainly affect USB audio playback.
 204
 205 dwc_otg: fix potential sleep while atomic during urb enqueue
 206
 207 Fixes a regression introduced with eb1b482a. Kmalloc called from
 208 dwc_otg_hcd_qtd_add / dwc_otg_hcd_qtd_create did not always have
 209 the GPF_ATOMIC flag set. Force this flag when inside the larger
 210 critical section.
 211
 212 dwc_otg: make fiq_split_enable imply fiq_fix_enable
 213
 214 Failing to set up the FIQ correctly would result in
 215 "IRQ 32: nobody cared" errors in dmesg.
 216
 217 dwc_otg: prevent crashes on host port disconnects
 218
 219 Fix several issues resulting in crashes or inconsistent state
 220 if a Model A root port was disconnected.
 221
 222 - Clean up queue heads properly in kill_urbs_in_qh_list by
 223   removing the empty QHs from the schedule lists
 224 - Set the halt status properly to prevent IRQ handlers from
 225   using freed memory
 226 - Add fiq_split related cleanup for saved registers
 227 - Make microframe scheduling reclaim host channels if
 228   active during a disconnect
 229 - Abort URBs with -ESHUTDOWN status response, informing
 230   device drivers so they respond in a more correct fashion
 231   and don't try to resubmit URBs
 232 - Prevent IRQ handlers from attempting to handle channel
 233   interrupts if the associated URB was dequeued (and the
 234   driver state was cleared)
 235
 236 dwc_otg: prevent leaking URBs during enqueue
 237
 238 A dwc_otg_urb would get leaked if the HCD enqueue function
 239 failed for any reason. Free the URB at the appropriate points.
 240
 241 dwc_otg: Enable NAK holdoff for control split transactions
 242
 243 Certain low-speed devices take a very long time to complete a
 244 data or status stage of a control transaction, producing NAK
 245 responses until they complete internal processing - the USB2.0
 246 spec limit is up to 500mS. This causes the same type of interrupt
 247 storm as seen with USB-serial dongles prior to c8edb238.
 248
 249 In certain circumstances, usually while booting, this interrupt
 250 storm could cause SD card timeouts.
 251
 252 dwc_otg: Fix for occasional lockup on boot when doing a USB reset
 253
 254 dwc_otg: Don't issue traffic to LS devices in FS mode
 255
 256 Issuing low-speed packets when the root port is in full-speed mode
 257 causes the root port to stop responding. Explicitly fail when
 258 enqueuing URBs to a LS endpoint on a FS bus.
 259
 260 Fix ARM architecture issue with local_irq_restore()
 261
 262 If local_fiq_enable() is called before a local_irq_restore(flags) where
 263 the flags variable has the F bit set, the FIQ will be erroneously disabled.
 264
 265 Fixup arch_local_irq_restore to avoid trampling the F bit in CPSR.
 266
 267 Also fix some of the hacks previously implemented for previous dwc_otg
 268 incarnations.
 269
 270 dwc_otg: fiq_fsm: Base commit for driver rewrite
 271
 272 This commit removes the previous FIQ fixes entirely and adds fiq_fsm.
 273
 274 This rewrite features much more complete support for split transactions
 275 and takes into account several OTG hardware bugs. High-speed
 276 isochronous transactions are also capable of being performed by fiq_fsm.
 277
 278 All driver options have been removed and replaced with:
 279   - dwc_otg.fiq_enable (bool)
 280   - dwc_otg.fiq_fsm_enable (bool)
 281   - dwc_otg.fiq_fsm_mask (bitmask)
 282   - dwc_otg.nak_holdoff (unsigned int)
 283
 284 Defaults are specified such that fiq_fsm behaves similarly to the
 285 previously implemented FIQ fixes.
 286
 287 fiq_fsm: Push error recovery into the FIQ when fiq_fsm is used
 288
 289 If the transfer associated with a QTD failed due to a bus error, the HCD
 290 would retry the transfer up to 3 times (implementing the USB2.0
 291 three-strikes retry in software).
 292
 293 Due to the masking mechanism used by fiq_fsm, it is only possible to pass
 294 a single interrupt through to the HCD per-transfer.
 295
 296 In this instance host channels would fall off the radar because the error
 297 reset would function, but the subsequent channel halt would be lost.
 298
 299 Push the error count reset into the FIQ handler.
 300
 301 fiq_fsm: Implement timeout mechanism
 302
 303 For full-speed endpoints with a large packet size, interrupt latency
 304 runs the risk of the FIQ starting a transaction too late in a full-speed
 305 frame. If the device is still transmitting data when EOF2 for the
 306 downstream frame occurs, the hub will disable the port. This change is
 307 not reflected in the hub status endpoint and the device becomes
 308 unresponsive.
 309
 310 Prevent high-bandwidth transactions from being started too late in a
 311 frame. The mechanism is not guaranteed: a combination of bit stuffing
 312 and hub latency may still result in a device overrunning.
 313
 314 fiq_fsm: fix bounce buffer utilisation for Isochronous OUT
 315
 316 Multi-packet isochronous OUT transactions were subject to a few bounday
 317 bugs. Fix them.
 318
 319 Audio playback is now much more robust: however, an issue stands with
 320 devices that have adaptive sinks - ALSA plays samples too fast.
 321
 322 dwc_otg: Return full-speed frame numbers in HS mode
 323
 324 The frame counter increments on every *microframe* in high-speed mode.
 325 Most device drivers expect this number to be in full-speed frames - this
 326 caused considerable confusion to e.g. snd_usb_audio which uses the
 327 frame counter to estimate the number of samples played.
 328
 329 fiq_fsm: save PID on completion of interrupt OUT transfers
 330
 331 Also add edge case handling for interrupt transports.
 332
 333 Note that for periodic split IN, data toggles are unimplemented in the
 334 OTG host hardware - it unconditionally accepts any PID.
 335
 336 fiq_fsm: add missing case for fiq_fsm_tt_in_use()
 337
 338 Certain combinations of bitrate and endpoint activity could
 339 result in a periodic transaction erroneously getting started
 340 while the previous Isochronous OUT was still active.
 341
 342 fiq_fsm: clear hcintmsk for aborted transactions
 343
 344 Prevents the FIQ from erroneously handling interrupts
 345 on a timed out channel.
 346
 347 fiq_fsm: enable by default
 348
 349 fiq_fsm: fix dequeues for non-periodic split transactions
 350
 351 If a dequeue happened between the SSPLIT and CSPLIT phases of the
 352 transaction, the HCD would never receive an interrupt.
 353
 354 fiq_fsm: Disable by default
 355
 356 fiq_fsm: Handle HC babble errors
 357
 358 The HCTSIZ transfer size field raises a babble interrupt if
 359 the counter wraps. Handle the resulting interrupt in this case.
 360
 361 dwc_otg: fix interrupt registration for fiq_enable=0
 362
 363 Additionally make the module parameter conditional for wherever
 364 hcd->fiq_state is touched.
 365
 366 fiq_fsm: Enable by default
 367
 368 dwc_otg: Fix various issues with root port and transaction errors
 369
 370 Process the host port interrupts correctly (and don't trample them).
 371 Root port hotplug now functional again.
 372
 373 Fix a few thinkos with the transaction error passthrough for fiq_fsm.
 374
 375 fiq_fsm: Implement hack for Split Interrupt transactions
 376
 377 Hubs aren't too picky about which endpoint we send Control type split
 378 transactions to. By treating Interrupt transfers as Control, it is
 379 possible to use the non-periodic queue in the OTG core as well as the
 380 non-periodic FIFOs in the hub itself. This massively reduces the
 381 microframe exclusivity/contention that periodic split transactions
 382 otherwise have to enforce.
 383
 384 It goes without saying that this is a fairly egregious USB specification
 385 violation, but it works.
 386
 387 Original idea by Hans Petter Selasky @ FreeBSD.org.
 388
 389 dwc_otg: FIQ support on SMP. Set up FIQ stack and handler on Core 0 only.
 390
 391 dwc_otg: introduce fiq_fsm_spin(un|)lock()
 392
 393 SMP safety for the FIQ relies on register read-modify write cycles being
 394 completed in the correct order. Several places in the DWC code modify
 395 registers also touched by the FIQ. Protect these by a bare-bones lock
 396 mechanism.
 397
 398 This also makes it possible to run the FIQ and IRQ handlers on different
 399 cores.
 400
 401 fiq_fsm: fix build on bcm2708 and bcm2709 platforms
 402
 403 dwc_otg: put some barriers back where they should be for UP
 404
 405 bcm2709/dwc_otg: Setup FIQ on core 1 if >1 core active
 406
 407 dwc_otg: fixup read-modify-write in critical paths
 408
 409 Be more careful about read-modify-write on registers that the FIQ
 410 also touches.
 411
 412 Guard fiq_fsm_spin_lock with fiq_enable check
 413
 414 fiq_fsm: Falling out of the state machine isn't fatal
 415
 416 This edge case can be hit if the port is disabled while the FIQ is
 417 in the middle of a transaction. Make the effects less severe.
 418
 419 Also get rid of the useless return value.
 420
 421 squash: dwc_otg: Allow to build without SMP
 422
 423 usb: core: make overcurrent messages more prominent
 424
 425 Hub overcurrent messages are more serious than "debug". Increase loglevel.
 426
 427 usb: dwc_otg: Don't use dma_to_virt()
 428
 429 Commit 6ce0d20 changes dma_to_virt() which breaks this driver.
 430 Open code the old dma_to_virt() implementation to work around this.
 431
 432 Limit the use of __bus_to_virt() to cases where transfer_buffer_length
 433 is set and transfer_buffer is not set. This is done to increase the
 434 chance that this driver will also work on ARCH_BCM2835.
 435
 436 transfer_buffer should not be NULL if the length is set, but the
 437 comment in the code indicates that there are situations where this
 438 might happen. drivers/usb/isp1760/isp1760-hcd.c also has a similar
 439 comment pointing to a possible: 'usb storage / SCSI bug'.
 440
 441 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
 442
 443 dwc_otg: Fix crash when fiq_enable=0
 444
 445 dwc_otg: fiq_fsm: Make high-speed isochronous strided transfers work properly
 446
 447 Certain low-bandwidth high-speed USB devices (specialist audio devices,
 448 compressed-frame webcams) have packet intervals > 1 microframe.
 449
 450 Stride these transfers in the FIQ by using the start-of-frame interrupt
 451 to restart the channel at the right time.
 452
 453 dwc_otg: Force host mode to fix incorrect compute module boards
 454
 455 dwc_otg: Add ARCH_BCM2835 support
 456
 457 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
 458
 459 dwc_otg: Simplify FIQ irq number code
 460
 461 Dropping ATAGS means we can simplify the FIQ irq number code.
 462 Also add error checking on the returned irq number.
 463
 464 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
 465
 466 dwc_otg: Remove duplicate gadget probe/unregister function
 467 ---
 468  arch/arm/include/asm/irqflags.h                    |   16 +-
 469  arch/arm/kernel/fiqasm.S                           |    4 +
 470  drivers/usb/Makefile                               |    1 +
 471  drivers/usb/core/generic.c                         |    1 +
 472  drivers/usb/core/hub.c                             |    2 +-
 473  drivers/usb/core/message.c                         |   79 +
 474  drivers/usb/core/otg_whitelist.h                   |  114 +-
 475  drivers/usb/gadget/file_storage.c                  | 3676 ++++++++++
 476  drivers/usb/host/Kconfig                           |   13 +
 477  drivers/usb/host/Makefile                          |    2 +
 478  drivers/usb/host/dwc_common_port/Makefile          |   58 +
 479  drivers/usb/host/dwc_common_port/Makefile.fbsd     |   17 +
 480  drivers/usb/host/dwc_common_port/Makefile.linux    |   49 +
 481  drivers/usb/host/dwc_common_port/changes.txt       |  174 +
 482  drivers/usb/host/dwc_common_port/doc/doxygen.cfg   |  270 +
 483  drivers/usb/host/dwc_common_port/dwc_cc.c          |  532 ++
 484  drivers/usb/host/dwc_common_port/dwc_cc.h          |  224 +
 485  drivers/usb/host/dwc_common_port/dwc_common_fbsd.c | 1308 ++++
 486  .../usb/host/dwc_common_port/dwc_common_linux.c    | 1433 ++++
 487  drivers/usb/host/dwc_common_port/dwc_common_nbsd.c | 1275 ++++
 488  drivers/usb/host/dwc_common_port/dwc_crypto.c      |  308 +
 489  drivers/usb/host/dwc_common_port/dwc_crypto.h      |  111 +
 490  drivers/usb/host/dwc_common_port/dwc_dh.c          |  291 +
 491  drivers/usb/host/dwc_common_port/dwc_dh.h          |  106 +
 492  drivers/usb/host/dwc_common_port/dwc_list.h        |  594 ++
 493  drivers/usb/host/dwc_common_port/dwc_mem.c         |  245 +
 494  drivers/usb/host/dwc_common_port/dwc_modpow.c      |  636 ++
 495  drivers/usb/host/dwc_common_port/dwc_modpow.h      |   34 +
 496  drivers/usb/host/dwc_common_port/dwc_notifier.c    |  319 +
 497  drivers/usb/host/dwc_common_port/dwc_notifier.h    |  122 +
 498  drivers/usb/host/dwc_common_port/dwc_os.h          | 1276 ++++
 499  drivers/usb/host/dwc_common_port/usb.h             |  946 +++
 500  drivers/usb/host/dwc_otg/Makefile                  |   82 +
 501  drivers/usb/host/dwc_otg/doc/doxygen.cfg           |  224 +
 502  drivers/usb/host/dwc_otg/dummy_audio.c             | 1575 +++++
 503  drivers/usb/host/dwc_otg/dwc_cfi_common.h          |  142 +
 504  drivers/usb/host/dwc_otg/dwc_otg_adp.c             |  854 +++
 505  drivers/usb/host/dwc_otg/dwc_otg_adp.h             |   80 +
 506  drivers/usb/host/dwc_otg/dwc_otg_attr.c            | 1210 ++++
 507  drivers/usb/host/dwc_otg/dwc_otg_attr.h            |   89 +
 508  drivers/usb/host/dwc_otg/dwc_otg_cfi.c             | 1876 +++++
 509  drivers/usb/host/dwc_otg/dwc_otg_cfi.h             |  320 +
 510  drivers/usb/host/dwc_otg/dwc_otg_cil.c             | 7141 ++++++++++++++++++++
 511  drivers/usb/host/dwc_otg/dwc_otg_cil.h             | 1464 ++++
 512  drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c        | 1594 +++++
 513  drivers/usb/host/dwc_otg/dwc_otg_core_if.h         |  705 ++
 514  drivers/usb/host/dwc_otg/dwc_otg_dbg.h             |  117 +
 515  drivers/usb/host/dwc_otg/dwc_otg_driver.c          | 1757 +++++
 516  drivers/usb/host/dwc_otg/dwc_otg_driver.h          |   86 +
 517  drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c         | 1355 ++++
 518  drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h         |  370 +
 519  drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S        |   80 +
 520  drivers/usb/host/dwc_otg/dwc_otg_hcd.c             | 4257 ++++++++++++
 521  drivers/usb/host/dwc_otg/dwc_otg_hcd.h             |  862 +++
 522  drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c        | 1132 ++++
 523  drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h          |  417 ++
 524  drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c        | 2714 ++++++++
 525  drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c       | 1005 +++
 526  drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c       |  957 +++
 527  drivers/usb/host/dwc_otg/dwc_otg_os_dep.h          |  188 +
 528  drivers/usb/host/dwc_otg/dwc_otg_pcd.c             | 2712 ++++++++
 529  drivers/usb/host/dwc_otg/dwc_otg_pcd.h             |  266 +
 530  drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h          |  360 +
 531  drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c        | 5147 ++++++++++++++
 532  drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c       | 1280 ++++
 533  drivers/usb/host/dwc_otg/dwc_otg_regs.h            | 2550 +++++++
 534  drivers/usb/host/dwc_otg/test/Makefile             |   16 +
 535  drivers/usb/host/dwc_otg/test/dwc_otg_test.pm      |  337 +
 536  drivers/usb/host/dwc_otg/test/test_mod_param.pl    |  133 +
 537  drivers/usb/host/dwc_otg/test/test_sysfs.pl        |  193 +
 538  70 files changed, 59867 insertions(+), 16 deletions(-)
 539  create mode 100644 drivers/usb/gadget/file_storage.c
 540  create mode 100644 drivers/usb/host/dwc_common_port/Makefile
 541  create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd
 542  create mode 100644 drivers/usb/host/dwc_common_port/Makefile.linux
 543  create mode 100644 drivers/usb/host/dwc_common_port/changes.txt
 544  create mode 100644 drivers/usb/host/dwc_common_port/doc/doxygen.cfg
 545  create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.c
 546  create mode 100644 drivers/usb/host/dwc_common_port/dwc_cc.h
 547  create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
 548  create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_linux.c
 549  create mode 100644 drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
 550  create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.c
 551  create mode 100644 drivers/usb/host/dwc_common_port/dwc_crypto.h
 552  create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.c
 553  create mode 100644 drivers/usb/host/dwc_common_port/dwc_dh.h
 554  create mode 100644 drivers/usb/host/dwc_common_port/dwc_list.h
 555  create mode 100644 drivers/usb/host/dwc_common_port/dwc_mem.c
 556  create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.c
 557  create mode 100644 drivers/usb/host/dwc_common_port/dwc_modpow.h
 558  create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.c
 559  create mode 100644 drivers/usb/host/dwc_common_port/dwc_notifier.h
 560  create mode 100644 drivers/usb/host/dwc_common_port/dwc_os.h
 561  create mode 100644 drivers/usb/host/dwc_common_port/usb.h
 562  create mode 100644 drivers/usb/host/dwc_otg/Makefile
 563  create mode 100644 drivers/usb/host/dwc_otg/doc/doxygen.cfg
 564  create mode 100644 drivers/usb/host/dwc_otg/dummy_audio.c
 565  create mode 100644 drivers/usb/host/dwc_otg/dwc_cfi_common.h
 566  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.c
 567  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_adp.h
 568  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.c
 569  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_attr.h
 570  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.c
 571  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cfi.h
 572  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.c
 573  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil.h
 574  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
 575  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_core_if.h
 576  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_dbg.h
 577  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.c
 578  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_driver.h
 579  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
 580  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
 581  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
 582  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.c
 583  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd.h
 584  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
 585  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
 586  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
 587  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
 588  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
 589  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
 590  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.c
 591  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd.h
 592  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
 593  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
 594  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
 595  create mode 100644 drivers/usb/host/dwc_otg/dwc_otg_regs.h
 596  create mode 100644 drivers/usb/host/dwc_otg/test/Makefile
 597  create mode 100644 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
 598  create mode 100644 drivers/usb/host/dwc_otg/test/test_mod_param.pl
 599  create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl
 600
 601 --- a/arch/arm/include/asm/irqflags.h
 602 +++ b/arch/arm/include/asm/irqflags.h
 603 @@ -162,13 +162,23 @@ static inline unsigned long arch_local_s
 604  }
 605
 606  /*
 607 - * restore saved IRQ & FIQ state
 608 + * restore saved IRQ state
 609   */
 610  #define arch_local_irq_restore arch_local_irq_restore
 611  static inline void arch_local_irq_restore(unsigned long flags)
 612  {
 613 -       asm volatile(
 614 -               "       msr     " IRQMASK_REG_NAME_W ", %0      @ local_irq_restore"
 615 +       unsigned long temp = 0;
 616 +       flags &= ~(1 << 6);
 617 +       asm volatile (
 618 +               " mrs %0, cpsr"
 619 +               : "=r" (temp)
 620 +               :
 621 +               : "memory", "cc");
 622 +               /* Preserve FIQ bit */
 623 +               temp &= (1 << 6);
 624 +               flags = flags | temp;
 625 +       asm volatile (
 626 +               "    msr    cpsr_c, %0    @ local_irq_restore"
 627                 :
 628                 : "r" (flags)
 629                 : "memory", "cc");
 630 --- a/arch/arm/kernel/fiqasm.S
 631 +++ b/arch/arm/kernel/fiqasm.S
 632 @@ -47,3 +47,7 @@ ENTRY(__get_fiq_regs)
 633         mov     r0, r0          @ avoid hazard prior to ARMv4
 634         ret     lr
 635  ENDPROC(__get_fiq_regs)
 636 +
 637 +ENTRY(__FIQ_Branch)
 638 +       mov pc, r8
 639 +ENDPROC(__FIQ_Branch)
 640 --- a/drivers/usb/Makefile
 641 +++ b/drivers/usb/Makefile
 642 @@ -7,6 +7,7 @@
 643  obj-$(CONFIG_USB)              += core/
 644  obj-$(CONFIG_USB_SUPPORT)      += phy/
 645
 646 +obj-$(CONFIG_USB_DWCOTG)       += host/
 647  obj-$(CONFIG_USB_DWC3)         += dwc3/
 648  obj-$(CONFIG_USB_DWC2)         += dwc2/
 649  obj-$(CONFIG_USB_ISP1760)      += isp1760/
 650 --- a/drivers/usb/core/generic.c
 651 +++ b/drivers/usb/core/generic.c
 652 @@ -152,6 +152,7 @@ int usb_choose_configuration(struct usb_
 653                 dev_warn(&udev->dev,
 654                         "no configuration chosen from %d choice%s\n",
 655                         num_configs, plural(num_configs));
 656 +               dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA);
 657         }
 658         return i;
 659  }
 660 --- a/drivers/usb/core/hub.c
 661 +++ b/drivers/usb/core/hub.c
 662 @@ -4967,7 +4967,7 @@ static void port_event(struct usb_hub *h
 663         if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
 664                 u16 status = 0, unused;
 665
 666 -               dev_dbg(&port_dev->dev, "over-current change\n");
 667 +               dev_notice(&port_dev->dev, "over-current change\n");
 668                 usb_clear_port_feature(hdev, port1,
 669                                 USB_PORT_FEAT_C_OVER_CURRENT);
 670                 msleep(100);    /* Cool down */
 671 --- a/drivers/usb/core/message.c
 672 +++ b/drivers/usb/core/message.c
 673 @@ -1909,6 +1909,85 @@ free_interfaces:
 674         if (cp->string == NULL &&
 675                         !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
 676                 cp->string = usb_cache_string(dev, cp->desc.iConfiguration);
 677 +/* Uncomment this define to enable the HS Electrical Test support */
 678 +#define DWC_HS_ELECT_TST 1
 679 +#ifdef DWC_HS_ELECT_TST
 680 +               /* Here we implement the HS Electrical Test support. The
 681 +                * tester uses a vendor ID of 0x1A0A to indicate we should
 682 +                * run a special test sequence. The product ID tells us
 683 +                * which sequence to run. We invoke the test sequence by
 684 +                * sending a non-standard SetFeature command to our root
 685 +                * hub port. Our dwc_otg_hcd_hub_control() routine will
 686 +                * recognize the command and perform the desired test
 687 +                * sequence.
 688 +                */
 689 +               if (dev->descriptor.idVendor == 0x1A0A) {
 690 +                       /* HSOTG Electrical Test */
 691 +                       dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n");
 692 +
 693 +                       if (dev->bus && dev->bus->root_hub) {
 694 +                               struct usb_device *hdev = dev->bus->root_hub;
 695 +                               dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct);
 696 +
 697 +                               switch (dev->descriptor.idProduct) {
 698 +                               case 0x0101:    /* TEST_SE0_NAK */
 699 +                                       dev_warn(&dev->dev, "TEST_SE0_NAK\n");
 700 +                                       usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 701 +                                                       USB_REQ_SET_FEATURE, USB_RT_PORT,
 702 +                                                       USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ);
 703 +                                       break;
 704 +
 705 +                               case 0x0102:    /* TEST_J */
 706 +                                       dev_warn(&dev->dev, "TEST_J\n");
 707 +                                       usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 708 +                                                       USB_REQ_SET_FEATURE, USB_RT_PORT,
 709 +                                                       USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ);
 710 +                                       break;
 711 +
 712 +                               case 0x0103:    /* TEST_K */
 713 +                                       dev_warn(&dev->dev, "TEST_K\n");
 714 +                                       usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 715 +                                                       USB_REQ_SET_FEATURE, USB_RT_PORT,
 716 +                                                       USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ);
 717 +                                       break;
 718 +
 719 +                               case 0x0104:    /* TEST_PACKET */
 720 +                                       dev_warn(&dev->dev, "TEST_PACKET\n");
 721 +                                       usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 722 +                                                       USB_REQ_SET_FEATURE, USB_RT_PORT,
 723 +                                                       USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ);
 724 +                                       break;
 725 +
 726 +                               case 0x0105:    /* TEST_FORCE_ENABLE */
 727 +                                       dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n");
 728 +                                       usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 729 +                                                       USB_REQ_SET_FEATURE, USB_RT_PORT,
 730 +                                                       USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ);
 731 +                                       break;
 732 +
 733 +                               case 0x0106:    /* HS_HOST_PORT_SUSPEND_RESUME */
 734 +                                       dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n");
 735 +                                       usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 736 +                                                       USB_REQ_SET_FEATURE, USB_RT_PORT,
 737 +                                                       USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ);
 738 +                                       break;
 739 +
 740 +                               case 0x0107:    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
 741 +                                       dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n");
 742 +                                       usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 743 +                                                       USB_REQ_SET_FEATURE, USB_RT_PORT,
 744 +                                                       USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ);
 745 +                                       break;
 746 +
 747 +                               case 0x0108:    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
 748 +                                       dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n");
 749 +                                       usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
 750 +                                                       USB_REQ_SET_FEATURE, USB_RT_PORT,
 751 +                                                       USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ);
 752 +                               }
 753 +                       }
 754 +               }
 755 +#endif /* DWC_HS_ELECT_TST */
 756
 757         /* Now that the interfaces are installed, re-enable LPM. */
 758         usb_unlocked_enable_lpm(dev);
 759 --- a/drivers/usb/core/otg_whitelist.h
 760 +++ b/drivers/usb/core/otg_whitelist.h
 761 @@ -19,33 +19,82 @@
 762  static struct usb_device_id whitelist_table[] = {
 763
 764  /* hubs are optional in OTG, but very handy ... */
 765 +#define CERT_WITHOUT_HUBS
 766 +#if defined(CERT_WITHOUT_HUBS)
 767 +{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/
 768 +#else
 769  { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
 770  { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
 771 +{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), },
 772 +#endif
 773
 774  #ifdef CONFIG_USB_PRINTER              /* ignoring nonstatic linkage! */
 775  /* FIXME actually, printers are NOT supposed to use device classes;
 776   * they're supposed to use interface classes...
 777   */
 778 -{ USB_DEVICE_INFO(7, 1, 1) },
 779 -{ USB_DEVICE_INFO(7, 1, 2) },
 780 -{ USB_DEVICE_INFO(7, 1, 3) },
 781 +//{ USB_DEVICE_INFO(7, 1, 1) },
 782 +//{ USB_DEVICE_INFO(7, 1, 2) },
 783 +//{ USB_DEVICE_INFO(7, 1, 3) },
 784  #endif
 785
 786  #ifdef CONFIG_USB_NET_CDCETHER
 787  /* Linux-USB CDC Ethernet gadget */
 788 -{ USB_DEVICE(0x0525, 0xa4a1), },
 789 +//{ USB_DEVICE(0x0525, 0xa4a1), },
 790  /* Linux-USB CDC Ethernet + RNDIS gadget */
 791 -{ USB_DEVICE(0x0525, 0xa4a2), },
 792 +//{ USB_DEVICE(0x0525, 0xa4a2), },
 793  #endif
 794
 795  #if    defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
 796  /* gadget zero, for testing */
 797 -{ USB_DEVICE(0x0525, 0xa4a0), },
 798 +//{ USB_DEVICE(0x0525, 0xa4a0), },
 799  #endif
 800
 801 +/* OPT Tester */
 802 +{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */
 803 +{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */
 804 +{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */
 805 +{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */
 806 +{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */
 807 +{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME  */
 808 +{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */
 809 +{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */
 810 +
 811 +/* Sony cameras */
 812 +{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), },
 813 +
 814 +/* Memory Devices */
 815 +//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */
 816 +//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */
 817 +//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */
 818 +//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD  */
 819 +{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/
 820 +//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */
 821 +
 822 +/* HP Printers */
 823 +//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */
 824 +//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */
 825 +
 826 +/* Speakers */
 827 +//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */
 828 +//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */
 829 +
 830  { }    /* Terminating entry */
 831  };
 832
 833 +static inline void report_errors(struct usb_device *dev)
 834 +{
 835 +       /* OTG MESSAGE: report errors here, customize to match your product */
 836 +       dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n",
 837 +                le16_to_cpu(dev->descriptor.idVendor),
 838 +                le16_to_cpu(dev->descriptor.idProduct));
 839 +        if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){
 840 +                dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n");
 841 +        } else {
 842 +                dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n");
 843 +        }
 844 +}
 845 +
 846 +
 847  static int is_targeted(struct usb_device *dev)
 848  {
 849         struct usb_device_id    *id = whitelist_table;
 850 @@ -95,16 +144,57 @@ static int is_targeted(struct usb_device
 851                         continue;
 852
 853                 return 1;
 854 -       }
 855 +               /* NOTE: can't use usb_match_id() since interface caches
 856 +                * aren't set up yet. this is cut/paste from that code.
 857 +                */
 858 +               for (id = whitelist_table; id->match_flags; id++) {
 859 +#ifdef DEBUG
 860 +                       dev_dbg(&dev->dev,
 861 +                               "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n",
 862 +                               id->idVendor,
 863 +                               id->idProduct,
 864 +                               id->bDeviceClass,
 865 +                               id->bDeviceSubClass,
 866 +                               id->bDeviceProtocol);
 867 +#endif
 868
 869 -       /* add other match criteria here ... */
 870 +                       if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) &&
 871 +                           id->idVendor != le16_to_cpu(dev->descriptor.idVendor))
 872 +                               continue;
 873 +
 874 +                       if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) &&
 875 +                           id->idProduct != le16_to_cpu(dev->descriptor.idProduct))
 876 +                               continue;
 877 +
 878 +                       /* No need to test id->bcdDevice_lo != 0, since 0 is never
 879 +                          greater than any unsigned number. */
 880 +                       if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) &&
 881 +                           (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice)))
 882 +                               continue;
 883 +
 884 +                       if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) &&
 885 +                           (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice)))
 886 +                               continue;
 887 +
 888 +                       if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) &&
 889 +                           (id->bDeviceClass != dev->descriptor.bDeviceClass))
 890 +                               continue;
 891 +
 892 +                       if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) &&
 893 +                           (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass))
 894 +                               continue;
 895 +
 896 +                       if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) &&
 897 +                           (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
 898 +                               continue;
 899
 900 +                       return 1;
 901 +               }
 902 +       }
 903
 904 -       /* OTG MESSAGE: report errors here, customize to match your product */
 905 -       dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
 906 -               le16_to_cpu(dev->descriptor.idVendor),
 907 -               le16_to_cpu(dev->descriptor.idProduct));
 908 +       /* add other match criteria here ... */
 909
 910 +       report_errors(dev);
 911         return 0;
 912  }
 913
 914 --- /dev/null
 915 +++ b/drivers/usb/gadget/file_storage.c
 916 @@ -0,0 +1,3676 @@
 917 +/*
 918 + * file_storage.c -- File-backed USB Storage Gadget, for USB development
 919 + *
 920 + * Copyright (C) 2003-2008 Alan Stern
 921 + * All rights reserved.
 922 + *
 923 + * Redistribution and use in source and binary forms, with or without
 924 + * modification, are permitted provided that the following conditions
 925 + * are met:
 926 + * 1. Redistributions of source code must retain the above copyright
 927 + *    notice, this list of conditions, and the following disclaimer,
 928 + *    without modification.
 929 + * 2. Redistributions in binary form must reproduce the above copyright
 930 + *    notice, this list of conditions and the following disclaimer in the
 931 + *    documentation and/or other materials provided with the distribution.
 932 + * 3. The names of the above-listed copyright holders may not be used
 933 + *    to endorse or promote products derived from this software without
 934 + *    specific prior written permission.
 935 + *
 936 + * ALTERNATIVELY, this software may be distributed under the terms of the
 937 + * GNU General Public License ("GPL") as published by the Free Software
 938 + * Foundation, either version 2 of that License or (at your option) any
 939 + * later version.
 940 + *
 941 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 942 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 943 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 944 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 945 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 946 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 947 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 948 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 949 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 950 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 951 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 952 + */
 953 +
 954 +
 955 +/*
 956 + * The File-backed Storage Gadget acts as a USB Mass Storage device,
 957 + * appearing to the host as a disk drive or as a CD-ROM drive.  In addition
 958 + * to providing an example of a genuinely useful gadget driver for a USB
 959 + * device, it also illustrates a technique of double-buffering for increased
 960 + * throughput.  Last but not least, it gives an easy way to probe the
 961 + * behavior of the Mass Storage drivers in a USB host.
 962 + *
 963 + * Backing storage is provided by a regular file or a block device, specified
 964 + * by the "file" module parameter.  Access can be limited to read-only by
 965 + * setting the optional "ro" module parameter.  (For CD-ROM emulation,
 966 + * access is always read-only.)  The gadget will indicate that it has
 967 + * removable media if the optional "removable" module parameter is set.
 968 + *
 969 + * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI),
 970 + * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected
 971 + * by the optional "transport" module parameter.  It also supports the
 972 + * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03),
 973 + * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by
 974 + * the optional "protocol" module parameter.  In addition, the default
 975 + * Vendor ID, Product ID, release number and serial number can be overridden.
 976 + *
 977 + * There is support for multiple logical units (LUNs), each of which has
 978 + * its own backing file.  The number of LUNs can be set using the optional
 979 + * "luns" module parameter (anywhere from 1 to 8), and the corresponding
 980 + * files are specified using comma-separated lists for "file" and "ro".
 981 + * The default number of LUNs is taken from the number of "file" elements;
 982 + * it is 1 if "file" is not given.  If "removable" is not set then a backing
 983 + * file must be specified for each LUN.  If it is set, then an unspecified
 984 + * or empty backing filename means the LUN's medium is not loaded.  Ideally
 985 + * each LUN would be settable independently as a disk drive or a CD-ROM
 986 + * drive, but currently all LUNs have to be the same type.  The CD-ROM
 987 + * emulation includes a single data track and no audio tracks; hence there
 988 + * need be only one backing file per LUN.
 989 + *
 990 + * Requirements are modest; only a bulk-in and a bulk-out endpoint are
 991 + * needed (an interrupt-out endpoint is also needed for CBI).  The memory
 992 + * requirement amounts to two 16K buffers, size configurable by a parameter.
 993 + * Support is included for both full-speed and high-speed operation.
 994 + *
 995 + * Note that the driver is slightly non-portable in that it assumes a
 996 + * single memory/DMA buffer will be useable for bulk-in, bulk-out, and
 997 + * interrupt-in endpoints.  With most device controllers this isn't an
 998 + * issue, but there may be some with hardware restrictions that prevent
 999 + * a buffer from being used by more than one endpoint.
1000 + *
1001 + * Module options:
1002 + *
1003 + *     file=filename[,filename...]
1004 + *                             Required if "removable" is not set, names of
1005 + *                                     the files or block devices used for
1006 + *                                     backing storage
1007 + *     serial=HHHH...          Required serial number (string of hex chars)
1008 + *     ro=b[,b...]             Default false, booleans for read-only access
1009 + *     removable               Default false, boolean for removable media
1010 + *     luns=N                  Default N = number of filenames, number of
1011 + *                                     LUNs to support
1012 + *     nofua=b[,b...]          Default false, booleans for ignore FUA flag
1013 + *                                     in SCSI WRITE(10,12) commands
1014 + *     stall                   Default determined according to the type of
1015 + *                                     USB device controller (usually true),
1016 + *                                     boolean to permit the driver to halt
1017 + *                                     bulk endpoints
1018 + *     cdrom                   Default false, boolean for whether to emulate
1019 + *                                     a CD-ROM drive
1020 + *     transport=XXX           Default BBB, transport name (CB, CBI, or BBB)
1021 + *     protocol=YYY            Default SCSI, protocol name (RBC, 8020 or
1022 + *                                     ATAPI, QIC, UFI, 8070, or SCSI;
1023 + *                                     also 1 - 6)
1024 + *     vendor=0xVVVV           Default 0x0525 (NetChip), USB Vendor ID
1025 + *     product=0xPPPP          Default 0xa4a5 (FSG), USB Product ID
1026 + *     release=0xRRRR          Override the USB release number (bcdDevice)
1027 + *     buflen=N                Default N=16384, buffer size used (will be
1028 + *                                     rounded down to a multiple of
1029 + *                                     PAGE_CACHE_SIZE)
1030 + *
1031 + * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro",
1032 + * "removable", "luns", "nofua", "stall", and "cdrom" options are available;
1033 + * default values are used for everything else.
1034 + *
1035 + * The pathnames of the backing files and the ro settings are available in
1036 + * the attribute files "file", "nofua", and "ro" in the lun<n> subdirectory of
1037 + * the gadget's sysfs directory.  If the "removable" option is set, writing to
1038 + * these files will simulate ejecting/loading the medium (writing an empty
1039 + * line means eject) and adjusting a write-enable tab.  Changes to the ro
1040 + * setting are not allowed when the medium is loaded or if CD-ROM emulation
1041 + * is being used.
1042 + *
1043 + * This gadget driver is heavily based on "Gadget Zero" by David Brownell.
1044 + * The driver's SCSI command interface was based on the "Information
1045 + * technology - Small Computer System Interface - 2" document from
1046 + * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at
1047 + * <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>.  The single exception
1048 + * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the
1049 + * "Universal Serial Bus Mass Storage Class UFI Command Specification"
1050 + * document, Revision 1.0, December 14, 1998, available at
1051 + * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>.
1052 + */
1053 +
1054 +
1055 +/*
1056 + *                             Driver Design
1057 + *
1058 + * The FSG driver is fairly straightforward.  There is a main kernel
1059 + * thread that handles most of the work.  Interrupt routines field
1060 + * callbacks from the controller driver: bulk- and interrupt-request
1061 + * completion notifications, endpoint-0 events, and disconnect events.
1062 + * Completion events are passed to the main thread by wakeup calls.  Many
1063 + * ep0 requests are handled at interrupt time, but SetInterface,
1064 + * SetConfiguration, and device reset requests are forwarded to the
1065 + * thread in the form of "exceptions" using SIGUSR1 signals (since they
1066 + * should interrupt any ongoing file I/O operations).
1067 + *
1068 + * The thread's main routine implements the standard command/data/status
1069 + * parts of a SCSI interaction.  It and its subroutines are full of tests
1070 + * for pending signals/exceptions -- all this polling is necessary since
1071 + * the kernel has no setjmp/longjmp equivalents.  (Maybe this is an
1072 + * indication that the driver really wants to be running in userspace.)
1073 + * An important point is that so long as the thread is alive it keeps an
1074 + * open reference to the backing file.  This will prevent unmounting
1075 + * the backing file's underlying filesystem and could cause problems
1076 + * during system shutdown, for example.  To prevent such problems, the
1077 + * thread catches INT, TERM, and KILL signals and converts them into
1078 + * an EXIT exception.
1079 + *
1080 + * In normal operation the main thread is started during the gadget's
1081 + * fsg_bind() callback and stopped during fsg_unbind().  But it can also
1082 + * exit when it receives a signal, and there's no point leaving the
1083 + * gadget running when the thread is dead.  So just before the thread
1084 + * exits, it deregisters the gadget driver.  This makes things a little
1085 + * tricky: The driver is deregistered at two places, and the exiting
1086 + * thread can indirectly call fsg_unbind() which in turn can tell the
1087 + * thread to exit.  The first problem is resolved through the use of the
1088 + * REGISTERED atomic bitflag; the driver will only be deregistered once.
1089 + * The second problem is resolved by having fsg_unbind() check
1090 + * fsg->state; it won't try to stop the thread if the state is already
1091 + * FSG_STATE_TERMINATED.
1092 + *
1093 + * To provide maximum throughput, the driver uses a circular pipeline of
1094 + * buffer heads (struct fsg_buffhd).  In principle the pipeline can be
1095 + * arbitrarily long; in practice the benefits don't justify having more
1096 + * than 2 stages (i.e., double buffering).  But it helps to think of the
1097 + * pipeline as being a long one.  Each buffer head contains a bulk-in and
1098 + * a bulk-out request pointer (since the buffer can be used for both
1099 + * output and input -- directions always are given from the host's
1100 + * point of view) as well as a pointer to the buffer and various state
1101 + * variables.
1102 + *
1103 + * Use of the pipeline follows a simple protocol.  There is a variable
1104 + * (fsg->next_buffhd_to_fill) that points to the next buffer head to use.
1105 + * At any time that buffer head may still be in use from an earlier
1106 + * request, so each buffer head has a state variable indicating whether
1107 + * it is EMPTY, FULL, or BUSY.  Typical use involves waiting for the
1108 + * buffer head to be EMPTY, filling the buffer either by file I/O or by
1109 + * USB I/O (during which the buffer head is BUSY), and marking the buffer
1110 + * head FULL when the I/O is complete.  Then the buffer will be emptied
1111 + * (again possibly by USB I/O, during which it is marked BUSY) and
1112 + * finally marked EMPTY again (possibly by a completion routine).
1113 + *
1114 + * A module parameter tells the driver to avoid stalling the bulk
1115 + * endpoints wherever the transport specification allows.  This is
1116 + * necessary for some UDCs like the SuperH, which cannot reliably clear a
1117 + * halt on a bulk endpoint.  However, under certain circumstances the
1118 + * Bulk-only specification requires a stall.  In such cases the driver
1119 + * will halt the endpoint and set a flag indicating that it should clear
1120 + * the halt in software during the next device reset.  Hopefully this
1121 + * will permit everything to work correctly.  Furthermore, although the
1122 + * specification allows the bulk-out endpoint to halt when the host sends
1123 + * too much data, implementing this would cause an unavoidable race.
1124 + * The driver will always use the "no-stall" approach for OUT transfers.
1125 + *
1126 + * One subtle point concerns sending status-stage responses for ep0
1127 + * requests.  Some of these requests, such as device reset, can involve
1128 + * interrupting an ongoing file I/O operation, which might take an
1129 + * arbitrarily long time.  During that delay the host might give up on
1130 + * the original ep0 request and issue a new one.  When that happens the
1131 + * driver should not notify the host about completion of the original
1132 + * request, as the host will no longer be waiting for it.  So the driver
1133 + * assigns to each ep0 request a unique tag, and it keeps track of the
1134 + * tag value of the request associated with a long-running exception
1135 + * (device-reset, interface-change, or configuration-change).  When the
1136 + * exception handler is finished, the status-stage response is submitted
1137 + * only if the current ep0 request tag is equal to the exception request
1138 + * tag.  Thus only the most recently received ep0 request will get a
1139 + * status-stage response.
1140 + *
1141 + * Warning: This driver source file is too long.  It ought to be split up
1142 + * into a header file plus about 3 separate .c files, to handle the details
1143 + * of the Gadget, USB Mass Storage, and SCSI protocols.
1144 + */
1145 +
1146 +
1147 +/* #define VERBOSE_DEBUG */
1148 +/* #define DUMP_MSGS */
1149 +
1150 +
1151 +#include <linux/blkdev.h>
1152 +#include <linux/completion.h>
1153 +#include <linux/dcache.h>
1154 +#include <linux/delay.h>
1155 +#include <linux/device.h>
1156 +#include <linux/fcntl.h>
1157 +#include <linux/file.h>
1158 +#include <linux/fs.h>
1159 +#include <linux/kref.h>
1160 +#include <linux/kthread.h>
1161 +#include <linux/limits.h>
1162 +#include <linux/module.h>
1163 +#include <linux/rwsem.h>
1164 +#include <linux/slab.h>
1165 +#include <linux/spinlock.h>
1166 +#include <linux/string.h>
1167 +#include <linux/freezer.h>
1168 +#include <linux/utsname.h>
1169 +
1170 +#include <linux/usb/ch9.h>
1171 +#include <linux/usb/gadget.h>
1172 +
1173 +#include "gadget_chips.h"
1174 +
1175 +
1176 +
1177 +/*
1178 + * Kbuild is not very cooperative with respect to linking separately
1179 + * compiled library objects into one module.  So for now we won't use
1180 + * separate compilation ... ensuring init/exit sections work to shrink
1181 + * the runtime footprint, and giving us at least some parts of what
1182 + * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
1183 + */
1184 +#include "usbstring.c"
1185 +#include "config.c"
1186 +#include "epautoconf.c"
1187 +
1188 +/*-------------------------------------------------------------------------*/
1189 +
1190 +#define DRIVER_DESC            "File-backed Storage Gadget"
1191 +#define DRIVER_NAME            "g_file_storage"
1192 +#define DRIVER_VERSION         "1 September 2010"
1193 +
1194 +static       char fsg_string_manufacturer[64];
1195 +static const char fsg_string_product[] = DRIVER_DESC;
1196 +static const char fsg_string_config[] = "Self-powered";
1197 +static const char fsg_string_interface[] = "Mass Storage";
1198 +
1199 +
1200 +#include "storage_common.c"
1201 +
1202 +
1203 +MODULE_DESCRIPTION(DRIVER_DESC);
1204 +MODULE_AUTHOR("Alan Stern");
1205 +MODULE_LICENSE("Dual BSD/GPL");
1206 +
1207 +/*
1208 + * This driver assumes self-powered hardware and has no way for users to
1209 + * trigger remote wakeup.  It uses autoconfiguration to select endpoints
1210 + * and endpoint addresses.
1211 + */
1212 +
1213 +
1214 +/*-------------------------------------------------------------------------*/
1215 +
1216 +
1217 +/* Encapsulate the module parameter settings */
1218 +
1219 +static struct {
1220 +       char            *file[FSG_MAX_LUNS];
1221 +       char            *serial;
1222 +       bool            ro[FSG_MAX_LUNS];
1223 +       bool            nofua[FSG_MAX_LUNS];
1224 +       unsigned int    num_filenames;
1225 +       unsigned int    num_ros;
1226 +       unsigned int    num_nofuas;
1227 +       unsigned int    nluns;
1228 +
1229 +       bool            removable;
1230 +       bool            can_stall;
1231 +       bool            cdrom;
1232 +
1233 +       char            *transport_parm;
1234 +       char            *protocol_parm;
1235 +       unsigned short  vendor;
1236 +       unsigned short  product;
1237 +       unsigned short  release;
1238 +       unsigned int    buflen;
1239 +
1240 +       int             transport_type;
1241 +       char            *transport_name;
1242 +       int             protocol_type;
1243 +       char            *protocol_name;
1244 +
1245 +} mod_data = {                                 // Default values
1246 +       .transport_parm         = "BBB",
1247 +       .protocol_parm          = "SCSI",
1248 +       .removable              = 0,
1249 +       .can_stall              = 1,
1250 +       .cdrom                  = 0,
1251 +       .vendor                 = FSG_VENDOR_ID,
1252 +       .product                = FSG_PRODUCT_ID,
1253 +       .release                = 0xffff,       // Use controller chip type
1254 +       .buflen                 = 16384,
1255 +       };
1256 +
1257 +
1258 +module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames,
1259 +               S_IRUGO);
1260 +MODULE_PARM_DESC(file, "names of backing files or devices");
1261 +
1262 +module_param_named(serial, mod_data.serial, charp, S_IRUGO);
1263 +MODULE_PARM_DESC(serial, "USB serial number");
1264 +
1265 +module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO);
1266 +MODULE_PARM_DESC(ro, "true to force read-only");
1267 +
1268 +module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas,
1269 +               S_IRUGO);
1270 +MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit");
1271 +
1272 +module_param_named(luns, mod_data.nluns, uint, S_IRUGO);
1273 +MODULE_PARM_DESC(luns, "number of LUNs");
1274 +
1275 +module_param_named(removable, mod_data.removable, bool, S_IRUGO);
1276 +MODULE_PARM_DESC(removable, "true to simulate removable media");
1277 +
1278 +module_param_named(stall, mod_data.can_stall, bool, S_IRUGO);
1279 +MODULE_PARM_DESC(stall, "false to prevent bulk stalls");
1280 +
1281 +module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO);
1282 +MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk");
1283 +
1284 +/* In the non-TEST version, only the module parameters listed above
1285 + * are available. */
1286 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1287 +
1288 +module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO);
1289 +MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)");
1290 +
1291 +module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO);
1292 +MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, "
1293 +               "8070, or SCSI)");
1294 +
1295 +module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO);
1296 +MODULE_PARM_DESC(vendor, "USB Vendor ID");
1297 +
1298 +module_param_named(product, mod_data.product, ushort, S_IRUGO);
1299 +MODULE_PARM_DESC(product, "USB Product ID");
1300 +
1301 +module_param_named(release, mod_data.release, ushort, S_IRUGO);
1302 +MODULE_PARM_DESC(release, "USB release number");
1303 +
1304 +module_param_named(buflen, mod_data.buflen, uint, S_IRUGO);
1305 +MODULE_PARM_DESC(buflen, "I/O buffer size");
1306 +
1307 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1308 +
1309 +
1310 +/*
1311 + * These definitions will permit the compiler to avoid generating code for
1312 + * parts of the driver that aren't used in the non-TEST version.  Even gcc
1313 + * can recognize when a test of a constant expression yields a dead code
1314 + * path.
1315 + */
1316 +
1317 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1318 +
1319 +#define transport_is_bbb()     (mod_data.transport_type == USB_PR_BULK)
1320 +#define transport_is_cbi()     (mod_data.transport_type == USB_PR_CBI)
1321 +#define protocol_is_scsi()     (mod_data.protocol_type == USB_SC_SCSI)
1322 +
1323 +#else
1324 +
1325 +#define transport_is_bbb()     1
1326 +#define transport_is_cbi()     0
1327 +#define protocol_is_scsi()     1
1328 +
1329 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1330 +
1331 +
1332 +/*-------------------------------------------------------------------------*/
1333 +
1334 +
1335 +struct fsg_dev {
1336 +       /* lock protects: state, all the req_busy's, and cbbuf_cmnd */
1337 +       spinlock_t              lock;
1338 +       struct usb_gadget       *gadget;
1339 +
1340 +       /* filesem protects: backing files in use */
1341 +       struct rw_semaphore     filesem;
1342 +
1343 +       /* reference counting: wait until all LUNs are released */
1344 +       struct kref             ref;
1345 +
1346 +       struct usb_ep           *ep0;           // Handy copy of gadget->ep0
1347 +       struct usb_request      *ep0req;        // For control responses
1348 +       unsigned int            ep0_req_tag;
1349 +       const char              *ep0req_name;
1350 +
1351 +       struct usb_request      *intreq;        // For interrupt responses
1352 +       int                     intreq_busy;
1353 +       struct fsg_buffhd       *intr_buffhd;
1354 +
1355 +       unsigned int            bulk_out_maxpacket;
1356 +       enum fsg_state          state;          // For exception handling
1357 +       unsigned int            exception_req_tag;
1358 +
1359 +       u8                      config, new_config;
1360 +
1361 +       unsigned int            running : 1;
1362 +       unsigned int            bulk_in_enabled : 1;
1363 +       unsigned int            bulk_out_enabled : 1;
1364 +       unsigned int            intr_in_enabled : 1;
1365 +       unsigned int            phase_error : 1;
1366 +       unsigned int            short_packet_received : 1;
1367 +       unsigned int            bad_lun_okay : 1;
1368 +
1369 +       unsigned long           atomic_bitflags;
1370 +#define REGISTERED             0
1371 +#define IGNORE_BULK_OUT                1
1372 +#define SUSPENDED              2
1373 +
1374 +       struct usb_ep           *bulk_in;
1375 +       struct usb_ep           *bulk_out;
1376 +       struct usb_ep           *intr_in;
1377 +
1378 +       struct fsg_buffhd       *next_buffhd_to_fill;
1379 +       struct fsg_buffhd       *next_buffhd_to_drain;
1380 +
1381 +       int                     thread_wakeup_needed;
1382 +       struct completion       thread_notifier;
1383 +       struct task_struct      *thread_task;
1384 +
1385 +       int                     cmnd_size;
1386 +       u8                      cmnd[MAX_COMMAND_SIZE];
1387 +       enum data_direction     data_dir;
1388 +       u32                     data_size;
1389 +       u32                     data_size_from_cmnd;
1390 +       u32                     tag;
1391 +       unsigned int            lun;
1392 +       u32                     residue;
1393 +       u32                     usb_amount_left;
1394 +
1395 +       /* The CB protocol offers no way for a host to know when a command
1396 +        * has completed.  As a result the next command may arrive early,
1397 +        * and we will still have to handle it.  For that reason we need
1398 +        * a buffer to store new commands when using CB (or CBI, which
1399 +        * does not oblige a host to wait for command completion either). */
1400 +       int                     cbbuf_cmnd_size;
1401 +       u8                      cbbuf_cmnd[MAX_COMMAND_SIZE];
1402 +
1403 +       unsigned int            nluns;
1404 +       struct fsg_lun          *luns;
1405 +       struct fsg_lun          *curlun;
1406 +       /* Must be the last entry */
1407 +       struct fsg_buffhd       buffhds[];
1408 +};
1409 +
1410 +typedef void (*fsg_routine_t)(struct fsg_dev *);
1411 +
1412 +static int exception_in_progress(struct fsg_dev *fsg)
1413 +{
1414 +       return (fsg->state > FSG_STATE_IDLE);
1415 +}
1416 +
1417 +/* Make bulk-out requests be divisible by the maxpacket size */
1418 +static void set_bulk_out_req_length(struct fsg_dev *fsg,
1419 +               struct fsg_buffhd *bh, unsigned int length)
1420 +{
1421 +       unsigned int    rem;
1422 +
1423 +       bh->bulk_out_intended_length = length;
1424 +       rem = length % fsg->bulk_out_maxpacket;
1425 +       if (rem > 0)
1426 +               length += fsg->bulk_out_maxpacket - rem;
1427 +       bh->outreq->length = length;
1428 +}
1429 +
1430 +static struct fsg_dev                  *the_fsg;
1431 +static struct usb_gadget_driver                fsg_driver;
1432 +
1433 +
1434 +/*-------------------------------------------------------------------------*/
1435 +
1436 +static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
1437 +{
1438 +       const char      *name;
1439 +
1440 +       if (ep == fsg->bulk_in)
1441 +               name = "bulk-in";
1442 +       else if (ep == fsg->bulk_out)
1443 +               name = "bulk-out";
1444 +       else
1445 +               name = ep->name;
1446 +       DBG(fsg, "%s set halt\n", name);
1447 +       return usb_ep_set_halt(ep);
1448 +}
1449 +
1450 +
1451 +/*-------------------------------------------------------------------------*/
1452 +
1453 +/*
1454 + * DESCRIPTORS ... most are static, but strings and (full) configuration
1455 + * descriptors are built on demand.  Also the (static) config and interface
1456 + * descriptors are adjusted during fsg_bind().
1457 + */
1458 +
1459 +/* There is only one configuration. */
1460 +#define        CONFIG_VALUE            1
1461 +
1462 +static struct usb_device_descriptor
1463 +device_desc = {
1464 +       .bLength =              sizeof device_desc,
1465 +       .bDescriptorType =      USB_DT_DEVICE,
1466 +
1467 +       .bcdUSB =               cpu_to_le16(0x0200),
1468 +       .bDeviceClass =         USB_CLASS_PER_INTERFACE,
1469 +
1470 +       /* The next three values can be overridden by module parameters */
1471 +       .idVendor =             cpu_to_le16(FSG_VENDOR_ID),
1472 +       .idProduct =            cpu_to_le16(FSG_PRODUCT_ID),
1473 +       .bcdDevice =            cpu_to_le16(0xffff),
1474 +
1475 +       .iManufacturer =        FSG_STRING_MANUFACTURER,
1476 +       .iProduct =             FSG_STRING_PRODUCT,
1477 +       .iSerialNumber =        FSG_STRING_SERIAL,
1478 +       .bNumConfigurations =   1,
1479 +};
1480 +
1481 +static struct usb_config_descriptor
1482 +config_desc = {
1483 +       .bLength =              sizeof config_desc,
1484 +       .bDescriptorType =      USB_DT_CONFIG,
1485 +
1486 +       /* wTotalLength computed by usb_gadget_config_buf() */
1487 +       .bNumInterfaces =       1,
1488 +       .bConfigurationValue =  CONFIG_VALUE,
1489 +       .iConfiguration =       FSG_STRING_CONFIG,
1490 +       .bmAttributes =         USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER,
1491 +       .bMaxPower =            CONFIG_USB_GADGET_VBUS_DRAW / 2,
1492 +};
1493 +
1494 +
1495 +static struct usb_qualifier_descriptor
1496 +dev_qualifier = {
1497 +       .bLength =              sizeof dev_qualifier,
1498 +       .bDescriptorType =      USB_DT_DEVICE_QUALIFIER,
1499 +
1500 +       .bcdUSB =               cpu_to_le16(0x0200),
1501 +       .bDeviceClass =         USB_CLASS_PER_INTERFACE,
1502 +
1503 +       .bNumConfigurations =   1,
1504 +};
1505 +
1506 +static int populate_bos(struct fsg_dev *fsg, u8 *buf)
1507 +{
1508 +       memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE);
1509 +       buf += USB_DT_BOS_SIZE;
1510 +
1511 +       memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE);
1512 +       buf += USB_DT_USB_EXT_CAP_SIZE;
1513 +
1514 +       memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE);
1515 +
1516 +       return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE
1517 +               + USB_DT_USB_EXT_CAP_SIZE;
1518 +}
1519 +
1520 +/*
1521 + * Config descriptors must agree with the code that sets configurations
1522 + * and with code managing interfaces and their altsettings.  They must
1523 + * also handle different speeds and other-speed requests.
1524 + */
1525 +static int populate_config_buf(struct usb_gadget *gadget,
1526 +               u8 *buf, u8 type, unsigned index)
1527 +{
1528 +       enum usb_device_speed                   speed = gadget->speed;
1529 +       int                                     len;
1530 +       const struct usb_descriptor_header      **function;
1531 +
1532 +       if (index > 0)
1533 +               return -EINVAL;
1534 +
1535 +       if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG)
1536 +               speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed;
1537 +       function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH
1538 +               ? (const struct usb_descriptor_header **)fsg_hs_function
1539 +               : (const struct usb_descriptor_header **)fsg_fs_function;
1540 +
1541 +       /* for now, don't advertise srp-only devices */
1542 +       if (!gadget_is_otg(gadget))
1543 +               function++;
1544 +
1545 +       len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function);
1546 +       ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
1547 +       return len;
1548 +}
1549 +
1550 +
1551 +/*-------------------------------------------------------------------------*/
1552 +
1553 +/* These routines may be called in process context or in_irq */
1554 +
1555 +/* Caller must hold fsg->lock */
1556 +static void wakeup_thread(struct fsg_dev *fsg)
1557 +{
1558 +       /* Tell the main thread that something has happened */
1559 +       fsg->thread_wakeup_needed = 1;
1560 +       if (fsg->thread_task)
1561 +               wake_up_process(fsg->thread_task);
1562 +}
1563 +
1564 +
1565 +static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state)
1566 +{
1567 +       unsigned long           flags;
1568 +
1569 +       /* Do nothing if a higher-priority exception is already in progress.
1570 +        * If a lower-or-equal priority exception is in progress, preempt it
1571 +        * and notify the main thread by sending it a signal. */
1572 +       spin_lock_irqsave(&fsg->lock, flags);
1573 +       if (fsg->state <= new_state) {
1574 +               fsg->exception_req_tag = fsg->ep0_req_tag;
1575 +               fsg->state = new_state;
1576 +               if (fsg->thread_task)
1577 +                       send_sig_info(SIGUSR1, SEND_SIG_FORCED,
1578 +                                       fsg->thread_task);
1579 +       }
1580 +       spin_unlock_irqrestore(&fsg->lock, flags);
1581 +}
1582 +
1583 +
1584 +/*-------------------------------------------------------------------------*/
1585 +
1586 +/* The disconnect callback and ep0 routines.  These always run in_irq,
1587 + * except that ep0_queue() is called in the main thread to acknowledge
1588 + * completion of various requests: set config, set interface, and
1589 + * Bulk-only device reset. */
1590 +
1591 +static void fsg_disconnect(struct usb_gadget *gadget)
1592 +{
1593 +       struct fsg_dev          *fsg = get_gadget_data(gadget);
1594 +
1595 +       DBG(fsg, "disconnect or port reset\n");
1596 +       raise_exception(fsg, FSG_STATE_DISCONNECT);
1597 +}
1598 +
1599 +
1600 +static int ep0_queue(struct fsg_dev *fsg)
1601 +{
1602 +       int     rc;
1603 +
1604 +       rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC);
1605 +       if (rc != 0 && rc != -ESHUTDOWN) {
1606 +
1607 +               /* We can't do much more than wait for a reset */
1608 +               WARNING(fsg, "error in submission: %s --> %d\n",
1609 +                               fsg->ep0->name, rc);
1610 +       }
1611 +       return rc;
1612 +}
1613 +
1614 +static void ep0_complete(struct usb_ep *ep, struct usb_request *req)
1615 +{
1616 +       struct fsg_dev          *fsg = ep->driver_data;
1617 +
1618 +       if (req->actual > 0)
1619 +               dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual);
1620 +       if (req->status || req->actual != req->length)
1621 +               DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1622 +                               req->status, req->actual, req->length);
1623 +       if (req->status == -ECONNRESET)         // Request was cancelled
1624 +               usb_ep_fifo_flush(ep);
1625 +
1626 +       if (req->status == 0 && req->context)
1627 +               ((fsg_routine_t) (req->context))(fsg);
1628 +}
1629 +
1630 +
1631 +/*-------------------------------------------------------------------------*/
1632 +
1633 +/* Bulk and interrupt endpoint completion handlers.
1634 + * These always run in_irq. */
1635 +
1636 +static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req)
1637 +{
1638 +       struct fsg_dev          *fsg = ep->driver_data;
1639 +       struct fsg_buffhd       *bh = req->context;
1640 +
1641 +       if (req->status || req->actual != req->length)
1642 +               DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1643 +                               req->status, req->actual, req->length);
1644 +       if (req->status == -ECONNRESET)         // Request was cancelled
1645 +               usb_ep_fifo_flush(ep);
1646 +
1647 +       /* Hold the lock while we update the request and buffer states */
1648 +       smp_wmb();
1649 +       spin_lock(&fsg->lock);
1650 +       bh->inreq_busy = 0;
1651 +       bh->state = BUF_STATE_EMPTY;
1652 +       wakeup_thread(fsg);
1653 +       spin_unlock(&fsg->lock);
1654 +}
1655 +
1656 +static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req)
1657 +{
1658 +       struct fsg_dev          *fsg = ep->driver_data;
1659 +       struct fsg_buffhd       *bh = req->context;
1660 +
1661 +       dump_msg(fsg, "bulk-out", req->buf, req->actual);
1662 +       if (req->status || req->actual != bh->bulk_out_intended_length)
1663 +               DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1664 +                               req->status, req->actual,
1665 +                               bh->bulk_out_intended_length);
1666 +       if (req->status == -ECONNRESET)         // Request was cancelled
1667 +               usb_ep_fifo_flush(ep);
1668 +
1669 +       /* Hold the lock while we update the request and buffer states */
1670 +       smp_wmb();
1671 +       spin_lock(&fsg->lock);
1672 +       bh->outreq_busy = 0;
1673 +       bh->state = BUF_STATE_FULL;
1674 +       wakeup_thread(fsg);
1675 +       spin_unlock(&fsg->lock);
1676 +}
1677 +
1678 +
1679 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1680 +static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
1681 +{
1682 +       struct fsg_dev          *fsg = ep->driver_data;
1683 +       struct fsg_buffhd       *bh = req->context;
1684 +
1685 +       if (req->status || req->actual != req->length)
1686 +               DBG(fsg, "%s --> %d, %u/%u\n", __func__,
1687 +                               req->status, req->actual, req->length);
1688 +       if (req->status == -ECONNRESET)         // Request was cancelled
1689 +               usb_ep_fifo_flush(ep);
1690 +
1691 +       /* Hold the lock while we update the request and buffer states */
1692 +       smp_wmb();
1693 +       spin_lock(&fsg->lock);
1694 +       fsg->intreq_busy = 0;
1695 +       bh->state = BUF_STATE_EMPTY;
1696 +       wakeup_thread(fsg);
1697 +       spin_unlock(&fsg->lock);
1698 +}
1699 +
1700 +#else
1701 +static void intr_in_complete(struct usb_ep *ep, struct usb_request *req)
1702 +{}
1703 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1704 +
1705 +
1706 +/*-------------------------------------------------------------------------*/
1707 +
1708 +/* Ep0 class-specific handlers.  These always run in_irq. */
1709 +
1710 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
1711 +static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
1712 +{
1713 +       struct usb_request      *req = fsg->ep0req;
1714 +       static u8               cbi_reset_cmnd[6] = {
1715 +                       SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff};
1716 +
1717 +       /* Error in command transfer? */
1718 +       if (req->status || req->length != req->actual ||
1719 +                       req->actual < 6 || req->actual > MAX_COMMAND_SIZE) {
1720 +
1721 +               /* Not all controllers allow a protocol stall after
1722 +                * receiving control-out data, but we'll try anyway. */
1723 +               fsg_set_halt(fsg, fsg->ep0);
1724 +               return;                 // Wait for reset
1725 +       }
1726 +
1727 +       /* Is it the special reset command? */
1728 +       if (req->actual >= sizeof cbi_reset_cmnd &&
1729 +                       memcmp(req->buf, cbi_reset_cmnd,
1730 +                               sizeof cbi_reset_cmnd) == 0) {
1731 +
1732 +               /* Raise an exception to stop the current operation
1733 +                * and reinitialize our state. */
1734 +               DBG(fsg, "cbi reset request\n");
1735 +               raise_exception(fsg, FSG_STATE_RESET);
1736 +               return;
1737 +       }
1738 +
1739 +       VDBG(fsg, "CB[I] accept device-specific command\n");
1740 +       spin_lock(&fsg->lock);
1741 +
1742 +       /* Save the command for later */
1743 +       if (fsg->cbbuf_cmnd_size)
1744 +               WARNING(fsg, "CB[I] overwriting previous command\n");
1745 +       fsg->cbbuf_cmnd_size = req->actual;
1746 +       memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size);
1747 +
1748 +       wakeup_thread(fsg);
1749 +       spin_unlock(&fsg->lock);
1750 +}
1751 +
1752 +#else
1753 +static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
1754 +{}
1755 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
1756 +
1757 +
1758 +static int class_setup_req(struct fsg_dev *fsg,
1759 +               const struct usb_ctrlrequest *ctrl)
1760 +{
1761 +       struct usb_request      *req = fsg->ep0req;
1762 +       int                     value = -EOPNOTSUPP;
1763 +       u16                     w_index = le16_to_cpu(ctrl->wIndex);
1764 +       u16                     w_value = le16_to_cpu(ctrl->wValue);
1765 +       u16                     w_length = le16_to_cpu(ctrl->wLength);
1766 +
1767 +       if (!fsg->config)
1768 +               return value;
1769 +
1770 +       /* Handle Bulk-only class-specific requests */
1771 +       if (transport_is_bbb()) {
1772 +               switch (ctrl->bRequest) {
1773 +
1774 +               case US_BULK_RESET_REQUEST:
1775 +                       if (ctrl->bRequestType != (USB_DIR_OUT |
1776 +                                       USB_TYPE_CLASS | USB_RECIP_INTERFACE))
1777 +                               break;
1778 +                       if (w_index != 0 || w_value != 0 || w_length != 0) {
1779 +                               value = -EDOM;
1780 +                               break;
1781 +                       }
1782 +
1783 +                       /* Raise an exception to stop the current operation
1784 +                        * and reinitialize our state. */
1785 +                       DBG(fsg, "bulk reset request\n");
1786 +                       raise_exception(fsg, FSG_STATE_RESET);
1787 +                       value = DELAYED_STATUS;
1788 +                       break;
1789 +
1790 +               case US_BULK_GET_MAX_LUN:
1791 +                       if (ctrl->bRequestType != (USB_DIR_IN |
1792 +                                       USB_TYPE_CLASS | USB_RECIP_INTERFACE))
1793 +                               break;
1794 +                       if (w_index != 0 || w_value != 0 || w_length != 1) {
1795 +                               value = -EDOM;
1796 +                               break;
1797 +                       }
1798 +                       VDBG(fsg, "get max LUN\n");
1799 +                       *(u8 *) req->buf = fsg->nluns - 1;
1800 +                       value = 1;
1801 +                       break;
1802 +               }
1803 +       }
1804 +
1805 +       /* Handle CBI class-specific requests */
1806 +       else {
1807 +               switch (ctrl->bRequest) {
1808 +
1809 +               case USB_CBI_ADSC_REQUEST:
1810 +                       if (ctrl->bRequestType != (USB_DIR_OUT |
1811 +                                       USB_TYPE_CLASS | USB_RECIP_INTERFACE))
1812 +                               break;
1813 +                       if (w_index != 0 || w_value != 0) {
1814 +                               value = -EDOM;
1815 +                               break;
1816 +                       }
1817 +                       if (w_length > MAX_COMMAND_SIZE) {
1818 +                               value = -EOVERFLOW;
1819 +                               break;
1820 +                       }
1821 +                       value = w_length;
1822 +                       fsg->ep0req->context = received_cbi_adsc;
1823 +                       break;
1824 +               }
1825 +       }
1826 +
1827 +       if (value == -EOPNOTSUPP)
1828 +               VDBG(fsg,
1829 +                       "unknown class-specific control req "
1830 +                       "%02x.%02x v%04x i%04x l%u\n",
1831 +                       ctrl->bRequestType, ctrl->bRequest,
1832 +                       le16_to_cpu(ctrl->wValue), w_index, w_length);
1833 +       return value;
1834 +}
1835 +
1836 +
1837 +/*-------------------------------------------------------------------------*/
1838 +
1839 +/* Ep0 standard request handlers.  These always run in_irq. */
1840 +
1841 +static int standard_setup_req(struct fsg_dev *fsg,
1842 +               const struct usb_ctrlrequest *ctrl)
1843 +{
1844 +       struct usb_request      *req = fsg->ep0req;
1845 +       int                     value = -EOPNOTSUPP;
1846 +       u16                     w_index = le16_to_cpu(ctrl->wIndex);
1847 +       u16                     w_value = le16_to_cpu(ctrl->wValue);
1848 +
1849 +       /* Usually this just stores reply data in the pre-allocated ep0 buffer,
1850 +        * but config change events will also reconfigure hardware. */
1851 +       switch (ctrl->bRequest) {
1852 +
1853 +       case USB_REQ_GET_DESCRIPTOR:
1854 +               if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
1855 +                               USB_RECIP_DEVICE))
1856 +                       break;
1857 +               switch (w_value >> 8) {
1858 +
1859 +               case USB_DT_DEVICE:
1860 +                       VDBG(fsg, "get device descriptor\n");
1861 +                       device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket;
1862 +                       value = sizeof device_desc;
1863 +                       memcpy(req->buf, &device_desc, value);
1864 +                       break;
1865 +               case USB_DT_DEVICE_QUALIFIER:
1866 +                       VDBG(fsg, "get device qualifier\n");
1867 +                       if (!gadget_is_dualspeed(fsg->gadget) ||
1868 +                                       fsg->gadget->speed == USB_SPEED_SUPER)
1869 +                               break;
1870 +                       /*
1871 +                        * Assume ep0 uses the same maxpacket value for both
1872 +                        * speeds
1873 +                        */
1874 +                       dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket;
1875 +                       value = sizeof dev_qualifier;
1876 +                       memcpy(req->buf, &dev_qualifier, value);
1877 +                       break;
1878 +
1879 +               case USB_DT_OTHER_SPEED_CONFIG:
1880 +                       VDBG(fsg, "get other-speed config descriptor\n");
1881 +                       if (!gadget_is_dualspeed(fsg->gadget) ||
1882 +                                       fsg->gadget->speed == USB_SPEED_SUPER)
1883 +                               break;
1884 +                       goto get_config;
1885 +               case USB_DT_CONFIG:
1886 +                       VDBG(fsg, "get configuration descriptor\n");
1887 +get_config:
1888 +                       value = populate_config_buf(fsg->gadget,
1889 +                                       req->buf,
1890 +                                       w_value >> 8,
1891 +                                       w_value & 0xff);
1892 +                       break;
1893 +
1894 +               case USB_DT_STRING:
1895 +                       VDBG(fsg, "get string descriptor\n");
1896 +
1897 +                       /* wIndex == language code */
1898 +                       value = usb_gadget_get_string(&fsg_stringtab,
1899 +                                       w_value & 0xff, req->buf);
1900 +                       break;
1901 +
1902 +               case USB_DT_BOS:
1903 +                       VDBG(fsg, "get bos descriptor\n");
1904 +
1905 +                       if (gadget_is_superspeed(fsg->gadget))
1906 +                               value = populate_bos(fsg, req->buf);
1907 +                       break;
1908 +               }
1909 +
1910 +               break;
1911 +
1912 +       /* One config, two speeds */
1913 +       case USB_REQ_SET_CONFIGURATION:
1914 +               if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD |
1915 +                               USB_RECIP_DEVICE))
1916 +                       break;
1917 +               VDBG(fsg, "set configuration\n");
1918 +               if (w_value == CONFIG_VALUE || w_value == 0) {
1919 +                       fsg->new_config = w_value;
1920 +
1921 +                       /* Raise an exception to wipe out previous transaction
1922 +                        * state (queued bufs, etc) and set the new config. */
1923 +                       raise_exception(fsg, FSG_STATE_CONFIG_CHANGE);
1924 +                       value = DELAYED_STATUS;
1925 +               }
1926 +               break;
1927 +       case USB_REQ_GET_CONFIGURATION:
1928 +               if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
1929 +                               USB_RECIP_DEVICE))
1930 +                       break;
1931 +               VDBG(fsg, "get configuration\n");
1932 +               *(u8 *) req->buf = fsg->config;
1933 +               value = 1;
1934 +               break;
1935 +
1936 +       case USB_REQ_SET_INTERFACE:
1937 +               if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD |
1938 +                               USB_RECIP_INTERFACE))
1939 +                       break;
1940 +               if (fsg->config && w_index == 0) {
1941 +
1942 +                       /* Raise an exception to wipe out previous transaction
1943 +                        * state (queued bufs, etc) and install the new
1944 +                        * interface altsetting. */
1945 +                       raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE);
1946 +                       value = DELAYED_STATUS;
1947 +               }
1948 +               break;
1949 +       case USB_REQ_GET_INTERFACE:
1950 +               if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD |
1951 +                               USB_RECIP_INTERFACE))
1952 +                       break;
1953 +               if (!fsg->config)
1954 +                       break;
1955 +               if (w_index != 0) {
1956 +                       value = -EDOM;
1957 +                       break;
1958 +               }
1959 +               VDBG(fsg, "get interface\n");
1960 +               *(u8 *) req->buf = 0;
1961 +               value = 1;
1962 +               break;
1963 +
1964 +       default:
1965 +               VDBG(fsg,
1966 +                       "unknown control req %02x.%02x v%04x i%04x l%u\n",
1967 +                       ctrl->bRequestType, ctrl->bRequest,
1968 +                       w_value, w_index, le16_to_cpu(ctrl->wLength));
1969 +       }
1970 +
1971 +       return value;
1972 +}
1973 +
1974 +
1975 +static int fsg_setup(struct usb_gadget *gadget,
1976 +               const struct usb_ctrlrequest *ctrl)
1977 +{
1978 +       struct fsg_dev          *fsg = get_gadget_data(gadget);
1979 +       int                     rc;
1980 +       int                     w_length = le16_to_cpu(ctrl->wLength);
1981 +
1982 +       ++fsg->ep0_req_tag;             // Record arrival of a new request
1983 +       fsg->ep0req->context = NULL;
1984 +       fsg->ep0req->length = 0;
1985 +       dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
1986 +
1987 +       if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
1988 +               rc = class_setup_req(fsg, ctrl);
1989 +       else
1990 +               rc = standard_setup_req(fsg, ctrl);
1991 +
1992 +       /* Respond with data/status or defer until later? */
1993 +       if (rc >= 0 && rc != DELAYED_STATUS) {
1994 +               rc = min(rc, w_length);
1995 +               fsg->ep0req->length = rc;
1996 +               fsg->ep0req->zero = rc < w_length;
1997 +               fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ?
1998 +                               "ep0-in" : "ep0-out");
1999 +               rc = ep0_queue(fsg);
2000 +       }
2001 +
2002 +       /* Device either stalls (rc < 0) or reports success */
2003 +       return rc;
2004 +}
2005 +
2006 +
2007 +/*-------------------------------------------------------------------------*/
2008 +
2009 +/* All the following routines run in process context */
2010 +
2011 +
2012 +/* Use this for bulk or interrupt transfers, not ep0 */
2013 +static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep,
2014 +               struct usb_request *req, int *pbusy,
2015 +               enum fsg_buffer_state *state)
2016 +{
2017 +       int     rc;
2018 +
2019 +       if (ep == fsg->bulk_in)
2020 +               dump_msg(fsg, "bulk-in", req->buf, req->length);
2021 +       else if (ep == fsg->intr_in)
2022 +               dump_msg(fsg, "intr-in", req->buf, req->length);
2023 +
2024 +       spin_lock_irq(&fsg->lock);
2025 +       *pbusy = 1;
2026 +       *state = BUF_STATE_BUSY;
2027 +       spin_unlock_irq(&fsg->lock);
2028 +       rc = usb_ep_queue(ep, req, GFP_KERNEL);
2029 +       if (rc != 0) {
2030 +               *pbusy = 0;
2031 +               *state = BUF_STATE_EMPTY;
2032 +
2033 +               /* We can't do much more than wait for a reset */
2034 +
2035 +               /* Note: currently the net2280 driver fails zero-length
2036 +                * submissions if DMA is enabled. */
2037 +               if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP &&
2038 +                                               req->length == 0))
2039 +                       WARNING(fsg, "error in submission: %s --> %d\n",
2040 +                                       ep->name, rc);
2041 +       }
2042 +}
2043 +
2044 +
2045 +static int sleep_thread(struct fsg_dev *fsg)
2046 +{
2047 +       int     rc = 0;
2048 +
2049 +       /* Wait until a signal arrives or we are woken up */
2050 +       for (;;) {
2051 +               try_to_freeze();
2052 +               set_current_state(TASK_INTERRUPTIBLE);
2053 +               if (signal_pending(current)) {
2054 +                       rc = -EINTR;
2055 +                       break;
2056 +               }
2057 +               if (fsg->thread_wakeup_needed)
2058 +                       break;
2059 +               schedule();
2060 +       }
2061 +       __set_current_state(TASK_RUNNING);
2062 +       fsg->thread_wakeup_needed = 0;
2063 +       return rc;
2064 +}
2065 +
2066 +
2067 +/*-------------------------------------------------------------------------*/
2068 +
2069 +static int do_read(struct fsg_dev *fsg)
2070 +{
2071 +       struct fsg_lun          *curlun = fsg->curlun;
2072 +       u32                     lba;
2073 +       struct fsg_buffhd       *bh;
2074 +       int                     rc;
2075 +       u32                     amount_left;
2076 +       loff_t                  file_offset, file_offset_tmp;
2077 +       unsigned int            amount;
2078 +       ssize_t                 nread;
2079 +
2080 +       /* Get the starting Logical Block Address and check that it's
2081 +        * not too big */
2082 +       if (fsg->cmnd[0] == READ_6)
2083 +               lba = get_unaligned_be24(&fsg->cmnd[1]);
2084 +       else {
2085 +               lba = get_unaligned_be32(&fsg->cmnd[2]);
2086 +
2087 +               /* We allow DPO (Disable Page Out = don't save data in the
2088 +                * cache) and FUA (Force Unit Access = don't read from the
2089 +                * cache), but we don't implement them. */
2090 +               if ((fsg->cmnd[1] & ~0x18) != 0) {
2091 +                       curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2092 +                       return -EINVAL;
2093 +               }
2094 +       }
2095 +       if (lba >= curlun->num_sectors) {
2096 +               curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2097 +               return -EINVAL;
2098 +       }
2099 +       file_offset = ((loff_t) lba) << curlun->blkbits;
2100 +
2101 +       /* Carry out the file reads */
2102 +       amount_left = fsg->data_size_from_cmnd;
2103 +       if (unlikely(amount_left == 0))
2104 +               return -EIO;            // No default reply
2105 +
2106 +       for (;;) {
2107 +
2108 +               /* Figure out how much we need to read:
2109 +                * Try to read the remaining amount.
2110 +                * But don't read more than the buffer size.
2111 +                * And don't try to read past the end of the file.
2112 +                */
2113 +               amount = min((unsigned int) amount_left, mod_data.buflen);
2114 +               amount = min((loff_t) amount,
2115 +                               curlun->file_length - file_offset);
2116 +
2117 +               /* Wait for the next buffer to become available */
2118 +               bh = fsg->next_buffhd_to_fill;
2119 +               while (bh->state != BUF_STATE_EMPTY) {
2120 +                       rc = sleep_thread(fsg);
2121 +                       if (rc)
2122 +                               return rc;
2123 +               }
2124 +
2125 +               /* If we were asked to read past the end of file,
2126 +                * end with an empty buffer. */
2127 +               if (amount == 0) {
2128 +                       curlun->sense_data =
2129 +                                       SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2130 +                       curlun->sense_data_info = file_offset >> curlun->blkbits;
2131 +                       curlun->info_valid = 1;
2132 +                       bh->inreq->length = 0;
2133 +                       bh->state = BUF_STATE_FULL;
2134 +                       break;
2135 +               }
2136 +
2137 +               /* Perform the read */
2138 +               file_offset_tmp = file_offset;
2139 +               nread = vfs_read(curlun->filp,
2140 +                               (char __user *) bh->buf,
2141 +                               amount, &file_offset_tmp);
2142 +               VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
2143 +                               (unsigned long long) file_offset,
2144 +                               (int) nread);
2145 +               if (signal_pending(current))
2146 +                       return -EINTR;
2147 +
2148 +               if (nread < 0) {
2149 +                       LDBG(curlun, "error in file read: %d\n",
2150 +                                       (int) nread);
2151 +                       nread = 0;
2152 +               } else if (nread < amount) {
2153 +                       LDBG(curlun, "partial file read: %d/%u\n",
2154 +                                       (int) nread, amount);
2155 +                       nread = round_down(nread, curlun->blksize);
2156 +               }
2157 +               file_offset  += nread;
2158 +               amount_left  -= nread;
2159 +               fsg->residue -= nread;
2160 +
2161 +               /* Except at the end of the transfer, nread will be
2162 +                * equal to the buffer size, which is divisible by the
2163 +                * bulk-in maxpacket size.
2164 +                */
2165 +               bh->inreq->length = nread;
2166 +               bh->state = BUF_STATE_FULL;
2167 +
2168 +               /* If an error occurred, report it and its position */
2169 +               if (nread < amount) {
2170 +                       curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
2171 +                       curlun->sense_data_info = file_offset >> curlun->blkbits;
2172 +                       curlun->info_valid = 1;
2173 +                       break;
2174 +               }
2175 +
2176 +               if (amount_left == 0)
2177 +                       break;          // No more left to read
2178 +
2179 +               /* Send this buffer and go read some more */
2180 +               bh->inreq->zero = 0;
2181 +               start_transfer(fsg, fsg->bulk_in, bh->inreq,
2182 +                               &bh->inreq_busy, &bh->state);
2183 +               fsg->next_buffhd_to_fill = bh->next;
2184 +       }
2185 +
2186 +       return -EIO;            // No default reply
2187 +}
2188 +
2189 +
2190 +/*-------------------------------------------------------------------------*/
2191 +
2192 +static int do_write(struct fsg_dev *fsg)
2193 +{
2194 +       struct fsg_lun          *curlun = fsg->curlun;
2195 +       u32                     lba;
2196 +       struct fsg_buffhd       *bh;
2197 +       int                     get_some_more;
2198 +       u32                     amount_left_to_req, amount_left_to_write;
2199 +       loff_t                  usb_offset, file_offset, file_offset_tmp;
2200 +       unsigned int            amount;
2201 +       ssize_t                 nwritten;
2202 +       int                     rc;
2203 +
2204 +       if (curlun->ro) {
2205 +               curlun->sense_data = SS_WRITE_PROTECTED;
2206 +               return -EINVAL;
2207 +       }
2208 +       spin_lock(&curlun->filp->f_lock);
2209 +       curlun->filp->f_flags &= ~O_SYNC;       // Default is not to wait
2210 +       spin_unlock(&curlun->filp->f_lock);
2211 +
2212 +       /* Get the starting Logical Block Address and check that it's
2213 +        * not too big */
2214 +       if (fsg->cmnd[0] == WRITE_6)
2215 +               lba = get_unaligned_be24(&fsg->cmnd[1]);
2216 +       else {
2217 +               lba = get_unaligned_be32(&fsg->cmnd[2]);
2218 +
2219 +               /* We allow DPO (Disable Page Out = don't save data in the
2220 +                * cache) and FUA (Force Unit Access = write directly to the
2221 +                * medium).  We don't implement DPO; we implement FUA by
2222 +                * performing synchronous output. */
2223 +               if ((fsg->cmnd[1] & ~0x18) != 0) {
2224 +                       curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2225 +                       return -EINVAL;
2226 +               }
2227 +               /* FUA */
2228 +               if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) {
2229 +                       spin_lock(&curlun->filp->f_lock);
2230 +                       curlun->filp->f_flags |= O_DSYNC;
2231 +                       spin_unlock(&curlun->filp->f_lock);
2232 +               }
2233 +       }
2234 +       if (lba >= curlun->num_sectors) {
2235 +               curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2236 +               return -EINVAL;
2237 +       }
2238 +
2239 +       /* Carry out the file writes */
2240 +       get_some_more = 1;
2241 +       file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits;
2242 +       amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd;
2243 +
2244 +       while (amount_left_to_write > 0) {
2245 +
2246 +               /* Queue a request for more data from the host */
2247 +               bh = fsg->next_buffhd_to_fill;
2248 +               if (bh->state == BUF_STATE_EMPTY && get_some_more) {
2249 +
2250 +                       /* Figure out how much we want to get:
2251 +                        * Try to get the remaining amount,
2252 +                        * but not more than the buffer size.
2253 +                        */
2254 +                       amount = min(amount_left_to_req, mod_data.buflen);
2255 +
2256 +                       /* Beyond the end of the backing file? */
2257 +                       if (usb_offset >= curlun->file_length) {
2258 +                               get_some_more = 0;
2259 +                               curlun->sense_data =
2260 +                                       SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2261 +                               curlun->sense_data_info = usb_offset >> curlun->blkbits;
2262 +                               curlun->info_valid = 1;
2263 +                               continue;
2264 +                       }
2265 +
2266 +                       /* Get the next buffer */
2267 +                       usb_offset += amount;
2268 +                       fsg->usb_amount_left -= amount;
2269 +                       amount_left_to_req -= amount;
2270 +                       if (amount_left_to_req == 0)
2271 +                               get_some_more = 0;
2272 +
2273 +                       /* Except at the end of the transfer, amount will be
2274 +                        * equal to the buffer size, which is divisible by
2275 +                        * the bulk-out maxpacket size.
2276 +                        */
2277 +                       set_bulk_out_req_length(fsg, bh, amount);
2278 +                       start_transfer(fsg, fsg->bulk_out, bh->outreq,
2279 +                                       &bh->outreq_busy, &bh->state);
2280 +                       fsg->next_buffhd_to_fill = bh->next;
2281 +                       continue;
2282 +               }
2283 +
2284 +               /* Write the received data to the backing file */
2285 +               bh = fsg->next_buffhd_to_drain;
2286 +               if (bh->state == BUF_STATE_EMPTY && !get_some_more)
2287 +                       break;                  // We stopped early
2288 +               if (bh->state == BUF_STATE_FULL) {
2289 +                       smp_rmb();
2290 +                       fsg->next_buffhd_to_drain = bh->next;
2291 +                       bh->state = BUF_STATE_EMPTY;
2292 +
2293 +                       /* Did something go wrong with the transfer? */
2294 +                       if (bh->outreq->status != 0) {
2295 +                               curlun->sense_data = SS_COMMUNICATION_FAILURE;
2296 +                               curlun->sense_data_info = file_offset >> curlun->blkbits;
2297 +                               curlun->info_valid = 1;
2298 +                               break;
2299 +                       }
2300 +
2301 +                       amount = bh->outreq->actual;
2302 +                       if (curlun->file_length - file_offset < amount) {
2303 +                               LERROR(curlun,
2304 +       "write %u @ %llu beyond end %llu\n",
2305 +       amount, (unsigned long long) file_offset,
2306 +       (unsigned long long) curlun->file_length);
2307 +                               amount = curlun->file_length - file_offset;
2308 +                       }
2309 +
2310 +                       /* Don't accept excess data.  The spec doesn't say
2311 +                        * what to do in this case.  We'll ignore the error.
2312 +                        */
2313 +                       amount = min(amount, bh->bulk_out_intended_length);
2314 +
2315 +                       /* Don't write a partial block */
2316 +                       amount = round_down(amount, curlun->blksize);
2317 +                       if (amount == 0)
2318 +                               goto empty_write;
2319 +
2320 +                       /* Perform the write */
2321 +                       file_offset_tmp = file_offset;
2322 +                       nwritten = vfs_write(curlun->filp,
2323 +                                       (char __user *) bh->buf,
2324 +                                       amount, &file_offset_tmp);
2325 +                       VLDBG(curlun, "file write %u @ %llu -> %d\n", amount,
2326 +                                       (unsigned long long) file_offset,
2327 +                                       (int) nwritten);
2328 +                       if (signal_pending(current))
2329 +                               return -EINTR;          // Interrupted!
2330 +
2331 +                       if (nwritten < 0) {
2332 +                               LDBG(curlun, "error in file write: %d\n",
2333 +                                               (int) nwritten);
2334 +                               nwritten = 0;
2335 +                       } else if (nwritten < amount) {
2336 +                               LDBG(curlun, "partial file write: %d/%u\n",
2337 +                                               (int) nwritten, amount);
2338 +                               nwritten = round_down(nwritten, curlun->blksize);
2339 +                       }
2340 +                       file_offset += nwritten;
2341 +                       amount_left_to_write -= nwritten;
2342 +                       fsg->residue -= nwritten;
2343 +
2344 +                       /* If an error occurred, report it and its position */
2345 +                       if (nwritten < amount) {
2346 +                               curlun->sense_data = SS_WRITE_ERROR;
2347 +                               curlun->sense_data_info = file_offset >> curlun->blkbits;
2348 +                               curlun->info_valid = 1;
2349 +                               break;
2350 +                       }
2351 +
2352 + empty_write:
2353 +                       /* Did the host decide to stop early? */
2354 +                       if (bh->outreq->actual < bh->bulk_out_intended_length) {
2355 +                               fsg->short_packet_received = 1;
2356 +                               break;
2357 +                       }
2358 +                       continue;
2359 +               }
2360 +
2361 +               /* Wait for something to happen */
2362 +               rc = sleep_thread(fsg);
2363 +               if (rc)
2364 +                       return rc;
2365 +       }
2366 +
2367 +       return -EIO;            // No default reply
2368 +}
2369 +
2370 +
2371 +/*-------------------------------------------------------------------------*/
2372 +
2373 +static int do_synchronize_cache(struct fsg_dev *fsg)
2374 +{
2375 +       struct fsg_lun  *curlun = fsg->curlun;
2376 +       int             rc;
2377 +
2378 +       /* We ignore the requested LBA and write out all file's
2379 +        * dirty data buffers. */
2380 +       rc = fsg_lun_fsync_sub(curlun);
2381 +       if (rc)
2382 +               curlun->sense_data = SS_WRITE_ERROR;
2383 +       return 0;
2384 +}
2385 +
2386 +
2387 +/*-------------------------------------------------------------------------*/
2388 +
2389 +static void invalidate_sub(struct fsg_lun *curlun)
2390 +{
2391 +       struct file     *filp = curlun->filp;
2392 +       struct inode    *inode = filp->f_path.dentry->d_inode;
2393 +       unsigned long   rc;
2394 +
2395 +       rc = invalidate_mapping_pages(inode->i_mapping, 0, -1);
2396 +       VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc);
2397 +}
2398 +
2399 +static int do_verify(struct fsg_dev *fsg)
2400 +{
2401 +       struct fsg_lun          *curlun = fsg->curlun;
2402 +       u32                     lba;
2403 +       u32                     verification_length;
2404 +       struct fsg_buffhd       *bh = fsg->next_buffhd_to_fill;
2405 +       loff_t                  file_offset, file_offset_tmp;
2406 +       u32                     amount_left;
2407 +       unsigned int            amount;
2408 +       ssize_t                 nread;
2409 +
2410 +       /* Get the starting Logical Block Address and check that it's
2411 +        * not too big */
2412 +       lba = get_unaligned_be32(&fsg->cmnd[2]);
2413 +       if (lba >= curlun->num_sectors) {
2414 +               curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2415 +               return -EINVAL;
2416 +       }
2417 +
2418 +       /* We allow DPO (Disable Page Out = don't save data in the
2419 +        * cache) but we don't implement it. */
2420 +       if ((fsg->cmnd[1] & ~0x10) != 0) {
2421 +               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2422 +               return -EINVAL;
2423 +       }
2424 +
2425 +       verification_length = get_unaligned_be16(&fsg->cmnd[7]);
2426 +       if (unlikely(verification_length == 0))
2427 +               return -EIO;            // No default reply
2428 +
2429 +       /* Prepare to carry out the file verify */
2430 +       amount_left = verification_length << curlun->blkbits;
2431 +       file_offset = ((loff_t) lba) << curlun->blkbits;
2432 +
2433 +       /* Write out all the dirty buffers before invalidating them */
2434 +       fsg_lun_fsync_sub(curlun);
2435 +       if (signal_pending(current))
2436 +               return -EINTR;
2437 +
2438 +       invalidate_sub(curlun);
2439 +       if (signal_pending(current))
2440 +               return -EINTR;
2441 +
2442 +       /* Just try to read the requested blocks */
2443 +       while (amount_left > 0) {
2444 +
2445 +               /* Figure out how much we need to read:
2446 +                * Try to read the remaining amount, but not more than
2447 +                * the buffer size.
2448 +                * And don't try to read past the end of the file.
2449 +                */
2450 +               amount = min((unsigned int) amount_left, mod_data.buflen);
2451 +               amount = min((loff_t) amount,
2452 +                               curlun->file_length - file_offset);
2453 +               if (amount == 0) {
2454 +                       curlun->sense_data =
2455 +                                       SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2456 +                       curlun->sense_data_info = file_offset >> curlun->blkbits;
2457 +                       curlun->info_valid = 1;
2458 +                       break;
2459 +               }
2460 +
2461 +               /* Perform the read */
2462 +               file_offset_tmp = file_offset;
2463 +               nread = vfs_read(curlun->filp,
2464 +                               (char __user *) bh->buf,
2465 +                               amount, &file_offset_tmp);
2466 +               VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
2467 +                               (unsigned long long) file_offset,
2468 +                               (int) nread);
2469 +               if (signal_pending(current))
2470 +                       return -EINTR;
2471 +
2472 +               if (nread < 0) {
2473 +                       LDBG(curlun, "error in file verify: %d\n",
2474 +                                       (int) nread);
2475 +                       nread = 0;
2476 +               } else if (nread < amount) {
2477 +                       LDBG(curlun, "partial file verify: %d/%u\n",
2478 +                                       (int) nread, amount);
2479 +                       nread = round_down(nread, curlun->blksize);
2480 +               }
2481 +               if (nread == 0) {
2482 +                       curlun->sense_data = SS_UNRECOVERED_READ_ERROR;
2483 +                       curlun->sense_data_info = file_offset >> curlun->blkbits;
2484 +                       curlun->info_valid = 1;
2485 +                       break;
2486 +               }
2487 +               file_offset += nread;
2488 +               amount_left -= nread;
2489 +       }
2490 +       return 0;
2491 +}
2492 +
2493 +
2494 +/*-------------------------------------------------------------------------*/
2495 +
2496 +static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2497 +{
2498 +       u8      *buf = (u8 *) bh->buf;
2499 +
2500 +       static char vendor_id[] = "Linux   ";
2501 +       static char product_disk_id[] = "File-Stor Gadget";
2502 +       static char product_cdrom_id[] = "File-CD Gadget  ";
2503 +
2504 +       if (!fsg->curlun) {             // Unsupported LUNs are okay
2505 +               fsg->bad_lun_okay = 1;
2506 +               memset(buf, 0, 36);
2507 +               buf[0] = 0x7f;          // Unsupported, no device-type
2508 +               buf[4] = 31;            // Additional length
2509 +               return 36;
2510 +       }
2511 +
2512 +       memset(buf, 0, 8);
2513 +       buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK);
2514 +       if (mod_data.removable)
2515 +               buf[1] = 0x80;
2516 +       buf[2] = 2;             // ANSI SCSI level 2
2517 +       buf[3] = 2;             // SCSI-2 INQUIRY data format
2518 +       buf[4] = 31;            // Additional length
2519 +                               // No special options
2520 +       sprintf(buf + 8, "%-8s%-16s%04x", vendor_id,
2521 +                       (mod_data.cdrom ? product_cdrom_id :
2522 +                               product_disk_id),
2523 +                       mod_data.release);
2524 +       return 36;
2525 +}
2526 +
2527 +
2528 +static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2529 +{
2530 +       struct fsg_lun  *curlun = fsg->curlun;
2531 +       u8              *buf = (u8 *) bh->buf;
2532 +       u32             sd, sdinfo;
2533 +       int             valid;
2534 +
2535 +       /*
2536 +        * From the SCSI-2 spec., section 7.9 (Unit attention condition):
2537 +        *
2538 +        * If a REQUEST SENSE command is received from an initiator
2539 +        * with a pending unit attention condition (before the target
2540 +        * generates the contingent allegiance condition), then the
2541 +        * target shall either:
2542 +        *   a) report any pending sense data and preserve the unit
2543 +        *      attention condition on the logical unit, or,
2544 +        *   b) report the unit attention condition, may discard any
2545 +        *      pending sense data, and clear the unit attention
2546 +        *      condition on the logical unit for that initiator.
2547 +        *
2548 +        * FSG normally uses option a); enable this code to use option b).
2549 +        */
2550 +#if 0
2551 +       if (curlun && curlun->unit_attention_data != SS_NO_SENSE) {
2552 +               curlun->sense_data = curlun->unit_attention_data;
2553 +               curlun->unit_attention_data = SS_NO_SENSE;
2554 +       }
2555 +#endif
2556 +
2557 +       if (!curlun) {          // Unsupported LUNs are okay
2558 +               fsg->bad_lun_okay = 1;
2559 +               sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
2560 +               sdinfo = 0;
2561 +               valid = 0;
2562 +       } else {
2563 +               sd = curlun->sense_data;
2564 +               sdinfo = curlun->sense_data_info;
2565 +               valid = curlun->info_valid << 7;
2566 +               curlun->sense_data = SS_NO_SENSE;
2567 +               curlun->sense_data_info = 0;
2568 +               curlun->info_valid = 0;
2569 +       }
2570 +
2571 +       memset(buf, 0, 18);
2572 +       buf[0] = valid | 0x70;                  // Valid, current error
2573 +       buf[2] = SK(sd);
2574 +       put_unaligned_be32(sdinfo, &buf[3]);    /* Sense information */
2575 +       buf[7] = 18 - 8;                        // Additional sense length
2576 +       buf[12] = ASC(sd);
2577 +       buf[13] = ASCQ(sd);
2578 +       return 18;
2579 +}
2580 +
2581 +
2582 +static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2583 +{
2584 +       struct fsg_lun  *curlun = fsg->curlun;
2585 +       u32             lba = get_unaligned_be32(&fsg->cmnd[2]);
2586 +       int             pmi = fsg->cmnd[8];
2587 +       u8              *buf = (u8 *) bh->buf;
2588 +
2589 +       /* Check the PMI and LBA fields */
2590 +       if (pmi > 1 || (pmi == 0 && lba != 0)) {
2591 +               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2592 +               return -EINVAL;
2593 +       }
2594 +
2595 +       put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
2596 +                                               /* Max logical block */
2597 +       put_unaligned_be32(curlun->blksize, &buf[4]);   /* Block length */
2598 +       return 8;
2599 +}
2600 +
2601 +
2602 +static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2603 +{
2604 +       struct fsg_lun  *curlun = fsg->curlun;
2605 +       int             msf = fsg->cmnd[1] & 0x02;
2606 +       u32             lba = get_unaligned_be32(&fsg->cmnd[2]);
2607 +       u8              *buf = (u8 *) bh->buf;
2608 +
2609 +       if ((fsg->cmnd[1] & ~0x02) != 0) {              /* Mask away MSF */
2610 +               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2611 +               return -EINVAL;
2612 +       }
2613 +       if (lba >= curlun->num_sectors) {
2614 +               curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
2615 +               return -EINVAL;
2616 +       }
2617 +
2618 +       memset(buf, 0, 8);
2619 +       buf[0] = 0x01;          /* 2048 bytes of user data, rest is EC */
2620 +       store_cdrom_address(&buf[4], msf, lba);
2621 +       return 8;
2622 +}
2623 +
2624 +
2625 +static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2626 +{
2627 +       struct fsg_lun  *curlun = fsg->curlun;
2628 +       int             msf = fsg->cmnd[1] & 0x02;
2629 +       int             start_track = fsg->cmnd[6];
2630 +       u8              *buf = (u8 *) bh->buf;
2631 +
2632 +       if ((fsg->cmnd[1] & ~0x02) != 0 ||              /* Mask away MSF */
2633 +                       start_track > 1) {
2634 +               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2635 +               return -EINVAL;
2636 +       }
2637 +
2638 +       memset(buf, 0, 20);
2639 +       buf[1] = (20-2);                /* TOC data length */
2640 +       buf[2] = 1;                     /* First track number */
2641 +       buf[3] = 1;                     /* Last track number */
2642 +       buf[5] = 0x16;                  /* Data track, copying allowed */
2643 +       buf[6] = 0x01;                  /* Only track is number 1 */
2644 +       store_cdrom_address(&buf[8], msf, 0);
2645 +
2646 +       buf[13] = 0x16;                 /* Lead-out track is data */
2647 +       buf[14] = 0xAA;                 /* Lead-out track number */
2648 +       store_cdrom_address(&buf[16], msf, curlun->num_sectors);
2649 +       return 20;
2650 +}
2651 +
2652 +
2653 +static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2654 +{
2655 +       struct fsg_lun  *curlun = fsg->curlun;
2656 +       int             mscmnd = fsg->cmnd[0];
2657 +       u8              *buf = (u8 *) bh->buf;
2658 +       u8              *buf0 = buf;
2659 +       int             pc, page_code;
2660 +       int             changeable_values, all_pages;
2661 +       int             valid_page = 0;
2662 +       int             len, limit;
2663 +
2664 +       if ((fsg->cmnd[1] & ~0x08) != 0) {              // Mask away DBD
2665 +               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2666 +               return -EINVAL;
2667 +       }
2668 +       pc = fsg->cmnd[2] >> 6;
2669 +       page_code = fsg->cmnd[2] & 0x3f;
2670 +       if (pc == 3) {
2671 +               curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED;
2672 +               return -EINVAL;
2673 +       }
2674 +       changeable_values = (pc == 1);
2675 +       all_pages = (page_code == 0x3f);
2676 +
2677 +       /* Write the mode parameter header.  Fixed values are: default
2678 +        * medium type, no cache control (DPOFUA), and no block descriptors.
2679 +        * The only variable value is the WriteProtect bit.  We will fill in
2680 +        * the mode data length later. */
2681 +       memset(buf, 0, 8);
2682 +       if (mscmnd == MODE_SENSE) {
2683 +               buf[2] = (curlun->ro ? 0x80 : 0x00);            // WP, DPOFUA
2684 +               buf += 4;
2685 +               limit = 255;
2686 +       } else {                        // MODE_SENSE_10
2687 +               buf[3] = (curlun->ro ? 0x80 : 0x00);            // WP, DPOFUA
2688 +               buf += 8;
2689 +               limit = 65535;          // Should really be mod_data.buflen
2690 +       }
2691 +
2692 +       /* No block descriptors */
2693 +
2694 +       /* The mode pages, in numerical order.  The only page we support
2695 +        * is the Caching page. */
2696 +       if (page_code == 0x08 || all_pages) {
2697 +               valid_page = 1;
2698 +               buf[0] = 0x08;          // Page code
2699 +               buf[1] = 10;            // Page length
2700 +               memset(buf+2, 0, 10);   // None of the fields are changeable
2701 +
2702 +               if (!changeable_values) {
2703 +                       buf[2] = 0x04;  // Write cache enable,
2704 +                                       // Read cache not disabled
2705 +                                       // No cache retention priorities
2706 +                       put_unaligned_be16(0xffff, &buf[4]);
2707 +                                       /* Don't disable prefetch */
2708 +                                       /* Minimum prefetch = 0 */
2709 +                       put_unaligned_be16(0xffff, &buf[8]);
2710 +                                       /* Maximum prefetch */
2711 +                       put_unaligned_be16(0xffff, &buf[10]);
2712 +                                       /* Maximum prefetch ceiling */
2713 +               }
2714 +               buf += 12;
2715 +       }
2716 +
2717 +       /* Check that a valid page was requested and the mode data length
2718 +        * isn't too long. */
2719 +       len = buf - buf0;
2720 +       if (!valid_page || len > limit) {
2721 +               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2722 +               return -EINVAL;
2723 +       }
2724 +
2725 +       /*  Store the mode data length */
2726 +       if (mscmnd == MODE_SENSE)
2727 +               buf0[0] = len - 1;
2728 +       else
2729 +               put_unaligned_be16(len - 2, buf0);
2730 +       return len;
2731 +}
2732 +
2733 +
2734 +static int do_start_stop(struct fsg_dev *fsg)
2735 +{
2736 +       struct fsg_lun  *curlun = fsg->curlun;
2737 +       int             loej, start;
2738 +
2739 +       if (!mod_data.removable) {
2740 +               curlun->sense_data = SS_INVALID_COMMAND;
2741 +               return -EINVAL;
2742 +       }
2743 +
2744 +       // int immed = fsg->cmnd[1] & 0x01;
2745 +       loej = fsg->cmnd[4] & 0x02;
2746 +       start = fsg->cmnd[4] & 0x01;
2747 +
2748 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
2749 +       if ((fsg->cmnd[1] & ~0x01) != 0 ||              // Mask away Immed
2750 +                       (fsg->cmnd[4] & ~0x03) != 0) {  // Mask LoEj, Start
2751 +               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2752 +               return -EINVAL;
2753 +       }
2754 +
2755 +       if (!start) {
2756 +
2757 +               /* Are we allowed to unload the media? */
2758 +               if (curlun->prevent_medium_removal) {
2759 +                       LDBG(curlun, "unload attempt prevented\n");
2760 +                       curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED;
2761 +                       return -EINVAL;
2762 +               }
2763 +               if (loej) {             // Simulate an unload/eject
2764 +                       up_read(&fsg->filesem);
2765 +                       down_write(&fsg->filesem);
2766 +                       fsg_lun_close(curlun);
2767 +                       up_write(&fsg->filesem);
2768 +                       down_read(&fsg->filesem);
2769 +               }
2770 +       } else {
2771 +
2772 +               /* Our emulation doesn't support mounting; the medium is
2773 +                * available for use as soon as it is loaded. */
2774 +               if (!fsg_lun_is_open(curlun)) {
2775 +                       curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
2776 +                       return -EINVAL;
2777 +               }
2778 +       }
2779 +#endif
2780 +       return 0;
2781 +}
2782 +
2783 +
2784 +static int do_prevent_allow(struct fsg_dev *fsg)
2785 +{
2786 +       struct fsg_lun  *curlun = fsg->curlun;
2787 +       int             prevent;
2788 +
2789 +       if (!mod_data.removable) {
2790 +               curlun->sense_data = SS_INVALID_COMMAND;
2791 +               return -EINVAL;
2792 +       }
2793 +
2794 +       prevent = fsg->cmnd[4] & 0x01;
2795 +       if ((fsg->cmnd[4] & ~0x01) != 0) {              // Mask away Prevent
2796 +               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
2797 +               return -EINVAL;
2798 +       }
2799 +
2800 +       if (curlun->prevent_medium_removal && !prevent)
2801 +               fsg_lun_fsync_sub(curlun);
2802 +       curlun->prevent_medium_removal = prevent;
2803 +       return 0;
2804 +}
2805 +
2806 +
2807 +static int do_read_format_capacities(struct fsg_dev *fsg,
2808 +                       struct fsg_buffhd *bh)
2809 +{
2810 +       struct fsg_lun  *curlun = fsg->curlun;
2811 +       u8              *buf = (u8 *) bh->buf;
2812 +
2813 +       buf[0] = buf[1] = buf[2] = 0;
2814 +       buf[3] = 8;             // Only the Current/Maximum Capacity Descriptor
2815 +       buf += 4;
2816 +
2817 +       put_unaligned_be32(curlun->num_sectors, &buf[0]);
2818 +                                               /* Number of blocks */
2819 +       put_unaligned_be32(curlun->blksize, &buf[4]);   /* Block length */
2820 +       buf[4] = 0x02;                          /* Current capacity */
2821 +       return 12;
2822 +}
2823 +
2824 +
2825 +static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh)
2826 +{
2827 +       struct fsg_lun  *curlun = fsg->curlun;
2828 +
2829 +       /* We don't support MODE SELECT */
2830 +       curlun->sense_data = SS_INVALID_COMMAND;
2831 +       return -EINVAL;
2832 +}
2833 +
2834 +
2835 +/*-------------------------------------------------------------------------*/
2836 +
2837 +static int halt_bulk_in_endpoint(struct fsg_dev *fsg)
2838 +{
2839 +       int     rc;
2840 +
2841 +       rc = fsg_set_halt(fsg, fsg->bulk_in);
2842 +       if (rc == -EAGAIN)
2843 +               VDBG(fsg, "delayed bulk-in endpoint halt\n");
2844 +       while (rc != 0) {
2845 +               if (rc != -EAGAIN) {
2846 +                       WARNING(fsg, "usb_ep_set_halt -> %d\n", rc);
2847 +                       rc = 0;
2848 +                       break;
2849 +               }
2850 +
2851 +               /* Wait for a short time and then try again */
2852 +               if (msleep_interruptible(100) != 0)
2853 +                       return -EINTR;
2854 +               rc = usb_ep_set_halt(fsg->bulk_in);
2855 +       }
2856 +       return rc;
2857 +}
2858 +
2859 +static int wedge_bulk_in_endpoint(struct fsg_dev *fsg)
2860 +{
2861 +       int     rc;
2862 +
2863 +       DBG(fsg, "bulk-in set wedge\n");
2864 +       rc = usb_ep_set_wedge(fsg->bulk_in);
2865 +       if (rc == -EAGAIN)
2866 +               VDBG(fsg, "delayed bulk-in endpoint wedge\n");
2867 +       while (rc != 0) {
2868 +               if (rc != -EAGAIN) {
2869 +                       WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc);
2870 +                       rc = 0;
2871 +                       break;
2872 +               }
2873 +
2874 +               /* Wait for a short time and then try again */
2875 +               if (msleep_interruptible(100) != 0)
2876 +                       return -EINTR;
2877 +               rc = usb_ep_set_wedge(fsg->bulk_in);
2878 +       }
2879 +       return rc;
2880 +}
2881 +
2882 +static int throw_away_data(struct fsg_dev *fsg)
2883 +{
2884 +       struct fsg_buffhd       *bh;
2885 +       u32                     amount;
2886 +       int                     rc;
2887 +
2888 +       while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY ||
2889 +                       fsg->usb_amount_left > 0) {
2890 +
2891 +               /* Throw away the data in a filled buffer */
2892 +               if (bh->state == BUF_STATE_FULL) {
2893 +                       smp_rmb();
2894 +                       bh->state = BUF_STATE_EMPTY;
2895 +                       fsg->next_buffhd_to_drain = bh->next;
2896 +
2897 +                       /* A short packet or an error ends everything */
2898 +                       if (bh->outreq->actual < bh->bulk_out_intended_length ||
2899 +                                       bh->outreq->status != 0) {
2900 +                               raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
2901 +                               return -EINTR;
2902 +                       }
2903 +                       continue;
2904 +               }
2905 +
2906 +               /* Try to submit another request if we need one */
2907 +               bh = fsg->next_buffhd_to_fill;
2908 +               if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) {
2909 +                       amount = min(fsg->usb_amount_left,
2910 +                                       (u32) mod_data.buflen);
2911 +
2912 +                       /* Except at the end of the transfer, amount will be
2913 +                        * equal to the buffer size, which is divisible by
2914 +                        * the bulk-out maxpacket size.
2915 +                        */
2916 +                       set_bulk_out_req_length(fsg, bh, amount);
2917 +                       start_transfer(fsg, fsg->bulk_out, bh->outreq,
2918 +                                       &bh->outreq_busy, &bh->state);
2919 +                       fsg->next_buffhd_to_fill = bh->next;
2920 +                       fsg->usb_amount_left -= amount;
2921 +                       continue;
2922 +               }
2923 +
2924 +               /* Otherwise wait for something to happen */
2925 +               rc = sleep_thread(fsg);
2926 +               if (rc)
2927 +                       return rc;
2928 +       }
2929 +       return 0;
2930 +}
2931 +
2932 +
2933 +static int finish_reply(struct fsg_dev *fsg)
2934 +{
2935 +       struct fsg_buffhd       *bh = fsg->next_buffhd_to_fill;
2936 +       int                     rc = 0;
2937 +
2938 +       switch (fsg->data_dir) {
2939 +       case DATA_DIR_NONE:
2940 +               break;                  // Nothing to send
2941 +
2942 +       /* If we don't know whether the host wants to read or write,
2943 +        * this must be CB or CBI with an unknown command.  We mustn't
2944 +        * try to send or receive any data.  So stall both bulk pipes
2945 +        * if we can and wait for a reset. */
2946 +       case DATA_DIR_UNKNOWN:
2947 +               if (mod_data.can_stall) {
2948 +                       fsg_set_halt(fsg, fsg->bulk_out);
2949 +                       rc = halt_bulk_in_endpoint(fsg);
2950 +               }
2951 +               break;
2952 +
2953 +       /* All but the last buffer of data must have already been sent */
2954 +       case DATA_DIR_TO_HOST:
2955 +               if (fsg->data_size == 0)
2956 +                       ;               // Nothing to send
2957 +
2958 +               /* If there's no residue, simply send the last buffer */
2959 +               else if (fsg->residue == 0) {
2960 +                       bh->inreq->zero = 0;
2961 +                       start_transfer(fsg, fsg->bulk_in, bh->inreq,
2962 +                                       &bh->inreq_busy, &bh->state);
2963 +                       fsg->next_buffhd_to_fill = bh->next;
2964 +               }
2965 +
2966 +               /* There is a residue.  For CB and CBI, simply mark the end
2967 +                * of the data with a short packet.  However, if we are
2968 +                * allowed to stall, there was no data at all (residue ==
2969 +                * data_size), and the command failed (invalid LUN or
2970 +                * sense data is set), then halt the bulk-in endpoint
2971 +                * instead. */
2972 +               else if (!transport_is_bbb()) {
2973 +                       if (mod_data.can_stall &&
2974 +                                       fsg->residue == fsg->data_size &&
2975 +       (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) {
2976 +                               bh->state = BUF_STATE_EMPTY;
2977 +                               rc = halt_bulk_in_endpoint(fsg);
2978 +                       } else {
2979 +                               bh->inreq->zero = 1;
2980 +                               start_transfer(fsg, fsg->bulk_in, bh->inreq,
2981 +                                               &bh->inreq_busy, &bh->state);
2982 +                               fsg->next_buffhd_to_fill = bh->next;
2983 +                       }
2984 +               }
2985 +
2986 +               /*
2987 +                * For Bulk-only, mark the end of the data with a short
2988 +                * packet.  If we are allowed to stall, halt the bulk-in
2989 +                * endpoint.  (Note: This violates the Bulk-Only Transport
2990 +                * specification, which requires us to pad the data if we
2991 +                * don't halt the endpoint.  Presumably nobody will mind.)
2992 +                */
2993 +               else {
2994 +                       bh->inreq->zero = 1;
2995 +                       start_transfer(fsg, fsg->bulk_in, bh->inreq,
2996 +                                       &bh->inreq_busy, &bh->state);
2997 +                       fsg->next_buffhd_to_fill = bh->next;
2998 +                       if (mod_data.can_stall)
2999 +                               rc = halt_bulk_in_endpoint(fsg);
3000 +               }
3001 +               break;
3002 +
3003 +       /* We have processed all we want from the data the host has sent.
3004 +        * There may still be outstanding bulk-out requests. */
3005 +       case DATA_DIR_FROM_HOST:
3006 +               if (fsg->residue == 0)
3007 +                       ;               // Nothing to receive
3008 +
3009 +               /* Did the host stop sending unexpectedly early? */
3010 +               else if (fsg->short_packet_received) {
3011 +                       raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
3012 +                       rc = -EINTR;
3013 +               }
3014 +
3015 +               /* We haven't processed all the incoming data.  Even though
3016 +                * we may be allowed to stall, doing so would cause a race.
3017 +                * The controller may already have ACK'ed all the remaining
3018 +                * bulk-out packets, in which case the host wouldn't see a
3019 +                * STALL.  Not realizing the endpoint was halted, it wouldn't
3020 +                * clear the halt -- leading to problems later on. */
3021 +#if 0
3022 +               else if (mod_data.can_stall) {
3023 +                       fsg_set_halt(fsg, fsg->bulk_out);
3024 +                       raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT);
3025 +                       rc = -EINTR;
3026 +               }
3027 +#endif
3028 +
3029 +               /* We can't stall.  Read in the excess data and throw it
3030 +                * all away. */
3031 +               else
3032 +                       rc = throw_away_data(fsg);
3033 +               break;
3034 +       }
3035 +       return rc;
3036 +}
3037 +
3038 +
3039 +static int send_status(struct fsg_dev *fsg)
3040 +{
3041 +       struct fsg_lun          *curlun = fsg->curlun;
3042 +       struct fsg_buffhd       *bh;
3043 +       int                     rc;
3044 +       u8                      status = US_BULK_STAT_OK;
3045 +       u32                     sd, sdinfo = 0;
3046 +
3047 +       /* Wait for the next buffer to become available */
3048 +       bh = fsg->next_buffhd_to_fill;
3049 +       while (bh->state != BUF_STATE_EMPTY) {
3050 +               rc = sleep_thread(fsg);
3051 +               if (rc)
3052 +                       return rc;
3053 +       }
3054 +
3055 +       if (curlun) {
3056 +               sd = curlun->sense_data;
3057 +               sdinfo = curlun->sense_data_info;
3058 +       } else if (fsg->bad_lun_okay)
3059 +               sd = SS_NO_SENSE;
3060 +       else
3061 +               sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
3062 +
3063 +       if (fsg->phase_error) {
3064 +               DBG(fsg, "sending phase-error status\n");
3065 +               status = US_BULK_STAT_PHASE;
3066 +               sd = SS_INVALID_COMMAND;
3067 +       } else if (sd != SS_NO_SENSE) {
3068 +               DBG(fsg, "sending command-failure status\n");
3069 +               status = US_BULK_STAT_FAIL;
3070 +               VDBG(fsg, "  sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
3071 +                               "  info x%x\n",
3072 +                               SK(sd), ASC(sd), ASCQ(sd), sdinfo);
3073 +       }
3074 +
3075 +       if (transport_is_bbb()) {
3076 +               struct bulk_cs_wrap     *csw = bh->buf;
3077 +
3078 +               /* Store and send the Bulk-only CSW */
3079 +               csw->Signature = cpu_to_le32(US_BULK_CS_SIGN);
3080 +               csw->Tag = fsg->tag;
3081 +               csw->Residue = cpu_to_le32(fsg->residue);
3082 +               csw->Status = status;
3083 +
3084 +               bh->inreq->length = US_BULK_CS_WRAP_LEN;
3085 +               bh->inreq->zero = 0;
3086 +               start_transfer(fsg, fsg->bulk_in, bh->inreq,
3087 +                               &bh->inreq_busy, &bh->state);
3088 +
3089 +       } else if (mod_data.transport_type == USB_PR_CB) {
3090 +
3091 +               /* Control-Bulk transport has no status phase! */
3092 +               return 0;
3093 +
3094 +       } else {                        // USB_PR_CBI
3095 +               struct interrupt_data   *buf = bh->buf;
3096 +
3097 +               /* Store and send the Interrupt data.  UFI sends the ASC
3098 +                * and ASCQ bytes.  Everything else sends a Type (which
3099 +                * is always 0) and the status Value. */
3100 +               if (mod_data.protocol_type == USB_SC_UFI) {
3101 +                       buf->bType = ASC(sd);
3102 +                       buf->bValue = ASCQ(sd);
3103 +               } else {
3104 +                       buf->bType = 0;
3105 +                       buf->bValue = status;
3106 +               }
3107 +               fsg->intreq->length = CBI_INTERRUPT_DATA_LEN;
3108 +
3109 +               fsg->intr_buffhd = bh;          // Point to the right buffhd
3110 +               fsg->intreq->buf = bh->inreq->buf;
3111 +               fsg->intreq->context = bh;
3112 +               start_transfer(fsg, fsg->intr_in, fsg->intreq,
3113 +                               &fsg->intreq_busy, &bh->state);
3114 +       }
3115 +
3116 +       fsg->next_buffhd_to_fill = bh->next;
3117 +       return 0;
3118 +}
3119 +
3120 +
3121 +/*-------------------------------------------------------------------------*/
3122 +
3123 +/* Check whether the command is properly formed and whether its data size
3124 + * and direction agree with the values we already have. */
3125 +static int check_command(struct fsg_dev *fsg, int cmnd_size,
3126 +               enum data_direction data_dir, unsigned int mask,
3127 +               int needs_medium, const char *name)
3128 +{
3129 +       int                     i;
3130 +       int                     lun = fsg->cmnd[1] >> 5;
3131 +       static const char       dirletter[4] = {'u', 'o', 'i', 'n'};
3132 +       char                    hdlen[20];
3133 +       struct fsg_lun          *curlun;
3134 +
3135 +       /* Adjust the expected cmnd_size for protocol encapsulation padding.
3136 +        * Transparent SCSI doesn't pad. */
3137 +       if (protocol_is_scsi())
3138 +               ;
3139 +
3140 +       /* There's some disagreement as to whether RBC pads commands or not.
3141 +        * We'll play it safe and accept either form. */
3142 +       else if (mod_data.protocol_type == USB_SC_RBC) {
3143 +               if (fsg->cmnd_size == 12)
3144 +                       cmnd_size = 12;
3145 +
3146 +       /* All the other protocols pad to 12 bytes */
3147 +       } else
3148 +               cmnd_size = 12;
3149 +
3150 +       hdlen[0] = 0;
3151 +       if (fsg->data_dir != DATA_DIR_UNKNOWN)
3152 +               sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir],
3153 +                               fsg->data_size);
3154 +       VDBG(fsg, "SCSI command: %s;  Dc=%d, D%c=%u;  Hc=%d%s\n",
3155 +                       name, cmnd_size, dirletter[(int) data_dir],
3156 +                       fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen);
3157 +
3158 +       /* We can't reply at all until we know the correct data direction
3159 +        * and size. */
3160 +       if (fsg->data_size_from_cmnd == 0)
3161 +               data_dir = DATA_DIR_NONE;
3162 +       if (fsg->data_dir == DATA_DIR_UNKNOWN) {        // CB or CBI
3163 +               fsg->data_dir = data_dir;
3164 +               fsg->data_size = fsg->data_size_from_cmnd;
3165 +
3166 +       } else {                                        // Bulk-only
3167 +               if (fsg->data_size < fsg->data_size_from_cmnd) {
3168 +
3169 +                       /* Host data size < Device data size is a phase error.
3170 +                        * Carry out the command, but only transfer as much
3171 +                        * as we are allowed. */
3172 +                       fsg->data_size_from_cmnd = fsg->data_size;
3173 +                       fsg->phase_error = 1;
3174 +               }
3175 +       }
3176 +       fsg->residue = fsg->usb_amount_left = fsg->data_size;
3177 +
3178 +       /* Conflicting data directions is a phase error */
3179 +       if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) {
3180 +               fsg->phase_error = 1;
3181 +               return -EINVAL;
3182 +       }
3183 +
3184 +       /* Verify the length of the command itself */
3185 +       if (cmnd_size != fsg->cmnd_size) {
3186 +
3187 +               /* Special case workaround: There are plenty of buggy SCSI
3188 +                * implementations. Many have issues with cbw->Length
3189 +                * field passing a wrong command size. For those cases we
3190 +                * always try to work around the problem by using the length
3191 +                * sent by the host side provided it is at least as large
3192 +                * as the correct command length.
3193 +                * Examples of such cases would be MS-Windows, which issues
3194 +                * REQUEST SENSE with cbw->Length == 12 where it should
3195 +                * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and
3196 +                * REQUEST SENSE with cbw->Length == 10 where it should
3197 +                * be 6 as well.
3198 +                */
3199 +               if (cmnd_size <= fsg->cmnd_size) {
3200 +                       DBG(fsg, "%s is buggy! Expected length %d "
3201 +                                       "but we got %d\n", name,
3202 +                                       cmnd_size, fsg->cmnd_size);
3203 +                       cmnd_size = fsg->cmnd_size;
3204 +               } else {
3205 +                       fsg->phase_error = 1;
3206 +                       return -EINVAL;
3207 +               }
3208 +       }
3209 +
3210 +       /* Check that the LUN values are consistent */
3211 +       if (transport_is_bbb()) {
3212 +               if (fsg->lun != lun)
3213 +                       DBG(fsg, "using LUN %d from CBW, "
3214 +                                       "not LUN %d from CDB\n",
3215 +                                       fsg->lun, lun);
3216 +       }
3217 +
3218 +       /* Check the LUN */
3219 +       curlun = fsg->curlun;
3220 +       if (curlun) {
3221 +               if (fsg->cmnd[0] != REQUEST_SENSE) {
3222 +                       curlun->sense_data = SS_NO_SENSE;
3223 +                       curlun->sense_data_info = 0;
3224 +                       curlun->info_valid = 0;
3225 +               }
3226 +       } else {
3227 +               fsg->bad_lun_okay = 0;
3228 +
3229 +               /* INQUIRY and REQUEST SENSE commands are explicitly allowed
3230 +                * to use unsupported LUNs; all others may not. */
3231 +               if (fsg->cmnd[0] != INQUIRY &&
3232 +                               fsg->cmnd[0] != REQUEST_SENSE) {
3233 +                       DBG(fsg, "unsupported LUN %d\n", fsg->lun);
3234 +                       return -EINVAL;
3235 +               }
3236 +       }
3237 +
3238 +       /* If a unit attention condition exists, only INQUIRY and
3239 +        * REQUEST SENSE commands are allowed; anything else must fail. */
3240 +       if (curlun && curlun->unit_attention_data != SS_NO_SENSE &&
3241 +                       fsg->cmnd[0] != INQUIRY &&
3242 +                       fsg->cmnd[0] != REQUEST_SENSE) {
3243 +               curlun->sense_data = curlun->unit_attention_data;
3244 +               curlun->unit_attention_data = SS_NO_SENSE;
3245 +               return -EINVAL;
3246 +       }
3247 +
3248 +       /* Check that only command bytes listed in the mask are non-zero */
3249 +       fsg->cmnd[1] &= 0x1f;                   // Mask away the LUN
3250 +       for (i = 1; i < cmnd_size; ++i) {
3251 +               if (fsg->cmnd[i] && !(mask & (1 << i))) {
3252 +                       if (curlun)
3253 +                               curlun->sense_data = SS_INVALID_FIELD_IN_CDB;
3254 +                       return -EINVAL;
3255 +               }
3256 +       }
3257 +
3258 +       /* If the medium isn't mounted and the command needs to access
3259 +        * it, return an error. */
3260 +       if (curlun && !fsg_lun_is_open(curlun) && needs_medium) {
3261 +               curlun->sense_data = SS_MEDIUM_NOT_PRESENT;
3262 +               return -EINVAL;
3263 +       }
3264 +
3265 +       return 0;
3266 +}
3267 +
3268 +/* wrapper of check_command for data size in blocks handling */
3269 +static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size,
3270 +               enum data_direction data_dir, unsigned int mask,
3271 +               int needs_medium, const char *name)
3272 +{
3273 +       if (fsg->curlun)
3274 +               fsg->data_size_from_cmnd <<= fsg->curlun->blkbits;
3275 +       return check_command(fsg, cmnd_size, data_dir,
3276 +                       mask, needs_medium, name);
3277 +}
3278 +
3279 +static int do_scsi_command(struct fsg_dev *fsg)
3280 +{
3281 +       struct fsg_buffhd       *bh;
3282 +       int                     rc;
3283 +       int                     reply = -EINVAL;
3284 +       int                     i;
3285 +       static char             unknown[16];
3286 +
3287 +       dump_cdb(fsg);
3288 +
3289 +       /* Wait for the next buffer to become available for data or status */
3290 +       bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill;
3291 +       while (bh->state != BUF_STATE_EMPTY) {
3292 +               rc = sleep_thread(fsg);
3293 +               if (rc)
3294 +                       return rc;
3295 +       }
3296 +       fsg->phase_error = 0;
3297 +       fsg->short_packet_received = 0;
3298 +
3299 +       down_read(&fsg->filesem);       // We're using the backing file
3300 +       switch (fsg->cmnd[0]) {
3301 +
3302 +       case INQUIRY:
3303 +               fsg->data_size_from_cmnd = fsg->cmnd[4];
3304 +               if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3305 +                               (1<<4), 0,
3306 +                               "INQUIRY")) == 0)
3307 +                       reply = do_inquiry(fsg, bh);
3308 +               break;
3309 +
3310 +       case MODE_SELECT:
3311 +               fsg->data_size_from_cmnd = fsg->cmnd[4];
3312 +               if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST,
3313 +                               (1<<1) | (1<<4), 0,
3314 +                               "MODE SELECT(6)")) == 0)
3315 +                       reply = do_mode_select(fsg, bh);
3316 +               break;
3317 +
3318 +       case MODE_SELECT_10:
3319 +               fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3320 +               if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
3321 +                               (1<<1) | (3<<7), 0,
3322 +                               "MODE SELECT(10)")) == 0)
3323 +                       reply = do_mode_select(fsg, bh);
3324 +               break;
3325 +
3326 +       case MODE_SENSE:
3327 +               fsg->data_size_from_cmnd = fsg->cmnd[4];
3328 +               if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3329 +                               (1<<1) | (1<<2) | (1<<4), 0,
3330 +                               "MODE SENSE(6)")) == 0)
3331 +                       reply = do_mode_sense(fsg, bh);
3332 +               break;
3333 +
3334 +       case MODE_SENSE_10:
3335 +               fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3336 +               if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3337 +                               (1<<1) | (1<<2) | (3<<7), 0,
3338 +                               "MODE SENSE(10)")) == 0)
3339 +                       reply = do_mode_sense(fsg, bh);
3340 +               break;
3341 +
3342 +       case ALLOW_MEDIUM_REMOVAL:
3343 +               fsg->data_size_from_cmnd = 0;
3344 +               if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
3345 +                               (1<<4), 0,
3346 +                               "PREVENT-ALLOW MEDIUM REMOVAL")) == 0)
3347 +                       reply = do_prevent_allow(fsg);
3348 +               break;
3349 +
3350 +       case READ_6:
3351 +               i = fsg->cmnd[4];
3352 +               fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
3353 +               if ((reply = check_command_size_in_blocks(fsg, 6,
3354 +                               DATA_DIR_TO_HOST,
3355 +                               (7<<1) | (1<<4), 1,
3356 +                               "READ(6)")) == 0)
3357 +                       reply = do_read(fsg);
3358 +               break;
3359 +
3360 +       case READ_10:
3361 +               fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3362 +               if ((reply = check_command_size_in_blocks(fsg, 10,
3363 +                               DATA_DIR_TO_HOST,
3364 +                               (1<<1) | (0xf<<2) | (3<<7), 1,
3365 +                               "READ(10)")) == 0)
3366 +                       reply = do_read(fsg);
3367 +               break;
3368 +
3369 +       case READ_12:
3370 +               fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
3371 +               if ((reply = check_command_size_in_blocks(fsg, 12,
3372 +                               DATA_DIR_TO_HOST,
3373 +                               (1<<1) | (0xf<<2) | (0xf<<6), 1,
3374 +                               "READ(12)")) == 0)
3375 +                       reply = do_read(fsg);
3376 +               break;
3377 +
3378 +       case READ_CAPACITY:
3379 +               fsg->data_size_from_cmnd = 8;
3380 +               if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3381 +                               (0xf<<2) | (1<<8), 1,
3382 +                               "READ CAPACITY")) == 0)
3383 +                       reply = do_read_capacity(fsg, bh);
3384 +               break;
3385 +
3386 +       case READ_HEADER:
3387 +               if (!mod_data.cdrom)
3388 +                       goto unknown_cmnd;
3389 +               fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3390 +               if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3391 +                               (3<<7) | (0x1f<<1), 1,
3392 +                               "READ HEADER")) == 0)
3393 +                       reply = do_read_header(fsg, bh);
3394 +               break;
3395 +
3396 +       case READ_TOC:
3397 +               if (!mod_data.cdrom)
3398 +                       goto unknown_cmnd;
3399 +               fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3400 +               if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3401 +                               (7<<6) | (1<<1), 1,
3402 +                               "READ TOC")) == 0)
3403 +                       reply = do_read_toc(fsg, bh);
3404 +               break;
3405 +
3406 +       case READ_FORMAT_CAPACITIES:
3407 +               fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3408 +               if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
3409 +                               (3<<7), 1,
3410 +                               "READ FORMAT CAPACITIES")) == 0)
3411 +                       reply = do_read_format_capacities(fsg, bh);
3412 +               break;
3413 +
3414 +       case REQUEST_SENSE:
3415 +               fsg->data_size_from_cmnd = fsg->cmnd[4];
3416 +               if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST,
3417 +                               (1<<4), 0,
3418 +                               "REQUEST SENSE")) == 0)
3419 +                       reply = do_request_sense(fsg, bh);
3420 +               break;
3421 +
3422 +       case START_STOP:
3423 +               fsg->data_size_from_cmnd = 0;
3424 +               if ((reply = check_command(fsg, 6, DATA_DIR_NONE,
3425 +                               (1<<1) | (1<<4), 0,
3426 +                               "START-STOP UNIT")) == 0)
3427 +                       reply = do_start_stop(fsg);
3428 +               break;
3429 +
3430 +       case SYNCHRONIZE_CACHE:
3431 +               fsg->data_size_from_cmnd = 0;
3432 +               if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
3433 +                               (0xf<<2) | (3<<7), 1,
3434 +                               "SYNCHRONIZE CACHE")) == 0)
3435 +                       reply = do_synchronize_cache(fsg);
3436 +               break;
3437 +
3438 +       case TEST_UNIT_READY:
3439 +               fsg->data_size_from_cmnd = 0;
3440 +               reply = check_command(fsg, 6, DATA_DIR_NONE,
3441 +                               0, 1,
3442 +                               "TEST UNIT READY");
3443 +               break;
3444 +
3445 +       /* Although optional, this command is used by MS-Windows.  We
3446 +        * support a minimal version: BytChk must be 0. */
3447 +       case VERIFY:
3448 +               fsg->data_size_from_cmnd = 0;
3449 +               if ((reply = check_command(fsg, 10, DATA_DIR_NONE,
3450 +                               (1<<1) | (0xf<<2) | (3<<7), 1,
3451 +                               "VERIFY")) == 0)
3452 +                       reply = do_verify(fsg);
3453 +               break;
3454 +
3455 +       case WRITE_6:
3456 +               i = fsg->cmnd[4];
3457 +               fsg->data_size_from_cmnd = (i == 0) ? 256 : i;
3458 +               if ((reply = check_command_size_in_blocks(fsg, 6,
3459 +                               DATA_DIR_FROM_HOST,
3460 +                               (7<<1) | (1<<4), 1,
3461 +                               "WRITE(6)")) == 0)
3462 +                       reply = do_write(fsg);
3463 +               break;
3464 +
3465 +       case WRITE_10:
3466 +               fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
3467 +               if ((reply = check_command_size_in_blocks(fsg, 10,
3468 +                               DATA_DIR_FROM_HOST,
3469 +                               (1<<1) | (0xf<<2) | (3<<7), 1,
3470 +                               "WRITE(10)")) == 0)
3471 +                       reply = do_write(fsg);
3472 +               break;
3473 +
3474 +       case WRITE_12:
3475 +               fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]);
3476 +               if ((reply = check_command_size_in_blocks(fsg, 12,
3477 +                               DATA_DIR_FROM_HOST,
3478 +                               (1<<1) | (0xf<<2) | (0xf<<6), 1,
3479 +                               "WRITE(12)")) == 0)
3480 +                       reply = do_write(fsg);
3481 +               break;
3482 +
3483 +       /* Some mandatory commands that we recognize but don't implement.
3484 +        * They don't mean much in this setting.  It's left as an exercise
3485 +        * for anyone interested to implement RESERVE and RELEASE in terms
3486 +        * of Posix locks. */
3487 +       case FORMAT_UNIT:
3488 +       case RELEASE:
3489 +       case RESERVE:
3490 +       case SEND_DIAGNOSTIC:
3491 +               // Fall through
3492 +
3493 +       default:
3494 + unknown_cmnd:
3495 +               fsg->data_size_from_cmnd = 0;
3496 +               sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]);
3497 +               if ((reply = check_command(fsg, fsg->cmnd_size,
3498 +                               DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) {
3499 +                       fsg->curlun->sense_data = SS_INVALID_COMMAND;
3500 +                       reply = -EINVAL;
3501 +               }
3502 +               break;
3503 +       }
3504 +       up_read(&fsg->filesem);
3505 +
3506 +       if (reply == -EINTR || signal_pending(current))
3507 +               return -EINTR;
3508 +
3509 +       /* Set up the single reply buffer for finish_reply() */
3510 +       if (reply == -EINVAL)
3511 +               reply = 0;              // Error reply length
3512 +       if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) {
3513 +               reply = min((u32) reply, fsg->data_size_from_cmnd);
3514 +               bh->inreq->length = reply;
3515 +               bh->state = BUF_STATE_FULL;
3516 +               fsg->residue -= reply;
3517 +       }                               // Otherwise it's already set
3518 +
3519 +       return 0;
3520 +}
3521 +
3522 +
3523 +/*-------------------------------------------------------------------------*/
3524 +
3525 +static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh)
3526 +{
3527 +       struct usb_request              *req = bh->outreq;
3528 +       struct bulk_cb_wrap     *cbw = req->buf;
3529 +
3530 +       /* Was this a real packet?  Should it be ignored? */
3531 +       if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
3532 +               return -EINVAL;
3533 +
3534 +       /* Is the CBW valid? */
3535 +       if (req->actual != US_BULK_CB_WRAP_LEN ||
3536 +                       cbw->Signature != cpu_to_le32(
3537 +                               US_BULK_CB_SIGN)) {
3538 +               DBG(fsg, "invalid CBW: len %u sig 0x%x\n",
3539 +                               req->actual,
3540 +                               le32_to_cpu(cbw->Signature));
3541 +
3542 +               /* The Bulk-only spec says we MUST stall the IN endpoint
3543 +                * (6.6.1), so it's unavoidable.  It also says we must
3544 +                * retain this state until the next reset, but there's
3545 +                * no way to tell the controller driver it should ignore
3546 +                * Clear-Feature(HALT) requests.
3547 +                *
3548 +                * We aren't required to halt the OUT endpoint; instead
3549 +                * we can simply accept and discard any data received
3550 +                * until the next reset. */
3551 +               wedge_bulk_in_endpoint(fsg);
3552 +               set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
3553 +               return -EINVAL;
3554 +       }
3555 +
3556 +       /* Is the CBW meaningful? */
3557 +       if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN ||
3558 +                       cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) {
3559 +               DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, "
3560 +                               "cmdlen %u\n",
3561 +                               cbw->Lun, cbw->Flags, cbw->Length);
3562 +
3563 +               /* We can do anything we want here, so let's stall the
3564 +                * bulk pipes if we are allowed to. */
3565 +               if (mod_data.can_stall) {
3566 +                       fsg_set_halt(fsg, fsg->bulk_out);
3567 +                       halt_bulk_in_endpoint(fsg);
3568 +               }
3569 +               return -EINVAL;
3570 +       }
3571 +
3572 +       /* Save the command for later */
3573 +       fsg->cmnd_size = cbw->Length;
3574 +       memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size);
3575 +       if (cbw->Flags & US_BULK_FLAG_IN)
3576 +               fsg->data_dir = DATA_DIR_TO_HOST;
3577 +       else
3578 +               fsg->data_dir = DATA_DIR_FROM_HOST;
3579 +       fsg->data_size = le32_to_cpu(cbw->DataTransferLength);
3580 +       if (fsg->data_size == 0)
3581 +               fsg->data_dir = DATA_DIR_NONE;
3582 +       fsg->lun = cbw->Lun;
3583 +       fsg->tag = cbw->Tag;
3584 +       return 0;
3585 +}
3586 +
3587 +
3588 +static int get_next_command(struct fsg_dev *fsg)
3589 +{
3590 +       struct fsg_buffhd       *bh;
3591 +       int                     rc = 0;
3592 +
3593 +       if (transport_is_bbb()) {
3594 +
3595 +               /* Wait for the next buffer to become available */
3596 +               bh = fsg->next_buffhd_to_fill;
3597 +               while (bh->state != BUF_STATE_EMPTY) {
3598 +                       rc = sleep_thread(fsg);
3599 +                       if (rc)
3600 +                               return rc;
3601 +               }
3602 +
3603 +               /* Queue a request to read a Bulk-only CBW */
3604 +               set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN);
3605 +               start_transfer(fsg, fsg->bulk_out, bh->outreq,
3606 +                               &bh->outreq_busy, &bh->state);
3607 +
3608 +               /* We will drain the buffer in software, which means we
3609 +                * can reuse it for the next filling.  No need to advance
3610 +                * next_buffhd_to_fill. */
3611 +
3612 +               /* Wait for the CBW to arrive */
3613 +               while (bh->state != BUF_STATE_FULL) {
3614 +                       rc = sleep_thread(fsg);
3615 +                       if (rc)
3616 +                               return rc;
3617 +               }
3618 +               smp_rmb();
3619 +               rc = received_cbw(fsg, bh);
3620 +               bh->state = BUF_STATE_EMPTY;
3621 +
3622 +       } else {                // USB_PR_CB or USB_PR_CBI
3623 +
3624 +               /* Wait for the next command to arrive */
3625 +               while (fsg->cbbuf_cmnd_size == 0) {
3626 +                       rc = sleep_thread(fsg);
3627 +                       if (rc)
3628 +                               return rc;
3629 +               }
3630 +
3631 +               /* Is the previous status interrupt request still busy?
3632 +                * The host is allowed to skip reading the status,
3633 +                * so we must cancel it. */
3634 +               if (fsg->intreq_busy)
3635 +                       usb_ep_dequeue(fsg->intr_in, fsg->intreq);
3636 +
3637 +               /* Copy the command and mark the buffer empty */
3638 +               fsg->data_dir = DATA_DIR_UNKNOWN;
3639 +               spin_lock_irq(&fsg->lock);
3640 +               fsg->cmnd_size = fsg->cbbuf_cmnd_size;
3641 +               memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size);
3642 +               fsg->cbbuf_cmnd_size = 0;
3643 +               spin_unlock_irq(&fsg->lock);
3644 +
3645 +               /* Use LUN from the command */
3646 +               fsg->lun = fsg->cmnd[1] >> 5;
3647 +       }
3648 +
3649 +       /* Update current lun */
3650 +       if (fsg->lun >= 0 && fsg->lun < fsg->nluns)
3651 +               fsg->curlun = &fsg->luns[fsg->lun];
3652 +       else
3653 +               fsg->curlun = NULL;
3654 +
3655 +       return rc;
3656 +}
3657 +
3658 +
3659 +/*-------------------------------------------------------------------------*/
3660 +
3661 +static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep,
3662 +               const struct usb_endpoint_descriptor *d)
3663 +{
3664 +       int     rc;
3665 +
3666 +       ep->driver_data = fsg;
3667 +       ep->desc = d;
3668 +       rc = usb_ep_enable(ep);
3669 +       if (rc)
3670 +               ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc);
3671 +       return rc;
3672 +}
3673 +
3674 +static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep,
3675 +               struct usb_request **preq)
3676 +{
3677 +       *preq = usb_ep_alloc_request(ep, GFP_ATOMIC);
3678 +       if (*preq)
3679 +               return 0;
3680 +       ERROR(fsg, "can't allocate request for %s\n", ep->name);
3681 +       return -ENOMEM;
3682 +}
3683 +
3684 +/*
3685 + * Reset interface setting and re-init endpoint state (toggle etc).
3686 + * Call with altsetting < 0 to disable the interface.  The only other
3687 + * available altsetting is 0, which enables the interface.
3688 + */
3689 +static int do_set_interface(struct fsg_dev *fsg, int altsetting)
3690 +{
3691 +       int     rc = 0;
3692 +       int     i;
3693 +       const struct usb_endpoint_descriptor    *d;
3694 +
3695 +       if (fsg->running)
3696 +               DBG(fsg, "reset interface\n");
3697 +
3698 +reset:
3699 +       /* Deallocate the requests */
3700 +       for (i = 0; i < fsg_num_buffers; ++i) {
3701 +               struct fsg_buffhd *bh = &fsg->buffhds[i];
3702 +
3703 +               if (bh->inreq) {
3704 +                       usb_ep_free_request(fsg->bulk_in, bh->inreq);
3705 +                       bh->inreq = NULL;
3706 +               }
3707 +               if (bh->outreq) {
3708 +                       usb_ep_free_request(fsg->bulk_out, bh->outreq);
3709 +                       bh->outreq = NULL;
3710 +               }
3711 +       }
3712 +       if (fsg->intreq) {
3713 +               usb_ep_free_request(fsg->intr_in, fsg->intreq);
3714 +               fsg->intreq = NULL;
3715 +       }
3716 +
3717 +       /* Disable the endpoints */
3718 +       if (fsg->bulk_in_enabled) {
3719 +               usb_ep_disable(fsg->bulk_in);
3720 +               fsg->bulk_in_enabled = 0;
3721 +       }
3722 +       if (fsg->bulk_out_enabled) {
3723 +               usb_ep_disable(fsg->bulk_out);
3724 +               fsg->bulk_out_enabled = 0;
3725 +       }
3726 +       if (fsg->intr_in_enabled) {
3727 +               usb_ep_disable(fsg->intr_in);
3728 +               fsg->intr_in_enabled = 0;
3729 +       }
3730 +
3731 +       fsg->running = 0;
3732 +       if (altsetting < 0 || rc != 0)
3733 +               return rc;
3734 +
3735 +       DBG(fsg, "set interface %d\n", altsetting);
3736 +
3737 +       /* Enable the endpoints */
3738 +       d = fsg_ep_desc(fsg->gadget,
3739 +                       &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc,
3740 +                       &fsg_ss_bulk_in_desc);
3741 +       if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0)
3742 +               goto reset;
3743 +       fsg->bulk_in_enabled = 1;
3744 +
3745 +       d = fsg_ep_desc(fsg->gadget,
3746 +                       &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc,
3747 +                       &fsg_ss_bulk_out_desc);
3748 +       if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0)
3749 +               goto reset;
3750 +       fsg->bulk_out_enabled = 1;
3751 +       fsg->bulk_out_maxpacket = usb_endpoint_maxp(d);
3752 +       clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags);
3753 +
3754 +       if (transport_is_cbi()) {
3755 +               d = fsg_ep_desc(fsg->gadget,
3756 +                               &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc,
3757 +                               &fsg_ss_intr_in_desc);
3758 +               if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0)
3759 +                       goto reset;
3760 +               fsg->intr_in_enabled = 1;
3761 +       }
3762 +
3763 +       /* Allocate the requests */
3764 +       for (i = 0; i < fsg_num_buffers; ++i) {
3765 +               struct fsg_buffhd       *bh = &fsg->buffhds[i];
3766 +
3767 +               if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0)
3768 +                       goto reset;
3769 +               if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0)
3770 +                       goto reset;
3771 +               bh->inreq->buf = bh->outreq->buf = bh->buf;
3772 +               bh->inreq->context = bh->outreq->context = bh;
3773 +               bh->inreq->complete = bulk_in_complete;
3774 +               bh->outreq->complete = bulk_out_complete;
3775 +       }
3776 +       if (transport_is_cbi()) {
3777 +               if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0)
3778 +                       goto reset;
3779 +               fsg->intreq->complete = intr_in_complete;
3780 +       }
3781 +
3782 +       fsg->running = 1;
3783 +       for (i = 0; i < fsg->nluns; ++i)
3784 +               fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
3785 +       return rc;
3786 +}
3787 +
3788 +
3789 +/*
3790 + * Change our operational configuration.  This code must agree with the code
3791 + * that returns config descriptors, and with interface altsetting code.
3792 + *
3793 + * It's also responsible for power management interactions.  Some
3794 + * configurations might not work with our current power sources.
3795 + * For now we just assume the gadget is always self-powered.
3796 + */
3797 +static int do_set_config(struct fsg_dev *fsg, u8 new_config)
3798 +{
3799 +       int     rc = 0;
3800 +
3801 +       /* Disable the single interface */
3802 +       if (fsg->config != 0) {
3803 +               DBG(fsg, "reset config\n");
3804 +               fsg->config = 0;
3805 +               rc = do_set_interface(fsg, -1);
3806 +       }
3807 +
3808 +       /* Enable the interface */
3809 +       if (new_config != 0) {
3810 +               fsg->config = new_config;
3811 +               if ((rc = do_set_interface(fsg, 0)) != 0)
3812 +                       fsg->config = 0;        // Reset on errors
3813 +               else
3814 +                       INFO(fsg, "%s config #%d\n",
3815 +                            usb_speed_string(fsg->gadget->speed),
3816 +                            fsg->config);
3817 +       }
3818 +       return rc;
3819 +}
3820 +
3821 +
3822 +/*-------------------------------------------------------------------------*/
3823 +
3824 +static void handle_exception(struct fsg_dev *fsg)
3825 +{
3826 +       siginfo_t               info;
3827 +       int                     sig;
3828 +       int                     i;
3829 +       int                     num_active;
3830 +       struct fsg_buffhd       *bh;
3831 +       enum fsg_state          old_state;
3832 +       u8                      new_config;
3833 +       struct fsg_lun          *curlun;
3834 +       unsigned int            exception_req_tag;
3835 +       int                     rc;
3836 +
3837 +       /* Clear the existing signals.  Anything but SIGUSR1 is converted
3838 +        * into a high-priority EXIT exception. */
3839 +       for (;;) {
3840 +               sig = dequeue_signal_lock(current, &current->blocked, &info);
3841 +               if (!sig)
3842 +                       break;
3843 +               if (sig != SIGUSR1) {
3844 +                       if (fsg->state < FSG_STATE_EXIT)
3845 +                               DBG(fsg, "Main thread exiting on signal\n");
3846 +                       raise_exception(fsg, FSG_STATE_EXIT);
3847 +               }
3848 +       }
3849 +
3850 +       /* Cancel all the pending transfers */
3851 +       if (fsg->intreq_busy)
3852 +               usb_ep_dequeue(fsg->intr_in, fsg->intreq);
3853 +       for (i = 0; i < fsg_num_buffers; ++i) {
3854 +               bh = &fsg->buffhds[i];
3855 +               if (bh->inreq_busy)
3856 +                       usb_ep_dequeue(fsg->bulk_in, bh->inreq);
3857 +               if (bh->outreq_busy)
3858 +                       usb_ep_dequeue(fsg->bulk_out, bh->outreq);
3859 +       }
3860 +
3861 +       /* Wait until everything is idle */
3862 +       for (;;) {
3863 +               num_active = fsg->intreq_busy;
3864 +               for (i = 0; i < fsg_num_buffers; ++i) {
3865 +                       bh = &fsg->buffhds[i];
3866 +                       num_active += bh->inreq_busy + bh->outreq_busy;
3867 +               }
3868 +               if (num_active == 0)
3869 +                       break;
3870 +               if (sleep_thread(fsg))
3871 +                       return;
3872 +       }
3873 +
3874 +       /* Clear out the controller's fifos */
3875 +       if (fsg->bulk_in_enabled)
3876 +               usb_ep_fifo_flush(fsg->bulk_in);
3877 +       if (fsg->bulk_out_enabled)
3878 +               usb_ep_fifo_flush(fsg->bulk_out);
3879 +       if (fsg->intr_in_enabled)
3880 +               usb_ep_fifo_flush(fsg->intr_in);
3881 +
3882 +       /* Reset the I/O buffer states and pointers, the SCSI
3883 +        * state, and the exception.  Then invoke the handler. */
3884 +       spin_lock_irq(&fsg->lock);
3885 +
3886 +       for (i = 0; i < fsg_num_buffers; ++i) {
3887 +               bh = &fsg->buffhds[i];
3888 +               bh->state = BUF_STATE_EMPTY;
3889 +       }
3890 +       fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain =
3891 +                       &fsg->buffhds[0];
3892 +
3893 +       exception_req_tag = fsg->exception_req_tag;
3894 +       new_config = fsg->new_config;
3895 +       old_state = fsg->state;
3896 +
3897 +       if (old_state == FSG_STATE_ABORT_BULK_OUT)
3898 +               fsg->state = FSG_STATE_STATUS_PHASE;
3899 +       else {
3900 +               for (i = 0; i < fsg->nluns; ++i) {
3901 +                       curlun = &fsg->luns[i];
3902 +                       curlun->prevent_medium_removal = 0;
3903 +                       curlun->sense_data = curlun->unit_attention_data =
3904 +                                       SS_NO_SENSE;
3905 +                       curlun->sense_data_info = 0;
3906 +                       curlun->info_valid = 0;
3907 +               }
3908 +               fsg->state = FSG_STATE_IDLE;
3909 +       }
3910 +       spin_unlock_irq(&fsg->lock);
3911 +
3912 +       /* Carry out any extra actions required for the exception */
3913 +       switch (old_state) {
3914 +       default:
3915 +               break;
3916 +
3917 +       case FSG_STATE_ABORT_BULK_OUT:
3918 +               send_status(fsg);
3919 +               spin_lock_irq(&fsg->lock);
3920 +               if (fsg->state == FSG_STATE_STATUS_PHASE)
3921 +                       fsg->state = FSG_STATE_IDLE;
3922 +               spin_unlock_irq(&fsg->lock);
3923 +               break;
3924 +
3925 +       case FSG_STATE_RESET:
3926 +               /* In case we were forced against our will to halt a
3927 +                * bulk endpoint, clear the halt now.  (The SuperH UDC
3928 +                * requires this.) */
3929 +               if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags))
3930 +                       usb_ep_clear_halt(fsg->bulk_in);
3931 +
3932 +               if (transport_is_bbb()) {
3933 +                       if (fsg->ep0_req_tag == exception_req_tag)
3934 +                               ep0_queue(fsg); // Complete the status stage
3935 +
3936 +               } else if (transport_is_cbi())
3937 +                       send_status(fsg);       // Status by interrupt pipe
3938 +
3939 +               /* Technically this should go here, but it would only be
3940 +                * a waste of time.  Ditto for the INTERFACE_CHANGE and
3941 +                * CONFIG_CHANGE cases. */
3942 +               // for (i = 0; i < fsg->nluns; ++i)
3943 +               //      fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED;
3944 +               break;
3945 +
3946 +       case FSG_STATE_INTERFACE_CHANGE:
3947 +               rc = do_set_interface(fsg, 0);
3948 +               if (fsg->ep0_req_tag != exception_req_tag)
3949 +                       break;
3950 +               if (rc != 0)                    // STALL on errors
3951 +                       fsg_set_halt(fsg, fsg->ep0);
3952 +               else                            // Complete the status stage
3953 +                       ep0_queue(fsg);
3954 +               break;
3955 +
3956 +       case FSG_STATE_CONFIG_CHANGE:
3957 +               rc = do_set_config(fsg, new_config);
3958 +               if (fsg->ep0_req_tag != exception_req_tag)
3959 +                       break;
3960 +               if (rc != 0)                    // STALL on errors
3961 +                       fsg_set_halt(fsg, fsg->ep0);
3962 +               else                            // Complete the status stage
3963 +                       ep0_queue(fsg);
3964 +               break;
3965 +
3966 +       case FSG_STATE_DISCONNECT:
3967 +               for (i = 0; i < fsg->nluns; ++i)
3968 +                       fsg_lun_fsync_sub(fsg->luns + i);
3969 +               do_set_config(fsg, 0);          // Unconfigured state
3970 +               break;
3971 +
3972 +       case FSG_STATE_EXIT:
3973 +       case FSG_STATE_TERMINATED:
3974 +               do_set_config(fsg, 0);                  // Free resources
3975 +               spin_lock_irq(&fsg->lock);
3976 +               fsg->state = FSG_STATE_TERMINATED;      // Stop the thread
3977 +               spin_unlock_irq(&fsg->lock);
3978 +               break;
3979 +       }
3980 +}
3981 +
3982 +
3983 +/*-------------------------------------------------------------------------*/
3984 +
3985 +static int fsg_main_thread(void *fsg_)
3986 +{
3987 +       struct fsg_dev          *fsg = fsg_;
3988 +
3989 +       /* Allow the thread to be killed by a signal, but set the signal mask
3990 +        * to block everything but INT, TERM, KILL, and USR1. */
3991 +       allow_signal(SIGINT);
3992 +       allow_signal(SIGTERM);
3993 +       allow_signal(SIGKILL);
3994 +       allow_signal(SIGUSR1);
3995 +
3996 +       /* Allow the thread to be frozen */
3997 +       set_freezable();
3998 +
3999 +       /* Arrange for userspace references to be interpreted as kernel
4000 +        * pointers.  That way we can pass a kernel pointer to a routine
4001 +        * that expects a __user pointer and it will work okay. */
4002 +       set_fs(get_ds());
4003 +
4004 +       /* The main loop */
4005 +       while (fsg->state != FSG_STATE_TERMINATED) {
4006 +               if (exception_in_progress(fsg) || signal_pending(current)) {
4007 +                       handle_exception(fsg);
4008 +                       continue;
4009 +               }
4010 +
4011 +               if (!fsg->running) {
4012 +                       sleep_thread(fsg);
4013 +                       continue;
4014 +               }
4015 +
4016 +               if (get_next_command(fsg))
4017 +                       continue;
4018 +
4019 +               spin_lock_irq(&fsg->lock);
4020 +               if (!exception_in_progress(fsg))
4021 +                       fsg->state = FSG_STATE_DATA_PHASE;
4022 +               spin_unlock_irq(&fsg->lock);
4023 +
4024 +               if (do_scsi_command(fsg) || finish_reply(fsg))
4025 +                       continue;
4026 +
4027 +               spin_lock_irq(&fsg->lock);
4028 +               if (!exception_in_progress(fsg))
4029 +                       fsg->state = FSG_STATE_STATUS_PHASE;
4030 +               spin_unlock_irq(&fsg->lock);
4031 +
4032 +               if (send_status(fsg))
4033 +                       continue;
4034 +
4035 +               spin_lock_irq(&fsg->lock);
4036 +               if (!exception_in_progress(fsg))
4037 +                       fsg->state = FSG_STATE_IDLE;
4038 +               spin_unlock_irq(&fsg->lock);
4039 +               }
4040 +
4041 +       spin_lock_irq(&fsg->lock);
4042 +       fsg->thread_task = NULL;
4043 +       spin_unlock_irq(&fsg->lock);
4044 +
4045 +       /* If we are exiting because of a signal, unregister the
4046 +        * gadget driver. */
4047 +       if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
4048 +               usb_gadget_unregister_driver(&fsg_driver);
4049 +
4050 +       /* Let the unbind and cleanup routines know the thread has exited */
4051 +       complete_and_exit(&fsg->thread_notifier, 0);
4052 +}
4053 +
4054 +
4055 +/*-------------------------------------------------------------------------*/
4056 +
4057 +
4058 +/* The write permissions and store_xxx pointers are set in fsg_bind() */
4059 +static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL);
4060 +static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL);
4061 +static DEVICE_ATTR(file, 0444, fsg_show_file, NULL);
4062 +
4063 +
4064 +/*-------------------------------------------------------------------------*/
4065 +
4066 +static void fsg_release(struct kref *ref)
4067 +{
4068 +       struct fsg_dev  *fsg = container_of(ref, struct fsg_dev, ref);
4069 +
4070 +       kfree(fsg->luns);
4071 +       kfree(fsg);
4072 +}
4073 +
4074 +static void lun_release(struct device *dev)
4075 +{
4076 +       struct rw_semaphore     *filesem = dev_get_drvdata(dev);
4077 +       struct fsg_dev          *fsg =
4078 +               container_of(filesem, struct fsg_dev, filesem);
4079 +
4080 +       kref_put(&fsg->ref, fsg_release);
4081 +}
4082 +
4083 +static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget)
4084 +{
4085 +       struct fsg_dev          *fsg = get_gadget_data(gadget);
4086 +       int                     i;
4087 +       struct fsg_lun          *curlun;
4088 +       struct usb_request      *req = fsg->ep0req;
4089 +
4090 +       DBG(fsg, "unbind\n");
4091 +       clear_bit(REGISTERED, &fsg->atomic_bitflags);
4092 +
4093 +       /* If the thread isn't already dead, tell it to exit now */
4094 +       if (fsg->state != FSG_STATE_TERMINATED) {
4095 +               raise_exception(fsg, FSG_STATE_EXIT);
4096 +               wait_for_completion(&fsg->thread_notifier);
4097 +
4098 +               /* The cleanup routine waits for this completion also */
4099 +               complete(&fsg->thread_notifier);
4100 +       }
4101 +
4102 +       /* Unregister the sysfs attribute files and the LUNs */
4103 +       for (i = 0; i < fsg->nluns; ++i) {
4104 +               curlun = &fsg->luns[i];
4105 +               if (curlun->registered) {
4106 +                       device_remove_file(&curlun->dev, &dev_attr_nofua);
4107 +                       device_remove_file(&curlun->dev, &dev_attr_ro);
4108 +                       device_remove_file(&curlun->dev, &dev_attr_file);
4109 +                       fsg_lun_close(curlun);
4110 +                       device_unregister(&curlun->dev);
4111 +                       curlun->registered = 0;
4112 +               }
4113 +       }
4114 +
4115 +       /* Free the data buffers */
4116 +       for (i = 0; i < fsg_num_buffers; ++i)
4117 +               kfree(fsg->buffhds[i].buf);
4118 +
4119 +       /* Free the request and buffer for endpoint 0 */
4120 +       if (req) {
4121 +               kfree(req->buf);
4122 +               usb_ep_free_request(fsg->ep0, req);
4123 +       }
4124 +
4125 +       set_gadget_data(gadget, NULL);
4126 +}
4127 +
4128 +
4129 +static int __init check_parameters(struct fsg_dev *fsg)
4130 +{
4131 +       int     prot;
4132 +       int     gcnum;
4133 +
4134 +       /* Store the default values */
4135 +       mod_data.transport_type = USB_PR_BULK;
4136 +       mod_data.transport_name = "Bulk-only";
4137 +       mod_data.protocol_type = USB_SC_SCSI;
4138 +       mod_data.protocol_name = "Transparent SCSI";
4139 +
4140 +       /* Some peripheral controllers are known not to be able to
4141 +        * halt bulk endpoints correctly.  If one of them is present,
4142 +        * disable stalls.
4143 +        */
4144 +       if (gadget_is_at91(fsg->gadget))
4145 +               mod_data.can_stall = 0;
4146 +
4147 +       if (mod_data.release == 0xffff) {       // Parameter wasn't set
4148 +               gcnum = usb_gadget_controller_number(fsg->gadget);
4149 +               if (gcnum >= 0)
4150 +                       mod_data.release = 0x0300 + gcnum;
4151 +               else {
4152 +                       WARNING(fsg, "controller '%s' not recognized\n",
4153 +                               fsg->gadget->name);
4154 +                       mod_data.release = 0x0399;
4155 +               }
4156 +       }
4157 +
4158 +       prot = simple_strtol(mod_data.protocol_parm, NULL, 0);
4159 +
4160 +#ifdef CONFIG_USB_FILE_STORAGE_TEST
4161 +       if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) {
4162 +               ;               // Use default setting
4163 +       } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) {
4164 +               mod_data.transport_type = USB_PR_CB;
4165 +               mod_data.transport_name = "Control-Bulk";
4166 +       } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) {
4167 +               mod_data.transport_type = USB_PR_CBI;
4168 +               mod_data.transport_name = "Control-Bulk-Interrupt";
4169 +       } else {
4170 +               ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm);
4171 +               return -EINVAL;
4172 +       }
4173 +
4174 +       if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 ||
4175 +                       prot == USB_SC_SCSI) {
4176 +               ;               // Use default setting
4177 +       } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 ||
4178 +                       prot == USB_SC_RBC) {
4179 +               mod_data.protocol_type = USB_SC_RBC;
4180 +               mod_data.protocol_name = "RBC";
4181 +       } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 ||
4182 +                       strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 ||
4183 +                       prot == USB_SC_8020) {
4184 +               mod_data.protocol_type = USB_SC_8020;
4185 +               mod_data.protocol_name = "8020i (ATAPI)";
4186 +       } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 ||
4187 +                       prot == USB_SC_QIC) {
4188 +               mod_data.protocol_type = USB_SC_QIC;
4189 +               mod_data.protocol_name = "QIC-157";
4190 +       } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 ||
4191 +                       prot == USB_SC_UFI) {
4192 +               mod_data.protocol_type = USB_SC_UFI;
4193 +               mod_data.protocol_name = "UFI";
4194 +       } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 ||
4195 +                       prot == USB_SC_8070) {
4196 +               mod_data.protocol_type = USB_SC_8070;
4197 +               mod_data.protocol_name = "8070i";
4198 +       } else {
4199 +               ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm);
4200 +               return -EINVAL;
4201 +       }
4202 +
4203 +       mod_data.buflen &= PAGE_CACHE_MASK;
4204 +       if (mod_data.buflen <= 0) {
4205 +               ERROR(fsg, "invalid buflen\n");
4206 +               return -ETOOSMALL;
4207 +       }
4208 +
4209 +#endif /* CONFIG_USB_FILE_STORAGE_TEST */
4210 +
4211 +       /* Serial string handling.
4212 +        * On a real device, the serial string would be loaded
4213 +        * from permanent storage. */
4214 +       if (mod_data.serial) {
4215 +               const char *ch;
4216 +               unsigned len = 0;
4217 +
4218 +               /* Sanity check :
4219 +                * The CB[I] specification limits the serial string to
4220 +                * 12 uppercase hexadecimal characters.
4221 +                * BBB need at least 12 uppercase hexadecimal characters,
4222 +                * with a maximum of 126. */
4223 +               for (ch = mod_data.serial; *ch; ++ch) {
4224 +                       ++len;
4225 +                       if ((*ch < '0' || *ch > '9') &&
4226 +                           (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */
4227 +                               WARNING(fsg,
4228 +                                       "Invalid serial string character: %c\n",
4229 +                                       *ch);
4230 +                               goto no_serial;
4231 +                       }
4232 +               }
4233 +               if (len > 126 ||
4234 +                   (mod_data.transport_type == USB_PR_BULK && len < 12) ||
4235 +                   (mod_data.transport_type != USB_PR_BULK && len > 12)) {
4236 +                       WARNING(fsg, "Invalid serial string length!\n");
4237 +                       goto no_serial;
4238 +               }
4239 +               fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial;
4240 +       } else {
4241 +               WARNING(fsg, "No serial-number string provided!\n");
4242 + no_serial:
4243 +               device_desc.iSerialNumber = 0;
4244 +       }
4245 +
4246 +       return 0;
4247 +}
4248 +
4249 +
4250 +static int __init fsg_bind(struct usb_gadget *gadget)
4251 +{
4252 +       struct fsg_dev          *fsg = the_fsg;
4253 +       int                     rc;
4254 +       int                     i;
4255 +       struct fsg_lun          *curlun;
4256 +       struct usb_ep           *ep;
4257 +       struct usb_request      *req;
4258 +       char                    *pathbuf, *p;
4259 +
4260 +       fsg->gadget = gadget;
4261 +       set_gadget_data(gadget, fsg);
4262 +       fsg->ep0 = gadget->ep0;
4263 +       fsg->ep0->driver_data = fsg;
4264 +
4265 +       if ((rc = check_parameters(fsg)) != 0)
4266 +               goto out;
4267 +
4268 +       if (mod_data.removable) {       // Enable the store_xxx attributes
4269 +               dev_attr_file.attr.mode = 0644;
4270 +               dev_attr_file.store = fsg_store_file;
4271 +               if (!mod_data.cdrom) {
4272 +                       dev_attr_ro.attr.mode = 0644;
4273 +                       dev_attr_ro.store = fsg_store_ro;
4274 +               }
4275 +       }
4276 +
4277 +       /* Only for removable media? */
4278 +       dev_attr_nofua.attr.mode = 0644;
4279 +       dev_attr_nofua.store = fsg_store_nofua;
4280 +
4281 +       /* Find out how many LUNs there should be */
4282 +       i = mod_data.nluns;
4283 +       if (i == 0)
4284 +               i = max(mod_data.num_filenames, 1u);
4285 +       if (i > FSG_MAX_LUNS) {
4286 +               ERROR(fsg, "invalid number of LUNs: %d\n", i);
4287 +               rc = -EINVAL;
4288 +               goto out;
4289 +       }
4290 +
4291 +       /* Create the LUNs, open their backing files, and register the
4292 +        * LUN devices in sysfs. */
4293 +       fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL);
4294 +       if (!fsg->luns) {
4295 +               rc = -ENOMEM;
4296 +               goto out;
4297 +       }
4298 +       fsg->nluns = i;
4299 +
4300 +       for (i = 0; i < fsg->nluns; ++i) {
4301 +               curlun = &fsg->luns[i];
4302 +               curlun->cdrom = !!mod_data.cdrom;
4303 +               curlun->ro = mod_data.cdrom || mod_data.ro[i];
4304 +               curlun->initially_ro = curlun->ro;
4305 +               curlun->removable = mod_data.removable;
4306 +               curlun->nofua = mod_data.nofua[i];
4307 +               curlun->dev.release = lun_release;
4308 +               curlun->dev.parent = &gadget->dev;
4309 +               curlun->dev.driver = &fsg_driver.driver;
4310 +               dev_set_drvdata(&curlun->dev, &fsg->filesem);
4311 +               dev_set_name(&curlun->dev,"%s-lun%d",
4312 +                            dev_name(&gadget->dev), i);
4313 +
4314 +               kref_get(&fsg->ref);
4315 +               rc = device_register(&curlun->dev);
4316 +               if (rc) {
4317 +                       INFO(fsg, "failed to register LUN%d: %d\n", i, rc);
4318 +                       put_device(&curlun->dev);
4319 +                       goto out;
4320 +               }
4321 +               curlun->registered = 1;
4322 +
4323 +               rc = device_create_file(&curlun->dev, &dev_attr_ro);
4324 +               if (rc)
4325 +                       goto out;
4326 +               rc = device_create_file(&curlun->dev, &dev_attr_nofua);
4327 +               if (rc)
4328 +                       goto out;
4329 +               rc = device_create_file(&curlun->dev, &dev_attr_file);
4330 +               if (rc)
4331 +                       goto out;
4332 +
4333 +               if (mod_data.file[i] && *mod_data.file[i]) {
4334 +                       rc = fsg_lun_open(curlun, mod_data.file[i]);
4335 +                       if (rc)
4336 +                               goto out;
4337 +               } else if (!mod_data.removable) {
4338 +                       ERROR(fsg, "no file given for LUN%d\n", i);
4339 +                       rc = -EINVAL;
4340 +                       goto out;
4341 +               }
4342 +       }
4343 +
4344 +       /* Find all the endpoints we will use */
4345 +       usb_ep_autoconfig_reset(gadget);
4346 +       ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
4347 +       if (!ep)
4348 +               goto autoconf_fail;
4349 +       ep->driver_data = fsg;          // claim the endpoint
4350 +       fsg->bulk_in = ep;
4351 +
4352 +       ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc);
4353 +       if (!ep)
4354 +               goto autoconf_fail;
4355 +       ep->driver_data = fsg;          // claim the endpoint
4356 +       fsg->bulk_out = ep;
4357 +
4358 +       if (transport_is_cbi()) {
4359 +               ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc);
4360 +               if (!ep)
4361 +                       goto autoconf_fail;
4362 +               ep->driver_data = fsg;          // claim the endpoint
4363 +               fsg->intr_in = ep;
4364 +       }
4365 +
4366 +       /* Fix up the descriptors */
4367 +       device_desc.idVendor = cpu_to_le16(mod_data.vendor);
4368 +       device_desc.idProduct = cpu_to_le16(mod_data.product);
4369 +       device_desc.bcdDevice = cpu_to_le16(mod_data.release);
4370 +
4371 +       i = (transport_is_cbi() ? 3 : 2);       // Number of endpoints
4372 +       fsg_intf_desc.bNumEndpoints = i;
4373 +       fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type;
4374 +       fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type;
4375 +       fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4376 +
4377 +       if (gadget_is_dualspeed(gadget)) {
4378 +               fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4379 +
4380 +               /* Assume endpoint addresses are the same for both speeds */
4381 +               fsg_hs_bulk_in_desc.bEndpointAddress =
4382 +                       fsg_fs_bulk_in_desc.bEndpointAddress;
4383 +               fsg_hs_bulk_out_desc.bEndpointAddress =
4384 +                       fsg_fs_bulk_out_desc.bEndpointAddress;
4385 +               fsg_hs_intr_in_desc.bEndpointAddress =
4386 +                       fsg_fs_intr_in_desc.bEndpointAddress;
4387 +       }
4388 +
4389 +       if (gadget_is_superspeed(gadget)) {
4390 +               unsigned                max_burst;
4391 +
4392 +               fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL;
4393 +
4394 +               /* Calculate bMaxBurst, we know packet size is 1024 */
4395 +               max_burst = min_t(unsigned, mod_data.buflen / 1024, 15);
4396 +
4397 +               /* Assume endpoint addresses are the same for both speeds */
4398 +               fsg_ss_bulk_in_desc.bEndpointAddress =
4399 +                       fsg_fs_bulk_in_desc.bEndpointAddress;
4400 +               fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst;
4401 +
4402 +               fsg_ss_bulk_out_desc.bEndpointAddress =
4403 +                       fsg_fs_bulk_out_desc.bEndpointAddress;
4404 +               fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst;
4405 +       }
4406 +
4407 +       if (gadget_is_otg(gadget))
4408 +               fsg_otg_desc.bmAttributes |= USB_OTG_HNP;
4409 +
4410 +       rc = -ENOMEM;
4411 +
4412 +       /* Allocate the request and buffer for endpoint 0 */
4413 +       fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL);
4414 +       if (!req)
4415 +               goto out;
4416 +       req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL);
4417 +       if (!req->buf)
4418 +               goto out;
4419 +       req->complete = ep0_complete;
4420 +
4421 +       /* Allocate the data buffers */
4422 +       for (i = 0; i < fsg_num_buffers; ++i) {
4423 +               struct fsg_buffhd       *bh = &fsg->buffhds[i];
4424 +
4425 +               /* Allocate for the bulk-in endpoint.  We assume that
4426 +                * the buffer will also work with the bulk-out (and
4427 +                * interrupt-in) endpoint. */
4428 +               bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL);
4429 +               if (!bh->buf)
4430 +                       goto out;
4431 +               bh->next = bh + 1;
4432 +       }
4433 +       fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0];
4434 +
4435 +       /* This should reflect the actual gadget power source */
4436 +       usb_gadget_set_selfpowered(gadget);
4437 +
4438 +       snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer,
4439 +                       "%s %s with %s",
4440 +                       init_utsname()->sysname, init_utsname()->release,
4441 +                       gadget->name);
4442 +
4443 +       fsg->thread_task = kthread_create(fsg_main_thread, fsg,
4444 +                       "file-storage-gadget");
4445 +       if (IS_ERR(fsg->thread_task)) {
4446 +               rc = PTR_ERR(fsg->thread_task);
4447 +               goto out;
4448 +       }
4449 +
4450 +       INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n");
4451 +       INFO(fsg, "NOTE: This driver is deprecated.  "
4452 +                       "Consider using g_mass_storage instead.\n");
4453 +       INFO(fsg, "Number of LUNs=%d\n", fsg->nluns);
4454 +
4455 +       pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
4456 +       for (i = 0; i < fsg->nluns; ++i) {
4457 +               curlun = &fsg->luns[i];
4458 +               if (fsg_lun_is_open(curlun)) {
4459 +                       p = NULL;
4460 +                       if (pathbuf) {
4461 +                               p = d_path(&curlun->filp->f_path,
4462 +                                          pathbuf, PATH_MAX);
4463 +                               if (IS_ERR(p))
4464 +                                       p = NULL;
4465 +                       }
4466 +                       LINFO(curlun, "ro=%d, nofua=%d, file: %s\n",
4467 +                             curlun->ro, curlun->nofua, (p ? p : "(error)"));
4468 +               }
4469 +       }
4470 +       kfree(pathbuf);
4471 +
4472 +       DBG(fsg, "transport=%s (x%02x)\n",
4473 +                       mod_data.transport_name, mod_data.transport_type);
4474 +       DBG(fsg, "protocol=%s (x%02x)\n",
4475 +                       mod_data.protocol_name, mod_data.protocol_type);
4476 +       DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n",
4477 +                       mod_data.vendor, mod_data.product, mod_data.release);
4478 +       DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n",
4479 +                       mod_data.removable, mod_data.can_stall,
4480 +                       mod_data.cdrom, mod_data.buflen);
4481 +       DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task));
4482 +
4483 +       set_bit(REGISTERED, &fsg->atomic_bitflags);
4484 +
4485 +       /* Tell the thread to start working */
4486 +       wake_up_process(fsg->thread_task);
4487 +       return 0;
4488 +
4489 +autoconf_fail:
4490 +       ERROR(fsg, "unable to autoconfigure all endpoints\n");
4491 +       rc = -ENOTSUPP;
4492 +
4493 +out:
4494 +       fsg->state = FSG_STATE_TERMINATED;      // The thread is dead
4495 +       fsg_unbind(gadget);
4496 +       complete(&fsg->thread_notifier);
4497 +       return rc;
4498 +}
4499 +
4500 +
4501 +/*-------------------------------------------------------------------------*/
4502 +
4503 +static void fsg_suspend(struct usb_gadget *gadget)
4504 +{
4505 +       struct fsg_dev          *fsg = get_gadget_data(gadget);
4506 +
4507 +       DBG(fsg, "suspend\n");
4508 +       set_bit(SUSPENDED, &fsg->atomic_bitflags);
4509 +}
4510 +
4511 +static void fsg_resume(struct usb_gadget *gadget)
4512 +{
4513 +       struct fsg_dev          *fsg = get_gadget_data(gadget);
4514 +
4515 +       DBG(fsg, "resume\n");
4516 +       clear_bit(SUSPENDED, &fsg->atomic_bitflags);
4517 +}
4518 +
4519 +
4520 +/*-------------------------------------------------------------------------*/
4521 +
4522 +static struct usb_gadget_driver                fsg_driver = {
4523 +       .max_speed      = USB_SPEED_SUPER,
4524 +       .function       = (char *) fsg_string_product,
4525 +       .unbind         = fsg_unbind,
4526 +       .disconnect     = fsg_disconnect,
4527 +       .setup          = fsg_setup,
4528 +       .suspend        = fsg_suspend,
4529 +       .resume         = fsg_resume,
4530 +
4531 +       .driver         = {
4532 +               .name           = DRIVER_NAME,
4533 +               .owner          = THIS_MODULE,
4534 +               // .release = ...
4535 +               // .suspend = ...
4536 +               // .resume = ...
4537 +       },
4538 +};
4539 +
4540 +
4541 +static int __init fsg_alloc(void)
4542 +{
4543 +       struct fsg_dev          *fsg;
4544 +
4545 +       fsg = kzalloc(sizeof *fsg +
4546 +                     fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL);
4547 +
4548 +       if (!fsg)
4549 +               return -ENOMEM;
4550 +       spin_lock_init(&fsg->lock);
4551 +       init_rwsem(&fsg->filesem);
4552 +       kref_init(&fsg->ref);
4553 +       init_completion(&fsg->thread_notifier);
4554 +
4555 +       the_fsg = fsg;
4556 +       return 0;
4557 +}
4558 +
4559 +
4560 +static int __init fsg_init(void)
4561 +{
4562 +       int             rc;
4563 +       struct fsg_dev  *fsg;
4564 +
4565 +       rc = fsg_num_buffers_validate();
4566 +       if (rc != 0)
4567 +               return rc;
4568 +
4569 +       if ((rc = fsg_alloc()) != 0)
4570 +               return rc;
4571 +       fsg = the_fsg;
4572 +       if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0)
4573 +               kref_put(&fsg->ref, fsg_release);
4574 +       return rc;
4575 +}
4576 +module_init(fsg_init);
4577 +
4578 +
4579 +static void __exit fsg_cleanup(void)
4580 +{
4581 +       struct fsg_dev  *fsg = the_fsg;
4582 +
4583 +       /* Unregister the driver iff the thread hasn't already done so */
4584 +       if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags))
4585 +               usb_gadget_unregister_driver(&fsg_driver);
4586 +
4587 +       /* Wait for the thread to finish up */
4588 +       wait_for_completion(&fsg->thread_notifier);
4589 +
4590 +       kref_put(&fsg->ref, fsg_release);
4591 +}
4592 +module_exit(fsg_cleanup);
4593 --- a/drivers/usb/host/Kconfig
4594 +++ b/drivers/usb/host/Kconfig
4595 @@ -735,6 +735,19 @@ config USB_HWA_HCD
4596           To compile this driver a module, choose M here: the module
4597           will be called "hwa-hc".
4598
4599 +config USB_DWCOTG
4600 +       tristate "Synopsis DWC host support"
4601 +       depends on USB
4602 +       help
4603 +         The Synopsis DWC controller is a dual-role
4604 +         host/peripheral/OTG ("On The Go") USB controllers.
4605 +
4606 +         Enable this option to support this IP in host controller mode.
4607 +         If unsure, say N.
4608 +
4609 +         To compile this driver as a module, choose M here: the
4610 +         modules built will be called dwc_otg and dwc_common_port.
4611 +
4612  config USB_IMX21_HCD
4613         tristate "i.MX21 HCD support"
4614         depends on ARM && ARCH_MXC
4615 --- a/drivers/usb/host/Makefile
4616 +++ b/drivers/usb/host/Makefile
4617 @@ -69,6 +69,8 @@ obj-$(CONFIG_USB_SL811_CS)    += sl811_cs.o
4618  obj-$(CONFIG_USB_U132_HCD)     += u132-hcd.o
4619  obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
4620  obj-$(CONFIG_USB_HWA_HCD)      += hwa-hc.o
4621 +
4622 +obj-$(CONFIG_USB_DWCOTG)        += dwc_otg/ dwc_common_port/
4623  obj-$(CONFIG_USB_IMX21_HCD)    += imx21-hcd.o
4624  obj-$(CONFIG_USB_FSL_MPH_DR_OF)        += fsl-mph-dr-of.o
4625  obj-$(CONFIG_USB_EHCI_FSL)     += ehci-fsl.o
4626 --- /dev/null
4627 +++ b/drivers/usb/host/dwc_common_port/Makefile
4628 @@ -0,0 +1,58 @@
4629 +#
4630 +# Makefile for DWC_common library
4631 +#
4632 +
4633 +ifneq ($(KERNELRELEASE),)
4634 +
4635 +ccflags-y      += -DDWC_LINUX
4636 +#ccflags-y     += -DDEBUG
4637 +#ccflags-y     += -DDWC_DEBUG_REGS
4638 +#ccflags-y     += -DDWC_DEBUG_MEMORY
4639 +
4640 +ccflags-y      += -DDWC_LIBMODULE
4641 +ccflags-y      += -DDWC_CCLIB
4642 +#ccflags-y     += -DDWC_CRYPTOLIB
4643 +ccflags-y      += -DDWC_NOTIFYLIB
4644 +ccflags-y      += -DDWC_UTFLIB
4645 +
4646 +obj-$(CONFIG_USB_DWCOTG)       += dwc_common_port_lib.o
4647 +dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
4648 +                           dwc_crypto.o dwc_notifier.o \
4649 +                           dwc_common_linux.o dwc_mem.o
4650 +
4651 +kernrelwd := $(subst ., ,$(KERNELRELEASE))
4652 +kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
4653 +
4654 +ifneq ($(kernrel3),2.6.20)
4655 +# grayg - I only know that we use ccflags-y in 2.6.31 actually
4656 +ccflags-y += $(CPPFLAGS)
4657 +endif
4658 +
4659 +else
4660 +
4661 +#ifeq ($(KDIR),)
4662 +#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
4663 +#endif
4664 +
4665 +ifeq ($(ARCH),)
4666 +$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
4667 + cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
4668 +endif
4669 +
4670 +ifeq ($(DOXYGEN),)
4671 +DOXYGEN                := doxygen
4672 +endif
4673 +
4674 +default:
4675 +       $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
4676 +
4677 +docs:  $(wildcard *.[hc]) doc/doxygen.cfg
4678 +       $(DOXYGEN) doc/doxygen.cfg
4679 +
4680 +tags:  $(wildcard *.[hc])
4681 +       $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
4682 +
4683 +endif
4684 +
4685 +clean:
4686 +       rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
4687 --- /dev/null
4688 +++ b/drivers/usb/host/dwc_common_port/Makefile.fbsd
4689 @@ -0,0 +1,17 @@
4690 +CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include
4691 +CFLAGS += -DDWC_FREEBSD
4692 +CFLAGS += -DDEBUG
4693 +#CFLAGS        += -DDWC_DEBUG_REGS
4694 +#CFLAGS        += -DDWC_DEBUG_MEMORY
4695 +
4696 +#CFLAGS        += -DDWC_LIBMODULE
4697 +#CFLAGS        += -DDWC_CCLIB
4698 +#CFLAGS        += -DDWC_CRYPTOLIB
4699 +#CFLAGS        += -DDWC_NOTIFYLIB
4700 +#CFLAGS        += -DDWC_UTFLIB
4701 +
4702 +KMOD = dwc_common_port_lib
4703 +SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \
4704 +       dwc_common_fbsd.c dwc_mem.c
4705 +
4706 +.include <bsd.kmod.mk>
4707 --- /dev/null
4708 +++ b/drivers/usb/host/dwc_common_port/Makefile.linux
4709 @@ -0,0 +1,49 @@
4710 +#
4711 +# Makefile for DWC_common library
4712 +#
4713 +ifneq ($(KERNELRELEASE),)
4714 +
4715 +ccflags-y      += -DDWC_LINUX
4716 +#ccflags-y     += -DDEBUG
4717 +#ccflags-y     += -DDWC_DEBUG_REGS
4718 +#ccflags-y     += -DDWC_DEBUG_MEMORY
4719 +
4720 +ccflags-y      += -DDWC_LIBMODULE
4721 +ccflags-y      += -DDWC_CCLIB
4722 +ccflags-y      += -DDWC_CRYPTOLIB
4723 +ccflags-y      += -DDWC_NOTIFYLIB
4724 +ccflags-y      += -DDWC_UTFLIB
4725 +
4726 +obj-m                   := dwc_common_port_lib.o
4727 +dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \
4728 +                           dwc_crypto.o dwc_notifier.o \
4729 +                           dwc_common_linux.o dwc_mem.o
4730 +
4731 +else
4732 +
4733 +ifeq ($(KDIR),)
4734 +$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment)
4735 +endif
4736 +
4737 +ifeq ($(ARCH),)
4738 +$(error Must give "ARCH=<arch>" on command line or in environment. Also, if \
4739 + cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-")
4740 +endif
4741 +
4742 +ifeq ($(DOXYGEN),)
4743 +DOXYGEN                := doxygen
4744 +endif
4745 +
4746 +default:
4747 +       $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
4748 +
4749 +docs:  $(wildcard *.[hc]) doc/doxygen.cfg
4750 +       $(DOXYGEN) doc/doxygen.cfg
4751 +
4752 +tags:  $(wildcard *.[hc])
4753 +       $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
4754 +
4755 +endif
4756 +
4757 +clean:
4758 +       rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/
4759 --- /dev/null
4760 +++ b/drivers/usb/host/dwc_common_port/changes.txt
4761 @@ -0,0 +1,174 @@
4762 +
4763 +dwc_read_reg32() and friends now take an additional parameter, a pointer to an
4764 +IO context struct. The IO context struct should live in an os-dependent struct
4765 +in your driver. As an example, the dwc_usb3 driver has an os-dependent struct
4766 +named 'os_dep' embedded in the main device struct. So there these calls look
4767 +like this:
4768 +
4769 +       dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg);
4770 +
4771 +       dwc_write_reg32(&usb3_dev->os_dep.ioctx,
4772 +                       &pcd->dev_global_regs->dcfg, 0);
4773 +
4774 +Note that for the existing Linux driver ports, it is not necessary to actually
4775 +define the 'ioctx' member in the os-dependent struct. Since Linux does not
4776 +require an IO context, its macros for dwc_read_reg32() and friends do not
4777 +use the context pointer, so it is optimized away by the compiler. But it is
4778 +necessary to add the pointer parameter to all of the call sites, to be ready
4779 +for any future ports (such as FreeBSD) which do require an IO context.
4780 +
4781 +
4782 +Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now
4783 +take an additional parameter, a pointer to a memory context. Examples:
4784 +
4785 +       addr = dwc_alloc(&usb3_dev->os_dep.memctx, size);
4786 +
4787 +       dwc_free(&usb3_dev->os_dep.memctx, addr);
4788 +
4789 +Again, for the Linux ports, it is not necessary to actually define the memctx
4790 +member, but it is necessary to add the pointer parameter to all of the call
4791 +sites.
4792 +
4793 +
4794 +Same for dwc_dma_alloc() and dwc_dma_free(). Examples:
4795 +
4796 +       virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr);
4797 +
4798 +       dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr);
4799 +
4800 +
4801 +Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples:
4802 +
4803 +       mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx);
4804 +
4805 +       dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex);
4806 +
4807 +
4808 +Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples:
4809 +
4810 +       lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx);
4811 +
4812 +       dwc_spinlock_free(&usb3_dev->osdep.splctx, lock);
4813 +
4814 +
4815 +Same for dwc_timer_alloc(). Example:
4816 +
4817 +       timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1",
4818 +                               cb_func, cb_data);
4819 +
4820 +
4821 +Same for dwc_waitq_alloc(). Example:
4822 +
4823 +       waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx);
4824 +
4825 +
4826 +Same for dwc_thread_run(). Example:
4827 +
4828 +       thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func,
4829 +                               "dwc_usb3_thd1", data);
4830 +
4831 +
4832 +Same for dwc_workq_alloc(). Example:
4833 +
4834 +       workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1");
4835 +
4836 +
4837 +Same for dwc_task_alloc(). Example:
4838 +
4839 +       task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1",
4840 +                             cb_func, cb_data);
4841 +
4842 +
4843 +In addition to the context pointer additions, a few core functions have had
4844 +other changes made to their parameters:
4845 +
4846 +The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore()
4847 +has been changed from a uint64_t to a dwc_irqflags_t.
4848 +
4849 +dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the
4850 +FreeBSD equivalent of that function requires it.
4851 +
4852 +And, in addition to the context pointer, dwc_task_alloc() also adds a
4853 +'char *name' parameter, to be consistent with dwc_thread_run() and
4854 +dwc_workq_alloc(), and because the FreeBSD equivalent of that function
4855 +requires a unique name.
4856 +
4857 +
4858 +Here is a complete list of the core functions that now take a pointer to a
4859 +context as their first parameter:
4860 +
4861 +       dwc_read_reg32
4862 +       dwc_read_reg64
4863 +       dwc_write_reg32
4864 +       dwc_write_reg64
4865 +       dwc_modify_reg32
4866 +       dwc_modify_reg64
4867 +       dwc_alloc
4868 +       dwc_alloc_atomic
4869 +       dwc_strdup
4870 +       dwc_free
4871 +       dwc_dma_alloc
4872 +       dwc_dma_free
4873 +       dwc_mutex_alloc
4874 +       dwc_mutex_free
4875 +       dwc_spinlock_alloc
4876 +       dwc_spinlock_free
4877 +       dwc_timer_alloc
4878 +       dwc_waitq_alloc
4879 +       dwc_thread_run
4880 +       dwc_workq_alloc
4881 +       dwc_task_alloc     Also adds a 'char *name' as its 2nd parameter
4882 +
4883 +And here are the core functions that have other changes to their parameters:
4884 +
4885 +       dwc_spinlock_irqsave      'flags' param is now a 'dwc_irqflags_t *'
4886 +       dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t'
4887 +       dwc_thread_should_stop    Adds a 'dwc_thread_t *' parameter
4888 +
4889 +
4890 +
4891 +The changes to the core functions also require some of the other library
4892 +functions to change:
4893 +
4894 +       dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx'
4895 +       (for memory allocation) as the 1st param and a 'void *mtxctx'
4896 +       (for mutex allocation) as the 2nd param.
4897 +
4898 +       dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(),
4899 +       dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a
4900 +       'void *memctx' as the 1st param.
4901 +
4902 +       dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a
4903 +       'void *memctx' as the 1st param.
4904 +
4905 +       dwc_modpow() now takes a 'void *memctx' as the 1st param.
4906 +
4907 +       dwc_alloc_notification_manager() now takes a 'void *memctx' as the
4908 +       1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd
4909 +       param, and also now returns an integer value that is non-zero if
4910 +       allocation of its data structures or work queue fails.
4911 +
4912 +       dwc_register_notifier() now takes a 'void *memctx' as the 1st param.
4913 +
4914 +       dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first
4915 +       param, and also now returns an integer value that is non-zero if
4916 +       allocation of its data structures fails.
4917 +
4918 +
4919 +
4920 +Other miscellaneous changes:
4921 +
4922 +The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to
4923 +DWC_DEBUG_MEMORY and DWC_DEBUG_REGS.
4924 +
4925 +The following #define's have been added to allow selectively compiling library
4926 +features:
4927 +
4928 +       DWC_CCLIB
4929 +       DWC_CRYPTOLIB
4930 +       DWC_NOTIFYLIB
4931 +       DWC_UTFLIB
4932 +
4933 +A DWC_LIBMODULE #define has also been added. If this is not defined, then the
4934 +module code in dwc_common_linux.c is not compiled in. This allows linking the
4935 +library code directly into a driver module, instead of as a standalone module.
4936 --- /dev/null
4937 +++ b/drivers/usb/host/dwc_common_port/doc/doxygen.cfg
4938 @@ -0,0 +1,270 @@
4939 +# Doxyfile 1.4.5
4940 +
4941 +#---------------------------------------------------------------------------
4942 +# Project related configuration options
4943 +#---------------------------------------------------------------------------
4944 +PROJECT_NAME           = "Synopsys DWC Portability and Common Library for UWB"
4945 +PROJECT_NUMBER         =
4946 +OUTPUT_DIRECTORY       = doc
4947 +CREATE_SUBDIRS         = NO
4948 +OUTPUT_LANGUAGE        = English
4949 +BRIEF_MEMBER_DESC      = YES
4950 +REPEAT_BRIEF           = YES
4951 +ABBREVIATE_BRIEF       = "The $name class" \
4952 +                         "The $name widget" \
4953 +                         "The $name file" \
4954 +                         is \
4955 +                         provides \
4956 +                         specifies \
4957 +                         contains \
4958 +                         represents \
4959 +                         a \
4960 +                         an \
4961 +                         the
4962 +ALWAYS_DETAILED_SEC    = YES
4963 +INLINE_INHERITED_MEMB  = NO
4964 +FULL_PATH_NAMES        = NO
4965 +STRIP_FROM_PATH        = ..
4966 +STRIP_FROM_INC_PATH    =
4967 +SHORT_NAMES            = NO
4968 +JAVADOC_AUTOBRIEF      = YES
4969 +MULTILINE_CPP_IS_BRIEF = NO
4970 +DETAILS_AT_TOP         = YES
4971 +INHERIT_DOCS           = YES
4972 +SEPARATE_MEMBER_PAGES  = NO
4973 +TAB_SIZE               = 8
4974 +ALIASES                =
4975 +OPTIMIZE_OUTPUT_FOR_C  = YES
4976 +OPTIMIZE_OUTPUT_JAVA   = NO
4977 +BUILTIN_STL_SUPPORT    = NO
4978 +DISTRIBUTE_GROUP_DOC   = NO
4979 +SUBGROUPING            = NO
4980 +#---------------------------------------------------------------------------
4981 +# Build related configuration options
4982 +#---------------------------------------------------------------------------
4983 +EXTRACT_ALL            = NO
4984 +EXTRACT_PRIVATE        = NO
4985 +EXTRACT_STATIC         = YES
4986 +EXTRACT_LOCAL_CLASSES  = NO
4987 +EXTRACT_LOCAL_METHODS  = NO
4988 +HIDE_UNDOC_MEMBERS     = NO
4989 +HIDE_UNDOC_CLASSES     = NO
4990 +HIDE_FRIEND_COMPOUNDS  = NO
4991 +HIDE_IN_BODY_DOCS      = NO
4992 +INTERNAL_DOCS          = NO
4993 +CASE_SENSE_NAMES       = YES
4994 +HIDE_SCOPE_NAMES       = NO
4995 +SHOW_INCLUDE_FILES     = NO
4996 +INLINE_INFO            = YES
4997 +SORT_MEMBER_DOCS       = NO
4998 +SORT_BRIEF_DOCS        = NO
4999 +SORT_BY_SCOPE_NAME     = NO
5000 +GENERATE_TODOLIST      = YES
5001 +GENERATE_TESTLIST      = YES
5002 +GENERATE_BUGLIST       = YES
5003 +GENERATE_DEPRECATEDLIST= YES
5004 +ENABLED_SECTIONS       =
5005 +MAX_INITIALIZER_LINES  = 30
5006 +SHOW_USED_FILES        = YES
5007 +SHOW_DIRECTORIES       = YES
5008 +FILE_VERSION_FILTER    =
5009 +#---------------------------------------------------------------------------
5010 +# configuration options related to warning and progress messages
5011 +#---------------------------------------------------------------------------
5012 +QUIET                  = YES
5013 +WARNINGS               = YES
5014 +WARN_IF_UNDOCUMENTED   = NO
5015 +WARN_IF_DOC_ERROR      = YES
5016 +WARN_NO_PARAMDOC       = YES
5017 +WARN_FORMAT            = "$file:$line: $text"
5018 +WARN_LOGFILE           =
5019 +#---------------------------------------------------------------------------
5020 +# configuration options related to the input files
5021 +#---------------------------------------------------------------------------
5022 +INPUT                  = .
5023 +FILE_PATTERNS          = *.c \
5024 +                         *.cc \
5025 +                         *.cxx \
5026 +                         *.cpp \
5027 +                         *.c++ \
5028 +                         *.d \
5029 +                         *.java \
5030 +                         *.ii \
5031 +                         *.ixx \
5032 +                         *.ipp \
5033 +                         *.i++ \
5034 +                         *.inl \
5035 +                         *.h \
5036 +                         *.hh \
5037 +                         *.hxx \
5038 +                         *.hpp \
5039 +                         *.h++ \
5040 +                         *.idl \
5041 +                         *.odl \
5042 +                         *.cs \
5043 +                         *.php \
5044 +                         *.php3 \
5045 +                         *.inc \
5046 +                         *.m \
5047 +                         *.mm \
5048 +                         *.dox \
5049 +                         *.py \
5050 +                         *.C \
5051 +                         *.CC \
5052 +                         *.C++ \
5053 +                         *.II \
5054 +                         *.I++ \
5055 +                         *.H \
5056 +                         *.HH \
5057 +                         *.H++ \
5058 +                         *.CS \
5059 +                         *.PHP \
5060 +                         *.PHP3 \
5061 +                         *.M \
5062 +                         *.MM \
5063 +                         *.PY
5064 +RECURSIVE              = NO
5065 +EXCLUDE                =
5066 +EXCLUDE_SYMLINKS       = NO
5067 +EXCLUDE_PATTERNS       =
5068 +EXAMPLE_PATH           =
5069 +EXAMPLE_PATTERNS       = *
5070 +EXAMPLE_RECURSIVE      = NO
5071 +IMAGE_PATH             =
5072 +INPUT_FILTER           =
5073 +FILTER_PATTERNS        =
5074 +FILTER_SOURCE_FILES    = NO
5075 +#---------------------------------------------------------------------------
5076 +# configuration options related to source browsing
5077 +#---------------------------------------------------------------------------
5078 +SOURCE_BROWSER         = NO
5079 +INLINE_SOURCES         = NO
5080 +STRIP_CODE_COMMENTS    = YES
5081 +REFERENCED_BY_RELATION = YES
5082 +REFERENCES_RELATION    = YES
5083 +USE_HTAGS              = NO
5084 +VERBATIM_HEADERS       = NO
5085 +#---------------------------------------------------------------------------
5086 +# configuration options related to the alphabetical class index
5087 +#---------------------------------------------------------------------------
5088 +ALPHABETICAL_INDEX     = NO
5089 +COLS_IN_ALPHA_INDEX    = 5
5090 +IGNORE_PREFIX          =
5091 +#---------------------------------------------------------------------------
5092 +# configuration options related to the HTML output
5093 +#---------------------------------------------------------------------------
5094 +GENERATE_HTML          = YES
5095 +HTML_OUTPUT            = html
5096 +HTML_FILE_EXTENSION    = .html
5097 +HTML_HEADER            =
5098 +HTML_FOOTER            =
5099 +HTML_STYLESHEET        =
5100 +HTML_ALIGN_MEMBERS     = YES
5101 +GENERATE_HTMLHELP      = NO
5102 +CHM_FILE               =
5103 +HHC_LOCATION           =
5104 +GENERATE_CHI           = NO
5105 +BINARY_TOC             = NO
5106 +TOC_EXPAND             = NO
5107 +DISABLE_INDEX          = NO
5108 +ENUM_VALUES_PER_LINE   = 4
5109 +GENERATE_TREEVIEW      = YES
5110 +TREEVIEW_WIDTH         = 250
5111 +#---------------------------------------------------------------------------
5112 +# configuration options related to the LaTeX output
5113 +#---------------------------------------------------------------------------
5114 +GENERATE_LATEX         = NO
5115 +LATEX_OUTPUT           = latex
5116 +LATEX_CMD_NAME         = latex
5117 +MAKEINDEX_CMD_NAME     = makeindex
5118 +COMPACT_LATEX          = NO
5119 +PAPER_TYPE             = a4wide
5120 +EXTRA_PACKAGES         =
5121 +LATEX_HEADER           =
5122 +PDF_HYPERLINKS         = NO
5123 +USE_PDFLATEX           = NO
5124 +LATEX_BATCHMODE        = NO
5125 +LATEX_HIDE_INDICES     = NO
5126 +#---------------------------------------------------------------------------
5127 +# configuration options related to the RTF output
5128 +#---------------------------------------------------------------------------
5129 +GENERATE_RTF           = NO
5130 +RTF_OUTPUT             = rtf
5131 +COMPACT_RTF            = NO
5132 +RTF_HYPERLINKS         = NO
5133 +RTF_STYLESHEET_FILE    =
5134 +RTF_EXTENSIONS_FILE    =
5135 +#---------------------------------------------------------------------------
5136 +# configuration options related to the man page output
5137 +#---------------------------------------------------------------------------
5138 +GENERATE_MAN           = NO
5139 +MAN_OUTPUT             = man
5140 +MAN_EXTENSION          = .3
5141 +MAN_LINKS              = NO
5142 +#---------------------------------------------------------------------------
5143 +# configuration options related to the XML output
5144 +#---------------------------------------------------------------------------
5145 +GENERATE_XML           = NO
5146 +XML_OUTPUT             = xml
5147 +XML_SCHEMA             =
5148 +XML_DTD                =
5149 +XML_PROGRAMLISTING     = YES
5150 +#---------------------------------------------------------------------------
5151 +# configuration options for the AutoGen Definitions output
5152 +#---------------------------------------------------------------------------
5153 +GENERATE_AUTOGEN_DEF   = NO
5154 +#---------------------------------------------------------------------------
5155 +# configuration options related to the Perl module output
5156 +#---------------------------------------------------------------------------
5157 +GENERATE_PERLMOD       = NO
5158 +PERLMOD_LATEX          = NO
5159 +PERLMOD_PRETTY         = YES
5160 +PERLMOD_MAKEVAR_PREFIX =
5161 +#---------------------------------------------------------------------------
5162 +# Configuration options related to the preprocessor
5163 +#---------------------------------------------------------------------------
5164 +ENABLE_PREPROCESSING   = YES
5165 +MACRO_EXPANSION        = NO
5166 +EXPAND_ONLY_PREDEF     = NO
5167 +SEARCH_INCLUDES        = YES
5168 +INCLUDE_PATH           =
5169 +INCLUDE_FILE_PATTERNS  =
5170 +PREDEFINED             = DEBUG DEBUG_MEMORY
5171 +EXPAND_AS_DEFINED      =
5172 +SKIP_FUNCTION_MACROS   = YES
5173 +#---------------------------------------------------------------------------
5174 +# Configuration::additions related to external references
5175 +#---------------------------------------------------------------------------
5176 +TAGFILES               =
5177 +GENERATE_TAGFILE       =
5178 +ALLEXTERNALS           = NO
5179 +EXTERNAL_GROUPS        = YES
5180 +PERL_PATH              = /usr/bin/perl
5181 +#---------------------------------------------------------------------------
5182 +# Configuration options related to the dot tool
5183 +#---------------------------------------------------------------------------
5184 +CLASS_DIAGRAMS         = YES
5185 +HIDE_UNDOC_RELATIONS   = YES
5186 +HAVE_DOT               = NO
5187 +CLASS_GRAPH            = YES
5188 +COLLABORATION_GRAPH    = YES
5189 +GROUP_GRAPHS           = YES
5190 +UML_LOOK               = NO
5191 +TEMPLATE_RELATIONS     = NO
5192 +INCLUDE_GRAPH          = NO
5193 +INCLUDED_BY_GRAPH      = YES
5194 +CALL_GRAPH             = NO
5195 +GRAPHICAL_HIERARCHY    = YES
5196 +DIRECTORY_GRAPH        = YES
5197 +DOT_IMAGE_FORMAT       = png
5198 +DOT_PATH               =
5199 +DOTFILE_DIRS           =
5200 +MAX_DOT_GRAPH_DEPTH    = 1000
5201 +DOT_TRANSPARENT        = NO
5202 +DOT_MULTI_TARGETS      = NO
5203 +GENERATE_LEGEND        = YES
5204 +DOT_CLEANUP            = YES
5205 +#---------------------------------------------------------------------------
5206 +# Configuration::additions related to the search engine
5207 +#---------------------------------------------------------------------------
5208 +SEARCHENGINE           = NO
5209 --- /dev/null
5210 +++ b/drivers/usb/host/dwc_common_port/dwc_cc.c
5211 @@ -0,0 +1,532 @@
5212 +/* =========================================================================
5213 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $
5214 + * $Revision: #4 $
5215 + * $Date: 2010/11/04 $
5216 + * $Change: 1621692 $
5217 + *
5218 + * Synopsys Portability Library Software and documentation
5219 + * (hereinafter, "Software") is an Unsupported proprietary work of
5220 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
5221 + * between Synopsys and you.
5222 + *
5223 + * The Software IS NOT an item of Licensed Software or Licensed Product
5224 + * under any End User Software License Agreement or Agreement for
5225 + * Licensed Product with Synopsys or any supplement thereto. You are
5226 + * permitted to use and redistribute this Software in source and binary
5227 + * forms, with or without modification, provided that redistributions
5228 + * of source code must retain this notice. You may not view, use,
5229 + * disclose, copy or distribute this file or any information contained
5230 + * herein except pursuant to this license grant from Synopsys. If you
5231 + * do not agree with this notice, including the disclaimer below, then
5232 + * you are not authorized to use the Software.
5233 + *
5234 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
5235 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
5236 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
5237 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
5238 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
5239 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
5240 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
5241 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
5242 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5243 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
5244 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5245 + * DAMAGE.
5246 + * ========================================================================= */
5247 +#ifdef DWC_CCLIB
5248 +
5249 +#include "dwc_cc.h"
5250 +
5251 +typedef struct dwc_cc
5252 +{
5253 +       uint32_t uid;
5254 +       uint8_t chid[16];
5255 +       uint8_t cdid[16];
5256 +       uint8_t ck[16];
5257 +       uint8_t *name;
5258 +       uint8_t length;
5259 +        DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry;
5260 +} dwc_cc_t;
5261 +
5262 +DWC_CIRCLEQ_HEAD(context_list, dwc_cc);
5263 +
5264 +/** The main structure for CC management.  */
5265 +struct dwc_cc_if
5266 +{
5267 +       dwc_mutex_t *mutex;
5268 +       char *filename;
5269 +
5270 +       unsigned is_host:1;
5271 +
5272 +       dwc_notifier_t *notifier;
5273 +
5274 +       struct context_list list;
5275 +};
5276 +
5277 +#ifdef DEBUG
5278 +static inline void dump_bytes(char *name, uint8_t *bytes, int len)
5279 +{
5280 +       int i;
5281 +       DWC_PRINTF("%s: ", name);
5282 +       for (i=0; i<len; i++) {
5283 +               DWC_PRINTF("%02x ", bytes[i]);
5284 +       }
5285 +       DWC_PRINTF("\n");
5286 +}
5287 +#else
5288 +#define dump_bytes(x...)
5289 +#endif
5290 +
5291 +static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length)
5292 +{
5293 +       dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t));
5294 +       if (!cc) {
5295 +               return NULL;
5296 +       }
5297 +       DWC_MEMSET(cc, 0, sizeof(dwc_cc_t));
5298 +
5299 +       if (name) {
5300 +               cc->length = length;
5301 +               cc->name = dwc_alloc(mem_ctx, length);
5302 +               if (!cc->name) {
5303 +                       dwc_free(mem_ctx, cc);
5304 +                       return NULL;
5305 +               }
5306 +
5307 +               DWC_MEMCPY(cc->name, name, length);
5308 +       }
5309 +
5310 +       return cc;
5311 +}
5312 +
5313 +static void free_cc(void *mem_ctx, dwc_cc_t *cc)
5314 +{
5315 +       if (cc->name) {
5316 +               dwc_free(mem_ctx, cc->name);
5317 +       }
5318 +       dwc_free(mem_ctx, cc);
5319 +}
5320 +
5321 +static uint32_t next_uid(dwc_cc_if_t *cc_if)
5322 +{
5323 +       uint32_t uid = 0;
5324 +       dwc_cc_t *cc;
5325 +       DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5326 +               if (cc->uid > uid) {
5327 +                       uid = cc->uid;
5328 +               }
5329 +       }
5330 +
5331 +       if (uid == 0) {
5332 +               uid = 255;
5333 +       }
5334 +
5335 +       return uid + 1;
5336 +}
5337 +
5338 +static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid)
5339 +{
5340 +       dwc_cc_t *cc;
5341 +       DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5342 +               if (cc->uid == uid) {
5343 +                       return cc;
5344 +               }
5345 +       }
5346 +       return NULL;
5347 +}
5348 +
5349 +static unsigned int cc_data_size(dwc_cc_if_t *cc_if)
5350 +{
5351 +       unsigned int size = 0;
5352 +       dwc_cc_t *cc;
5353 +       DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5354 +               size += (48 + 1);
5355 +               if (cc->name) {
5356 +                       size += cc->length;
5357 +               }
5358 +       }
5359 +       return size;
5360 +}
5361 +
5362 +static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
5363 +{
5364 +       uint32_t uid = 0;
5365 +       dwc_cc_t *cc;
5366 +
5367 +       DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5368 +               if (DWC_MEMCMP(cc->chid, chid, 16) == 0) {
5369 +                       uid = cc->uid;
5370 +                       break;
5371 +               }
5372 +       }
5373 +       return uid;
5374 +}
5375 +static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
5376 +{
5377 +       uint32_t uid = 0;
5378 +       dwc_cc_t *cc;
5379 +
5380 +       DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5381 +               if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) {
5382 +                       uid = cc->uid;
5383 +                       break;
5384 +               }
5385 +       }
5386 +       return uid;
5387 +}
5388 +
5389 +/* Internal cc_add */
5390 +static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5391 +                     uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5392 +{
5393 +       dwc_cc_t *cc;
5394 +       uint32_t uid;
5395 +
5396 +       if (cc_if->is_host) {
5397 +               uid = cc_match_cdid(cc_if, cdid);
5398 +       }
5399 +       else {
5400 +               uid = cc_match_chid(cc_if, chid);
5401 +       }
5402 +
5403 +       if (uid) {
5404 +               DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length);
5405 +               cc = cc_find(cc_if, uid);
5406 +       }
5407 +       else {
5408 +               cc = alloc_cc(mem_ctx, name, length);
5409 +               cc->uid = next_uid(cc_if);
5410 +               DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry);
5411 +       }
5412 +
5413 +       DWC_MEMCPY(&(cc->chid[0]), chid, 16);
5414 +       DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
5415 +       DWC_MEMCPY(&(cc->ck[0]), ck, 16);
5416 +
5417 +       DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length);
5418 +       dump_bytes("CHID", cc->chid, 16);
5419 +       dump_bytes("CDID", cc->cdid, 16);
5420 +       dump_bytes("CK", cc->ck, 16);
5421 +       return cc->uid;
5422 +}
5423 +
5424 +/* Internal cc_clear */
5425 +static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
5426 +{
5427 +       while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) {
5428 +               dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list);
5429 +               DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
5430 +               free_cc(mem_ctx, cc);
5431 +       }
5432 +}
5433 +
5434 +dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
5435 +                            dwc_notifier_t *notifier, unsigned is_host)
5436 +{
5437 +       dwc_cc_if_t *cc_if = NULL;
5438 +
5439 +       /* Allocate a common_cc_if structure */
5440 +       cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t));
5441 +
5442 +       if (!cc_if)
5443 +               return NULL;
5444 +
5445 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
5446 +       DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex);
5447 +#else
5448 +       cc_if->mutex = dwc_mutex_alloc(mtx_ctx);
5449 +#endif
5450 +       if (!cc_if->mutex) {
5451 +               dwc_free(mem_ctx, cc_if);
5452 +               return NULL;
5453 +       }
5454 +
5455 +       DWC_CIRCLEQ_INIT(&cc_if->list);
5456 +       cc_if->is_host = is_host;
5457 +       cc_if->notifier = notifier;
5458 +       return cc_if;
5459 +}
5460 +
5461 +void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if)
5462 +{
5463 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
5464 +       DWC_MUTEX_FREE(cc_if->mutex);
5465 +#else
5466 +       dwc_mutex_free(mtx_ctx, cc_if->mutex);
5467 +#endif
5468 +       cc_clear(mem_ctx, cc_if);
5469 +       dwc_free(mem_ctx, cc_if);
5470 +}
5471 +
5472 +static void cc_changed(dwc_cc_if_t *cc_if)
5473 +{
5474 +       if (cc_if->notifier) {
5475 +               dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if);
5476 +       }
5477 +}
5478 +
5479 +void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if)
5480 +{
5481 +       DWC_MUTEX_LOCK(cc_if->mutex);
5482 +       cc_clear(mem_ctx, cc_if);
5483 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5484 +       cc_changed(cc_if);
5485 +}
5486 +
5487 +int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5488 +                  uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5489 +{
5490 +       uint32_t uid;
5491 +
5492 +       DWC_MUTEX_LOCK(cc_if->mutex);
5493 +       uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length);
5494 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5495 +       cc_changed(cc_if);
5496 +
5497 +       return uid;
5498 +}
5499 +
5500 +void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid,
5501 +                  uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
5502 +{
5503 +       dwc_cc_t* cc;
5504 +
5505 +       DWC_DEBUGC("Change connection context %d", id);
5506 +
5507 +       DWC_MUTEX_LOCK(cc_if->mutex);
5508 +       cc = cc_find(cc_if, id);
5509 +       if (!cc) {
5510 +               DWC_ERROR("Uid %d not found in cc list\n", id);
5511 +               DWC_MUTEX_UNLOCK(cc_if->mutex);
5512 +               return;
5513 +       }
5514 +
5515 +       if (chid) {
5516 +               DWC_MEMCPY(&(cc->chid[0]), chid, 16);
5517 +       }
5518 +       if (cdid) {
5519 +               DWC_MEMCPY(&(cc->cdid[0]), cdid, 16);
5520 +       }
5521 +       if (ck) {
5522 +               DWC_MEMCPY(&(cc->ck[0]), ck, 16);
5523 +       }
5524 +
5525 +       if (name) {
5526 +               if (cc->name) {
5527 +                       dwc_free(mem_ctx, cc->name);
5528 +               }
5529 +               cc->name = dwc_alloc(mem_ctx, length);
5530 +               if (!cc->name) {
5531 +                       DWC_ERROR("Out of memory in dwc_cc_change()\n");
5532 +                       DWC_MUTEX_UNLOCK(cc_if->mutex);
5533 +                       return;
5534 +               }
5535 +               cc->length = length;
5536 +               DWC_MEMCPY(cc->name, name, length);
5537 +       }
5538 +
5539 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5540 +
5541 +       cc_changed(cc_if);
5542 +
5543 +       DWC_DEBUGC("Changed connection context id=%d\n", id);
5544 +       dump_bytes("New CHID", cc->chid, 16);
5545 +       dump_bytes("New CDID", cc->cdid, 16);
5546 +       dump_bytes("New CK", cc->ck, 16);
5547 +}
5548 +
5549 +void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id)
5550 +{
5551 +       dwc_cc_t *cc;
5552 +
5553 +       DWC_DEBUGC("Removing connection context %d", id);
5554 +
5555 +       DWC_MUTEX_LOCK(cc_if->mutex);
5556 +       cc = cc_find(cc_if, id);
5557 +       if (!cc) {
5558 +               DWC_ERROR("Uid %d not found in cc list\n", id);
5559 +               DWC_MUTEX_UNLOCK(cc_if->mutex);
5560 +               return;
5561 +       }
5562 +
5563 +       DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry);
5564 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5565 +       free_cc(mem_ctx, cc);
5566 +
5567 +       cc_changed(cc_if);
5568 +}
5569 +
5570 +uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length)
5571 +{
5572 +       uint8_t *buf, *x;
5573 +       uint8_t zero = 0;
5574 +       dwc_cc_t *cc;
5575 +
5576 +       DWC_MUTEX_LOCK(cc_if->mutex);
5577 +       *length = cc_data_size(cc_if);
5578 +       if (!(*length)) {
5579 +               DWC_MUTEX_UNLOCK(cc_if->mutex);
5580 +               return NULL;
5581 +       }
5582 +
5583 +       DWC_DEBUGC("Creating data for saving (length=%d)", *length);
5584 +
5585 +       buf = dwc_alloc(mem_ctx, *length);
5586 +       if (!buf) {
5587 +               *length = 0;
5588 +               DWC_MUTEX_UNLOCK(cc_if->mutex);
5589 +               return NULL;
5590 +       }
5591 +
5592 +       x = buf;
5593 +       DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) {
5594 +               DWC_MEMCPY(x, cc->chid, 16);
5595 +               x += 16;
5596 +               DWC_MEMCPY(x, cc->cdid, 16);
5597 +               x += 16;
5598 +               DWC_MEMCPY(x, cc->ck, 16);
5599 +               x += 16;
5600 +               if (cc->name) {
5601 +                       DWC_MEMCPY(x, &cc->length, 1);
5602 +                       x += 1;
5603 +                       DWC_MEMCPY(x, cc->name, cc->length);
5604 +                       x += cc->length;
5605 +               }
5606 +               else {
5607 +                       DWC_MEMCPY(x, &zero, 1);
5608 +                       x += 1;
5609 +               }
5610 +       }
5611 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5612 +
5613 +       return buf;
5614 +}
5615 +
5616 +void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length)
5617 +{
5618 +       uint8_t name_length;
5619 +       uint8_t *name;
5620 +       uint8_t *chid;
5621 +       uint8_t *cdid;
5622 +       uint8_t *ck;
5623 +       uint32_t i = 0;
5624 +
5625 +       DWC_MUTEX_LOCK(cc_if->mutex);
5626 +       cc_clear(mem_ctx, cc_if);
5627 +
5628 +       while (i < length) {
5629 +               chid = &data[i];
5630 +               i += 16;
5631 +               cdid = &data[i];
5632 +               i += 16;
5633 +               ck = &data[i];
5634 +               i += 16;
5635 +
5636 +               name_length = data[i];
5637 +               i ++;
5638 +
5639 +               if (name_length) {
5640 +                       name = &data[i];
5641 +                       i += name_length;
5642 +               }
5643 +               else {
5644 +                       name = NULL;
5645 +               }
5646 +
5647 +               /* check to see if we haven't overflown the buffer */
5648 +               if (i > length) {
5649 +                       DWC_ERROR("Data format error while attempting to load CCs "
5650 +                                 "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length);
5651 +                       break;
5652 +               }
5653 +
5654 +               cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length);
5655 +       }
5656 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5657 +
5658 +       cc_changed(cc_if);
5659 +}
5660 +
5661 +uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid)
5662 +{
5663 +       uint32_t uid = 0;
5664 +
5665 +       DWC_MUTEX_LOCK(cc_if->mutex);
5666 +       uid = cc_match_chid(cc_if, chid);
5667 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5668 +       return uid;
5669 +}
5670 +uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid)
5671 +{
5672 +       uint32_t uid = 0;
5673 +
5674 +       DWC_MUTEX_LOCK(cc_if->mutex);
5675 +       uid = cc_match_cdid(cc_if, cdid);
5676 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5677 +       return uid;
5678 +}
5679 +
5680 +uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id)
5681 +{
5682 +       uint8_t *ck = NULL;
5683 +       dwc_cc_t *cc;
5684 +
5685 +       DWC_MUTEX_LOCK(cc_if->mutex);
5686 +       cc = cc_find(cc_if, id);
5687 +       if (cc) {
5688 +               ck = cc->ck;
5689 +       }
5690 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5691 +
5692 +       return ck;
5693 +
5694 +}
5695 +
5696 +uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id)
5697 +{
5698 +       uint8_t *retval = NULL;
5699 +       dwc_cc_t *cc;
5700 +
5701 +       DWC_MUTEX_LOCK(cc_if->mutex);
5702 +       cc = cc_find(cc_if, id);
5703 +       if (cc) {
5704 +               retval = cc->chid;
5705 +       }
5706 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5707 +
5708 +       return retval;
5709 +}
5710 +
5711 +uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id)
5712 +{
5713 +       uint8_t *retval = NULL;
5714 +       dwc_cc_t *cc;
5715 +
5716 +       DWC_MUTEX_LOCK(cc_if->mutex);
5717 +       cc = cc_find(cc_if, id);
5718 +       if (cc) {
5719 +               retval = cc->cdid;
5720 +       }
5721 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5722 +
5723 +       return retval;
5724 +}
5725 +
5726 +uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
5727 +{
5728 +       uint8_t *retval = NULL;
5729 +       dwc_cc_t *cc;
5730 +
5731 +       DWC_MUTEX_LOCK(cc_if->mutex);
5732 +       *length = 0;
5733 +       cc = cc_find(cc_if, id);
5734 +       if (cc) {
5735 +               *length = cc->length;
5736 +               retval = cc->name;
5737 +       }
5738 +       DWC_MUTEX_UNLOCK(cc_if->mutex);
5739 +
5740 +       return retval;
5741 +}
5742 +
5743 +#endif /* DWC_CCLIB */
5744 --- /dev/null
5745 +++ b/drivers/usb/host/dwc_common_port/dwc_cc.h
5746 @@ -0,0 +1,224 @@
5747 +/* =========================================================================
5748 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $
5749 + * $Revision: #4 $
5750 + * $Date: 2010/09/28 $
5751 + * $Change: 1596182 $
5752 + *
5753 + * Synopsys Portability Library Software and documentation
5754 + * (hereinafter, "Software") is an Unsupported proprietary work of
5755 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
5756 + * between Synopsys and you.
5757 + *
5758 + * The Software IS NOT an item of Licensed Software or Licensed Product
5759 + * under any End User Software License Agreement or Agreement for
5760 + * Licensed Product with Synopsys or any supplement thereto. You are
5761 + * permitted to use and redistribute this Software in source and binary
5762 + * forms, with or without modification, provided that redistributions
5763 + * of source code must retain this notice. You may not view, use,
5764 + * disclose, copy or distribute this file or any information contained
5765 + * herein except pursuant to this license grant from Synopsys. If you
5766 + * do not agree with this notice, including the disclaimer below, then
5767 + * you are not authorized to use the Software.
5768 + *
5769 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
5770 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
5771 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
5772 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
5773 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
5774 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
5775 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
5776 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
5777 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5778 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
5779 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
5780 + * DAMAGE.
5781 + * ========================================================================= */
5782 +#ifndef _DWC_CC_H_
5783 +#define _DWC_CC_H_
5784 +
5785 +#ifdef __cplusplus
5786 +extern "C" {
5787 +#endif
5788 +
5789 +/** @file
5790 + *
5791 + * This file defines the Context Context library.
5792 + *
5793 + * The main data structure is dwc_cc_if_t which is returned by either the
5794 + * dwc_cc_if_alloc function or returned by the module to the user via a provided
5795 + * function. The data structure is opaque and should only be manipulated via the
5796 + * functions provied in this API.
5797 + *
5798 + * It manages a list of connection contexts and operations can be performed to
5799 + * add, remove, query, search, and change, those contexts.  Additionally,
5800 + * a dwc_notifier_t object can be requested from the manager so that
5801 + * the user can be notified whenever the context list has changed.
5802 + */
5803 +
5804 +#include "dwc_os.h"
5805 +#include "dwc_list.h"
5806 +#include "dwc_notifier.h"
5807 +
5808 +
5809 +/* Notifications */
5810 +#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION"
5811 +
5812 +struct dwc_cc_if;
5813 +typedef struct dwc_cc_if dwc_cc_if_t;
5814 +
5815 +
5816 +/** @name Connection Context Operations */
5817 +/** @{ */
5818 +
5819 +/** This function allocates memory for a dwc_cc_if_t structure, initializes
5820 + * fields to default values, and returns a pointer to the structure or NULL on
5821 + * error. */
5822 +extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx,
5823 +                                   dwc_notifier_t *notifier, unsigned is_host);
5824 +
5825 +/** Frees the memory for the specified CC structure allocated from
5826 + * dwc_cc_if_alloc(). */
5827 +extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if);
5828 +
5829 +/** Removes all contexts from the connection context list */
5830 +extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if);
5831 +
5832 +/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
5833 + * If a CHID already exists, the CK and name are overwritten.  Statistics are
5834 + * not overwritten.
5835 + *
5836 + * @param cc_if The cc_if structure.
5837 + * @param chid A pointer to the 16-byte CHID.  This value will be copied.
5838 + * @param ck A pointer to the 16-byte CK.  This value will be copied.
5839 + * @param cdid A pointer to the 16-byte CDID.  This value will be copied.
5840 + * @param name An optional host friendly name as defined in the association model
5841 + * spec.  Must be a UTF16-LE unicode string.  Can be NULL to indicated no name.
5842 + * @param length The length othe unicode string.
5843 + * @return A unique identifier used to refer to this context that is valid for
5844 + * as long as this context is still in the list. */
5845 +extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid,
5846 +                         uint8_t *cdid, uint8_t *ck, uint8_t *name,
5847 +                         uint8_t length);
5848 +
5849 +/** Changes the CHID, CK, CDID, or Name values of a connection context in the
5850 + * list, preserving any accumulated statistics.  This would typically be called
5851 + * if the host decideds to change the context with a SET_CONNECTION request.
5852 + *
5853 + * @param cc_if The cc_if structure.
5854 + * @param id The identifier of the connection context.
5855 + * @param chid A pointer to the 16-byte CHID.  This value will be copied.  NULL
5856 + * indicates no change.
5857 + * @param cdid A pointer to the 16-byte CDID.  This value will be copied.  NULL
5858 + * indicates no change.
5859 + * @param ck A pointer to the 16-byte CK.  This value will be copied.  NULL
5860 + * indicates no change.
5861 + * @param name Host friendly name UTF16-LE.  NULL indicates no change.
5862 + * @param length Length of name. */
5863 +extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id,
5864 +                         uint8_t *chid, uint8_t *cdid, uint8_t *ck,
5865 +                         uint8_t *name, uint8_t length);
5866 +
5867 +/** Remove the specified connection context.
5868 + * @param cc_if The cc_if structure.
5869 + * @param id The identifier of the connection context to remove. */
5870 +extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id);
5871 +
5872 +/** Get a binary block of data for the connection context list and attributes.
5873 + * This data can be used by the OS specific driver to save the connection
5874 + * context list into non-volatile memory.
5875 + *
5876 + * @param cc_if The cc_if structure.
5877 + * @param length Return the length of the data buffer.
5878 + * @return A pointer to the data buffer.  The memory for this buffer should be
5879 + * freed with DWC_FREE() after use. */
5880 +extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if,
5881 +                                    unsigned int *length);
5882 +
5883 +/** Restore the connection context list from the binary data that was previously
5884 + * returned from a call to dwc_cc_data_for_save.  This can be used by the OS specific
5885 + * driver to load a connection context list from non-volatile memory.
5886 + *
5887 + * @param cc_if The cc_if structure.
5888 + * @param data The data bytes as returned from dwc_cc_data_for_save.
5889 + * @param length The length of the data. */
5890 +extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if,
5891 +                                    uint8_t *data, unsigned int length);
5892 +
5893 +/** Find the connection context from the specified CHID.
5894 + *
5895 + * @param cc_if The cc_if structure.
5896 + * @param chid A pointer to the CHID data.
5897 + * @return A non-zero identifier of the connection context if the CHID matches.
5898 + * Otherwise returns 0. */
5899 +extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid);
5900 +
5901 +/** Find the connection context from the specified CDID.
5902 + *
5903 + * @param cc_if The cc_if structure.
5904 + * @param cdid A pointer to the CDID data.
5905 + * @return A non-zero identifier of the connection context if the CHID matches.
5906 + * Otherwise returns 0. */
5907 +extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid);
5908 +
5909 +/** Retrieve the CK from the specified connection context.
5910 + *
5911 + * @param cc_if The cc_if structure.
5912 + * @param id The identifier of the connection context.
5913 + * @return A pointer to the CK data.  The memory does not need to be freed. */
5914 +extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id);
5915 +
5916 +/** Retrieve the CHID from the specified connection context.
5917 + *
5918 + * @param cc_if The cc_if structure.
5919 + * @param id The identifier of the connection context.
5920 + * @return A pointer to the CHID data.  The memory does not need to be freed. */
5921 +extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id);
5922 +
5923 +/** Retrieve the CDID from the specified connection context.
5924 + *
5925 + * @param cc_if The cc_if structure.
5926 + * @param id The identifier of the connection context.
5927 + * @return A pointer to the CDID data.  The memory does not need to be freed. */
5928 +extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id);
5929 +
5930 +extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length);
5931 +
5932 +/** Checks a buffer for non-zero.
5933 + * @param id A pointer to a 16 byte buffer.
5934 + * @return true if the 16 byte value is non-zero. */
5935 +static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) {
5936 +       int i;
5937 +       for (i=0; i<16; i++) {
5938 +               if (id[i]) return 1;
5939 +       }
5940 +       return 0;
5941 +}
5942 +
5943 +/** Checks a buffer for zero.
5944 + * @param id A pointer to a 16 byte buffer.
5945 + * @return true if the 16 byte value is zero. */
5946 +static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) {
5947 +       return !dwc_assoc_is_not_zero_id(id);
5948 +}
5949 +
5950 +/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into
5951 + * buffer. */
5952 +static inline int dwc_print_id_string(char *buffer, uint8_t *id) {
5953 +       char *ptr = buffer;
5954 +       int i;
5955 +       for (i=0; i<16; i++) {
5956 +               ptr += DWC_SPRINTF(ptr, "%02x", id[i]);
5957 +               if (i < 15) {
5958 +                       ptr += DWC_SPRINTF(ptr, " ");
5959 +               }
5960 +       }
5961 +       return ptr - buffer;
5962 +}
5963 +
5964 +/** @} */
5965 +
5966 +#ifdef __cplusplus
5967 +}
5968 +#endif
5969 +
5970 +#endif /* _DWC_CC_H_ */
5971 --- /dev/null
5972 +++ b/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c
5973 @@ -0,0 +1,1308 @@
5974 +#include "dwc_os.h"
5975 +#include "dwc_list.h"
5976 +
5977 +#ifdef DWC_CCLIB
5978 +# include "dwc_cc.h"
5979 +#endif
5980 +
5981 +#ifdef DWC_CRYPTOLIB
5982 +# include "dwc_modpow.h"
5983 +# include "dwc_dh.h"
5984 +# include "dwc_crypto.h"
5985 +#endif
5986 +
5987 +#ifdef DWC_NOTIFYLIB
5988 +# include "dwc_notifier.h"
5989 +#endif
5990 +
5991 +/* OS-Level Implementations */
5992 +
5993 +/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */
5994 +
5995 +
5996 +/* MISC */
5997 +
5998 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
5999 +{
6000 +       return memset(dest, byte, size);
6001 +}
6002 +
6003 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
6004 +{
6005 +       return memcpy(dest, src, size);
6006 +}
6007 +
6008 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
6009 +{
6010 +       bcopy(src, dest, size);
6011 +       return dest;
6012 +}
6013 +
6014 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
6015 +{
6016 +       return memcmp(m1, m2, size);
6017 +}
6018 +
6019 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
6020 +{
6021 +       return strncmp(s1, s2, size);
6022 +}
6023 +
6024 +int DWC_STRCMP(void *s1, void *s2)
6025 +{
6026 +       return strcmp(s1, s2);
6027 +}
6028 +
6029 +int DWC_STRLEN(char const *str)
6030 +{
6031 +       return strlen(str);
6032 +}
6033 +
6034 +char *DWC_STRCPY(char *to, char const *from)
6035 +{
6036 +       return strcpy(to, from);
6037 +}
6038 +
6039 +char *DWC_STRDUP(char const *str)
6040 +{
6041 +       int len = DWC_STRLEN(str) + 1;
6042 +       char *new = DWC_ALLOC_ATOMIC(len);
6043 +
6044 +       if (!new) {
6045 +               return NULL;
6046 +       }
6047 +
6048 +       DWC_MEMCPY(new, str, len);
6049 +       return new;
6050 +}
6051 +
6052 +int DWC_ATOI(char *str, int32_t *value)
6053 +{
6054 +       char *end = NULL;
6055 +
6056 +       *value = strtol(str, &end, 0);
6057 +       if (*end == '\0') {
6058 +               return 0;
6059 +       }
6060 +
6061 +       return -1;
6062 +}
6063 +
6064 +int DWC_ATOUI(char *str, uint32_t *value)
6065 +{
6066 +       char *end = NULL;
6067 +
6068 +       *value = strtoul(str, &end, 0);
6069 +       if (*end == '\0') {
6070 +               return 0;
6071 +       }
6072 +
6073 +       return -1;
6074 +}
6075 +
6076 +
6077 +#ifdef DWC_UTFLIB
6078 +/* From usbstring.c */
6079 +
6080 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
6081 +{
6082 +       int     count = 0;
6083 +       u8      c;
6084 +       u16     uchar;
6085 +
6086 +       /* this insists on correct encodings, though not minimal ones.
6087 +        * BUT it currently rejects legit 4-byte UTF-8 code points,
6088 +        * which need surrogate pairs.  (Unicode 3.1 can use them.)
6089 +        */
6090 +       while (len != 0 && (c = (u8) *s++) != 0) {
6091 +               if (unlikely(c & 0x80)) {
6092 +                       // 2-byte sequence:
6093 +                       // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
6094 +                       if ((c & 0xe0) == 0xc0) {
6095 +                               uchar = (c & 0x1f) << 6;
6096 +
6097 +                               c = (u8) *s++;
6098 +                               if ((c & 0xc0) != 0xc0)
6099 +                                       goto fail;
6100 +                               c &= 0x3f;
6101 +                               uchar |= c;
6102 +
6103 +                       // 3-byte sequence (most CJKV characters):
6104 +                       // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
6105 +                       } else if ((c & 0xf0) == 0xe0) {
6106 +                               uchar = (c & 0x0f) << 12;
6107 +
6108 +                               c = (u8) *s++;
6109 +                               if ((c & 0xc0) != 0xc0)
6110 +                                       goto fail;
6111 +                               c &= 0x3f;
6112 +                               uchar |= c << 6;
6113 +
6114 +                               c = (u8) *s++;
6115 +                               if ((c & 0xc0) != 0xc0)
6116 +                                       goto fail;
6117 +                               c &= 0x3f;
6118 +                               uchar |= c;
6119 +
6120 +                               /* no bogus surrogates */
6121 +                               if (0xd800 <= uchar && uchar <= 0xdfff)
6122 +                                       goto fail;
6123 +
6124 +                       // 4-byte sequence (surrogate pairs, currently rare):
6125 +                       // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
6126 +                       //     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
6127 +                       // (uuuuu = wwww + 1)
6128 +                       // FIXME accept the surrogate code points (only)
6129 +                       } else
6130 +                               goto fail;
6131 +               } else
6132 +                       uchar = c;
6133 +               put_unaligned (cpu_to_le16 (uchar), cp++);
6134 +               count++;
6135 +               len--;
6136 +       }
6137 +       return count;
6138 +fail:
6139 +       return -1;
6140 +}
6141 +
6142 +#endif /* DWC_UTFLIB */
6143 +
6144 +
6145 +/* dwc_debug.h */
6146 +
6147 +dwc_bool_t DWC_IN_IRQ(void)
6148 +{
6149 +//     return in_irq();
6150 +       return 0;
6151 +}
6152 +
6153 +dwc_bool_t DWC_IN_BH(void)
6154 +{
6155 +//     return in_softirq();
6156 +       return 0;
6157 +}
6158 +
6159 +void DWC_VPRINTF(char *format, va_list args)
6160 +{
6161 +       vprintf(format, args);
6162 +}
6163 +
6164 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
6165 +{
6166 +       return vsnprintf(str, size, format, args);
6167 +}
6168 +
6169 +void DWC_PRINTF(char *format, ...)
6170 +{
6171 +       va_list args;
6172 +
6173 +       va_start(args, format);
6174 +       DWC_VPRINTF(format, args);
6175 +       va_end(args);
6176 +}
6177 +
6178 +int DWC_SPRINTF(char *buffer, char *format, ...)
6179 +{
6180 +       int retval;
6181 +       va_list args;
6182 +
6183 +       va_start(args, format);
6184 +       retval = vsprintf(buffer, format, args);
6185 +       va_end(args);
6186 +       return retval;
6187 +}
6188 +
6189 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
6190 +{
6191 +       int retval;
6192 +       va_list args;
6193 +
6194 +       va_start(args, format);
6195 +       retval = vsnprintf(buffer, size, format, args);
6196 +       va_end(args);
6197 +       return retval;
6198 +}
6199 +
6200 +void __DWC_WARN(char *format, ...)
6201 +{
6202 +       va_list args;
6203 +
6204 +       va_start(args, format);
6205 +       DWC_VPRINTF(format, args);
6206 +       va_end(args);
6207 +}
6208 +
6209 +void __DWC_ERROR(char *format, ...)
6210 +{
6211 +       va_list args;
6212 +
6213 +       va_start(args, format);
6214 +       DWC_VPRINTF(format, args);
6215 +       va_end(args);
6216 +}
6217 +
6218 +void DWC_EXCEPTION(char *format, ...)
6219 +{
6220 +       va_list args;
6221 +
6222 +       va_start(args, format);
6223 +       DWC_VPRINTF(format, args);
6224 +       va_end(args);
6225 +//     BUG_ON(1);      ???
6226 +}
6227 +
6228 +#ifdef DEBUG
6229 +void __DWC_DEBUG(char *format, ...)
6230 +{
6231 +       va_list args;
6232 +
6233 +       va_start(args, format);
6234 +       DWC_VPRINTF(format, args);
6235 +       va_end(args);
6236 +}
6237 +#endif
6238 +
6239 +
6240 +/* dwc_mem.h */
6241 +
6242 +#if 0
6243 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
6244 +                               uint32_t align,
6245 +                               uint32_t alloc)
6246 +{
6247 +       struct dma_pool *pool = dma_pool_create("Pool", NULL,
6248 +                                               size, align, alloc);
6249 +       return (dwc_pool_t *)pool;
6250 +}
6251 +
6252 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
6253 +{
6254 +       dma_pool_destroy((struct dma_pool *)pool);
6255 +}
6256 +
6257 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
6258 +{
6259 +//     return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
6260 +       return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
6261 +}
6262 +
6263 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
6264 +{
6265 +       void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
6266 +       memset(..);
6267 +}
6268 +
6269 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
6270 +{
6271 +       dma_pool_free(pool, vaddr, daddr);
6272 +}
6273 +#endif
6274 +
6275 +static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
6276 +{
6277 +       if (error)
6278 +               return;
6279 +       *(bus_addr_t *)arg = segs[0].ds_addr;
6280 +}
6281 +
6282 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
6283 +{
6284 +       dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
6285 +       int error;
6286 +
6287 +       error = bus_dma_tag_create(
6288 +#if __FreeBSD_version >= 700000
6289 +                       bus_get_dma_tag(dma->dev),      /* parent */
6290 +#else
6291 +                       NULL,                           /* parent */
6292 +#endif
6293 +                       4, 0,                           /* alignment, bounds */
6294 +                       BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
6295 +                       BUS_SPACE_MAXADDR,              /* highaddr */
6296 +                       NULL, NULL,                     /* filter, filterarg */
6297 +                       size,                           /* maxsize */
6298 +                       1,                              /* nsegments */
6299 +                       size,                           /* maxsegsize */
6300 +                       0,                              /* flags */
6301 +                       NULL,                           /* lockfunc */
6302 +                       NULL,                           /* lockarg */
6303 +                       &dma->dma_tag);
6304 +       if (error) {
6305 +               device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n",
6306 +                             __func__, error);
6307 +               goto fail_0;
6308 +       }
6309 +
6310 +       error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr,
6311 +                                BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map);
6312 +       if (error) {
6313 +               device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n",
6314 +                             __func__, (uintmax_t)size, error);
6315 +               goto fail_1;
6316 +       }
6317 +
6318 +       dma->dma_paddr = 0;
6319 +       error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,
6320 +                               dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT);
6321 +       if (error || dma->dma_paddr == 0) {
6322 +               device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n",
6323 +                             __func__, error);
6324 +               goto fail_2;
6325 +       }
6326 +
6327 +       *dma_addr = dma->dma_paddr;
6328 +       return dma->dma_vaddr;
6329 +
6330 +fail_2:
6331 +       bus_dmamap_unload(dma->dma_tag, dma->dma_map);
6332 +fail_1:
6333 +       bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
6334 +       bus_dma_tag_destroy(dma->dma_tag);
6335 +fail_0:
6336 +       dma->dma_map = NULL;
6337 +       dma->dma_tag = NULL;
6338 +
6339 +       return NULL;
6340 +}
6341 +
6342 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
6343 +{
6344 +       dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
6345 +
6346 +       if (dma->dma_tag == NULL)
6347 +               return;
6348 +       if (dma->dma_map != NULL) {
6349 +               bus_dmamap_sync(dma->dma_tag, dma->dma_map,
6350 +                               BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6351 +               bus_dmamap_unload(dma->dma_tag, dma->dma_map);
6352 +               bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
6353 +               dma->dma_map = NULL;
6354 +       }
6355 +
6356 +       bus_dma_tag_destroy(dma->dma_tag);
6357 +       dma->dma_tag = NULL;
6358 +}
6359 +
6360 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
6361 +{
6362 +       return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
6363 +}
6364 +
6365 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
6366 +{
6367 +       return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
6368 +}
6369 +
6370 +void __DWC_FREE(void *mem_ctx, void *addr)
6371 +{
6372 +       free(addr, M_DEVBUF);
6373 +}
6374 +
6375 +
6376 +#ifdef DWC_CRYPTOLIB
6377 +/* dwc_crypto.h */
6378 +
6379 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
6380 +{
6381 +       get_random_bytes(buffer, length);
6382 +}
6383 +
6384 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
6385 +{
6386 +       struct crypto_blkcipher *tfm;
6387 +       struct blkcipher_desc desc;
6388 +       struct scatterlist sgd;
6389 +       struct scatterlist sgs;
6390 +
6391 +       tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
6392 +       if (tfm == NULL) {
6393 +               printk("failed to load transform for aes CBC\n");
6394 +               return -1;
6395 +       }
6396 +
6397 +       crypto_blkcipher_setkey(tfm, key, keylen);
6398 +       crypto_blkcipher_set_iv(tfm, iv, 16);
6399 +
6400 +       sg_init_one(&sgd, out, messagelen);
6401 +       sg_init_one(&sgs, message, messagelen);
6402 +
6403 +       desc.tfm = tfm;
6404 +       desc.flags = 0;
6405 +
6406 +       if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
6407 +               crypto_free_blkcipher(tfm);
6408 +               DWC_ERROR("AES CBC encryption failed");
6409 +               return -1;
6410 +       }
6411 +
6412 +       crypto_free_blkcipher(tfm);
6413 +       return 0;
6414 +}
6415 +
6416 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
6417 +{
6418 +       struct crypto_hash *tfm;
6419 +       struct hash_desc desc;
6420 +       struct scatterlist sg;
6421 +
6422 +       tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
6423 +       if (IS_ERR(tfm)) {
6424 +               DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
6425 +               return 0;
6426 +       }
6427 +       desc.tfm = tfm;
6428 +       desc.flags = 0;
6429 +
6430 +       sg_init_one(&sg, message, len);
6431 +       crypto_hash_digest(&desc, &sg, len, out);
6432 +       crypto_free_hash(tfm);
6433 +
6434 +       return 1;
6435 +}
6436 +
6437 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
6438 +                   uint8_t *key, uint32_t keylen, uint8_t *out)
6439 +{
6440 +       struct crypto_hash *tfm;
6441 +       struct hash_desc desc;
6442 +       struct scatterlist sg;
6443 +
6444 +       tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
6445 +       if (IS_ERR(tfm)) {
6446 +               DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
6447 +               return 0;
6448 +       }
6449 +       desc.tfm = tfm;
6450 +       desc.flags = 0;
6451 +
6452 +       sg_init_one(&sg, message, messagelen);
6453 +       crypto_hash_setkey(tfm, key, keylen);
6454 +       crypto_hash_digest(&desc, &sg, messagelen, out);
6455 +       crypto_free_hash(tfm);
6456 +
6457 +       return 1;
6458 +}
6459 +
6460 +#endif /* DWC_CRYPTOLIB */
6461 +
6462 +
6463 +/* Byte Ordering Conversions */
6464 +
6465 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
6466 +{
6467 +#ifdef __LITTLE_ENDIAN
6468 +       return *p;
6469 +#else
6470 +       uint8_t *u_p = (uint8_t *)p;
6471 +
6472 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6473 +#endif
6474 +}
6475 +
6476 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
6477 +{
6478 +#ifdef __BIG_ENDIAN
6479 +       return *p;
6480 +#else
6481 +       uint8_t *u_p = (uint8_t *)p;
6482 +
6483 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6484 +#endif
6485 +}
6486 +
6487 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
6488 +{
6489 +#ifdef __LITTLE_ENDIAN
6490 +       return *p;
6491 +#else
6492 +       uint8_t *u_p = (uint8_t *)p;
6493 +
6494 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6495 +#endif
6496 +}
6497 +
6498 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
6499 +{
6500 +#ifdef __BIG_ENDIAN
6501 +       return *p;
6502 +#else
6503 +       uint8_t *u_p = (uint8_t *)p;
6504 +
6505 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
6506 +#endif
6507 +}
6508 +
6509 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
6510 +{
6511 +#ifdef __LITTLE_ENDIAN
6512 +       return *p;
6513 +#else
6514 +       uint8_t *u_p = (uint8_t *)p;
6515 +       return (u_p[1] | (u_p[0] << 8));
6516 +#endif
6517 +}
6518 +
6519 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
6520 +{
6521 +#ifdef __BIG_ENDIAN
6522 +       return *p;
6523 +#else
6524 +       uint8_t *u_p = (uint8_t *)p;
6525 +       return (u_p[1] | (u_p[0] << 8));
6526 +#endif
6527 +}
6528 +
6529 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
6530 +{
6531 +#ifdef __LITTLE_ENDIAN
6532 +       return *p;
6533 +#else
6534 +       uint8_t *u_p = (uint8_t *)p;
6535 +       return (u_p[1] | (u_p[0] << 8));
6536 +#endif
6537 +}
6538 +
6539 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
6540 +{
6541 +#ifdef __BIG_ENDIAN
6542 +       return *p;
6543 +#else
6544 +       uint8_t *u_p = (uint8_t *)p;
6545 +       return (u_p[1] | (u_p[0] << 8));
6546 +#endif
6547 +}
6548 +
6549 +
6550 +/* Registers */
6551 +
6552 +uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
6553 +{
6554 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6555 +       bus_size_t ior = (bus_size_t)reg;
6556 +
6557 +       return bus_space_read_4(io->iot, io->ioh, ior);
6558 +}
6559 +
6560 +#if 0
6561 +uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
6562 +{
6563 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6564 +       bus_size_t ior = (bus_size_t)reg;
6565 +
6566 +       return bus_space_read_8(io->iot, io->ioh, ior);
6567 +}
6568 +#endif
6569 +
6570 +void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
6571 +{
6572 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6573 +       bus_size_t ior = (bus_size_t)reg;
6574 +
6575 +       bus_space_write_4(io->iot, io->ioh, ior, value);
6576 +}
6577 +
6578 +#if 0
6579 +void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
6580 +{
6581 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6582 +       bus_size_t ior = (bus_size_t)reg;
6583 +
6584 +       bus_space_write_8(io->iot, io->ioh, ior, value);
6585 +}
6586 +#endif
6587 +
6588 +void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
6589 +                     uint32_t set_mask)
6590 +{
6591 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6592 +       bus_size_t ior = (bus_size_t)reg;
6593 +
6594 +       bus_space_write_4(io->iot, io->ioh, ior,
6595 +                         (bus_space_read_4(io->iot, io->ioh, ior) &
6596 +                          ~clear_mask) | set_mask);
6597 +}
6598 +
6599 +#if 0
6600 +void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
6601 +                     uint64_t set_mask)
6602 +{
6603 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
6604 +       bus_size_t ior = (bus_size_t)reg;
6605 +
6606 +       bus_space_write_8(io->iot, io->ioh, ior,
6607 +                         (bus_space_read_8(io->iot, io->ioh, ior) &
6608 +                          ~clear_mask) | set_mask);
6609 +}
6610 +#endif
6611 +
6612 +
6613 +/* Locking */
6614 +
6615 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
6616 +{
6617 +       struct mtx *sl = DWC_ALLOC(sizeof(*sl));
6618 +
6619 +       if (!sl) {
6620 +               DWC_ERROR("Cannot allocate memory for spinlock");
6621 +               return NULL;
6622 +       }
6623 +
6624 +       mtx_init(sl, "dw3spn", NULL, MTX_SPIN);
6625 +       return (dwc_spinlock_t *)sl;
6626 +}
6627 +
6628 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
6629 +{
6630 +       struct mtx *sl = (struct mtx *)lock;
6631 +
6632 +       mtx_destroy(sl);
6633 +       DWC_FREE(sl);
6634 +}
6635 +
6636 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
6637 +{
6638 +       mtx_lock_spin((struct mtx *)lock);      // ???
6639 +}
6640 +
6641 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
6642 +{
6643 +       mtx_unlock_spin((struct mtx *)lock);    // ???
6644 +}
6645 +
6646 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
6647 +{
6648 +       mtx_lock_spin((struct mtx *)lock);
6649 +}
6650 +
6651 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
6652 +{
6653 +       mtx_unlock_spin((struct mtx *)lock);
6654 +}
6655 +
6656 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
6657 +{
6658 +       struct mtx *m;
6659 +       dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx));
6660 +
6661 +       if (!mutex) {
6662 +               DWC_ERROR("Cannot allocate memory for mutex");
6663 +               return NULL;
6664 +       }
6665 +
6666 +       m = (struct mtx *)mutex;
6667 +       mtx_init(m, "dw3mtx", NULL, MTX_DEF);
6668 +       return mutex;
6669 +}
6670 +
6671 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
6672 +#else
6673 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
6674 +{
6675 +       mtx_destroy((struct mtx *)mutex);
6676 +       DWC_FREE(mutex);
6677 +}
6678 +#endif
6679 +
6680 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
6681 +{
6682 +       struct mtx *m = (struct mtx *)mutex;
6683 +
6684 +       mtx_lock(m);
6685 +}
6686 +
6687 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
6688 +{
6689 +       struct mtx *m = (struct mtx *)mutex;
6690 +
6691 +       return mtx_trylock(m);
6692 +}
6693 +
6694 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
6695 +{
6696 +       struct mtx *m = (struct mtx *)mutex;
6697 +
6698 +       mtx_unlock(m);
6699 +}
6700 +
6701 +
6702 +/* Timing */
6703 +
6704 +void DWC_UDELAY(uint32_t usecs)
6705 +{
6706 +       DELAY(usecs);
6707 +}
6708 +
6709 +void DWC_MDELAY(uint32_t msecs)
6710 +{
6711 +       do {
6712 +               DELAY(1000);
6713 +       } while (--msecs);
6714 +}
6715 +
6716 +void DWC_MSLEEP(uint32_t msecs)
6717 +{
6718 +       struct timeval tv;
6719 +
6720 +       tv.tv_sec = msecs / 1000;
6721 +       tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
6722 +       pause("dw3slp", tvtohz(&tv));
6723 +}
6724 +
6725 +uint32_t DWC_TIME(void)
6726 +{
6727 +       struct timeval tv;
6728 +
6729 +       microuptime(&tv);       // or getmicrouptime? (less precise, but faster)
6730 +       return tv.tv_sec * 1000 + tv.tv_usec / 1000;
6731 +}
6732 +
6733 +
6734 +/* Timers */
6735 +
6736 +struct dwc_timer {
6737 +       struct callout t;
6738 +       char *name;
6739 +       dwc_spinlock_t *lock;
6740 +       dwc_timer_callback_t cb;
6741 +       void *data;
6742 +};
6743 +
6744 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
6745 +{
6746 +       dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
6747 +
6748 +       if (!t) {
6749 +               DWC_ERROR("Cannot allocate memory for timer");
6750 +               return NULL;
6751 +       }
6752 +
6753 +       callout_init(&t->t, 1);
6754 +
6755 +       t->name = DWC_STRDUP(name);
6756 +       if (!t->name) {
6757 +               DWC_ERROR("Cannot allocate memory for timer->name");
6758 +               goto no_name;
6759 +       }
6760 +
6761 +       t->lock = DWC_SPINLOCK_ALLOC();
6762 +       if (!t->lock) {
6763 +               DWC_ERROR("Cannot allocate memory for lock");
6764 +               goto no_lock;
6765 +       }
6766 +
6767 +       t->cb = cb;
6768 +       t->data = data;
6769 +
6770 +       return t;
6771 +
6772 + no_lock:
6773 +       DWC_FREE(t->name);
6774 + no_name:
6775 +       DWC_FREE(t);
6776 +
6777 +       return NULL;
6778 +}
6779 +
6780 +void DWC_TIMER_FREE(dwc_timer_t *timer)
6781 +{
6782 +       callout_stop(&timer->t);
6783 +       DWC_SPINLOCK_FREE(timer->lock);
6784 +       DWC_FREE(timer->name);
6785 +       DWC_FREE(timer);
6786 +}
6787 +
6788 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
6789 +{
6790 +       struct timeval tv;
6791 +
6792 +       tv.tv_sec = time / 1000;
6793 +       tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
6794 +       callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
6795 +}
6796 +
6797 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
6798 +{
6799 +       callout_stop(&timer->t);
6800 +}
6801 +
6802 +
6803 +/* Wait Queues */
6804 +
6805 +struct dwc_waitq {
6806 +       struct mtx lock;
6807 +       int abort;
6808 +};
6809 +
6810 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
6811 +{
6812 +       dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
6813 +
6814 +       if (!wq) {
6815 +               DWC_ERROR("Cannot allocate memory for waitqueue");
6816 +               return NULL;
6817 +       }
6818 +
6819 +       mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF);
6820 +       wq->abort = 0;
6821 +
6822 +       return wq;
6823 +}
6824 +
6825 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
6826 +{
6827 +       mtx_destroy(&wq->lock);
6828 +       DWC_FREE(wq);
6829 +}
6830 +
6831 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
6832 +{
6833 +//     intrmask_t ipl;
6834 +       int result = 0;
6835 +
6836 +       mtx_lock(&wq->lock);
6837 +//     ipl = splbio();
6838 +
6839 +       /* Skip the sleep if already aborted or triggered */
6840 +       if (!wq->abort && !cond(data)) {
6841 +//             splx(ipl);
6842 +               result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout
6843 +//             ipl = splbio();
6844 +       }
6845 +
6846 +       if (result == ERESTART) {       // signaled - restart
6847 +               result = -DWC_E_RESTART;
6848 +
6849 +       } else if (result == EINTR) {   // signaled - interrupt
6850 +               result = -DWC_E_ABORT;
6851 +
6852 +       } else if (wq->abort) {
6853 +               result = -DWC_E_ABORT;
6854 +
6855 +       } else {
6856 +               result = 0;
6857 +       }
6858 +
6859 +       wq->abort = 0;
6860 +//     splx(ipl);
6861 +       mtx_unlock(&wq->lock);
6862 +       return result;
6863 +}
6864 +
6865 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
6866 +                              void *data, int32_t msecs)
6867 +{
6868 +       struct timeval tv, tv1, tv2;
6869 +//     intrmask_t ipl;
6870 +       int result = 0;
6871 +
6872 +       tv.tv_sec = msecs / 1000;
6873 +       tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
6874 +
6875 +       mtx_lock(&wq->lock);
6876 +//     ipl = splbio();
6877 +
6878 +       /* Skip the sleep if already aborted or triggered */
6879 +       if (!wq->abort && !cond(data)) {
6880 +//             splx(ipl);
6881 +               getmicrouptime(&tv1);
6882 +               result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv));
6883 +               getmicrouptime(&tv2);
6884 +//             ipl = splbio();
6885 +       }
6886 +
6887 +       if (result == 0) {                      // awoken
6888 +               if (wq->abort) {
6889 +                       result = -DWC_E_ABORT;
6890 +               } else {
6891 +                       tv2.tv_usec -= tv1.tv_usec;
6892 +                       if (tv2.tv_usec < 0) {
6893 +                               tv2.tv_usec += 1000000;
6894 +                               tv2.tv_sec--;
6895 +                       }
6896 +
6897 +                       tv2.tv_sec -= tv1.tv_sec;
6898 +                       result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
6899 +                       result = msecs - result;
6900 +                       if (result <= 0)
6901 +                               result = 1;
6902 +               }
6903 +       } else if (result == ERESTART) {        // signaled - restart
6904 +               result = -DWC_E_RESTART;
6905 +
6906 +       } else if (result == EINTR) {           // signaled - interrupt
6907 +               result = -DWC_E_ABORT;
6908 +
6909 +       } else {                                // timed out
6910 +               result = -DWC_E_TIMEOUT;
6911 +       }
6912 +
6913 +       wq->abort = 0;
6914 +//     splx(ipl);
6915 +       mtx_unlock(&wq->lock);
6916 +       return result;
6917 +}
6918 +
6919 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
6920 +{
6921 +       wakeup(wq);
6922 +}
6923 +
6924 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
6925 +{
6926 +//     intrmask_t ipl;
6927 +
6928 +       mtx_lock(&wq->lock);
6929 +//     ipl = splbio();
6930 +       wq->abort = 1;
6931 +       wakeup(wq);
6932 +//     splx(ipl);
6933 +       mtx_unlock(&wq->lock);
6934 +}
6935 +
6936 +
6937 +/* Threading */
6938 +
6939 +struct dwc_thread {
6940 +       struct proc *proc;
6941 +       int abort;
6942 +};
6943 +
6944 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
6945 +{
6946 +       int retval;
6947 +       dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
6948 +
6949 +       if (!thread) {
6950 +               return NULL;
6951 +       }
6952 +
6953 +       thread->abort = 0;
6954 +       retval = kthread_create((void (*)(void *))func, data, &thread->proc,
6955 +                               RFPROC | RFNOWAIT, 0, "%s", name);
6956 +       if (retval) {
6957 +               DWC_FREE(thread);
6958 +               return NULL;
6959 +       }
6960 +
6961 +       return thread;
6962 +}
6963 +
6964 +int DWC_THREAD_STOP(dwc_thread_t *thread)
6965 +{
6966 +       int retval;
6967 +
6968 +       thread->abort = 1;
6969 +       retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
6970 +
6971 +       if (retval == 0) {
6972 +               /* DWC_THREAD_EXIT() will free the thread struct */
6973 +               return 0;
6974 +       }
6975 +
6976 +       /* NOTE: We leak the thread struct if thread doesn't die */
6977 +
6978 +       if (retval == EWOULDBLOCK) {
6979 +               return -DWC_E_TIMEOUT;
6980 +       }
6981 +
6982 +       return -DWC_E_UNKNOWN;
6983 +}
6984 +
6985 +dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
6986 +{
6987 +       return thread->abort;
6988 +}
6989 +
6990 +void DWC_THREAD_EXIT(dwc_thread_t *thread)
6991 +{
6992 +       wakeup(&thread->abort);
6993 +       DWC_FREE(thread);
6994 +       kthread_exit(0);
6995 +}
6996 +
6997 +
6998 +/* tasklets
6999 + - Runs in interrupt context (cannot sleep)
7000 + - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ]
7001 + - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ]
7002 + */
7003 +struct dwc_tasklet {
7004 +       struct task t;
7005 +       dwc_tasklet_callback_t cb;
7006 +       void *data;
7007 +};
7008 +
7009 +static void tasklet_callback(void *data, int pending)  // what to do with pending ???
7010 +{
7011 +       dwc_tasklet_t *task = (dwc_tasklet_t *)data;
7012 +
7013 +       task->cb(task->data);
7014 +}
7015 +
7016 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
7017 +{
7018 +       dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
7019 +
7020 +       if (task) {
7021 +               task->cb = cb;
7022 +               task->data = data;
7023 +               TASK_INIT(&task->t, 0, tasklet_callback, task);
7024 +       } else {
7025 +               DWC_ERROR("Cannot allocate memory for tasklet");
7026 +       }
7027 +
7028 +       return task;
7029 +}
7030 +
7031 +void DWC_TASK_FREE(dwc_tasklet_t *task)
7032 +{
7033 +       taskqueue_drain(taskqueue_fast, &task->t);      // ???
7034 +       DWC_FREE(task);
7035 +}
7036 +
7037 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
7038 +{
7039 +       /* Uses predefined system queue */
7040 +       taskqueue_enqueue_fast(taskqueue_fast, &task->t);
7041 +}
7042 +
7043 +
7044 +/* workqueues
7045 + - Runs in process context (can sleep)
7046 + */
7047 +typedef struct work_container {
7048 +       dwc_work_callback_t cb;
7049 +       void *data;
7050 +       dwc_workq_t *wq;
7051 +       char *name;
7052 +       int hz;
7053 +
7054 +#ifdef DEBUG
7055 +       DWC_CIRCLEQ_ENTRY(work_container) entry;
7056 +#endif
7057 +       struct task task;
7058 +} work_container_t;
7059 +
7060 +#ifdef DEBUG
7061 +DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
7062 +#endif
7063 +
7064 +struct dwc_workq {
7065 +       struct taskqueue *taskq;
7066 +       dwc_spinlock_t *lock;
7067 +       dwc_waitq_t *waitq;
7068 +       int pending;
7069 +
7070 +#ifdef DEBUG
7071 +       struct work_container_queue entries;
7072 +#endif
7073 +};
7074 +
7075 +static void do_work(void *data, int pending)   // what to do with pending ???
7076 +{
7077 +       work_container_t *container = (work_container_t *)data;
7078 +       dwc_workq_t *wq = container->wq;
7079 +       dwc_irqflags_t flags;
7080 +
7081 +       if (container->hz) {
7082 +               pause("dw3wrk", container->hz);
7083 +       }
7084 +
7085 +       container->cb(container->data);
7086 +       DWC_DEBUG("Work done: %s, container=%p", container->name, container);
7087 +
7088 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7089 +
7090 +#ifdef DEBUG
7091 +       DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
7092 +#endif
7093 +       if (container->name)
7094 +               DWC_FREE(container->name);
7095 +       DWC_FREE(container);
7096 +       wq->pending--;
7097 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7098 +       DWC_WAITQ_TRIGGER(wq->waitq);
7099 +}
7100 +
7101 +static int work_done(void *data)
7102 +{
7103 +       dwc_workq_t *workq = (dwc_workq_t *)data;
7104 +
7105 +       return workq->pending == 0;
7106 +}
7107 +
7108 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
7109 +{
7110 +       return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
7111 +}
7112 +
7113 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
7114 +{
7115 +       dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
7116 +
7117 +       if (!wq) {
7118 +               DWC_ERROR("Cannot allocate memory for workqueue");
7119 +               return NULL;
7120 +       }
7121 +
7122 +       wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq);
7123 +       if (!wq->taskq) {
7124 +               DWC_ERROR("Cannot allocate memory for taskqueue");
7125 +               goto no_taskq;
7126 +       }
7127 +
7128 +       wq->pending = 0;
7129 +
7130 +       wq->lock = DWC_SPINLOCK_ALLOC();
7131 +       if (!wq->lock) {
7132 +               DWC_ERROR("Cannot allocate memory for spinlock");
7133 +               goto no_lock;
7134 +       }
7135 +
7136 +       wq->waitq = DWC_WAITQ_ALLOC();
7137 +       if (!wq->waitq) {
7138 +               DWC_ERROR("Cannot allocate memory for waitqueue");
7139 +               goto no_waitq;
7140 +       }
7141 +
7142 +       taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk");
7143 +
7144 +#ifdef DEBUG
7145 +       DWC_CIRCLEQ_INIT(&wq->entries);
7146 +#endif
7147 +       return wq;
7148 +
7149 + no_waitq:
7150 +       DWC_SPINLOCK_FREE(wq->lock);
7151 + no_lock:
7152 +       taskqueue_free(wq->taskq);
7153 + no_taskq:
7154 +       DWC_FREE(wq);
7155 +
7156 +       return NULL;
7157 +}
7158 +
7159 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
7160 +{
7161 +#ifdef DEBUG
7162 +       dwc_irqflags_t flags;
7163 +
7164 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7165 +
7166 +       if (wq->pending != 0) {
7167 +               struct work_container *container;
7168 +
7169 +               DWC_ERROR("Destroying work queue with pending work");
7170 +
7171 +               DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) {
7172 +                       DWC_ERROR("Work %s still pending", container->name);
7173 +               }
7174 +       }
7175 +
7176 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7177 +#endif
7178 +       DWC_WAITQ_FREE(wq->waitq);
7179 +       DWC_SPINLOCK_FREE(wq->lock);
7180 +       taskqueue_free(wq->taskq);
7181 +       DWC_FREE(wq);
7182 +}
7183 +
7184 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
7185 +                       char *format, ...)
7186 +{
7187 +       dwc_irqflags_t flags;
7188 +       work_container_t *container;
7189 +       static char name[128];
7190 +       va_list args;
7191 +
7192 +       va_start(args, format);
7193 +       DWC_VSNPRINTF(name, 128, format, args);
7194 +       va_end(args);
7195 +
7196 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7197 +       wq->pending++;
7198 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7199 +       DWC_WAITQ_TRIGGER(wq->waitq);
7200 +
7201 +       container = DWC_ALLOC_ATOMIC(sizeof(*container));
7202 +       if (!container) {
7203 +               DWC_ERROR("Cannot allocate memory for container");
7204 +               return;
7205 +       }
7206 +
7207 +       container->name = DWC_STRDUP(name);
7208 +       if (!container->name) {
7209 +               DWC_ERROR("Cannot allocate memory for container->name");
7210 +               DWC_FREE(container);
7211 +               return;
7212 +       }
7213 +
7214 +       container->cb = cb;
7215 +       container->data = data;
7216 +       container->wq = wq;
7217 +       container->hz = 0;
7218 +
7219 +       DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
7220 +
7221 +       TASK_INIT(&container->task, 0, do_work, container);
7222 +
7223 +#ifdef DEBUG
7224 +       DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
7225 +#endif
7226 +       taskqueue_enqueue_fast(wq->taskq, &container->task);
7227 +}
7228 +
7229 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
7230 +                               void *data, uint32_t time, char *format, ...)
7231 +{
7232 +       dwc_irqflags_t flags;
7233 +       work_container_t *container;
7234 +       static char name[128];
7235 +       struct timeval tv;
7236 +       va_list args;
7237 +
7238 +       va_start(args, format);
7239 +       DWC_VSNPRINTF(name, 128, format, args);
7240 +       va_end(args);
7241 +
7242 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
7243 +       wq->pending++;
7244 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
7245 +       DWC_WAITQ_TRIGGER(wq->waitq);
7246 +
7247 +       container = DWC_ALLOC_ATOMIC(sizeof(*container));
7248 +       if (!container) {
7249 +               DWC_ERROR("Cannot allocate memory for container");
7250 +               return;
7251 +       }
7252 +
7253 +       container->name = DWC_STRDUP(name);
7254 +       if (!container->name) {
7255 +               DWC_ERROR("Cannot allocate memory for container->name");
7256 +               DWC_FREE(container);
7257 +               return;
7258 +       }
7259 +
7260 +       container->cb = cb;
7261 +       container->data = data;
7262 +       container->wq = wq;
7263 +
7264 +       tv.tv_sec = time / 1000;
7265 +       tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
7266 +       container->hz = tvtohz(&tv);
7267 +
7268 +       DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
7269 +
7270 +       TASK_INIT(&container->task, 0, do_work, container);
7271 +
7272 +#ifdef DEBUG
7273 +       DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
7274 +#endif
7275 +       taskqueue_enqueue_fast(wq->taskq, &container->task);
7276 +}
7277 +
7278 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
7279 +{
7280 +       return wq->pending;
7281 +}
7282 --- /dev/null
7283 +++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c
7284 @@ -0,0 +1,1433 @@
7285 +#include <linux/kernel.h>
7286 +#include <linux/init.h>
7287 +#include <linux/module.h>
7288 +#include <linux/kthread.h>
7289 +
7290 +#ifdef DWC_CCLIB
7291 +# include "dwc_cc.h"
7292 +#endif
7293 +
7294 +#ifdef DWC_CRYPTOLIB
7295 +# include "dwc_modpow.h"
7296 +# include "dwc_dh.h"
7297 +# include "dwc_crypto.h"
7298 +#endif
7299 +
7300 +#ifdef DWC_NOTIFYLIB
7301 +# include "dwc_notifier.h"
7302 +#endif
7303 +
7304 +/* OS-Level Implementations */
7305 +
7306 +/* This is the Linux kernel implementation of the DWC platform library. */
7307 +#include <linux/moduleparam.h>
7308 +#include <linux/ctype.h>
7309 +#include <linux/crypto.h>
7310 +#include <linux/delay.h>
7311 +#include <linux/device.h>
7312 +#include <linux/dma-mapping.h>
7313 +#include <linux/cdev.h>
7314 +#include <linux/errno.h>
7315 +#include <linux/interrupt.h>
7316 +#include <linux/jiffies.h>
7317 +#include <linux/list.h>
7318 +#include <linux/pci.h>
7319 +#include <linux/random.h>
7320 +#include <linux/scatterlist.h>
7321 +#include <linux/slab.h>
7322 +#include <linux/stat.h>
7323 +#include <linux/string.h>
7324 +#include <linux/timer.h>
7325 +#include <linux/usb.h>
7326 +
7327 +#include <linux/version.h>
7328 +
7329 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
7330 +# include <linux/usb/gadget.h>
7331 +#else
7332 +# include <linux/usb_gadget.h>
7333 +#endif
7334 +
7335 +#include <asm/io.h>
7336 +#include <asm/page.h>
7337 +#include <asm/uaccess.h>
7338 +#include <asm/unaligned.h>
7339 +
7340 +#include "dwc_os.h"
7341 +#include "dwc_list.h"
7342 +
7343 +
7344 +/* MISC */
7345 +
7346 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
7347 +{
7348 +       return memset(dest, byte, size);
7349 +}
7350 +
7351 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
7352 +{
7353 +       return memcpy(dest, src, size);
7354 +}
7355 +
7356 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
7357 +{
7358 +       return memmove(dest, src, size);
7359 +}
7360 +
7361 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
7362 +{
7363 +       return memcmp(m1, m2, size);
7364 +}
7365 +
7366 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
7367 +{
7368 +       return strncmp(s1, s2, size);
7369 +}
7370 +
7371 +int DWC_STRCMP(void *s1, void *s2)
7372 +{
7373 +       return strcmp(s1, s2);
7374 +}
7375 +
7376 +int DWC_STRLEN(char const *str)
7377 +{
7378 +       return strlen(str);
7379 +}
7380 +
7381 +char *DWC_STRCPY(char *to, char const *from)
7382 +{
7383 +       return strcpy(to, from);
7384 +}
7385 +
7386 +char *DWC_STRDUP(char const *str)
7387 +{
7388 +       int len = DWC_STRLEN(str) + 1;
7389 +       char *new = DWC_ALLOC_ATOMIC(len);
7390 +
7391 +       if (!new) {
7392 +               return NULL;
7393 +       }
7394 +
7395 +       DWC_MEMCPY(new, str, len);
7396 +       return new;
7397 +}
7398 +
7399 +int DWC_ATOI(const char *str, int32_t *value)
7400 +{
7401 +       char *end = NULL;
7402 +
7403 +       *value = simple_strtol(str, &end, 0);
7404 +       if (*end == '\0') {
7405 +               return 0;
7406 +       }
7407 +
7408 +       return -1;
7409 +}
7410 +
7411 +int DWC_ATOUI(const char *str, uint32_t *value)
7412 +{
7413 +       char *end = NULL;
7414 +
7415 +       *value = simple_strtoul(str, &end, 0);
7416 +       if (*end == '\0') {
7417 +               return 0;
7418 +       }
7419 +
7420 +       return -1;
7421 +}
7422 +
7423 +
7424 +#ifdef DWC_UTFLIB
7425 +/* From usbstring.c */
7426 +
7427 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
7428 +{
7429 +       int     count = 0;
7430 +       u8      c;
7431 +       u16     uchar;
7432 +
7433 +       /* this insists on correct encodings, though not minimal ones.
7434 +        * BUT it currently rejects legit 4-byte UTF-8 code points,
7435 +        * which need surrogate pairs.  (Unicode 3.1 can use them.)
7436 +        */
7437 +       while (len != 0 && (c = (u8) *s++) != 0) {
7438 +               if (unlikely(c & 0x80)) {
7439 +                       // 2-byte sequence:
7440 +                       // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
7441 +                       if ((c & 0xe0) == 0xc0) {
7442 +                               uchar = (c & 0x1f) << 6;
7443 +
7444 +                               c = (u8) *s++;
7445 +                               if ((c & 0xc0) != 0xc0)
7446 +                                       goto fail;
7447 +                               c &= 0x3f;
7448 +                               uchar |= c;
7449 +
7450 +                       // 3-byte sequence (most CJKV characters):
7451 +                       // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
7452 +                       } else if ((c & 0xf0) == 0xe0) {
7453 +                               uchar = (c & 0x0f) << 12;
7454 +
7455 +                               c = (u8) *s++;
7456 +                               if ((c & 0xc0) != 0xc0)
7457 +                                       goto fail;
7458 +                               c &= 0x3f;
7459 +                               uchar |= c << 6;
7460 +
7461 +                               c = (u8) *s++;
7462 +                               if ((c & 0xc0) != 0xc0)
7463 +                                       goto fail;
7464 +                               c &= 0x3f;
7465 +                               uchar |= c;
7466 +
7467 +                               /* no bogus surrogates */
7468 +                               if (0xd800 <= uchar && uchar <= 0xdfff)
7469 +                                       goto fail;
7470 +
7471 +                       // 4-byte sequence (surrogate pairs, currently rare):
7472 +                       // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
7473 +                       //     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
7474 +                       // (uuuuu = wwww + 1)
7475 +                       // FIXME accept the surrogate code points (only)
7476 +                       } else
7477 +                               goto fail;
7478 +               } else
7479 +                       uchar = c;
7480 +               put_unaligned (cpu_to_le16 (uchar), cp++);
7481 +               count++;
7482 +               len--;
7483 +       }
7484 +       return count;
7485 +fail:
7486 +       return -1;
7487 +}
7488 +#endif /* DWC_UTFLIB */
7489 +
7490 +
7491 +/* dwc_debug.h */
7492 +
7493 +dwc_bool_t DWC_IN_IRQ(void)
7494 +{
7495 +       return in_irq();
7496 +}
7497 +
7498 +dwc_bool_t DWC_IN_BH(void)
7499 +{
7500 +       return in_softirq();
7501 +}
7502 +
7503 +void DWC_VPRINTF(char *format, va_list args)
7504 +{
7505 +       vprintk(format, args);
7506 +}
7507 +
7508 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
7509 +{
7510 +       return vsnprintf(str, size, format, args);
7511 +}
7512 +
7513 +void DWC_PRINTF(char *format, ...)
7514 +{
7515 +       va_list args;
7516 +
7517 +       va_start(args, format);
7518 +       DWC_VPRINTF(format, args);
7519 +       va_end(args);
7520 +}
7521 +
7522 +int DWC_SPRINTF(char *buffer, char *format, ...)
7523 +{
7524 +       int retval;
7525 +       va_list args;
7526 +
7527 +       va_start(args, format);
7528 +       retval = vsprintf(buffer, format, args);
7529 +       va_end(args);
7530 +       return retval;
7531 +}
7532 +
7533 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
7534 +{
7535 +       int retval;
7536 +       va_list args;
7537 +
7538 +       va_start(args, format);
7539 +       retval = vsnprintf(buffer, size, format, args);
7540 +       va_end(args);
7541 +       return retval;
7542 +}
7543 +
7544 +void __DWC_WARN(char *format, ...)
7545 +{
7546 +       va_list args;
7547 +
7548 +       va_start(args, format);
7549 +       DWC_PRINTF(KERN_WARNING);
7550 +       DWC_VPRINTF(format, args);
7551 +       va_end(args);
7552 +}
7553 +
7554 +void __DWC_ERROR(char *format, ...)
7555 +{
7556 +       va_list args;
7557 +
7558 +       va_start(args, format);
7559 +       DWC_PRINTF(KERN_ERR);
7560 +       DWC_VPRINTF(format, args);
7561 +       va_end(args);
7562 +}
7563 +
7564 +void DWC_EXCEPTION(char *format, ...)
7565 +{
7566 +       va_list args;
7567 +
7568 +       va_start(args, format);
7569 +       DWC_PRINTF(KERN_ERR);
7570 +       DWC_VPRINTF(format, args);
7571 +       va_end(args);
7572 +       BUG_ON(1);
7573 +}
7574 +
7575 +#ifdef DEBUG
7576 +void __DWC_DEBUG(char *format, ...)
7577 +{
7578 +       va_list args;
7579 +
7580 +       va_start(args, format);
7581 +       DWC_PRINTF(KERN_DEBUG);
7582 +       DWC_VPRINTF(format, args);
7583 +       va_end(args);
7584 +}
7585 +#endif
7586 +
7587 +
7588 +/* dwc_mem.h */
7589 +
7590 +#if 0
7591 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
7592 +                               uint32_t align,
7593 +                               uint32_t alloc)
7594 +{
7595 +       struct dma_pool *pool = dma_pool_create("Pool", NULL,
7596 +                                               size, align, alloc);
7597 +       return (dwc_pool_t *)pool;
7598 +}
7599 +
7600 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
7601 +{
7602 +       dma_pool_destroy((struct dma_pool *)pool);
7603 +}
7604 +
7605 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
7606 +{
7607 +       return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
7608 +}
7609 +
7610 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
7611 +{
7612 +       void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
7613 +       memset(..);
7614 +}
7615 +
7616 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
7617 +{
7618 +       dma_pool_free(pool, vaddr, daddr);
7619 +}
7620 +#endif
7621 +
7622 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
7623 +{
7624 +#ifdef xxCOSIM /* Only works for 32-bit cosim */
7625 +       void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL);
7626 +#else
7627 +       void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32);
7628 +#endif
7629 +       if (!buf) {
7630 +               return NULL;
7631 +       }
7632 +
7633 +       memset(buf, 0, (size_t)size);
7634 +       return buf;
7635 +}
7636 +
7637 +void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
7638 +{
7639 +       void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC);
7640 +       if (!buf) {
7641 +               return NULL;
7642 +       }
7643 +       memset(buf, 0, (size_t)size);
7644 +       return buf;
7645 +}
7646 +
7647 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
7648 +{
7649 +       dma_free_coherent(dma_ctx, size, virt_addr, dma_addr);
7650 +}
7651 +
7652 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
7653 +{
7654 +       return kzalloc(size, GFP_KERNEL);
7655 +}
7656 +
7657 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
7658 +{
7659 +       return kzalloc(size, GFP_ATOMIC);
7660 +}
7661 +
7662 +void __DWC_FREE(void *mem_ctx, void *addr)
7663 +{
7664 +       kfree(addr);
7665 +}
7666 +
7667 +
7668 +#ifdef DWC_CRYPTOLIB
7669 +/* dwc_crypto.h */
7670 +
7671 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
7672 +{
7673 +       get_random_bytes(buffer, length);
7674 +}
7675 +
7676 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
7677 +{
7678 +       struct crypto_blkcipher *tfm;
7679 +       struct blkcipher_desc desc;
7680 +       struct scatterlist sgd;
7681 +       struct scatterlist sgs;
7682 +
7683 +       tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
7684 +       if (tfm == NULL) {
7685 +               printk("failed to load transform for aes CBC\n");
7686 +               return -1;
7687 +       }
7688 +
7689 +       crypto_blkcipher_setkey(tfm, key, keylen);
7690 +       crypto_blkcipher_set_iv(tfm, iv, 16);
7691 +
7692 +       sg_init_one(&sgd, out, messagelen);
7693 +       sg_init_one(&sgs, message, messagelen);
7694 +
7695 +       desc.tfm = tfm;
7696 +       desc.flags = 0;
7697 +
7698 +       if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
7699 +               crypto_free_blkcipher(tfm);
7700 +               DWC_ERROR("AES CBC encryption failed");
7701 +               return -1;
7702 +       }
7703 +
7704 +       crypto_free_blkcipher(tfm);
7705 +       return 0;
7706 +}
7707 +
7708 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
7709 +{
7710 +       struct crypto_hash *tfm;
7711 +       struct hash_desc desc;
7712 +       struct scatterlist sg;
7713 +
7714 +       tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
7715 +       if (IS_ERR(tfm)) {
7716 +               DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm));
7717 +               return 0;
7718 +       }
7719 +       desc.tfm = tfm;
7720 +       desc.flags = 0;
7721 +
7722 +       sg_init_one(&sg, message, len);
7723 +       crypto_hash_digest(&desc, &sg, len, out);
7724 +       crypto_free_hash(tfm);
7725 +
7726 +       return 1;
7727 +}
7728 +
7729 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
7730 +                   uint8_t *key, uint32_t keylen, uint8_t *out)
7731 +{
7732 +       struct crypto_hash *tfm;
7733 +       struct hash_desc desc;
7734 +       struct scatterlist sg;
7735 +
7736 +       tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
7737 +       if (IS_ERR(tfm)) {
7738 +               DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm));
7739 +               return 0;
7740 +       }
7741 +       desc.tfm = tfm;
7742 +       desc.flags = 0;
7743 +
7744 +       sg_init_one(&sg, message, messagelen);
7745 +       crypto_hash_setkey(tfm, key, keylen);
7746 +       crypto_hash_digest(&desc, &sg, messagelen, out);
7747 +       crypto_free_hash(tfm);
7748 +
7749 +       return 1;
7750 +}
7751 +#endif /* DWC_CRYPTOLIB */
7752 +
7753 +
7754 +/* Byte Ordering Conversions */
7755 +
7756 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
7757 +{
7758 +#ifdef __LITTLE_ENDIAN
7759 +       return *p;
7760 +#else
7761 +       uint8_t *u_p = (uint8_t *)p;
7762 +
7763 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7764 +#endif
7765 +}
7766 +
7767 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
7768 +{
7769 +#ifdef __BIG_ENDIAN
7770 +       return *p;
7771 +#else
7772 +       uint8_t *u_p = (uint8_t *)p;
7773 +
7774 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7775 +#endif
7776 +}
7777 +
7778 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
7779 +{
7780 +#ifdef __LITTLE_ENDIAN
7781 +       return *p;
7782 +#else
7783 +       uint8_t *u_p = (uint8_t *)p;
7784 +
7785 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7786 +#endif
7787 +}
7788 +
7789 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
7790 +{
7791 +#ifdef __BIG_ENDIAN
7792 +       return *p;
7793 +#else
7794 +       uint8_t *u_p = (uint8_t *)p;
7795 +
7796 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
7797 +#endif
7798 +}
7799 +
7800 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
7801 +{
7802 +#ifdef __LITTLE_ENDIAN
7803 +       return *p;
7804 +#else
7805 +       uint8_t *u_p = (uint8_t *)p;
7806 +       return (u_p[1] | (u_p[0] << 8));
7807 +#endif
7808 +}
7809 +
7810 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
7811 +{
7812 +#ifdef __BIG_ENDIAN
7813 +       return *p;
7814 +#else
7815 +       uint8_t *u_p = (uint8_t *)p;
7816 +       return (u_p[1] | (u_p[0] << 8));
7817 +#endif
7818 +}
7819 +
7820 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
7821 +{
7822 +#ifdef __LITTLE_ENDIAN
7823 +       return *p;
7824 +#else
7825 +       uint8_t *u_p = (uint8_t *)p;
7826 +       return (u_p[1] | (u_p[0] << 8));
7827 +#endif
7828 +}
7829 +
7830 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
7831 +{
7832 +#ifdef __BIG_ENDIAN
7833 +       return *p;
7834 +#else
7835 +       uint8_t *u_p = (uint8_t *)p;
7836 +       return (u_p[1] | (u_p[0] << 8));
7837 +#endif
7838 +}
7839 +
7840 +
7841 +/* Registers */
7842 +
7843 +uint32_t DWC_READ_REG32(uint32_t volatile *reg)
7844 +{
7845 +       return readl(reg);
7846 +}
7847 +
7848 +#if 0
7849 +uint64_t DWC_READ_REG64(uint64_t volatile *reg)
7850 +{
7851 +}
7852 +#endif
7853 +
7854 +void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value)
7855 +{
7856 +       writel(value, reg);
7857 +}
7858 +
7859 +#if 0
7860 +void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value)
7861 +{
7862 +}
7863 +#endif
7864 +
7865 +void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
7866 +{
7867 +       writel((readl(reg) & ~clear_mask) | set_mask, reg);
7868 +}
7869 +
7870 +#if 0
7871 +void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask)
7872 +{
7873 +}
7874 +#endif
7875 +
7876 +
7877 +/* Locking */
7878 +
7879 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
7880 +{
7881 +       spinlock_t *sl = (spinlock_t *)1;
7882 +
7883 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7884 +       sl = DWC_ALLOC(sizeof(*sl));
7885 +       if (!sl) {
7886 +               DWC_ERROR("Cannot allocate memory for spinlock\n");
7887 +               return NULL;
7888 +       }
7889 +
7890 +       spin_lock_init(sl);
7891 +#endif
7892 +       return (dwc_spinlock_t *)sl;
7893 +}
7894 +
7895 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
7896 +{
7897 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7898 +       DWC_FREE(lock);
7899 +#endif
7900 +}
7901 +
7902 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
7903 +{
7904 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7905 +       spin_lock((spinlock_t *)lock);
7906 +#endif
7907 +}
7908 +
7909 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
7910 +{
7911 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7912 +       spin_unlock((spinlock_t *)lock);
7913 +#endif
7914 +}
7915 +
7916 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
7917 +{
7918 +       dwc_irqflags_t f;
7919 +
7920 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7921 +       spin_lock_irqsave((spinlock_t *)lock, f);
7922 +#else
7923 +       local_irq_save(f);
7924 +#endif
7925 +       *flags = f;
7926 +}
7927 +
7928 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
7929 +{
7930 +#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP)
7931 +       spin_unlock_irqrestore((spinlock_t *)lock, flags);
7932 +#else
7933 +       local_irq_restore(flags);
7934 +#endif
7935 +}
7936 +
7937 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
7938 +{
7939 +       struct mutex *m;
7940 +       dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex));
7941 +
7942 +       if (!mutex) {
7943 +               DWC_ERROR("Cannot allocate memory for mutex\n");
7944 +               return NULL;
7945 +       }
7946 +
7947 +       m = (struct mutex *)mutex;
7948 +       mutex_init(m);
7949 +       return mutex;
7950 +}
7951 +
7952 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
7953 +#else
7954 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
7955 +{
7956 +       mutex_destroy((struct mutex *)mutex);
7957 +       DWC_FREE(mutex);
7958 +}
7959 +#endif
7960 +
7961 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
7962 +{
7963 +       struct mutex *m = (struct mutex *)mutex;
7964 +       mutex_lock(m);
7965 +}
7966 +
7967 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
7968 +{
7969 +       struct mutex *m = (struct mutex *)mutex;
7970 +       return mutex_trylock(m);
7971 +}
7972 +
7973 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
7974 +{
7975 +       struct mutex *m = (struct mutex *)mutex;
7976 +       mutex_unlock(m);
7977 +}
7978 +
7979 +
7980 +/* Timing */
7981 +
7982 +void DWC_UDELAY(uint32_t usecs)
7983 +{
7984 +       udelay(usecs);
7985 +}
7986 +
7987 +void DWC_MDELAY(uint32_t msecs)
7988 +{
7989 +       mdelay(msecs);
7990 +}
7991 +
7992 +void DWC_MSLEEP(uint32_t msecs)
7993 +{
7994 +       msleep(msecs);
7995 +}
7996 +
7997 +uint32_t DWC_TIME(void)
7998 +{
7999 +       return jiffies_to_msecs(jiffies);
8000 +}
8001 +
8002 +
8003 +/* Timers */
8004 +
8005 +struct dwc_timer {
8006 +       struct timer_list *t;
8007 +       char *name;
8008 +       dwc_timer_callback_t cb;
8009 +       void *data;
8010 +       uint8_t scheduled;
8011 +       dwc_spinlock_t *lock;
8012 +};
8013 +
8014 +static void timer_callback(unsigned long data)
8015 +{
8016 +       dwc_timer_t *timer = (dwc_timer_t *)data;
8017 +       dwc_irqflags_t flags;
8018 +
8019 +       DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8020 +       timer->scheduled = 0;
8021 +       DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8022 +       DWC_DEBUGC("Timer %s callback", timer->name);
8023 +       timer->cb(timer->data);
8024 +}
8025 +
8026 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
8027 +{
8028 +       dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
8029 +
8030 +       if (!t) {
8031 +               DWC_ERROR("Cannot allocate memory for timer");
8032 +               return NULL;
8033 +       }
8034 +
8035 +       t->t = DWC_ALLOC(sizeof(*t->t));
8036 +       if (!t->t) {
8037 +               DWC_ERROR("Cannot allocate memory for timer->t");
8038 +               goto no_timer;
8039 +       }
8040 +
8041 +       t->name = DWC_STRDUP(name);
8042 +       if (!t->name) {
8043 +               DWC_ERROR("Cannot allocate memory for timer->name");
8044 +               goto no_name;
8045 +       }
8046 +
8047 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
8048 +       DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock);
8049 +#else
8050 +       t->lock = DWC_SPINLOCK_ALLOC();
8051 +#endif
8052 +       if (!t->lock) {
8053 +               DWC_ERROR("Cannot allocate memory for lock");
8054 +               goto no_lock;
8055 +       }
8056 +
8057 +       t->scheduled = 0;
8058 +       t->t->expires = jiffies;
8059 +       setup_timer(t->t, timer_callback, (unsigned long)t);
8060 +
8061 +       t->cb = cb;
8062 +       t->data = data;
8063 +
8064 +       return t;
8065 +
8066 + no_lock:
8067 +       DWC_FREE(t->name);
8068 + no_name:
8069 +       DWC_FREE(t->t);
8070 + no_timer:
8071 +       DWC_FREE(t);
8072 +       return NULL;
8073 +}
8074 +
8075 +void DWC_TIMER_FREE(dwc_timer_t *timer)
8076 +{
8077 +       dwc_irqflags_t flags;
8078 +
8079 +       DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8080 +
8081 +       if (timer->scheduled) {
8082 +               del_timer(timer->t);
8083 +               timer->scheduled = 0;
8084 +       }
8085 +
8086 +       DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8087 +       DWC_SPINLOCK_FREE(timer->lock);
8088 +       DWC_FREE(timer->t);
8089 +       DWC_FREE(timer->name);
8090 +       DWC_FREE(timer);
8091 +}
8092 +
8093 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
8094 +{
8095 +       dwc_irqflags_t flags;
8096 +
8097 +       DWC_SPINLOCK_IRQSAVE(timer->lock, &flags);
8098 +
8099 +       if (!timer->scheduled) {
8100 +               timer->scheduled = 1;
8101 +               DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time);
8102 +               timer->t->expires = jiffies + msecs_to_jiffies(time);
8103 +               add_timer(timer->t);
8104 +       } else {
8105 +               DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time);
8106 +               mod_timer(timer->t, jiffies + msecs_to_jiffies(time));
8107 +       }
8108 +
8109 +       DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags);
8110 +}
8111 +
8112 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
8113 +{
8114 +       del_timer(timer->t);
8115 +}
8116 +
8117 +
8118 +/* Wait Queues */
8119 +
8120 +struct dwc_waitq {
8121 +       wait_queue_head_t queue;
8122 +       int abort;
8123 +};
8124 +
8125 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
8126 +{
8127 +       dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
8128 +
8129 +       if (!wq) {
8130 +               DWC_ERROR("Cannot allocate memory for waitqueue\n");
8131 +               return NULL;
8132 +       }
8133 +
8134 +       init_waitqueue_head(&wq->queue);
8135 +       wq->abort = 0;
8136 +       return wq;
8137 +}
8138 +
8139 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
8140 +{
8141 +       DWC_FREE(wq);
8142 +}
8143 +
8144 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
8145 +{
8146 +       int result = wait_event_interruptible(wq->queue,
8147 +                                             cond(data) || wq->abort);
8148 +       if (result == -ERESTARTSYS) {
8149 +               wq->abort = 0;
8150 +               return -DWC_E_RESTART;
8151 +       }
8152 +
8153 +       if (wq->abort == 1) {
8154 +               wq->abort = 0;
8155 +               return -DWC_E_ABORT;
8156 +       }
8157 +
8158 +       wq->abort = 0;
8159 +
8160 +       if (result == 0) {
8161 +               return 0;
8162 +       }
8163 +
8164 +       return -DWC_E_UNKNOWN;
8165 +}
8166 +
8167 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
8168 +                              void *data, int32_t msecs)
8169 +{
8170 +       int32_t tmsecs;
8171 +       int result = wait_event_interruptible_timeout(wq->queue,
8172 +                                                     cond(data) || wq->abort,
8173 +                                                     msecs_to_jiffies(msecs));
8174 +       if (result == -ERESTARTSYS) {
8175 +               wq->abort = 0;
8176 +               return -DWC_E_RESTART;
8177 +       }
8178 +
8179 +       if (wq->abort == 1) {
8180 +               wq->abort = 0;
8181 +               return -DWC_E_ABORT;
8182 +       }
8183 +
8184 +       wq->abort = 0;
8185 +
8186 +       if (result > 0) {
8187 +               tmsecs = jiffies_to_msecs(result);
8188 +               if (!tmsecs) {
8189 +                       return 1;
8190 +               }
8191 +
8192 +               return tmsecs;
8193 +       }
8194 +
8195 +       if (result == 0) {
8196 +               return -DWC_E_TIMEOUT;
8197 +       }
8198 +
8199 +       return -DWC_E_UNKNOWN;
8200 +}
8201 +
8202 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
8203 +{
8204 +       wq->abort = 0;
8205 +       wake_up_interruptible(&wq->queue);
8206 +}
8207 +
8208 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
8209 +{
8210 +       wq->abort = 1;
8211 +       wake_up_interruptible(&wq->queue);
8212 +}
8213 +
8214 +
8215 +/* Threading */
8216 +
8217 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
8218 +{
8219 +       struct task_struct *thread = kthread_run(func, data, name);
8220 +
8221 +       if (thread == ERR_PTR(-ENOMEM)) {
8222 +               return NULL;
8223 +       }
8224 +
8225 +       return (dwc_thread_t *)thread;
8226 +}
8227 +
8228 +int DWC_THREAD_STOP(dwc_thread_t *thread)
8229 +{
8230 +       return kthread_stop((struct task_struct *)thread);
8231 +}
8232 +
8233 +dwc_bool_t DWC_THREAD_SHOULD_STOP(void)
8234 +{
8235 +       return kthread_should_stop();
8236 +}
8237 +
8238 +
8239 +/* tasklets
8240 + - run in interrupt context (cannot sleep)
8241 + - each tasklet runs on a single CPU
8242 + - different tasklets can be running simultaneously on different CPUs
8243 + */
8244 +struct dwc_tasklet {
8245 +       struct tasklet_struct t;
8246 +       dwc_tasklet_callback_t cb;
8247 +       void *data;
8248 +};
8249 +
8250 +static void tasklet_callback(unsigned long data)
8251 +{
8252 +       dwc_tasklet_t *t = (dwc_tasklet_t *)data;
8253 +       t->cb(t->data);
8254 +}
8255 +
8256 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
8257 +{
8258 +       dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t));
8259 +
8260 +       if (t) {
8261 +               t->cb = cb;
8262 +               t->data = data;
8263 +               tasklet_init(&t->t, tasklet_callback, (unsigned long)t);
8264 +       } else {
8265 +               DWC_ERROR("Cannot allocate memory for tasklet\n");
8266 +       }
8267 +
8268 +       return t;
8269 +}
8270 +
8271 +void DWC_TASK_FREE(dwc_tasklet_t *task)
8272 +{
8273 +       DWC_FREE(task);
8274 +}
8275 +
8276 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
8277 +{
8278 +       tasklet_schedule(&task->t);
8279 +}
8280 +
8281 +void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task)
8282 +{
8283 +       tasklet_hi_schedule(&task->t);
8284 +}
8285 +
8286 +
8287 +/* workqueues
8288 + - run in process context (can sleep)
8289 + */
8290 +typedef struct work_container {
8291 +       dwc_work_callback_t cb;
8292 +       void *data;
8293 +       dwc_workq_t *wq;
8294 +       char *name;
8295 +
8296 +#ifdef DEBUG
8297 +       DWC_CIRCLEQ_ENTRY(work_container) entry;
8298 +#endif
8299 +       struct delayed_work work;
8300 +} work_container_t;
8301 +
8302 +#ifdef DEBUG
8303 +DWC_CIRCLEQ_HEAD(work_container_queue, work_container);
8304 +#endif
8305 +
8306 +struct dwc_workq {
8307 +       struct workqueue_struct *wq;
8308 +       dwc_spinlock_t *lock;
8309 +       dwc_waitq_t *waitq;
8310 +       int pending;
8311 +
8312 +#ifdef DEBUG
8313 +       struct work_container_queue entries;
8314 +#endif
8315 +};
8316 +
8317 +static void do_work(struct work_struct *work)
8318 +{
8319 +       dwc_irqflags_t flags;
8320 +       struct delayed_work *dw = container_of(work, struct delayed_work, work);
8321 +       work_container_t *container = container_of(dw, struct work_container, work);
8322 +       dwc_workq_t *wq = container->wq;
8323 +
8324 +       container->cb(container->data);
8325 +
8326 +#ifdef DEBUG
8327 +       DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry);
8328 +#endif
8329 +       DWC_DEBUGC("Work done: %s, container=%p", container->name, container);
8330 +       if (container->name) {
8331 +               DWC_FREE(container->name);
8332 +       }
8333 +       DWC_FREE(container);
8334 +
8335 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8336 +       wq->pending--;
8337 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8338 +       DWC_WAITQ_TRIGGER(wq->waitq);
8339 +}
8340 +
8341 +static int work_done(void *data)
8342 +{
8343 +       dwc_workq_t *workq = (dwc_workq_t *)data;
8344 +       return workq->pending == 0;
8345 +}
8346 +
8347 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
8348 +{
8349 +       return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
8350 +}
8351 +
8352 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
8353 +{
8354 +       dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
8355 +
8356 +       if (!wq) {
8357 +               return NULL;
8358 +       }
8359 +
8360 +       wq->wq = create_singlethread_workqueue(name);
8361 +       if (!wq->wq) {
8362 +               goto no_wq;
8363 +       }
8364 +
8365 +       wq->pending = 0;
8366 +
8367 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
8368 +       DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock);
8369 +#else
8370 +       wq->lock = DWC_SPINLOCK_ALLOC();
8371 +#endif
8372 +       if (!wq->lock) {
8373 +               goto no_lock;
8374 +       }
8375 +
8376 +       wq->waitq = DWC_WAITQ_ALLOC();
8377 +       if (!wq->waitq) {
8378 +               goto no_waitq;
8379 +       }
8380 +
8381 +#ifdef DEBUG
8382 +       DWC_CIRCLEQ_INIT(&wq->entries);
8383 +#endif
8384 +       return wq;
8385 +
8386 + no_waitq:
8387 +       DWC_SPINLOCK_FREE(wq->lock);
8388 + no_lock:
8389 +       destroy_workqueue(wq->wq);
8390 + no_wq:
8391 +       DWC_FREE(wq);
8392 +
8393 +       return NULL;
8394 +}
8395 +
8396 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
8397 +{
8398 +#ifdef DEBUG
8399 +       if (wq->pending != 0) {
8400 +               struct work_container *wc;
8401 +               DWC_ERROR("Destroying work queue with pending work");
8402 +               DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) {
8403 +                       DWC_ERROR("Work %s still pending", wc->name);
8404 +               }
8405 +       }
8406 +#endif
8407 +       destroy_workqueue(wq->wq);
8408 +       DWC_SPINLOCK_FREE(wq->lock);
8409 +       DWC_WAITQ_FREE(wq->waitq);
8410 +       DWC_FREE(wq);
8411 +}
8412 +
8413 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
8414 +                       char *format, ...)
8415 +{
8416 +       dwc_irqflags_t flags;
8417 +       work_container_t *container;
8418 +       static char name[128];
8419 +       va_list args;
8420 +
8421 +       va_start(args, format);
8422 +       DWC_VSNPRINTF(name, 128, format, args);
8423 +       va_end(args);
8424 +
8425 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8426 +       wq->pending++;
8427 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8428 +       DWC_WAITQ_TRIGGER(wq->waitq);
8429 +
8430 +       container = DWC_ALLOC_ATOMIC(sizeof(*container));
8431 +       if (!container) {
8432 +               DWC_ERROR("Cannot allocate memory for container\n");
8433 +               return;
8434 +       }
8435 +
8436 +       container->name = DWC_STRDUP(name);
8437 +       if (!container->name) {
8438 +               DWC_ERROR("Cannot allocate memory for container->name\n");
8439 +               DWC_FREE(container);
8440 +               return;
8441 +       }
8442 +
8443 +       container->cb = cb;
8444 +       container->data = data;
8445 +       container->wq = wq;
8446 +       DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
8447 +       INIT_WORK(&container->work.work, do_work);
8448 +
8449 +#ifdef DEBUG
8450 +       DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
8451 +#endif
8452 +       queue_work(wq->wq, &container->work.work);
8453 +}
8454 +
8455 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
8456 +                               void *data, uint32_t time, char *format, ...)
8457 +{
8458 +       dwc_irqflags_t flags;
8459 +       work_container_t *container;
8460 +       static char name[128];
8461 +       va_list args;
8462 +
8463 +       va_start(args, format);
8464 +       DWC_VSNPRINTF(name, 128, format, args);
8465 +       va_end(args);
8466 +
8467 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
8468 +       wq->pending++;
8469 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
8470 +       DWC_WAITQ_TRIGGER(wq->waitq);
8471 +
8472 +       container = DWC_ALLOC_ATOMIC(sizeof(*container));
8473 +       if (!container) {
8474 +               DWC_ERROR("Cannot allocate memory for container\n");
8475 +               return;
8476 +       }
8477 +
8478 +       container->name = DWC_STRDUP(name);
8479 +       if (!container->name) {
8480 +               DWC_ERROR("Cannot allocate memory for container->name\n");
8481 +               DWC_FREE(container);
8482 +               return;
8483 +       }
8484 +
8485 +       container->cb = cb;
8486 +       container->data = data;
8487 +       container->wq = wq;
8488 +       DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container);
8489 +       INIT_DELAYED_WORK(&container->work, do_work);
8490 +
8491 +#ifdef DEBUG
8492 +       DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry);
8493 +#endif
8494 +       queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time));
8495 +}
8496 +
8497 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
8498 +{
8499 +       return wq->pending;
8500 +}
8501 +
8502 +
8503 +#ifdef DWC_LIBMODULE
8504 +
8505 +#ifdef DWC_CCLIB
8506 +/* CC */
8507 +EXPORT_SYMBOL(dwc_cc_if_alloc);
8508 +EXPORT_SYMBOL(dwc_cc_if_free);
8509 +EXPORT_SYMBOL(dwc_cc_clear);
8510 +EXPORT_SYMBOL(dwc_cc_add);
8511 +EXPORT_SYMBOL(dwc_cc_remove);
8512 +EXPORT_SYMBOL(dwc_cc_change);
8513 +EXPORT_SYMBOL(dwc_cc_data_for_save);
8514 +EXPORT_SYMBOL(dwc_cc_restore_from_data);
8515 +EXPORT_SYMBOL(dwc_cc_match_chid);
8516 +EXPORT_SYMBOL(dwc_cc_match_cdid);
8517 +EXPORT_SYMBOL(dwc_cc_ck);
8518 +EXPORT_SYMBOL(dwc_cc_chid);
8519 +EXPORT_SYMBOL(dwc_cc_cdid);
8520 +EXPORT_SYMBOL(dwc_cc_name);
8521 +#endif /* DWC_CCLIB */
8522 +
8523 +#ifdef DWC_CRYPTOLIB
8524 +# ifndef CONFIG_MACH_IPMATE
8525 +/* Modpow */
8526 +EXPORT_SYMBOL(dwc_modpow);
8527 +
8528 +/* DH */
8529 +EXPORT_SYMBOL(dwc_dh_modpow);
8530 +EXPORT_SYMBOL(dwc_dh_derive_keys);
8531 +EXPORT_SYMBOL(dwc_dh_pk);
8532 +# endif        /* CONFIG_MACH_IPMATE */
8533 +
8534 +/* Crypto */
8535 +EXPORT_SYMBOL(dwc_wusb_aes_encrypt);
8536 +EXPORT_SYMBOL(dwc_wusb_cmf);
8537 +EXPORT_SYMBOL(dwc_wusb_prf);
8538 +EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce);
8539 +EXPORT_SYMBOL(dwc_wusb_gen_nonce);
8540 +EXPORT_SYMBOL(dwc_wusb_gen_key);
8541 +EXPORT_SYMBOL(dwc_wusb_gen_mic);
8542 +#endif /* DWC_CRYPTOLIB */
8543 +
8544 +/* Notification */
8545 +#ifdef DWC_NOTIFYLIB
8546 +EXPORT_SYMBOL(dwc_alloc_notification_manager);
8547 +EXPORT_SYMBOL(dwc_free_notification_manager);
8548 +EXPORT_SYMBOL(dwc_register_notifier);
8549 +EXPORT_SYMBOL(dwc_unregister_notifier);
8550 +EXPORT_SYMBOL(dwc_add_observer);
8551 +EXPORT_SYMBOL(dwc_remove_observer);
8552 +EXPORT_SYMBOL(dwc_notify);
8553 +#endif
8554 +
8555 +/* Memory Debugging Routines */
8556 +#ifdef DWC_DEBUG_MEMORY
8557 +EXPORT_SYMBOL(dwc_alloc_debug);
8558 +EXPORT_SYMBOL(dwc_alloc_atomic_debug);
8559 +EXPORT_SYMBOL(dwc_free_debug);
8560 +EXPORT_SYMBOL(dwc_dma_alloc_debug);
8561 +EXPORT_SYMBOL(dwc_dma_free_debug);
8562 +#endif
8563 +
8564 +EXPORT_SYMBOL(DWC_MEMSET);
8565 +EXPORT_SYMBOL(DWC_MEMCPY);
8566 +EXPORT_SYMBOL(DWC_MEMMOVE);
8567 +EXPORT_SYMBOL(DWC_MEMCMP);
8568 +EXPORT_SYMBOL(DWC_STRNCMP);
8569 +EXPORT_SYMBOL(DWC_STRCMP);
8570 +EXPORT_SYMBOL(DWC_STRLEN);
8571 +EXPORT_SYMBOL(DWC_STRCPY);
8572 +EXPORT_SYMBOL(DWC_STRDUP);
8573 +EXPORT_SYMBOL(DWC_ATOI);
8574 +EXPORT_SYMBOL(DWC_ATOUI);
8575 +
8576 +#ifdef DWC_UTFLIB
8577 +EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE);
8578 +#endif /* DWC_UTFLIB */
8579 +
8580 +EXPORT_SYMBOL(DWC_IN_IRQ);
8581 +EXPORT_SYMBOL(DWC_IN_BH);
8582 +EXPORT_SYMBOL(DWC_VPRINTF);
8583 +EXPORT_SYMBOL(DWC_VSNPRINTF);
8584 +EXPORT_SYMBOL(DWC_PRINTF);
8585 +EXPORT_SYMBOL(DWC_SPRINTF);
8586 +EXPORT_SYMBOL(DWC_SNPRINTF);
8587 +EXPORT_SYMBOL(__DWC_WARN);
8588 +EXPORT_SYMBOL(__DWC_ERROR);
8589 +EXPORT_SYMBOL(DWC_EXCEPTION);
8590 +
8591 +#ifdef DEBUG
8592 +EXPORT_SYMBOL(__DWC_DEBUG);
8593 +#endif
8594 +
8595 +EXPORT_SYMBOL(__DWC_DMA_ALLOC);
8596 +EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC);
8597 +EXPORT_SYMBOL(__DWC_DMA_FREE);
8598 +EXPORT_SYMBOL(__DWC_ALLOC);
8599 +EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC);
8600 +EXPORT_SYMBOL(__DWC_FREE);
8601 +
8602 +#ifdef DWC_CRYPTOLIB
8603 +EXPORT_SYMBOL(DWC_RANDOM_BYTES);
8604 +EXPORT_SYMBOL(DWC_AES_CBC);
8605 +EXPORT_SYMBOL(DWC_SHA256);
8606 +EXPORT_SYMBOL(DWC_HMAC_SHA256);
8607 +#endif
8608 +
8609 +EXPORT_SYMBOL(DWC_CPU_TO_LE32);
8610 +EXPORT_SYMBOL(DWC_CPU_TO_BE32);
8611 +EXPORT_SYMBOL(DWC_LE32_TO_CPU);
8612 +EXPORT_SYMBOL(DWC_BE32_TO_CPU);
8613 +EXPORT_SYMBOL(DWC_CPU_TO_LE16);
8614 +EXPORT_SYMBOL(DWC_CPU_TO_BE16);
8615 +EXPORT_SYMBOL(DWC_LE16_TO_CPU);
8616 +EXPORT_SYMBOL(DWC_BE16_TO_CPU);
8617 +EXPORT_SYMBOL(DWC_READ_REG32);
8618 +EXPORT_SYMBOL(DWC_WRITE_REG32);
8619 +EXPORT_SYMBOL(DWC_MODIFY_REG32);
8620 +
8621 +#if 0
8622 +EXPORT_SYMBOL(DWC_READ_REG64);
8623 +EXPORT_SYMBOL(DWC_WRITE_REG64);
8624 +EXPORT_SYMBOL(DWC_MODIFY_REG64);
8625 +#endif
8626 +
8627 +EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC);
8628 +EXPORT_SYMBOL(DWC_SPINLOCK_FREE);
8629 +EXPORT_SYMBOL(DWC_SPINLOCK);
8630 +EXPORT_SYMBOL(DWC_SPINUNLOCK);
8631 +EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE);
8632 +EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE);
8633 +EXPORT_SYMBOL(DWC_MUTEX_ALLOC);
8634 +
8635 +#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES))
8636 +EXPORT_SYMBOL(DWC_MUTEX_FREE);
8637 +#endif
8638 +
8639 +EXPORT_SYMBOL(DWC_MUTEX_LOCK);
8640 +EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK);
8641 +EXPORT_SYMBOL(DWC_MUTEX_UNLOCK);
8642 +EXPORT_SYMBOL(DWC_UDELAY);
8643 +EXPORT_SYMBOL(DWC_MDELAY);
8644 +EXPORT_SYMBOL(DWC_MSLEEP);
8645 +EXPORT_SYMBOL(DWC_TIME);
8646 +EXPORT_SYMBOL(DWC_TIMER_ALLOC);
8647 +EXPORT_SYMBOL(DWC_TIMER_FREE);
8648 +EXPORT_SYMBOL(DWC_TIMER_SCHEDULE);
8649 +EXPORT_SYMBOL(DWC_TIMER_CANCEL);
8650 +EXPORT_SYMBOL(DWC_WAITQ_ALLOC);
8651 +EXPORT_SYMBOL(DWC_WAITQ_FREE);
8652 +EXPORT_SYMBOL(DWC_WAITQ_WAIT);
8653 +EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT);
8654 +EXPORT_SYMBOL(DWC_WAITQ_TRIGGER);
8655 +EXPORT_SYMBOL(DWC_WAITQ_ABORT);
8656 +EXPORT_SYMBOL(DWC_THREAD_RUN);
8657 +EXPORT_SYMBOL(DWC_THREAD_STOP);
8658 +EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP);
8659 +EXPORT_SYMBOL(DWC_TASK_ALLOC);
8660 +EXPORT_SYMBOL(DWC_TASK_FREE);
8661 +EXPORT_SYMBOL(DWC_TASK_SCHEDULE);
8662 +EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE);
8663 +EXPORT_SYMBOL(DWC_WORKQ_ALLOC);
8664 +EXPORT_SYMBOL(DWC_WORKQ_FREE);
8665 +EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE);
8666 +EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED);
8667 +EXPORT_SYMBOL(DWC_WORKQ_PENDING);
8668 +
8669 +static int dwc_common_port_init_module(void)
8670 +{
8671 +       int result = 0;
8672 +
8673 +       printk(KERN_DEBUG "Module dwc_common_port init\n" );
8674 +
8675 +#ifdef DWC_DEBUG_MEMORY
8676 +       result = dwc_memory_debug_start(NULL);
8677 +       if (result) {
8678 +               printk(KERN_ERR
8679 +                      "dwc_memory_debug_start() failed with error %d\n",
8680 +                      result);
8681 +               return result;
8682 +       }
8683 +#endif
8684 +
8685 +#ifdef DWC_NOTIFYLIB
8686 +       result = dwc_alloc_notification_manager(NULL, NULL);
8687 +       if (result) {
8688 +               printk(KERN_ERR
8689 +                      "dwc_alloc_notification_manager() failed with error %d\n",
8690 +                      result);
8691 +               return result;
8692 +       }
8693 +#endif
8694 +       return result;
8695 +}
8696 +
8697 +static void dwc_common_port_exit_module(void)
8698 +{
8699 +       printk(KERN_DEBUG "Module dwc_common_port exit\n" );
8700 +
8701 +#ifdef DWC_NOTIFYLIB
8702 +       dwc_free_notification_manager();
8703 +#endif
8704 +
8705 +#ifdef DWC_DEBUG_MEMORY
8706 +       dwc_memory_debug_stop();
8707 +#endif
8708 +}
8709 +
8710 +module_init(dwc_common_port_init_module);
8711 +module_exit(dwc_common_port_exit_module);
8712 +
8713 +MODULE_DESCRIPTION("DWC Common Library - Portable version");
8714 +MODULE_AUTHOR("Synopsys Inc.");
8715 +MODULE_LICENSE ("GPL");
8716 +
8717 +#endif /* DWC_LIBMODULE */
8718 --- /dev/null
8719 +++ b/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c
8720 @@ -0,0 +1,1275 @@
8721 +#include "dwc_os.h"
8722 +#include "dwc_list.h"
8723 +
8724 +#ifdef DWC_CCLIB
8725 +# include "dwc_cc.h"
8726 +#endif
8727 +
8728 +#ifdef DWC_CRYPTOLIB
8729 +# include "dwc_modpow.h"
8730 +# include "dwc_dh.h"
8731 +# include "dwc_crypto.h"
8732 +#endif
8733 +
8734 +#ifdef DWC_NOTIFYLIB
8735 +# include "dwc_notifier.h"
8736 +#endif
8737 +
8738 +/* OS-Level Implementations */
8739 +
8740 +/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */
8741 +
8742 +
8743 +/* MISC */
8744 +
8745 +void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size)
8746 +{
8747 +       return memset(dest, byte, size);
8748 +}
8749 +
8750 +void *DWC_MEMCPY(void *dest, void const *src, uint32_t size)
8751 +{
8752 +       return memcpy(dest, src, size);
8753 +}
8754 +
8755 +void *DWC_MEMMOVE(void *dest, void *src, uint32_t size)
8756 +{
8757 +       bcopy(src, dest, size);
8758 +       return dest;
8759 +}
8760 +
8761 +int DWC_MEMCMP(void *m1, void *m2, uint32_t size)
8762 +{
8763 +       return memcmp(m1, m2, size);
8764 +}
8765 +
8766 +int DWC_STRNCMP(void *s1, void *s2, uint32_t size)
8767 +{
8768 +       return strncmp(s1, s2, size);
8769 +}
8770 +
8771 +int DWC_STRCMP(void *s1, void *s2)
8772 +{
8773 +       return strcmp(s1, s2);
8774 +}
8775 +
8776 +int DWC_STRLEN(char const *str)
8777 +{
8778 +       return strlen(str);
8779 +}
8780 +
8781 +char *DWC_STRCPY(char *to, char const *from)
8782 +{
8783 +       return strcpy(to, from);
8784 +}
8785 +
8786 +char *DWC_STRDUP(char const *str)
8787 +{
8788 +       int len = DWC_STRLEN(str) + 1;
8789 +       char *new = DWC_ALLOC_ATOMIC(len);
8790 +
8791 +       if (!new) {
8792 +               return NULL;
8793 +       }
8794 +
8795 +       DWC_MEMCPY(new, str, len);
8796 +       return new;
8797 +}
8798 +
8799 +int DWC_ATOI(char *str, int32_t *value)
8800 +{
8801 +       char *end = NULL;
8802 +
8803 +       /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul'
8804 +        * should be equivalent on 2's complement machines
8805 +        */
8806 +       *value = strtoul(str, &end, 0);
8807 +       if (*end == '\0') {
8808 +               return 0;
8809 +       }
8810 +
8811 +       return -1;
8812 +}
8813 +
8814 +int DWC_ATOUI(char *str, uint32_t *value)
8815 +{
8816 +       char *end = NULL;
8817 +
8818 +       *value = strtoul(str, &end, 0);
8819 +       if (*end == '\0') {
8820 +               return 0;
8821 +       }
8822 +
8823 +       return -1;
8824 +}
8825 +
8826 +
8827 +#ifdef DWC_UTFLIB
8828 +/* From usbstring.c */
8829 +
8830 +int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len)
8831 +{
8832 +       int     count = 0;
8833 +       u8      c;
8834 +       u16     uchar;
8835 +
8836 +       /* this insists on correct encodings, though not minimal ones.
8837 +        * BUT it currently rejects legit 4-byte UTF-8 code points,
8838 +        * which need surrogate pairs.  (Unicode 3.1 can use them.)
8839 +        */
8840 +       while (len != 0 && (c = (u8) *s++) != 0) {
8841 +               if (unlikely(c & 0x80)) {
8842 +                       // 2-byte sequence:
8843 +                       // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
8844 +                       if ((c & 0xe0) == 0xc0) {
8845 +                               uchar = (c & 0x1f) << 6;
8846 +
8847 +                               c = (u8) *s++;
8848 +                               if ((c & 0xc0) != 0xc0)
8849 +                                       goto fail;
8850 +                               c &= 0x3f;
8851 +                               uchar |= c;
8852 +
8853 +                       // 3-byte sequence (most CJKV characters):
8854 +                       // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
8855 +                       } else if ((c & 0xf0) == 0xe0) {
8856 +                               uchar = (c & 0x0f) << 12;
8857 +
8858 +                               c = (u8) *s++;
8859 +                               if ((c & 0xc0) != 0xc0)
8860 +                                       goto fail;
8861 +                               c &= 0x3f;
8862 +                               uchar |= c << 6;
8863 +
8864 +                               c = (u8) *s++;
8865 +                               if ((c & 0xc0) != 0xc0)
8866 +                                       goto fail;
8867 +                               c &= 0x3f;
8868 +                               uchar |= c;
8869 +
8870 +                               /* no bogus surrogates */
8871 +                               if (0xd800 <= uchar && uchar <= 0xdfff)
8872 +                                       goto fail;
8873 +
8874 +                       // 4-byte sequence (surrogate pairs, currently rare):
8875 +                       // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
8876 +                       //     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
8877 +                       // (uuuuu = wwww + 1)
8878 +                       // FIXME accept the surrogate code points (only)
8879 +                       } else
8880 +                               goto fail;
8881 +               } else
8882 +                       uchar = c;
8883 +               put_unaligned (cpu_to_le16 (uchar), cp++);
8884 +               count++;
8885 +               len--;
8886 +       }
8887 +       return count;
8888 +fail:
8889 +       return -1;
8890 +}
8891 +
8892 +#endif /* DWC_UTFLIB */
8893 +
8894 +
8895 +/* dwc_debug.h */
8896 +
8897 +dwc_bool_t DWC_IN_IRQ(void)
8898 +{
8899 +//     return in_irq();
8900 +       return 0;
8901 +}
8902 +
8903 +dwc_bool_t DWC_IN_BH(void)
8904 +{
8905 +//     return in_softirq();
8906 +       return 0;
8907 +}
8908 +
8909 +void DWC_VPRINTF(char *format, va_list args)
8910 +{
8911 +       vprintf(format, args);
8912 +}
8913 +
8914 +int DWC_VSNPRINTF(char *str, int size, char *format, va_list args)
8915 +{
8916 +       return vsnprintf(str, size, format, args);
8917 +}
8918 +
8919 +void DWC_PRINTF(char *format, ...)
8920 +{
8921 +       va_list args;
8922 +
8923 +       va_start(args, format);
8924 +       DWC_VPRINTF(format, args);
8925 +       va_end(args);
8926 +}
8927 +
8928 +int DWC_SPRINTF(char *buffer, char *format, ...)
8929 +{
8930 +       int retval;
8931 +       va_list args;
8932 +
8933 +       va_start(args, format);
8934 +       retval = vsprintf(buffer, format, args);
8935 +       va_end(args);
8936 +       return retval;
8937 +}
8938 +
8939 +int DWC_SNPRINTF(char *buffer, int size, char *format, ...)
8940 +{
8941 +       int retval;
8942 +       va_list args;
8943 +
8944 +       va_start(args, format);
8945 +       retval = vsnprintf(buffer, size, format, args);
8946 +       va_end(args);
8947 +       return retval;
8948 +}
8949 +
8950 +void __DWC_WARN(char *format, ...)
8951 +{
8952 +       va_list args;
8953 +
8954 +       va_start(args, format);
8955 +       DWC_VPRINTF(format, args);
8956 +       va_end(args);
8957 +}
8958 +
8959 +void __DWC_ERROR(char *format, ...)
8960 +{
8961 +       va_list args;
8962 +
8963 +       va_start(args, format);
8964 +       DWC_VPRINTF(format, args);
8965 +       va_end(args);
8966 +}
8967 +
8968 +void DWC_EXCEPTION(char *format, ...)
8969 +{
8970 +       va_list args;
8971 +
8972 +       va_start(args, format);
8973 +       DWC_VPRINTF(format, args);
8974 +       va_end(args);
8975 +//     BUG_ON(1);      ???
8976 +}
8977 +
8978 +#ifdef DEBUG
8979 +void __DWC_DEBUG(char *format, ...)
8980 +{
8981 +       va_list args;
8982 +
8983 +       va_start(args, format);
8984 +       DWC_VPRINTF(format, args);
8985 +       va_end(args);
8986 +}
8987 +#endif
8988 +
8989 +
8990 +/* dwc_mem.h */
8991 +
8992 +#if 0
8993 +dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size,
8994 +                               uint32_t align,
8995 +                               uint32_t alloc)
8996 +{
8997 +       struct dma_pool *pool = dma_pool_create("Pool", NULL,
8998 +                                               size, align, alloc);
8999 +       return (dwc_pool_t *)pool;
9000 +}
9001 +
9002 +void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool)
9003 +{
9004 +       dma_pool_destroy((struct dma_pool *)pool);
9005 +}
9006 +
9007 +void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
9008 +{
9009 +//     return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr);
9010 +       return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr);
9011 +}
9012 +
9013 +void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr)
9014 +{
9015 +       void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr);
9016 +       memset(..);
9017 +}
9018 +
9019 +void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr)
9020 +{
9021 +       dma_pool_free(pool, vaddr, daddr);
9022 +}
9023 +#endif
9024 +
9025 +void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr)
9026 +{
9027 +       dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
9028 +       int error;
9029 +
9030 +       error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs,
9031 +                                sizeof(dma->segs) / sizeof(dma->segs[0]),
9032 +                                &dma->nsegs, BUS_DMA_NOWAIT);
9033 +       if (error) {
9034 +               printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__,
9035 +                      (uintmax_t)size, error);
9036 +               goto fail_0;
9037 +       }
9038 +
9039 +       error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size,
9040 +                              (caddr_t *)&dma->dma_vaddr,
9041 +                              BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
9042 +       if (error) {
9043 +               printf("%s: bus_dmamem_map failed: %d\n", __func__, error);
9044 +               goto fail_1;
9045 +       }
9046 +
9047 +       error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0,
9048 +                                 BUS_DMA_NOWAIT, &dma->dma_map);
9049 +       if (error) {
9050 +               printf("%s: bus_dmamap_create failed: %d\n", __func__, error);
9051 +               goto fail_2;
9052 +       }
9053 +
9054 +       error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
9055 +                               size, NULL, BUS_DMA_NOWAIT);
9056 +       if (error) {
9057 +               printf("%s: bus_dmamap_load failed: %d\n", __func__, error);
9058 +               goto fail_3;
9059 +       }
9060 +
9061 +       dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr;
9062 +       *dma_addr = dma->dma_paddr;
9063 +       return dma->dma_vaddr;
9064 +
9065 +fail_3:
9066 +       bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
9067 +fail_2:
9068 +       bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
9069 +fail_1:
9070 +       bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
9071 +fail_0:
9072 +       dma->dma_map = NULL;
9073 +       dma->dma_vaddr = NULL;
9074 +       dma->nsegs = 0;
9075 +
9076 +       return NULL;
9077 +}
9078 +
9079 +void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
9080 +{
9081 +       dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx;
9082 +
9083 +       if (dma->dma_map != NULL) {
9084 +               bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size,
9085 +                               BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
9086 +               bus_dmamap_unload(dma->dma_tag, dma->dma_map);
9087 +               bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
9088 +               bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
9089 +               bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs);
9090 +               dma->dma_paddr = 0;
9091 +               dma->dma_map = NULL;
9092 +               dma->dma_vaddr = NULL;
9093 +               dma->nsegs = 0;
9094 +       }
9095 +}
9096 +
9097 +void *__DWC_ALLOC(void *mem_ctx, uint32_t size)
9098 +{
9099 +       return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
9100 +}
9101 +
9102 +void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size)
9103 +{
9104 +       return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO);
9105 +}
9106 +
9107 +void __DWC_FREE(void *mem_ctx, void *addr)
9108 +{
9109 +       free(addr, M_DEVBUF);
9110 +}
9111 +
9112 +
9113 +#ifdef DWC_CRYPTOLIB
9114 +/* dwc_crypto.h */
9115 +
9116 +void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length)
9117 +{
9118 +       get_random_bytes(buffer, length);
9119 +}
9120 +
9121 +int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
9122 +{
9123 +       struct crypto_blkcipher *tfm;
9124 +       struct blkcipher_desc desc;
9125 +       struct scatterlist sgd;
9126 +       struct scatterlist sgs;
9127 +
9128 +       tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC);
9129 +       if (tfm == NULL) {
9130 +               printk("failed to load transform for aes CBC\n");
9131 +               return -1;
9132 +       }
9133 +
9134 +       crypto_blkcipher_setkey(tfm, key, keylen);
9135 +       crypto_blkcipher_set_iv(tfm, iv, 16);
9136 +
9137 +       sg_init_one(&sgd, out, messagelen);
9138 +       sg_init_one(&sgs, message, messagelen);
9139 +
9140 +       desc.tfm = tfm;
9141 +       desc.flags = 0;
9142 +
9143 +       if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) {
9144 +               crypto_free_blkcipher(tfm);
9145 +               DWC_ERROR("AES CBC encryption failed");
9146 +               return -1;
9147 +       }
9148 +
9149 +       crypto_free_blkcipher(tfm);
9150 +       return 0;
9151 +}
9152 +
9153 +int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out)
9154 +{
9155 +       struct crypto_hash *tfm;
9156 +       struct hash_desc desc;
9157 +       struct scatterlist sg;
9158 +
9159 +       tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC);
9160 +       if (IS_ERR(tfm)) {
9161 +               DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm));
9162 +               return 0;
9163 +       }
9164 +       desc.tfm = tfm;
9165 +       desc.flags = 0;
9166 +
9167 +       sg_init_one(&sg, message, len);
9168 +       crypto_hash_digest(&desc, &sg, len, out);
9169 +       crypto_free_hash(tfm);
9170 +
9171 +       return 1;
9172 +}
9173 +
9174 +int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen,
9175 +                   uint8_t *key, uint32_t keylen, uint8_t *out)
9176 +{
9177 +       struct crypto_hash *tfm;
9178 +       struct hash_desc desc;
9179 +       struct scatterlist sg;
9180 +
9181 +       tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC);
9182 +       if (IS_ERR(tfm)) {
9183 +               DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm));
9184 +               return 0;
9185 +       }
9186 +       desc.tfm = tfm;
9187 +       desc.flags = 0;
9188 +
9189 +       sg_init_one(&sg, message, messagelen);
9190 +       crypto_hash_setkey(tfm, key, keylen);
9191 +       crypto_hash_digest(&desc, &sg, messagelen, out);
9192 +       crypto_free_hash(tfm);
9193 +
9194 +       return 1;
9195 +}
9196 +
9197 +#endif /* DWC_CRYPTOLIB */
9198 +
9199 +
9200 +/* Byte Ordering Conversions */
9201 +
9202 +uint32_t DWC_CPU_TO_LE32(uint32_t *p)
9203 +{
9204 +#ifdef __LITTLE_ENDIAN
9205 +       return *p;
9206 +#else
9207 +       uint8_t *u_p = (uint8_t *)p;
9208 +
9209 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9210 +#endif
9211 +}
9212 +
9213 +uint32_t DWC_CPU_TO_BE32(uint32_t *p)
9214 +{
9215 +#ifdef __BIG_ENDIAN
9216 +       return *p;
9217 +#else
9218 +       uint8_t *u_p = (uint8_t *)p;
9219 +
9220 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9221 +#endif
9222 +}
9223 +
9224 +uint32_t DWC_LE32_TO_CPU(uint32_t *p)
9225 +{
9226 +#ifdef __LITTLE_ENDIAN
9227 +       return *p;
9228 +#else
9229 +       uint8_t *u_p = (uint8_t *)p;
9230 +
9231 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9232 +#endif
9233 +}
9234 +
9235 +uint32_t DWC_BE32_TO_CPU(uint32_t *p)
9236 +{
9237 +#ifdef __BIG_ENDIAN
9238 +       return *p;
9239 +#else
9240 +       uint8_t *u_p = (uint8_t *)p;
9241 +
9242 +       return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24));
9243 +#endif
9244 +}
9245 +
9246 +uint16_t DWC_CPU_TO_LE16(uint16_t *p)
9247 +{
9248 +#ifdef __LITTLE_ENDIAN
9249 +       return *p;
9250 +#else
9251 +       uint8_t *u_p = (uint8_t *)p;
9252 +       return (u_p[1] | (u_p[0] << 8));
9253 +#endif
9254 +}
9255 +
9256 +uint16_t DWC_CPU_TO_BE16(uint16_t *p)
9257 +{
9258 +#ifdef __BIG_ENDIAN
9259 +       return *p;
9260 +#else
9261 +       uint8_t *u_p = (uint8_t *)p;
9262 +       return (u_p[1] | (u_p[0] << 8));
9263 +#endif
9264 +}
9265 +
9266 +uint16_t DWC_LE16_TO_CPU(uint16_t *p)
9267 +{
9268 +#ifdef __LITTLE_ENDIAN
9269 +       return *p;
9270 +#else
9271 +       uint8_t *u_p = (uint8_t *)p;
9272 +       return (u_p[1] | (u_p[0] << 8));
9273 +#endif
9274 +}
9275 +
9276 +uint16_t DWC_BE16_TO_CPU(uint16_t *p)
9277 +{
9278 +#ifdef __BIG_ENDIAN
9279 +       return *p;
9280 +#else
9281 +       uint8_t *u_p = (uint8_t *)p;
9282 +       return (u_p[1] | (u_p[0] << 8));
9283 +#endif
9284 +}
9285 +
9286 +
9287 +/* Registers */
9288 +
9289 +uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg)
9290 +{
9291 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9292 +       bus_size_t ior = (bus_size_t)reg;
9293 +
9294 +       return bus_space_read_4(io->iot, io->ioh, ior);
9295 +}
9296 +
9297 +#if 0
9298 +uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg)
9299 +{
9300 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9301 +       bus_size_t ior = (bus_size_t)reg;
9302 +
9303 +       return bus_space_read_8(io->iot, io->ioh, ior);
9304 +}
9305 +#endif
9306 +
9307 +void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value)
9308 +{
9309 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9310 +       bus_size_t ior = (bus_size_t)reg;
9311 +
9312 +       bus_space_write_4(io->iot, io->ioh, ior, value);
9313 +}
9314 +
9315 +#if 0
9316 +void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value)
9317 +{
9318 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9319 +       bus_size_t ior = (bus_size_t)reg;
9320 +
9321 +       bus_space_write_8(io->iot, io->ioh, ior, value);
9322 +}
9323 +#endif
9324 +
9325 +void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask,
9326 +                     uint32_t set_mask)
9327 +{
9328 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9329 +       bus_size_t ior = (bus_size_t)reg;
9330 +
9331 +       bus_space_write_4(io->iot, io->ioh, ior,
9332 +                         (bus_space_read_4(io->iot, io->ioh, ior) &
9333 +                          ~clear_mask) | set_mask);
9334 +}
9335 +
9336 +#if 0
9337 +void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask,
9338 +                     uint64_t set_mask)
9339 +{
9340 +       dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx;
9341 +       bus_size_t ior = (bus_size_t)reg;
9342 +
9343 +       bus_space_write_8(io->iot, io->ioh, ior,
9344 +                         (bus_space_read_8(io->iot, io->ioh, ior) &
9345 +                          ~clear_mask) | set_mask);
9346 +}
9347 +#endif
9348 +
9349 +
9350 +/* Locking */
9351 +
9352 +dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void)
9353 +{
9354 +       struct simplelock *sl = DWC_ALLOC(sizeof(*sl));
9355 +
9356 +       if (!sl) {
9357 +               DWC_ERROR("Cannot allocate memory for spinlock");
9358 +               return NULL;
9359 +       }
9360 +
9361 +       simple_lock_init(sl);
9362 +       return (dwc_spinlock_t *)sl;
9363 +}
9364 +
9365 +void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock)
9366 +{
9367 +       struct simplelock *sl = (struct simplelock *)lock;
9368 +
9369 +       DWC_FREE(sl);
9370 +}
9371 +
9372 +void DWC_SPINLOCK(dwc_spinlock_t *lock)
9373 +{
9374 +       simple_lock((struct simplelock *)lock);
9375 +}
9376 +
9377 +void DWC_SPINUNLOCK(dwc_spinlock_t *lock)
9378 +{
9379 +       simple_unlock((struct simplelock *)lock);
9380 +}
9381 +
9382 +void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags)
9383 +{
9384 +       simple_lock((struct simplelock *)lock);
9385 +       *flags = splbio();
9386 +}
9387 +
9388 +void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags)
9389 +{
9390 +       splx(flags);
9391 +       simple_unlock((struct simplelock *)lock);
9392 +}
9393 +
9394 +dwc_mutex_t *DWC_MUTEX_ALLOC(void)
9395 +{
9396 +       dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock));
9397 +
9398 +       if (!mutex) {
9399 +               DWC_ERROR("Cannot allocate memory for mutex");
9400 +               return NULL;
9401 +       }
9402 +
9403 +       lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0);
9404 +       return mutex;
9405 +}
9406 +
9407 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES))
9408 +#else
9409 +void DWC_MUTEX_FREE(dwc_mutex_t *mutex)
9410 +{
9411 +       DWC_FREE(mutex);
9412 +}
9413 +#endif
9414 +
9415 +void DWC_MUTEX_LOCK(dwc_mutex_t *mutex)
9416 +{
9417 +       lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL);
9418 +}
9419 +
9420 +int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex)
9421 +{
9422 +       int status;
9423 +
9424 +       status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL);
9425 +       return status == 0;
9426 +}
9427 +
9428 +void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex)
9429 +{
9430 +       lockmgr((struct lock *)mutex, LK_RELEASE, NULL);
9431 +}
9432 +
9433 +
9434 +/* Timing */
9435 +
9436 +void DWC_UDELAY(uint32_t usecs)
9437 +{
9438 +       DELAY(usecs);
9439 +}
9440 +
9441 +void DWC_MDELAY(uint32_t msecs)
9442 +{
9443 +       do {
9444 +               DELAY(1000);
9445 +       } while (--msecs);
9446 +}
9447 +
9448 +void DWC_MSLEEP(uint32_t msecs)
9449 +{
9450 +       struct timeval tv;
9451 +
9452 +       tv.tv_sec = msecs / 1000;
9453 +       tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
9454 +       tsleep(&tv, 0, "dw3slp", tvtohz(&tv));
9455 +}
9456 +
9457 +uint32_t DWC_TIME(void)
9458 +{
9459 +       struct timeval tv;
9460 +
9461 +       microuptime(&tv);       // or getmicrouptime? (less precise, but faster)
9462 +       return tv.tv_sec * 1000 + tv.tv_usec / 1000;
9463 +}
9464 +
9465 +
9466 +/* Timers */
9467 +
9468 +struct dwc_timer {
9469 +       struct callout t;
9470 +       char *name;
9471 +       dwc_spinlock_t *lock;
9472 +       dwc_timer_callback_t cb;
9473 +       void *data;
9474 +};
9475 +
9476 +dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data)
9477 +{
9478 +       dwc_timer_t *t = DWC_ALLOC(sizeof(*t));
9479 +
9480 +       if (!t) {
9481 +               DWC_ERROR("Cannot allocate memory for timer");
9482 +               return NULL;
9483 +       }
9484 +
9485 +       callout_init(&t->t);
9486 +
9487 +       t->name = DWC_STRDUP(name);
9488 +       if (!t->name) {
9489 +               DWC_ERROR("Cannot allocate memory for timer->name");
9490 +               goto no_name;
9491 +       }
9492 +
9493 +       t->lock = DWC_SPINLOCK_ALLOC();
9494 +       if (!t->lock) {
9495 +               DWC_ERROR("Cannot allocate memory for timer->lock");
9496 +               goto no_lock;
9497 +       }
9498 +
9499 +       t->cb = cb;
9500 +       t->data = data;
9501 +
9502 +       return t;
9503 +
9504 + no_lock:
9505 +       DWC_FREE(t->name);
9506 + no_name:
9507 +       DWC_FREE(t);
9508 +
9509 +       return NULL;
9510 +}
9511 +
9512 +void DWC_TIMER_FREE(dwc_timer_t *timer)
9513 +{
9514 +       callout_stop(&timer->t);
9515 +       DWC_SPINLOCK_FREE(timer->lock);
9516 +       DWC_FREE(timer->name);
9517 +       DWC_FREE(timer);
9518 +}
9519 +
9520 +void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time)
9521 +{
9522 +       struct timeval tv;
9523 +
9524 +       tv.tv_sec = time / 1000;
9525 +       tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
9526 +       callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data);
9527 +}
9528 +
9529 +void DWC_TIMER_CANCEL(dwc_timer_t *timer)
9530 +{
9531 +       callout_stop(&timer->t);
9532 +}
9533 +
9534 +
9535 +/* Wait Queues */
9536 +
9537 +struct dwc_waitq {
9538 +       struct simplelock lock;
9539 +       int abort;
9540 +};
9541 +
9542 +dwc_waitq_t *DWC_WAITQ_ALLOC(void)
9543 +{
9544 +       dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq));
9545 +
9546 +       if (!wq) {
9547 +               DWC_ERROR("Cannot allocate memory for waitqueue");
9548 +               return NULL;
9549 +       }
9550 +
9551 +       simple_lock_init(&wq->lock);
9552 +       wq->abort = 0;
9553 +
9554 +       return wq;
9555 +}
9556 +
9557 +void DWC_WAITQ_FREE(dwc_waitq_t *wq)
9558 +{
9559 +       DWC_FREE(wq);
9560 +}
9561 +
9562 +int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data)
9563 +{
9564 +       int ipl;
9565 +       int result = 0;
9566 +
9567 +       simple_lock(&wq->lock);
9568 +       ipl = splbio();
9569 +
9570 +       /* Skip the sleep if already aborted or triggered */
9571 +       if (!wq->abort && !cond(data)) {
9572 +               splx(ipl);
9573 +               result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout
9574 +               ipl = splbio();
9575 +       }
9576 +
9577 +       if (result == 0) {                      // awoken
9578 +               if (wq->abort) {
9579 +                       wq->abort = 0;
9580 +                       result = -DWC_E_ABORT;
9581 +               } else {
9582 +                       result = 0;
9583 +               }
9584 +
9585 +               splx(ipl);
9586 +               simple_unlock(&wq->lock);
9587 +       } else {
9588 +               wq->abort = 0;
9589 +               splx(ipl);
9590 +               simple_unlock(&wq->lock);
9591 +
9592 +               if (result == ERESTART) {       // signaled - restart
9593 +                       result = -DWC_E_RESTART;
9594 +               } else {                        // signaled - must be EINTR
9595 +                       result = -DWC_E_ABORT;
9596 +               }
9597 +       }
9598 +
9599 +       return result;
9600 +}
9601 +
9602 +int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
9603 +                              void *data, int32_t msecs)
9604 +{
9605 +       struct timeval tv, tv1, tv2;
9606 +       int ipl;
9607 +       int result = 0;
9608 +
9609 +       tv.tv_sec = msecs / 1000;
9610 +       tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000;
9611 +
9612 +       simple_lock(&wq->lock);
9613 +       ipl = splbio();
9614 +
9615 +       /* Skip the sleep if already aborted or triggered */
9616 +       if (!wq->abort && !cond(data)) {
9617 +               splx(ipl);
9618 +               getmicrouptime(&tv1);
9619 +               result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock);
9620 +               getmicrouptime(&tv2);
9621 +               ipl = splbio();
9622 +       }
9623 +
9624 +       if (result == 0) {                      // awoken
9625 +               if (wq->abort) {
9626 +                       wq->abort = 0;
9627 +                       splx(ipl);
9628 +                       simple_unlock(&wq->lock);
9629 +                       result = -DWC_E_ABORT;
9630 +               } else {
9631 +                       splx(ipl);
9632 +                       simple_unlock(&wq->lock);
9633 +
9634 +                       tv2.tv_usec -= tv1.tv_usec;
9635 +                       if (tv2.tv_usec < 0) {
9636 +                               tv2.tv_usec += 1000000;
9637 +                               tv2.tv_sec--;
9638 +                       }
9639 +
9640 +                       tv2.tv_sec -= tv1.tv_sec;
9641 +                       result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000;
9642 +                       result = msecs - result;
9643 +                       if (result <= 0)
9644 +                               result = 1;
9645 +               }
9646 +       } else {
9647 +               wq->abort = 0;
9648 +               splx(ipl);
9649 +               simple_unlock(&wq->lock);
9650 +
9651 +               if (result == ERESTART) {       // signaled - restart
9652 +                       result = -DWC_E_RESTART;
9653 +
9654 +               } else if (result == EINTR) {           // signaled - interrupt
9655 +                       result = -DWC_E_ABORT;
9656 +
9657 +               } else {                                // timed out
9658 +                       result = -DWC_E_TIMEOUT;
9659 +               }
9660 +       }
9661 +
9662 +       return result;
9663 +}
9664 +
9665 +void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq)
9666 +{
9667 +       wakeup(wq);
9668 +}
9669 +
9670 +void DWC_WAITQ_ABORT(dwc_waitq_t *wq)
9671 +{
9672 +       int ipl;
9673 +
9674 +       simple_lock(&wq->lock);
9675 +       ipl = splbio();
9676 +       wq->abort = 1;
9677 +       wakeup(wq);
9678 +       splx(ipl);
9679 +       simple_unlock(&wq->lock);
9680 +}
9681 +
9682 +
9683 +/* Threading */
9684 +
9685 +struct dwc_thread {
9686 +       struct proc *proc;
9687 +       int abort;
9688 +};
9689 +
9690 +dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data)
9691 +{
9692 +       int retval;
9693 +       dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread));
9694 +
9695 +       if (!thread) {
9696 +               return NULL;
9697 +       }
9698 +
9699 +       thread->abort = 0;
9700 +       retval = kthread_create1((void (*)(void *))func, data, &thread->proc,
9701 +                                "%s", name);
9702 +       if (retval) {
9703 +               DWC_FREE(thread);
9704 +               return NULL;
9705 +       }
9706 +
9707 +       return thread;
9708 +}
9709 +
9710 +int DWC_THREAD_STOP(dwc_thread_t *thread)
9711 +{
9712 +       int retval;
9713 +
9714 +       thread->abort = 1;
9715 +       retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz);
9716 +
9717 +       if (retval == 0) {
9718 +               /* DWC_THREAD_EXIT() will free the thread struct */
9719 +               return 0;
9720 +       }
9721 +
9722 +       /* NOTE: We leak the thread struct if thread doesn't die */
9723 +
9724 +       if (retval == EWOULDBLOCK) {
9725 +               return -DWC_E_TIMEOUT;
9726 +       }
9727 +
9728 +       return -DWC_E_UNKNOWN;
9729 +}
9730 +
9731 +dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread)
9732 +{
9733 +       return thread->abort;
9734 +}
9735 +
9736 +void DWC_THREAD_EXIT(dwc_thread_t *thread)
9737 +{
9738 +       wakeup(&thread->abort);
9739 +       DWC_FREE(thread);
9740 +       kthread_exit(0);
9741 +}
9742 +
9743 +/* tasklets
9744 + - Runs in interrupt context (cannot sleep)
9745 + - Each tasklet runs on a single CPU
9746 + - Different tasklets can be running simultaneously on different CPUs
9747 + [ On NetBSD there is no corresponding mechanism, drivers don't have bottom-
9748 +   halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ]
9749 + */
9750 +struct dwc_tasklet {
9751 +       dwc_tasklet_callback_t cb;
9752 +       void *data;
9753 +};
9754 +
9755 +static void tasklet_callback(void *data)
9756 +{
9757 +       dwc_tasklet_t *task = (dwc_tasklet_t *)data;
9758 +
9759 +       task->cb(task->data);
9760 +}
9761 +
9762 +dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data)
9763 +{
9764 +       dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task));
9765 +
9766 +       if (task) {
9767 +               task->cb = cb;
9768 +               task->data = data;
9769 +       } else {
9770 +               DWC_ERROR("Cannot allocate memory for tasklet");
9771 +       }
9772 +
9773 +       return task;
9774 +}
9775 +
9776 +void DWC_TASK_FREE(dwc_tasklet_t *task)
9777 +{
9778 +       DWC_FREE(task);
9779 +}
9780 +
9781 +void DWC_TASK_SCHEDULE(dwc_tasklet_t *task)
9782 +{
9783 +       tasklet_callback(task);
9784 +}
9785 +
9786 +
9787 +/* workqueues
9788 + - Runs in process context (can sleep)
9789 + */
9790 +typedef struct work_container {
9791 +       dwc_work_callback_t cb;
9792 +       void *data;
9793 +       dwc_workq_t *wq;
9794 +       char *name;
9795 +       int hz;
9796 +       struct work task;
9797 +} work_container_t;
9798 +
9799 +struct dwc_workq {
9800 +       struct workqueue *taskq;
9801 +       dwc_spinlock_t *lock;
9802 +       dwc_waitq_t *waitq;
9803 +       int pending;
9804 +       struct work_container *container;
9805 +};
9806 +
9807 +static void do_work(struct work *task, void *data)
9808 +{
9809 +       dwc_workq_t *wq = (dwc_workq_t *)data;
9810 +       work_container_t *container = wq->container;
9811 +       dwc_irqflags_t flags;
9812 +
9813 +       if (container->hz) {
9814 +               tsleep(container, 0, "dw3wrk", container->hz);
9815 +       }
9816 +
9817 +       container->cb(container->data);
9818 +       DWC_DEBUG("Work done: %s, container=%p", container->name, container);
9819 +
9820 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
9821 +       if (container->name)
9822 +               DWC_FREE(container->name);
9823 +       DWC_FREE(container);
9824 +       wq->pending--;
9825 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
9826 +       DWC_WAITQ_TRIGGER(wq->waitq);
9827 +}
9828 +
9829 +static int work_done(void *data)
9830 +{
9831 +       dwc_workq_t *workq = (dwc_workq_t *)data;
9832 +
9833 +       return workq->pending == 0;
9834 +}
9835 +
9836 +int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout)
9837 +{
9838 +       return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout);
9839 +}
9840 +
9841 +dwc_workq_t *DWC_WORKQ_ALLOC(char *name)
9842 +{
9843 +       int result;
9844 +       dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq));
9845 +
9846 +       if (!wq) {
9847 +               DWC_ERROR("Cannot allocate memory for workqueue");
9848 +               return NULL;
9849 +       }
9850 +
9851 +       result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/,
9852 +                                 IPL_BIO, 0);
9853 +       if (result) {
9854 +               DWC_ERROR("Cannot create workqueue");
9855 +               goto no_taskq;
9856 +       }
9857 +
9858 +       wq->pending = 0;
9859 +
9860 +       wq->lock = DWC_SPINLOCK_ALLOC();
9861 +       if (!wq->lock) {
9862 +               DWC_ERROR("Cannot allocate memory for spinlock");
9863 +               goto no_lock;
9864 +       }
9865 +
9866 +       wq->waitq = DWC_WAITQ_ALLOC();
9867 +       if (!wq->waitq) {
9868 +               DWC_ERROR("Cannot allocate memory for waitqueue");
9869 +               goto no_waitq;
9870 +       }
9871 +
9872 +       return wq;
9873 +
9874 + no_waitq:
9875 +       DWC_SPINLOCK_FREE(wq->lock);
9876 + no_lock:
9877 +       workqueue_destroy(wq->taskq);
9878 + no_taskq:
9879 +       DWC_FREE(wq);
9880 +
9881 +       return NULL;
9882 +}
9883 +
9884 +void DWC_WORKQ_FREE(dwc_workq_t *wq)
9885 +{
9886 +#ifdef DEBUG
9887 +       dwc_irqflags_t flags;
9888 +
9889 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
9890 +
9891 +       if (wq->pending != 0) {
9892 +               struct work_container *container = wq->container;
9893 +
9894 +               DWC_ERROR("Destroying work queue with pending work");
9895 +
9896 +               if (container && container->name) {
9897 +                       DWC_ERROR("Work %s still pending", container->name);
9898 +               }
9899 +       }
9900 +
9901 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
9902 +#endif
9903 +       DWC_WAITQ_FREE(wq->waitq);
9904 +       DWC_SPINLOCK_FREE(wq->lock);
9905 +       workqueue_destroy(wq->taskq);
9906 +       DWC_FREE(wq);
9907 +}
9908 +
9909 +void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data,
9910 +                       char *format, ...)
9911 +{
9912 +       dwc_irqflags_t flags;
9913 +       work_container_t *container;
9914 +       static char name[128];
9915 +       va_list args;
9916 +
9917 +       va_start(args, format);
9918 +       DWC_VSNPRINTF(name, 128, format, args);
9919 +       va_end(args);
9920 +
9921 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
9922 +       wq->pending++;
9923 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
9924 +       DWC_WAITQ_TRIGGER(wq->waitq);
9925 +
9926 +       container = DWC_ALLOC_ATOMIC(sizeof(*container));
9927 +       if (!container) {
9928 +               DWC_ERROR("Cannot allocate memory for container");
9929 +               return;
9930 +       }
9931 +
9932 +       container->name = DWC_STRDUP(name);
9933 +       if (!container->name) {
9934 +               DWC_ERROR("Cannot allocate memory for container->name");
9935 +               DWC_FREE(container);
9936 +               return;
9937 +       }
9938 +
9939 +       container->cb = cb;
9940 +       container->data = data;
9941 +       container->wq = wq;
9942 +       container->hz = 0;
9943 +       wq->container = container;
9944 +
9945 +       DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
9946 +       workqueue_enqueue(wq->taskq, &container->task);
9947 +}
9948 +
9949 +void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb,
9950 +                               void *data, uint32_t time, char *format, ...)
9951 +{
9952 +       dwc_irqflags_t flags;
9953 +       work_container_t *container;
9954 +       static char name[128];
9955 +       struct timeval tv;
9956 +       va_list args;
9957 +
9958 +       va_start(args, format);
9959 +       DWC_VSNPRINTF(name, 128, format, args);
9960 +       va_end(args);
9961 +
9962 +       DWC_SPINLOCK_IRQSAVE(wq->lock, &flags);
9963 +       wq->pending++;
9964 +       DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags);
9965 +       DWC_WAITQ_TRIGGER(wq->waitq);
9966 +
9967 +       container = DWC_ALLOC_ATOMIC(sizeof(*container));
9968 +       if (!container) {
9969 +               DWC_ERROR("Cannot allocate memory for container");
9970 +               return;
9971 +       }
9972 +
9973 +       container->name = DWC_STRDUP(name);
9974 +       if (!container->name) {
9975 +               DWC_ERROR("Cannot allocate memory for container->name");
9976 +               DWC_FREE(container);
9977 +               return;
9978 +       }
9979 +
9980 +       container->cb = cb;
9981 +       container->data = data;
9982 +       container->wq = wq;
9983 +       tv.tv_sec = time / 1000;
9984 +       tv.tv_usec = (time - tv.tv_sec * 1000) * 1000;
9985 +       container->hz = tvtohz(&tv);
9986 +       wq->container = container;
9987 +
9988 +       DWC_DEBUG("Queueing work: %s, container=%p", container->name, container);
9989 +       workqueue_enqueue(wq->taskq, &container->task);
9990 +}
9991 +
9992 +int DWC_WORKQ_PENDING(dwc_workq_t *wq)
9993 +{
9994 +       return wq->pending;
9995 +}
9996 --- /dev/null
9997 +++ b/drivers/usb/host/dwc_common_port/dwc_crypto.c
9998 @@ -0,0 +1,308 @@
9999 +/* =========================================================================
10000 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $
10001 + * $Revision: #5 $
10002 + * $Date: 2010/09/28 $
10003 + * $Change: 1596182 $
10004 + *
10005 + * Synopsys Portability Library Software and documentation
10006 + * (hereinafter, "Software") is an Unsupported proprietary work of
10007 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10008 + * between Synopsys and you.
10009 + *
10010 + * The Software IS NOT an item of Licensed Software or Licensed Product
10011 + * under any End User Software License Agreement or Agreement for
10012 + * Licensed Product with Synopsys or any supplement thereto. You are
10013 + * permitted to use and redistribute this Software in source and binary
10014 + * forms, with or without modification, provided that redistributions
10015 + * of source code must retain this notice. You may not view, use,
10016 + * disclose, copy or distribute this file or any information contained
10017 + * herein except pursuant to this license grant from Synopsys. If you
10018 + * do not agree with this notice, including the disclaimer below, then
10019 + * you are not authorized to use the Software.
10020 + *
10021 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10022 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10023 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10024 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10025 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10026 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10027 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10028 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10029 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10030 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10031 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10032 + * DAMAGE.
10033 + * ========================================================================= */
10034 +
10035 +/** @file
10036 + * This file contains the WUSB cryptographic routines.
10037 + */
10038 +
10039 +#ifdef DWC_CRYPTOLIB
10040 +
10041 +#include "dwc_crypto.h"
10042 +#include "usb.h"
10043 +
10044 +#ifdef DEBUG
10045 +static inline void dump_bytes(char *name, uint8_t *bytes, int len)
10046 +{
10047 +       int i;
10048 +       DWC_PRINTF("%s: ", name);
10049 +       for (i=0; i<len; i++) {
10050 +               DWC_PRINTF("%02x ", bytes[i]);
10051 +       }
10052 +       DWC_PRINTF("\n");
10053 +}
10054 +#else
10055 +#define dump_bytes(x...)
10056 +#endif
10057 +
10058 +/* Display a block */
10059 +void show_block(const u8 *blk, const char *prefix, const char *suffix, int a)
10060 +{
10061 +#ifdef DWC_DEBUG_CRYPTO
10062 +       int i, blksize = 16;
10063 +
10064 +       DWC_DEBUG("%s", prefix);
10065 +
10066 +       if (suffix == NULL) {
10067 +               suffix = "\n";
10068 +               blksize = a;
10069 +       }
10070 +
10071 +       for (i = 0; i < blksize; i++)
10072 +               DWC_PRINT("%02x%s", *blk++, ((i & 3) == 3) ? "  " : " ");
10073 +       DWC_PRINT(suffix);
10074 +#endif
10075 +}
10076 +
10077 +/**
10078 + * Encrypts an array of bytes using the AES encryption engine.
10079 + * If <code>dst</code> == <code>src</code>, then the bytes will be encrypted
10080 + * in-place.
10081 + *
10082 + * @return  0 on success, negative error code on error.
10083 + */
10084 +int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst)
10085 +{
10086 +       u8 block_t[16];
10087 +       DWC_MEMSET(block_t, 0, 16);
10088 +
10089 +       return DWC_AES_CBC(src, 16, key, 16, block_t, dst);
10090 +}
10091 +
10092 +/**
10093 + * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
10094 + * This function takes a data string and returns the encrypted CBC
10095 + * Counter-mode MIC.
10096 + *
10097 + * @param key     The 128-bit symmetric key.
10098 + * @param nonce   The CCM nonce.
10099 + * @param label   The unique 14-byte ASCII text label.
10100 + * @param bytes   The byte array to be encrypted.
10101 + * @param len     Length of the byte array.
10102 + * @param result  Byte array to receive the 8-byte encrypted MIC.
10103 + */
10104 +void dwc_wusb_cmf(u8 *key, u8 *nonce,
10105 +                 char *label, u8 *bytes, int len, u8 *result)
10106 +{
10107 +       u8 block_m[16];
10108 +       u8 block_x[16];
10109 +       u8 block_t[8];
10110 +       int idx, blkNum;
10111 +       u16 la = (u16)(len + 14);
10112 +
10113 +       /* Set the AES-128 key */
10114 +       //dwc_aes_setkey(tfm, key, 16);
10115 +
10116 +       /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */
10117 +       block_m[0] = 0x59;
10118 +       for (idx = 0; idx < 13; idx++)
10119 +               block_m[idx + 1] = nonce[idx];
10120 +       block_m[14] = 0;
10121 +       block_m[15] = 0;
10122 +
10123 +       /* Produce the CBC IV */
10124 +       dwc_wusb_aes_encrypt(block_m, key, block_x);
10125 +       show_block(block_m, "CBC IV in: ", "\n", 0);
10126 +       show_block(block_x, "CBC IV out:", "\n", 0);
10127 +
10128 +       /* Fill block B1 from l(a) = Blen + 14, and A */
10129 +       block_x[0] ^= (u8)(la >> 8);
10130 +       block_x[1] ^= (u8)la;
10131 +       for (idx = 0; idx < 14; idx++)
10132 +               block_x[idx + 2] ^= label[idx];
10133 +       show_block(block_x, "After xor: ", "b1\n", 16);
10134 +
10135 +       dwc_wusb_aes_encrypt(block_x, key, block_x);
10136 +       show_block(block_x, "After AES: ", "b1\n", 16);
10137 +
10138 +       idx = 0;
10139 +       blkNum = 0;
10140 +
10141 +       /* Fill remaining blocks with B */
10142 +       while (len-- > 0) {
10143 +               block_x[idx] ^= *bytes++;
10144 +               if (++idx >= 16) {
10145 +                       idx = 0;
10146 +                       show_block(block_x, "After xor: ", "\n", blkNum);
10147 +                       dwc_wusb_aes_encrypt(block_x, key, block_x);
10148 +                       show_block(block_x, "After AES: ", "\n", blkNum);
10149 +                       blkNum++;
10150 +               }
10151 +       }
10152 +
10153 +       /* Handle partial last block */
10154 +       if (idx > 0) {
10155 +               show_block(block_x, "After xor: ", "\n", blkNum);
10156 +               dwc_wusb_aes_encrypt(block_x, key, block_x);
10157 +               show_block(block_x, "After AES: ", "\n", blkNum);
10158 +       }
10159 +
10160 +       /* Save the MIC tag */
10161 +       DWC_MEMCPY(block_t, block_x, 8);
10162 +       show_block(block_t, "MIC tag  : ", NULL, 8);
10163 +
10164 +       /* Fill block A0 from flags = 0x01, N, and counter = 0 */
10165 +       block_m[0] = 0x01;
10166 +       block_m[14] = 0;
10167 +       block_m[15] = 0;
10168 +
10169 +       /* Encrypt the counter */
10170 +       dwc_wusb_aes_encrypt(block_m, key, block_x);
10171 +       show_block(block_x, "CTR[MIC] : ", NULL, 8);
10172 +
10173 +       /* XOR with MIC tag */
10174 +       for (idx = 0; idx < 8; idx++) {
10175 +               block_t[idx] ^= block_x[idx];
10176 +       }
10177 +
10178 +       /* Return result to caller */
10179 +       DWC_MEMCPY(result, block_t, 8);
10180 +       show_block(result, "CCM-MIC  : ", NULL, 8);
10181 +
10182 +}
10183 +
10184 +/**
10185 + * The PRF function described in section 6.5 of the WUSB spec. This function
10186 + * concatenates MIC values returned from dwc_cmf() to create a value of
10187 + * the requested length.
10188 + *
10189 + * @param prf_len  Length of the PRF function in bits (64, 128, or 256).
10190 + * @param key, nonce, label, bytes, len  Same as for dwc_cmf().
10191 + * @param result   Byte array to receive the result.
10192 + */
10193 +void dwc_wusb_prf(int prf_len, u8 *key,
10194 +                 u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
10195 +{
10196 +       int i;
10197 +
10198 +       nonce[0] = 0;
10199 +       for (i = 0; i < prf_len >> 6; i++, nonce[0]++) {
10200 +               dwc_wusb_cmf(key, nonce, label, bytes, len, result);
10201 +               result += 8;
10202 +       }
10203 +}
10204 +
10205 +/**
10206 + * Fills in CCM Nonce per the WUSB spec.
10207 + *
10208 + * @param[in] haddr Host address.
10209 + * @param[in] daddr Device address.
10210 + * @param[in] tkid Session Key(PTK) identifier.
10211 + * @param[out] nonce Pointer to where the CCM Nonce output is to be written.
10212 + */
10213 +void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
10214 +                            uint8_t *nonce)
10215 +{
10216 +
10217 +       DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr);
10218 +
10219 +       DWC_MEMSET(&nonce[0], 0, 16);
10220 +
10221 +       DWC_MEMCPY(&nonce[6], tkid, 3);
10222 +       nonce[9] = daddr & 0xFF;
10223 +       nonce[10] = (daddr >> 8) & 0xFF;
10224 +       nonce[11] = haddr & 0xFF;
10225 +       nonce[12] = (haddr >> 8) & 0xFF;
10226 +
10227 +       dump_bytes("CCM nonce", nonce, 16);
10228 +}
10229 +
10230 +/**
10231 + * Generates a 16-byte cryptographic-grade random number for the Host/Device
10232 + * Nonce.
10233 + */
10234 +void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce)
10235 +{
10236 +       uint8_t inonce[16];
10237 +       uint32_t temp[4];
10238 +
10239 +       /* Fill in the Nonce */
10240 +       DWC_MEMSET(&inonce[0], 0, sizeof(inonce));
10241 +       inonce[9] = addr & 0xFF;
10242 +       inonce[10] = (addr >> 8) & 0xFF;
10243 +       inonce[11] = inonce[9];
10244 +       inonce[12] = inonce[10];
10245 +
10246 +       /* Collect "randomness samples" */
10247 +       DWC_RANDOM_BYTES((uint8_t *)temp, 16);
10248 +
10249 +       dwc_wusb_prf_128((uint8_t *)temp, nonce,
10250 +                        "Random Numbers", (uint8_t *)temp, sizeof(temp),
10251 +                        nonce);
10252 +}
10253 +
10254 +/**
10255 + * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the
10256 + * WUSB spec.
10257 + *
10258 + * @param[in] ccm_nonce Pointer to CCM Nonce.
10259 + * @param[in] mk Master Key to derive the session from
10260 + * @param[in] hnonce Pointer to Host Nonce.
10261 + * @param[in] dnonce Pointer to Device Nonce.
10262 + * @param[out] kck Pointer to where the KCK output is to be written.
10263 + * @param[out] ptk Pointer to where the PTK output is to be written.
10264 + */
10265 +void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce,
10266 +                     uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
10267 +{
10268 +       uint8_t idata[32];
10269 +       uint8_t odata[32];
10270 +
10271 +       dump_bytes("ck", mk, 16);
10272 +       dump_bytes("hnonce", hnonce, 16);
10273 +       dump_bytes("dnonce", dnonce, 16);
10274 +
10275 +       /* The data is the HNonce and DNonce concatenated */
10276 +       DWC_MEMCPY(&idata[0], hnonce, 16);
10277 +       DWC_MEMCPY(&idata[16], dnonce, 16);
10278 +
10279 +       dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata);
10280 +
10281 +       /* Low 16 bytes of the result is the KCK, high 16 is the PTK */
10282 +       DWC_MEMCPY(kck, &odata[0], 16);
10283 +       DWC_MEMCPY(ptk, &odata[16], 16);
10284 +
10285 +       dump_bytes("kck", kck, 16);
10286 +       dump_bytes("ptk", ptk, 16);
10287 +}
10288 +
10289 +/**
10290 + * Generates the Message Integrity Code over the Handshake data per the
10291 + * WUSB spec.
10292 + *
10293 + * @param ccm_nonce Pointer to CCM Nonce.
10294 + * @param kck   Pointer to Key Confirmation Key.
10295 + * @param data  Pointer to Handshake data to be checked.
10296 + * @param mic   Pointer to where the MIC output is to be written.
10297 + */
10298 +void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck,
10299 +                     uint8_t *data, uint8_t *mic)
10300 +{
10301 +
10302 +       dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC",
10303 +                       data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic);
10304 +}
10305 +
10306 +#endif /* DWC_CRYPTOLIB */
10307 --- /dev/null
10308 +++ b/drivers/usb/host/dwc_common_port/dwc_crypto.h
10309 @@ -0,0 +1,111 @@
10310 +/* =========================================================================
10311 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $
10312 + * $Revision: #3 $
10313 + * $Date: 2010/09/28 $
10314 + * $Change: 1596182 $
10315 + *
10316 + * Synopsys Portability Library Software and documentation
10317 + * (hereinafter, "Software") is an Unsupported proprietary work of
10318 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10319 + * between Synopsys and you.
10320 + *
10321 + * The Software IS NOT an item of Licensed Software or Licensed Product
10322 + * under any End User Software License Agreement or Agreement for
10323 + * Licensed Product with Synopsys or any supplement thereto. You are
10324 + * permitted to use and redistribute this Software in source and binary
10325 + * forms, with or without modification, provided that redistributions
10326 + * of source code must retain this notice. You may not view, use,
10327 + * disclose, copy or distribute this file or any information contained
10328 + * herein except pursuant to this license grant from Synopsys. If you
10329 + * do not agree with this notice, including the disclaimer below, then
10330 + * you are not authorized to use the Software.
10331 + *
10332 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10333 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10334 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10335 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10336 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10337 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10338 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10339 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10340 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10341 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10342 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10343 + * DAMAGE.
10344 + * ========================================================================= */
10345 +
10346 +#ifndef _DWC_CRYPTO_H_
10347 +#define _DWC_CRYPTO_H_
10348 +
10349 +#ifdef __cplusplus
10350 +extern "C" {
10351 +#endif
10352 +
10353 +/** @file
10354 + *
10355 + * This file contains declarations for the WUSB Cryptographic routines as
10356 + * defined in the WUSB spec.  They are only to be used internally by the DWC UWB
10357 + * modules.
10358 + */
10359 +
10360 +#include "dwc_os.h"
10361 +
10362 +int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst);
10363 +
10364 +void dwc_wusb_cmf(u8 *key, u8 *nonce,
10365 +                 char *label, u8 *bytes, int len, u8 *result);
10366 +void dwc_wusb_prf(int prf_len, u8 *key,
10367 +                 u8 *nonce, char *label, u8 *bytes, int len, u8 *result);
10368 +
10369 +/**
10370 + * The PRF-64 function described in section 6.5 of the WUSB spec.
10371 + *
10372 + * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
10373 + */
10374 +static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce,
10375 +                                  char *label, u8 *bytes, int len, u8 *result)
10376 +{
10377 +       dwc_wusb_prf(64, key, nonce, label, bytes, len, result);
10378 +}
10379 +
10380 +/**
10381 + * The PRF-128 function described in section 6.5 of the WUSB spec.
10382 + *
10383 + * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
10384 + */
10385 +static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce,
10386 +                                   char *label, u8 *bytes, int len, u8 *result)
10387 +{
10388 +       dwc_wusb_prf(128, key, nonce, label, bytes, len, result);
10389 +}
10390 +
10391 +/**
10392 + * The PRF-256 function described in section 6.5 of the WUSB spec.
10393 + *
10394 + * @param key, nonce, label, bytes, len, result  Same as for dwc_prf().
10395 + */
10396 +static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce,
10397 +                                   char *label, u8 *bytes, int len, u8 *result)
10398 +{
10399 +       dwc_wusb_prf(256, key, nonce, label, bytes, len, result);
10400 +}
10401 +
10402 +
10403 +void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid,
10404 +                              uint8_t *nonce);
10405 +void dwc_wusb_gen_nonce(uint16_t addr,
10406 +                         uint8_t *nonce);
10407 +
10408 +void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk,
10409 +                       uint8_t *hnonce, uint8_t *dnonce,
10410 +                       uint8_t *kck, uint8_t *ptk);
10411 +
10412 +
10413 +void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t
10414 +                       *kck, uint8_t *data, uint8_t *mic);
10415 +
10416 +#ifdef __cplusplus
10417 +}
10418 +#endif
10419 +
10420 +#endif /* _DWC_CRYPTO_H_ */
10421 --- /dev/null
10422 +++ b/drivers/usb/host/dwc_common_port/dwc_dh.c
10423 @@ -0,0 +1,291 @@
10424 +/* =========================================================================
10425 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $
10426 + * $Revision: #3 $
10427 + * $Date: 2010/09/28 $
10428 + * $Change: 1596182 $
10429 + *
10430 + * Synopsys Portability Library Software and documentation
10431 + * (hereinafter, "Software") is an Unsupported proprietary work of
10432 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10433 + * between Synopsys and you.
10434 + *
10435 + * The Software IS NOT an item of Licensed Software or Licensed Product
10436 + * under any End User Software License Agreement or Agreement for
10437 + * Licensed Product with Synopsys or any supplement thereto. You are
10438 + * permitted to use and redistribute this Software in source and binary
10439 + * forms, with or without modification, provided that redistributions
10440 + * of source code must retain this notice. You may not view, use,
10441 + * disclose, copy or distribute this file or any information contained
10442 + * herein except pursuant to this license grant from Synopsys. If you
10443 + * do not agree with this notice, including the disclaimer below, then
10444 + * you are not authorized to use the Software.
10445 + *
10446 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10447 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10448 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10449 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10450 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10451 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10452 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10453 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10454 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10455 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10456 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10457 + * DAMAGE.
10458 + * ========================================================================= */
10459 +#ifdef DWC_CRYPTOLIB
10460 +
10461 +#ifndef CONFIG_MACH_IPMATE
10462 +
10463 +#include "dwc_dh.h"
10464 +#include "dwc_modpow.h"
10465 +
10466 +#ifdef DEBUG
10467 +/* This function prints out a buffer in the format described in the Association
10468 + * Model specification. */
10469 +static void dh_dump(char *str, void *_num, int len)
10470 +{
10471 +       uint8_t *num = _num;
10472 +       int i;
10473 +       DWC_PRINTF("%s\n", str);
10474 +       for (i = 0; i < len; i ++) {
10475 +               DWC_PRINTF("%02x", num[i]);
10476 +               if (((i + 1) % 2) == 0) DWC_PRINTF(" ");
10477 +               if (((i + 1) % 26) == 0) DWC_PRINTF("\n");
10478 +       }
10479 +
10480 +       DWC_PRINTF("\n");
10481 +}
10482 +#else
10483 +#define dh_dump(_x...) do {; } while(0)
10484 +#endif
10485 +
10486 +/* Constant g value */
10487 +static __u32 dh_g[] = {
10488 +       0x02000000,
10489 +};
10490 +
10491 +/* Constant p value */
10492 +static __u32 dh_p[] = {
10493 +       0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A,
10494 +       0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2,
10495 +       0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4,
10496 +       0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1,
10497 +       0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520,
10498 +       0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E,
10499 +       0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895,
10500 +       0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004,
10501 +       0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6,
10502 +       0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9,
10503 +       0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA,
10504 +       0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF,
10505 +};
10506 +
10507 +static void dh_swap_bytes(void *_in, void *_out, uint32_t len)
10508 +{
10509 +       uint8_t *in = _in;
10510 +       uint8_t *out = _out;
10511 +       int i;
10512 +       for (i=0; i<len; i++) {
10513 +               out[i] = in[len-1-i];
10514 +       }
10515 +}
10516 +
10517 +/* Computes the modular exponentiation (num^exp % mod).  num, exp, and mod are
10518 + * big endian numbers of size len, in bytes.  Each len value must be a multiple
10519 + * of 4. */
10520 +int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
10521 +                 void *exp, uint32_t exp_len,
10522 +                 void *mod, uint32_t mod_len,
10523 +                 void *out)
10524 +{
10525 +       /* modpow() takes little endian numbers.  AM uses big-endian.  This
10526 +        * function swaps bytes of numbers before passing onto modpow. */
10527 +
10528 +       int retval = 0;
10529 +       uint32_t *result;
10530 +
10531 +       uint32_t *bignum_num = dwc_alloc(mem_ctx, num_len + 4);
10532 +       uint32_t *bignum_exp = dwc_alloc(mem_ctx, exp_len + 4);
10533 +       uint32_t *bignum_mod = dwc_alloc(mem_ctx, mod_len + 4);
10534 +
10535 +       dh_swap_bytes(num, &bignum_num[1], num_len);
10536 +       bignum_num[0] = num_len / 4;
10537 +
10538 +       dh_swap_bytes(exp, &bignum_exp[1], exp_len);
10539 +       bignum_exp[0] = exp_len / 4;
10540 +
10541 +       dh_swap_bytes(mod, &bignum_mod[1], mod_len);
10542 +       bignum_mod[0] = mod_len / 4;
10543 +
10544 +       result = dwc_modpow(mem_ctx, bignum_num, bignum_exp, bignum_mod);
10545 +       if (!result) {
10546 +               retval = -1;
10547 +               goto dh_modpow_nomem;
10548 +       }
10549 +
10550 +       dh_swap_bytes(&result[1], out, result[0] * 4);
10551 +       dwc_free(mem_ctx, result);
10552 +
10553 + dh_modpow_nomem:
10554 +       dwc_free(mem_ctx, bignum_num);
10555 +       dwc_free(mem_ctx, bignum_exp);
10556 +       dwc_free(mem_ctx, bignum_mod);
10557 +       return retval;
10558 +}
10559 +
10560 +
10561 +int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pk, uint8_t *hash)
10562 +{
10563 +       int retval;
10564 +       uint8_t m3[385];
10565 +
10566 +#ifndef DH_TEST_VECTORS
10567 +       DWC_RANDOM_BYTES(exp, 32);
10568 +#endif
10569 +
10570 +       /* Compute the pkd */
10571 +       if ((retval = dwc_dh_modpow(mem_ctx, dh_g, 4,
10572 +                                   exp, 32,
10573 +                                   dh_p, 384, pk))) {
10574 +               return retval;
10575 +       }
10576 +
10577 +       m3[384] = nd;
10578 +       DWC_MEMCPY(&m3[0], pk, 384);
10579 +       DWC_SHA256(m3, 385, hash);
10580 +
10581 +       dh_dump("PK", pk, 384);
10582 +       dh_dump("SHA-256(M3)", hash, 32);
10583 +       return 0;
10584 +}
10585 +
10586 +int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
10587 +                      uint8_t *exp, int is_host,
10588 +                      char *dd, uint8_t *ck, uint8_t *kdk)
10589 +{
10590 +       int retval;
10591 +       uint8_t mv[784];
10592 +       uint8_t sha_result[32];
10593 +       uint8_t dhkey[384];
10594 +       uint8_t shared_secret[384];
10595 +       char *message;
10596 +       uint32_t vd;
10597 +
10598 +       uint8_t *pk;
10599 +
10600 +       if (is_host) {
10601 +               pk = pkd;
10602 +       }
10603 +       else {
10604 +               pk = pkh;
10605 +       }
10606 +
10607 +       if ((retval = dwc_dh_modpow(mem_ctx, pk, 384,
10608 +                                   exp, 32,
10609 +                                   dh_p, 384, shared_secret))) {
10610 +               return retval;
10611 +       }
10612 +       dh_dump("Shared Secret", shared_secret, 384);
10613 +
10614 +       DWC_SHA256(shared_secret, 384, dhkey);
10615 +       dh_dump("DHKEY", dhkey, 384);
10616 +
10617 +       DWC_MEMCPY(&mv[0], pkd, 384);
10618 +       DWC_MEMCPY(&mv[384], pkh, 384);
10619 +       DWC_MEMCPY(&mv[768], "displayed digest", 16);
10620 +       dh_dump("MV", mv, 784);
10621 +
10622 +       DWC_SHA256(mv, 784, sha_result);
10623 +       dh_dump("SHA-256(MV)", sha_result, 32);
10624 +       dh_dump("First 32-bits of SHA-256(MV)", sha_result, 4);
10625 +
10626 +       dh_swap_bytes(sha_result, &vd, 4);
10627 +#ifdef DEBUG
10628 +       DWC_PRINTF("Vd (decimal) = %d\n", vd);
10629 +#endif
10630 +
10631 +       switch (nd) {
10632 +       case 2:
10633 +               vd = vd % 100;
10634 +               DWC_SPRINTF(dd, "%02d", vd);
10635 +               break;
10636 +       case 3:
10637 +               vd = vd % 1000;
10638 +               DWC_SPRINTF(dd, "%03d", vd);
10639 +               break;
10640 +       case 4:
10641 +               vd = vd % 10000;
10642 +               DWC_SPRINTF(dd, "%04d", vd);
10643 +               break;
10644 +       }
10645 +#ifdef DEBUG
10646 +       DWC_PRINTF("Display Digits: %s\n", dd);
10647 +#endif
10648 +
10649 +       message = "connection key";
10650 +       DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
10651 +       dh_dump("HMAC(SHA-256, DHKey, connection key)", sha_result, 32);
10652 +       DWC_MEMCPY(ck, sha_result, 16);
10653 +
10654 +       message = "key derivation key";
10655 +       DWC_HMAC_SHA256(message, DWC_STRLEN(message), dhkey, 32, sha_result);
10656 +       dh_dump("HMAC(SHA-256, DHKey, key derivation key)", sha_result, 32);
10657 +       DWC_MEMCPY(kdk, sha_result, 32);
10658 +
10659 +       return 0;
10660 +}
10661 +
10662 +
10663 +#ifdef DH_TEST_VECTORS
10664 +
10665 +static __u8 dh_a[] = {
10666 +       0x44, 0x00, 0x51, 0xd6,
10667 +       0xf0, 0xb5, 0x5e, 0xa9,
10668 +       0x67, 0xab, 0x31, 0xc6,
10669 +       0x8a, 0x8b, 0x5e, 0x37,
10670 +       0xd9, 0x10, 0xda, 0xe0,
10671 +       0xe2, 0xd4, 0x59, 0xa4,
10672 +       0x86, 0x45, 0x9c, 0xaa,
10673 +       0xdf, 0x36, 0x75, 0x16,
10674 +};
10675 +
10676 +static __u8 dh_b[] = {
10677 +       0x5d, 0xae, 0xc7, 0x86,
10678 +       0x79, 0x80, 0xa3, 0x24,
10679 +       0x8c, 0xe3, 0x57, 0x8f,
10680 +       0xc7, 0x5f, 0x1b, 0x0f,
10681 +       0x2d, 0xf8, 0x9d, 0x30,
10682 +       0x6f, 0xa4, 0x52, 0xcd,
10683 +       0xe0, 0x7a, 0x04, 0x8a,
10684 +       0xde, 0xd9, 0x26, 0x56,
10685 +};
10686 +
10687 +void dwc_run_dh_test_vectors(void *mem_ctx)
10688 +{
10689 +       uint8_t pkd[384];
10690 +       uint8_t pkh[384];
10691 +       uint8_t hashd[32];
10692 +       uint8_t hashh[32];
10693 +       uint8_t ck[16];
10694 +       uint8_t kdk[32];
10695 +       char dd[5];
10696 +
10697 +       DWC_PRINTF("\n\n\nDH_TEST_VECTORS\n\n");
10698 +
10699 +       /* compute the PKd and SHA-256(PKd || Nd) */
10700 +       DWC_PRINTF("Computing PKd\n");
10701 +       dwc_dh_pk(mem_ctx, 2, dh_a, pkd, hashd);
10702 +
10703 +       /* compute the PKd and SHA-256(PKh || Nd) */
10704 +       DWC_PRINTF("Computing PKh\n");
10705 +       dwc_dh_pk(mem_ctx, 2, dh_b, pkh, hashh);
10706 +
10707 +       /* compute the dhkey */
10708 +       dwc_dh_derive_keys(mem_ctx, 2, pkh, pkd, dh_a, 0, dd, ck, kdk);
10709 +}
10710 +#endif /* DH_TEST_VECTORS */
10711 +
10712 +#endif /* !CONFIG_MACH_IPMATE */
10713 +
10714 +#endif /* DWC_CRYPTOLIB */
10715 --- /dev/null
10716 +++ b/drivers/usb/host/dwc_common_port/dwc_dh.h
10717 @@ -0,0 +1,106 @@
10718 +/* =========================================================================
10719 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.h $
10720 + * $Revision: #4 $
10721 + * $Date: 2010/09/28 $
10722 + * $Change: 1596182 $
10723 + *
10724 + * Synopsys Portability Library Software and documentation
10725 + * (hereinafter, "Software") is an Unsupported proprietary work of
10726 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
10727 + * between Synopsys and you.
10728 + *
10729 + * The Software IS NOT an item of Licensed Software or Licensed Product
10730 + * under any End User Software License Agreement or Agreement for
10731 + * Licensed Product with Synopsys or any supplement thereto. You are
10732 + * permitted to use and redistribute this Software in source and binary
10733 + * forms, with or without modification, provided that redistributions
10734 + * of source code must retain this notice. You may not view, use,
10735 + * disclose, copy or distribute this file or any information contained
10736 + * herein except pursuant to this license grant from Synopsys. If you
10737 + * do not agree with this notice, including the disclaimer below, then
10738 + * you are not authorized to use the Software.
10739 + *
10740 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
10741 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
10742 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
10743 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
10744 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
10745 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
10746 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
10747 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
10748 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10749 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
10750 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
10751 + * DAMAGE.
10752 + * ========================================================================= */
10753 +#ifndef _DWC_DH_H_
10754 +#define _DWC_DH_H_
10755 +
10756 +#ifdef __cplusplus
10757 +extern "C" {
10758 +#endif
10759 +
10760 +#include "dwc_os.h"
10761 +
10762 +/** @file
10763 + *
10764 + * This file defines the common functions on device and host for performing
10765 + * numeric association as defined in the WUSB spec.  They are only to be
10766 + * used internally by the DWC UWB modules. */
10767 +
10768 +extern int dwc_dh_sha256(uint8_t *message, uint32_t len, uint8_t *out);
10769 +extern int dwc_dh_hmac_sha256(uint8_t *message, uint32_t messagelen,
10770 +                             uint8_t *key, uint32_t keylen,
10771 +                             uint8_t *out);
10772 +extern int dwc_dh_modpow(void *mem_ctx, void *num, uint32_t num_len,
10773 +                        void *exp, uint32_t exp_len,
10774 +                        void *mod, uint32_t mod_len,
10775 +                        void *out);
10776 +
10777 +/** Computes PKD or PKH, and SHA-256(PKd || Nd)
10778 + *
10779 + * PK = g^exp mod p.
10780 + *
10781 + * Input:
10782 + * Nd = Number of digits on the device.
10783 + *
10784 + * Output:
10785 + * exp = A 32-byte buffer to be filled with a randomly generated number.
10786 + *       used as either A or B.
10787 + * pk = A 384-byte buffer to be filled with the PKH or PKD.
10788 + * hash = A 32-byte buffer to be filled with SHA-256(PK || ND).
10789 + */
10790 +extern int dwc_dh_pk(void *mem_ctx, uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash);
10791 +
10792 +/** Computes the DHKEY, and VD.
10793 + *
10794 + * If called from host, then it will comput DHKEY=PKD^exp % p.
10795 + * If called from device, then it will comput DHKEY=PKH^exp % p.
10796 + *
10797 + * Input:
10798 + * pkd = The PKD value.
10799 + * pkh = The PKH value.
10800 + * exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk.
10801 + * is_host = Set to non zero if a WUSB host is calling this function.
10802 + *
10803 + * Output:
10804 +
10805 + * dd = A pointer to an buffer to be set to the displayed digits string to be shown
10806 + *      to the user.  This buffer should be at 5 bytes long to hold 4 digits plus a
10807 + *      null termination character.  This buffer can be used directly for display.
10808 + * ck = A 16-byte buffer to be filled with the CK.
10809 + * kdk = A 32-byte buffer to be filled with the KDK.
10810 + */
10811 +extern int dwc_dh_derive_keys(void *mem_ctx, uint8_t nd, uint8_t *pkh, uint8_t *pkd,
10812 +                             uint8_t *exp, int is_host,
10813 +                             char *dd, uint8_t *ck, uint8_t *kdk);
10814 +
10815 +#ifdef DH_TEST_VECTORS
10816 +extern void dwc_run_dh_test_vectors(void);
10817 +#endif
10818 +
10819 +#ifdef __cplusplus
10820 +}
10821 +#endif
10822 +
10823 +#endif /* _DWC_DH_H_ */
10824 --- /dev/null
10825 +++ b/drivers/usb/host/dwc_common_port/dwc_list.h
10826 @@ -0,0 +1,594 @@
10827 +/*     $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $       */
10828 +/*     $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $       */
10829 +
10830 +/*
10831 + * Copyright (c) 1991, 1993
10832 + *     The Regents of the University of California.  All rights reserved.
10833 + *
10834 + * Redistribution and use in source and binary forms, with or without
10835 + * modification, are permitted provided that the following conditions
10836 + * are met:
10837 + * 1. Redistributions of source code must retain the above copyright
10838 + *    notice, this list of conditions and the following disclaimer.
10839 + * 2. Redistributions in binary form must reproduce the above copyright
10840 + *    notice, this list of conditions and the following disclaimer in the
10841 + *    documentation and/or other materials provided with the distribution.
10842 + * 3. Neither the name of the University nor the names of its contributors
10843 + *    may be used to endorse or promote products derived from this software
10844 + *    without specific prior written permission.
10845 + *
10846 + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
10847 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10848 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10849 + * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
10850 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
10851 + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
10852 + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
10853 + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
10854 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
10855 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
10856 + * SUCH DAMAGE.
10857 + *
10858 + *     @(#)queue.h     8.5 (Berkeley) 8/20/94
10859 + */
10860 +
10861 +#ifndef _DWC_LIST_H_
10862 +#define _DWC_LIST_H_
10863 +
10864 +#ifdef __cplusplus
10865 +extern "C" {
10866 +#endif
10867 +
10868 +/** @file
10869 + *
10870 + * This file defines linked list operations.  It is derived from BSD with
10871 + * only the MACRO names being prefixed with DWC_.  This is because a few of
10872 + * these names conflict with those on Linux.  For documentation on use, see the
10873 + * inline comments in the source code.  The original license for this source
10874 + * code applies and is preserved in the dwc_list.h source file.
10875 + */
10876 +
10877 +/*
10878 + * This file defines five types of data structures: singly-linked lists,
10879 + * lists, simple queues, tail queues, and circular queues.
10880 + *
10881 + *
10882 + * A singly-linked list is headed by a single forward pointer. The elements
10883 + * are singly linked for minimum space and pointer manipulation overhead at
10884 + * the expense of O(n) removal for arbitrary elements. New elements can be
10885 + * added to the list after an existing element or at the head of the list.
10886 + * Elements being removed from the head of the list should use the explicit
10887 + * macro for this purpose for optimum efficiency. A singly-linked list may
10888 + * only be traversed in the forward direction.  Singly-linked lists are ideal
10889 + * for applications with large datasets and few or no removals or for
10890 + * implementing a LIFO queue.
10891 + *
10892 + * A list is headed by a single forward pointer (or an array of forward
10893 + * pointers for a hash table header). The elements are doubly linked
10894 + * so that an arbitrary element can be removed without a need to
10895 + * traverse the list. New elements can be added to the list before
10896 + * or after an existing element or at the head of the list. A list
10897 + * may only be traversed in the forward direction.
10898 + *
10899 + * A simple queue is headed by a pair of pointers, one the head of the
10900 + * list and the other to the tail of the list. The elements are singly
10901 + * linked to save space, so elements can only be removed from the
10902 + * head of the list. New elements can be added to the list before or after
10903 + * an existing element, at the head of the list, or at the end of the
10904 + * list. A simple queue may only be traversed in the forward direction.
10905 + *
10906 + * A tail queue is headed by a pair of pointers, one to the head of the
10907 + * list and the other to the tail of the list. The elements are doubly
10908 + * linked so that an arbitrary element can be removed without a need to
10909 + * traverse the list. New elements can be added to the list before or
10910 + * after an existing element, at the head of the list, or at the end of
10911 + * the list. A tail queue may be traversed in either direction.
10912 + *
10913 + * A circle queue is headed by a pair of pointers, one to the head of the
10914 + * list and the other to the tail of the list. The elements are doubly
10915 + * linked so that an arbitrary element can be removed without a need to
10916 + * traverse the list. New elements can be added to the list before or after
10917 + * an existing element, at the head of the list, or at the end of the list.
10918 + * A circle queue may be traversed in either direction, but has a more
10919 + * complex end of list detection.
10920 + *
10921 + * For details on the use of these macros, see the queue(3) manual page.
10922 + */
10923 +
10924 +/*
10925 + * Double-linked List.
10926 + */
10927 +
10928 +typedef struct dwc_list_link {
10929 +       struct dwc_list_link *next;
10930 +       struct dwc_list_link *prev;
10931 +} dwc_list_link_t;
10932 +
10933 +#define DWC_LIST_INIT(link) do {       \
10934 +       (link)->next = (link);          \
10935 +       (link)->prev = (link);          \
10936 +} while (0)
10937 +
10938 +#define DWC_LIST_FIRST(link)   ((link)->next)
10939 +#define DWC_LIST_LAST(link)    ((link)->prev)
10940 +#define DWC_LIST_END(link)     (link)
10941 +#define DWC_LIST_NEXT(link)    ((link)->next)
10942 +#define DWC_LIST_PREV(link)    ((link)->prev)
10943 +#define DWC_LIST_EMPTY(link)   \
10944 +       (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
10945 +#define DWC_LIST_ENTRY(link, type, field)                      \
10946 +       (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
10947 +
10948 +#if 0
10949 +#define DWC_LIST_INSERT_HEAD(list, link) do {                  \
10950 +       (link)->next = (list)->next;                            \
10951 +       (link)->prev = (list);                                  \
10952 +       (list)->next->prev = (link);                            \
10953 +       (list)->next = (link);                                  \
10954 +} while (0)
10955 +
10956 +#define DWC_LIST_INSERT_TAIL(list, link) do {                  \
10957 +       (link)->next = (list);                                  \
10958 +       (link)->prev = (list)->prev;                            \
10959 +       (list)->prev->next = (link);                            \
10960 +       (list)->prev = (link);                                  \
10961 +} while (0)
10962 +#else
10963 +#define DWC_LIST_INSERT_HEAD(list, link) do {                  \
10964 +       dwc_list_link_t *__next__ = (list)->next;               \
10965 +       __next__->prev = (link);                                \
10966 +       (link)->next = __next__;                                \
10967 +       (link)->prev = (list);                                  \
10968 +       (list)->next = (link);                                  \
10969 +} while (0)
10970 +
10971 +#define DWC_LIST_INSERT_TAIL(list, link) do {                  \
10972 +       dwc_list_link_t *__prev__ = (list)->prev;               \
10973 +       (list)->prev = (link);                                  \
10974 +       (link)->next = (list);                                  \
10975 +       (link)->prev = __prev__;                                \
10976 +       __prev__->next = (link);                                \
10977 +} while (0)
10978 +#endif
10979 +
10980 +#if 0
10981 +static inline void __list_add(struct list_head *new,
10982 +                              struct list_head *prev,
10983 +                              struct list_head *next)
10984 +{
10985 +        next->prev = new;
10986 +        new->next = next;
10987 +        new->prev = prev;
10988 +        prev->next = new;
10989 +}
10990 +
10991 +static inline void list_add(struct list_head *new, struct list_head *head)
10992 +{
10993 +        __list_add(new, head, head->next);
10994 +}
10995 +
10996 +static inline void list_add_tail(struct list_head *new, struct list_head *head)
10997 +{
10998 +        __list_add(new, head->prev, head);
10999 +}
11000 +
11001 +static inline void __list_del(struct list_head * prev, struct list_head * next)
11002 +{
11003 +        next->prev = prev;
11004 +        prev->next = next;
11005 +}
11006 +
11007 +static inline void list_del(struct list_head *entry)
11008 +{
11009 +        __list_del(entry->prev, entry->next);
11010 +        entry->next = LIST_POISON1;
11011 +        entry->prev = LIST_POISON2;
11012 +}
11013 +#endif
11014 +
11015 +#define DWC_LIST_REMOVE(link) do {                             \
11016 +       (link)->next->prev = (link)->prev;                      \
11017 +       (link)->prev->next = (link)->next;                      \
11018 +} while (0)
11019 +
11020 +#define DWC_LIST_REMOVE_INIT(link) do {                                \
11021 +       DWC_LIST_REMOVE(link);                                  \
11022 +       DWC_LIST_INIT(link);                                    \
11023 +} while (0)
11024 +
11025 +#define DWC_LIST_MOVE_HEAD(list, link) do {                    \
11026 +       DWC_LIST_REMOVE(link);                                  \
11027 +       DWC_LIST_INSERT_HEAD(list, link);                       \
11028 +} while (0)
11029 +
11030 +#define DWC_LIST_MOVE_TAIL(list, link) do {                    \
11031 +       DWC_LIST_REMOVE(link);                                  \
11032 +       DWC_LIST_INSERT_TAIL(list, link);                       \
11033 +} while (0)
11034 +
11035 +#define DWC_LIST_FOREACH(var, list)                            \
11036 +       for((var) = DWC_LIST_FIRST(list);                       \
11037 +           (var) != DWC_LIST_END(list);                        \
11038 +           (var) = DWC_LIST_NEXT(var))
11039 +
11040 +#define DWC_LIST_FOREACH_SAFE(var, var2, list)                 \
11041 +       for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var);  \
11042 +           (var) != DWC_LIST_END(list);                        \
11043 +           (var) = (var2), (var2) = DWC_LIST_NEXT(var2))
11044 +
11045 +#define DWC_LIST_FOREACH_REVERSE(var, list)                    \
11046 +       for((var) = DWC_LIST_LAST(list);                        \
11047 +           (var) != DWC_LIST_END(list);                        \
11048 +           (var) = DWC_LIST_PREV(var))
11049 +
11050 +/*
11051 + * Singly-linked List definitions.
11052 + */
11053 +#define DWC_SLIST_HEAD(name, type)                                     \
11054 +struct name {                                                          \
11055 +       struct type *slh_first; /* first element */                     \
11056 +}
11057 +
11058 +#define DWC_SLIST_HEAD_INITIALIZER(head)                               \
11059 +       { NULL }
11060 +
11061 +#define DWC_SLIST_ENTRY(type)                                          \
11062 +struct {                                                               \
11063 +       struct type *sle_next;  /* next element */                      \
11064 +}
11065 +
11066 +/*
11067 + * Singly-linked List access methods.
11068 + */
11069 +#define DWC_SLIST_FIRST(head)  ((head)->slh_first)
11070 +#define DWC_SLIST_END(head)            NULL
11071 +#define DWC_SLIST_EMPTY(head)  (SLIST_FIRST(head) == SLIST_END(head))
11072 +#define DWC_SLIST_NEXT(elm, field)     ((elm)->field.sle_next)
11073 +
11074 +#define DWC_SLIST_FOREACH(var, head, field)                            \
11075 +       for((var) = SLIST_FIRST(head);                                  \
11076 +           (var) != SLIST_END(head);                                   \
11077 +           (var) = SLIST_NEXT(var, field))
11078 +
11079 +#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field)              \
11080 +       for((varp) = &SLIST_FIRST((head));                              \
11081 +           ((var) = *(varp)) != SLIST_END(head);                       \
11082 +           (varp) = &SLIST_NEXT((var), field))
11083 +
11084 +/*
11085 + * Singly-linked List functions.
11086 + */
11087 +#define DWC_SLIST_INIT(head) {                                         \
11088 +       SLIST_FIRST(head) = SLIST_END(head);                            \
11089 +}
11090 +
11091 +#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do {              \
11092 +       (elm)->field.sle_next = (slistelm)->field.sle_next;             \
11093 +       (slistelm)->field.sle_next = (elm);                             \
11094 +} while (0)
11095 +
11096 +#define DWC_SLIST_INSERT_HEAD(head, elm, field) do {                   \
11097 +       (elm)->field.sle_next = (head)->slh_first;                      \
11098 +       (head)->slh_first = (elm);                                      \
11099 +} while (0)
11100 +
11101 +#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do {                   \
11102 +       (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next;  \
11103 +} while (0)
11104 +
11105 +#define DWC_SLIST_REMOVE_HEAD(head, field) do {                                \
11106 +       (head)->slh_first = (head)->slh_first->field.sle_next;          \
11107 +} while (0)
11108 +
11109 +#define DWC_SLIST_REMOVE(head, elm, type, field) do {                  \
11110 +       if ((head)->slh_first == (elm)) {                               \
11111 +               SLIST_REMOVE_HEAD((head), field);                       \
11112 +       }                                                               \
11113 +       else {                                                          \
11114 +               struct type *curelm = (head)->slh_first;                \
11115 +               while( curelm->field.sle_next != (elm) )                \
11116 +                       curelm = curelm->field.sle_next;                \
11117 +               curelm->field.sle_next =                                \
11118 +                   curelm->field.sle_next->field.sle_next;             \
11119 +       }                                                               \
11120 +} while (0)
11121 +
11122 +/*
11123 + * Simple queue definitions.
11124 + */
11125 +#define DWC_SIMPLEQ_HEAD(name, type)                                   \
11126 +struct name {                                                          \
11127 +       struct type *sqh_first; /* first element */                     \
11128 +       struct type **sqh_last; /* addr of last next element */         \
11129 +}
11130 +
11131 +#define DWC_SIMPLEQ_HEAD_INITIALIZER(head)                             \
11132 +       { NULL, &(head).sqh_first }
11133 +
11134 +#define DWC_SIMPLEQ_ENTRY(type)                                                \
11135 +struct {                                                               \
11136 +       struct type *sqe_next;  /* next element */                      \
11137 +}
11138 +
11139 +/*
11140 + * Simple queue access methods.
11141 + */
11142 +#define DWC_SIMPLEQ_FIRST(head)            ((head)->sqh_first)
11143 +#define DWC_SIMPLEQ_END(head)      NULL
11144 +#define DWC_SIMPLEQ_EMPTY(head)            (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
11145 +#define DWC_SIMPLEQ_NEXT(elm, field)    ((elm)->field.sqe_next)
11146 +
11147 +#define DWC_SIMPLEQ_FOREACH(var, head, field)                          \
11148 +       for((var) = SIMPLEQ_FIRST(head);                                \
11149 +           (var) != SIMPLEQ_END(head);                                 \
11150 +           (var) = SIMPLEQ_NEXT(var, field))
11151 +
11152 +/*
11153 + * Simple queue functions.
11154 + */
11155 +#define DWC_SIMPLEQ_INIT(head) do {                                    \
11156 +       (head)->sqh_first = NULL;                                       \
11157 +       (head)->sqh_last = &(head)->sqh_first;                          \
11158 +} while (0)
11159 +
11160 +#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do {                 \
11161 +       if (((elm)->field.sqe_next = (head)->sqh_first) == NULL)        \
11162 +               (head)->sqh_last = &(elm)->field.sqe_next;              \
11163 +       (head)->sqh_first = (elm);                                      \
11164 +} while (0)
11165 +
11166 +#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do {                 \
11167 +       (elm)->field.sqe_next = NULL;                                   \
11168 +       *(head)->sqh_last = (elm);                                      \
11169 +       (head)->sqh_last = &(elm)->field.sqe_next;                      \
11170 +} while (0)
11171 +
11172 +#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do {       \
11173 +       if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
11174 +               (head)->sqh_last = &(elm)->field.sqe_next;              \
11175 +       (listelm)->field.sqe_next = (elm);                              \
11176 +} while (0)
11177 +
11178 +#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do {                      \
11179 +       if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
11180 +               (head)->sqh_last = &(head)->sqh_first;                  \
11181 +} while (0)
11182 +
11183 +/*
11184 + * Tail queue definitions.
11185 + */
11186 +#define DWC_TAILQ_HEAD(name, type)                                     \
11187 +struct name {                                                          \
11188 +       struct type *tqh_first; /* first element */                     \
11189 +       struct type **tqh_last; /* addr of last next element */         \
11190 +}
11191 +
11192 +#define DWC_TAILQ_HEAD_INITIALIZER(head)                               \
11193 +       { NULL, &(head).tqh_first }
11194 +
11195 +#define DWC_TAILQ_ENTRY(type)                                          \
11196 +struct {                                                               \
11197 +       struct type *tqe_next;  /* next element */                      \
11198 +       struct type **tqe_prev; /* address of previous next element */  \
11199 +}
11200 +
11201 +/*
11202 + * tail queue access methods
11203 + */
11204 +#define DWC_TAILQ_FIRST(head)          ((head)->tqh_first)
11205 +#define DWC_TAILQ_END(head)            NULL
11206 +#define DWC_TAILQ_NEXT(elm, field)     ((elm)->field.tqe_next)
11207 +#define DWC_TAILQ_LAST(head, headname)                                 \
11208 +       (*(((struct headname *)((head)->tqh_last))->tqh_last))
11209 +/* XXX */
11210 +#define DWC_TAILQ_PREV(elm, headname, field)                           \
11211 +       (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
11212 +#define DWC_TAILQ_EMPTY(head)                                          \
11213 +       (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head))
11214 +
11215 +#define DWC_TAILQ_FOREACH(var, head, field)                            \
11216 +       for ((var) = DWC_TAILQ_FIRST(head);                             \
11217 +           (var) != DWC_TAILQ_END(head);                               \
11218 +           (var) = DWC_TAILQ_NEXT(var, field))
11219 +
11220 +#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field)          \
11221 +       for ((var) = DWC_TAILQ_LAST(head, headname);                    \
11222 +           (var) != DWC_TAILQ_END(head);                               \
11223 +           (var) = DWC_TAILQ_PREV(var, headname, field))
11224 +
11225 +/*
11226 + * Tail queue functions.
11227 + */
11228 +#define DWC_TAILQ_INIT(head) do {                                      \
11229 +       (head)->tqh_first = NULL;                                       \
11230 +       (head)->tqh_last = &(head)->tqh_first;                          \
11231 +} while (0)
11232 +
11233 +#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do {                   \
11234 +       if (((elm)->field.tqe_next = (head)->tqh_first) != NULL)        \
11235 +               (head)->tqh_first->field.tqe_prev =                     \
11236 +                   &(elm)->field.tqe_next;                             \
11237 +       else                                                            \
11238 +               (head)->tqh_last = &(elm)->field.tqe_next;              \
11239 +       (head)->tqh_first = (elm);                                      \
11240 +       (elm)->field.tqe_prev = &(head)->tqh_first;                     \
11241 +} while (0)
11242 +
11243 +#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do {                   \
11244 +       (elm)->field.tqe_next = NULL;                                   \
11245 +       (elm)->field.tqe_prev = (head)->tqh_last;                       \
11246 +       *(head)->tqh_last = (elm);                                      \
11247 +       (head)->tqh_last = &(elm)->field.tqe_next;                      \
11248 +} while (0)
11249 +
11250 +#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do {         \
11251 +       if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
11252 +               (elm)->field.tqe_next->field.tqe_prev =                 \
11253 +                   &(elm)->field.tqe_next;                             \
11254 +       else                                                            \
11255 +               (head)->tqh_last = &(elm)->field.tqe_next;              \
11256 +       (listelm)->field.tqe_next = (elm);                              \
11257 +       (elm)->field.tqe_prev = &(listelm)->field.tqe_next;             \
11258 +} while (0)
11259 +
11260 +#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do {              \
11261 +       (elm)->field.tqe_prev = (listelm)->field.tqe_prev;              \
11262 +       (elm)->field.tqe_next = (listelm);                              \
11263 +       *(listelm)->field.tqe_prev = (elm);                             \
11264 +       (listelm)->field.tqe_prev = &(elm)->field.tqe_next;             \
11265 +} while (0)
11266 +
11267 +#define DWC_TAILQ_REMOVE(head, elm, field) do {                                \
11268 +       if (((elm)->field.tqe_next) != NULL)                            \
11269 +               (elm)->field.tqe_next->field.tqe_prev =                 \
11270 +                   (elm)->field.tqe_prev;                              \
11271 +       else                                                            \
11272 +               (head)->tqh_last = (elm)->field.tqe_prev;               \
11273 +       *(elm)->field.tqe_prev = (elm)->field.tqe_next;                 \
11274 +} while (0)
11275 +
11276 +#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do {                 \
11277 +       if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL)   \
11278 +               (elm2)->field.tqe_next->field.tqe_prev =                \
11279 +                   &(elm2)->field.tqe_next;                            \
11280 +       else                                                            \
11281 +               (head)->tqh_last = &(elm2)->field.tqe_next;             \
11282 +       (elm2)->field.tqe_prev = (elm)->field.tqe_prev;                 \
11283 +       *(elm2)->field.tqe_prev = (elm2);                               \
11284 +} while (0)
11285 +
11286 +/*
11287 + * Circular queue definitions.
11288 + */
11289 +#define DWC_CIRCLEQ_HEAD(name, type)                                   \
11290 +struct name {                                                          \
11291 +       struct type *cqh_first;         /* first element */             \
11292 +       struct type *cqh_last;          /* last element */              \
11293 +}
11294 +
11295 +#define DWC_CIRCLEQ_HEAD_INITIALIZER(head)                             \
11296 +       { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
11297 +
11298 +#define DWC_CIRCLEQ_ENTRY(type)                                                \
11299 +struct {                                                               \
11300 +       struct type *cqe_next;          /* next element */              \
11301 +       struct type *cqe_prev;          /* previous element */          \
11302 +}
11303 +
11304 +/*
11305 + * Circular queue access methods
11306 + */
11307 +#define DWC_CIRCLEQ_FIRST(head)                ((head)->cqh_first)
11308 +#define DWC_CIRCLEQ_LAST(head)         ((head)->cqh_last)
11309 +#define DWC_CIRCLEQ_END(head)          ((void *)(head))
11310 +#define DWC_CIRCLEQ_NEXT(elm, field)   ((elm)->field.cqe_next)
11311 +#define DWC_CIRCLEQ_PREV(elm, field)   ((elm)->field.cqe_prev)
11312 +#define DWC_CIRCLEQ_EMPTY(head)                                                \
11313 +       (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
11314 +
11315 +#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
11316 +
11317 +#define DWC_CIRCLEQ_FOREACH(var, head, field)                          \
11318 +       for((var) = DWC_CIRCLEQ_FIRST(head);                            \
11319 +           (var) != DWC_CIRCLEQ_END(head);                             \
11320 +           (var) = DWC_CIRCLEQ_NEXT(var, field))
11321 +
11322 +#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field)                       \
11323 +       for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
11324 +           (var) != DWC_CIRCLEQ_END(head);                                     \
11325 +           (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
11326 +
11327 +#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field)                  \
11328 +       for((var) = DWC_CIRCLEQ_LAST(head);                             \
11329 +           (var) != DWC_CIRCLEQ_END(head);                             \
11330 +           (var) = DWC_CIRCLEQ_PREV(var, field))
11331 +
11332 +/*
11333 + * Circular queue functions.
11334 + */
11335 +#define DWC_CIRCLEQ_INIT(head) do {                                    \
11336 +       (head)->cqh_first = DWC_CIRCLEQ_END(head);                      \
11337 +       (head)->cqh_last = DWC_CIRCLEQ_END(head);                       \
11338 +} while (0)
11339 +
11340 +#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do {                                \
11341 +       (elm)->field.cqe_next = NULL;                                   \
11342 +       (elm)->field.cqe_prev = NULL;                                   \
11343 +} while (0)
11344 +
11345 +#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do {       \
11346 +       (elm)->field.cqe_next = (listelm)->field.cqe_next;              \
11347 +       (elm)->field.cqe_prev = (listelm);                              \
11348 +       if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head))         \
11349 +               (head)->cqh_last = (elm);                               \
11350 +       else                                                            \
11351 +               (listelm)->field.cqe_next->field.cqe_prev = (elm);      \
11352 +       (listelm)->field.cqe_next = (elm);                              \
11353 +} while (0)
11354 +
11355 +#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do {      \
11356 +       (elm)->field.cqe_next = (listelm);                              \
11357 +       (elm)->field.cqe_prev = (listelm)->field.cqe_prev;              \
11358 +       if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head))         \
11359 +               (head)->cqh_first = (elm);                              \
11360 +       else                                                            \
11361 +               (listelm)->field.cqe_prev->field.cqe_next = (elm);      \
11362 +       (listelm)->field.cqe_prev = (elm);                              \
11363 +} while (0)
11364 +
11365 +#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do {                 \
11366 +       (elm)->field.cqe_next = (head)->cqh_first;                      \
11367 +       (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head);                  \
11368 +       if ((head)->cqh_last == DWC_CIRCLEQ_END(head))                  \
11369 +               (head)->cqh_last = (elm);                               \
11370 +       else                                                            \
11371 +               (head)->cqh_first->field.cqe_prev = (elm);              \
11372 +       (head)->cqh_first = (elm);                                      \
11373 +} while (0)
11374 +
11375 +#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do {                 \
11376 +       (elm)->field.cqe_next = DWC_CIRCLEQ_END(head);                  \
11377 +       (elm)->field.cqe_prev = (head)->cqh_last;                       \
11378 +       if ((head)->cqh_first == DWC_CIRCLEQ_END(head))                 \
11379 +               (head)->cqh_first = (elm);                              \
11380 +       else                                                            \
11381 +               (head)->cqh_last->field.cqe_next = (elm);               \
11382 +       (head)->cqh_last = (elm);                                       \
11383 +} while (0)
11384 +
11385 +#define DWC_CIRCLEQ_REMOVE(head, elm, field) do {                      \
11386 +       if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head))             \
11387 +               (head)->cqh_last = (elm)->field.cqe_prev;               \
11388 +       else                                                            \
11389 +               (elm)->field.cqe_next->field.cqe_prev =                 \
11390 +                   (elm)->field.cqe_prev;                              \
11391 +       if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head))             \
11392 +               (head)->cqh_first = (elm)->field.cqe_next;              \
11393 +       else                                                            \
11394 +               (elm)->field.cqe_prev->field.cqe_next =                 \
11395 +                   (elm)->field.cqe_next;                              \
11396 +} while (0)
11397 +
11398 +#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do {                 \
11399 +       DWC_CIRCLEQ_REMOVE(head, elm, field);                           \
11400 +       DWC_CIRCLEQ_INIT_ENTRY(elm, field);                             \
11401 +} while (0)
11402 +
11403 +#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do {               \
11404 +       if (((elm2)->field.cqe_next = (elm)->field.cqe_next) ==         \
11405 +           DWC_CIRCLEQ_END(head))                                      \
11406 +               (head).cqh_last = (elm2);                               \
11407 +       else                                                            \
11408 +               (elm2)->field.cqe_next->field.cqe_prev = (elm2);        \
11409 +       if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) ==         \
11410 +           DWC_CIRCLEQ_END(head))                                      \
11411 +               (head).cqh_first = (elm2);                              \
11412 +       else                                                            \
11413 +               (elm2)->field.cqe_prev->field.cqe_next = (elm2);        \
11414 +} while (0)
11415 +
11416 +#ifdef __cplusplus
11417 +}
11418 +#endif
11419 +
11420 +#endif /* _DWC_LIST_H_ */
11421 --- /dev/null
11422 +++ b/drivers/usb/host/dwc_common_port/dwc_mem.c
11423 @@ -0,0 +1,245 @@
11424 +/* Memory Debugging */
11425 +#ifdef DWC_DEBUG_MEMORY
11426 +
11427 +#include "dwc_os.h"
11428 +#include "dwc_list.h"
11429 +
11430 +struct allocation {
11431 +       void *addr;
11432 +       void *ctx;
11433 +       char *func;
11434 +       int line;
11435 +       uint32_t size;
11436 +       int dma;
11437 +       DWC_CIRCLEQ_ENTRY(allocation) entry;
11438 +};
11439 +
11440 +DWC_CIRCLEQ_HEAD(allocation_queue, allocation);
11441 +
11442 +struct allocation_manager {
11443 +       void *mem_ctx;
11444 +       struct allocation_queue allocations;
11445 +
11446 +       /* statistics */
11447 +       int num;
11448 +       int num_freed;
11449 +       int num_active;
11450 +       uint32_t total;
11451 +       uint32_t cur;
11452 +       uint32_t max;
11453 +};
11454 +
11455 +static struct allocation_manager *manager = NULL;
11456 +
11457 +static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr,
11458 +                         int dma)
11459 +{
11460 +       struct allocation *a;
11461 +
11462 +       DWC_ASSERT(manager != NULL, "manager not allocated");
11463 +
11464 +       a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a));
11465 +       if (!a) {
11466 +               return -DWC_E_NO_MEMORY;
11467 +       }
11468 +
11469 +       a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1);
11470 +       if (!a->func) {
11471 +               __DWC_FREE(manager->mem_ctx, a);
11472 +               return -DWC_E_NO_MEMORY;
11473 +       }
11474 +
11475 +       DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1);
11476 +       a->addr = addr;
11477 +       a->ctx = ctx;
11478 +       a->line = line;
11479 +       a->size = size;
11480 +       a->dma = dma;
11481 +       DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry);
11482 +
11483 +       /* Update stats */
11484 +       manager->num++;
11485 +       manager->num_active++;
11486 +       manager->total += size;
11487 +       manager->cur += size;
11488 +
11489 +       if (manager->max < manager->cur) {
11490 +               manager->max = manager->cur;
11491 +       }
11492 +
11493 +       return 0;
11494 +}
11495 +
11496 +static struct allocation *find_allocation(void *ctx, void *addr)
11497 +{
11498 +       struct allocation *a;
11499 +
11500 +       DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11501 +               if (a->ctx == ctx && a->addr == addr) {
11502 +                       return a;
11503 +               }
11504 +       }
11505 +
11506 +       return NULL;
11507 +}
11508 +
11509 +static void free_allocation(void *ctx, void *addr, char const *func, int line)
11510 +{
11511 +       struct allocation *a = find_allocation(ctx, addr);
11512 +
11513 +       if (!a) {
11514 +               DWC_ASSERT(0,
11515 +                          "Free of address %p that was never allocated or already freed %s:%d",
11516 +                          addr, func, line);
11517 +               return;
11518 +       }
11519 +
11520 +       DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry);
11521 +
11522 +       manager->num_active--;
11523 +       manager->num_freed++;
11524 +       manager->cur -= a->size;
11525 +       __DWC_FREE(manager->mem_ctx, a->func);
11526 +       __DWC_FREE(manager->mem_ctx, a);
11527 +}
11528 +
11529 +int dwc_memory_debug_start(void *mem_ctx)
11530 +{
11531 +       DWC_ASSERT(manager == NULL, "Memory debugging has already started\n");
11532 +
11533 +       if (manager) {
11534 +               return -DWC_E_BUSY;
11535 +       }
11536 +
11537 +       manager = __DWC_ALLOC(mem_ctx, sizeof(*manager));
11538 +       if (!manager) {
11539 +               return -DWC_E_NO_MEMORY;
11540 +       }
11541 +
11542 +       DWC_CIRCLEQ_INIT(&manager->allocations);
11543 +       manager->mem_ctx = mem_ctx;
11544 +       manager->num = 0;
11545 +       manager->num_freed = 0;
11546 +       manager->num_active = 0;
11547 +       manager->total = 0;
11548 +       manager->cur = 0;
11549 +       manager->max = 0;
11550 +
11551 +       return 0;
11552 +}
11553 +
11554 +void dwc_memory_debug_stop(void)
11555 +{
11556 +       struct allocation *a;
11557 +
11558 +       dwc_memory_debug_report();
11559 +
11560 +       DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11561 +               DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line);
11562 +               free_allocation(a->ctx, a->addr, NULL, -1);
11563 +       }
11564 +
11565 +       __DWC_FREE(manager->mem_ctx, manager);
11566 +}
11567 +
11568 +void dwc_memory_debug_report(void)
11569 +{
11570 +       struct allocation *a;
11571 +
11572 +       DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n");
11573 +       DWC_PRINTF("Num Allocations = %d\n", manager->num);
11574 +       DWC_PRINTF("Freed = %d\n", manager->num_freed);
11575 +       DWC_PRINTF("Active = %d\n", manager->num_active);
11576 +       DWC_PRINTF("Current Memory Used = %d\n", manager->cur);
11577 +       DWC_PRINTF("Total Memory Used = %d\n", manager->total);
11578 +       DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max);
11579 +       DWC_PRINTF("Unfreed allocations:\n");
11580 +
11581 +       DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) {
11582 +               DWC_PRINTF("    addr=%p, size=%d from %s:%d, DMA=%d\n",
11583 +                          a->addr, a->size, a->func, a->line, a->dma);
11584 +       }
11585 +}
11586 +
11587 +/* The replacement functions */
11588 +void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line)
11589 +{
11590 +       void *addr = __DWC_ALLOC(mem_ctx, size);
11591 +
11592 +       if (!addr) {
11593 +               return NULL;
11594 +       }
11595 +
11596 +       if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
11597 +               __DWC_FREE(mem_ctx, addr);
11598 +               return NULL;
11599 +       }
11600 +
11601 +       return addr;
11602 +}
11603 +
11604 +void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func,
11605 +                            int line)
11606 +{
11607 +       void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size);
11608 +
11609 +       if (!addr) {
11610 +               return NULL;
11611 +       }
11612 +
11613 +       if (add_allocation(mem_ctx, size, func, line, addr, 0)) {
11614 +               __DWC_FREE(mem_ctx, addr);
11615 +               return NULL;
11616 +       }
11617 +
11618 +       return addr;
11619 +}
11620 +
11621 +void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line)
11622 +{
11623 +       free_allocation(mem_ctx, addr, func, line);
11624 +       __DWC_FREE(mem_ctx, addr);
11625 +}
11626 +
11627 +void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
11628 +                         char const *func, int line)
11629 +{
11630 +       void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr);
11631 +
11632 +       if (!addr) {
11633 +               return NULL;
11634 +       }
11635 +
11636 +       if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
11637 +               __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
11638 +               return NULL;
11639 +       }
11640 +
11641 +       return addr;
11642 +}
11643 +
11644 +void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size,
11645 +                                dwc_dma_t *dma_addr, char const *func, int line)
11646 +{
11647 +       void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr);
11648 +
11649 +       if (!addr) {
11650 +               return NULL;
11651 +       }
11652 +
11653 +       if (add_allocation(dma_ctx, size, func, line, addr, 1)) {
11654 +               __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr);
11655 +               return NULL;
11656 +       }
11657 +
11658 +       return addr;
11659 +}
11660 +
11661 +void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
11662 +                       dwc_dma_t dma_addr, char const *func, int line)
11663 +{
11664 +       free_allocation(dma_ctx, virt_addr, func, line);
11665 +       __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr);
11666 +}
11667 +
11668 +#endif /* DWC_DEBUG_MEMORY */
11669 --- /dev/null
11670 +++ b/drivers/usb/host/dwc_common_port/dwc_modpow.c
11671 @@ -0,0 +1,636 @@
11672 +/* Bignum routines adapted from PUTTY sources.  PuTTY copyright notice follows.
11673 + *
11674 + * PuTTY is copyright 1997-2007 Simon Tatham.
11675 + *
11676 + * Portions copyright Robert de Bath, Joris van Rantwijk, Delian
11677 + * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry,
11678 + * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus
11679 + * Kuhn, and CORE SDI S.A.
11680 + *
11681 + * Permission is hereby granted, free of charge, to any person
11682 + * obtaining a copy of this software and associated documentation files
11683 + * (the "Software"), to deal in the Software without restriction,
11684 + * including without limitation the rights to use, copy, modify, merge,
11685 + * publish, distribute, sublicense, and/or sell copies of the Software,
11686 + * and to permit persons to whom the Software is furnished to do so,
11687 + * subject to the following conditions:
11688 + *
11689 + * The above copyright notice and this permission notice shall be
11690 + * included in all copies or substantial portions of the Software.
11691 +
11692 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11693 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11694 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
11695 + * NONINFRINGEMENT.  IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
11696 + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
11697 + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
11698 + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
11699 + *
11700 + */
11701 +#ifdef DWC_CRYPTOLIB
11702 +
11703 +#ifndef CONFIG_MACH_IPMATE
11704 +
11705 +#include "dwc_modpow.h"
11706 +
11707 +#define BIGNUM_INT_MASK  0xFFFFFFFFUL
11708 +#define BIGNUM_TOP_BIT   0x80000000UL
11709 +#define BIGNUM_INT_BITS  32
11710 +
11711 +
11712 +static void *snmalloc(void *mem_ctx, size_t n, size_t size)
11713 +{
11714 +    void *p;
11715 +    size *= n;
11716 +    if (size == 0) size = 1;
11717 +    p = dwc_alloc(mem_ctx, size);
11718 +    return p;
11719 +}
11720 +
11721 +#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type)))
11722 +#define sfree dwc_free
11723 +
11724 +/*
11725 + * Usage notes:
11726 + *  * Do not call the DIVMOD_WORD macro with expressions such as array
11727 + *    subscripts, as some implementations object to this (see below).
11728 + *  * Note that none of the division methods below will cope if the
11729 + *    quotient won't fit into BIGNUM_INT_BITS. Callers should be careful
11730 + *    to avoid this case.
11731 + *    If this condition occurs, in the case of the x86 DIV instruction,
11732 + *    an overflow exception will occur, which (according to a correspondent)
11733 + *    will manifest on Windows as something like
11734 + *      0xC0000095: Integer overflow
11735 + *    The C variant won't give the right answer, either.
11736 + */
11737 +
11738 +#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2)
11739 +
11740 +#if defined __GNUC__ && defined __i386__
11741 +#define DIVMOD_WORD(q, r, hi, lo, w) \
11742 +    __asm__("div %2" : \
11743 +           "=d" (r), "=a" (q) : \
11744 +           "r" (w), "d" (hi), "a" (lo))
11745 +#else
11746 +#define DIVMOD_WORD(q, r, hi, lo, w) do { \
11747 +    BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \
11748 +    q = n / w; \
11749 +    r = n % w; \
11750 +} while (0)
11751 +#endif
11752 +
11753 +//    q = n / w;
11754 +//    r = n % w;
11755 +
11756 +#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8)
11757 +
11758 +#define BIGNUM_INTERNAL
11759 +
11760 +static Bignum newbn(void *mem_ctx, int length)
11761 +{
11762 +    Bignum b = snewn(mem_ctx, length + 1, BignumInt);
11763 +    //if (!b)
11764 +    //abort();                /* FIXME */
11765 +    DWC_MEMSET(b, 0, (length + 1) * sizeof(*b));
11766 +    b[0] = length;
11767 +    return b;
11768 +}
11769 +
11770 +void freebn(void *mem_ctx, Bignum b)
11771 +{
11772 +    /*
11773 +     * Burn the evidence, just in case.
11774 +     */
11775 +    DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1));
11776 +    sfree(mem_ctx, b);
11777 +}
11778 +
11779 +/*
11780 + * Compute c = a * b.
11781 + * Input is in the first len words of a and b.
11782 + * Result is returned in the first 2*len words of c.
11783 + */
11784 +static void internal_mul(BignumInt *a, BignumInt *b,
11785 +                        BignumInt *c, int len)
11786 +{
11787 +    int i, j;
11788 +    BignumDblInt t;
11789 +
11790 +    for (j = 0; j < 2 * len; j++)
11791 +       c[j] = 0;
11792 +
11793 +    for (i = len - 1; i >= 0; i--) {
11794 +       t = 0;
11795 +       for (j = len - 1; j >= 0; j--) {
11796 +           t += MUL_WORD(a[i], (BignumDblInt) b[j]);
11797 +           t += (BignumDblInt) c[i + j + 1];
11798 +           c[i + j + 1] = (BignumInt) t;
11799 +           t = t >> BIGNUM_INT_BITS;
11800 +       }
11801 +       c[i] = (BignumInt) t;
11802 +    }
11803 +}
11804 +
11805 +static void internal_add_shifted(BignumInt *number,
11806 +                                unsigned n, int shift)
11807 +{
11808 +    int word = 1 + (shift / BIGNUM_INT_BITS);
11809 +    int bshift = shift % BIGNUM_INT_BITS;
11810 +    BignumDblInt addend;
11811 +
11812 +    addend = (BignumDblInt)n << bshift;
11813 +
11814 +    while (addend) {
11815 +       addend += number[word];
11816 +       number[word] = (BignumInt) addend & BIGNUM_INT_MASK;
11817 +       addend >>= BIGNUM_INT_BITS;
11818 +       word++;
11819 +    }
11820 +}
11821 +
11822 +/*
11823 + * Compute a = a % m.
11824 + * Input in first alen words of a and first mlen words of m.
11825 + * Output in first alen words of a
11826 + * (of which first alen-mlen words will be zero).
11827 + * The MSW of m MUST have its high bit set.
11828 + * Quotient is accumulated in the `quotient' array, which is a Bignum
11829 + * rather than the internal bigendian format. Quotient parts are shifted
11830 + * left by `qshift' before adding into quot.
11831 + */
11832 +static void internal_mod(BignumInt *a, int alen,
11833 +                        BignumInt *m, int mlen,
11834 +                        BignumInt *quot, int qshift)
11835 +{
11836 +    BignumInt m0, m1;
11837 +    unsigned int h;
11838 +    int i, k;
11839 +
11840 +    m0 = m[0];
11841 +    if (mlen > 1)
11842 +       m1 = m[1];
11843 +    else
11844 +       m1 = 0;
11845 +
11846 +    for (i = 0; i <= alen - mlen; i++) {
11847 +       BignumDblInt t;
11848 +       unsigned int q, r, c, ai1;
11849 +
11850 +       if (i == 0) {
11851 +           h = 0;
11852 +       } else {
11853 +           h = a[i - 1];
11854 +           a[i - 1] = 0;
11855 +       }
11856 +
11857 +       if (i == alen - 1)
11858 +           ai1 = 0;
11859 +       else
11860 +           ai1 = a[i + 1];
11861 +
11862 +       /* Find q = h:a[i] / m0 */
11863 +       if (h >= m0) {
11864 +           /*
11865 +            * Special case.
11866 +            *
11867 +            * To illustrate it, suppose a BignumInt is 8 bits, and
11868 +            * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then
11869 +            * our initial division will be 0xA123 / 0xA1, which
11870 +            * will give a quotient of 0x100 and a divide overflow.
11871 +            * However, the invariants in this division algorithm
11872 +            * are not violated, since the full number A1:23:... is
11873 +            * _less_ than the quotient prefix A1:B2:... and so the
11874 +            * following correction loop would have sorted it out.
11875 +            *
11876 +            * In this situation we set q to be the largest
11877 +            * quotient we _can_ stomach (0xFF, of course).
11878 +            */
11879 +           q = BIGNUM_INT_MASK;
11880 +       } else {
11881 +           /* Macro doesn't want an array subscript expression passed
11882 +            * into it (see definition), so use a temporary. */
11883 +           BignumInt tmplo = a[i];
11884 +           DIVMOD_WORD(q, r, h, tmplo, m0);
11885 +
11886 +           /* Refine our estimate of q by looking at
11887 +            h:a[i]:a[i+1] / m0:m1 */
11888 +           t = MUL_WORD(m1, q);
11889 +           if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) {
11890 +               q--;
11891 +               t -= m1;
11892 +               r = (r + m0) & BIGNUM_INT_MASK;     /* overflow? */
11893 +               if (r >= (BignumDblInt) m0 &&
11894 +                   t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--;
11895 +           }
11896 +       }
11897 +
11898 +       /* Subtract q * m from a[i...] */
11899 +       c = 0;
11900 +       for (k = mlen - 1; k >= 0; k--) {
11901 +           t = MUL_WORD(q, m[k]);
11902 +           t += c;
11903 +           c = (unsigned)(t >> BIGNUM_INT_BITS);
11904 +           if ((BignumInt) t > a[i + k])
11905 +               c++;
11906 +           a[i + k] -= (BignumInt) t;
11907 +       }
11908 +
11909 +       /* Add back m in case of borrow */
11910 +       if (c != h) {
11911 +           t = 0;
11912 +           for (k = mlen - 1; k >= 0; k--) {
11913 +               t += m[k];
11914 +               t += a[i + k];
11915 +               a[i + k] = (BignumInt) t;
11916 +               t = t >> BIGNUM_INT_BITS;
11917 +           }
11918 +           q--;
11919 +       }
11920 +       if (quot)
11921 +           internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i));
11922 +    }
11923 +}
11924 +
11925 +/*
11926 + * Compute p % mod.
11927 + * The most significant word of mod MUST be non-zero.
11928 + * We assume that the result array is the same size as the mod array.
11929 + * We optionally write out a quotient if `quotient' is non-NULL.
11930 + * We can avoid writing out the result if `result' is NULL.
11931 + */
11932 +void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient)
11933 +{
11934 +    BignumInt *n, *m;
11935 +    int mshift;
11936 +    int plen, mlen, i, j;
11937 +
11938 +    /* Allocate m of size mlen, copy mod to m */
11939 +    /* We use big endian internally */
11940 +    mlen = mod[0];
11941 +    m = snewn(mem_ctx, mlen, BignumInt);
11942 +    //if (!m)
11943 +    //abort();                /* FIXME */
11944 +    for (j = 0; j < mlen; j++)
11945 +       m[j] = mod[mod[0] - j];
11946 +
11947 +    /* Shift m left to make msb bit set */
11948 +    for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++)
11949 +       if ((m[0] << mshift) & BIGNUM_TOP_BIT)
11950 +           break;
11951 +    if (mshift) {
11952 +       for (i = 0; i < mlen - 1; i++)
11953 +           m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift));
11954 +       m[mlen - 1] = m[mlen - 1] << mshift;
11955 +    }
11956 +
11957 +    plen = p[0];
11958 +    /* Ensure plen > mlen */
11959 +    if (plen <= mlen)
11960 +       plen = mlen + 1;
11961 +
11962 +    /* Allocate n of size plen, copy p to n */
11963 +    n = snewn(mem_ctx, plen, BignumInt);
11964 +    //if (!n)
11965 +    //abort();                /* FIXME */
11966 +    for (j = 0; j < plen; j++)
11967 +       n[j] = 0;
11968 +    for (j = 1; j <= (int)p[0]; j++)
11969 +       n[plen - j] = p[j];
11970 +
11971 +    /* Main computation */
11972 +    internal_mod(n, plen, m, mlen, quotient, mshift);
11973 +
11974 +    /* Fixup result in case the modulus was shifted */
11975 +    if (mshift) {
11976 +       for (i = plen - mlen - 1; i < plen - 1; i++)
11977 +           n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift));
11978 +       n[plen - 1] = n[plen - 1] << mshift;
11979 +       internal_mod(n, plen, m, mlen, quotient, 0);
11980 +       for (i = plen - 1; i >= plen - mlen; i--)
11981 +           n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift));
11982 +    }
11983 +
11984 +    /* Copy result to buffer */
11985 +    if (result) {
11986 +       for (i = 1; i <= (int)result[0]; i++) {
11987 +           int j = plen - i;
11988 +           result[i] = j >= 0 ? n[j] : 0;
11989 +       }
11990 +    }
11991 +
11992 +    /* Free temporary arrays */
11993 +    for (i = 0; i < mlen; i++)
11994 +       m[i] = 0;
11995 +    sfree(mem_ctx, m);
11996 +    for (i = 0; i < plen; i++)
11997 +       n[i] = 0;
11998 +    sfree(mem_ctx, n);
11999 +}
12000 +
12001 +/*
12002 + * Simple remainder.
12003 + */
12004 +Bignum bigmod(void *mem_ctx, Bignum a, Bignum b)
12005 +{
12006 +    Bignum r = newbn(mem_ctx, b[0]);
12007 +    bigdivmod(mem_ctx, a, b, r, NULL);
12008 +    return r;
12009 +}
12010 +
12011 +/*
12012 + * Compute (base ^ exp) % mod.
12013 + */
12014 +Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod)
12015 +{
12016 +    BignumInt *a, *b, *n, *m;
12017 +    int mshift;
12018 +    int mlen, i, j;
12019 +    Bignum base, result;
12020 +
12021 +    /*
12022 +     * The most significant word of mod needs to be non-zero. It
12023 +     * should already be, but let's make sure.
12024 +     */
12025 +    //assert(mod[mod[0]] != 0);
12026 +
12027 +    /*
12028 +     * Make sure the base is smaller than the modulus, by reducing
12029 +     * it modulo the modulus if not.
12030 +     */
12031 +    base = bigmod(mem_ctx, base_in, mod);
12032 +
12033 +    /* Allocate m of size mlen, copy mod to m */
12034 +    /* We use big endian internally */
12035 +    mlen = mod[0];
12036 +    m = snewn(mem_ctx, mlen, BignumInt);
12037 +    //if (!m)
12038 +    //abort();                /* FIXME */
12039 +    for (j = 0; j < mlen; j++)
12040 +       m[j] = mod[mod[0] - j];
12041 +
12042 +    /* Shift m left to make msb bit set */
12043 +    for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++)
12044 +       if ((m[0] << mshift) & BIGNUM_TOP_BIT)
12045 +           break;
12046 +    if (mshift) {
12047 +       for (i = 0; i < mlen - 1; i++)
12048 +           m[i] =
12049 +               (m[i] << mshift) | (m[i + 1] >>
12050 +                                   (BIGNUM_INT_BITS - mshift));
12051 +       m[mlen - 1] = m[mlen - 1] << mshift;
12052 +    }
12053 +
12054 +    /* Allocate n of size mlen, copy base to n */
12055 +    n = snewn(mem_ctx, mlen, BignumInt);
12056 +    //if (!n)
12057 +    //abort();                /* FIXME */
12058 +    i = mlen - base[0];
12059 +    for (j = 0; j < i; j++)
12060 +       n[j] = 0;
12061 +    for (j = 0; j < base[0]; j++)
12062 +       n[i + j] = base[base[0] - j];
12063 +
12064 +    /* Allocate a and b of size 2*mlen. Set a = 1 */
12065 +    a = snewn(mem_ctx, 2 * mlen, BignumInt);
12066 +    //if (!a)
12067 +    //abort();                /* FIXME */
12068 +    b = snewn(mem_ctx, 2 * mlen, BignumInt);
12069 +    //if (!b)
12070 +    //abort();                /* FIXME */
12071 +    for (i = 0; i < 2 * mlen; i++)
12072 +       a[i] = 0;
12073 +    a[2 * mlen - 1] = 1;
12074 +
12075 +    /* Skip leading zero bits of exp. */
12076 +    i = 0;
12077 +    j = BIGNUM_INT_BITS - 1;
12078 +    while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) {
12079 +       j--;
12080 +       if (j < 0) {
12081 +           i++;
12082 +           j = BIGNUM_INT_BITS - 1;
12083 +       }
12084 +    }
12085 +
12086 +    /* Main computation */
12087 +    while (i < exp[0]) {
12088 +       while (j >= 0) {
12089 +           internal_mul(a + mlen, a + mlen, b, mlen);
12090 +           internal_mod(b, mlen * 2, m, mlen, NULL, 0);
12091 +           if ((exp[exp[0] - i] & (1 << j)) != 0) {
12092 +               internal_mul(b + mlen, n, a, mlen);
12093 +               internal_mod(a, mlen * 2, m, mlen, NULL, 0);
12094 +           } else {
12095 +               BignumInt *t;
12096 +               t = a;
12097 +               a = b;
12098 +               b = t;
12099 +           }
12100 +           j--;
12101 +       }
12102 +       i++;
12103 +       j = BIGNUM_INT_BITS - 1;
12104 +    }
12105 +
12106 +    /* Fixup result in case the modulus was shifted */
12107 +    if (mshift) {
12108 +       for (i = mlen - 1; i < 2 * mlen - 1; i++)
12109 +           a[i] =
12110 +               (a[i] << mshift) | (a[i + 1] >>
12111 +                                   (BIGNUM_INT_BITS - mshift));
12112 +       a[2 * mlen - 1] = a[2 * mlen - 1] << mshift;
12113 +       internal_mod(a, mlen * 2, m, mlen, NULL, 0);
12114 +       for (i = 2 * mlen - 1; i >= mlen; i--)
12115 +           a[i] =
12116 +               (a[i] >> mshift) | (a[i - 1] <<
12117 +                                   (BIGNUM_INT_BITS - mshift));
12118 +    }
12119 +
12120 +    /* Copy result to buffer */
12121 +    result = newbn(mem_ctx, mod[0]);
12122 +    for (i = 0; i < mlen; i++)
12123 +       result[result[0] - i] = a[i + mlen];
12124 +    while (result[0] > 1 && result[result[0]] == 0)
12125 +       result[0]--;
12126 +
12127 +    /* Free temporary arrays */
12128 +    for (i = 0; i < 2 * mlen; i++)
12129 +       a[i] = 0;
12130 +    sfree(mem_ctx, a);
12131 +    for (i = 0; i < 2 * mlen; i++)
12132 +       b[i] = 0;
12133 +    sfree(mem_ctx, b);
12134 +    for (i = 0; i < mlen; i++)
12135 +       m[i] = 0;
12136 +    sfree(mem_ctx, m);
12137 +    for (i = 0; i < mlen; i++)
12138 +       n[i] = 0;
12139 +    sfree(mem_ctx, n);
12140 +
12141 +    freebn(mem_ctx, base);
12142 +
12143 +    return result;
12144 +}
12145 +
12146 +
12147 +#ifdef UNITTEST
12148 +
12149 +static __u32 dh_p[] = {
12150 +       96,
12151 +       0xFFFFFFFF,
12152 +       0xFFFFFFFF,
12153 +       0xA93AD2CA,
12154 +       0x4B82D120,
12155 +       0xE0FD108E,
12156 +       0x43DB5BFC,
12157 +       0x74E5AB31,
12158 +       0x08E24FA0,
12159 +       0xBAD946E2,
12160 +       0x770988C0,
12161 +       0x7A615D6C,
12162 +       0xBBE11757,
12163 +       0x177B200C,
12164 +       0x521F2B18,
12165 +       0x3EC86A64,
12166 +       0xD8760273,
12167 +       0xD98A0864,
12168 +       0xF12FFA06,
12169 +       0x1AD2EE6B,
12170 +       0xCEE3D226,
12171 +       0x4A25619D,
12172 +       0x1E8C94E0,
12173 +       0xDB0933D7,
12174 +       0xABF5AE8C,
12175 +       0xA6E1E4C7,
12176 +       0xB3970F85,
12177 +       0x5D060C7D,
12178 +       0x8AEA7157,
12179 +       0x58DBEF0A,
12180 +       0xECFB8504,
12181 +       0xDF1CBA64,
12182 +       0xA85521AB,
12183 +       0x04507A33,
12184 +       0xAD33170D,
12185 +       0x8AAAC42D,
12186 +       0x15728E5A,
12187 +       0x98FA0510,
12188 +       0x15D22618,
12189 +       0xEA956AE5,
12190 +       0x3995497C,
12191 +       0x95581718,
12192 +       0xDE2BCBF6,
12193 +       0x6F4C52C9,
12194 +       0xB5C55DF0,
12195 +       0xEC07A28F,
12196 +       0x9B2783A2,
12197 +       0x180E8603,
12198 +       0xE39E772C,
12199 +       0x2E36CE3B,
12200 +       0x32905E46,
12201 +       0xCA18217C,
12202 +       0xF1746C08,
12203 +       0x4ABC9804,
12204 +       0x670C354E,
12205 +       0x7096966D,
12206 +       0x9ED52907,
12207 +       0x208552BB,
12208 +       0x1C62F356,
12209 +       0xDCA3AD96,
12210 +       0x83655D23,
12211 +       0xFD24CF5F,
12212 +       0x69163FA8,
12213 +       0x1C55D39A,
12214 +       0x98DA4836,
12215 +       0xA163BF05,
12216 +       0xC2007CB8,
12217 +       0xECE45B3D,
12218 +       0x49286651,
12219 +       0x7C4B1FE6,
12220 +       0xAE9F2411,
12221 +       0x5A899FA5,
12222 +       0xEE386BFB,
12223 +       0xF406B7ED,
12224 +       0x0BFF5CB6,
12225 +       0xA637ED6B,
12226 +       0xF44C42E9,
12227 +       0x625E7EC6,
12228 +       0xE485B576,
12229 +       0x6D51C245,
12230 +       0x4FE1356D,
12231 +       0xF25F1437,
12232 +       0x302B0A6D,
12233 +       0xCD3A431B,
12234 +       0xEF9519B3,
12235 +       0x8E3404DD,
12236 +       0x514A0879,
12237 +       0x3B139B22,
12238 +       0x020BBEA6,
12239 +       0x8A67CC74,
12240 +       0x29024E08,
12241 +       0x80DC1CD1,
12242 +       0xC4C6628B,
12243 +       0x2168C234,
12244 +       0xC90FDAA2,
12245 +       0xFFFFFFFF,
12246 +       0xFFFFFFFF,
12247 +};
12248 +
12249 +static __u32 dh_a[] = {
12250 +       8,
12251 +       0xdf367516,
12252 +       0x86459caa,
12253 +       0xe2d459a4,
12254 +       0xd910dae0,
12255 +       0x8a8b5e37,
12256 +       0x67ab31c6,
12257 +       0xf0b55ea9,
12258 +       0x440051d6,
12259 +};
12260 +
12261 +static __u32 dh_b[] = {
12262 +       8,
12263 +       0xded92656,
12264 +       0xe07a048a,
12265 +       0x6fa452cd,
12266 +       0x2df89d30,
12267 +       0xc75f1b0f,
12268 +       0x8ce3578f,
12269 +       0x7980a324,
12270 +       0x5daec786,
12271 +};
12272 +
12273 +static __u32 dh_g[] = {
12274 +       1,
12275 +       2,
12276 +};
12277 +
12278 +int main(void)
12279 +{
12280 +       int i;
12281 +       __u32 *k;
12282 +       k = dwc_modpow(NULL, dh_g, dh_a, dh_p);
12283 +
12284 +       printf("\n\n");
12285 +       for (i=0; i<k[0]; i++) {
12286 +               __u32 word32 = k[k[0] - i];
12287 +               __u16 l = word32 & 0xffff;
12288 +               __u16 m = (word32 & 0xffff0000) >> 16;
12289 +               printf("%04x %04x ", m, l);
12290 +               if (!((i + 1)%13)) printf("\n");
12291 +       }
12292 +       printf("\n\n");
12293 +
12294 +       if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) {
12295 +               printf("PASS\n\n");
12296 +       }
12297 +       else {
12298 +               printf("FAIL\n\n");
12299 +       }
12300 +
12301 +}
12302 +
12303 +#endif /* UNITTEST */
12304 +
12305 +#endif /* CONFIG_MACH_IPMATE */
12306 +
12307 +#endif /*DWC_CRYPTOLIB */
12308 --- /dev/null
12309 +++ b/drivers/usb/host/dwc_common_port/dwc_modpow.h
12310 @@ -0,0 +1,34 @@
12311 +/*
12312 + * dwc_modpow.h
12313 + * See dwc_modpow.c for license and changes
12314 + */
12315 +#ifndef _DWC_MODPOW_H
12316 +#define _DWC_MODPOW_H
12317 +
12318 +#ifdef __cplusplus
12319 +extern "C" {
12320 +#endif
12321 +
12322 +#include "dwc_os.h"
12323 +
12324 +/** @file
12325 + *
12326 + * This file defines the module exponentiation function which is only used
12327 + * internally by the DWC UWB modules for calculation of PKs during numeric
12328 + * association.  The routine is taken from the PUTTY, an open source terminal
12329 + * emulator.  The PUTTY License is preserved in the dwc_modpow.c file.
12330 + *
12331 + */
12332 +
12333 +typedef uint32_t BignumInt;
12334 +typedef uint64_t BignumDblInt;
12335 +typedef BignumInt *Bignum;
12336 +
12337 +/* Compute modular exponentiaion */
12338 +extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod);
12339 +
12340 +#ifdef __cplusplus
12341 +}
12342 +#endif
12343 +
12344 +#endif /* _LINUX_BIGNUM_H */
12345 --- /dev/null
12346 +++ b/drivers/usb/host/dwc_common_port/dwc_notifier.c
12347 @@ -0,0 +1,319 @@
12348 +#ifdef DWC_NOTIFYLIB
12349 +
12350 +#include "dwc_notifier.h"
12351 +#include "dwc_list.h"
12352 +
12353 +typedef struct dwc_observer {
12354 +       void *observer;
12355 +       dwc_notifier_callback_t callback;
12356 +       void *data;
12357 +       char *notification;
12358 +       DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry;
12359 +} observer_t;
12360 +
12361 +DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer);
12362 +
12363 +typedef struct dwc_notifier {
12364 +       void *mem_ctx;
12365 +       void *object;
12366 +       struct observer_queue observers;
12367 +       DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry;
12368 +} notifier_t;
12369 +
12370 +DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier);
12371 +
12372 +typedef struct manager {
12373 +       void *mem_ctx;
12374 +       void *wkq_ctx;
12375 +       dwc_workq_t *wq;
12376 +//     dwc_mutex_t *mutex;
12377 +       struct notifier_queue notifiers;
12378 +} manager_t;
12379 +
12380 +static manager_t *manager = NULL;
12381 +
12382 +static int create_manager(void *mem_ctx, void *wkq_ctx)
12383 +{
12384 +       manager = dwc_alloc(mem_ctx, sizeof(manager_t));
12385 +       if (!manager) {
12386 +               return -DWC_E_NO_MEMORY;
12387 +       }
12388 +
12389 +       DWC_CIRCLEQ_INIT(&manager->notifiers);
12390 +
12391 +       manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ");
12392 +       if (!manager->wq) {
12393 +               return -DWC_E_NO_MEMORY;
12394 +       }
12395 +
12396 +       return 0;
12397 +}
12398 +
12399 +static void free_manager(void)
12400 +{
12401 +       dwc_workq_free(manager->wq);
12402 +
12403 +       /* All notifiers must have unregistered themselves before this module
12404 +        * can be removed.  Hitting this assertion indicates a programmer
12405 +        * error. */
12406 +       DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers),
12407 +                  "Notification manager being freed before all notifiers have been removed");
12408 +       dwc_free(manager->mem_ctx, manager);
12409 +}
12410 +
12411 +#ifdef DEBUG
12412 +static void dump_manager(void)
12413 +{
12414 +       notifier_t *n;
12415 +       observer_t *o;
12416 +
12417 +       DWC_ASSERT(manager, "Notification manager not found");
12418 +
12419 +       DWC_DEBUG("List of all notifiers and observers:\n");
12420 +       DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
12421 +               DWC_DEBUG("Notifier %p has observers:\n", n->object);
12422 +               DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) {
12423 +                       DWC_DEBUG("    %p watching %s\n", o->observer, o->notification);
12424 +               }
12425 +       }
12426 +}
12427 +#else
12428 +#define dump_manager(...)
12429 +#endif
12430 +
12431 +static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification,
12432 +                                 dwc_notifier_callback_t callback, void *data)
12433 +{
12434 +       observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t));
12435 +
12436 +       if (!new_observer) {
12437 +               return NULL;
12438 +       }
12439 +
12440 +       DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry);
12441 +       new_observer->observer = observer;
12442 +       new_observer->notification = notification;
12443 +       new_observer->callback = callback;
12444 +       new_observer->data = data;
12445 +       return new_observer;
12446 +}
12447 +
12448 +static void free_observer(void *mem_ctx, observer_t *observer)
12449 +{
12450 +       dwc_free(mem_ctx, observer);
12451 +}
12452 +
12453 +static notifier_t *alloc_notifier(void *mem_ctx, void *object)
12454 +{
12455 +       notifier_t *notifier;
12456 +
12457 +       if (!object) {
12458 +               return NULL;
12459 +       }
12460 +
12461 +       notifier = dwc_alloc(mem_ctx, sizeof(notifier_t));
12462 +       if (!notifier) {
12463 +               return NULL;
12464 +       }
12465 +
12466 +       DWC_CIRCLEQ_INIT(&notifier->observers);
12467 +       DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry);
12468 +
12469 +       notifier->mem_ctx = mem_ctx;
12470 +       notifier->object = object;
12471 +       return notifier;
12472 +}
12473 +
12474 +static void free_notifier(notifier_t *notifier)
12475 +{
12476 +       observer_t *observer;
12477 +
12478 +       DWC_CIRCLEQ_FOREACH(observer, &notifier->observers, list_entry) {
12479 +               free_observer(notifier->mem_ctx, observer);
12480 +       }
12481 +
12482 +       dwc_free(notifier->mem_ctx, notifier);
12483 +}
12484 +
12485 +static notifier_t *find_notifier(void *object)
12486 +{
12487 +       notifier_t *notifier;
12488 +
12489 +       DWC_ASSERT(manager, "Notification manager not found");
12490 +
12491 +       if (!object) {
12492 +               return NULL;
12493 +       }
12494 +
12495 +       DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) {
12496 +               if (notifier->object == object) {
12497 +                       return notifier;
12498 +               }
12499 +       }
12500 +
12501 +       return NULL;
12502 +}
12503 +
12504 +int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx)
12505 +{
12506 +       return create_manager(mem_ctx, wkq_ctx);
12507 +}
12508 +
12509 +void dwc_free_notification_manager(void)
12510 +{
12511 +       free_manager();
12512 +}
12513 +
12514 +dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object)
12515 +{
12516 +       notifier_t *notifier;
12517 +
12518 +       DWC_ASSERT(manager, "Notification manager not found");
12519 +
12520 +       notifier = find_notifier(object);
12521 +       if (notifier) {
12522 +               DWC_ERROR("Notifier %p is already registered\n", object);
12523 +               return NULL;
12524 +       }
12525 +
12526 +       notifier = alloc_notifier(mem_ctx, object);
12527 +       if (!notifier) {
12528 +               return NULL;
12529 +       }
12530 +
12531 +       DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry);
12532 +
12533 +       DWC_INFO("Notifier %p registered", object);
12534 +       dump_manager();
12535 +
12536 +       return notifier;
12537 +}
12538 +
12539 +void dwc_unregister_notifier(dwc_notifier_t *notifier)
12540 +{
12541 +       DWC_ASSERT(manager, "Notification manager not found");
12542 +
12543 +       if (!DWC_CIRCLEQ_EMPTY(&notifier->observers)) {
12544 +               observer_t *o;
12545 +
12546 +               DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object);
12547 +               DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
12548 +                       DWC_DEBUGC("    %p watching %s\n", o->observer, o->notification);
12549 +               }
12550 +
12551 +               DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&notifier->observers),
12552 +                          "Notifier %p has active observers when removing", notifier);
12553 +       }
12554 +
12555 +       DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry);
12556 +       free_notifier(notifier);
12557 +
12558 +       DWC_INFO("Notifier unregistered");
12559 +       dump_manager();
12560 +}
12561 +
12562 +/* Add an observer to observe the notifier for a particular state, event, or notification. */
12563 +int dwc_add_observer(void *observer, void *object, char *notification,
12564 +                    dwc_notifier_callback_t callback, void *data)
12565 +{
12566 +       notifier_t *notifier = find_notifier(object);
12567 +       observer_t *new_observer;
12568 +
12569 +       if (!notifier) {
12570 +               DWC_ERROR("Notifier %p is not found when adding observer\n", object);
12571 +               return -DWC_E_INVALID;
12572 +       }
12573 +
12574 +       new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data);
12575 +       if (!new_observer) {
12576 +               return -DWC_E_NO_MEMORY;
12577 +       }
12578 +
12579 +       DWC_CIRCLEQ_INSERT_TAIL(&notifier->observers, new_observer, list_entry);
12580 +
12581 +       DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p",
12582 +                observer, object, notification, callback, data);
12583 +
12584 +       dump_manager();
12585 +       return 0;
12586 +}
12587 +
12588 +int dwc_remove_observer(void *observer)
12589 +{
12590 +       notifier_t *n;
12591 +
12592 +       DWC_ASSERT(manager, "Notification manager not found");
12593 +
12594 +       DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) {
12595 +               observer_t *o;
12596 +               observer_t *o2;
12597 +
12598 +               DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) {
12599 +                       if (o->observer == observer) {
12600 +                               DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry);
12601 +                               DWC_INFO("Removing observer %p from notifier %p watching notification %s:",
12602 +                                        o->observer, n->object, o->notification);
12603 +                               free_observer(n->mem_ctx, o);
12604 +                       }
12605 +               }
12606 +       }
12607 +
12608 +       dump_manager();
12609 +       return 0;
12610 +}
12611 +
12612 +typedef struct callback_data {
12613 +       void *mem_ctx;
12614 +       dwc_notifier_callback_t cb;
12615 +       void *observer;
12616 +       void *data;
12617 +       void *object;
12618 +       char *notification;
12619 +       void *notification_data;
12620 +} cb_data_t;
12621 +
12622 +static void cb_task(void *data)
12623 +{
12624 +       cb_data_t *cb = (cb_data_t *)data;
12625 +
12626 +       cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data);
12627 +       dwc_free(cb->mem_ctx, cb);
12628 +}
12629 +
12630 +void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data)
12631 +{
12632 +       observer_t *o;
12633 +
12634 +       DWC_ASSERT(manager, "Notification manager not found");
12635 +
12636 +       DWC_CIRCLEQ_FOREACH(o, &notifier->observers, list_entry) {
12637 +               int len = DWC_STRLEN(notification);
12638 +
12639 +               if (DWC_STRLEN(o->notification) != len) {
12640 +                       continue;
12641 +               }
12642 +
12643 +               if (DWC_STRNCMP(o->notification, notification, len) == 0) {
12644 +                       cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t));
12645 +
12646 +                       if (!cb_data) {
12647 +                               DWC_ERROR("Failed to allocate callback data\n");
12648 +                               return;
12649 +                       }
12650 +
12651 +                       cb_data->mem_ctx = notifier->mem_ctx;
12652 +                       cb_data->cb = o->callback;
12653 +                       cb_data->observer = o->observer;
12654 +                       cb_data->data = o->data;
12655 +                       cb_data->object = notifier->object;
12656 +                       cb_data->notification = notification;
12657 +                       cb_data->notification_data = notification_data;
12658 +                       DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification);
12659 +                       DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data,
12660 +                                          "Notify callback from %p for Notification %s, to observer %p",
12661 +                                          cb_data->object, notification, cb_data->observer);
12662 +               }
12663 +       }
12664 +}
12665 +
12666 +#endif /* DWC_NOTIFYLIB */
12667 --- /dev/null
12668 +++ b/drivers/usb/host/dwc_common_port/dwc_notifier.h
12669 @@ -0,0 +1,122 @@
12670 +
12671 +#ifndef __DWC_NOTIFIER_H__
12672 +#define __DWC_NOTIFIER_H__
12673 +
12674 +#ifdef __cplusplus
12675 +extern "C" {
12676 +#endif
12677 +
12678 +#include "dwc_os.h"
12679 +
12680 +/** @file
12681 + *
12682 + * A simple implementation of the Observer pattern.  Any "module" can
12683 + * register as an observer or notifier.  The notion of "module" is abstract and
12684 + * can mean anything used to identify either an observer or notifier.  Usually
12685 + * it will be a pointer to a data structure which contains some state, ie an
12686 + * object.
12687 + *
12688 + * Before any notifiers can be added, the global notification manager must be
12689 + * brought up with dwc_alloc_notification_manager().
12690 + * dwc_free_notification_manager() will bring it down and free all resources.
12691 + * These would typically be called upon module load and unload.  The
12692 + * notification manager is a single global instance that handles all registered
12693 + * observable modules and observers so this should be done only once.
12694 + *
12695 + * A module can be observable by using Notifications to publicize some general
12696 + * information about it's state or operation.  It does not care who listens, or
12697 + * even if anyone listens, or what they do with the information.  The observable
12698 + * modules do not need to know any information about it's observers or their
12699 + * interface, or their state or data.
12700 + *
12701 + * Any module can register to emit Notifications.  It should publish a list of
12702 + * notifications that it can emit and their behavior, such as when they will get
12703 + * triggered, and what information will be provided to the observer.  Then it
12704 + * should register itself as an observable module. See dwc_register_notifier().
12705 + *
12706 + * Any module can observe any observable, registered module, provided it has a
12707 + * handle to the other module and knows what notifications to observe.  See
12708 + * dwc_add_observer().
12709 + *
12710 + * A function of type dwc_notifier_callback_t is called whenever a notification
12711 + * is triggered with one or more observers observing it.  This function is
12712 + * called in it's own process so it may sleep or block if needed.  It is
12713 + * guaranteed to be called sometime after the notification has occurred and will
12714 + * be called once per each time the notification is triggered.  It will NOT be
12715 + * called in the same process context used to trigger the notification.
12716 + *
12717 + * @section Limitiations
12718 + *
12719 + * Keep in mind that Notifications that can be triggered in rapid sucession may
12720 + * schedule too many processes too handle.  Be aware of this limitation when
12721 + * designing to use notifications, and only add notifications for appropriate
12722 + * observable information.
12723 + *
12724 + * Also Notification callbacks are not synchronous.  If you need to synchronize
12725 + * the behavior between module/observer you must use other means.  And perhaps
12726 + * that will mean Notifications are not the proper solution.
12727 + */
12728 +
12729 +struct dwc_notifier;
12730 +typedef struct dwc_notifier dwc_notifier_t;
12731 +
12732 +/** The callback function must be of this type.
12733 + *
12734 + * @param object This is the object that is being observed.
12735 + * @param notification This is the notification that was triggered.
12736 + * @param observer This is the observer
12737 + * @param notification_data This is notification-specific data that the notifier
12738 + * has included in this notification.  The value of this should be published in
12739 + * the documentation of the observable module with the notifications.
12740 + * @param user_data This is any custom data that the observer provided when
12741 + * adding itself as an observer to the notification. */
12742 +typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer,
12743 +                                       void *notification_data, void *user_data);
12744 +
12745 +/** Brings up the notification manager. */
12746 +extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx);
12747 +/** Brings down the notification manager. */
12748 +extern void dwc_free_notification_manager(void);
12749 +
12750 +/** This function registers an observable module.  A dwc_notifier_t object is
12751 + * returned to the observable module.  This is an opaque object that is used by
12752 + * the observable module to trigger notifications.  This object should only be
12753 + * accessible to functions that are authorized to trigger notifications for this
12754 + * module.  Observers do not need this object. */
12755 +extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object);
12756 +
12757 +/** This function unregisters an observable module.  All observers have to be
12758 + * removed prior to unregistration. */
12759 +extern void dwc_unregister_notifier(dwc_notifier_t *notifier);
12760 +
12761 +/** Add a module as an observer to the observable module.  The observable module
12762 + * needs to have previously registered with the notification manager.
12763 + *
12764 + * @param observer The observer module
12765 + * @param object The module to observe
12766 + * @param notification The notification to observe
12767 + * @param callback The callback function to call
12768 + * @param user_data Any additional user data to pass into the callback function */
12769 +extern int dwc_add_observer(void *observer, void *object, char *notification,
12770 +                           dwc_notifier_callback_t callback, void *user_data);
12771 +
12772 +/** Removes the specified observer from all notifications that it is currently
12773 + * observing. */
12774 +extern int dwc_remove_observer(void *observer);
12775 +
12776 +/** This function triggers a Notification.  It should be called by the
12777 + * observable module, or any module or library which the observable module
12778 + * allows to trigger notification on it's behalf.  Such as the dwc_cc_t.
12779 + *
12780 + * dwc_notify is a non-blocking function.  Callbacks are scheduled called in
12781 + * their own process context for each trigger.  Callbacks can be blocking.
12782 + * dwc_notify can be called from interrupt context if needed.
12783 + *
12784 + */
12785 +void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data);
12786 +
12787 +#ifdef __cplusplus
12788 +}
12789 +#endif
12790 +
12791 +#endif /* __DWC_NOTIFIER_H__ */
12792 --- /dev/null
12793 +++ b/drivers/usb/host/dwc_common_port/dwc_os.h
12794 @@ -0,0 +1,1276 @@
12795 +/* =========================================================================
12796 + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $
12797 + * $Revision: #14 $
12798 + * $Date: 2010/11/04 $
12799 + * $Change: 1621695 $
12800 + *
12801 + * Synopsys Portability Library Software and documentation
12802 + * (hereinafter, "Software") is an Unsupported proprietary work of
12803 + * Synopsys, Inc. unless otherwise expressly agreed to in writing
12804 + * between Synopsys and you.
12805 + *
12806 + * The Software IS NOT an item of Licensed Software or Licensed Product
12807 + * under any End User Software License Agreement or Agreement for
12808 + * Licensed Product with Synopsys or any supplement thereto. You are
12809 + * permitted to use and redistribute this Software in source and binary
12810 + * forms, with or without modification, provided that redistributions
12811 + * of source code must retain this notice. You may not view, use,
12812 + * disclose, copy or distribute this file or any information contained
12813 + * herein except pursuant to this license grant from Synopsys. If you
12814 + * do not agree with this notice, including the disclaimer below, then
12815 + * you are not authorized to use the Software.
12816 + *
12817 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
12818 + * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
12819 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
12820 + * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL
12821 + * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
12822 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
12823 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
12824 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
12825 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
12826 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
12827 + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
12828 + * DAMAGE.
12829 + * ========================================================================= */
12830 +#ifndef _DWC_OS_H_
12831 +#define _DWC_OS_H_
12832 +
12833 +#ifdef __cplusplus
12834 +extern "C" {
12835 +#endif
12836 +
12837 +/** @file
12838 + *
12839 + * DWC portability library, low level os-wrapper functions
12840 + *
12841 + */
12842 +
12843 +/* These basic types need to be defined by some OS header file or custom header
12844 + * file for your specific target architecture.
12845 + *
12846 + * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t
12847 + *
12848 + * Any custom or alternate header file must be added and enabled here.
12849 + */
12850 +
12851 +#ifdef DWC_LINUX
12852 +# include <linux/types.h>
12853 +# ifdef CONFIG_DEBUG_MUTEXES
12854 +#  include <linux/mutex.h>
12855 +# endif
12856 +# include <linux/spinlock.h>
12857 +# include <linux/errno.h>
12858 +# include <stdarg.h>
12859 +#endif
12860 +
12861 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
12862 +# include <os_dep.h>
12863 +#endif
12864 +
12865 +
12866 +/** @name Primitive Types and Values */
12867 +
12868 +/** We define a boolean type for consistency.  Can be either YES or NO */
12869 +typedef uint8_t dwc_bool_t;
12870 +#define YES  1
12871 +#define NO   0
12872 +
12873 +#ifdef DWC_LINUX
12874 +
12875 +/** @name Error Codes */
12876 +#define DWC_E_INVALID          EINVAL
12877 +#define DWC_E_NO_MEMORY                ENOMEM
12878 +#define DWC_E_NO_DEVICE                ENODEV
12879 +#define DWC_E_NOT_SUPPORTED    EOPNOTSUPP
12880 +#define DWC_E_TIMEOUT          ETIMEDOUT
12881 +#define DWC_E_BUSY             EBUSY
12882 +#define DWC_E_AGAIN            EAGAIN
12883 +#define DWC_E_RESTART          ERESTART
12884 +#define DWC_E_ABORT            ECONNABORTED
12885 +#define DWC_E_SHUTDOWN         ESHUTDOWN
12886 +#define DWC_E_NO_DATA          ENODATA
12887 +#define DWC_E_DISCONNECT       ECONNRESET
12888 +#define DWC_E_UNKNOWN          EINVAL
12889 +#define DWC_E_NO_STREAM_RES    ENOSR
12890 +#define DWC_E_COMMUNICATION    ECOMM
12891 +#define DWC_E_OVERFLOW         EOVERFLOW
12892 +#define DWC_E_PROTOCOL         EPROTO
12893 +#define DWC_E_IN_PROGRESS      EINPROGRESS
12894 +#define DWC_E_PIPE             EPIPE
12895 +#define DWC_E_IO               EIO
12896 +#define DWC_E_NO_SPACE         ENOSPC
12897 +
12898 +#else
12899 +
12900 +/** @name Error Codes */
12901 +#define DWC_E_INVALID          1001
12902 +#define DWC_E_NO_MEMORY                1002
12903 +#define DWC_E_NO_DEVICE                1003
12904 +#define DWC_E_NOT_SUPPORTED    1004
12905 +#define DWC_E_TIMEOUT          1005
12906 +#define DWC_E_BUSY             1006
12907 +#define DWC_E_AGAIN            1007
12908 +#define DWC_E_RESTART          1008
12909 +#define DWC_E_ABORT            1009
12910 +#define DWC_E_SHUTDOWN         1010
12911 +#define DWC_E_NO_DATA          1011
12912 +#define DWC_E_DISCONNECT       2000
12913 +#define DWC_E_UNKNOWN          3000
12914 +#define DWC_E_NO_STREAM_RES    4001
12915 +#define DWC_E_COMMUNICATION    4002
12916 +#define DWC_E_OVERFLOW         4003
12917 +#define DWC_E_PROTOCOL         4004
12918 +#define DWC_E_IN_PROGRESS      4005
12919 +#define DWC_E_PIPE             4006
12920 +#define DWC_E_IO               4007
12921 +#define DWC_E_NO_SPACE         4008
12922 +
12923 +#endif
12924 +
12925 +
12926 +/** @name Tracing/Logging Functions
12927 + *
12928 + * These function provide the capability to add tracing, debugging, and error
12929 + * messages, as well exceptions as assertions.  The WUDEV uses these
12930 + * extensively.  These could be logged to the main console, the serial port, an
12931 + * internal buffer, etc.  These functions could also be no-op if they are too
12932 + * expensive on your system.  By default undefining the DEBUG macro already
12933 + * no-ops some of these functions. */
12934 +
12935 +/** Returns non-zero if in interrupt context. */
12936 +extern dwc_bool_t DWC_IN_IRQ(void);
12937 +#define dwc_in_irq DWC_IN_IRQ
12938 +
12939 +/** Returns "IRQ" if DWC_IN_IRQ is true. */
12940 +static inline char *dwc_irq(void) {
12941 +       return DWC_IN_IRQ() ? "IRQ" : "";
12942 +}
12943 +
12944 +/** Returns non-zero if in bottom-half context. */
12945 +extern dwc_bool_t DWC_IN_BH(void);
12946 +#define dwc_in_bh DWC_IN_BH
12947 +
12948 +/** Returns "BH" if DWC_IN_BH is true. */
12949 +static inline char *dwc_bh(void) {
12950 +       return DWC_IN_BH() ? "BH" : "";
12951 +}
12952 +
12953 +/**
12954 + * A vprintf() clone.  Just call vprintf if you've got it.
12955 + */
12956 +extern void DWC_VPRINTF(char *format, va_list args);
12957 +#define dwc_vprintf DWC_VPRINTF
12958 +
12959 +/**
12960 + * A vsnprintf() clone.  Just call vprintf if you've got it.
12961 + */
12962 +extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args);
12963 +#define dwc_vsnprintf DWC_VSNPRINTF
12964 +
12965 +/**
12966 + * printf() clone.  Just call printf if you've go it.
12967 + */
12968 +extern void DWC_PRINTF(char *format, ...)
12969 +/* This provides compiler level static checking of the parameters if you're
12970 + * using GCC. */
12971 +#ifdef __GNUC__
12972 +       __attribute__ ((format(printf, 1, 2)));
12973 +#else
12974 +       ;
12975 +#endif
12976 +#define dwc_printf DWC_PRINTF
12977 +
12978 +/**
12979 + * sprintf() clone.  Just call sprintf if you've got it.
12980 + */
12981 +extern int DWC_SPRINTF(char *string, char *format, ...)
12982 +#ifdef __GNUC__
12983 +       __attribute__ ((format(printf, 2, 3)));
12984 +#else
12985 +       ;
12986 +#endif
12987 +#define dwc_sprintf DWC_SPRINTF
12988 +
12989 +/**
12990 + * snprintf() clone.  Just call snprintf if you've got it.
12991 + */
12992 +extern int DWC_SNPRINTF(char *string, int size, char *format, ...)
12993 +#ifdef __GNUC__
12994 +       __attribute__ ((format(printf, 3, 4)));
12995 +#else
12996 +       ;
12997 +#endif
12998 +#define dwc_snprintf DWC_SNPRINTF
12999 +
13000 +/**
13001 + * Prints a WARNING message.  On systems that don't differentiate between
13002 + * warnings and regular log messages, just print it.  Indicates that something
13003 + * may be wrong with the driver.  Works like printf().
13004 + *
13005 + * Use the DWC_WARN macro to call this function.
13006 + */
13007 +extern void __DWC_WARN(char *format, ...)
13008 +#ifdef __GNUC__
13009 +       __attribute__ ((format(printf, 1, 2)));
13010 +#else
13011 +       ;
13012 +#endif
13013 +
13014 +/**
13015 + * Prints an error message.  On systems that don't differentiate between errors
13016 + * and regular log messages, just print it.  Indicates that something went wrong
13017 + * with the driver.  Works like printf().
13018 + *
13019 + * Use the DWC_ERROR macro to call this function.
13020 + */
13021 +extern void __DWC_ERROR(char *format, ...)
13022 +#ifdef __GNUC__
13023 +       __attribute__ ((format(printf, 1, 2)));
13024 +#else
13025 +       ;
13026 +#endif
13027 +
13028 +/**
13029 + * Prints an exception error message and takes some user-defined action such as
13030 + * print out a backtrace or trigger a breakpoint.  Indicates that something went
13031 + * abnormally wrong with the driver such as programmer error, or other
13032 + * exceptional condition.  It should not be ignored so even on systems without
13033 + * printing capability, some action should be taken to notify the developer of
13034 + * it.  Works like printf().
13035 + */
13036 +extern void DWC_EXCEPTION(char *format, ...)
13037 +#ifdef __GNUC__
13038 +       __attribute__ ((format(printf, 1, 2)));
13039 +#else
13040 +       ;
13041 +#endif
13042 +#define dwc_exception DWC_EXCEPTION
13043 +
13044 +#ifndef DWC_OTG_DEBUG_LEV
13045 +#define DWC_OTG_DEBUG_LEV 0
13046 +#endif
13047 +
13048 +#ifdef DEBUG
13049 +/**
13050 + * Prints out a debug message.  Used for logging/trace messages.
13051 + *
13052 + * Use the DWC_DEBUG macro to call this function
13053 + */
13054 +extern void __DWC_DEBUG(char *format, ...)
13055 +#ifdef __GNUC__
13056 +       __attribute__ ((format(printf, 1, 2)));
13057 +#else
13058 +       ;
13059 +#endif
13060 +#else
13061 +#define __DWC_DEBUG printk
13062 +#endif
13063 +
13064 +/**
13065 + * Prints out a Debug message.
13066 + */
13067 +#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \
13068 +                                                __func__, dwc_irq(), ## _args)
13069 +#define dwc_debug DWC_DEBUG
13070 +/**
13071 + * Prints out a Debug message if enabled at compile time.
13072 + */
13073 +#if DWC_OTG_DEBUG_LEV > 0
13074 +#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args )
13075 +#else
13076 +#define DWC_DEBUGC(_format, _args...)
13077 +#endif
13078 +#define dwc_debugc DWC_DEBUGC
13079 +/**
13080 + * Prints out an informative message.
13081 + */
13082 +#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \
13083 +                                              dwc_irq(), ## _args)
13084 +#define dwc_info DWC_INFO
13085 +/**
13086 + * Prints out an informative message if enabled at compile time.
13087 + */
13088 +#if DWC_OTG_DEBUG_LEV > 1
13089 +#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args )
13090 +#else
13091 +#define DWC_INFOC(_format, _args...)
13092 +#endif
13093 +#define dwc_infoc DWC_INFOC
13094 +/**
13095 + * Prints out a warning message.
13096 + */
13097 +#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \
13098 +                                       dwc_irq(), __func__, __LINE__, ## _args)
13099 +#define dwc_warn DWC_WARN
13100 +/**
13101 + * Prints out an error message.
13102 + */
13103 +#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \
13104 +                                       dwc_irq(), __func__, __LINE__, ## _args)
13105 +#define dwc_error DWC_ERROR
13106 +
13107 +#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \
13108 +                                               dwc_irq(), __func__, __LINE__, ## _args)
13109 +#define dwc_proto_error DWC_PROTO_ERROR
13110 +
13111 +#ifdef DEBUG
13112 +/** Prints out a exception error message if the _expr expression fails.  Disabled
13113 + * if DEBUG is not enabled. */
13114 +#define DWC_ASSERT(_expr, _format, _args...) do { \
13115 +       if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \
13116 +                                     __FILE__, __LINE__, ## _args); } \
13117 +       } while (0)
13118 +#else
13119 +#define DWC_ASSERT(_x...)
13120 +#endif
13121 +#define dwc_assert DWC_ASSERT
13122 +
13123 +
13124 +/** @name Byte Ordering
13125 + * The following functions are for conversions between processor's byte ordering
13126 + * and specific ordering you want.
13127 + */
13128 +
13129 +/** Converts 32 bit data in CPU byte ordering to little endian. */
13130 +extern uint32_t DWC_CPU_TO_LE32(uint32_t *p);
13131 +#define dwc_cpu_to_le32 DWC_CPU_TO_LE32
13132 +
13133 +/** Converts 32 bit data in CPU byte orderint to big endian. */
13134 +extern uint32_t DWC_CPU_TO_BE32(uint32_t *p);
13135 +#define dwc_cpu_to_be32 DWC_CPU_TO_BE32
13136 +
13137 +/** Converts 32 bit little endian data to CPU byte ordering. */
13138 +extern uint32_t DWC_LE32_TO_CPU(uint32_t *p);
13139 +#define dwc_le32_to_cpu DWC_LE32_TO_CPU
13140 +
13141 +/** Converts 32 bit big endian data to CPU byte ordering. */
13142 +extern uint32_t DWC_BE32_TO_CPU(uint32_t *p);
13143 +#define dwc_be32_to_cpu DWC_BE32_TO_CPU
13144 +
13145 +/** Converts 16 bit data in CPU byte ordering to little endian. */
13146 +extern uint16_t DWC_CPU_TO_LE16(uint16_t *p);
13147 +#define dwc_cpu_to_le16 DWC_CPU_TO_LE16
13148 +
13149 +/** Converts 16 bit data in CPU byte orderint to big endian. */
13150 +extern uint16_t DWC_CPU_TO_BE16(uint16_t *p);
13151 +#define dwc_cpu_to_be16 DWC_CPU_TO_BE16
13152 +
13153 +/** Converts 16 bit little endian data to CPU byte ordering. */
13154 +extern uint16_t DWC_LE16_TO_CPU(uint16_t *p);
13155 +#define dwc_le16_to_cpu DWC_LE16_TO_CPU
13156 +
13157 +/** Converts 16 bit bi endian data to CPU byte ordering. */
13158 +extern uint16_t DWC_BE16_TO_CPU(uint16_t *p);
13159 +#define dwc_be16_to_cpu DWC_BE16_TO_CPU
13160 +
13161 +
13162 +/** @name Register Read/Write
13163 + *
13164 + * The following six functions should be implemented to read/write registers of
13165 + * 32-bit and 64-bit sizes.  All modules use this to read/write register values.
13166 + * The reg value is a pointer to the register calculated from the void *base
13167 + * variable passed into the driver when it is started.  */
13168 +
13169 +#ifdef DWC_LINUX
13170 +/* Linux doesn't need any extra parameters for register read/write, so we
13171 + * just throw away the IO context parameter.
13172 + */
13173 +/** Reads the content of a 32-bit register. */
13174 +extern uint32_t DWC_READ_REG32(uint32_t volatile *reg);
13175 +#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_)
13176 +
13177 +/** Reads the content of a 64-bit register. */
13178 +extern uint64_t DWC_READ_REG64(uint64_t volatile *reg);
13179 +#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_)
13180 +
13181 +/** Writes to a 32-bit register. */
13182 +extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value);
13183 +#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_)
13184 +
13185 +/** Writes to a 64-bit register. */
13186 +extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value);
13187 +#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_)
13188 +
13189 +/**
13190 + * Modify bit values in a register.  Using the
13191 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
13192 + */
13193 +extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
13194 +#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_)
13195 +extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
13196 +#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_)
13197 +
13198 +#endif /* DWC_LINUX */
13199 +
13200 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13201 +typedef struct dwc_ioctx {
13202 +       struct device *dev;
13203 +       bus_space_tag_t iot;
13204 +       bus_space_handle_t ioh;
13205 +} dwc_ioctx_t;
13206 +
13207 +/** BSD needs two extra parameters for register read/write, so we pass
13208 + * them in using the IO context parameter.
13209 + */
13210 +/** Reads the content of a 32-bit register. */
13211 +extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg);
13212 +#define dwc_read_reg32 DWC_READ_REG32
13213 +
13214 +/** Reads the content of a 64-bit register. */
13215 +extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg);
13216 +#define dwc_read_reg64 DWC_READ_REG64
13217 +
13218 +/** Writes to a 32-bit register. */
13219 +extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value);
13220 +#define dwc_write_reg32 DWC_WRITE_REG32
13221 +
13222 +/** Writes to a 64-bit register. */
13223 +extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value);
13224 +#define dwc_write_reg64 DWC_WRITE_REG64
13225 +
13226 +/**
13227 + * Modify bit values in a register.  Using the
13228 + * algorithm: (reg_contents & ~clear_mask) | set_mask.
13229 + */
13230 +extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask);
13231 +#define dwc_modify_reg32 DWC_MODIFY_REG32
13232 +extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask);
13233 +#define dwc_modify_reg64 DWC_MODIFY_REG64
13234 +
13235 +#endif /* DWC_FREEBSD || DWC_NETBSD */
13236 +
13237 +/** @cond */
13238 +
13239 +/** @name Some convenience MACROS used internally.  Define DWC_DEBUG_REGS to log the
13240 + * register writes. */
13241 +
13242 +#ifdef DWC_LINUX
13243 +
13244 +# ifdef DWC_DEBUG_REGS
13245 +
13246 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13247 +static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
13248 +       return DWC_READ_REG32(&container->regs->_reg[num]); \
13249 +} \
13250 +static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
13251 +       DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
13252 +                 &(((uint32_t*)container->regs->_reg)[num]), data); \
13253 +       DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
13254 +}
13255 +
13256 +#define dwc_define_read_write_reg(_reg,_container_type) \
13257 +static inline uint32_t dwc_read_##_reg(_container_type *container) { \
13258 +       return DWC_READ_REG32(&container->regs->_reg); \
13259 +} \
13260 +static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
13261 +       DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
13262 +       DWC_WRITE_REG32(&container->regs->_reg, data); \
13263 +}
13264 +
13265 +# else /* DWC_DEBUG_REGS */
13266 +
13267 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13268 +static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \
13269 +       return DWC_READ_REG32(&container->regs->_reg[num]); \
13270 +} \
13271 +static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \
13272 +       DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \
13273 +}
13274 +
13275 +#define dwc_define_read_write_reg(_reg,_container_type) \
13276 +static inline uint32_t dwc_read_##_reg(_container_type *container) { \
13277 +       return DWC_READ_REG32(&container->regs->_reg); \
13278 +} \
13279 +static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \
13280 +       DWC_WRITE_REG32(&container->regs->_reg, data); \
13281 +}
13282 +
13283 +# endif        /* DWC_DEBUG_REGS */
13284 +
13285 +#endif /* DWC_LINUX */
13286 +
13287 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13288 +
13289 +# ifdef DWC_DEBUG_REGS
13290 +
13291 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13292 +static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
13293 +       return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
13294 +} \
13295 +static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
13296 +       DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \
13297 +                 &(((uint32_t*)container->regs->_reg)[num]), data); \
13298 +       DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
13299 +}
13300 +
13301 +#define dwc_define_read_write_reg(_reg,_container_type) \
13302 +static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
13303 +       return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
13304 +} \
13305 +static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
13306 +       DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \
13307 +       DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
13308 +}
13309 +
13310 +# else /* DWC_DEBUG_REGS */
13311 +
13312 +#define dwc_define_read_write_reg_n(_reg,_container_type) \
13313 +static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \
13314 +       return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \
13315 +} \
13316 +static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \
13317 +       DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \
13318 +}
13319 +
13320 +#define dwc_define_read_write_reg(_reg,_container_type) \
13321 +static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \
13322 +       return DWC_READ_REG32(io_ctx, &container->regs->_reg); \
13323 +} \
13324 +static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \
13325 +       DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \
13326 +}
13327 +
13328 +# endif        /* DWC_DEBUG_REGS */
13329 +
13330 +#endif /* DWC_FREEBSD || DWC_NETBSD */
13331 +
13332 +/** @endcond */
13333 +
13334 +
13335 +#ifdef DWC_CRYPTOLIB
13336 +/** @name Crypto Functions
13337 + *
13338 + * These are the low-level cryptographic functions used by the driver. */
13339 +
13340 +/** Perform AES CBC */
13341 +extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out);
13342 +#define dwc_aes_cbc DWC_AES_CBC
13343 +
13344 +/** Fill the provided buffer with random bytes.  These should be cryptographic grade random numbers. */
13345 +extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length);
13346 +#define dwc_random_bytes DWC_RANDOM_BYTES
13347 +
13348 +/** Perform the SHA-256 hash function */
13349 +extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out);
13350 +#define dwc_sha256 DWC_SHA256
13351 +
13352 +/** Calculated the HMAC-SHA256 */
13353 +extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out);
13354 +#define dwc_hmac_sha256 DWC_HMAC_SHA256
13355 +
13356 +#endif /* DWC_CRYPTOLIB */
13357 +
13358 +
13359 +/** @name Memory Allocation
13360 + *
13361 + * These function provide access to memory allocation.  There are only 2 DMA
13362 + * functions and 3 Regular memory functions that need to be implemented.  None
13363 + * of the memory debugging routines need to be implemented.  The allocation
13364 + * routines all ZERO the contents of the memory.
13365 + *
13366 + * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering.
13367 + * This checks for memory leaks, keeping track of alloc/free pairs.  It also
13368 + * keeps track of how much memory the driver is using at any given time. */
13369 +
13370 +#define DWC_PAGE_SIZE 4096
13371 +#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff)
13372 +#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0)
13373 +
13374 +#define DWC_INVALID_DMA_ADDR 0x0
13375 +
13376 +#ifdef DWC_LINUX
13377 +/** Type for a DMA address */
13378 +typedef dma_addr_t dwc_dma_t;
13379 +#endif
13380 +
13381 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13382 +typedef bus_addr_t dwc_dma_t;
13383 +#endif
13384 +
13385 +#ifdef DWC_FREEBSD
13386 +typedef struct dwc_dmactx {
13387 +       struct device *dev;
13388 +       bus_dma_tag_t dma_tag;
13389 +       bus_dmamap_t dma_map;
13390 +       bus_addr_t dma_paddr;
13391 +       void *dma_vaddr;
13392 +} dwc_dmactx_t;
13393 +#endif
13394 +
13395 +#ifdef DWC_NETBSD
13396 +typedef struct dwc_dmactx {
13397 +       struct device *dev;
13398 +       bus_dma_tag_t dma_tag;
13399 +       bus_dmamap_t dma_map;
13400 +       bus_dma_segment_t segs[1];
13401 +       int nsegs;
13402 +       bus_addr_t dma_paddr;
13403 +       void *dma_vaddr;
13404 +} dwc_dmactx_t;
13405 +#endif
13406 +
13407 +/* @todo these functions will be added in the future */
13408 +#if 0
13409 +/**
13410 + * Creates a DMA pool from which you can allocate DMA buffers.  Buffers
13411 + * allocated from this pool will be guaranteed to meet the size, alignment, and
13412 + * boundary requirements specified.
13413 + *
13414 + * @param[in] size Specifies the size of the buffers that will be allocated from
13415 + * this pool.
13416 + * @param[in] align Specifies the byte alignment requirements of the buffers
13417 + * allocated from this pool.  Must be a power of 2.
13418 + * @param[in] boundary Specifies the N-byte boundary that buffers allocated from
13419 + * this pool must not cross.
13420 + *
13421 + * @returns A pointer to an internal opaque structure which is not to be
13422 + * accessed outside of these library functions.  Use this handle to specify
13423 + * which pools to allocate/free DMA buffers from and also to destroy the pool,
13424 + * when you are done with it.
13425 + */
13426 +extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary);
13427 +
13428 +/**
13429 + * Destroy a DMA pool.  All buffers allocated from that pool must be freed first.
13430 + */
13431 +extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool);
13432 +
13433 +/**
13434 + * Allocate a buffer from the specified DMA pool and zeros its contents.
13435 + */
13436 +extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr);
13437 +
13438 +/**
13439 + * Free a previously allocated buffer from the DMA pool.
13440 + */
13441 +extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr);
13442 +#endif
13443 +
13444 +/** Allocates a DMA capable buffer and zeroes its contents. */
13445 +extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
13446 +
13447 +/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */
13448 +extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr);
13449 +
13450 +/** Frees a previously allocated buffer. */
13451 +extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr);
13452 +
13453 +/** Allocates a block of memory and zeroes its contents. */
13454 +extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size);
13455 +
13456 +/** Allocates a block of memory and zeroes its contents, in an atomic manner
13457 + * which can be used inside interrupt context.  The size should be sufficiently
13458 + * small, a few KB at most, such that failures are not likely to occur.  Can just call
13459 + * __DWC_ALLOC if it is atomic. */
13460 +extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size);
13461 +
13462 +/** Frees a previously allocated buffer. */
13463 +extern void __DWC_FREE(void *mem_ctx, void *addr);
13464 +
13465 +#ifndef DWC_DEBUG_MEMORY
13466 +
13467 +#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_)
13468 +#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_)
13469 +#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_)
13470 +
13471 +# ifdef DWC_LINUX
13472 +#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_)
13473 +#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_)
13474 +#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_)
13475 +# endif
13476 +
13477 +# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13478 +#define DWC_DMA_ALLOC __DWC_DMA_ALLOC
13479 +#define DWC_DMA_FREE __DWC_DMA_FREE
13480 +# endif
13481 +extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line);
13482 +
13483 +#else  /* DWC_DEBUG_MEMORY */
13484 +
13485 +extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line);
13486 +extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line);
13487 +extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line);
13488 +extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
13489 +                                char const *func, int line);
13490 +extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr,
13491 +                               char const *func, int line);
13492 +extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr,
13493 +                              dwc_dma_t dma_addr, char const *func, int line);
13494 +
13495 +extern int dwc_memory_debug_start(void *mem_ctx);
13496 +extern void dwc_memory_debug_stop(void);
13497 +extern void dwc_memory_debug_report(void);
13498 +
13499 +#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__)
13500 +#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \
13501 +                                                       __func__, __LINE__)
13502 +#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__)
13503 +
13504 +# ifdef DWC_LINUX
13505 +#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \
13506 +                                               _dma_, __func__, __LINE__)
13507 +#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \
13508 +                                               _dma_, __func__, __LINE__)
13509 +#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \
13510 +                                               _virt_, _dma_, __func__, __LINE__)
13511 +# endif
13512 +
13513 +# if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13514 +#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \
13515 +                                               _dma_, __func__, __LINE__)
13516 +#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \
13517 +                                                _virt_, _dma_, __func__, __LINE__)
13518 +# endif
13519 +
13520 +#endif /* DWC_DEBUG_MEMORY */
13521 +
13522 +#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_)
13523 +#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_)
13524 +#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_)
13525 +
13526 +#ifdef DWC_LINUX
13527 +/* Linux doesn't need any extra parameters for DMA buffer allocation, so we
13528 + * just throw away the DMA context parameter.
13529 + */
13530 +#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_)
13531 +#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_)
13532 +#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_)
13533 +#endif
13534 +
13535 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13536 +/** BSD needs several extra parameters for DMA buffer allocation, so we pass
13537 + * them in using the DMA context parameter.
13538 + */
13539 +#define dwc_dma_alloc DWC_DMA_ALLOC
13540 +#define dwc_dma_free DWC_DMA_FREE
13541 +#endif
13542 +
13543 +
13544 +/** @name Memory and String Processing */
13545 +
13546 +/** memset() clone */
13547 +extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size);
13548 +#define dwc_memset DWC_MEMSET
13549 +
13550 +/** memcpy() clone */
13551 +extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size);
13552 +#define dwc_memcpy DWC_MEMCPY
13553 +
13554 +/** memmove() clone */
13555 +extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size);
13556 +#define dwc_memmove DWC_MEMMOVE
13557 +
13558 +/** memcmp() clone */
13559 +extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size);
13560 +#define dwc_memcmp DWC_MEMCMP
13561 +
13562 +/** strcmp() clone */
13563 +extern int DWC_STRCMP(void *s1, void *s2);
13564 +#define dwc_strcmp DWC_STRCMP
13565 +
13566 +/** strncmp() clone */
13567 +extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size);
13568 +#define dwc_strncmp DWC_STRNCMP
13569 +
13570 +/** strlen() clone, for NULL terminated ASCII strings */
13571 +extern int DWC_STRLEN(char const *str);
13572 +#define dwc_strlen DWC_STRLEN
13573 +
13574 +/** strcpy() clone, for NULL terminated ASCII strings */
13575 +extern char *DWC_STRCPY(char *to, const char *from);
13576 +#define dwc_strcpy DWC_STRCPY
13577 +
13578 +/** strdup() clone.  If you wish to use memory allocation debugging, this
13579 + * implementation of strdup should use the DWC_* memory routines instead of
13580 + * calling a predefined strdup.  Otherwise the memory allocated by this routine
13581 + * will not be seen by the debugging routines. */
13582 +extern char *DWC_STRDUP(char const *str);
13583 +#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_)
13584 +
13585 +/** NOT an atoi() clone.  Read the description carefully.  Returns an integer
13586 + * converted from the string str in base 10 unless the string begins with a "0x"
13587 + * in which case it is base 16.  String must be a NULL terminated sequence of
13588 + * ASCII characters and may optionally begin with whitespace, a + or -, and a
13589 + * "0x" prefix if base 16.  The remaining characters must be valid digits for
13590 + * the number and end with a NULL character.  If any invalid characters are
13591 + * encountered or it returns with a negative error code and the results of the
13592 + * conversion are undefined.  On sucess it returns 0.  Overflow conditions are
13593 + * undefined.  An example implementation using atoi() can be referenced from the
13594 + * Linux implementation. */
13595 +extern int DWC_ATOI(const char *str, int32_t *value);
13596 +#define dwc_atoi DWC_ATOI
13597 +
13598 +/** Same as above but for unsigned. */
13599 +extern int DWC_ATOUI(const char *str, uint32_t *value);
13600 +#define dwc_atoui DWC_ATOUI
13601 +
13602 +#ifdef DWC_UTFLIB
13603 +/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */
13604 +extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len);
13605 +#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE
13606 +#endif
13607 +
13608 +
13609 +/** @name Wait queues
13610 + *
13611 + * Wait queues provide a means of synchronizing between threads or processes.  A
13612 + * process can block on a waitq if some condition is not true, waiting for it to
13613 + * become true.  When the waitq is triggered all waiting process will get
13614 + * unblocked and the condition will be check again.  Waitqs should be triggered
13615 + * every time a condition can potentially change.*/
13616 +struct dwc_waitq;
13617 +
13618 +/** Type for a waitq */
13619 +typedef struct dwc_waitq dwc_waitq_t;
13620 +
13621 +/** The type of waitq condition callback function.  This is called every time
13622 + * condition is evaluated. */
13623 +typedef int (*dwc_waitq_condition_t)(void *data);
13624 +
13625 +/** Allocate a waitq */
13626 +extern dwc_waitq_t *DWC_WAITQ_ALLOC(void);
13627 +#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC()
13628 +
13629 +/** Free a waitq */
13630 +extern void DWC_WAITQ_FREE(dwc_waitq_t *wq);
13631 +#define dwc_waitq_free DWC_WAITQ_FREE
13632 +
13633 +/** Check the condition and if it is false, block on the waitq.  When unblocked, check the
13634 + * condition again.  The function returns when the condition becomes true.  The return value
13635 + * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */
13636 +extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data);
13637 +#define dwc_waitq_wait DWC_WAITQ_WAIT
13638 +
13639 +/** Check the condition and if it is false, block on the waitq.  When unblocked,
13640 + * check the condition again.  The function returns when the condition become
13641 + * true or the timeout has passed.  The return value is 0 on condition true or
13642 + * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on
13643 + * error. */
13644 +extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond,
13645 +                                     void *data, int32_t msecs);
13646 +#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT
13647 +
13648 +/** Trigger a waitq, unblocking all processes.  This should be called whenever a condition
13649 + * has potentially changed. */
13650 +extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq);
13651 +#define dwc_waitq_trigger DWC_WAITQ_TRIGGER
13652 +
13653 +/** Unblock all processes waiting on the waitq with an ABORTED result. */
13654 +extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq);
13655 +#define dwc_waitq_abort DWC_WAITQ_ABORT
13656 +
13657 +
13658 +/** @name Threads
13659 + *
13660 + * A thread must be explicitly stopped.  It must check DWC_THREAD_SHOULD_STOP
13661 + * whenever it is woken up, and then return.  The DWC_THREAD_STOP function
13662 + * returns the value from the thread.
13663 + */
13664 +
13665 +struct dwc_thread;
13666 +
13667 +/** Type for a thread */
13668 +typedef struct dwc_thread dwc_thread_t;
13669 +
13670 +/** The thread function */
13671 +typedef int (*dwc_thread_function_t)(void *data);
13672 +
13673 +/** Create a thread and start it running the thread_function.  Returns a handle
13674 + * to the thread */
13675 +extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data);
13676 +#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_)
13677 +
13678 +/** Stops a thread.  Return the value returned by the thread.  Or will return
13679 + * DWC_ABORT if the thread never started. */
13680 +extern int DWC_THREAD_STOP(dwc_thread_t *thread);
13681 +#define dwc_thread_stop DWC_THREAD_STOP
13682 +
13683 +/** Signifies to the thread that it must stop. */
13684 +#ifdef DWC_LINUX
13685 +/* Linux doesn't need any parameters for kthread_should_stop() */
13686 +extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void);
13687 +#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP()
13688 +
13689 +/* No thread_exit function in Linux */
13690 +#define dwc_thread_exit(_thrd_)
13691 +#endif
13692 +
13693 +#if defined(DWC_FREEBSD) || defined(DWC_NETBSD)
13694 +/** BSD needs the thread pointer for kthread_suspend_check() */
13695 +extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread);
13696 +#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP
13697 +
13698 +/** The thread must call this to exit. */
13699 +extern void DWC_THREAD_EXIT(dwc_thread_t *thread);
13700 +#define dwc_thread_exit DWC_THREAD_EXIT
13701 +#endif
13702 +
13703 +
13704 +/** @name Work queues
13705 + *
13706 + * Workqs are used to queue a callback function to be called at some later time,
13707 + * in another thread. */
13708 +struct dwc_workq;
13709 +
13710 +/** Type for a workq */
13711 +typedef struct dwc_workq dwc_workq_t;
13712 +
13713 +/** The type of the callback function to be called. */
13714 +typedef void (*dwc_work_callback_t)(void *data);
13715 +
13716 +/** Allocate a workq */
13717 +extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name);
13718 +#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_)
13719 +
13720 +/** Free a workq.  All work must be completed before being freed. */
13721 +extern void DWC_WORKQ_FREE(dwc_workq_t *workq);
13722 +#define dwc_workq_free DWC_WORKQ_FREE
13723 +
13724 +/** Schedule a callback on the workq, passing in data.  The function will be
13725 + * scheduled at some later time. */
13726 +extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb,
13727 +                              void *data, char *format, ...)
13728 +#ifdef __GNUC__
13729 +       __attribute__ ((format(printf, 4, 5)));
13730 +#else
13731 +       ;
13732 +#endif
13733 +#define dwc_workq_schedule DWC_WORKQ_SCHEDULE
13734 +
13735 +/** Schedule a callback on the workq, that will be called until at least
13736 + * given number miliseconds have passed. */
13737 +extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb,
13738 +                                      void *data, uint32_t time, char *format, ...)
13739 +#ifdef __GNUC__
13740 +       __attribute__ ((format(printf, 5, 6)));
13741 +#else
13742 +       ;
13743 +#endif
13744 +#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED
13745 +
13746 +/** The number of processes in the workq */
13747 +extern int DWC_WORKQ_PENDING(dwc_workq_t *workq);
13748 +#define dwc_workq_pending DWC_WORKQ_PENDING
13749 +
13750 +/** Blocks until all the work in the workq is complete or timed out.  Returns <
13751 + * 0 on timeout. */
13752 +extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout);
13753 +#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE
13754 +
13755 +
13756 +/** @name Tasklets
13757 + *
13758 + */
13759 +struct dwc_tasklet;
13760 +
13761 +/** Type for a tasklet */
13762 +typedef struct dwc_tasklet dwc_tasklet_t;
13763 +
13764 +/** The type of the callback function to be called */
13765 +typedef void (*dwc_tasklet_callback_t)(void *data);
13766 +
13767 +/** Allocates a tasklet */
13768 +extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data);
13769 +#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_)
13770 +
13771 +/** Frees a tasklet */
13772 +extern void DWC_TASK_FREE(dwc_tasklet_t *task);
13773 +#define dwc_task_free DWC_TASK_FREE
13774 +
13775 +/** Schedules a tasklet to run */
13776 +extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task);
13777 +#define dwc_task_schedule DWC_TASK_SCHEDULE
13778 +
13779 +extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task);
13780 +#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE
13781 +
13782 +/** @name Timer
13783 + *
13784 + * Callbacks must be small and atomic.
13785 + */
13786 +struct dwc_timer;
13787 +
13788 +/** Type for a timer */
13789 +typedef struct dwc_timer dwc_timer_t;
13790 +
13791 +/** The type of the callback function to be called */
13792 +typedef void (*dwc_timer_callback_t)(void *data);
13793 +
13794 +/** Allocates a timer */
13795 +extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data);
13796 +#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_)
13797 +
13798 +/** Frees a timer */
13799 +extern void DWC_TIMER_FREE(dwc_timer_t *timer);
13800 +#define dwc_timer_free DWC_TIMER_FREE
13801 +
13802 +/** Schedules the timer to run at time ms from now.  And will repeat at every
13803 + * repeat_interval msec therafter
13804 + *
13805 + * Modifies a timer that is still awaiting execution to a new expiration time.
13806 + * The mod_time is added to the old time.  */
13807 +extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time);
13808 +#define dwc_timer_schedule DWC_TIMER_SCHEDULE
13809 +
13810 +/** Disables the timer from execution. */
13811 +extern void DWC_TIMER_CANCEL(dwc_timer_t *timer);
13812 +#define dwc_timer_cancel DWC_TIMER_CANCEL
13813 +
13814 +
13815 +/** @name Spinlocks
13816 + *
13817 + * These locks are used when the work between the lock/unlock is atomic and
13818 + * short.  Interrupts are also disabled during the lock/unlock and thus they are
13819 + * suitable to lock between interrupt/non-interrupt context.  They also lock
13820 + * between processes if you have multiple CPUs or Preemption.  If you don't have
13821 + * multiple CPUS or Preemption, then the you can simply implement the
13822 + * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts.  Because
13823 + * the work between the lock/unlock is atomic, the process context will never
13824 + * change, and so you never have to lock between processes.  */
13825 +
13826 +struct dwc_spinlock;
13827 +
13828 +/** Type for a spinlock */
13829 +typedef struct dwc_spinlock dwc_spinlock_t;
13830 +
13831 +/** Type for the 'flags' argument to spinlock funtions */
13832 +typedef unsigned long dwc_irqflags_t;
13833 +
13834 +/** Returns an initialized lock variable.  This function should allocate and
13835 + * initialize the OS-specific data structure used for locking.  This data
13836 + * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should
13837 + * be freed by the DWC_FREE_LOCK when it is no longer used.
13838 + *
13839 + * For Linux Spinlock Debugging make it macro because the debugging routines use
13840 + * the symbol name to determine recursive locking. Using a wrapper function
13841 + * makes it falsely think recursive locking occurs. */
13842 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)
13843 +#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \
13844 +       lock = DWC_ALLOC(sizeof(spinlock_t)); \
13845 +       if (lock) { \
13846 +               spin_lock_init((spinlock_t *)lock); \
13847 +       } \
13848 +})
13849 +#else
13850 +extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void);
13851 +#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC()
13852 +#endif
13853 +
13854 +/** Frees an initialized lock variable. */
13855 +extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock);
13856 +#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_)
13857 +
13858 +/** Disables interrupts and blocks until it acquires the lock.
13859 + *
13860 + * @param lock Pointer to the spinlock.
13861 + * @param flags Unsigned long for irq flags storage.
13862 + */
13863 +extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags);
13864 +#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE
13865 +
13866 +/** Re-enables the interrupt and releases the lock.
13867 + *
13868 + * @param lock Pointer to the spinlock.
13869 + * @param flags Unsigned long for irq flags storage.  Must be the same as was
13870 + * passed into DWC_LOCK.
13871 + */
13872 +extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags);
13873 +#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE
13874 +
13875 +/** Blocks until it acquires the lock.
13876 + *
13877 + * @param lock Pointer to the spinlock.
13878 + */
13879 +extern void DWC_SPINLOCK(dwc_spinlock_t *lock);
13880 +#define dwc_spinlock DWC_SPINLOCK
13881 +
13882 +/** Releases the lock.
13883 + *
13884 + * @param lock Pointer to the spinlock.
13885 + */
13886 +extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock);
13887 +#define dwc_spinunlock DWC_SPINUNLOCK
13888 +
13889 +
13890 +/** @name Mutexes
13891 + *
13892 + * Unlike spinlocks Mutexes lock only between processes and the work between the
13893 + * lock/unlock CAN block, therefore it CANNOT be called from interrupt context.
13894 + */
13895 +
13896 +struct dwc_mutex;
13897 +
13898 +/** Type for a mutex */
13899 +typedef struct dwc_mutex dwc_mutex_t;
13900 +
13901 +/* For Linux Mutex Debugging make it inline because the debugging routines use
13902 + * the symbol to determine recursive locking.  This makes it falsely think
13903 + * recursive locking occurs. */
13904 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
13905 +#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \
13906 +       __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \
13907 +       mutex_init((struct mutex *)__mutexp); \
13908 +})
13909 +#endif
13910 +
13911 +/** Allocate a mutex */
13912 +extern dwc_mutex_t *DWC_MUTEX_ALLOC(void);
13913 +#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC()
13914 +
13915 +/* For memory leak debugging when using Linux Mutex Debugging */
13916 +#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)
13917 +#define DWC_MUTEX_FREE(__mutexp) do { \
13918 +       mutex_destroy((struct mutex *)__mutexp); \
13919 +       DWC_FREE(__mutexp); \
13920 +} while(0)
13921 +#else
13922 +/** Free a mutex */
13923 +extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex);
13924 +#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_)
13925 +#endif
13926 +
13927 +/** Lock a mutex */
13928 +extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex);
13929 +#define dwc_mutex_lock DWC_MUTEX_LOCK
13930 +
13931 +/** Non-blocking lock returns 1 on successful lock. */
13932 +extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex);
13933 +#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK
13934 +
13935 +/** Unlock a mutex */
13936 +extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex);
13937 +#define dwc_mutex_unlock DWC_MUTEX_UNLOCK
13938 +
13939 +
13940 +/** @name Time */
13941 +
13942 +/** Microsecond delay.
13943 + *
13944 + * @param usecs  Microseconds to delay.
13945 + */
13946 +extern void DWC_UDELAY(uint32_t usecs);
13947 +#define dwc_udelay DWC_UDELAY
13948 +
13949 +/** Millisecond delay.
13950 + *
13951 + * @param msecs  Milliseconds to delay.
13952 + */
13953 +extern void DWC_MDELAY(uint32_t msecs);
13954 +#define dwc_mdelay DWC_MDELAY
13955 +
13956 +/** Non-busy waiting.
13957 + * Sleeps for specified number of milliseconds.
13958 + *
13959 + * @param msecs Milliseconds to sleep.
13960 + */
13961 +extern void DWC_MSLEEP(uint32_t msecs);
13962 +#define dwc_msleep DWC_MSLEEP
13963 +
13964 +/**
13965 + * Returns number of milliseconds since boot.
13966 + */
13967 +extern uint32_t DWC_TIME(void);
13968 +#define dwc_time DWC_TIME
13969 +
13970 +
13971 +
13972 +
13973 +/* @mainpage DWC Portability and Common Library
13974 + *
13975 + * This is the documentation for the DWC Portability and Common Library.
13976 + *
13977 + * @section intro Introduction
13978 + *
13979 + * The DWC Portability library consists of wrapper calls and data structures to
13980 + * all low-level functions which are typically provided by the OS.  The WUDEV
13981 + * driver uses only these functions.  In order to port the WUDEV driver, only
13982 + * the functions in this library need to be re-implemented, with the same
13983 + * behavior as documented here.
13984 + *
13985 + * The Common library consists of higher level functions, which rely only on
13986 + * calling the functions from the DWC Portability library.  These common
13987 + * routines are shared across modules.  Some of the common libraries need to be
13988 + * used directly by the driver programmer when porting WUDEV.  Such as the
13989 + * parameter and notification libraries.
13990 + *
13991 + * @section low Portability Library OS Wrapper Functions
13992 + *
13993 + * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that
13994 + * needs to be implemented when porting, for example DWC_MUTEX_ALLOC().  All of
13995 + * these functions are included in the dwc_os.h file.
13996 + *
13997 + * There are many functions here covering a wide array of OS services.  Please
13998 + * see dwc_os.h for details, and implementation notes for each function.
13999 + *
14000 + * @section common Common Library Functions
14001 + *
14002 + * Any function starting with dwc and in all lowercase is a common library
14003 + * routine.  These functions have a portable implementation and do not need to
14004 + * be reimplemented when porting.  The common routines can be used by any
14005 + * driver, and some must be used by the end user to control the drivers.  For
14006 + * example, you must use the Parameter common library in order to set the
14007 + * parameters in the WUDEV module.
14008 + *
14009 + * The common libraries consist of the following:
14010 + *
14011 + * - Connection Contexts - Used internally and can be used by end-user.  See dwc_cc.h
14012 + * - Parameters - Used internally and can be used by end-user.  See dwc_params.h
14013 + * - Notifications - Used internally and can be used by end-user.  See dwc_notifier.h
14014 + * - Lists - Used internally and can be used by end-user.  See dwc_list.h
14015 + * - Memory Debugging - Used internally and can be used by end-user.  See dwc_os.h
14016 + * - Modpow - Used internally only.  See dwc_modpow.h
14017 + * - DH - Used internally only.  See dwc_dh.h
14018 + * - Crypto - Used internally only.  See dwc_crypto.h
14019 + *
14020 + *
14021 + * @section prereq Prerequistes For dwc_os.h
14022 + * @subsection types Data Types
14023 + *
14024 + * The dwc_os.h file assumes that several low-level data types are pre defined for the
14025 + * compilation environment.  These data types are:
14026 + *
14027 + * - uint8_t - unsigned 8-bit data type
14028 + * - int8_t - signed 8-bit data type
14029 + * - uint16_t - unsigned 16-bit data type
14030 + * - int16_t - signed 16-bit data type
14031 + * - uint32_t - unsigned 32-bit data type
14032 + * - int32_t - signed 32-bit data type
14033 + * - uint64_t - unsigned 64-bit data type
14034 + * - int64_t - signed 64-bit data type
14035 + *
14036 + * Ensure that these are defined before using dwc_os.h.  The easiest way to do
14037 + * that is to modify the top of the file to include the appropriate header.
14038 + * This is already done for the Linux environment.  If the DWC_LINUX macro is
14039 + * defined, the correct header will be added.  A standard header <stdint.h> is
14040 + * also used for environments where standard C headers are available.
14041 + *
14042 + * @subsection stdarg Variable Arguments
14043 + *
14044 + * Variable arguments are provided by a standard C header <stdarg.h>.  it is
14045 + * available in Both the Linux and ANSI C enviornment.  An equivalent must be
14046 + * provided in your enviornment in order to use dwc_os.h with the debug and
14047 + * tracing message functionality.
14048 + *
14049 + * @subsection thread Threading
14050 + *
14051 + * WUDEV Core must be run on an operating system that provides for multiple
14052 + * threads/processes.  Threading can be implemented in many ways, even in
14053 + * embedded systems without an operating system.  At the bare minimum, the
14054 + * system should be able to start any number of processes at any time to handle
14055 + * special work.  It need not be a pre-emptive system.  Process context can
14056 + * change upon a call to a blocking function.  The hardware interrupt context
14057 + * that calls the module's ISR() function must be differentiable from process
14058 + * context, even if your processes are impemented via a hardware interrupt.
14059 + * Further locking mechanism between process must exist (or be implemented), and
14060 + * process context must have a way to disable interrupts for a period of time to
14061 + * lock them out.  If all of this exists, the functions in dwc_os.h related to
14062 + * threading should be able to be implemented with the defined behavior.
14063 + *
14064 + */
14065 +
14066 +#ifdef __cplusplus
14067 +}
14068 +#endif
14069 +
14070 +#endif /* _DWC_OS_H_ */
14071 --- /dev/null
14072 +++ b/drivers/usb/host/dwc_common_port/usb.h
14073 @@ -0,0 +1,946 @@
14074 +/*
14075 + * Copyright (c) 1998 The NetBSD Foundation, Inc.
14076 + * All rights reserved.
14077 + *
14078 + * This code is derived from software contributed to The NetBSD Foundation
14079 + * by Lennart Augustsson (lennart@augustsson.net) at
14080 + * Carlstedt Research & Technology.
14081 + *
14082 + * Redistribution and use in source and binary forms, with or without
14083 + * modification, are permitted provided that the following conditions
14084 + * are met:
14085 + * 1. Redistributions of source code must retain the above copyright
14086 + *    notice, this list of conditions and the following disclaimer.
14087 + * 2. Redistributions in binary form must reproduce the above copyright
14088 + *    notice, this list of conditions and the following disclaimer in the
14089 + *    documentation and/or other materials provided with the distribution.
14090 + * 3. All advertising materials mentioning features or use of this software
14091 + *    must display the following acknowledgement:
14092 + *        This product includes software developed by the NetBSD
14093 + *        Foundation, Inc. and its contributors.
14094 + * 4. Neither the name of The NetBSD Foundation nor the names of its
14095 + *    contributors may be used to endorse or promote products derived
14096 + *    from this software without specific prior written permission.
14097 + *
14098 + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
14099 + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
14100 + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
14101 + * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
14102 + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
14103 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
14104 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
14105 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
14106 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
14107 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
14108 + * POSSIBILITY OF SUCH DAMAGE.
14109 + */
14110 +
14111 +/* Modified by Synopsys, Inc, 12/12/2007 */
14112 +
14113 +
14114 +#ifndef _USB_H_
14115 +#define _USB_H_
14116 +
14117 +#ifdef __cplusplus
14118 +extern "C" {
14119 +#endif
14120 +
14121 +/*
14122 + * The USB records contain some unaligned little-endian word
14123 + * components.  The U[SG]ETW macros take care of both the alignment
14124 + * and endian problem and should always be used to access non-byte
14125 + * values.
14126 + */
14127 +typedef u_int8_t uByte;
14128 +typedef u_int8_t uWord[2];
14129 +typedef u_int8_t uDWord[4];
14130 +
14131 +#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h))
14132 +#define UCONSTW(x)     { (x) & 0xff, ((x) >> 8) & 0xff }
14133 +#define UCONSTDW(x)    { (x) & 0xff, ((x) >> 8) & 0xff, \
14134 +                         ((x) >> 16) & 0xff, ((x) >> 24) & 0xff }
14135 +
14136 +#if 1
14137 +#define UGETW(w) ((w)[0] | ((w)[1] << 8))
14138 +#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8))
14139 +#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24))
14140 +#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \
14141 +                    (w)[1] = (u_int8_t)((v) >> 8), \
14142 +                    (w)[2] = (u_int8_t)((v) >> 16), \
14143 +                    (w)[3] = (u_int8_t)((v) >> 24))
14144 +#else
14145 +/*
14146 + * On little-endian machines that can handle unanliged accesses
14147 + * (e.g. i386) these macros can be replaced by the following.
14148 + */
14149 +#define UGETW(w) (*(u_int16_t *)(w))
14150 +#define USETW(w,v) (*(u_int16_t *)(w) = (v))
14151 +#define UGETDW(w) (*(u_int32_t *)(w))
14152 +#define USETDW(w,v) (*(u_int32_t *)(w) = (v))
14153 +#endif
14154 +
14155 +/*
14156 + * Macros for accessing UAS IU fields, which are big-endian
14157 + */
14158 +#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l))
14159 +#define IUCONSTW(x)    { ((x) >> 8) & 0xff, (x) & 0xff }
14160 +#define IUCONSTDW(x)   { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \
14161 +                       ((x) >> 8) & 0xff, (x) & 0xff }
14162 +#define IUGETW(w) (((w)[0] << 8) | (w)[1])
14163 +#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v))
14164 +#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3])
14165 +#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \
14166 +                     (w)[1] = (u_int8_t)((v) >> 16), \
14167 +                     (w)[2] = (u_int8_t)((v) >> 8), \
14168 +                     (w)[3] = (u_int8_t)(v))
14169 +
14170 +#define UPACKED __attribute__((__packed__))
14171 +
14172 +typedef struct {
14173 +       uByte           bmRequestType;
14174 +       uByte           bRequest;
14175 +       uWord           wValue;
14176 +       uWord           wIndex;
14177 +       uWord           wLength;
14178 +} UPACKED usb_device_request_t;
14179 +
14180 +#define UT_GET_DIR(a) ((a) & 0x80)
14181 +#define UT_WRITE               0x00
14182 +#define UT_READ                        0x80
14183 +
14184 +#define UT_GET_TYPE(a) ((a) & 0x60)
14185 +#define UT_STANDARD            0x00
14186 +#define UT_CLASS               0x20
14187 +#define UT_VENDOR              0x40
14188 +
14189 +#define UT_GET_RECIPIENT(a) ((a) & 0x1f)
14190 +#define UT_DEVICE              0x00
14191 +#define UT_INTERFACE           0x01
14192 +#define UT_ENDPOINT            0x02
14193 +#define UT_OTHER               0x03
14194 +
14195 +#define UT_READ_DEVICE         (UT_READ  | UT_STANDARD | UT_DEVICE)
14196 +#define UT_READ_INTERFACE      (UT_READ  | UT_STANDARD | UT_INTERFACE)
14197 +#define UT_READ_ENDPOINT       (UT_READ  | UT_STANDARD | UT_ENDPOINT)
14198 +#define UT_WRITE_DEVICE                (UT_WRITE | UT_STANDARD | UT_DEVICE)
14199 +#define UT_WRITE_INTERFACE     (UT_WRITE | UT_STANDARD | UT_INTERFACE)
14200 +#define UT_WRITE_ENDPOINT      (UT_WRITE | UT_STANDARD | UT_ENDPOINT)
14201 +#define UT_READ_CLASS_DEVICE   (UT_READ  | UT_CLASS | UT_DEVICE)
14202 +#define UT_READ_CLASS_INTERFACE        (UT_READ  | UT_CLASS | UT_INTERFACE)
14203 +#define UT_READ_CLASS_OTHER    (UT_READ  | UT_CLASS | UT_OTHER)
14204 +#define UT_READ_CLASS_ENDPOINT (UT_READ  | UT_CLASS | UT_ENDPOINT)
14205 +#define UT_WRITE_CLASS_DEVICE  (UT_WRITE | UT_CLASS | UT_DEVICE)
14206 +#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE)
14207 +#define UT_WRITE_CLASS_OTHER   (UT_WRITE | UT_CLASS | UT_OTHER)
14208 +#define UT_WRITE_CLASS_ENDPOINT        (UT_WRITE | UT_CLASS | UT_ENDPOINT)
14209 +#define UT_READ_VENDOR_DEVICE  (UT_READ  | UT_VENDOR | UT_DEVICE)
14210 +#define UT_READ_VENDOR_INTERFACE (UT_READ  | UT_VENDOR | UT_INTERFACE)
14211 +#define UT_READ_VENDOR_OTHER   (UT_READ  | UT_VENDOR | UT_OTHER)
14212 +#define UT_READ_VENDOR_ENDPOINT        (UT_READ  | UT_VENDOR | UT_ENDPOINT)
14213 +#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE)
14214 +#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE)
14215 +#define UT_WRITE_VENDOR_OTHER  (UT_WRITE | UT_VENDOR | UT_OTHER)
14216 +#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT)
14217 +
14218 +/* Requests */
14219 +#define UR_GET_STATUS          0x00
14220 +#define  USTAT_STANDARD_STATUS  0x00
14221 +#define  WUSTAT_WUSB_FEATURE    0x01
14222 +#define  WUSTAT_CHANNEL_INFO    0x02
14223 +#define  WUSTAT_RECEIVED_DATA   0x03
14224 +#define  WUSTAT_MAS_AVAILABILITY 0x04
14225 +#define  WUSTAT_CURRENT_TRANSMIT_POWER 0x05
14226 +#define UR_CLEAR_FEATURE       0x01
14227 +#define UR_SET_FEATURE         0x03
14228 +#define UR_SET_AND_TEST_FEATURE 0x0c
14229 +#define UR_SET_ADDRESS         0x05
14230 +#define UR_GET_DESCRIPTOR      0x06
14231 +#define  UDESC_DEVICE          0x01
14232 +#define  UDESC_CONFIG          0x02
14233 +#define  UDESC_STRING          0x03
14234 +#define  UDESC_INTERFACE       0x04
14235 +#define  UDESC_ENDPOINT                0x05
14236 +#define  UDESC_SS_USB_COMPANION        0x30
14237 +#define  UDESC_DEVICE_QUALIFIER        0x06
14238 +#define  UDESC_OTHER_SPEED_CONFIGURATION 0x07
14239 +#define  UDESC_INTERFACE_POWER 0x08
14240 +#define  UDESC_OTG             0x09
14241 +#define  WUDESC_SECURITY       0x0c
14242 +#define  WUDESC_KEY            0x0d
14243 +#define   WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf)
14244 +#define   WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4)
14245 +#define    WUD_KEY_TYPE_ASSOC    0x01
14246 +#define    WUD_KEY_TYPE_GTK      0x02
14247 +#define   WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6)
14248 +#define    WUD_KEY_ORIGIN_HOST   0x00
14249 +#define    WUD_KEY_ORIGIN_DEVICE 0x01
14250 +#define  WUDESC_ENCRYPTION_TYPE        0x0e
14251 +#define  WUDESC_BOS            0x0f
14252 +#define  WUDESC_DEVICE_CAPABILITY 0x10
14253 +#define  WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11
14254 +#define  UDESC_BOS             0x0f
14255 +#define  UDESC_DEVICE_CAPABILITY 0x10
14256 +#define  UDESC_CS_DEVICE       0x21    /* class specific */
14257 +#define  UDESC_CS_CONFIG       0x22
14258 +#define  UDESC_CS_STRING       0x23
14259 +#define  UDESC_CS_INTERFACE    0x24
14260 +#define  UDESC_CS_ENDPOINT     0x25
14261 +#define  UDESC_HUB             0x29
14262 +#define UR_SET_DESCRIPTOR      0x07
14263 +#define UR_GET_CONFIG          0x08
14264 +#define UR_SET_CONFIG          0x09
14265 +#define UR_GET_INTERFACE       0x0a
14266 +#define UR_SET_INTERFACE       0x0b
14267 +#define UR_SYNCH_FRAME         0x0c
14268 +#define WUR_SET_ENCRYPTION      0x0d
14269 +#define WUR_GET_ENCRYPTION     0x0e
14270 +#define WUR_SET_HANDSHAKE      0x0f
14271 +#define WUR_GET_HANDSHAKE      0x10
14272 +#define WUR_SET_CONNECTION     0x11
14273 +#define WUR_SET_SECURITY_DATA  0x12
14274 +#define WUR_GET_SECURITY_DATA  0x13
14275 +#define WUR_SET_WUSB_DATA      0x14
14276 +#define  WUDATA_DRPIE_INFO     0x01
14277 +#define  WUDATA_TRANSMIT_DATA  0x02
14278 +#define  WUDATA_TRANSMIT_PARAMS        0x03
14279 +#define  WUDATA_RECEIVE_PARAMS 0x04
14280 +#define  WUDATA_TRANSMIT_POWER 0x05
14281 +#define WUR_LOOPBACK_DATA_WRITE        0x15
14282 +#define WUR_LOOPBACK_DATA_READ 0x16
14283 +#define WUR_SET_INTERFACE_DS   0x17
14284 +
14285 +/* Feature numbers */
14286 +#define UF_ENDPOINT_HALT       0
14287 +#define UF_DEVICE_REMOTE_WAKEUP        1
14288 +#define UF_TEST_MODE           2
14289 +#define UF_DEVICE_B_HNP_ENABLE 3
14290 +#define UF_DEVICE_A_HNP_SUPPORT        4
14291 +#define UF_DEVICE_A_ALT_HNP_SUPPORT 5
14292 +#define WUF_WUSB               3
14293 +#define  WUF_TX_DRPIE          0x0
14294 +#define  WUF_DEV_XMIT_PACKET   0x1
14295 +#define  WUF_COUNT_PACKETS     0x2
14296 +#define  WUF_CAPTURE_PACKETS   0x3
14297 +#define UF_FUNCTION_SUSPEND    0
14298 +#define UF_U1_ENABLE           48
14299 +#define UF_U2_ENABLE           49
14300 +#define UF_LTM_ENABLE          50
14301 +
14302 +/* Class requests from the USB 2.0 hub spec, table 11-15 */
14303 +#define UCR_CLEAR_HUB_FEATURE          (0x2000 | UR_CLEAR_FEATURE)
14304 +#define UCR_CLEAR_PORT_FEATURE         (0x2300 | UR_CLEAR_FEATURE)
14305 +#define UCR_GET_HUB_DESCRIPTOR         (0xa000 | UR_GET_DESCRIPTOR)
14306 +#define UCR_GET_HUB_STATUS             (0xa000 | UR_GET_STATUS)
14307 +#define UCR_GET_PORT_STATUS            (0xa300 | UR_GET_STATUS)
14308 +#define UCR_SET_HUB_FEATURE            (0x2000 | UR_SET_FEATURE)
14309 +#define UCR_SET_PORT_FEATURE           (0x2300 | UR_SET_FEATURE)
14310 +#define UCR_SET_AND_TEST_PORT_FEATURE  (0xa300 | UR_SET_AND_TEST_FEATURE)
14311 +
14312 +#ifdef _MSC_VER
14313 +#include <pshpack1.h>
14314 +#endif
14315 +
14316 +typedef struct {
14317 +       uByte           bLength;
14318 +       uByte           bDescriptorType;
14319 +       uByte           bDescriptorSubtype;
14320 +} UPACKED usb_descriptor_t;
14321 +
14322 +typedef struct {
14323 +       uByte           bLength;
14324 +       uByte           bDescriptorType;
14325 +} UPACKED usb_descriptor_header_t;
14326 +
14327 +typedef struct {
14328 +       uByte           bLength;
14329 +       uByte           bDescriptorType;
14330 +       uWord           bcdUSB;
14331 +#define UD_USB_2_0             0x0200
14332 +#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0)
14333 +       uByte           bDeviceClass;
14334 +       uByte           bDeviceSubClass;
14335 +       uByte           bDeviceProtocol;
14336 +       uByte           bMaxPacketSize;
14337 +       /* The fields below are not part of the initial descriptor. */
14338 +       uWord           idVendor;
14339 +       uWord           idProduct;
14340 +       uWord           bcdDevice;
14341 +       uByte           iManufacturer;
14342 +       uByte           iProduct;
14343 +       uByte           iSerialNumber;
14344 +       uByte           bNumConfigurations;
14345 +} UPACKED usb_device_descriptor_t;
14346 +#define USB_DEVICE_DESCRIPTOR_SIZE 18
14347 +
14348 +typedef struct {
14349 +       uByte           bLength;
14350 +       uByte           bDescriptorType;
14351 +       uWord           wTotalLength;
14352 +       uByte           bNumInterface;
14353 +       uByte           bConfigurationValue;
14354 +       uByte           iConfiguration;
14355 +#define UC_ATT_ONE             (1 << 7)        /* must be set */
14356 +#define UC_ATT_SELFPOWER       (1 << 6)        /* self powered */
14357 +#define UC_ATT_WAKEUP          (1 << 5)        /* can wakeup */
14358 +#define UC_ATT_BATTERY         (1 << 4)        /* battery powered */
14359 +       uByte           bmAttributes;
14360 +#define UC_BUS_POWERED         0x80
14361 +#define UC_SELF_POWERED                0x40
14362 +#define UC_REMOTE_WAKEUP       0x20
14363 +       uByte           bMaxPower; /* max current in 2 mA units */
14364 +#define UC_POWER_FACTOR 2
14365 +} UPACKED usb_config_descriptor_t;
14366 +#define USB_CONFIG_DESCRIPTOR_SIZE 9
14367 +
14368 +typedef struct {
14369 +       uByte           bLength;
14370 +       uByte           bDescriptorType;
14371 +       uByte           bInterfaceNumber;
14372 +       uByte           bAlternateSetting;
14373 +       uByte           bNumEndpoints;
14374 +       uByte           bInterfaceClass;
14375 +       uByte           bInterfaceSubClass;
14376 +       uByte           bInterfaceProtocol;
14377 +       uByte           iInterface;
14378 +} UPACKED usb_interface_descriptor_t;
14379 +#define USB_INTERFACE_DESCRIPTOR_SIZE 9
14380 +
14381 +typedef struct {
14382 +       uByte           bLength;
14383 +       uByte           bDescriptorType;
14384 +       uByte           bEndpointAddress;
14385 +#define UE_GET_DIR(a)  ((a) & 0x80)
14386 +#define UE_SET_DIR(a,d)        ((a) | (((d)&1) << 7))
14387 +#define UE_DIR_IN      0x80
14388 +#define UE_DIR_OUT     0x00
14389 +#define UE_ADDR                0x0f
14390 +#define UE_GET_ADDR(a) ((a) & UE_ADDR)
14391 +       uByte           bmAttributes;
14392 +#define UE_XFERTYPE    0x03
14393 +#define  UE_CONTROL    0x00
14394 +#define  UE_ISOCHRONOUS        0x01
14395 +#define  UE_BULK       0x02
14396 +#define  UE_INTERRUPT  0x03
14397 +#define UE_GET_XFERTYPE(a)     ((a) & UE_XFERTYPE)
14398 +#define UE_ISO_TYPE    0x0c
14399 +#define  UE_ISO_ASYNC  0x04
14400 +#define  UE_ISO_ADAPT  0x08
14401 +#define  UE_ISO_SYNC   0x0c
14402 +#define UE_GET_ISO_TYPE(a)     ((a) & UE_ISO_TYPE)
14403 +       uWord           wMaxPacketSize;
14404 +       uByte           bInterval;
14405 +} UPACKED usb_endpoint_descriptor_t;
14406 +#define USB_ENDPOINT_DESCRIPTOR_SIZE 7
14407 +
14408 +typedef struct ss_endpoint_companion_descriptor {
14409 +       uByte bLength;
14410 +       uByte bDescriptorType;
14411 +       uByte bMaxBurst;
14412 +#define USSE_GET_MAX_STREAMS(a)                ((a) & 0x1f)
14413 +#define USSE_SET_MAX_STREAMS(a, b)     ((a) | ((b) & 0x1f))
14414 +#define USSE_GET_MAX_PACKET_NUM(a)     ((a) & 0x03)
14415 +#define USSE_SET_MAX_PACKET_NUM(a, b)  ((a) | ((b) & 0x03))
14416 +       uByte bmAttributes;
14417 +       uWord wBytesPerInterval;
14418 +} UPACKED ss_endpoint_companion_descriptor_t;
14419 +#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6
14420 +
14421 +typedef struct {
14422 +       uByte           bLength;
14423 +       uByte           bDescriptorType;
14424 +       uWord           bString[127];
14425 +} UPACKED usb_string_descriptor_t;
14426 +#define USB_MAX_STRING_LEN 128
14427 +#define USB_LANGUAGE_TABLE 0   /* # of the string language id table */
14428 +
14429 +/* Hub specific request */
14430 +#define UR_GET_BUS_STATE       0x02
14431 +#define UR_CLEAR_TT_BUFFER     0x08
14432 +#define UR_RESET_TT            0x09
14433 +#define UR_GET_TT_STATE                0x0a
14434 +#define UR_STOP_TT             0x0b
14435 +
14436 +/* Hub features */
14437 +#define UHF_C_HUB_LOCAL_POWER  0
14438 +#define UHF_C_HUB_OVER_CURRENT 1
14439 +#define UHF_PORT_CONNECTION    0
14440 +#define UHF_PORT_ENABLE                1
14441 +#define UHF_PORT_SUSPEND       2
14442 +#define UHF_PORT_OVER_CURRENT  3
14443 +#define UHF_PORT_RESET         4
14444 +#define UHF_PORT_L1            5
14445 +#define UHF_PORT_POWER         8
14446 +#define UHF_PORT_LOW_SPEED     9
14447 +#define UHF_PORT_HIGH_SPEED    10
14448 +#define UHF_C_PORT_CONNECTION  16
14449 +#define UHF_C_PORT_ENABLE      17
14450 +#define UHF_C_PORT_SUSPEND     18
14451 +#define UHF_C_PORT_OVER_CURRENT        19
14452 +#define UHF_C_PORT_RESET       20
14453 +#define UHF_C_PORT_L1          23
14454 +#define UHF_PORT_TEST          21
14455 +#define UHF_PORT_INDICATOR     22
14456 +
14457 +typedef struct {
14458 +       uByte           bDescLength;
14459 +       uByte           bDescriptorType;
14460 +       uByte           bNbrPorts;
14461 +       uWord           wHubCharacteristics;
14462 +#define UHD_PWR                        0x0003
14463 +#define  UHD_PWR_GANGED                0x0000
14464 +#define  UHD_PWR_INDIVIDUAL    0x0001
14465 +#define  UHD_PWR_NO_SWITCH     0x0002
14466 +#define UHD_COMPOUND           0x0004
14467 +#define UHD_OC                 0x0018
14468 +#define  UHD_OC_GLOBAL         0x0000
14469 +#define  UHD_OC_INDIVIDUAL     0x0008
14470 +#define  UHD_OC_NONE           0x0010
14471 +#define UHD_TT_THINK           0x0060
14472 +#define  UHD_TT_THINK_8                0x0000
14473 +#define  UHD_TT_THINK_16       0x0020
14474 +#define  UHD_TT_THINK_24       0x0040
14475 +#define  UHD_TT_THINK_32       0x0060
14476 +#define UHD_PORT_IND           0x0080
14477 +       uByte           bPwrOn2PwrGood; /* delay in 2 ms units */
14478 +#define UHD_PWRON_FACTOR 2
14479 +       uByte           bHubContrCurrent;
14480 +       uByte           DeviceRemovable[32]; /* max 255 ports */
14481 +#define UHD_NOT_REMOV(desc, i) \
14482 +    (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1)
14483 +       /* deprecated */ uByte          PortPowerCtrlMask[1];
14484 +} UPACKED usb_hub_descriptor_t;
14485 +#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */
14486 +
14487 +typedef struct {
14488 +       uByte           bLength;
14489 +       uByte           bDescriptorType;
14490 +       uWord           bcdUSB;
14491 +       uByte           bDeviceClass;
14492 +       uByte           bDeviceSubClass;
14493 +       uByte           bDeviceProtocol;
14494 +       uByte           bMaxPacketSize0;
14495 +       uByte           bNumConfigurations;
14496 +       uByte           bReserved;
14497 +} UPACKED usb_device_qualifier_t;
14498 +#define USB_DEVICE_QUALIFIER_SIZE 10
14499 +
14500 +typedef struct {
14501 +       uByte           bLength;
14502 +       uByte           bDescriptorType;
14503 +       uByte           bmAttributes;
14504 +#define UOTG_SRP       0x01
14505 +#define UOTG_HNP       0x02
14506 +} UPACKED usb_otg_descriptor_t;
14507 +
14508 +/* OTG feature selectors */
14509 +#define UOTG_B_HNP_ENABLE      3
14510 +#define UOTG_A_HNP_SUPPORT     4
14511 +#define UOTG_A_ALT_HNP_SUPPORT 5
14512 +
14513 +typedef struct {
14514 +       uWord           wStatus;
14515 +/* Device status flags */
14516 +#define UDS_SELF_POWERED               0x0001
14517 +#define UDS_REMOTE_WAKEUP              0x0002
14518 +/* Endpoint status flags */
14519 +#define UES_HALT                       0x0001
14520 +} UPACKED usb_status_t;
14521 +
14522 +typedef struct {
14523 +       uWord           wHubStatus;
14524 +#define UHS_LOCAL_POWER                        0x0001
14525 +#define UHS_OVER_CURRENT               0x0002
14526 +       uWord           wHubChange;
14527 +} UPACKED usb_hub_status_t;
14528 +
14529 +typedef struct {
14530 +       uWord           wPortStatus;
14531 +#define UPS_CURRENT_CONNECT_STATUS     0x0001
14532 +#define UPS_PORT_ENABLED               0x0002
14533 +#define UPS_SUSPEND                    0x0004
14534 +#define UPS_OVERCURRENT_INDICATOR      0x0008
14535 +#define UPS_RESET                      0x0010
14536 +#define UPS_PORT_POWER                 0x0100
14537 +#define UPS_LOW_SPEED                  0x0200
14538 +#define UPS_HIGH_SPEED                 0x0400
14539 +#define UPS_PORT_TEST                  0x0800
14540 +#define UPS_PORT_INDICATOR             0x1000
14541 +       uWord           wPortChange;
14542 +#define UPS_C_CONNECT_STATUS           0x0001
14543 +#define UPS_C_PORT_ENABLED             0x0002
14544 +#define UPS_C_SUSPEND                  0x0004
14545 +#define UPS_C_OVERCURRENT_INDICATOR    0x0008
14546 +#define UPS_C_PORT_RESET               0x0010
14547 +} UPACKED usb_port_status_t;
14548 +
14549 +#ifdef _MSC_VER
14550 +#include <poppack.h>
14551 +#endif
14552 +
14553 +/* Device class codes */
14554 +#define UDCLASS_IN_INTERFACE   0x00
14555 +#define UDCLASS_COMM           0x02
14556 +#define UDCLASS_HUB            0x09
14557 +#define  UDSUBCLASS_HUB                0x00
14558 +#define  UDPROTO_FSHUB         0x00
14559 +#define  UDPROTO_HSHUBSTT      0x01
14560 +#define  UDPROTO_HSHUBMTT      0x02
14561 +#define UDCLASS_DIAGNOSTIC     0xdc
14562 +#define UDCLASS_WIRELESS       0xe0
14563 +#define  UDSUBCLASS_RF         0x01
14564 +#define   UDPROTO_BLUETOOTH    0x01
14565 +#define UDCLASS_VENDOR         0xff
14566 +
14567 +/* Interface class codes */
14568 +#define UICLASS_UNSPEC         0x00
14569 +
14570 +#define UICLASS_AUDIO          0x01
14571 +#define  UISUBCLASS_AUDIOCONTROL       1
14572 +#define  UISUBCLASS_AUDIOSTREAM                2
14573 +#define  UISUBCLASS_MIDISTREAM         3
14574 +
14575 +#define UICLASS_CDC            0x02 /* communication */
14576 +#define  UISUBCLASS_DIRECT_LINE_CONTROL_MODEL  1
14577 +#define  UISUBCLASS_ABSTRACT_CONTROL_MODEL     2
14578 +#define  UISUBCLASS_TELEPHONE_CONTROL_MODEL    3
14579 +#define  UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4
14580 +#define  UISUBCLASS_CAPI_CONTROLMODEL          5
14581 +#define  UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6
14582 +#define  UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7
14583 +#define   UIPROTO_CDC_AT                       1
14584 +
14585 +#define UICLASS_HID            0x03
14586 +#define  UISUBCLASS_BOOT       1
14587 +#define  UIPROTO_BOOT_KEYBOARD 1
14588 +
14589 +#define UICLASS_PHYSICAL       0x05
14590 +
14591 +#define UICLASS_IMAGE          0x06
14592 +
14593 +#define UICLASS_PRINTER                0x07
14594 +#define  UISUBCLASS_PRINTER    1
14595 +#define  UIPROTO_PRINTER_UNI   1
14596 +#define  UIPROTO_PRINTER_BI    2
14597 +#define  UIPROTO_PRINTER_1284  3
14598 +
14599 +#define UICLASS_MASS           0x08
14600 +#define  UISUBCLASS_RBC                1
14601 +#define  UISUBCLASS_SFF8020I   2
14602 +#define  UISUBCLASS_QIC157     3
14603 +#define  UISUBCLASS_UFI                4
14604 +#define  UISUBCLASS_SFF8070I   5
14605 +#define  UISUBCLASS_SCSI       6
14606 +#define  UIPROTO_MASS_CBI_I    0
14607 +#define  UIPROTO_MASS_CBI      1
14608 +#define  UIPROTO_MASS_BBB_OLD  2       /* Not in the spec anymore */
14609 +#define  UIPROTO_MASS_BBB      80      /* 'P' for the Iomega Zip drive */
14610 +
14611 +#define UICLASS_HUB            0x09
14612 +#define  UISUBCLASS_HUB                0
14613 +#define  UIPROTO_FSHUB         0
14614 +#define  UIPROTO_HSHUBSTT      0 /* Yes, same as previous */
14615 +#define  UIPROTO_HSHUBMTT      1
14616 +
14617 +#define UICLASS_CDC_DATA       0x0a
14618 +#define  UISUBCLASS_DATA               0
14619 +#define   UIPROTO_DATA_ISDNBRI         0x30    /* Physical iface */
14620 +#define   UIPROTO_DATA_HDLC            0x31    /* HDLC */
14621 +#define   UIPROTO_DATA_TRANSPARENT     0x32    /* Transparent */
14622 +#define   UIPROTO_DATA_Q921M           0x50    /* Management for Q921 */
14623 +#define   UIPROTO_DATA_Q921            0x51    /* Data for Q921 */
14624 +#define   UIPROTO_DATA_Q921TM          0x52    /* TEI multiplexer for Q921 */
14625 +#define   UIPROTO_DATA_V42BIS          0x90    /* Data compression */
14626 +#define   UIPROTO_DATA_Q931            0x91    /* Euro-ISDN */
14627 +#define   UIPROTO_DATA_V120            0x92    /* V.24 rate adaption */
14628 +#define   UIPROTO_DATA_CAPI            0x93    /* CAPI 2.0 commands */
14629 +#define   UIPROTO_DATA_HOST_BASED      0xfd    /* Host based driver */
14630 +#define   UIPROTO_DATA_PUF             0xfe    /* see Prot. Unit Func. Desc.*/
14631 +#define   UIPROTO_DATA_VENDOR          0xff    /* Vendor specific */
14632 +
14633 +#define UICLASS_SMARTCARD      0x0b
14634 +
14635 +/*#define UICLASS_FIRM_UPD     0x0c*/
14636 +
14637 +#define UICLASS_SECURITY       0x0d
14638 +
14639 +#define UICLASS_DIAGNOSTIC     0xdc
14640 +
14641 +#define UICLASS_WIRELESS       0xe0
14642 +#define  UISUBCLASS_RF                 0x01
14643 +#define   UIPROTO_BLUETOOTH            0x01
14644 +
14645 +#define UICLASS_APPL_SPEC      0xfe
14646 +#define  UISUBCLASS_FIRMWARE_DOWNLOAD  1
14647 +#define  UISUBCLASS_IRDA               2
14648 +#define  UIPROTO_IRDA                  0
14649 +
14650 +#define UICLASS_VENDOR         0xff
14651 +
14652 +#define USB_HUB_MAX_DEPTH 5
14653 +
14654 +/*
14655 + * Minimum time a device needs to be powered down to go through
14656 + * a power cycle.  XXX Are these time in the spec?
14657 + */
14658 +#define USB_POWER_DOWN_TIME    200 /* ms */
14659 +#define USB_PORT_POWER_DOWN_TIME       100 /* ms */
14660 +
14661 +#if 0
14662 +/* These are the values from the spec. */
14663 +#define USB_PORT_RESET_DELAY   10  /* ms */
14664 +#define USB_PORT_ROOT_RESET_DELAY 50  /* ms */
14665 +#define USB_PORT_RESET_RECOVERY        10  /* ms */
14666 +#define USB_PORT_POWERUP_DELAY 100 /* ms */
14667 +#define USB_SET_ADDRESS_SETTLE 2   /* ms */
14668 +#define USB_RESUME_DELAY       (20*5)  /* ms */
14669 +#define USB_RESUME_WAIT                10  /* ms */
14670 +#define USB_RESUME_RECOVERY    10  /* ms */
14671 +#define USB_EXTRA_POWER_UP_TIME        0   /* ms */
14672 +#else
14673 +/* Allow for marginal (i.e. non-conforming) devices. */
14674 +#define USB_PORT_RESET_DELAY   50  /* ms */
14675 +#define USB_PORT_ROOT_RESET_DELAY 250  /* ms */
14676 +#define USB_PORT_RESET_RECOVERY        250  /* ms */
14677 +#define USB_PORT_POWERUP_DELAY 300 /* ms */
14678 +#define USB_SET_ADDRESS_SETTLE 10  /* ms */
14679 +#define USB_RESUME_DELAY       (50*5)  /* ms */
14680 +#define USB_RESUME_WAIT                50  /* ms */
14681 +#define USB_RESUME_RECOVERY    50  /* ms */
14682 +#define USB_EXTRA_POWER_UP_TIME        20  /* ms */
14683 +#endif
14684 +
14685 +#define USB_MIN_POWER          100 /* mA */
14686 +#define USB_MAX_POWER          500 /* mA */
14687 +
14688 +#define USB_BUS_RESET_DELAY    100 /* ms XXX?*/
14689 +
14690 +#define USB_UNCONFIG_NO 0
14691 +#define USB_UNCONFIG_INDEX (-1)
14692 +
14693 +/*** ioctl() related stuff ***/
14694 +
14695 +struct usb_ctl_request {
14696 +       int     ucr_addr;
14697 +       usb_device_request_t ucr_request;
14698 +       void    *ucr_data;
14699 +       int     ucr_flags;
14700 +#define USBD_SHORT_XFER_OK     0x04    /* allow short reads */
14701 +       int     ucr_actlen;             /* actual length transferred */
14702 +};
14703 +
14704 +struct usb_alt_interface {
14705 +       int     uai_config_index;
14706 +       int     uai_interface_index;
14707 +       int     uai_alt_no;
14708 +};
14709 +
14710 +#define USB_CURRENT_CONFIG_INDEX (-1)
14711 +#define USB_CURRENT_ALT_INDEX (-1)
14712 +
14713 +struct usb_config_desc {
14714 +       int     ucd_config_index;
14715 +       usb_config_descriptor_t ucd_desc;
14716 +};
14717 +
14718 +struct usb_interface_desc {
14719 +       int     uid_config_index;
14720 +       int     uid_interface_index;
14721 +       int     uid_alt_index;
14722 +       usb_interface_descriptor_t uid_desc;
14723 +};
14724 +
14725 +struct usb_endpoint_desc {
14726 +       int     ued_config_index;
14727 +       int     ued_interface_index;
14728 +       int     ued_alt_index;
14729 +       int     ued_endpoint_index;
14730 +       usb_endpoint_descriptor_t ued_desc;
14731 +};
14732 +
14733 +struct usb_full_desc {
14734 +       int     ufd_config_index;
14735 +       u_int   ufd_size;
14736 +       u_char  *ufd_data;
14737 +};
14738 +
14739 +struct usb_string_desc {
14740 +       int     usd_string_index;
14741 +       int     usd_language_id;
14742 +       usb_string_descriptor_t usd_desc;
14743 +};
14744 +
14745 +struct usb_ctl_report_desc {
14746 +       int     ucrd_size;
14747 +       u_char  ucrd_data[1024];        /* filled data size will vary */
14748 +};
14749 +
14750 +typedef struct { u_int32_t cookie; } usb_event_cookie_t;
14751 +
14752 +#define USB_MAX_DEVNAMES 4
14753 +#define USB_MAX_DEVNAMELEN 16
14754 +struct usb_device_info {
14755 +       u_int8_t        udi_bus;
14756 +       u_int8_t        udi_addr;       /* device address */
14757 +       usb_event_cookie_t udi_cookie;
14758 +       char            udi_product[USB_MAX_STRING_LEN];
14759 +       char            udi_vendor[USB_MAX_STRING_LEN];
14760 +       char            udi_release[8];
14761 +       u_int16_t       udi_productNo;
14762 +       u_int16_t       udi_vendorNo;
14763 +       u_int16_t       udi_releaseNo;
14764 +       u_int8_t        udi_class;
14765 +       u_int8_t        udi_subclass;
14766 +       u_int8_t        udi_protocol;
14767 +       u_int8_t        udi_config;
14768 +       u_int8_t        udi_speed;
14769 +#define USB_SPEED_UNKNOWN      0
14770 +#define USB_SPEED_LOW          1
14771 +#define USB_SPEED_FULL         2
14772 +#define USB_SPEED_HIGH         3
14773 +#define USB_SPEED_VARIABLE     4
14774 +#define USB_SPEED_SUPER                5
14775 +       int             udi_power;      /* power consumption in mA, 0 if selfpowered */
14776 +       int             udi_nports;
14777 +       char            udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN];
14778 +       u_int8_t        udi_ports[16];/* hub only: addresses of devices on ports */
14779 +#define USB_PORT_ENABLED 0xff
14780 +#define USB_PORT_SUSPENDED 0xfe
14781 +#define USB_PORT_POWERED 0xfd
14782 +#define USB_PORT_DISABLED 0xfc
14783 +};
14784 +
14785 +struct usb_ctl_report {
14786 +       int     ucr_report;
14787 +       u_char  ucr_data[1024]; /* filled data size will vary */
14788 +};
14789 +
14790 +struct usb_device_stats {
14791 +       u_long  uds_requests[4];        /* indexed by transfer type UE_* */
14792 +};
14793 +
14794 +#define WUSB_MIN_IE                    0x80
14795 +#define WUSB_WCTA_IE                   0x80
14796 +#define WUSB_WCONNECTACK_IE            0x81
14797 +#define WUSB_WHOSTINFO_IE              0x82
14798 +#define  WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3)
14799 +#define   WUHI_CA_RECONN               0x00
14800 +#define   WUHI_CA_LIMITED              0x01
14801 +#define   WUHI_CA_ALL                  0x03
14802 +#define  WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3)
14803 +#define WUSB_WCHCHANGEANNOUNCE_IE      0x83
14804 +#define WUSB_WDEV_DISCONNECT_IE                0x84
14805 +#define WUSB_WHOST_DISCONNECT_IE       0x85
14806 +#define WUSB_WRELEASE_CHANNEL_IE       0x86
14807 +#define WUSB_WWORK_IE                  0x87
14808 +#define WUSB_WCHANNEL_STOP_IE          0x88
14809 +#define WUSB_WDEV_KEEPALIVE_IE         0x89
14810 +#define WUSB_WISOCH_DISCARD_IE         0x8A
14811 +#define WUSB_WRESETDEVICE_IE           0x8B
14812 +#define WUSB_WXMIT_PACKET_ADJUST_IE    0x8C
14813 +#define WUSB_MAX_IE                    0x8C
14814 +
14815 +/* Device Notification Types */
14816 +
14817 +#define WUSB_DN_MIN                    0x01
14818 +#define WUSB_DN_CONNECT                        0x01
14819 +# define WUSB_DA_OLDCONN       0x00
14820 +# define WUSB_DA_NEWCONN       0x01
14821 +# define WUSB_DA_SELF_BEACON   0x02
14822 +# define WUSB_DA_DIR_BEACON    0x04
14823 +# define WUSB_DA_NO_BEACON     0x06
14824 +#define WUSB_DN_DISCONNECT             0x02
14825 +#define WUSB_DN_EPRDY                  0x03
14826 +#define WUSB_DN_MASAVAILCHANGED                0x04
14827 +#define WUSB_DN_REMOTEWAKEUP           0x05
14828 +#define WUSB_DN_SLEEP                  0x06
14829 +#define WUSB_DN_ALIVE                  0x07
14830 +#define WUSB_DN_MAX                    0x07
14831 +
14832 +#ifdef _MSC_VER
14833 +#include <pshpack1.h>
14834 +#endif
14835 +
14836 +/* WUSB Handshake Data.  Used during the SET/GET HANDSHAKE requests */
14837 +typedef struct wusb_hndshk_data {
14838 +       uByte bMessageNumber;
14839 +       uByte bStatus;
14840 +       uByte tTKID[3];
14841 +       uByte bReserved;
14842 +       uByte CDID[16];
14843 +       uByte Nonce[16];
14844 +       uByte MIC[8];
14845 +} UPACKED wusb_hndshk_data_t;
14846 +#define WUSB_HANDSHAKE_LEN_FOR_MIC     38
14847 +
14848 +/* WUSB Connection Context */
14849 +typedef struct wusb_conn_context {
14850 +       uByte CHID [16];
14851 +       uByte CDID [16];
14852 +       uByte CK [16];
14853 +} UPACKED wusb_conn_context_t;
14854 +
14855 +/* WUSB Security Descriptor */
14856 +typedef struct wusb_security_desc {
14857 +       uByte bLength;
14858 +       uByte bDescriptorType;
14859 +       uWord wTotalLength;
14860 +       uByte bNumEncryptionTypes;
14861 +} UPACKED wusb_security_desc_t;
14862 +
14863 +/* WUSB Encryption Type Descriptor */
14864 +typedef struct wusb_encrypt_type_desc {
14865 +       uByte bLength;
14866 +       uByte bDescriptorType;
14867 +
14868 +       uByte bEncryptionType;
14869 +#define WUETD_UNSECURE         0
14870 +#define WUETD_WIRED            1
14871 +#define WUETD_CCM_1            2
14872 +#define WUETD_RSA_1            3
14873 +
14874 +       uByte bEncryptionValue;
14875 +       uByte bAuthKeyIndex;
14876 +} UPACKED wusb_encrypt_type_desc_t;
14877 +
14878 +/* WUSB Key Descriptor */
14879 +typedef struct wusb_key_desc {
14880 +       uByte bLength;
14881 +       uByte bDescriptorType;
14882 +       uByte tTKID[3];
14883 +       uByte bReserved;
14884 +       uByte KeyData[1];       /* variable length */
14885 +} UPACKED wusb_key_desc_t;
14886 +
14887 +/* WUSB BOS Descriptor (Binary device Object Store) */
14888 +typedef struct wusb_bos_desc {
14889 +       uByte bLength;
14890 +       uByte bDescriptorType;
14891 +       uWord wTotalLength;
14892 +       uByte bNumDeviceCaps;
14893 +} UPACKED wusb_bos_desc_t;
14894 +
14895 +#define USB_DEVICE_CAPABILITY_20_EXTENSION     0x02
14896 +typedef struct usb_dev_cap_20_ext_desc {
14897 +       uByte bLength;
14898 +       uByte bDescriptorType;
14899 +       uByte bDevCapabilityType;
14900 +#define USB_20_EXT_LPM                         0x02
14901 +       uDWord bmAttributes;
14902 +} UPACKED usb_dev_cap_20_ext_desc_t;
14903 +
14904 +#define USB_DEVICE_CAPABILITY_SS_USB           0x03
14905 +typedef struct usb_dev_cap_ss_usb {
14906 +       uByte bLength;
14907 +       uByte bDescriptorType;
14908 +       uByte bDevCapabilityType;
14909 +#define USB_DC_SS_USB_LTM_CAPABLE              0x02
14910 +       uByte bmAttributes;
14911 +#define USB_DC_SS_USB_SPEED_SUPPORT_LOW                0x01
14912 +#define USB_DC_SS_USB_SPEED_SUPPORT_FULL       0x02
14913 +#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH       0x04
14914 +#define USB_DC_SS_USB_SPEED_SUPPORT_SS         0x08
14915 +       uWord wSpeedsSupported;
14916 +       uByte bFunctionalitySupport;
14917 +       uByte bU1DevExitLat;
14918 +       uWord wU2DevExitLat;
14919 +} UPACKED usb_dev_cap_ss_usb_t;
14920 +
14921 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID     0x04
14922 +typedef struct usb_dev_cap_container_id {
14923 +       uByte bLength;
14924 +       uByte bDescriptorType;
14925 +       uByte bDevCapabilityType;
14926 +       uByte bReserved;
14927 +       uByte containerID[16];
14928 +} UPACKED usb_dev_cap_container_id_t;
14929 +
14930 +/* Device Capability Type Codes */
14931 +#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01
14932 +
14933 +/* Device Capability Descriptor */
14934 +typedef struct wusb_dev_cap_desc {
14935 +       uByte bLength;
14936 +       uByte bDescriptorType;
14937 +       uByte bDevCapabilityType;
14938 +       uByte caps[1];  /* Variable length */
14939 +} UPACKED wusb_dev_cap_desc_t;
14940 +
14941 +/* Device Capability Descriptor */
14942 +typedef struct wusb_dev_cap_uwb_desc {
14943 +       uByte bLength;
14944 +       uByte bDescriptorType;
14945 +       uByte bDevCapabilityType;
14946 +       uByte bmAttributes;
14947 +       uWord wPHYRates;        /* Bitmap */
14948 +       uByte bmTFITXPowerInfo;
14949 +       uByte bmFFITXPowerInfo;
14950 +       uWord bmBandGroup;
14951 +       uByte bReserved;
14952 +} UPACKED wusb_dev_cap_uwb_desc_t;
14953 +
14954 +/* Wireless USB Endpoint Companion Descriptor */
14955 +typedef struct wusb_endpoint_companion_desc {
14956 +       uByte bLength;
14957 +       uByte bDescriptorType;
14958 +       uByte bMaxBurst;
14959 +       uByte bMaxSequence;
14960 +       uWord wMaxStreamDelay;
14961 +       uWord wOverTheAirPacketSize;
14962 +       uByte bOverTheAirInterval;
14963 +       uByte bmCompAttributes;
14964 +} UPACKED wusb_endpoint_companion_desc_t;
14965 +
14966 +/* Wireless USB Numeric Association M1 Data Structure */
14967 +typedef struct wusb_m1_data {
14968 +       uByte version;
14969 +       uWord langId;
14970 +       uByte deviceFriendlyNameLength;
14971 +       uByte sha_256_m3[32];
14972 +       uByte deviceFriendlyName[256];
14973 +} UPACKED wusb_m1_data_t;
14974 +
14975 +typedef struct wusb_m2_data {
14976 +       uByte version;
14977 +       uWord langId;
14978 +       uByte hostFriendlyNameLength;
14979 +       uByte pkh[384];
14980 +       uByte hostFriendlyName[256];
14981 +} UPACKED wusb_m2_data_t;
14982 +
14983 +typedef struct wusb_m3_data {
14984 +       uByte pkd[384];
14985 +       uByte nd;
14986 +} UPACKED wusb_m3_data_t;
14987 +
14988 +typedef struct wusb_m4_data {
14989 +       uDWord _attributeTypeIdAndLength_1;
14990 +       uWord  associationTypeId;
14991 +
14992 +       uDWord _attributeTypeIdAndLength_2;
14993 +       uWord  associationSubTypeId;
14994 +
14995 +       uDWord _attributeTypeIdAndLength_3;
14996 +       uDWord length;
14997 +
14998 +       uDWord _attributeTypeIdAndLength_4;
14999 +       uDWord associationStatus;
15000 +
15001 +       uDWord _attributeTypeIdAndLength_5;
15002 +       uByte  chid[16];
15003 +
15004 +       uDWord _attributeTypeIdAndLength_6;
15005 +       uByte  cdid[16];
15006 +
15007 +       uDWord _attributeTypeIdAndLength_7;
15008 +       uByte  bandGroups[2];
15009 +} UPACKED wusb_m4_data_t;
15010 +
15011 +#ifdef _MSC_VER
15012 +#include <poppack.h>
15013 +#endif
15014 +
15015 +#ifdef __cplusplus
15016 +}
15017 +#endif
15018 +
15019 +#endif /* _USB_H_ */
15020 --- /dev/null
15021 +++ b/drivers/usb/host/dwc_otg/Makefile
15022 @@ -0,0 +1,82 @@
15023 +#
15024 +# Makefile for DWC_otg Highspeed USB controller driver
15025 +#
15026 +
15027 +ifneq ($(KERNELRELEASE),)
15028 +
15029 +# Use the BUS_INTERFACE variable to compile the software for either
15030 +# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus.
15031 +ifeq ($(BUS_INTERFACE),)
15032 +#      BUS_INTERFACE = -DPCI_INTERFACE
15033 +#      BUS_INTERFACE = -DLM_INTERFACE
15034 +        BUS_INTERFACE = -DPLATFORM_INTERFACE
15035 +endif
15036 +
15037 +#ccflags-y     += -DDEBUG
15038 +#ccflags-y     += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs
15039 +
15040 +# Use one of the following flags to compile the software in host-only or
15041 +# device-only mode.
15042 +#ccflags-y        += -DDWC_HOST_ONLY
15043 +#ccflags-y        += -DDWC_DEVICE_ONLY
15044 +
15045 +ccflags-y      += -Dlinux -DDWC_HS_ELECT_TST
15046 +#ccflags-y     += -DDWC_EN_ISOC
15047 +ccflags-y      += -I$(obj)/../dwc_common_port
15048 +#ccflags-y     += -I$(PORTLIB)
15049 +ccflags-y      += -DDWC_LINUX
15050 +ccflags-y      += $(CFI)
15051 +ccflags-y      += $(BUS_INTERFACE)
15052 +#ccflags-y     += -DDWC_DEV_SRPCAP
15053 +
15054 +obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o
15055 +
15056 +dwc_otg-objs   := dwc_otg_driver.o dwc_otg_attr.o
15057 +dwc_otg-objs   += dwc_otg_cil.o dwc_otg_cil_intr.o
15058 +dwc_otg-objs   += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o
15059 +dwc_otg-objs   += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o
15060 +dwc_otg-objs   += dwc_otg_adp.o
15061 +dwc_otg-objs   += dwc_otg_fiq_fsm.o
15062 +dwc_otg-objs   += dwc_otg_fiq_stub.o
15063 +ifneq ($(CFI),)
15064 +dwc_otg-objs   += dwc_otg_cfi.o
15065 +endif
15066 +
15067 +kernrelwd := $(subst ., ,$(KERNELRELEASE))
15068 +kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd))
15069 +
15070 +ifneq ($(kernrel3),2.6.20)
15071 +ccflags-y += $(CPPFLAGS)
15072 +endif
15073 +
15074 +else
15075 +
15076 +PWD            := $(shell pwd)
15077 +PORTLIB                := $(PWD)/../dwc_common_port
15078 +
15079 +# Command paths
15080 +CTAGS          := $(CTAGS)
15081 +DOXYGEN                := $(DOXYGEN)
15082 +
15083 +default: portlib
15084 +       $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
15085 +
15086 +install: default
15087 +       $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install
15088 +       $(MAKE) -C$(KDIR) M=$(PWD) modules_install
15089 +
15090 +portlib:
15091 +       $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules
15092 +       cp $(PORTLIB)/Module.symvers $(PWD)/
15093 +
15094 +docs:  $(wildcard *.[hc]) doc/doxygen.cfg
15095 +       $(DOXYGEN) doc/doxygen.cfg
15096 +
15097 +tags:  $(wildcard *.[hc])
15098 +       $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h)
15099 +
15100 +
15101 +clean:
15102 +       rm -rf   *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers
15103 +
15104 +endif
15105 --- /dev/null
15106 +++ b/drivers/usb/host/dwc_otg/doc/doxygen.cfg
15107 @@ -0,0 +1,224 @@
15108 +# Doxyfile 1.3.9.1
15109 +
15110 +#---------------------------------------------------------------------------
15111 +# Project related configuration options
15112 +#---------------------------------------------------------------------------
15113 +PROJECT_NAME           = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver"
15114 +PROJECT_NUMBER         = v3.00a
15115 +OUTPUT_DIRECTORY       = ./doc/
15116 +CREATE_SUBDIRS         = NO
15117 +OUTPUT_LANGUAGE        = English
15118 +BRIEF_MEMBER_DESC      = YES
15119 +REPEAT_BRIEF           = YES
15120 +ABBREVIATE_BRIEF       = "The $name class" \
15121 +                         "The $name widget" \
15122 +                         "The $name file" \
15123 +                         is \
15124 +                         provides \
15125 +                         specifies \
15126 +                         contains \
15127 +                         represents \
15128 +                         a \
15129 +                         an \
15130 +                         the
15131 +ALWAYS_DETAILED_SEC    = NO
15132 +INLINE_INHERITED_MEMB  = NO
15133 +FULL_PATH_NAMES        = NO
15134 +STRIP_FROM_PATH        =
15135 +STRIP_FROM_INC_PATH    =
15136 +SHORT_NAMES            = NO
15137 +JAVADOC_AUTOBRIEF      = YES
15138 +MULTILINE_CPP_IS_BRIEF = NO
15139 +INHERIT_DOCS           = YES
15140 +DISTRIBUTE_GROUP_DOC   = NO
15141 +TAB_SIZE               = 8
15142 +ALIASES                =
15143 +OPTIMIZE_OUTPUT_FOR_C  = YES
15144 +OPTIMIZE_OUTPUT_JAVA   = NO
15145 +SUBGROUPING            = YES
15146 +#---------------------------------------------------------------------------
15147 +# Build related configuration options
15148 +#---------------------------------------------------------------------------
15149 +EXTRACT_ALL            = NO
15150 +EXTRACT_PRIVATE        = YES
15151 +EXTRACT_STATIC         = YES
15152 +EXTRACT_LOCAL_CLASSES  = YES
15153 +EXTRACT_LOCAL_METHODS  = NO
15154 +HIDE_UNDOC_MEMBERS     = NO
15155 +HIDE_UNDOC_CLASSES     = NO
15156 +HIDE_FRIEND_COMPOUNDS  = NO
15157 +HIDE_IN_BODY_DOCS      = NO
15158 +INTERNAL_DOCS          = NO
15159 +CASE_SENSE_NAMES       = NO
15160 +HIDE_SCOPE_NAMES       = NO
15161 +SHOW_INCLUDE_FILES     = YES
15162 +INLINE_INFO            = YES
15163 +SORT_MEMBER_DOCS       = NO
15164 +SORT_BRIEF_DOCS        = NO
15165 +SORT_BY_SCOPE_NAME     = NO
15166 +GENERATE_TODOLIST      = YES
15167 +GENERATE_TESTLIST      = YES
15168 +GENERATE_BUGLIST       = YES
15169 +GENERATE_DEPRECATEDLIST= YES
15170 +ENABLED_SECTIONS       =
15171 +MAX_INITIALIZER_LINES  = 30
15172 +SHOW_USED_FILES        = YES
15173 +SHOW_DIRECTORIES       = YES
15174 +#---------------------------------------------------------------------------
15175 +# configuration options related to warning and progress messages
15176 +#---------------------------------------------------------------------------
15177 +QUIET                  = YES
15178 +WARNINGS               = YES
15179 +WARN_IF_UNDOCUMENTED   = NO
15180 +WARN_IF_DOC_ERROR      = YES
15181 +WARN_FORMAT            = "$file:$line: $text"
15182 +WARN_LOGFILE           =
15183 +#---------------------------------------------------------------------------
15184 +# configuration options related to the input files
15185 +#---------------------------------------------------------------------------
15186 +INPUT                  = .
15187 +FILE_PATTERNS          = *.c \
15188 +                         *.h \
15189 +                         ./linux/*.c \
15190 +                         ./linux/*.h
15191 +RECURSIVE              = NO
15192 +EXCLUDE                = ./test/ \
15193 +                         ./dwc_otg/.AppleDouble/
15194 +EXCLUDE_SYMLINKS       = YES
15195 +EXCLUDE_PATTERNS       = *.mod.*
15196 +EXAMPLE_PATH           =
15197 +EXAMPLE_PATTERNS       = *
15198 +EXAMPLE_RECURSIVE      = NO
15199 +IMAGE_PATH             =
15200 +INPUT_FILTER           =
15201 +FILTER_PATTERNS        =
15202 +FILTER_SOURCE_FILES    = NO
15203 +#---------------------------------------------------------------------------
15204 +# configuration options related to source browsing
15205 +#---------------------------------------------------------------------------
15206 +SOURCE_BROWSER         = YES
15207 +INLINE_SOURCES         = NO
15208 +STRIP_CODE_COMMENTS    = YES
15209 +REFERENCED_BY_RELATION = NO
15210 +REFERENCES_RELATION    = NO
15211 +VERBATIM_HEADERS       = NO
15212 +#---------------------------------------------------------------------------
15213 +# configuration options related to the alphabetical class index
15214 +#---------------------------------------------------------------------------
15215 +ALPHABETICAL_INDEX     = NO
15216 +COLS_IN_ALPHA_INDEX    = 5
15217 +IGNORE_PREFIX          =
15218 +#---------------------------------------------------------------------------
15219 +# configuration options related to the HTML output
15220 +#---------------------------------------------------------------------------
15221 +GENERATE_HTML          = YES
15222 +HTML_OUTPUT            = html
15223 +HTML_FILE_EXTENSION    = .html
15224 +HTML_HEADER            =
15225 +HTML_FOOTER            =
15226 +HTML_STYLESHEET        =
15227 +HTML_ALIGN_MEMBERS     = YES
15228 +GENERATE_HTMLHELP      = NO
15229 +CHM_FILE               =
15230 +HHC_LOCATION           =
15231 +GENERATE_CHI           = NO
15232 +BINARY_TOC             = NO
15233 +TOC_EXPAND             = NO
15234 +DISABLE_INDEX          = NO
15235 +ENUM_VALUES_PER_LINE   = 4
15236 +GENERATE_TREEVIEW      = YES
15237 +TREEVIEW_WIDTH         = 250
15238 +#---------------------------------------------------------------------------
15239 +# configuration options related to the LaTeX output
15240 +#---------------------------------------------------------------------------
15241 +GENERATE_LATEX         = NO
15242 +LATEX_OUTPUT           = latex
15243 +LATEX_CMD_NAME         = latex
15244 +MAKEINDEX_CMD_NAME     = makeindex
15245 +COMPACT_LATEX          = NO
15246 +PAPER_TYPE             = a4wide
15247 +EXTRA_PACKAGES         =
15248 +LATEX_HEADER           =
15249 +PDF_HYPERLINKS         = NO
15250 +USE_PDFLATEX           = NO
15251 +LATEX_BATCHMODE        = NO
15252 +LATEX_HIDE_INDICES     = NO
15253 +#---------------------------------------------------------------------------
15254 +# configuration options related to the RTF output
15255 +#---------------------------------------------------------------------------
15256 +GENERATE_RTF           = NO
15257 +RTF_OUTPUT             = rtf
15258 +COMPACT_RTF            = NO
15259 +RTF_HYPERLINKS         = NO
15260 +RTF_STYLESHEET_FILE    =
15261 +RTF_EXTENSIONS_FILE    =
15262 +#---------------------------------------------------------------------------
15263 +# configuration options related to the man page output
15264 +#---------------------------------------------------------------------------
15265 +GENERATE_MAN           = NO
15266 +MAN_OUTPUT             = man
15267 +MAN_EXTENSION          = .3
15268 +MAN_LINKS              = NO
15269 +#---------------------------------------------------------------------------
15270 +# configuration options related to the XML output
15271 +#---------------------------------------------------------------------------
15272 +GENERATE_XML           = NO
15273 +XML_OUTPUT             = xml
15274 +XML_SCHEMA             =
15275 +XML_DTD                =
15276 +XML_PROGRAMLISTING     = YES
15277 +#---------------------------------------------------------------------------
15278 +# configuration options for the AutoGen Definitions output
15279 +#---------------------------------------------------------------------------
15280 +GENERATE_AUTOGEN_DEF   = NO
15281 +#---------------------------------------------------------------------------
15282 +# configuration options related to the Perl module output
15283 +#---------------------------------------------------------------------------
15284 +GENERATE_PERLMOD       = NO
15285 +PERLMOD_LATEX          = NO
15286 +PERLMOD_PRETTY         = YES
15287 +PERLMOD_MAKEVAR_PREFIX =
15288 +#---------------------------------------------------------------------------
15289 +# Configuration options related to the preprocessor
15290 +#---------------------------------------------------------------------------
15291 +ENABLE_PREPROCESSING   = YES
15292 +MACRO_EXPANSION        = YES
15293 +EXPAND_ONLY_PREDEF     = YES
15294 +SEARCH_INCLUDES        = YES
15295 +INCLUDE_PATH           =
15296 +INCLUDE_FILE_PATTERNS  =
15297 +PREDEFINED             = DEVICE_ATTR DWC_EN_ISOC
15298 +EXPAND_AS_DEFINED      = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC
15299 +SKIP_FUNCTION_MACROS   = NO
15300 +#---------------------------------------------------------------------------
15301 +# Configuration::additions related to external references
15302 +#---------------------------------------------------------------------------
15303 +TAGFILES               =
15304 +GENERATE_TAGFILE       =
15305 +ALLEXTERNALS           = NO
15306 +EXTERNAL_GROUPS        = YES
15307 +PERL_PATH              = /usr/bin/perl
15308 +#---------------------------------------------------------------------------
15309 +# Configuration options related to the dot tool
15310 +#---------------------------------------------------------------------------
15311 +CLASS_DIAGRAMS         = YES
15312 +HIDE_UNDOC_RELATIONS   = YES
15313 +HAVE_DOT               = NO
15314 +CLASS_GRAPH            = YES
15315 +COLLABORATION_GRAPH    = YES
15316 +UML_LOOK               = NO
15317 +TEMPLATE_RELATIONS     = NO
15318 +INCLUDE_GRAPH          = YES
15319 +INCLUDED_BY_GRAPH      = YES
15320 +CALL_GRAPH             = NO
15321 +GRAPHICAL_HIERARCHY    = YES
15322 +DOT_IMAGE_FORMAT       = png
15323 +DOT_PATH               =
15324 +DOTFILE_DIRS           =
15325 +MAX_DOT_GRAPH_DEPTH    = 1000
15326 +GENERATE_LEGEND        = YES
15327 +DOT_CLEANUP            = YES
15328 +#---------------------------------------------------------------------------
15329 +# Configuration::additions related to the search engine
15330 +#---------------------------------------------------------------------------
15331 +SEARCHENGINE           = NO
15332 --- /dev/null
15333 +++ b/drivers/usb/host/dwc_otg/dummy_audio.c
15334 @@ -0,0 +1,1575 @@
15335 +/*
15336 + * zero.c -- Gadget Zero, for USB development
15337 + *
15338 + * Copyright (C) 2003-2004 David Brownell
15339 + * All rights reserved.
15340 + *
15341 + * Redistribution and use in source and binary forms, with or without
15342 + * modification, are permitted provided that the following conditions
15343 + * are met:
15344 + * 1. Redistributions of source code must retain the above copyright
15345 + *    notice, this list of conditions, and the following disclaimer,
15346 + *    without modification.
15347 + * 2. Redistributions in binary form must reproduce the above copyright
15348 + *    notice, this list of conditions and the following disclaimer in the
15349 + *    documentation and/or other materials provided with the distribution.
15350 + * 3. The names of the above-listed copyright holders may not be used
15351 + *    to endorse or promote products derived from this software without
15352 + *    specific prior written permission.
15353 + *
15354 + * ALTERNATIVELY, this software may be distributed under the terms of the
15355 + * GNU General Public License ("GPL") as published by the Free Software
15356 + * Foundation, either version 2 of that License or (at your option) any
15357 + * later version.
15358 + *
15359 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
15360 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
15361 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
15362 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
15363 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
15364 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
15365 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
15366 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
15367 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
15368 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
15369 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
15370 + */
15371 +
15372 +
15373 +/*
15374 + * Gadget Zero only needs two bulk endpoints, and is an example of how you
15375 + * can write a hardware-agnostic gadget driver running inside a USB device.
15376 + *
15377 + * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
15378 + * affect most of the driver.
15379 + *
15380 + * Use it with the Linux host/master side "usbtest" driver to get a basic
15381 + * functional test of your device-side usb stack, or with "usb-skeleton".
15382 + *
15383 + * It supports two similar configurations.  One sinks whatever the usb host
15384 + * writes, and in return sources zeroes.  The other loops whatever the host
15385 + * writes back, so the host can read it.  Module options include:
15386 + *
15387 + *   buflen=N          default N=4096, buffer size used
15388 + *   qlen=N            default N=32, how many buffers in the loopback queue
15389 + *   loopdefault       default false, list loopback config first
15390 + *
15391 + * Many drivers will only have one configuration, letting them be much
15392 + * simpler if they also don't support high speed operation (like this
15393 + * driver does).
15394 + */
15395 +
15396 +#include <linux/config.h>
15397 +#include <linux/module.h>
15398 +#include <linux/kernel.h>
15399 +#include <linux/delay.h>
15400 +#include <linux/ioport.h>
15401 +#include <linux/sched.h>
15402 +#include <linux/slab.h>
15403 +#include <linux/smp_lock.h>
15404 +#include <linux/errno.h>
15405 +#include <linux/init.h>
15406 +#include <linux/timer.h>
15407 +#include <linux/list.h>
15408 +#include <linux/interrupt.h>
15409 +#include <linux/uts.h>
15410 +#include <linux/version.h>
15411 +#include <linux/device.h>
15412 +#include <linux/moduleparam.h>
15413 +#include <linux/proc_fs.h>
15414 +
15415 +#include <asm/byteorder.h>
15416 +#include <asm/io.h>
15417 +#include <asm/irq.h>
15418 +#include <asm/system.h>
15419 +#include <asm/unaligned.h>
15420 +
15421 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
15422 +# include <linux/usb/ch9.h>
15423 +#else
15424 +# include <linux/usb_ch9.h>
15425 +#endif
15426 +
15427 +#include <linux/usb_gadget.h>
15428 +
15429 +
15430 +/*-------------------------------------------------------------------------*/
15431 +/*-------------------------------------------------------------------------*/
15432 +
15433 +
15434 +static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
15435 +{
15436 +       int     count = 0;
15437 +       u8      c;
15438 +       u16     uchar;
15439 +
15440 +       /* this insists on correct encodings, though not minimal ones.
15441 +        * BUT it currently rejects legit 4-byte UTF-8 code points,
15442 +        * which need surrogate pairs.  (Unicode 3.1 can use them.)
15443 +        */
15444 +       while (len != 0 && (c = (u8) *s++) != 0) {
15445 +               if (unlikely(c & 0x80)) {
15446 +                       // 2-byte sequence:
15447 +                       // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
15448 +                       if ((c & 0xe0) == 0xc0) {
15449 +                               uchar = (c & 0x1f) << 6;
15450 +
15451 +                               c = (u8) *s++;
15452 +                               if ((c & 0xc0) != 0xc0)
15453 +                                       goto fail;
15454 +                               c &= 0x3f;
15455 +                               uchar |= c;
15456 +
15457 +                       // 3-byte sequence (most CJKV characters):
15458 +                       // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
15459 +                       } else if ((c & 0xf0) == 0xe0) {
15460 +                               uchar = (c & 0x0f) << 12;
15461 +
15462 +                               c = (u8) *s++;
15463 +                               if ((c & 0xc0) != 0xc0)
15464 +                                       goto fail;
15465 +                               c &= 0x3f;
15466 +                               uchar |= c << 6;
15467 +
15468 +                               c = (u8) *s++;
15469 +                               if ((c & 0xc0) != 0xc0)
15470 +                                       goto fail;
15471 +                               c &= 0x3f;
15472 +                               uchar |= c;
15473 +
15474 +                               /* no bogus surrogates */
15475 +                               if (0xd800 <= uchar && uchar <= 0xdfff)
15476 +                                       goto fail;
15477 +
15478 +                       // 4-byte sequence (surrogate pairs, currently rare):
15479 +                       // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
15480 +                       //     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
15481 +                       // (uuuuu = wwww + 1)
15482 +                       // FIXME accept the surrogate code points (only)
15483 +
15484 +                       } else
15485 +                               goto fail;
15486 +               } else
15487 +                       uchar = c;
15488 +               put_unaligned (cpu_to_le16 (uchar), cp++);
15489 +               count++;
15490 +               len--;
15491 +       }
15492 +       return count;
15493 +fail:
15494 +       return -1;
15495 +}
15496 +
15497 +
15498 +/**
15499 + * usb_gadget_get_string - fill out a string descriptor
15500 + * @table: of c strings encoded using UTF-8
15501 + * @id: string id, from low byte of wValue in get string descriptor
15502 + * @buf: at least 256 bytes
15503 + *
15504 + * Finds the UTF-8 string matching the ID, and converts it into a
15505 + * string descriptor in utf16-le.
15506 + * Returns length of descriptor (always even) or negative errno
15507 + *
15508 + * If your driver needs stings in multiple languages, you'll probably
15509 + * "switch (wIndex) { ... }"  in your ep0 string descriptor logic,
15510 + * using this routine after choosing which set of UTF-8 strings to use.
15511 + * Note that US-ASCII is a strict subset of UTF-8; any string bytes with
15512 + * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1
15513 + * characters (which are also widely used in C strings).
15514 + */
15515 +int
15516 +usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
15517 +{
15518 +       struct usb_string       *s;
15519 +       int                     len;
15520 +
15521 +       /* descriptor 0 has the language id */
15522 +       if (id == 0) {
15523 +               buf [0] = 4;
15524 +               buf [1] = USB_DT_STRING;
15525 +               buf [2] = (u8) table->language;
15526 +               buf [3] = (u8) (table->language >> 8);
15527 +               return 4;
15528 +       }
15529 +       for (s = table->strings; s && s->s; s++)
15530 +               if (s->id == id)
15531 +                       break;
15532 +
15533 +       /* unrecognized: stall. */
15534 +       if (!s || !s->s)
15535 +               return -EINVAL;
15536 +
15537 +       /* string descriptors have length, tag, then UTF16-LE text */
15538 +       len = min ((size_t) 126, strlen (s->s));
15539 +       memset (buf + 2, 0, 2 * len);   /* zero all the bytes */
15540 +       len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
15541 +       if (len < 0)
15542 +               return -EINVAL;
15543 +       buf [0] = (len + 1) * 2;
15544 +       buf [1] = USB_DT_STRING;
15545 +       return buf [0];
15546 +}
15547 +
15548 +
15549 +/*-------------------------------------------------------------------------*/
15550 +/*-------------------------------------------------------------------------*/
15551 +
15552 +
15553 +/**
15554 + * usb_descriptor_fillbuf - fill buffer with descriptors
15555 + * @buf: Buffer to be filled
15556 + * @buflen: Size of buf
15557 + * @src: Array of descriptor pointers, terminated by null pointer.
15558 + *
15559 + * Copies descriptors into the buffer, returning the length or a
15560 + * negative error code if they can't all be copied.  Useful when
15561 + * assembling descriptors for an associated set of interfaces used
15562 + * as part of configuring a composite device; or in other cases where
15563 + * sets of descriptors need to be marshaled.
15564 + */
15565 +int
15566 +usb_descriptor_fillbuf(void *buf, unsigned buflen,
15567 +               const struct usb_descriptor_header **src)
15568 +{
15569 +       u8      *dest = buf;
15570 +
15571 +       if (!src)
15572 +               return -EINVAL;
15573 +
15574 +       /* fill buffer from src[] until null descriptor ptr */
15575 +       for (; 0 != *src; src++) {
15576 +               unsigned                len = (*src)->bLength;
15577 +
15578 +               if (len > buflen)
15579 +                       return -EINVAL;
15580 +               memcpy(dest, *src, len);
15581 +               buflen -= len;
15582 +               dest += len;
15583 +       }
15584 +       return dest - (u8 *)buf;
15585 +}
15586 +
15587 +
15588 +/**
15589 + * usb_gadget_config_buf - builts a complete configuration descriptor
15590 + * @config: Header for the descriptor, including characteristics such
15591 + *     as power requirements and number of interfaces.
15592 + * @desc: Null-terminated vector of pointers to the descriptors (interface,
15593 + *     endpoint, etc) defining all functions in this device configuration.
15594 + * @buf: Buffer for the resulting configuration descriptor.
15595 + * @length: Length of buffer.  If this is not big enough to hold the
15596 + *     entire configuration descriptor, an error code will be returned.
15597 + *
15598 + * This copies descriptors into the response buffer, building a descriptor
15599 + * for that configuration.  It returns the buffer length or a negative
15600 + * status code.  The config.wTotalLength field is set to match the length
15601 + * of the result, but other descriptor fields (including power usage and
15602 + * interface count) must be set by the caller.
15603 + *
15604 + * Gadget drivers could use this when constructing a config descriptor
15605 + * in response to USB_REQ_GET_DESCRIPTOR.  They will need to patch the
15606 + * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed.
15607 + */
15608 +int usb_gadget_config_buf(
15609 +       const struct usb_config_descriptor      *config,
15610 +       void                                    *buf,
15611 +       unsigned                                length,
15612 +       const struct usb_descriptor_header      **desc
15613 +)
15614 +{
15615 +       struct usb_config_descriptor            *cp = buf;
15616 +       int                                     len;
15617 +
15618 +       /* config descriptor first */
15619 +       if (length < USB_DT_CONFIG_SIZE || !desc)
15620 +               return -EINVAL;
15621 +       *cp = *config;
15622 +
15623 +       /* then interface/endpoint/class/vendor/... */
15624 +       len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
15625 +                       length - USB_DT_CONFIG_SIZE, desc);
15626 +       if (len < 0)
15627 +               return len;
15628 +       len += USB_DT_CONFIG_SIZE;
15629 +       if (len > 0xffff)
15630 +               return -EINVAL;
15631 +
15632 +       /* patch up the config descriptor */
15633 +       cp->bLength = USB_DT_CONFIG_SIZE;
15634 +       cp->bDescriptorType = USB_DT_CONFIG;
15635 +       cp->wTotalLength = cpu_to_le16(len);
15636 +       cp->bmAttributes |= USB_CONFIG_ATT_ONE;
15637 +       return len;
15638 +}
15639 +
15640 +/*-------------------------------------------------------------------------*/
15641 +/*-------------------------------------------------------------------------*/
15642 +
15643 +
15644 +#define RBUF_LEN (1024*1024)
15645 +static int rbuf_start;
15646 +static int rbuf_len;
15647 +static __u8 rbuf[RBUF_LEN];
15648 +
15649 +/*-------------------------------------------------------------------------*/
15650 +
15651 +#define DRIVER_VERSION         "St Patrick's Day 2004"
15652 +
15653 +static const char shortname [] = "zero";
15654 +static const char longname [] = "YAMAHA YST-MS35D USB Speaker  ";
15655 +
15656 +static const char source_sink [] = "source and sink data";
15657 +static const char loopback [] = "loop input to output";
15658 +
15659 +/*-------------------------------------------------------------------------*/
15660 +
15661 +/*
15662 + * driver assumes self-powered hardware, and
15663 + * has no way for users to trigger remote wakeup.
15664 + *
15665 + * this version autoconfigures as much as possible,
15666 + * which is reasonable for most "bulk-only" drivers.
15667 + */
15668 +static const char *EP_IN_NAME;         /* source */
15669 +static const char *EP_OUT_NAME;                /* sink */
15670 +
15671 +/*-------------------------------------------------------------------------*/
15672 +
15673 +/* big enough to hold our biggest descriptor */
15674 +#define USB_BUFSIZ     512
15675 +
15676 +struct zero_dev {
15677 +       spinlock_t              lock;
15678 +       struct usb_gadget       *gadget;
15679 +       struct usb_request      *req;           /* for control responses */
15680 +
15681 +       /* when configured, we have one of two configs:
15682 +        * - source data (in to host) and sink it (out from host)
15683 +        * - or loop it back (out from host back in to host)
15684 +        */
15685 +       u8                      config;
15686 +       struct usb_ep           *in_ep, *out_ep;
15687 +
15688 +       /* autoresume timer */
15689 +       struct timer_list       resume;
15690 +};
15691 +
15692 +#define xprintk(d,level,fmt,args...) \
15693 +       dev_printk(level , &(d)->gadget->dev , fmt , ## args)
15694 +
15695 +#ifdef DEBUG
15696 +#define DBG(dev,fmt,args...) \
15697 +       xprintk(dev , KERN_DEBUG , fmt , ## args)
15698 +#else
15699 +#define DBG(dev,fmt,args...) \
15700 +       do { } while (0)
15701 +#endif /* DEBUG */
15702 +
15703 +#ifdef VERBOSE
15704 +#define VDBG   DBG
15705 +#else
15706 +#define VDBG(dev,fmt,args...) \
15707 +       do { } while (0)
15708 +#endif /* VERBOSE */
15709 +
15710 +#define ERROR(dev,fmt,args...) \
15711 +       xprintk(dev , KERN_ERR , fmt , ## args)
15712 +#define WARN(dev,fmt,args...) \
15713 +       xprintk(dev , KERN_WARNING , fmt , ## args)
15714 +#define INFO(dev,fmt,args...) \
15715 +       xprintk(dev , KERN_INFO , fmt , ## args)
15716 +
15717 +/*-------------------------------------------------------------------------*/
15718 +
15719 +static unsigned buflen = 4096;
15720 +static unsigned qlen = 32;
15721 +static unsigned pattern = 0;
15722 +
15723 +module_param (buflen, uint, S_IRUGO|S_IWUSR);
15724 +module_param (qlen, uint, S_IRUGO|S_IWUSR);
15725 +module_param (pattern, uint, S_IRUGO|S_IWUSR);
15726 +
15727 +/*
15728 + * if it's nonzero, autoresume says how many seconds to wait
15729 + * before trying to wake up the host after suspend.
15730 + */
15731 +static unsigned autoresume = 0;
15732 +module_param (autoresume, uint, 0);
15733 +
15734 +/*
15735 + * Normally the "loopback" configuration is second (index 1) so
15736 + * it's not the default.  Here's where to change that order, to
15737 + * work better with hosts where config changes are problematic.
15738 + * Or controllers (like superh) that only support one config.
15739 + */
15740 +static int loopdefault = 0;
15741 +
15742 +module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
15743 +
15744 +/*-------------------------------------------------------------------------*/
15745 +
15746 +/* Thanks to NetChip Technologies for donating this product ID.
15747 + *
15748 + * DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!
15749 + * Instead:  allocate your own, using normal USB-IF procedures.
15750 + */
15751 +#ifndef        CONFIG_USB_ZERO_HNPTEST
15752 +#define DRIVER_VENDOR_NUM      0x0525          /* NetChip */
15753 +#define DRIVER_PRODUCT_NUM     0xa4a0          /* Linux-USB "Gadget Zero" */
15754 +#else
15755 +#define DRIVER_VENDOR_NUM      0x1a0a          /* OTG test device IDs */
15756 +#define DRIVER_PRODUCT_NUM     0xbadd
15757 +#endif
15758 +
15759 +/*-------------------------------------------------------------------------*/
15760 +
15761 +/*
15762 + * DESCRIPTORS ... most are static, but strings and (full)
15763 + * configuration descriptors are built on demand.
15764 + */
15765 +
15766 +/*
15767 +#define STRING_MANUFACTURER            25
15768 +#define STRING_PRODUCT                 42
15769 +#define STRING_SERIAL                  101
15770 +*/
15771 +#define STRING_MANUFACTURER            1
15772 +#define STRING_PRODUCT                 2
15773 +#define STRING_SERIAL                  3
15774 +
15775 +#define STRING_SOURCE_SINK             250
15776 +#define STRING_LOOPBACK                        251
15777 +
15778 +/*
15779 + * This device advertises two configurations; these numbers work
15780 + * on a pxa250 as well as more flexible hardware.
15781 + */
15782 +#define        CONFIG_SOURCE_SINK      3
15783 +#define        CONFIG_LOOPBACK         2
15784 +
15785 +/*
15786 +static struct usb_device_descriptor
15787 +device_desc = {
15788 +       .bLength =              sizeof device_desc,
15789 +       .bDescriptorType =      USB_DT_DEVICE,
15790 +
15791 +       .bcdUSB =               __constant_cpu_to_le16 (0x0200),
15792 +       .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
15793 +
15794 +       .idVendor =             __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
15795 +       .idProduct =            __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
15796 +       .iManufacturer =        STRING_MANUFACTURER,
15797 +       .iProduct =             STRING_PRODUCT,
15798 +       .iSerialNumber =        STRING_SERIAL,
15799 +       .bNumConfigurations =   2,
15800 +};
15801 +*/
15802 +static struct usb_device_descriptor
15803 +device_desc = {
15804 +       .bLength =              sizeof device_desc,
15805 +       .bDescriptorType =      USB_DT_DEVICE,
15806 +       .bcdUSB =               __constant_cpu_to_le16 (0x0100),
15807 +       .bDeviceClass =         USB_CLASS_PER_INTERFACE,
15808 +       .bDeviceSubClass =      0,
15809 +       .bDeviceProtocol =      0,
15810 +       .bMaxPacketSize0 =      64,
15811 +       .bcdDevice =            __constant_cpu_to_le16 (0x0100),
15812 +       .idVendor =             __constant_cpu_to_le16 (0x0499),
15813 +       .idProduct =            __constant_cpu_to_le16 (0x3002),
15814 +       .iManufacturer =        STRING_MANUFACTURER,
15815 +       .iProduct =             STRING_PRODUCT,
15816 +       .iSerialNumber =        STRING_SERIAL,
15817 +       .bNumConfigurations =   1,
15818 +};
15819 +
15820 +static struct usb_config_descriptor
15821 +z_config = {
15822 +       .bLength =              sizeof z_config,
15823 +       .bDescriptorType =      USB_DT_CONFIG,
15824 +
15825 +       /* compute wTotalLength on the fly */
15826 +       .bNumInterfaces =       2,
15827 +       .bConfigurationValue =  1,
15828 +       .iConfiguration =       0,
15829 +       .bmAttributes =         0x40,
15830 +       .bMaxPower =            0,      /* self-powered */
15831 +};
15832 +
15833 +
15834 +static struct usb_otg_descriptor
15835 +otg_descriptor = {
15836 +       .bLength =              sizeof otg_descriptor,
15837 +       .bDescriptorType =      USB_DT_OTG,
15838 +
15839 +       .bmAttributes =         USB_OTG_SRP,
15840 +};
15841 +
15842 +/* one interface in each configuration */
15843 +#ifdef CONFIG_USB_GADGET_DUALSPEED
15844 +
15845 +/*
15846 + * usb 2.0 devices need to expose both high speed and full speed
15847 + * descriptors, unless they only run at full speed.
15848 + *
15849 + * that means alternate endpoint descriptors (bigger packets)
15850 + * and a "device qualifier" ... plus more construction options
15851 + * for the config descriptor.
15852 + */
15853 +
15854 +static struct usb_qualifier_descriptor
15855 +dev_qualifier = {
15856 +       .bLength =              sizeof dev_qualifier,
15857 +       .bDescriptorType =      USB_DT_DEVICE_QUALIFIER,
15858 +
15859 +       .bcdUSB =               __constant_cpu_to_le16 (0x0200),
15860 +       .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
15861 +
15862 +       .bNumConfigurations =   2,
15863 +};
15864 +
15865 +
15866 +struct usb_cs_as_general_descriptor {
15867 +       __u8  bLength;
15868 +       __u8  bDescriptorType;
15869 +
15870 +       __u8  bDescriptorSubType;
15871 +       __u8  bTerminalLink;
15872 +       __u8  bDelay;
15873 +       __u16  wFormatTag;
15874 +} __attribute__ ((packed));
15875 +
15876 +struct usb_cs_as_format_descriptor {
15877 +       __u8  bLength;
15878 +       __u8  bDescriptorType;
15879 +
15880 +       __u8  bDescriptorSubType;
15881 +       __u8  bFormatType;
15882 +       __u8  bNrChannels;
15883 +       __u8  bSubframeSize;
15884 +       __u8  bBitResolution;
15885 +       __u8  bSamfreqType;
15886 +       __u8  tLowerSamFreq[3];
15887 +       __u8  tUpperSamFreq[3];
15888 +} __attribute__ ((packed));
15889 +
15890 +static const struct usb_interface_descriptor
15891 +z_audio_control_if_desc = {
15892 +       .bLength =              sizeof z_audio_control_if_desc,
15893 +       .bDescriptorType =      USB_DT_INTERFACE,
15894 +       .bInterfaceNumber = 0,
15895 +       .bAlternateSetting = 0,
15896 +       .bNumEndpoints = 0,
15897 +       .bInterfaceClass = USB_CLASS_AUDIO,
15898 +       .bInterfaceSubClass = 0x1,
15899 +       .bInterfaceProtocol = 0,
15900 +       .iInterface = 0,
15901 +};
15902 +
15903 +static const struct usb_interface_descriptor
15904 +z_audio_if_desc = {
15905 +       .bLength =              sizeof z_audio_if_desc,
15906 +       .bDescriptorType =      USB_DT_INTERFACE,
15907 +       .bInterfaceNumber = 1,
15908 +       .bAlternateSetting = 0,
15909 +       .bNumEndpoints = 0,
15910 +       .bInterfaceClass = USB_CLASS_AUDIO,
15911 +       .bInterfaceSubClass = 0x2,
15912 +       .bInterfaceProtocol = 0,
15913 +       .iInterface = 0,
15914 +};
15915 +
15916 +static const struct usb_interface_descriptor
15917 +z_audio_if_desc2 = {
15918 +       .bLength =              sizeof z_audio_if_desc,
15919 +       .bDescriptorType =      USB_DT_INTERFACE,
15920 +       .bInterfaceNumber = 1,
15921 +       .bAlternateSetting = 1,
15922 +       .bNumEndpoints = 1,
15923 +       .bInterfaceClass = USB_CLASS_AUDIO,
15924 +       .bInterfaceSubClass = 0x2,
15925 +       .bInterfaceProtocol = 0,
15926 +       .iInterface = 0,
15927 +};
15928 +
15929 +static const struct usb_cs_as_general_descriptor
15930 +z_audio_cs_as_if_desc = {
15931 +       .bLength = 7,
15932 +       .bDescriptorType = 0x24,
15933 +
15934 +       .bDescriptorSubType = 0x01,
15935 +       .bTerminalLink = 0x01,
15936 +       .bDelay = 0x0,
15937 +       .wFormatTag = __constant_cpu_to_le16 (0x0001)
15938 +};
15939 +
15940 +
15941 +static const struct usb_cs_as_format_descriptor
15942 +z_audio_cs_as_format_desc = {
15943 +       .bLength = 0xe,
15944 +       .bDescriptorType = 0x24,
15945 +
15946 +       .bDescriptorSubType = 2,
15947 +       .bFormatType = 1,
15948 +       .bNrChannels = 1,
15949 +       .bSubframeSize = 1,
15950 +       .bBitResolution = 8,
15951 +       .bSamfreqType = 0,
15952 +       .tLowerSamFreq = {0x7e, 0x13, 0x00},
15953 +       .tUpperSamFreq = {0xe2, 0xd6, 0x00},
15954 +};
15955 +
15956 +static const struct usb_endpoint_descriptor
15957 +z_iso_ep = {
15958 +       .bLength = 0x09,
15959 +       .bDescriptorType = 0x05,
15960 +       .bEndpointAddress = 0x04,
15961 +       .bmAttributes = 0x09,
15962 +       .wMaxPacketSize = 0x0038,
15963 +       .bInterval = 0x01,
15964 +       .bRefresh = 0x00,
15965 +       .bSynchAddress = 0x00,
15966 +};
15967 +
15968 +static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
15969 +
15970 +// 9 bytes
15971 +static char z_ac_interface_header_desc[] =
15972 +{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
15973 +
15974 +// 12 bytes
15975 +static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02,
15976 +                    0x03, 0x00, 0x00, 0x00};
15977 +// 13 bytes
15978 +static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00,
15979 +                    0x02, 0x00, 0x02, 0x00, 0x00};
15980 +// 9 bytes
15981 +static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02,
15982 +                    0x00};
15983 +
15984 +static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00,
15985 +                     0x00};
15986 +
15987 +static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
15988 +
15989 +static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00,
15990 +                     0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
15991 +
15992 +static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
15993 +                     0x00};
15994 +
15995 +static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
15996 +
15997 +static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
15998 +                     0x00};
15999 +
16000 +static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16001 +
16002 +static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
16003 +                     0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16004 +
16005 +static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
16006 +                     0x00};
16007 +
16008 +static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16009 +
16010 +static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
16011 +                      0x00};
16012 +
16013 +static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16014 +
16015 +static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
16016 +                      0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16017 +
16018 +static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
16019 +                      0x00};
16020 +
16021 +static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16022 +
16023 +static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00,
16024 +                      0x00};
16025 +
16026 +static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16027 +
16028 +static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00,
16029 +                      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16030 +
16031 +static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
16032 +                      0x00};
16033 +
16034 +static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16035 +
16036 +static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
16037 +                      0x00};
16038 +
16039 +static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
16040 +
16041 +static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00,
16042 +                      0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
16043 +
16044 +static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
16045 +                      0x00};
16046 +
16047 +static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
16048 +
16049 +
16050 +
16051 +static const struct usb_descriptor_header *z_function [] = {
16052 +       (struct usb_descriptor_header *) &z_audio_control_if_desc,
16053 +       (struct usb_descriptor_header *) &z_ac_interface_header_desc,
16054 +       (struct usb_descriptor_header *) &z_0,
16055 +       (struct usb_descriptor_header *) &z_1,
16056 +       (struct usb_descriptor_header *) &z_2,
16057 +       (struct usb_descriptor_header *) &z_audio_if_desc,
16058 +       (struct usb_descriptor_header *) &z_audio_if_desc2,
16059 +       (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
16060 +       (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
16061 +       (struct usb_descriptor_header *) &z_iso_ep,
16062 +       (struct usb_descriptor_header *) &z_iso_ep2,
16063 +       (struct usb_descriptor_header *) &za_0,
16064 +       (struct usb_descriptor_header *) &za_1,
16065 +       (struct usb_descriptor_header *) &za_2,
16066 +       (struct usb_descriptor_header *) &za_3,
16067 +       (struct usb_descriptor_header *) &za_4,
16068 +       (struct usb_descriptor_header *) &za_5,
16069 +       (struct usb_descriptor_header *) &za_6,
16070 +       (struct usb_descriptor_header *) &za_7,
16071 +       (struct usb_descriptor_header *) &za_8,
16072 +       (struct usb_descriptor_header *) &za_9,
16073 +       (struct usb_descriptor_header *) &za_10,
16074 +       (struct usb_descriptor_header *) &za_11,
16075 +       (struct usb_descriptor_header *) &za_12,
16076 +       (struct usb_descriptor_header *) &za_13,
16077 +       (struct usb_descriptor_header *) &za_14,
16078 +       (struct usb_descriptor_header *) &za_15,
16079 +       (struct usb_descriptor_header *) &za_16,
16080 +       (struct usb_descriptor_header *) &za_17,
16081 +       (struct usb_descriptor_header *) &za_18,
16082 +       (struct usb_descriptor_header *) &za_19,
16083 +       (struct usb_descriptor_header *) &za_20,
16084 +       (struct usb_descriptor_header *) &za_21,
16085 +       (struct usb_descriptor_header *) &za_22,
16086 +       (struct usb_descriptor_header *) &za_23,
16087 +       (struct usb_descriptor_header *) &za_24,
16088 +       NULL,
16089 +};
16090 +
16091 +/* maxpacket and other transfer characteristics vary by speed. */
16092 +#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
16093 +
16094 +#else
16095 +
16096 +/* if there's no high speed support, maxpacket doesn't change. */
16097 +#define ep_desc(g,hs,fs) fs
16098 +
16099 +#endif /* !CONFIG_USB_GADGET_DUALSPEED */
16100 +
16101 +static char                            manufacturer [40];
16102 +//static char                          serial [40];
16103 +static char                            serial [] = "Ser 00 em";
16104 +
16105 +/* static strings, in UTF-8 */
16106 +static struct usb_string               strings [] = {
16107 +       { STRING_MANUFACTURER, manufacturer, },
16108 +       { STRING_PRODUCT, longname, },
16109 +       { STRING_SERIAL, serial, },
16110 +       { STRING_LOOPBACK, loopback, },
16111 +       { STRING_SOURCE_SINK, source_sink, },
16112 +       {  }                    /* end of list */
16113 +};
16114 +
16115 +static struct usb_gadget_strings       stringtab = {
16116 +       .language       = 0x0409,       /* en-us */
16117 +       .strings        = strings,
16118 +};
16119 +
16120 +/*
16121 + * config descriptors are also handcrafted.  these must agree with code
16122 + * that sets configurations, and with code managing interfaces and their
16123 + * altsettings.  other complexity may come from:
16124 + *
16125 + *  - high speed support, including "other speed config" rules
16126 + *  - multiple configurations
16127 + *  - interfaces with alternate settings
16128 + *  - embedded class or vendor-specific descriptors
16129 + *
16130 + * this handles high speed, and has a second config that could as easily
16131 + * have been an alternate interface setting (on most hardware).
16132 + *
16133 + * NOTE:  to demonstrate (and test) more USB capabilities, this driver
16134 + * should include an altsetting to test interrupt transfers, including
16135 + * high bandwidth modes at high speed.  (Maybe work like Intel's test
16136 + * device?)
16137 + */
16138 +static int
16139 +config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
16140 +{
16141 +       int len;
16142 +       const struct usb_descriptor_header **function;
16143 +
16144 +       function = z_function;
16145 +       len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
16146 +       if (len < 0)
16147 +               return len;
16148 +       ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
16149 +       return len;
16150 +}
16151 +
16152 +/*-------------------------------------------------------------------------*/
16153 +
16154 +static struct usb_request *
16155 +alloc_ep_req (struct usb_ep *ep, unsigned length)
16156 +{
16157 +       struct usb_request      *req;
16158 +
16159 +       req = usb_ep_alloc_request (ep, GFP_ATOMIC);
16160 +       if (req) {
16161 +               req->length = length;
16162 +               req->buf = usb_ep_alloc_buffer (ep, length,
16163 +                               &req->dma, GFP_ATOMIC);
16164 +               if (!req->buf) {
16165 +                       usb_ep_free_request (ep, req);
16166 +                       req = NULL;
16167 +               }
16168 +       }
16169 +       return req;
16170 +}
16171 +
16172 +static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
16173 +{
16174 +       if (req->buf)
16175 +               usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
16176 +       usb_ep_free_request (ep, req);
16177 +}
16178 +
16179 +/*-------------------------------------------------------------------------*/
16180 +
16181 +/* optionally require specific source/sink data patterns  */
16182 +
16183 +static int
16184 +check_read_data (
16185 +       struct zero_dev         *dev,
16186 +       struct usb_ep           *ep,
16187 +       struct usb_request      *req
16188 +)
16189 +{
16190 +       unsigned        i;
16191 +       u8              *buf = req->buf;
16192 +
16193 +       for (i = 0; i < req->actual; i++, buf++) {
16194 +               switch (pattern) {
16195 +               /* all-zeroes has no synchronization issues */
16196 +               case 0:
16197 +                       if (*buf == 0)
16198 +                               continue;
16199 +                       break;
16200 +               /* mod63 stays in sync with short-terminated transfers,
16201 +                * or otherwise when host and gadget agree on how large
16202 +                * each usb transfer request should be.  resync is done
16203 +                * with set_interface or set_config.
16204 +                */
16205 +               case 1:
16206 +                       if (*buf == (u8)(i % 63))
16207 +                               continue;
16208 +                       break;
16209 +               }
16210 +               ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
16211 +               usb_ep_set_halt (ep);
16212 +               return -EINVAL;
16213 +       }
16214 +       return 0;
16215 +}
16216 +
16217 +/*-------------------------------------------------------------------------*/
16218 +
16219 +static void zero_reset_config (struct zero_dev *dev)
16220 +{
16221 +       if (dev->config == 0)
16222 +               return;
16223 +
16224 +       DBG (dev, "reset config\n");
16225 +
16226 +       /* just disable endpoints, forcing completion of pending i/o.
16227 +        * all our completion handlers free their requests in this case.
16228 +        */
16229 +       if (dev->in_ep) {
16230 +               usb_ep_disable (dev->in_ep);
16231 +               dev->in_ep = NULL;
16232 +       }
16233 +       if (dev->out_ep) {
16234 +               usb_ep_disable (dev->out_ep);
16235 +               dev->out_ep = NULL;
16236 +       }
16237 +       dev->config = 0;
16238 +       del_timer (&dev->resume);
16239 +}
16240 +
16241 +#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
16242 +
16243 +static void
16244 +zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
16245 +{
16246 +       struct zero_dev *dev = ep->driver_data;
16247 +       int             status = req->status;
16248 +       int i, j;
16249 +
16250 +       switch (status) {
16251 +
16252 +       case 0:                         /* normal completion? */
16253 +               //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
16254 +               for (i=0, j=rbuf_start; i<req->actual; i++) {
16255 +                       //printk ("%02x ", ((__u8*)req->buf)[i]);
16256 +                       rbuf[j] = ((__u8*)req->buf)[i];
16257 +                       j++;
16258 +                       if (j >= RBUF_LEN) j=0;
16259 +               }
16260 +               rbuf_start = j;
16261 +               //printk ("\n\n");
16262 +
16263 +               if (rbuf_len < RBUF_LEN) {
16264 +                       rbuf_len += req->actual;
16265 +                       if (rbuf_len > RBUF_LEN) {
16266 +                               rbuf_len = RBUF_LEN;
16267 +                       }
16268 +               }
16269 +
16270 +               break;
16271 +
16272 +       /* this endpoint is normally active while we're configured */
16273 +       case -ECONNABORTED:             /* hardware forced ep reset */
16274 +       case -ECONNRESET:               /* request dequeued */
16275 +       case -ESHUTDOWN:                /* disconnect from host */
16276 +               VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
16277 +                               req->actual, req->length);
16278 +               if (ep == dev->out_ep)
16279 +                       check_read_data (dev, ep, req);
16280 +               free_ep_req (ep, req);
16281 +               return;
16282 +
16283 +       case -EOVERFLOW:                /* buffer overrun on read means that
16284 +                                        * we didn't provide a big enough
16285 +                                        * buffer.
16286 +                                        */
16287 +       default:
16288 +#if 1
16289 +               DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
16290 +                               status, req->actual, req->length);
16291 +#endif
16292 +       case -EREMOTEIO:                /* short read */
16293 +               break;
16294 +       }
16295 +
16296 +       status = usb_ep_queue (ep, req, GFP_ATOMIC);
16297 +       if (status) {
16298 +               ERROR (dev, "kill %s:  resubmit %d bytes --> %d\n",
16299 +                               ep->name, req->length, status);
16300 +               usb_ep_set_halt (ep);
16301 +               /* FIXME recover later ... somehow */
16302 +       }
16303 +}
16304 +
16305 +static struct usb_request *
16306 +zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
16307 +{
16308 +       struct usb_request      *req;
16309 +       int                     status;
16310 +
16311 +       req = alloc_ep_req (ep, 512);
16312 +       if (!req)
16313 +               return NULL;
16314 +
16315 +       req->complete = zero_isoc_complete;
16316 +
16317 +       status = usb_ep_queue (ep, req, gfp_flags);
16318 +       if (status) {
16319 +               struct zero_dev *dev = ep->driver_data;
16320 +
16321 +               ERROR (dev, "start %s --> %d\n", ep->name, status);
16322 +               free_ep_req (ep, req);
16323 +               req = NULL;
16324 +       }
16325 +
16326 +       return req;
16327 +}
16328 +
16329 +/* change our operational config.  this code must agree with the code
16330 + * that returns config descriptors, and altsetting code.
16331 + *
16332 + * it's also responsible for power management interactions. some
16333 + * configurations might not work with our current power sources.
16334 + *
16335 + * note that some device controller hardware will constrain what this
16336 + * code can do, perhaps by disallowing more than one configuration or
16337 + * by limiting configuration choices (like the pxa2xx).
16338 + */
16339 +static int
16340 +zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
16341 +{
16342 +       int                     result = 0;
16343 +       struct usb_gadget       *gadget = dev->gadget;
16344 +       const struct usb_endpoint_descriptor    *d;
16345 +       struct usb_ep           *ep;
16346 +
16347 +       if (number == dev->config)
16348 +               return 0;
16349 +
16350 +       zero_reset_config (dev);
16351 +
16352 +       gadget_for_each_ep (ep, gadget) {
16353 +
16354 +               if (strcmp (ep->name, "ep4") == 0) {
16355 +
16356 +                       d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
16357 +                       result = usb_ep_enable (ep, d);
16358 +
16359 +                       if (result == 0) {
16360 +                               ep->driver_data = dev;
16361 +                               dev->in_ep = ep;
16362 +
16363 +                               if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
16364 +
16365 +                                       dev->in_ep = ep;
16366 +                                       continue;
16367 +                               }
16368 +
16369 +                               usb_ep_disable (ep);
16370 +                               result = -EIO;
16371 +                       }
16372 +               }
16373 +
16374 +       }
16375 +
16376 +       dev->config = number;
16377 +       return result;
16378 +}
16379 +
16380 +/*-------------------------------------------------------------------------*/
16381 +
16382 +static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
16383 +{
16384 +       if (req->status || req->actual != req->length)
16385 +               DBG ((struct zero_dev *) ep->driver_data,
16386 +                               "setup complete --> %d, %d/%d\n",
16387 +                               req->status, req->actual, req->length);
16388 +}
16389 +
16390 +/*
16391 + * The setup() callback implements all the ep0 functionality that's
16392 + * not handled lower down, in hardware or the hardware driver (like
16393 + * device and endpoint feature flags, and their status).  It's all
16394 + * housekeeping for the gadget function we're implementing.  Most of
16395 + * the work is in config-specific setup.
16396 + */
16397 +static int
16398 +zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
16399 +{
16400 +       struct zero_dev         *dev = get_gadget_data (gadget);
16401 +       struct usb_request      *req = dev->req;
16402 +       int                     value = -EOPNOTSUPP;
16403 +
16404 +       /* usually this stores reply data in the pre-allocated ep0 buffer,
16405 +        * but config change events will reconfigure hardware.
16406 +        */
16407 +       req->zero = 0;
16408 +       switch (ctrl->bRequest) {
16409 +
16410 +       case USB_REQ_GET_DESCRIPTOR:
16411 +
16412 +               switch (ctrl->wValue >> 8) {
16413 +
16414 +               case USB_DT_DEVICE:
16415 +                       value = min (ctrl->wLength, (u16) sizeof device_desc);
16416 +                       memcpy (req->buf, &device_desc, value);
16417 +                       break;
16418 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16419 +               case USB_DT_DEVICE_QUALIFIER:
16420 +                       if (!gadget->is_dualspeed)
16421 +                               break;
16422 +                       value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
16423 +                       memcpy (req->buf, &dev_qualifier, value);
16424 +                       break;
16425 +
16426 +               case USB_DT_OTHER_SPEED_CONFIG:
16427 +                       if (!gadget->is_dualspeed)
16428 +                               break;
16429 +                       // FALLTHROUGH
16430 +#endif /* CONFIG_USB_GADGET_DUALSPEED */
16431 +               case USB_DT_CONFIG:
16432 +                       value = config_buf (gadget, req->buf,
16433 +                                       ctrl->wValue >> 8,
16434 +                                       ctrl->wValue & 0xff);
16435 +                       if (value >= 0)
16436 +                               value = min (ctrl->wLength, (u16) value);
16437 +                       break;
16438 +
16439 +               case USB_DT_STRING:
16440 +                       /* wIndex == language code.
16441 +                        * this driver only handles one language, you can
16442 +                        * add string tables for other languages, using
16443 +                        * any UTF-8 characters
16444 +                        */
16445 +                       value = usb_gadget_get_string (&stringtab,
16446 +                                       ctrl->wValue & 0xff, req->buf);
16447 +                       if (value >= 0) {
16448 +                               value = min (ctrl->wLength, (u16) value);
16449 +                       }
16450 +                       break;
16451 +               }
16452 +               break;
16453 +
16454 +       /* currently two configs, two speeds */
16455 +       case USB_REQ_SET_CONFIGURATION:
16456 +               if (ctrl->bRequestType != 0)
16457 +                       goto unknown;
16458 +
16459 +               spin_lock (&dev->lock);
16460 +               value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
16461 +               spin_unlock (&dev->lock);
16462 +               break;
16463 +       case USB_REQ_GET_CONFIGURATION:
16464 +               if (ctrl->bRequestType != USB_DIR_IN)
16465 +                       goto unknown;
16466 +               *(u8 *)req->buf = dev->config;
16467 +               value = min (ctrl->wLength, (u16) 1);
16468 +               break;
16469 +
16470 +       /* until we add altsetting support, or other interfaces,
16471 +        * only 0/0 are possible.  pxa2xx only supports 0/0 (poorly)
16472 +        * and already killed pending endpoint I/O.
16473 +        */
16474 +       case USB_REQ_SET_INTERFACE:
16475 +
16476 +               if (ctrl->bRequestType != USB_RECIP_INTERFACE)
16477 +                       goto unknown;
16478 +               spin_lock (&dev->lock);
16479 +               if (dev->config) {
16480 +                       u8              config = dev->config;
16481 +
16482 +                       /* resets interface configuration, forgets about
16483 +                        * previous transaction state (queued bufs, etc)
16484 +                        * and re-inits endpoint state (toggle etc)
16485 +                        * no response queued, just zero status == success.
16486 +                        * if we had more than one interface we couldn't
16487 +                        * use this "reset the config" shortcut.
16488 +                        */
16489 +                       zero_reset_config (dev);
16490 +                       zero_set_config (dev, config, GFP_ATOMIC);
16491 +                       value = 0;
16492 +               }
16493 +               spin_unlock (&dev->lock);
16494 +               break;
16495 +       case USB_REQ_GET_INTERFACE:
16496 +               if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
16497 +                       value = ctrl->wLength;
16498 +                       break;
16499 +               }
16500 +               else {
16501 +                       if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
16502 +                               goto unknown;
16503 +                       if (!dev->config)
16504 +                               break;
16505 +                       if (ctrl->wIndex != 0) {
16506 +                               value = -EDOM;
16507 +                               break;
16508 +                       }
16509 +                       *(u8 *)req->buf = 0;
16510 +                       value = min (ctrl->wLength, (u16) 1);
16511 +               }
16512 +               break;
16513 +
16514 +       /*
16515 +        * These are the same vendor-specific requests supported by
16516 +        * Intel's USB 2.0 compliance test devices.  We exceed that
16517 +        * device spec by allowing multiple-packet requests.
16518 +        */
16519 +       case 0x5b:      /* control WRITE test -- fill the buffer */
16520 +               if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
16521 +                       goto unknown;
16522 +               if (ctrl->wValue || ctrl->wIndex)
16523 +                       break;
16524 +               /* just read that many bytes into the buffer */
16525 +               if (ctrl->wLength > USB_BUFSIZ)
16526 +                       break;
16527 +               value = ctrl->wLength;
16528 +               break;
16529 +       case 0x5c:      /* control READ test -- return the buffer */
16530 +               if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
16531 +                       goto unknown;
16532 +               if (ctrl->wValue || ctrl->wIndex)
16533 +                       break;
16534 +               /* expect those bytes are still in the buffer; send back */
16535 +               if (ctrl->wLength > USB_BUFSIZ
16536 +                               || ctrl->wLength != req->length)
16537 +                       break;
16538 +               value = ctrl->wLength;
16539 +               break;
16540 +
16541 +       case 0x01: // SET_CUR
16542 +       case 0x02:
16543 +       case 0x03:
16544 +       case 0x04:
16545 +       case 0x05:
16546 +               value = ctrl->wLength;
16547 +               break;
16548 +       case 0x81:
16549 +               switch (ctrl->wValue) {
16550 +               case 0x0201:
16551 +               case 0x0202:
16552 +                       ((u8*)req->buf)[0] = 0x00;
16553 +                       ((u8*)req->buf)[1] = 0xe3;
16554 +                       break;
16555 +               case 0x0300:
16556 +               case 0x0500:
16557 +                       ((u8*)req->buf)[0] = 0x00;
16558 +                       break;
16559 +               }
16560 +               //((u8*)req->buf)[0] = 0x81;
16561 +               //((u8*)req->buf)[1] = 0x81;
16562 +               value = ctrl->wLength;
16563 +               break;
16564 +       case 0x82:
16565 +               switch (ctrl->wValue) {
16566 +               case 0x0201:
16567 +               case 0x0202:
16568 +                       ((u8*)req->buf)[0] = 0x00;
16569 +                       ((u8*)req->buf)[1] = 0xc3;
16570 +                       break;
16571 +               case 0x0300:
16572 +               case 0x0500:
16573 +                       ((u8*)req->buf)[0] = 0x00;
16574 +                       break;
16575 +               }
16576 +               //((u8*)req->buf)[0] = 0x82;
16577 +               //((u8*)req->buf)[1] = 0x82;
16578 +               value = ctrl->wLength;
16579 +               break;
16580 +       case 0x83:
16581 +               switch (ctrl->wValue) {
16582 +               case 0x0201:
16583 +               case 0x0202:
16584 +                       ((u8*)req->buf)[0] = 0x00;
16585 +                       ((u8*)req->buf)[1] = 0x00;
16586 +                       break;
16587 +               case 0x0300:
16588 +                       ((u8*)req->buf)[0] = 0x60;
16589 +                       break;
16590 +               case 0x0500:
16591 +                       ((u8*)req->buf)[0] = 0x18;
16592 +                       break;
16593 +               }
16594 +               //((u8*)req->buf)[0] = 0x83;
16595 +               //((u8*)req->buf)[1] = 0x83;
16596 +               value = ctrl->wLength;
16597 +               break;
16598 +       case 0x84:
16599 +               switch (ctrl->wValue) {
16600 +               case 0x0201:
16601 +               case 0x0202:
16602 +                       ((u8*)req->buf)[0] = 0x00;
16603 +                       ((u8*)req->buf)[1] = 0x01;
16604 +                       break;
16605 +               case 0x0300:
16606 +               case 0x0500:
16607 +                       ((u8*)req->buf)[0] = 0x08;
16608 +                       break;
16609 +               }
16610 +               //((u8*)req->buf)[0] = 0x84;
16611 +               //((u8*)req->buf)[1] = 0x84;
16612 +               value = ctrl->wLength;
16613 +               break;
16614 +       case 0x85:
16615 +               ((u8*)req->buf)[0] = 0x85;
16616 +               ((u8*)req->buf)[1] = 0x85;
16617 +               value = ctrl->wLength;
16618 +               break;
16619 +
16620 +
16621 +       default:
16622 +unknown:
16623 +               printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
16624 +                       ctrl->bRequestType, ctrl->bRequest,
16625 +                       ctrl->wValue, ctrl->wIndex, ctrl->wLength);
16626 +       }
16627 +
16628 +       /* respond with data transfer before status phase? */
16629 +       if (value >= 0) {
16630 +               req->length = value;
16631 +               req->zero = value < ctrl->wLength
16632 +                               && (value % gadget->ep0->maxpacket) == 0;
16633 +               value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
16634 +               if (value < 0) {
16635 +                       DBG (dev, "ep_queue < 0 --> %d\n", value);
16636 +                       req->status = 0;
16637 +                       zero_setup_complete (gadget->ep0, req);
16638 +               }
16639 +       }
16640 +
16641 +       /* device either stalls (value < 0) or reports success */
16642 +       return value;
16643 +}
16644 +
16645 +static void
16646 +zero_disconnect (struct usb_gadget *gadget)
16647 +{
16648 +       struct zero_dev         *dev = get_gadget_data (gadget);
16649 +       unsigned long           flags;
16650 +
16651 +       spin_lock_irqsave (&dev->lock, flags);
16652 +       zero_reset_config (dev);
16653 +
16654 +       /* a more significant application might have some non-usb
16655 +        * activities to quiesce here, saving resources like power
16656 +        * or pushing the notification up a network stack.
16657 +        */
16658 +       spin_unlock_irqrestore (&dev->lock, flags);
16659 +
16660 +       /* next we may get setup() calls to enumerate new connections;
16661 +        * or an unbind() during shutdown (including removing module).
16662 +        */
16663 +}
16664 +
16665 +static void
16666 +zero_autoresume (unsigned long _dev)
16667 +{
16668 +       struct zero_dev *dev = (struct zero_dev *) _dev;
16669 +       int             status;
16670 +
16671 +       /* normally the host would be woken up for something
16672 +        * more significant than just a timer firing...
16673 +        */
16674 +       if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
16675 +               status = usb_gadget_wakeup (dev->gadget);
16676 +               DBG (dev, "wakeup --> %d\n", status);
16677 +       }
16678 +}
16679 +
16680 +/*-------------------------------------------------------------------------*/
16681 +
16682 +static void
16683 +zero_unbind (struct usb_gadget *gadget)
16684 +{
16685 +       struct zero_dev         *dev = get_gadget_data (gadget);
16686 +
16687 +       DBG (dev, "unbind\n");
16688 +
16689 +       /* we've already been disconnected ... no i/o is active */
16690 +       if (dev->req)
16691 +               free_ep_req (gadget->ep0, dev->req);
16692 +       del_timer_sync (&dev->resume);
16693 +       kfree (dev);
16694 +       set_gadget_data (gadget, NULL);
16695 +}
16696 +
16697 +static int
16698 +zero_bind (struct usb_gadget *gadget)
16699 +{
16700 +       struct zero_dev         *dev;
16701 +       //struct usb_ep         *ep;
16702 +
16703 +       printk("binding\n");
16704 +       /*
16705 +        * DRIVER POLICY CHOICE:  you may want to do this differently.
16706 +        * One thing to avoid is reusing a bcdDevice revision code
16707 +        * with different host-visible configurations or behavior
16708 +        * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
16709 +        */
16710 +       //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
16711 +
16712 +
16713 +       /* ok, we made sense of the hardware ... */
16714 +       dev = kmalloc (sizeof *dev, SLAB_KERNEL);
16715 +       if (!dev)
16716 +               return -ENOMEM;
16717 +       memset (dev, 0, sizeof *dev);
16718 +       spin_lock_init (&dev->lock);
16719 +       dev->gadget = gadget;
16720 +       set_gadget_data (gadget, dev);
16721 +
16722 +       /* preallocate control response and buffer */
16723 +       dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
16724 +       if (!dev->req)
16725 +               goto enomem;
16726 +       dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
16727 +                               &dev->req->dma, GFP_KERNEL);
16728 +       if (!dev->req->buf)
16729 +               goto enomem;
16730 +
16731 +       dev->req->complete = zero_setup_complete;
16732 +
16733 +       device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
16734 +
16735 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16736 +       /* assume ep0 uses the same value for both speeds ... */
16737 +       dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
16738 +
16739 +       /* and that all endpoints are dual-speed */
16740 +       //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
16741 +       //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
16742 +#endif
16743 +
16744 +       usb_gadget_set_selfpowered (gadget);
16745 +
16746 +       init_timer (&dev->resume);
16747 +       dev->resume.function = zero_autoresume;
16748 +       dev->resume.data = (unsigned long) dev;
16749 +
16750 +       gadget->ep0->driver_data = dev;
16751 +
16752 +       INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
16753 +       INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
16754 +               EP_OUT_NAME, EP_IN_NAME);
16755 +
16756 +       snprintf (manufacturer, sizeof manufacturer,
16757 +               UTS_SYSNAME " " UTS_RELEASE " with %s",
16758 +               gadget->name);
16759 +
16760 +       return 0;
16761 +
16762 +enomem:
16763 +       zero_unbind (gadget);
16764 +       return -ENOMEM;
16765 +}
16766 +
16767 +/*-------------------------------------------------------------------------*/
16768 +
16769 +static void
16770 +zero_suspend (struct usb_gadget *gadget)
16771 +{
16772 +       struct zero_dev         *dev = get_gadget_data (gadget);
16773 +
16774 +       if (gadget->speed == USB_SPEED_UNKNOWN)
16775 +               return;
16776 +
16777 +       if (autoresume) {
16778 +               mod_timer (&dev->resume, jiffies + (HZ * autoresume));
16779 +               DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
16780 +       } else
16781 +               DBG (dev, "suspend\n");
16782 +}
16783 +
16784 +static void
16785 +zero_resume (struct usb_gadget *gadget)
16786 +{
16787 +       struct zero_dev         *dev = get_gadget_data (gadget);
16788 +
16789 +       DBG (dev, "resume\n");
16790 +       del_timer (&dev->resume);
16791 +}
16792 +
16793 +
16794 +/*-------------------------------------------------------------------------*/
16795 +
16796 +static struct usb_gadget_driver zero_driver = {
16797 +#ifdef CONFIG_USB_GADGET_DUALSPEED
16798 +       .speed          = USB_SPEED_HIGH,
16799 +#else
16800 +       .speed          = USB_SPEED_FULL,
16801 +#endif
16802 +       .function       = (char *) longname,
16803 +       .bind           = zero_bind,
16804 +       .unbind         = zero_unbind,
16805 +
16806 +       .setup          = zero_setup,
16807 +       .disconnect     = zero_disconnect,
16808 +
16809 +       .suspend        = zero_suspend,
16810 +       .resume         = zero_resume,
16811 +
16812 +       .driver         = {
16813 +               .name           = (char *) shortname,
16814 +               // .shutdown = ...
16815 +               // .suspend = ...
16816 +               // .resume = ...
16817 +       },
16818 +};
16819 +
16820 +MODULE_AUTHOR ("David Brownell");
16821 +MODULE_LICENSE ("Dual BSD/GPL");
16822 +
16823 +static struct proc_dir_entry *pdir, *pfile;
16824 +
16825 +static int isoc_read_data (char *page, char **start,
16826 +                          off_t off, int count,
16827 +                          int *eof, void *data)
16828 +{
16829 +       int i;
16830 +       static int c = 0;
16831 +       static int done = 0;
16832 +       static int s = 0;
16833 +
16834 +/*
16835 +       printk ("\ncount: %d\n", count);
16836 +       printk ("rbuf_start: %d\n", rbuf_start);
16837 +       printk ("rbuf_len: %d\n", rbuf_len);
16838 +       printk ("off: %d\n", off);
16839 +       printk ("start: %p\n\n", *start);
16840 +*/
16841 +       if (done) {
16842 +               c = 0;
16843 +               done = 0;
16844 +               *eof = 1;
16845 +               return 0;
16846 +       }
16847 +
16848 +       if (c == 0) {
16849 +               if (rbuf_len == RBUF_LEN)
16850 +                       s = rbuf_start;
16851 +               else s = 0;
16852 +       }
16853 +
16854 +       for (i=0; i<count && c<rbuf_len; i++, c++) {
16855 +               page[i] = rbuf[(c+s) % RBUF_LEN];
16856 +       }
16857 +       *start = page;
16858 +
16859 +       if (c >= rbuf_len) {
16860 +               *eof = 1;
16861 +               done = 1;
16862 +       }
16863 +
16864 +
16865 +       return i;
16866 +}
16867 +
16868 +static int __init init (void)
16869 +{
16870 +
16871 +       int retval = 0;
16872 +
16873 +       pdir = proc_mkdir("isoc_test", NULL);
16874 +       if(pdir == NULL) {
16875 +               retval = -ENOMEM;
16876 +               printk("Error creating dir\n");
16877 +               goto done;
16878 +       }
16879 +       pdir->owner = THIS_MODULE;
16880 +
16881 +       pfile = create_proc_read_entry("isoc_data",
16882 +                                      0444, pdir,
16883 +                                      isoc_read_data,
16884 +                                      NULL);
16885 +       if (pfile == NULL) {
16886 +               retval = -ENOMEM;
16887 +               printk("Error creating file\n");
16888 +               goto no_file;
16889 +       }
16890 +       pfile->owner = THIS_MODULE;
16891 +
16892 +       return usb_gadget_register_driver (&zero_driver);
16893 +
16894 + no_file:
16895 +       remove_proc_entry("isoc_data", NULL);
16896 + done:
16897 +       return retval;
16898 +}
16899 +module_init (init);
16900 +
16901 +static void __exit cleanup (void)
16902 +{
16903 +
16904 +       usb_gadget_unregister_driver (&zero_driver);
16905 +
16906 +       remove_proc_entry("isoc_data", pdir);
16907 +       remove_proc_entry("isoc_test", NULL);
16908 +}
16909 +module_exit (cleanup);
16910 --- /dev/null
16911 +++ b/drivers/usb/host/dwc_otg/dwc_cfi_common.h
16912 @@ -0,0 +1,142 @@
16913 +/* ==========================================================================
16914 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
16915 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
16916 + * otherwise expressly agreed to in writing between Synopsys and you.
16917 + *
16918 + * The Software IS NOT an item of Licensed Software or Licensed Product under
16919 + * any End User Software License Agreement or Agreement for Licensed Product
16920 + * with Synopsys or any supplement thereto. You are permitted to use and
16921 + * redistribute this Software in source and binary forms, with or without
16922 + * modification, provided that redistributions of source code must retain this
16923 + * notice. You may not view, use, disclose, copy or distribute this file or
16924 + * any information contained herein except pursuant to this license grant from
16925 + * Synopsys. If you do not agree with this notice, including the disclaimer
16926 + * below, then you are not authorized to use the Software.
16927 + *
16928 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
16929 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16930 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16931 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
16932 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16933 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16934 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
16935 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
16936 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
16937 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
16938 + * DAMAGE.
16939 + * ========================================================================== */
16940 +
16941 +#if !defined(__DWC_CFI_COMMON_H__)
16942 +#define __DWC_CFI_COMMON_H__
16943 +
16944 +//#include <linux/types.h>
16945 +
16946 +/**
16947 + * @file
16948 + *
16949 + * This file contains the CFI specific common constants, interfaces
16950 + * (functions and macros) and structures for Linux. No PCD specific
16951 + * data structure or definition is to be included in this file.
16952 + *
16953 + */
16954 +
16955 +/** This is a request for all Core Features */
16956 +#define VEN_CORE_GET_FEATURES          0xB1
16957 +
16958 +/** This is a request to get the value of a specific Core Feature */
16959 +#define VEN_CORE_GET_FEATURE           0xB2
16960 +
16961 +/** This command allows the host to set the value of a specific Core Feature */
16962 +#define VEN_CORE_SET_FEATURE           0xB3
16963 +
16964 +/** This command allows the host to set the default values of
16965 + * either all or any specific Core Feature
16966 + */
16967 +#define VEN_CORE_RESET_FEATURES                0xB4
16968 +
16969 +/** This command forces the PCD to write the deferred values of a Core Features */
16970 +#define VEN_CORE_ACTIVATE_FEATURES     0xB5
16971 +
16972 +/** This request reads a DWORD value from a register at the specified offset */
16973 +#define VEN_CORE_READ_REGISTER         0xB6
16974 +
16975 +/** This request writes a DWORD value into a register at the specified offset */
16976 +#define VEN_CORE_WRITE_REGISTER                0xB7
16977 +
16978 +/** This structure is the header of the Core Features dataset returned to
16979 + *  the Host
16980 + */
16981 +struct cfi_all_features_header {
16982 +/** The features header structure length is */
16983 +#define CFI_ALL_FEATURES_HDR_LEN               8
16984 +       /**
16985 +        * The total length of the features dataset returned to the Host
16986 +        */
16987 +       uint16_t wTotalLen;
16988 +
16989 +       /**
16990 +        * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
16991 +        * This field identifies the version of the CFI Specification with which
16992 +        * the device is compliant.
16993 +        */
16994 +       uint16_t wVersion;
16995 +
16996 +       /** The ID of the Core */
16997 +       uint16_t wCoreID;
16998 +#define CFI_CORE_ID_UDC                1
16999 +#define CFI_CORE_ID_OTG                2
17000 +#define CFI_CORE_ID_WUDEV      3
17001 +
17002 +       /** Number of features returned by VEN_CORE_GET_FEATURES request */
17003 +       uint16_t wNumFeatures;
17004 +} UPACKED;
17005 +
17006 +typedef struct cfi_all_features_header cfi_all_features_header_t;
17007 +
17008 +/** This structure is a header of the Core Feature descriptor dataset returned to
17009 + *  the Host after the VEN_CORE_GET_FEATURES request
17010 + */
17011 +struct cfi_feature_desc_header {
17012 +#define CFI_FEATURE_DESC_HDR_LEN       8
17013 +
17014 +       /** The feature ID */
17015 +       uint16_t wFeatureID;
17016 +
17017 +       /** Length of this feature descriptor in bytes - including the
17018 +        * length of the feature name string
17019 +        */
17020 +       uint16_t wLength;
17021 +
17022 +       /** The data length of this feature in bytes */
17023 +       uint16_t wDataLength;
17024 +
17025 +       /**
17026 +        * Attributes of this features
17027 +        * D0: Access rights
17028 +        * 0 - Read/Write
17029 +        * 1 - Read only
17030 +        */
17031 +       uint8_t bmAttributes;
17032 +#define CFI_FEATURE_ATTR_RO            1
17033 +#define CFI_FEATURE_ATTR_RW            0
17034 +
17035 +       /** Length of the feature name in bytes */
17036 +       uint8_t bNameLen;
17037 +
17038 +       /** The feature name buffer */
17039 +       //uint8_t *name;
17040 +} UPACKED;
17041 +
17042 +typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
17043 +
17044 +/**
17045 + * This structure describes a NULL terminated string referenced by its id field.
17046 + * It is very similar to usb_string structure but has the id field type set to 16-bit.
17047 + */
17048 +struct cfi_string {
17049 +       uint16_t id;
17050 +       const uint8_t *s;
17051 +};
17052 +typedef struct cfi_string cfi_string_t;
17053 +
17054 +#endif
17055 --- /dev/null
17056 +++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.c
17057 @@ -0,0 +1,854 @@
17058 +/* ==========================================================================
17059 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
17060 + * $Revision: #12 $
17061 + * $Date: 2011/10/26 $
17062 + * $Change: 1873028 $
17063 + *
17064 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
17065 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
17066 + * otherwise expressly agreed to in writing between Synopsys and you.
17067 + *
17068 + * The Software IS NOT an item of Licensed Software or Licensed Product under
17069 + * any End User Software License Agreement or Agreement for Licensed Product
17070 + * with Synopsys or any supplement thereto. You are permitted to use and
17071 + * redistribute this Software in source and binary forms, with or without
17072 + * modification, provided that redistributions of source code must retain this
17073 + * notice. You may not view, use, disclose, copy or distribute this file or
17074 + * any information contained herein except pursuant to this license grant from
17075 + * Synopsys. If you do not agree with this notice, including the disclaimer
17076 + * below, then you are not authorized to use the Software.
17077 + *
17078 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
17079 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17080 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17081 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
17082 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17083 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17084 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
17085 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
17086 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
17087 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
17088 + * DAMAGE.
17089 + * ========================================================================== */
17090 +
17091 +#include "dwc_os.h"
17092 +#include "dwc_otg_regs.h"
17093 +#include "dwc_otg_cil.h"
17094 +#include "dwc_otg_adp.h"
17095 +
17096 +/** @file
17097 + *
17098 + * This file contains the most of the Attach Detect Protocol implementation for
17099 + * the driver to support OTG Rev2.0.
17100 + *
17101 + */
17102 +
17103 +void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
17104 +{
17105 +       adpctl_data_t adpctl;
17106 +
17107 +       adpctl.d32 = value;
17108 +       adpctl.b.ar = 0x2;
17109 +
17110 +       DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
17111 +
17112 +       while (adpctl.b.ar) {
17113 +               adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
17114 +       }
17115 +
17116 +}
17117 +
17118 +/**
17119 + * Function is called to read ADP registers
17120 + */
17121 +uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
17122 +{
17123 +       adpctl_data_t adpctl;
17124 +
17125 +       adpctl.d32 = 0;
17126 +       adpctl.b.ar = 0x1;
17127 +
17128 +       DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
17129 +
17130 +       while (adpctl.b.ar) {
17131 +               adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
17132 +       }
17133 +
17134 +       return adpctl.d32;
17135 +}
17136 +
17137 +/**
17138 + * Function is called to read ADPCTL register and filter Write-clear bits
17139 + */
17140 +uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
17141 +{
17142 +       adpctl_data_t adpctl;
17143 +
17144 +       adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17145 +       adpctl.b.adp_tmout_int = 0;
17146 +       adpctl.b.adp_prb_int = 0;
17147 +       adpctl.b.adp_tmout_int = 0;
17148 +
17149 +       return adpctl.d32;
17150 +}
17151 +
17152 +/**
17153 + * Function is called to write ADP registers
17154 + */
17155 +void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
17156 +                           uint32_t set)
17157 +{
17158 +       dwc_otg_adp_write_reg(core_if,
17159 +                             (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
17160 +}
17161 +
17162 +static void adp_sense_timeout(void *ptr)
17163 +{
17164 +       dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
17165 +       core_if->adp.sense_timer_started = 0;
17166 +       DWC_PRINTF("ADP SENSE TIMEOUT\n");
17167 +       if (core_if->adp_enable) {
17168 +               dwc_otg_adp_sense_stop(core_if);
17169 +               dwc_otg_adp_probe_start(core_if);
17170 +       }
17171 +}
17172 +
17173 +/**
17174 + * This function is called when the ADP vbus timer expires. Timeout is 1.1s.
17175 + */
17176 +static void adp_vbuson_timeout(void *ptr)
17177 +{
17178 +       gpwrdn_data_t gpwrdn;
17179 +       dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
17180 +       hprt0_data_t hprt0 = {.d32 = 0 };
17181 +       pcgcctl_data_t pcgcctl = {.d32 = 0 };
17182 +       DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
17183 +       if (core_if) {
17184 +               core_if->adp.vbuson_timer_started = 0;
17185 +               /* Turn off vbus */
17186 +               hprt0.b.prtpwr = 1;
17187 +               DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
17188 +               gpwrdn.d32 = 0;
17189 +
17190 +               /* Power off the core */
17191 +               if (core_if->power_down == 2) {
17192 +                       /* Enable Wakeup Logic */
17193 +//                      gpwrdn.b.wkupactiv = 1;
17194 +                       gpwrdn.b.pmuactv = 0;
17195 +                       gpwrdn.b.pwrdnrstn = 1;
17196 +                       gpwrdn.b.pwrdnclmp = 1;
17197 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
17198 +                                        gpwrdn.d32);
17199 +
17200 +                       /* Suspend the Phy Clock */
17201 +                       pcgcctl.b.stoppclk = 1;
17202 +                       DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
17203 +
17204 +                       /* Switch on VDD */
17205 +//                      gpwrdn.b.wkupactiv = 1;
17206 +                       gpwrdn.b.pmuactv = 1;
17207 +                       gpwrdn.b.pwrdnrstn = 1;
17208 +                       gpwrdn.b.pwrdnclmp = 1;
17209 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
17210 +                                        gpwrdn.d32);
17211 +               } else {
17212 +                       /* Enable Power Down Logic */
17213 +                       gpwrdn.b.pmuintsel = 1;
17214 +                       gpwrdn.b.pmuactv = 1;
17215 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17216 +               }
17217 +
17218 +               /* Power off the core */
17219 +               if (core_if->power_down == 2) {
17220 +                       gpwrdn.d32 = 0;
17221 +                       gpwrdn.b.pwrdnswtch = 1;
17222 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
17223 +                                        gpwrdn.d32, 0);
17224 +               }
17225 +
17226 +               /* Unmask SRP detected interrupt from Power Down Logic */
17227 +               gpwrdn.d32 = 0;
17228 +               gpwrdn.b.srp_det_msk = 1;
17229 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17230 +
17231 +               dwc_otg_adp_probe_start(core_if);
17232 +               dwc_otg_dump_global_registers(core_if);
17233 +               dwc_otg_dump_host_registers(core_if);
17234 +       }
17235 +
17236 +}
17237 +
17238 +/**
17239 + * Start the ADP Initial Probe timer to detect if Port Connected interrupt is
17240 + * not asserted within 1.1 seconds.
17241 + *
17242 + * @param core_if the pointer to core_if strucure.
17243 + */
17244 +void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
17245 +{
17246 +       core_if->adp.vbuson_timer_started = 1;
17247 +       if (core_if->adp.vbuson_timer)
17248 +       {
17249 +               DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
17250 +               /* 1.1 secs + 60ms necessary for cil_hcd_start*/
17251 +               DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
17252 +       } else {
17253 +               DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
17254 +       }
17255 +}
17256 +
17257 +#if 0
17258 +/**
17259 + * Masks all DWC OTG core interrupts
17260 + *
17261 + */
17262 +static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
17263 +{
17264 +       int i;
17265 +       gahbcfg_data_t ahbcfg = {.d32 = 0 };
17266 +
17267 +       /* Mask Host Interrupts */
17268 +
17269 +       /* Clear and disable HCINTs */
17270 +       for (i = 0; i < core_if->core_params->host_channels; i++) {
17271 +               DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
17272 +               DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
17273 +
17274 +       }
17275 +
17276 +       /* Clear and disable HAINT */
17277 +       DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
17278 +       DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
17279 +
17280 +       /* Mask Device Interrupts */
17281 +       if (!core_if->multiproc_int_enable) {
17282 +               /* Clear and disable IN Endpoint interrupts */
17283 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
17284 +               for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
17285 +                       DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
17286 +                                       diepint, 0xFFFFFFFF);
17287 +               }
17288 +
17289 +               /* Clear and disable OUT Endpoint interrupts */
17290 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
17291 +               for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
17292 +                       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
17293 +                                       doepint, 0xFFFFFFFF);
17294 +               }
17295 +
17296 +               /* Clear and disable DAINT */
17297 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
17298 +                               0xFFFFFFFF);
17299 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
17300 +       } else {
17301 +               for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
17302 +                       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
17303 +                                       diepeachintmsk[i], 0);
17304 +                       DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
17305 +                                       diepint, 0xFFFFFFFF);
17306 +               }
17307 +
17308 +               for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
17309 +                       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
17310 +                                       doepeachintmsk[i], 0);
17311 +                       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
17312 +                                       doepint, 0xFFFFFFFF);
17313 +               }
17314 +
17315 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
17316 +                               0);
17317 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
17318 +                               0xFFFFFFFF);
17319 +
17320 +       }
17321 +
17322 +       /* Disable interrupts */
17323 +       ahbcfg.b.glblintrmsk = 1;
17324 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
17325 +
17326 +       /* Disable all interrupts. */
17327 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
17328 +
17329 +       /* Clear any pending interrupts */
17330 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17331 +
17332 +       /* Clear any pending OTG Interrupts */
17333 +       DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
17334 +}
17335 +
17336 +/**
17337 + * Unmask Port Connection Detected interrupt
17338 + *
17339 + */
17340 +static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
17341 +{
17342 +       gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
17343 +
17344 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
17345 +}
17346 +#endif
17347 +
17348 +/**
17349 + * Starts the ADP Probing
17350 + *
17351 + * @param core_if the pointer to core_if structure.
17352 + */
17353 +uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
17354 +{
17355 +
17356 +       adpctl_data_t adpctl = {.d32 = 0};
17357 +       gpwrdn_data_t gpwrdn;
17358 +#if 0
17359 +       adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
17360 +                                                               .b.adp_sns_int = 1, b.adp_tmout_int};
17361 +#endif
17362 +       dwc_otg_disable_global_interrupts(core_if);
17363 +       DWC_PRINTF("ADP Probe Start\n");
17364 +       core_if->adp.probe_enabled = 1;
17365 +
17366 +       adpctl.b.adpres = 1;
17367 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17368 +
17369 +       while (adpctl.b.adpres) {
17370 +               adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17371 +       }
17372 +
17373 +       adpctl.d32 = 0;
17374 +       gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17375 +
17376 +       /* In Host mode unmask SRP detected interrupt */
17377 +       gpwrdn.d32 = 0;
17378 +       gpwrdn.b.sts_chngint_msk = 1;
17379 +       if (!gpwrdn.b.idsts) {
17380 +               gpwrdn.b.srp_det_msk = 1;
17381 +       }
17382 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17383 +
17384 +       adpctl.b.adp_tmout_int_msk = 1;
17385 +       adpctl.b.adp_prb_int_msk = 1;
17386 +       adpctl.b.prb_dschg = 1;
17387 +       adpctl.b.prb_delta = 1;
17388 +       adpctl.b.prb_per = 1;
17389 +       adpctl.b.adpen = 1;
17390 +       adpctl.b.enaprb = 1;
17391 +
17392 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17393 +       DWC_PRINTF("ADP Probe Finish\n");
17394 +       return 0;
17395 +}
17396 +
17397 +/**
17398 + * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted
17399 + * within 3 seconds.
17400 + *
17401 + * @param core_if the pointer to core_if strucure.
17402 + */
17403 +void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
17404 +{
17405 +       core_if->adp.sense_timer_started = 1;
17406 +       DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
17407 +}
17408 +
17409 +/**
17410 + * Starts the ADP Sense
17411 + *
17412 + * @param core_if the pointer to core_if strucure.
17413 + */
17414 +uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
17415 +{
17416 +       adpctl_data_t adpctl;
17417 +
17418 +       DWC_PRINTF("ADP Sense Start\n");
17419 +
17420 +       /* Unmask ADP sense interrupt and mask all other from the core */
17421 +       adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17422 +       adpctl.b.adp_sns_int_msk = 1;
17423 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17424 +       dwc_otg_disable_global_interrupts(core_if); // vahrama
17425 +
17426 +       /* Set ADP reset bit*/
17427 +       adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17428 +       adpctl.b.adpres = 1;
17429 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17430 +
17431 +       while (adpctl.b.adpres) {
17432 +               adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17433 +       }
17434 +
17435 +       adpctl.b.adpres = 0;
17436 +       adpctl.b.adpen = 1;
17437 +       adpctl.b.enasns = 1;
17438 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17439 +
17440 +       dwc_otg_adp_sense_timer_start(core_if);
17441 +
17442 +       return 0;
17443 +}
17444 +
17445 +/**
17446 + * Stops the ADP Probing
17447 + *
17448 + * @param core_if the pointer to core_if strucure.
17449 + */
17450 +uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
17451 +{
17452 +
17453 +       adpctl_data_t adpctl;
17454 +       DWC_PRINTF("Stop ADP probe\n");
17455 +       core_if->adp.probe_enabled = 0;
17456 +       core_if->adp.probe_counter = 0;
17457 +       adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17458 +
17459 +       adpctl.b.adpen = 0;
17460 +       adpctl.b.adp_prb_int = 1;
17461 +       adpctl.b.adp_tmout_int = 1;
17462 +       adpctl.b.adp_sns_int = 1;
17463 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17464 +
17465 +       return 0;
17466 +}
17467 +
17468 +/**
17469 + * Stops the ADP Sensing
17470 + *
17471 + * @param core_if the pointer to core_if strucure.
17472 + */
17473 +uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
17474 +{
17475 +       adpctl_data_t adpctl;
17476 +
17477 +       core_if->adp.sense_enabled = 0;
17478 +
17479 +       adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
17480 +       adpctl.b.enasns = 0;
17481 +       adpctl.b.adp_sns_int = 1;
17482 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17483 +
17484 +       return 0;
17485 +}
17486 +
17487 +/**
17488 + * Called to turn on the VBUS after initial ADP probe in host mode.
17489 + * If port power was already enabled in cil_hcd_start function then
17490 + * only schedule a timer.
17491 + *
17492 + * @param core_if the pointer to core_if structure.
17493 + */
17494 +void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
17495 +{
17496 +       hprt0_data_t hprt0 = {.d32 = 0 };
17497 +       hprt0.d32 = dwc_otg_read_hprt0(core_if);
17498 +       DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
17499 +
17500 +       if (hprt0.b.prtpwr == 0) {
17501 +               hprt0.b.prtpwr = 1;
17502 +               //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
17503 +       }
17504 +
17505 +       dwc_otg_adp_vbuson_timer_start(core_if);
17506 +}
17507 +
17508 +/**
17509 + * Called right after driver is loaded
17510 + * to perform initial actions for ADP
17511 + *
17512 + * @param core_if the pointer to core_if structure.
17513 + * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN
17514 + */
17515 +void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
17516 +{
17517 +       gpwrdn_data_t gpwrdn;
17518 +
17519 +       DWC_PRINTF("ADP Initial Start\n");
17520 +       core_if->adp.adp_started = 1;
17521 +
17522 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17523 +       dwc_otg_disable_global_interrupts(core_if);
17524 +       if (is_host) {
17525 +               DWC_PRINTF("HOST MODE\n");
17526 +               /* Enable Power Down Logic Interrupt*/
17527 +               gpwrdn.d32 = 0;
17528 +               gpwrdn.b.pmuintsel = 1;
17529 +               gpwrdn.b.pmuactv = 1;
17530 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17531 +               /* Initialize first ADP probe to obtain Ramp Time value */
17532 +               core_if->adp.initial_probe = 1;
17533 +               dwc_otg_adp_probe_start(core_if);
17534 +       } else {
17535 +               gotgctl_data_t gotgctl;
17536 +               gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
17537 +               DWC_PRINTF("DEVICE MODE\n");
17538 +               if (gotgctl.b.bsesvld == 0) {
17539 +                       /* Enable Power Down Logic Interrupt*/
17540 +                       gpwrdn.d32 = 0;
17541 +                       DWC_PRINTF("VBUS is not valid - start ADP probe\n");
17542 +                       gpwrdn.b.pmuintsel = 1;
17543 +                       gpwrdn.b.pmuactv = 1;
17544 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
17545 +                       core_if->adp.initial_probe = 1;
17546 +                       dwc_otg_adp_probe_start(core_if);
17547 +               } else {
17548 +                       DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
17549 +                       core_if->op_state = B_PERIPHERAL;
17550 +                       dwc_otg_core_init(core_if);
17551 +                       dwc_otg_enable_global_interrupts(core_if);
17552 +                       cil_pcd_start(core_if);
17553 +                       dwc_otg_dump_global_registers(core_if);
17554 +                       dwc_otg_dump_dev_registers(core_if);
17555 +               }
17556 +       }
17557 +}
17558 +
17559 +void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
17560 +{
17561 +       core_if->adp.adp_started = 0;
17562 +       core_if->adp.initial_probe = 0;
17563 +       core_if->adp.probe_timer_values[0] = -1;
17564 +       core_if->adp.probe_timer_values[1] = -1;
17565 +       core_if->adp.probe_enabled = 0;
17566 +       core_if->adp.sense_enabled = 0;
17567 +       core_if->adp.sense_timer_started = 0;
17568 +       core_if->adp.vbuson_timer_started = 0;
17569 +       core_if->adp.probe_counter = 0;
17570 +       core_if->adp.gpwrdn = 0;
17571 +       core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
17572 +       /* Initialize timers */
17573 +       core_if->adp.sense_timer =
17574 +           DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
17575 +       core_if->adp.vbuson_timer =
17576 +           DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
17577 +       if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
17578 +       {
17579 +               DWC_ERROR("Could not allocate memory for ADP timers\n");
17580 +       }
17581 +}
17582 +
17583 +void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
17584 +{
17585 +       gpwrdn_data_t gpwrdn = { .d32 = 0 };
17586 +       gpwrdn.b.pmuintsel = 1;
17587 +       gpwrdn.b.pmuactv = 1;
17588 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17589 +
17590 +       if (core_if->adp.probe_enabled)
17591 +               dwc_otg_adp_probe_stop(core_if);
17592 +       if (core_if->adp.sense_enabled)
17593 +               dwc_otg_adp_sense_stop(core_if);
17594 +       if (core_if->adp.sense_timer_started)
17595 +               DWC_TIMER_CANCEL(core_if->adp.sense_timer);
17596 +       if (core_if->adp.vbuson_timer_started)
17597 +               DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
17598 +       DWC_TIMER_FREE(core_if->adp.sense_timer);
17599 +       DWC_TIMER_FREE(core_if->adp.vbuson_timer);
17600 +}
17601 +
17602 +/////////////////////////////////////////////////////////////////////
17603 +////////////// ADP Interrupt Handlers ///////////////////////////////
17604 +/////////////////////////////////////////////////////////////////////
17605 +/**
17606 + * This function sets Ramp Timer values
17607 + */
17608 +static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
17609 +{
17610 +       if (core_if->adp.probe_timer_values[0] == -1) {
17611 +               core_if->adp.probe_timer_values[0] = val;
17612 +               core_if->adp.probe_timer_values[1] = -1;
17613 +               return 1;
17614 +       } else {
17615 +               core_if->adp.probe_timer_values[1] =
17616 +                   core_if->adp.probe_timer_values[0];
17617 +               core_if->adp.probe_timer_values[0] = val;
17618 +               return 0;
17619 +       }
17620 +}
17621 +
17622 +/**
17623 + * This function compares Ramp Timer values
17624 + */
17625 +static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
17626 +{
17627 +       uint32_t diff;
17628 +       if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
17629 +                       diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
17630 +       else
17631 +                       diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];
17632 +       if(diff < 2) {
17633 +               return 0;
17634 +       } else {
17635 +               return 1;
17636 +       }
17637 +}
17638 +
17639 +/**
17640 + * This function handles ADP Probe Interrupts
17641 + */
17642 +static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
17643 +                                                uint32_t val)
17644 +{
17645 +       adpctl_data_t adpctl = {.d32 = 0 };
17646 +       gpwrdn_data_t gpwrdn, temp;
17647 +       adpctl.d32 = val;
17648 +
17649 +       temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17650 +       core_if->adp.probe_counter++;
17651 +       core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17652 +       if (adpctl.b.rtim == 0 && !temp.b.idsts){
17653 +               DWC_PRINTF("RTIM value is 0\n");
17654 +               goto exit;
17655 +       }
17656 +       if (set_timer_value(core_if, adpctl.b.rtim) &&
17657 +           core_if->adp.initial_probe) {
17658 +               core_if->adp.initial_probe = 0;
17659 +               dwc_otg_adp_probe_stop(core_if);
17660 +               gpwrdn.d32 = 0;
17661 +               gpwrdn.b.pmuactv = 1;
17662 +               gpwrdn.b.pmuintsel = 1;
17663 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17664 +               DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
17665 +
17666 +               /* check which value is for device mode and which for Host mode */
17667 +               if (!temp.b.idsts) {    /* considered host mode value is 0 */
17668 +                       /*
17669 +                        * Turn on VBUS after initial ADP probe.
17670 +                        */
17671 +                       core_if->op_state = A_HOST;
17672 +                       dwc_otg_enable_global_interrupts(core_if);
17673 +                       DWC_SPINUNLOCK(core_if->lock);
17674 +                       cil_hcd_start(core_if);
17675 +                       dwc_otg_adp_turnon_vbus(core_if);
17676 +                       DWC_SPINLOCK(core_if->lock);
17677 +               } else {
17678 +                       /*
17679 +                        * Initiate SRP after initial ADP probe.
17680 +                        */
17681 +                       dwc_otg_enable_global_interrupts(core_if);
17682 +                       dwc_otg_initiate_srp(core_if);
17683 +               }
17684 +       } else if (core_if->adp.probe_counter > 2){
17685 +               gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17686 +               if (compare_timer_values(core_if)) {
17687 +                       DWC_PRINTF("Difference in timer values !!! \n");
17688 +//                      core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
17689 +                       dwc_otg_adp_probe_stop(core_if);
17690 +
17691 +                       /* Power on the core */
17692 +                       if (core_if->power_down == 2) {
17693 +                               gpwrdn.b.pwrdnswtch = 1;
17694 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
17695 +                                                gpwrdn, 0, gpwrdn.d32);
17696 +                       }
17697 +
17698 +                       /* check which value is for device mode and which for Host mode */
17699 +                       if (!temp.b.idsts) {    /* considered host mode value is 0 */
17700 +                               /* Disable Interrupt from Power Down Logic */
17701 +                               gpwrdn.d32 = 0;
17702 +                               gpwrdn.b.pmuintsel = 1;
17703 +                               gpwrdn.b.pmuactv = 1;
17704 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
17705 +                                                gpwrdn, gpwrdn.d32, 0);
17706 +
17707 +                               /*
17708 +                                * Initialize the Core for Host mode.
17709 +                                */
17710 +                               core_if->op_state = A_HOST;
17711 +                               dwc_otg_core_init(core_if);
17712 +                               dwc_otg_enable_global_interrupts(core_if);
17713 +                               cil_hcd_start(core_if);
17714 +                       } else {
17715 +                               gotgctl_data_t gotgctl;
17716 +                               /* Mask SRP detected interrupt from Power Down Logic */
17717 +                               gpwrdn.d32 = 0;
17718 +                               gpwrdn.b.srp_det_msk = 1;
17719 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
17720 +                                                gpwrdn, gpwrdn.d32, 0);
17721 +
17722 +                               /* Disable Power Down Logic */
17723 +                               gpwrdn.d32 = 0;
17724 +                               gpwrdn.b.pmuintsel = 1;
17725 +                               gpwrdn.b.pmuactv = 1;
17726 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
17727 +                                                gpwrdn, gpwrdn.d32, 0);
17728 +
17729 +                               /*
17730 +                                * Initialize the Core for Device mode.
17731 +                                */
17732 +                               core_if->op_state = B_PERIPHERAL;
17733 +                               dwc_otg_core_init(core_if);
17734 +                               dwc_otg_enable_global_interrupts(core_if);
17735 +                               cil_pcd_start(core_if);
17736 +
17737 +                               gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
17738 +                               if (!gotgctl.b.bsesvld) {
17739 +                                       dwc_otg_initiate_srp(core_if);
17740 +                               }
17741 +                       }
17742 +               }
17743 +               if (core_if->power_down == 2) {
17744 +                       if (gpwrdn.b.bsessvld) {
17745 +                               /* Mask SRP detected interrupt from Power Down Logic */
17746 +                               gpwrdn.d32 = 0;
17747 +                               gpwrdn.b.srp_det_msk = 1;
17748 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17749 +
17750 +                               /* Disable Power Down Logic */
17751 +                               gpwrdn.d32 = 0;
17752 +                               gpwrdn.b.pmuactv = 1;
17753 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
17754 +
17755 +                               /*
17756 +                                * Initialize the Core for Device mode.
17757 +                                */
17758 +                               core_if->op_state = B_PERIPHERAL;
17759 +                               dwc_otg_core_init(core_if);
17760 +                               dwc_otg_enable_global_interrupts(core_if);
17761 +                               cil_pcd_start(core_if);
17762 +                       }
17763 +               }
17764 +       }
17765 +exit:
17766 +       /* Clear interrupt */
17767 +       adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17768 +       adpctl.b.adp_prb_int = 1;
17769 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17770 +
17771 +       return 0;
17772 +}
17773 +
17774 +/**
17775 + * This function hadles ADP Sense Interrupt
17776 + */
17777 +static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
17778 +{
17779 +       adpctl_data_t adpctl;
17780 +       /* Stop ADP Sense timer */
17781 +       DWC_TIMER_CANCEL(core_if->adp.sense_timer);
17782 +
17783 +       /* Restart ADP Sense timer */
17784 +       dwc_otg_adp_sense_timer_start(core_if);
17785 +
17786 +       /* Clear interrupt */
17787 +       adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17788 +       adpctl.b.adp_sns_int = 1;
17789 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17790 +
17791 +       return 0;
17792 +}
17793 +
17794 +/**
17795 + * This function handles ADP Probe Interrupts
17796 + */
17797 +static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
17798 +                                                uint32_t val)
17799 +{
17800 +       adpctl_data_t adpctl = {.d32 = 0 };
17801 +       adpctl.d32 = val;
17802 +       set_timer_value(core_if, adpctl.b.rtim);
17803 +
17804 +       /* Clear interrupt */
17805 +       adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17806 +       adpctl.b.adp_tmout_int = 1;
17807 +       dwc_otg_adp_write_reg(core_if, adpctl.d32);
17808 +
17809 +       return 0;
17810 +}
17811 +
17812 +/**
17813 + * ADP Interrupt handler.
17814 + *
17815 + */
17816 +int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
17817 +{
17818 +       int retval = 0;
17819 +       adpctl_data_t adpctl = {.d32 = 0};
17820 +
17821 +       adpctl.d32 = dwc_otg_adp_read_reg(core_if);
17822 +       DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
17823 +
17824 +       if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
17825 +               DWC_PRINTF("ADP Sense interrupt\n");
17826 +               retval |= dwc_otg_adp_handle_sns_intr(core_if);
17827 +       }
17828 +       if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
17829 +               DWC_PRINTF("ADP timeout interrupt\n");
17830 +               retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
17831 +       }
17832 +       if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
17833 +               DWC_PRINTF("ADP Probe interrupt\n");
17834 +               adpctl.b.adp_prb_int = 1;
17835 +               retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
17836 +       }
17837 +
17838 +//     dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
17839 +       //dwc_otg_adp_write_reg(core_if, adpctl.d32);
17840 +       DWC_PRINTF("RETURN FROM ADP ISR\n");
17841 +
17842 +       return retval;
17843 +}
17844 +
17845 +/**
17846 + *
17847 + * @param core_if Programming view of DWC_otg controller.
17848 + */
17849 +int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
17850 +{
17851 +
17852 +#ifndef DWC_HOST_ONLY
17853 +       hprt0_data_t hprt0;
17854 +       gpwrdn_data_t gpwrdn;
17855 +       DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
17856 +
17857 +       gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
17858 +       /* check which value is for device mode and which for Host mode */
17859 +       if (!gpwrdn.b.idsts) {  /* considered host mode value is 0 */
17860 +               DWC_PRINTF("SRP: Host mode\n");
17861 +
17862 +               if (core_if->adp_enable) {
17863 +                       dwc_otg_adp_probe_stop(core_if);
17864 +
17865 +                       /* Power on the core */
17866 +                       if (core_if->power_down == 2) {
17867 +                               gpwrdn.b.pwrdnswtch = 1;
17868 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
17869 +                                                gpwrdn, 0, gpwrdn.d32);
17870 +                       }
17871 +
17872 +                       core_if->op_state = A_HOST;
17873 +                       dwc_otg_core_init(core_if);
17874 +                       dwc_otg_enable_global_interrupts(core_if);
17875 +                       cil_hcd_start(core_if);
17876 +               }
17877 +
17878 +               /* Turn on the port power bit. */
17879 +               hprt0.d32 = dwc_otg_read_hprt0(core_if);
17880 +               hprt0.b.prtpwr = 1;
17881 +               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
17882 +
17883 +               /* Start the Connection timer. So a message can be displayed
17884 +                * if connect does not occur within 10 seconds. */
17885 +               cil_hcd_session_start(core_if);
17886 +       } else {
17887 +               DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
17888 +               if (core_if->adp_enable) {
17889 +                       dwc_otg_adp_probe_stop(core_if);
17890 +
17891 +                       /* Power on the core */
17892 +                       if (core_if->power_down == 2) {
17893 +                               gpwrdn.b.pwrdnswtch = 1;
17894 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
17895 +                                                gpwrdn, 0, gpwrdn.d32);
17896 +                       }
17897 +
17898 +                       gpwrdn.d32 = 0;
17899 +                       gpwrdn.b.pmuactv = 0;
17900 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
17901 +                                        gpwrdn.d32);
17902 +
17903 +                       core_if->op_state = B_PERIPHERAL;
17904 +                       dwc_otg_core_init(core_if);
17905 +                       dwc_otg_enable_global_interrupts(core_if);
17906 +                       cil_pcd_start(core_if);
17907 +               }
17908 +       }
17909 +#endif
17910 +       return 1;
17911 +}
17912 --- /dev/null
17913 +++ b/drivers/usb/host/dwc_otg/dwc_otg_adp.h
17914 @@ -0,0 +1,80 @@
17915 +/* ==========================================================================
17916 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
17917 + * $Revision: #7 $
17918 + * $Date: 2011/10/24 $
17919 + * $Change: 1871159 $
17920 + *
17921 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
17922 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
17923 + * otherwise expressly agreed to in writing between Synopsys and you.
17924 + *
17925 + * The Software IS NOT an item of Licensed Software or Licensed Product under
17926 + * any End User Software License Agreement or Agreement for Licensed Product
17927 + * with Synopsys or any supplement thereto. You are permitted to use and
17928 + * redistribute this Software in source and binary forms, with or without
17929 + * modification, provided that redistributions of source code must retain this
17930 + * notice. You may not view, use, disclose, copy or distribute this file or
17931 + * any information contained herein except pursuant to this license grant from
17932 + * Synopsys. If you do not agree with this notice, including the disclaimer
17933 + * below, then you are not authorized to use the Software.
17934 + *
17935 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
17936 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17937 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17938 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
17939 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17940 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17941 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
17942 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
17943 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
17944 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
17945 + * DAMAGE.
17946 + * ========================================================================== */
17947 +
17948 +#ifndef __DWC_OTG_ADP_H__
17949 +#define __DWC_OTG_ADP_H__
17950 +
17951 +/**
17952 + * @file
17953 + *
17954 + * This file contains the Attach Detect Protocol interfaces and defines
17955 + * (functions) and structures for Linux.
17956 + *
17957 + */
17958 +
17959 +#define DWC_OTG_ADP_UNATTACHED 0
17960 +#define DWC_OTG_ADP_ATTACHED   1
17961 +#define DWC_OTG_ADP_UNKOWN     2
17962 +
17963 +typedef struct dwc_otg_adp {
17964 +       uint32_t adp_started;
17965 +       uint32_t initial_probe;
17966 +       int32_t probe_timer_values[2];
17967 +       uint32_t probe_enabled;
17968 +       uint32_t sense_enabled;
17969 +       dwc_timer_t *sense_timer;
17970 +       uint32_t sense_timer_started;
17971 +       dwc_timer_t *vbuson_timer;
17972 +       uint32_t vbuson_timer_started;
17973 +       uint32_t attached;
17974 +       uint32_t probe_counter;
17975 +       uint32_t gpwrdn;
17976 +} dwc_otg_adp_t;
17977 +
17978 +/**
17979 + * Attach Detect Protocol functions
17980 + */
17981 +
17982 +extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
17983 +extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
17984 +extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
17985 +extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
17986 +extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
17987 +extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
17988 +extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
17989 +extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
17990 +extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
17991 +extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
17992 +extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
17993 +
17994 +#endif //__DWC_OTG_ADP_H__
17995 --- /dev/null
17996 +++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.c
17997 @@ -0,0 +1,1210 @@
17998 +/* ==========================================================================
17999 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
18000 + * $Revision: #44 $
18001 + * $Date: 2010/11/29 $
18002 + * $Change: 1636033 $
18003 + *
18004 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
18005 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
18006 + * otherwise expressly agreed to in writing between Synopsys and you.
18007 + *
18008 + * The Software IS NOT an item of Licensed Software or Licensed Product under
18009 + * any End User Software License Agreement or Agreement for Licensed Product
18010 + * with Synopsys or any supplement thereto. You are permitted to use and
18011 + * redistribute this Software in source and binary forms, with or without
18012 + * modification, provided that redistributions of source code must retain this
18013 + * notice. You may not view, use, disclose, copy or distribute this file or
18014 + * any information contained herein except pursuant to this license grant from
18015 + * Synopsys. If you do not agree with this notice, including the disclaimer
18016 + * below, then you are not authorized to use the Software.
18017 + *
18018 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
18019 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18020 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18021 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
18022 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18023 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
18024 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
18025 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
18026 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
18027 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
18028 + * DAMAGE.
18029 + * ========================================================================== */
18030 +
18031 +/** @file
18032 + *
18033 + * The diagnostic interface will provide access to the controller for
18034 + * bringing up the hardware and testing.  The Linux driver attributes
18035 + * feature will be used to provide the Linux Diagnostic
18036 + * Interface. These attributes are accessed through sysfs.
18037 + */
18038 +
18039 +/** @page "Linux Module Attributes"
18040 + *
18041 + * The Linux module attributes feature is used to provide the Linux
18042 + * Diagnostic Interface.  These attributes are accessed through sysfs.
18043 + * The diagnostic interface will provide access to the controller for
18044 + * bringing up the hardware and testing.
18045 +
18046 + The following table shows the attributes.
18047 + <table>
18048 + <tr>
18049 + <td><b> Name</b></td>
18050 + <td><b> Description</b></td>
18051 + <td><b> Access</b></td>
18052 + </tr>
18053 +
18054 + <tr>
18055 + <td> mode </td>
18056 + <td> Returns the current mode: 0 for device mode, 1 for host mode</td>
18057 + <td> Read</td>
18058 + </tr>
18059 +
18060 + <tr>
18061 + <td> hnpcapable </td>
18062 + <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register.
18063 + Read returns the current value.</td>
18064 + <td> Read/Write</td>
18065 + </tr>
18066 +
18067 + <tr>
18068 + <td> srpcapable </td>
18069 + <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register.
18070 + Read returns the current value.</td>
18071 + <td> Read/Write</td>
18072 + </tr>
18073 +
18074 + <tr>
18075 + <td> hsic_connect </td>
18076 + <td> Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register.
18077 + Read returns the current value.</td>
18078 + <td> Read/Write</td>
18079 + </tr>
18080 +
18081 + <tr>
18082 + <td> inv_sel_hsic </td>
18083 + <td> Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register.
18084 + Read returns the current value.</td>
18085 + <td> Read/Write</td>
18086 + </tr>
18087 +
18088 + <tr>
18089 + <td> hnp </td>
18090 + <td> Initiates the Host Negotiation Protocol.  Read returns the status.</td>
18091 + <td> Read/Write</td>
18092 + </tr>
18093 +
18094 + <tr>
18095 + <td> srp </td>
18096 + <td> Initiates the Session Request Protocol.  Read returns the status.</td>
18097 + <td> Read/Write</td>
18098 + </tr>
18099 +
18100 + <tr>
18101 + <td> buspower </td>
18102 + <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td>
18103 + <td> Read/Write</td>
18104 + </tr>
18105 +
18106 + <tr>
18107 + <td> bussuspend </td>
18108 + <td> Suspends the USB bus.</td>
18109 + <td> Read/Write</td>
18110 + </tr>
18111 +
18112 + <tr>
18113 + <td> busconnected </td>
18114 + <td> Gets the connection status of the bus</td>
18115 + <td> Read</td>
18116 + </tr>
18117 +
18118 + <tr>
18119 + <td> gotgctl </td>
18120 + <td> Gets or sets the Core Control Status Register.</td>
18121 + <td> Read/Write</td>
18122 + </tr>
18123 +
18124 + <tr>
18125 + <td> gusbcfg </td>
18126 + <td> Gets or sets the Core USB Configuration Register</td>
18127 + <td> Read/Write</td>
18128 + </tr>
18129 +
18130 + <tr>
18131 + <td> grxfsiz </td>
18132 + <td> Gets or sets the Receive FIFO Size Register</td>
18133 + <td> Read/Write</td>
18134 + </tr>
18135 +
18136 + <tr>
18137 + <td> gnptxfsiz </td>
18138 + <td> Gets or sets the non-periodic Transmit Size Register</td>
18139 + <td> Read/Write</td>
18140 + </tr>
18141 +
18142 + <tr>
18143 + <td> gpvndctl </td>
18144 + <td> Gets or sets the PHY Vendor Control Register</td>
18145 + <td> Read/Write</td>
18146 + </tr>
18147 +
18148 + <tr>
18149 + <td> ggpio </td>
18150 + <td> Gets the value in the lower 16-bits of the General Purpose IO Register
18151 + or sets the upper 16 bits.</td>
18152 + <td> Read/Write</td>
18153 + </tr>
18154 +
18155 + <tr>
18156 + <td> guid </td>
18157 + <td> Gets or sets the value of the User ID Register</td>
18158 + <td> Read/Write</td>
18159 + </tr>
18160 +
18161 + <tr>
18162 + <td> gsnpsid </td>
18163 + <td> Gets the value of the Synopsys ID Regester</td>
18164 + <td> Read</td>
18165 + </tr>
18166 +
18167 + <tr>
18168 + <td> devspeed </td>
18169 + <td> Gets or sets the device speed setting in the DCFG register</td>
18170 + <td> Read/Write</td>
18171 + </tr>
18172 +
18173 + <tr>
18174 + <td> enumspeed </td>
18175 + <td> Gets the device enumeration Speed.</td>
18176 + <td> Read</td>
18177 + </tr>
18178 +
18179 + <tr>
18180 + <td> hptxfsiz </td>
18181 + <td> Gets the value of the Host Periodic Transmit FIFO</td>
18182 + <td> Read</td>
18183 + </tr>
18184 +
18185 + <tr>
18186 + <td> hprt0 </td>
18187 + <td> Gets or sets the value in the Host Port Control and Status Register</td>
18188 + <td> Read/Write</td>
18189 + </tr>
18190 +
18191 + <tr>
18192 + <td> regoffset </td>
18193 + <td> Sets the register offset for the next Register Access</td>
18194 + <td> Read/Write</td>
18195 + </tr>
18196 +
18197 + <tr>
18198 + <td> regvalue </td>
18199 + <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td>
18200 + <td> Read/Write</td>
18201 + </tr>
18202 +
18203 + <tr>
18204 + <td> remote_wakeup </td>
18205 + <td> On read, shows the status of Remote Wakeup. On write, initiates a remote
18206 + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote
18207 + Wakeup signalling bit in the Device Control Register is set for 1
18208 + milli-second.</td>
18209 + <td> Read/Write</td>
18210 + </tr>
18211 +
18212 + <tr>
18213 + <td> rem_wakeup_pwrdn </td>
18214 + <td> On read, shows the status core - hibernated or not. On write, initiates
18215 + a remote wakeup of the device from Hibernation. </td>
18216 + <td> Read/Write</td>
18217 + </tr>
18218 +
18219 + <tr>
18220 + <td> mode_ch_tim_en </td>
18221 + <td> This bit is used to enable or disable the host core to wait for 200 PHY
18222 + clock cycles at the end of Resume to change the opmode signal to the PHY to 00
18223 + after Suspend or LPM. </td>
18224 + <td> Read/Write</td>
18225 + </tr>
18226 +
18227 + <tr>
18228 + <td> fr_interval </td>
18229 + <td> On read, shows the value of HFIR Frame Interval. On write, dynamically
18230 + reload HFIR register during runtime. The application can write a value to this
18231 + register only after the Port Enable bit of the Host Port Control and Status
18232 + register (HPRT.PrtEnaPort) has been set </td>
18233 + <td> Read/Write</td>
18234 + </tr>
18235 +
18236 + <tr>
18237 + <td> disconnect_us </td>
18238 + <td> On read, shows the status of disconnect_device_us. On write, sets disconnect_us
18239 + which causes soft disconnect for 100us. Applicable only for device mode of operation.</td>
18240 + <td> Read/Write</td>
18241 + </tr>
18242 +
18243 + <tr>
18244 + <td> regdump </td>
18245 + <td> Dumps the contents of core registers.</td>
18246 + <td> Read</td>
18247 + </tr>
18248 +
18249 + <tr>
18250 + <td> spramdump </td>
18251 + <td> Dumps the contents of core registers.</td>
18252 + <td> Read</td>
18253 + </tr>
18254 +
18255 + <tr>
18256 + <td> hcddump </td>
18257 + <td> Dumps the current HCD state.</td>
18258 + <td> Read</td>
18259 + </tr>
18260 +
18261 + <tr>
18262 + <td> hcd_frrem </td>
18263 + <td> Shows the average value of the Frame Remaining
18264 + field in the Host Frame Number/Frame Remaining register when an SOF interrupt
18265 + occurs. This can be used to determine the average interrupt latency. Also
18266 + shows the average Frame Remaining value for start_transfer and the "a" and
18267 + "b" sample points. The "a" and "b" sample points may be used during debugging
18268 + bto determine how long it takes to execute a section of the HCD code.</td>
18269 + <td> Read</td>
18270 + </tr>
18271 +
18272 + <tr>
18273 + <td> rd_reg_test </td>
18274 + <td> Displays the time required to read the GNPTXFSIZ register many times
18275 + (the output shows the number of times the register is read).
18276 + <td> Read</td>
18277 + </tr>
18278 +
18279 + <tr>
18280 + <td> wr_reg_test </td>
18281 + <td> Displays the time required to write the GNPTXFSIZ register many times
18282 + (the output shows the number of times the register is written).
18283 + <td> Read</td>
18284 + </tr>
18285 +
18286 + <tr>
18287 + <td> lpm_response </td>
18288 + <td> Gets or sets lpm_response mode. Applicable only in device mode.
18289 + <td> Write</td>
18290 + </tr>
18291 +
18292 + <tr>
18293 + <td> sleep_status </td>
18294 + <td> Shows sleep status of device.
18295 + <td> Read</td>
18296 + </tr>
18297 +
18298 + </table>
18299 +
18300 + Example usage:
18301 + To get the current mode:
18302 + cat /sys/devices/lm0/mode
18303 +
18304 + To power down the USB:
18305 + echo 0 > /sys/devices/lm0/buspower
18306 + */
18307 +
18308 +#include "dwc_otg_os_dep.h"
18309 +#include "dwc_os.h"
18310 +#include "dwc_otg_driver.h"
18311 +#include "dwc_otg_attr.h"
18312 +#include "dwc_otg_core_if.h"
18313 +#include "dwc_otg_pcd_if.h"
18314 +#include "dwc_otg_hcd_if.h"
18315 +
18316 +/*
18317 + * MACROs for defining sysfs attribute
18318 + */
18319 +#ifdef LM_INTERFACE
18320 +
18321 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18322 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18323 +{ \
18324 +       struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18325 +       dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);             \
18326 +       uint32_t val; \
18327 +       val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18328 +       return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18329 +}
18330 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18331 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18332 +                                       const char *buf, size_t count) \
18333 +{ \
18334 +       struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18335 +       dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18336 +       uint32_t set = simple_strtoul(buf, NULL, 16); \
18337 +       dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18338 +       return count; \
18339 +}
18340 +
18341 +#elif defined(PCI_INTERFACE)
18342 +
18343 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18344 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18345 +{ \
18346 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);      \
18347 +       uint32_t val; \
18348 +       val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18349 +       return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18350 +}
18351 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18352 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18353 +                                       const char *buf, size_t count) \
18354 +{ \
18355 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
18356 +       uint32_t set = simple_strtoul(buf, NULL, 16); \
18357 +       dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18358 +       return count; \
18359 +}
18360 +
18361 +#elif defined(PLATFORM_INTERFACE)
18362 +
18363 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18364 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18365 +{ \
18366 +        struct platform_device *platform_dev = \
18367 +                container_of(_dev, struct platform_device, dev); \
18368 +        dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev);  \
18369 +       uint32_t val; \
18370 +       DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
18371 +                    __func__, _dev, platform_dev, otg_dev); \
18372 +       val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18373 +       return sprintf (buf, "%s = 0x%x\n", _string_, val); \
18374 +}
18375 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18376 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18377 +                                       const char *buf, size_t count) \
18378 +{ \
18379 +        struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18380 +        dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18381 +       uint32_t set = simple_strtoul(buf, NULL, 16); \
18382 +       dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
18383 +       return count; \
18384 +}
18385 +#endif
18386 +
18387 +/*
18388 + * MACROs for defining sysfs attribute for 32-bit registers
18389 + */
18390 +#ifdef LM_INTERFACE
18391 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18392 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18393 +{ \
18394 +       struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18395 +       dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18396 +       uint32_t val; \
18397 +       val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18398 +       return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18399 +}
18400 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18401 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18402 +                                       const char *buf, size_t count) \
18403 +{ \
18404 +       struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
18405 +       dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
18406 +       uint32_t val = simple_strtoul(buf, NULL, 16); \
18407 +       dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18408 +       return count; \
18409 +}
18410 +#elif defined(PCI_INTERFACE)
18411 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18412 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18413 +{ \
18414 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
18415 +       uint32_t val; \
18416 +       val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18417 +       return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18418 +}
18419 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18420 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18421 +                                       const char *buf, size_t count) \
18422 +{ \
18423 +       dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
18424 +       uint32_t val = simple_strtoul(buf, NULL, 16); \
18425 +       dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18426 +       return count; \
18427 +}
18428 +
18429 +#elif defined(PLATFORM_INTERFACE)
18430 +#include "dwc_otg_dbg.h"
18431 +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18432 +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
18433 +{ \
18434 +       struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18435 +       dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18436 +       uint32_t val; \
18437 +       DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \
18438 +                    __func__, _dev, platform_dev, otg_dev); \
18439 +       val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
18440 +       return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
18441 +}
18442 +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18443 +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
18444 +                                       const char *buf, size_t count) \
18445 +{ \
18446 +       struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \
18447 +       dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \
18448 +       uint32_t val = simple_strtoul(buf, NULL, 16); \
18449 +       dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
18450 +       return count; \
18451 +}
18452 +
18453 +#endif
18454 +
18455 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
18456 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18457 +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
18458 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
18459 +
18460 +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
18461 +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
18462 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
18463 +
18464 +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
18465 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18466 +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
18467 +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
18468 +
18469 +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
18470 +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
18471 +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
18472 +
18473 +/** @name Functions for Show/Store of Attributes */
18474 +/**@{*/
18475 +
18476 +/**
18477 + * Helper function returning the otg_device structure of the given device
18478 + */
18479 +static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
18480 +{
18481 +        dwc_otg_device_t *otg_dev;
18482 +        DWC_OTG_GETDRVDEV(otg_dev, _dev);
18483 +        return otg_dev;
18484 +}
18485 +
18486 +/**
18487 + * Show the register offset of the Register Access.
18488 + */
18489 +static ssize_t regoffset_show(struct device *_dev,
18490 +                             struct device_attribute *attr, char *buf)
18491 +{
18492 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18493 +       return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
18494 +                       otg_dev->os_dep.reg_offset);
18495 +}
18496 +
18497 +/**
18498 + * Set the register offset for the next Register Access        Read/Write
18499 + */
18500 +static ssize_t regoffset_store(struct device *_dev,
18501 +                              struct device_attribute *attr,
18502 +                              const char *buf, size_t count)
18503 +{
18504 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18505 +       uint32_t offset = simple_strtoul(buf, NULL, 16);
18506 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
18507 +       if (offset < SZ_256K) {
18508 +#elif  defined(PCI_INTERFACE)
18509 +       if (offset < 0x00040000) {
18510 +#endif
18511 +               otg_dev->os_dep.reg_offset = offset;
18512 +       } else {
18513 +               dev_err(_dev, "invalid offset\n");
18514 +       }
18515 +
18516 +       return count;
18517 +}
18518 +
18519 +DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
18520 +
18521 +/**
18522 + * Show the value of the register at the offset in the reg_offset
18523 + * attribute.
18524 + */
18525 +static ssize_t regvalue_show(struct device *_dev,
18526 +                            struct device_attribute *attr, char *buf)
18527 +{
18528 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18529 +       uint32_t val;
18530 +       volatile uint32_t *addr;
18531 +
18532 +       if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
18533 +               /* Calculate the address */
18534 +               addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
18535 +                                    (uint8_t *) otg_dev->os_dep.base);
18536 +               val = DWC_READ_REG32(addr);
18537 +               return snprintf(buf,
18538 +                               sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
18539 +                               "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
18540 +                               val);
18541 +       } else {
18542 +               dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
18543 +               return sprintf(buf, "invalid offset\n");
18544 +       }
18545 +}
18546 +
18547 +/**
18548 + * Store the value in the register at the offset in the reg_offset
18549 + * attribute.
18550 + *
18551 + */
18552 +static ssize_t regvalue_store(struct device *_dev,
18553 +                             struct device_attribute *attr,
18554 +                             const char *buf, size_t count)
18555 +{
18556 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18557 +       volatile uint32_t *addr;
18558 +       uint32_t val = simple_strtoul(buf, NULL, 16);
18559 +       //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
18560 +       if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
18561 +               /* Calculate the address */
18562 +               addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
18563 +                                    (uint8_t *) otg_dev->os_dep.base);
18564 +               DWC_WRITE_REG32(addr, val);
18565 +       } else {
18566 +               dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
18567 +                       otg_dev->os_dep.reg_offset);
18568 +       }
18569 +       return count;
18570 +}
18571 +
18572 +DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
18573 +
18574 +/*
18575 + * Attributes
18576 + */
18577 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
18578 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
18579 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
18580 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
18581 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
18582 +
18583 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
18584 +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
18585 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
18586 +
18587 +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
18588 +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
18589 +                            &(otg_dev->core_if->core_global_regs->gusbcfg),
18590 +                            "GUSBCFG");
18591 +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
18592 +                            &(otg_dev->core_if->core_global_regs->grxfsiz),
18593 +                            "GRXFSIZ");
18594 +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
18595 +                            &(otg_dev->core_if->core_global_regs->gnptxfsiz),
18596 +                            "GNPTXFSIZ");
18597 +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
18598 +                            &(otg_dev->core_if->core_global_regs->gpvndctl),
18599 +                            "GPVNDCTL");
18600 +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
18601 +                            &(otg_dev->core_if->core_global_regs->ggpio),
18602 +                            "GGPIO");
18603 +DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
18604 +                            "GUID");
18605 +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
18606 +                            &(otg_dev->core_if->core_global_regs->gsnpsid),
18607 +                            "GSNPSID");
18608 +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
18609 +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
18610 +
18611 +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
18612 +                            &(otg_dev->core_if->core_global_regs->hptxfsiz),
18613 +                            "HPTXFSIZ");
18614 +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
18615 +
18616 +/**
18617 + * @todo Add code to initiate the HNP.
18618 + */
18619 +/**
18620 + * Show the HNP status bit
18621 + */
18622 +static ssize_t hnp_show(struct device *_dev,
18623 +                       struct device_attribute *attr, char *buf)
18624 +{
18625 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18626 +       return sprintf(buf, "HstNegScs = 0x%x\n",
18627 +                      dwc_otg_get_hnpstatus(otg_dev->core_if));
18628 +}
18629 +
18630 +/**
18631 + * Set the HNP Request bit
18632 + */
18633 +static ssize_t hnp_store(struct device *_dev,
18634 +                        struct device_attribute *attr,
18635 +                        const char *buf, size_t count)
18636 +{
18637 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18638 +       uint32_t in = simple_strtoul(buf, NULL, 16);
18639 +       dwc_otg_set_hnpreq(otg_dev->core_if, in);
18640 +       return count;
18641 +}
18642 +
18643 +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
18644 +
18645 +/**
18646 + * @todo Add code to initiate the SRP.
18647 + */
18648 +/**
18649 + * Show the SRP status bit
18650 + */
18651 +static ssize_t srp_show(struct device *_dev,
18652 +                       struct device_attribute *attr, char *buf)
18653 +{
18654 +#ifndef DWC_HOST_ONLY
18655 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18656 +       return sprintf(buf, "SesReqScs = 0x%x\n",
18657 +                      dwc_otg_get_srpstatus(otg_dev->core_if));
18658 +#else
18659 +       return sprintf(buf, "Host Only Mode!\n");
18660 +#endif
18661 +}
18662 +
18663 +/**
18664 + * Set the SRP Request bit
18665 + */
18666 +static ssize_t srp_store(struct device *_dev,
18667 +                        struct device_attribute *attr,
18668 +                        const char *buf, size_t count)
18669 +{
18670 +#ifndef DWC_HOST_ONLY
18671 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18672 +       dwc_otg_pcd_initiate_srp(otg_dev->pcd);
18673 +#endif
18674 +       return count;
18675 +}
18676 +
18677 +DEVICE_ATTR(srp, 0644, srp_show, srp_store);
18678 +
18679 +/**
18680 + * @todo Need to do more for power on/off?
18681 + */
18682 +/**
18683 + * Show the Bus Power status
18684 + */
18685 +static ssize_t buspower_show(struct device *_dev,
18686 +                            struct device_attribute *attr, char *buf)
18687 +{
18688 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18689 +       return sprintf(buf, "Bus Power = 0x%x\n",
18690 +                      dwc_otg_get_prtpower(otg_dev->core_if));
18691 +}
18692 +
18693 +/**
18694 + * Set the Bus Power status
18695 + */
18696 +static ssize_t buspower_store(struct device *_dev,
18697 +                             struct device_attribute *attr,
18698 +                             const char *buf, size_t count)
18699 +{
18700 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18701 +       uint32_t on = simple_strtoul(buf, NULL, 16);
18702 +       dwc_otg_set_prtpower(otg_dev->core_if, on);
18703 +       return count;
18704 +}
18705 +
18706 +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
18707 +
18708 +/**
18709 + * @todo Need to do more for suspend?
18710 + */
18711 +/**
18712 + * Show the Bus Suspend status
18713 + */
18714 +static ssize_t bussuspend_show(struct device *_dev,
18715 +                              struct device_attribute *attr, char *buf)
18716 +{
18717 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18718 +       return sprintf(buf, "Bus Suspend = 0x%x\n",
18719 +                      dwc_otg_get_prtsuspend(otg_dev->core_if));
18720 +}
18721 +
18722 +/**
18723 + * Set the Bus Suspend status
18724 + */
18725 +static ssize_t bussuspend_store(struct device *_dev,
18726 +                               struct device_attribute *attr,
18727 +                               const char *buf, size_t count)
18728 +{
18729 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18730 +       uint32_t in = simple_strtoul(buf, NULL, 16);
18731 +       dwc_otg_set_prtsuspend(otg_dev->core_if, in);
18732 +       return count;
18733 +}
18734 +
18735 +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
18736 +
18737 +/**
18738 + * Show the Mode Change Ready Timer status
18739 + */
18740 +static ssize_t mode_ch_tim_en_show(struct device *_dev,
18741 +                                  struct device_attribute *attr, char *buf)
18742 +{
18743 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18744 +       return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
18745 +                      dwc_otg_get_mode_ch_tim(otg_dev->core_if));
18746 +}
18747 +
18748 +/**
18749 + * Set the Mode Change Ready Timer status
18750 + */
18751 +static ssize_t mode_ch_tim_en_store(struct device *_dev,
18752 +                                   struct device_attribute *attr,
18753 +                                   const char *buf, size_t count)
18754 +{
18755 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18756 +       uint32_t in = simple_strtoul(buf, NULL, 16);
18757 +       dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
18758 +       return count;
18759 +}
18760 +
18761 +DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
18762 +
18763 +/**
18764 + * Show the value of HFIR Frame Interval bitfield
18765 + */
18766 +static ssize_t fr_interval_show(struct device *_dev,
18767 +                               struct device_attribute *attr, char *buf)
18768 +{
18769 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18770 +       return sprintf(buf, "Frame Interval = 0x%x\n",
18771 +                      dwc_otg_get_fr_interval(otg_dev->core_if));
18772 +}
18773 +
18774 +/**
18775 + * Set the HFIR Frame Interval value
18776 + */
18777 +static ssize_t fr_interval_store(struct device *_dev,
18778 +                                struct device_attribute *attr,
18779 +                                const char *buf, size_t count)
18780 +{
18781 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18782 +       uint32_t in = simple_strtoul(buf, NULL, 10);
18783 +       dwc_otg_set_fr_interval(otg_dev->core_if, in);
18784 +       return count;
18785 +}
18786 +
18787 +DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
18788 +
18789 +/**
18790 + * Show the status of Remote Wakeup.
18791 + */
18792 +static ssize_t remote_wakeup_show(struct device *_dev,
18793 +                                 struct device_attribute *attr, char *buf)
18794 +{
18795 +#ifndef DWC_HOST_ONLY
18796 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18797 +
18798 +       return sprintf(buf,
18799 +                      "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
18800 +                      dwc_otg_get_remotewakesig(otg_dev->core_if),
18801 +                      dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
18802 +                      dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
18803 +#else
18804 +       return sprintf(buf, "Host Only Mode!\n");
18805 +#endif /* DWC_HOST_ONLY */
18806 +}
18807 +
18808 +/**
18809 + * Initiate a remote wakeup of the host.  The Device control register
18810 + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable
18811 + * flag is set.
18812 + *
18813 + */
18814 +static ssize_t remote_wakeup_store(struct device *_dev,
18815 +                                  struct device_attribute *attr,
18816 +                                  const char *buf, size_t count)
18817 +{
18818 +#ifndef DWC_HOST_ONLY
18819 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18820 +       uint32_t val = simple_strtoul(buf, NULL, 16);
18821 +
18822 +       if (val & 1) {
18823 +               dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
18824 +       } else {
18825 +               dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
18826 +       }
18827 +#endif /* DWC_HOST_ONLY */
18828 +       return count;
18829 +}
18830 +
18831 +DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
18832 +           remote_wakeup_store);
18833 +
18834 +/**
18835 + * Show the whether core is hibernated or not.
18836 + */
18837 +static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
18838 +                                    struct device_attribute *attr, char *buf)
18839 +{
18840 +#ifndef DWC_HOST_ONLY
18841 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18842 +
18843 +       if (dwc_otg_get_core_state(otg_dev->core_if)) {
18844 +               DWC_PRINTF("Core is in hibernation\n");
18845 +       } else {
18846 +               DWC_PRINTF("Core is not in hibernation\n");
18847 +       }
18848 +#endif /* DWC_HOST_ONLY */
18849 +       return 0;
18850 +}
18851 +
18852 +extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
18853 +                                             int rem_wakeup, int reset);
18854 +
18855 +/**
18856 + * Initiate a remote wakeup of the device to exit from hibernation.
18857 + */
18858 +static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
18859 +                                     struct device_attribute *attr,
18860 +                                     const char *buf, size_t count)
18861 +{
18862 +#ifndef DWC_HOST_ONLY
18863 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18864 +       dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
18865 +#endif
18866 +       return count;
18867 +}
18868 +
18869 +DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
18870 +           rem_wakeup_pwrdn_store);
18871 +
18872 +static ssize_t disconnect_us(struct device *_dev,
18873 +                            struct device_attribute *attr,
18874 +                            const char *buf, size_t count)
18875 +{
18876 +
18877 +#ifndef DWC_HOST_ONLY
18878 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18879 +       uint32_t val = simple_strtoul(buf, NULL, 16);
18880 +       DWC_PRINTF("The Passed value is %04x\n", val);
18881 +
18882 +       dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
18883 +
18884 +#endif /* DWC_HOST_ONLY */
18885 +       return count;
18886 +}
18887 +
18888 +DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
18889 +
18890 +/**
18891 + * Dump global registers and either host or device registers (depending on the
18892 + * current mode of the core).
18893 + */
18894 +static ssize_t regdump_show(struct device *_dev,
18895 +                           struct device_attribute *attr, char *buf)
18896 +{
18897 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18898 +
18899 +       dwc_otg_dump_global_registers(otg_dev->core_if);
18900 +       if (dwc_otg_is_host_mode(otg_dev->core_if)) {
18901 +               dwc_otg_dump_host_registers(otg_dev->core_if);
18902 +       } else {
18903 +               dwc_otg_dump_dev_registers(otg_dev->core_if);
18904 +
18905 +       }
18906 +       return sprintf(buf, "Register Dump\n");
18907 +}
18908 +
18909 +DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0);
18910 +
18911 +/**
18912 + * Dump global registers and either host or device registers (depending on the
18913 + * current mode of the core).
18914 + */
18915 +static ssize_t spramdump_show(struct device *_dev,
18916 +                             struct device_attribute *attr, char *buf)
18917 +{
18918 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18919 +
18920 +       //dwc_otg_dump_spram(otg_dev->core_if);
18921 +
18922 +       return sprintf(buf, "SPRAM Dump\n");
18923 +}
18924 +
18925 +DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0);
18926 +
18927 +/**
18928 + * Dump the current hcd state.
18929 + */
18930 +static ssize_t hcddump_show(struct device *_dev,
18931 +                           struct device_attribute *attr, char *buf)
18932 +{
18933 +#ifndef DWC_DEVICE_ONLY
18934 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18935 +       dwc_otg_hcd_dump_state(otg_dev->hcd);
18936 +#endif /* DWC_DEVICE_ONLY */
18937 +       return sprintf(buf, "HCD Dump\n");
18938 +}
18939 +
18940 +DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0);
18941 +
18942 +/**
18943 + * Dump the average frame remaining at SOF. This can be used to
18944 + * determine average interrupt latency. Frame remaining is also shown for
18945 + * start transfer and two additional sample points.
18946 + */
18947 +static ssize_t hcd_frrem_show(struct device *_dev,
18948 +                             struct device_attribute *attr, char *buf)
18949 +{
18950 +#ifndef DWC_DEVICE_ONLY
18951 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18952 +
18953 +       dwc_otg_hcd_dump_frrem(otg_dev->hcd);
18954 +#endif /* DWC_DEVICE_ONLY */
18955 +       return sprintf(buf, "HCD Dump Frame Remaining\n");
18956 +}
18957 +
18958 +DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0);
18959 +
18960 +/**
18961 + * Displays the time required to read the GNPTXFSIZ register many times (the
18962 + * output shows the number of times the register is read).
18963 + */
18964 +#define RW_REG_COUNT 10000000
18965 +#define MSEC_PER_JIFFIE 1000/HZ
18966 +static ssize_t rd_reg_test_show(struct device *_dev,
18967 +                               struct device_attribute *attr, char *buf)
18968 +{
18969 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18970 +       int i;
18971 +       int time;
18972 +       int start_jiffies;
18973 +
18974 +       printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
18975 +              HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
18976 +       start_jiffies = jiffies;
18977 +       for (i = 0; i < RW_REG_COUNT; i++) {
18978 +               dwc_otg_get_gnptxfsiz(otg_dev->core_if);
18979 +       }
18980 +       time = jiffies - start_jiffies;
18981 +       return sprintf(buf,
18982 +                      "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
18983 +                      RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
18984 +}
18985 +
18986 +DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0);
18987 +
18988 +/**
18989 + * Displays the time required to write the GNPTXFSIZ register many times (the
18990 + * output shows the number of times the register is written).
18991 + */
18992 +static ssize_t wr_reg_test_show(struct device *_dev,
18993 +                               struct device_attribute *attr, char *buf)
18994 +{
18995 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
18996 +       uint32_t reg_val;
18997 +       int i;
18998 +       int time;
18999 +       int start_jiffies;
19000 +
19001 +       printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
19002 +              HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
19003 +       reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
19004 +       start_jiffies = jiffies;
19005 +       for (i = 0; i < RW_REG_COUNT; i++) {
19006 +               dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
19007 +       }
19008 +       time = jiffies - start_jiffies;
19009 +       return sprintf(buf,
19010 +                      "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
19011 +                      RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
19012 +}
19013 +
19014 +DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0);
19015 +
19016 +#ifdef CONFIG_USB_DWC_OTG_LPM
19017 +
19018 +/**
19019 +* Show the lpm_response attribute.
19020 +*/
19021 +static ssize_t lpmresp_show(struct device *_dev,
19022 +                           struct device_attribute *attr, char *buf)
19023 +{
19024 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19025 +
19026 +       if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
19027 +               return sprintf(buf, "** LPM is DISABLED **\n");
19028 +
19029 +       if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
19030 +               return sprintf(buf, "** Current mode is not device mode\n");
19031 +       }
19032 +       return sprintf(buf, "lpm_response = %d\n",
19033 +                      dwc_otg_get_lpmresponse(otg_dev->core_if));
19034 +}
19035 +
19036 +/**
19037 +* Store the lpm_response attribute.
19038 +*/
19039 +static ssize_t lpmresp_store(struct device *_dev,
19040 +                            struct device_attribute *attr,
19041 +                            const char *buf, size_t count)
19042 +{
19043 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19044 +       uint32_t val = simple_strtoul(buf, NULL, 16);
19045 +
19046 +       if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
19047 +               return 0;
19048 +       }
19049 +
19050 +       if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
19051 +               return 0;
19052 +       }
19053 +
19054 +       dwc_otg_set_lpmresponse(otg_dev->core_if, val);
19055 +       return count;
19056 +}
19057 +
19058 +DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
19059 +
19060 +/**
19061 +* Show the sleep_status attribute.
19062 +*/
19063 +static ssize_t sleepstatus_show(struct device *_dev,
19064 +                               struct device_attribute *attr, char *buf)
19065 +{
19066 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19067 +       return sprintf(buf, "Sleep Status = %d\n",
19068 +                      dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
19069 +}
19070 +
19071 +/**
19072 + * Store the sleep_status attribure.
19073 + */
19074 +static ssize_t sleepstatus_store(struct device *_dev,
19075 +                                struct device_attribute *attr,
19076 +                                const char *buf, size_t count)
19077 +{
19078 +        dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev);
19079 +       dwc_otg_core_if_t *core_if = otg_dev->core_if;
19080 +
19081 +       if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
19082 +               if (dwc_otg_is_host_mode(core_if)) {
19083 +
19084 +                       DWC_PRINTF("Host initiated resume\n");
19085 +                       dwc_otg_set_prtresume(otg_dev->core_if, 1);
19086 +               }
19087 +       }
19088 +
19089 +       return count;
19090 +}
19091 +
19092 +DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
19093 +           sleepstatus_store);
19094 +
19095 +#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
19096 +
19097 +/**@}*/
19098 +
19099 +/**
19100 + * Create the device files
19101 + */
19102 +void dwc_otg_attr_create(
19103 +#ifdef LM_INTERFACE
19104 +       struct lm_device *dev
19105 +#elif  defined(PCI_INTERFACE)
19106 +       struct pci_dev *dev
19107 +#elif  defined(PLATFORM_INTERFACE)
19108 +        struct platform_device *dev
19109 +#endif
19110 +    )
19111 +{
19112 +       int error;
19113 +
19114 +       error = device_create_file(&dev->dev, &dev_attr_regoffset);
19115 +       error = device_create_file(&dev->dev, &dev_attr_regvalue);
19116 +       error = device_create_file(&dev->dev, &dev_attr_mode);
19117 +       error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
19118 +       error = device_create_file(&dev->dev, &dev_attr_srpcapable);
19119 +       error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
19120 +       error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
19121 +       error = device_create_file(&dev->dev, &dev_attr_hnp);
19122 +       error = device_create_file(&dev->dev, &dev_attr_srp);
19123 +       error = device_create_file(&dev->dev, &dev_attr_buspower);
19124 +       error = device_create_file(&dev->dev, &dev_attr_bussuspend);
19125 +       error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
19126 +       error = device_create_file(&dev->dev, &dev_attr_fr_interval);
19127 +       error = device_create_file(&dev->dev, &dev_attr_busconnected);
19128 +       error = device_create_file(&dev->dev, &dev_attr_gotgctl);
19129 +       error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
19130 +       error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
19131 +       error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
19132 +       error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
19133 +       error = device_create_file(&dev->dev, &dev_attr_ggpio);
19134 +       error = device_create_file(&dev->dev, &dev_attr_guid);
19135 +       error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
19136 +       error = device_create_file(&dev->dev, &dev_attr_devspeed);
19137 +       error = device_create_file(&dev->dev, &dev_attr_enumspeed);
19138 +       error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
19139 +       error = device_create_file(&dev->dev, &dev_attr_hprt0);
19140 +       error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
19141 +       error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
19142 +       error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
19143 +       error = device_create_file(&dev->dev, &dev_attr_regdump);
19144 +       error = device_create_file(&dev->dev, &dev_attr_spramdump);
19145 +       error = device_create_file(&dev->dev, &dev_attr_hcddump);
19146 +       error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
19147 +       error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
19148 +       error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
19149 +#ifdef CONFIG_USB_DWC_OTG_LPM
19150 +       error = device_create_file(&dev->dev, &dev_attr_lpm_response);
19151 +       error = device_create_file(&dev->dev, &dev_attr_sleep_status);
19152 +#endif
19153 +}
19154 +
19155 +/**
19156 + * Remove the device files
19157 + */
19158 +void dwc_otg_attr_remove(
19159 +#ifdef LM_INTERFACE
19160 +       struct lm_device *dev
19161 +#elif  defined(PCI_INTERFACE)
19162 +       struct pci_dev *dev
19163 +#elif  defined(PLATFORM_INTERFACE)
19164 +       struct platform_device *dev
19165 +#endif
19166 +    )
19167 +{
19168 +       device_remove_file(&dev->dev, &dev_attr_regoffset);
19169 +       device_remove_file(&dev->dev, &dev_attr_regvalue);
19170 +       device_remove_file(&dev->dev, &dev_attr_mode);
19171 +       device_remove_file(&dev->dev, &dev_attr_hnpcapable);
19172 +       device_remove_file(&dev->dev, &dev_attr_srpcapable);
19173 +       device_remove_file(&dev->dev, &dev_attr_hsic_connect);
19174 +       device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
19175 +       device_remove_file(&dev->dev, &dev_attr_hnp);
19176 +       device_remove_file(&dev->dev, &dev_attr_srp);
19177 +       device_remove_file(&dev->dev, &dev_attr_buspower);
19178 +       device_remove_file(&dev->dev, &dev_attr_bussuspend);
19179 +       device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
19180 +       device_remove_file(&dev->dev, &dev_attr_fr_interval);
19181 +       device_remove_file(&dev->dev, &dev_attr_busconnected);
19182 +       device_remove_file(&dev->dev, &dev_attr_gotgctl);
19183 +       device_remove_file(&dev->dev, &dev_attr_gusbcfg);
19184 +       device_remove_file(&dev->dev, &dev_attr_grxfsiz);
19185 +       device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
19186 +       device_remove_file(&dev->dev, &dev_attr_gpvndctl);
19187 +       device_remove_file(&dev->dev, &dev_attr_ggpio);
19188 +       device_remove_file(&dev->dev, &dev_attr_guid);
19189 +       device_remove_file(&dev->dev, &dev_attr_gsnpsid);
19190 +       device_remove_file(&dev->dev, &dev_attr_devspeed);
19191 +       device_remove_file(&dev->dev, &dev_attr_enumspeed);
19192 +       device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
19193 +       device_remove_file(&dev->dev, &dev_attr_hprt0);
19194 +       device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
19195 +       device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
19196 +       device_remove_file(&dev->dev, &dev_attr_disconnect_us);
19197 +       device_remove_file(&dev->dev, &dev_attr_regdump);
19198 +       device_remove_file(&dev->dev, &dev_attr_spramdump);
19199 +       device_remove_file(&dev->dev, &dev_attr_hcddump);
19200 +       device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
19201 +       device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
19202 +       device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
19203 +#ifdef CONFIG_USB_DWC_OTG_LPM
19204 +       device_remove_file(&dev->dev, &dev_attr_lpm_response);
19205 +       device_remove_file(&dev->dev, &dev_attr_sleep_status);
19206 +#endif
19207 +}
19208 --- /dev/null
19209 +++ b/drivers/usb/host/dwc_otg/dwc_otg_attr.h
19210 @@ -0,0 +1,89 @@
19211 +/* ==========================================================================
19212 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
19213 + * $Revision: #13 $
19214 + * $Date: 2010/06/21 $
19215 + * $Change: 1532021 $
19216 + *
19217 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
19218 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
19219 + * otherwise expressly agreed to in writing between Synopsys and you.
19220 + *
19221 + * The Software IS NOT an item of Licensed Software or Licensed Product under
19222 + * any End User Software License Agreement or Agreement for Licensed Product
19223 + * with Synopsys or any supplement thereto. You are permitted to use and
19224 + * redistribute this Software in source and binary forms, with or without
19225 + * modification, provided that redistributions of source code must retain this
19226 + * notice. You may not view, use, disclose, copy or distribute this file or
19227 + * any information contained herein except pursuant to this license grant from
19228 + * Synopsys. If you do not agree with this notice, including the disclaimer
19229 + * below, then you are not authorized to use the Software.
19230 + *
19231 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
19232 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19233 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19234 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
19235 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19236 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19237 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
19238 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
19239 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
19240 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
19241 + * DAMAGE.
19242 + * ========================================================================== */
19243 +
19244 +#if !defined(__DWC_OTG_ATTR_H__)
19245 +#define __DWC_OTG_ATTR_H__
19246 +
19247 +/** @file
19248 + * This file contains the interface to the Linux device attributes.
19249 + */
19250 +extern struct device_attribute dev_attr_regoffset;
19251 +extern struct device_attribute dev_attr_regvalue;
19252 +
19253 +extern struct device_attribute dev_attr_mode;
19254 +extern struct device_attribute dev_attr_hnpcapable;
19255 +extern struct device_attribute dev_attr_srpcapable;
19256 +extern struct device_attribute dev_attr_hnp;
19257 +extern struct device_attribute dev_attr_srp;
19258 +extern struct device_attribute dev_attr_buspower;
19259 +extern struct device_attribute dev_attr_bussuspend;
19260 +extern struct device_attribute dev_attr_mode_ch_tim_en;
19261 +extern struct device_attribute dev_attr_fr_interval;
19262 +extern struct device_attribute dev_attr_busconnected;
19263 +extern struct device_attribute dev_attr_gotgctl;
19264 +extern struct device_attribute dev_attr_gusbcfg;
19265 +extern struct device_attribute dev_attr_grxfsiz;
19266 +extern struct device_attribute dev_attr_gnptxfsiz;
19267 +extern struct device_attribute dev_attr_gpvndctl;
19268 +extern struct device_attribute dev_attr_ggpio;
19269 +extern struct device_attribute dev_attr_guid;
19270 +extern struct device_attribute dev_attr_gsnpsid;
19271 +extern struct device_attribute dev_attr_devspeed;
19272 +extern struct device_attribute dev_attr_enumspeed;
19273 +extern struct device_attribute dev_attr_hptxfsiz;
19274 +extern struct device_attribute dev_attr_hprt0;
19275 +#ifdef CONFIG_USB_DWC_OTG_LPM
19276 +extern struct device_attribute dev_attr_lpm_response;
19277 +extern struct device_attribute devi_attr_sleep_status;
19278 +#endif
19279 +
19280 +void dwc_otg_attr_create(
19281 +#ifdef LM_INTERFACE
19282 +                               struct lm_device *dev
19283 +#elif  defined(PCI_INTERFACE)
19284 +                               struct pci_dev *dev
19285 +#elif  defined(PLATFORM_INTERFACE)
19286 +       struct platform_device *dev
19287 +#endif
19288 +    );
19289 +
19290 +void dwc_otg_attr_remove(
19291 +#ifdef LM_INTERFACE
19292 +                               struct lm_device *dev
19293 +#elif  defined(PCI_INTERFACE)
19294 +                               struct pci_dev *dev
19295 +#elif  defined(PLATFORM_INTERFACE)
19296 +       struct platform_device *dev
19297 +#endif
19298 +    );
19299 +#endif
19300 --- /dev/null
19301 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.c
19302 @@ -0,0 +1,1876 @@
19303 +/* ==========================================================================
19304 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
19305 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
19306 + * otherwise expressly agreed to in writing between Synopsys and you.
19307 + *
19308 + * The Software IS NOT an item of Licensed Software or Licensed Product under
19309 + * any End User Software License Agreement or Agreement for Licensed Product
19310 + * with Synopsys or any supplement thereto. You are permitted to use and
19311 + * redistribute this Software in source and binary forms, with or without
19312 + * modification, provided that redistributions of source code must retain this
19313 + * notice. You may not view, use, disclose, copy or distribute this file or
19314 + * any information contained herein except pursuant to this license grant from
19315 + * Synopsys. If you do not agree with this notice, including the disclaimer
19316 + * below, then you are not authorized to use the Software.
19317 + *
19318 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
19319 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19320 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19321 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
19322 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19323 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19324 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
19325 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
19326 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
19327 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
19328 + * DAMAGE.
19329 + * ========================================================================== */
19330 +
19331 +/** @file
19332 + *
19333 + * This file contains the most of the CFI(Core Feature Interface)
19334 + * implementation for the OTG.
19335 + */
19336 +
19337 +#ifdef DWC_UTE_CFI
19338 +
19339 +#include "dwc_otg_pcd.h"
19340 +#include "dwc_otg_cfi.h"
19341 +
19342 +/** This definition should actually migrate to the Portability Library */
19343 +#define DWC_CONSTANT_CPU_TO_LE16(x) (x)
19344 +
19345 +extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
19346 +
19347 +static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
19348 +static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
19349 +                                struct dwc_otg_pcd *pcd,
19350 +                                struct cfi_usb_ctrlrequest *ctrl_req);
19351 +static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
19352 +static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19353 +                            struct cfi_usb_ctrlrequest *req);
19354 +static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19355 +                                struct cfi_usb_ctrlrequest *req);
19356 +static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
19357 +                               struct cfi_usb_ctrlrequest *req);
19358 +static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
19359 +                            struct cfi_usb_ctrlrequest *req);
19360 +static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
19361 +
19362 +static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
19363 +static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
19364 +static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
19365 +
19366 +static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
19367 +
19368 +/** This is the header of the all features descriptor */
19369 +static cfi_all_features_header_t all_props_desc_header = {
19370 +       .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
19371 +       .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
19372 +       .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
19373 +};
19374 +
19375 +/** This is an array of statically allocated feature descriptors */
19376 +static cfi_feature_desc_header_t prop_descs[] = {
19377 +
19378 +       /* FT_ID_DMA_MODE */
19379 +       {
19380 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
19381 +        .bmAttributes = CFI_FEATURE_ATTR_RW,
19382 +        .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
19383 +        },
19384 +
19385 +       /* FT_ID_DMA_BUFFER_SETUP */
19386 +       {
19387 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
19388 +        .bmAttributes = CFI_FEATURE_ATTR_RW,
19389 +        .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19390 +        },
19391 +
19392 +       /* FT_ID_DMA_BUFF_ALIGN */
19393 +       {
19394 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
19395 +        .bmAttributes = CFI_FEATURE_ATTR_RW,
19396 +        .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19397 +        },
19398 +
19399 +       /* FT_ID_DMA_CONCAT_SETUP */
19400 +       {
19401 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
19402 +        .bmAttributes = CFI_FEATURE_ATTR_RW,
19403 +        //.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),
19404 +        },
19405 +
19406 +       /* FT_ID_DMA_CIRCULAR */
19407 +       {
19408 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
19409 +        .bmAttributes = CFI_FEATURE_ATTR_RW,
19410 +        .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19411 +        },
19412 +
19413 +       /* FT_ID_THRESHOLD_SETUP */
19414 +       {
19415 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
19416 +        .bmAttributes = CFI_FEATURE_ATTR_RW,
19417 +        .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
19418 +        },
19419 +
19420 +       /* FT_ID_DFIFO_DEPTH */
19421 +       {
19422 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
19423 +        .bmAttributes = CFI_FEATURE_ATTR_RO,
19424 +        .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19425 +        },
19426 +
19427 +       /* FT_ID_TX_FIFO_DEPTH */
19428 +       {
19429 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
19430 +        .bmAttributes = CFI_FEATURE_ATTR_RW,
19431 +        .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19432 +        },
19433 +
19434 +       /* FT_ID_RX_FIFO_DEPTH */
19435 +       {
19436 +        .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
19437 +        .bmAttributes = CFI_FEATURE_ATTR_RW,
19438 +        .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
19439 +        }
19440 +};
19441 +
19442 +/** The table of feature names */
19443 +cfi_string_t prop_name_table[] = {
19444 +       {FT_ID_DMA_MODE, "dma_mode"},
19445 +       {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
19446 +       {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
19447 +       {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
19448 +       {FT_ID_DMA_CIRCULAR, "buffer_circular"},
19449 +       {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
19450 +       {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
19451 +       {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
19452 +       {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
19453 +       {}
19454 +};
19455 +
19456 +/************************************************************************/
19457 +
19458 +/**
19459 + * Returns the name of the feature by its ID
19460 + * or NULL if no featute ID matches.
19461 + *
19462 + */
19463 +const uint8_t *get_prop_name(uint16_t prop_id, int *len)
19464 +{
19465 +       cfi_string_t *pstr;
19466 +       *len = 0;
19467 +
19468 +       for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
19469 +               if (pstr->id == prop_id) {
19470 +                       *len = DWC_STRLEN(pstr->s);
19471 +                       return pstr->s;
19472 +               }
19473 +       }
19474 +       return NULL;
19475 +}
19476 +
19477 +/**
19478 + * This function handles all CFI specific control requests.
19479 + *
19480 + * Return a negative value to stall the DCE.
19481 + */
19482 +int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
19483 +{
19484 +       int retval = 0;
19485 +       dwc_otg_pcd_ep_t *ep = NULL;
19486 +       cfiobject_t *cfi = pcd->cfi;
19487 +       struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
19488 +       uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
19489 +       uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
19490 +       uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
19491 +       uint32_t regaddr = 0;
19492 +       uint32_t regval = 0;
19493 +
19494 +       /* Save this Control Request in the CFI object.
19495 +        * The data field will be assigned in the data stage completion CB function.
19496 +        */
19497 +       cfi->ctrl_req = *ctrl;
19498 +       cfi->ctrl_req.data = NULL;
19499 +
19500 +       cfi->need_gadget_att = 0;
19501 +       cfi->need_status_in_complete = 0;
19502 +
19503 +       switch (ctrl->bRequest) {
19504 +       case VEN_CORE_GET_FEATURES:
19505 +               retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
19506 +               if (retval >= 0) {
19507 +                       //dump_msg(cfi->buf_in.buf, retval);
19508 +                       ep = &pcd->ep0;
19509 +
19510 +                       retval = min((uint16_t) retval, wLen);
19511 +                       /* Transfer this buffer to the host through the EP0-IN EP */
19512 +                       ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19513 +                       ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19514 +                       ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19515 +                       ep->dwc_ep.xfer_len = retval;
19516 +                       ep->dwc_ep.xfer_count = 0;
19517 +                       ep->dwc_ep.sent_zlp = 0;
19518 +                       ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19519 +
19520 +                       pcd->ep0_pending = 1;
19521 +                       dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19522 +               }
19523 +               retval = 0;
19524 +               break;
19525 +
19526 +       case VEN_CORE_GET_FEATURE:
19527 +               CFI_INFO("VEN_CORE_GET_FEATURE\n");
19528 +               retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
19529 +                                              pcd, ctrl);
19530 +               if (retval >= 0) {
19531 +                       ep = &pcd->ep0;
19532 +
19533 +                       retval = min((uint16_t) retval, wLen);
19534 +                       /* Transfer this buffer to the host through the EP0-IN EP */
19535 +                       ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19536 +                       ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19537 +                       ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19538 +                       ep->dwc_ep.xfer_len = retval;
19539 +                       ep->dwc_ep.xfer_count = 0;
19540 +                       ep->dwc_ep.sent_zlp = 0;
19541 +                       ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19542 +
19543 +                       pcd->ep0_pending = 1;
19544 +                       dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19545 +               }
19546 +               CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
19547 +               dump_msg(cfi->buf_in.buf, retval);
19548 +               break;
19549 +
19550 +       case VEN_CORE_SET_FEATURE:
19551 +               CFI_INFO("VEN_CORE_SET_FEATURE\n");
19552 +               /* Set up an XFER to get the data stage of the control request,
19553 +                * which is the new value of the feature to be modified.
19554 +                */
19555 +               ep = &pcd->ep0;
19556 +               ep->dwc_ep.is_in = 0;
19557 +               ep->dwc_ep.dma_addr = cfi->buf_out.addr;
19558 +               ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
19559 +               ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
19560 +               ep->dwc_ep.xfer_len = wLen;
19561 +               ep->dwc_ep.xfer_count = 0;
19562 +               ep->dwc_ep.sent_zlp = 0;
19563 +               ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19564 +
19565 +               pcd->ep0_pending = 1;
19566 +               /* Read the control write's data stage */
19567 +               dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19568 +               retval = 0;
19569 +               break;
19570 +
19571 +       case VEN_CORE_RESET_FEATURES:
19572 +               CFI_INFO("VEN_CORE_RESET_FEATURES\n");
19573 +               cfi->need_gadget_att = 1;
19574 +               cfi->need_status_in_complete = 1;
19575 +               retval = cfi_preproc_reset(pcd, ctrl);
19576 +               CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
19577 +               break;
19578 +
19579 +       case VEN_CORE_ACTIVATE_FEATURES:
19580 +               CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
19581 +               break;
19582 +
19583 +       case VEN_CORE_READ_REGISTER:
19584 +               CFI_INFO("VEN_CORE_READ_REGISTER\n");
19585 +               /* wValue optionally contains the HI WORD of the register offset and
19586 +                * wIndex contains the LOW WORD of the register offset
19587 +                */
19588 +               if (wValue == 0) {
19589 +                       /* @TODO - MAS - fix the access to the base field */
19590 +                       regaddr = 0;
19591 +                       //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
19592 +                       //GET_CORE_IF(pcd)->co
19593 +                       regaddr |= wIndex;
19594 +               } else {
19595 +                       regaddr = (wValue << 16) | wIndex;
19596 +               }
19597 +
19598 +               /* Read a 32-bit value of the memory at the regaddr */
19599 +               regval = DWC_READ_REG32((uint32_t *) regaddr);
19600 +
19601 +               ep = &pcd->ep0;
19602 +               dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
19603 +               ep->dwc_ep.is_in = 1;
19604 +               ep->dwc_ep.dma_addr = cfi->buf_in.addr;
19605 +               ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
19606 +               ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
19607 +               ep->dwc_ep.xfer_len = wLen;
19608 +               ep->dwc_ep.xfer_count = 0;
19609 +               ep->dwc_ep.sent_zlp = 0;
19610 +               ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19611 +
19612 +               pcd->ep0_pending = 1;
19613 +               dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19614 +               cfi->need_gadget_att = 0;
19615 +               retval = 0;
19616 +               break;
19617 +
19618 +       case VEN_CORE_WRITE_REGISTER:
19619 +               CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
19620 +               /* Set up an XFER to get the data stage of the control request,
19621 +                * which is the new value of the register to be modified.
19622 +                */
19623 +               ep = &pcd->ep0;
19624 +               ep->dwc_ep.is_in = 0;
19625 +               ep->dwc_ep.dma_addr = cfi->buf_out.addr;
19626 +               ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
19627 +               ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
19628 +               ep->dwc_ep.xfer_len = wLen;
19629 +               ep->dwc_ep.xfer_count = 0;
19630 +               ep->dwc_ep.sent_zlp = 0;
19631 +               ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
19632 +
19633 +               pcd->ep0_pending = 1;
19634 +               /* Read the control write's data stage */
19635 +               dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
19636 +               retval = 0;
19637 +               break;
19638 +
19639 +       default:
19640 +               retval = -DWC_E_NOT_SUPPORTED;
19641 +               break;
19642 +       }
19643 +
19644 +       return retval;
19645 +}
19646 +
19647 +/**
19648 + * This function prepares the core features descriptors and copies its
19649 + * raw representation into the buffer <buf>.
19650 + *
19651 + * The buffer structure is as follows:
19652 + *     all_features_header (8 bytes)
19653 + *     features_#1 (8 bytes + feature name string length)
19654 + *     features_#2 (8 bytes + feature name string length)
19655 + *     .....
19656 + *     features_#n - where n=the total count of feature descriptors
19657 + */
19658 +static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
19659 +{
19660 +       cfi_feature_desc_header_t *prop_hdr = prop_descs;
19661 +       cfi_feature_desc_header_t *prop;
19662 +       cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
19663 +       cfi_all_features_header_t *tmp;
19664 +       uint8_t *tmpbuf = buf;
19665 +       const uint8_t *pname = NULL;
19666 +       int i, j, namelen = 0, totlen;
19667 +
19668 +       /* Prepare and copy the core features into the buffer */
19669 +       CFI_INFO("%s:\n", __func__);
19670 +
19671 +       tmp = (cfi_all_features_header_t *) tmpbuf;
19672 +       *tmp = *all_props_hdr;
19673 +       tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
19674 +
19675 +       j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
19676 +       for (i = 0; i < j; i++, prop_hdr++) {
19677 +               pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
19678 +               prop = (cfi_feature_desc_header_t *) tmpbuf;
19679 +               *prop = *prop_hdr;
19680 +
19681 +               prop->bNameLen = namelen;
19682 +               prop->wLength =
19683 +                   DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
19684 +                                            namelen);
19685 +
19686 +               tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
19687 +               dwc_memcpy(tmpbuf, pname, namelen);
19688 +               tmpbuf += namelen;
19689 +       }
19690 +
19691 +       totlen = tmpbuf - buf;
19692 +
19693 +       if (totlen > 0) {
19694 +               tmp = (cfi_all_features_header_t *) buf;
19695 +               tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
19696 +       }
19697 +
19698 +       return totlen;
19699 +}
19700 +
19701 +/**
19702 + * This function releases all the dynamic memory in the CFI object.
19703 + */
19704 +static void cfi_release(cfiobject_t * cfiobj)
19705 +{
19706 +       cfi_ep_t *cfiep;
19707 +       dwc_list_link_t *tmp;
19708 +
19709 +       CFI_INFO("%s\n", __func__);
19710 +
19711 +       if (cfiobj->buf_in.buf) {
19712 +               DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
19713 +                            cfiobj->buf_in.addr);
19714 +               cfiobj->buf_in.buf = NULL;
19715 +       }
19716 +
19717 +       if (cfiobj->buf_out.buf) {
19718 +               DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
19719 +                            cfiobj->buf_out.addr);
19720 +               cfiobj->buf_out.buf = NULL;
19721 +       }
19722 +
19723 +       /* Free the Buffer Setup values for each EP */
19724 +       //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
19725 +       DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
19726 +               cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
19727 +               cfi_free_ep_bs_dyn_data(cfiep);
19728 +       }
19729 +}
19730 +
19731 +/**
19732 + * This function frees the dynamically allocated EP buffer setup data.
19733 + */
19734 +static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
19735 +{
19736 +       if (cfiep->bm_sg) {
19737 +               DWC_FREE(cfiep->bm_sg);
19738 +               cfiep->bm_sg = NULL;
19739 +       }
19740 +
19741 +       if (cfiep->bm_align) {
19742 +               DWC_FREE(cfiep->bm_align);
19743 +               cfiep->bm_align = NULL;
19744 +       }
19745 +
19746 +       if (cfiep->bm_concat) {
19747 +               if (NULL != cfiep->bm_concat->wTxBytes) {
19748 +                       DWC_FREE(cfiep->bm_concat->wTxBytes);
19749 +                       cfiep->bm_concat->wTxBytes = NULL;
19750 +               }
19751 +               DWC_FREE(cfiep->bm_concat);
19752 +               cfiep->bm_concat = NULL;
19753 +       }
19754 +}
19755 +
19756 +/**
19757 + * This function initializes the default values of the features
19758 + * for a specific endpoint and should be called only once when
19759 + * the EP is enabled first time.
19760 + */
19761 +static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
19762 +{
19763 +       int retval = 0;
19764 +
19765 +       cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
19766 +       if (NULL == cfiep->bm_sg) {
19767 +               CFI_INFO("Failed to allocate memory for SG feature value\n");
19768 +               return -DWC_E_NO_MEMORY;
19769 +       }
19770 +       dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
19771 +
19772 +       /* For the Concatenation feature's default value we do not allocate
19773 +        * memory for the wTxBytes field - it will be done in the set_feature_value
19774 +        * request handler.
19775 +        */
19776 +       cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
19777 +       if (NULL == cfiep->bm_concat) {
19778 +               CFI_INFO
19779 +                   ("Failed to allocate memory for CONCATENATION feature value\n");
19780 +               DWC_FREE(cfiep->bm_sg);
19781 +               return -DWC_E_NO_MEMORY;
19782 +       }
19783 +       dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
19784 +
19785 +       cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
19786 +       if (NULL == cfiep->bm_align) {
19787 +               CFI_INFO
19788 +                   ("Failed to allocate memory for Alignment feature value\n");
19789 +               DWC_FREE(cfiep->bm_sg);
19790 +               DWC_FREE(cfiep->bm_concat);
19791 +               return -DWC_E_NO_MEMORY;
19792 +       }
19793 +       dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
19794 +
19795 +       return retval;
19796 +}
19797 +
19798 +/**
19799 + * The callback function that notifies the CFI on the activation of
19800 + * an endpoint in the PCD. The following steps are done in this function:
19801 + *
19802 + *     Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's
19803 + *             active endpoint)
19804 + *     Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP
19805 + *     Set the Buffer Mode to standard
19806 + *     Initialize the default values for all EP modes (SG, Circular, Concat, Align)
19807 + *     Add the cfi_ep_t object to the list of active endpoints in the CFI object
19808 + */
19809 +static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
19810 +                        struct dwc_otg_pcd_ep *ep)
19811 +{
19812 +       cfi_ep_t *cfiep;
19813 +       int retval = -DWC_E_NOT_SUPPORTED;
19814 +
19815 +       CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
19816 +                "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
19817 +       /* MAS - Check whether this endpoint already is in the list */
19818 +       cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
19819 +
19820 +       if (NULL == cfiep) {
19821 +               /* Allocate a cfi_ep_t object */
19822 +               cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
19823 +               if (NULL == cfiep) {
19824 +                       CFI_INFO
19825 +                           ("Unable to allocate memory for <cfiep> in function %s\n",
19826 +                            __func__);
19827 +                       return -DWC_E_NO_MEMORY;
19828 +               }
19829 +               dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
19830 +
19831 +               /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
19832 +               cfiep->ep = ep;
19833 +
19834 +               /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
19835 +               ep->dwc_ep.descs =
19836 +                   DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
19837 +                                 sizeof(dwc_otg_dma_desc_t),
19838 +                                 &ep->dwc_ep.descs_dma_addr);
19839 +
19840 +               if (NULL == ep->dwc_ep.descs) {
19841 +                       DWC_FREE(cfiep);
19842 +                       return -DWC_E_NO_MEMORY;
19843 +               }
19844 +
19845 +               DWC_LIST_INIT(&cfiep->lh);
19846 +
19847 +               /* Set the buffer mode to BM_STANDARD. It will be modified
19848 +                * when building descriptors for a specific buffer mode */
19849 +               ep->dwc_ep.buff_mode = BM_STANDARD;
19850 +
19851 +               /* Create and initialize the default values for this EP's Buffer modes */
19852 +               if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
19853 +                       return retval;
19854 +
19855 +               /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
19856 +               DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
19857 +               retval = 0;
19858 +       } else {                /* The sought EP already is in the list */
19859 +               CFI_INFO("%s: The sought EP already is in the list\n",
19860 +                        __func__);
19861 +       }
19862 +
19863 +       return retval;
19864 +}
19865 +
19866 +/**
19867 + * This function is called when the data stage of a 3-stage Control Write request
19868 + * is complete.
19869 + *
19870 + */
19871 +static int cfi_ctrl_write_complete(struct cfiobject *cfi,
19872 +                                  struct dwc_otg_pcd *pcd)
19873 +{
19874 +       uint32_t addr, reg_value;
19875 +       uint16_t wIndex, wValue;
19876 +       uint8_t bRequest;
19877 +       uint8_t *buf = cfi->buf_out.buf;
19878 +       //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
19879 +       struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
19880 +       int retval = -DWC_E_NOT_SUPPORTED;
19881 +
19882 +       CFI_INFO("%s\n", __func__);
19883 +
19884 +       bRequest = ctrl_req->bRequest;
19885 +       wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
19886 +       wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
19887 +
19888 +       /*
19889 +        * Save the pointer to the data stage in the ctrl_req's <data> field.
19890 +        * The request should be already saved in the command stage by now.
19891 +        */
19892 +       ctrl_req->data = cfi->buf_out.buf;
19893 +       cfi->need_status_in_complete = 0;
19894 +       cfi->need_gadget_att = 0;
19895 +
19896 +       switch (bRequest) {
19897 +       case VEN_CORE_WRITE_REGISTER:
19898 +               /* The buffer contains raw data of the new value for the register */
19899 +               reg_value = *((uint32_t *) buf);
19900 +               if (wValue == 0) {
19901 +                       addr = 0;
19902 +                       //addr = (uint32_t) pcd->otg_dev->os_dep.base;
19903 +                       addr += wIndex;
19904 +               } else {
19905 +                       addr = (wValue << 16) | wIndex;
19906 +               }
19907 +
19908 +               //writel(reg_value, addr);
19909 +
19910 +               retval = 0;
19911 +               cfi->need_status_in_complete = 1;
19912 +               break;
19913 +
19914 +       case VEN_CORE_SET_FEATURE:
19915 +               /* The buffer contains raw data of the new value of the feature */
19916 +               retval = cfi_set_feature_value(pcd);
19917 +               if (retval < 0)
19918 +                       return retval;
19919 +
19920 +               cfi->need_status_in_complete = 1;
19921 +               break;
19922 +
19923 +       default:
19924 +               break;
19925 +       }
19926 +
19927 +       return retval;
19928 +}
19929 +
19930 +/**
19931 + * This function builds the DMA descriptors for the SG buffer mode.
19932 + */
19933 +static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
19934 +                              dwc_otg_pcd_request_t * req)
19935 +{
19936 +       struct dwc_otg_pcd_ep *ep = cfiep->ep;
19937 +       ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
19938 +       struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
19939 +       struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
19940 +       dma_addr_t buff_addr = req->dma;
19941 +       int i;
19942 +       uint32_t txsize, off;
19943 +
19944 +       txsize = sgval->wSize;
19945 +       off = sgval->bOffset;
19946 +
19947 +//      CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n",
19948 +//              __func__, cfiep->ep->ep.name, txsize, off);
19949 +
19950 +       for (i = 0; i < sgval->bCount; i++) {
19951 +               desc->status.b.bs = BS_HOST_BUSY;
19952 +               desc->buf = buff_addr;
19953 +               desc->status.b.l = 0;
19954 +               desc->status.b.ioc = 0;
19955 +               desc->status.b.sp = 0;
19956 +               desc->status.b.bytes = txsize;
19957 +               desc->status.b.bs = BS_HOST_READY;
19958 +
19959 +               /* Set the next address of the buffer */
19960 +               buff_addr += txsize + off;
19961 +               desc_last = desc;
19962 +               desc++;
19963 +       }
19964 +
19965 +       /* Set the last, ioc and sp bits on the Last DMA Descriptor */
19966 +       desc_last->status.b.l = 1;
19967 +       desc_last->status.b.ioc = 1;
19968 +       desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
19969 +       /* Save the last DMA descriptor pointer */
19970 +       cfiep->dma_desc_last = desc_last;
19971 +       cfiep->desc_count = sgval->bCount;
19972 +}
19973 +
19974 +/**
19975 + * This function builds the DMA descriptors for the Concatenation buffer mode.
19976 + */
19977 +static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
19978 +                                  dwc_otg_pcd_request_t * req)
19979 +{
19980 +       struct dwc_otg_pcd_ep *ep = cfiep->ep;
19981 +       ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
19982 +       struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
19983 +       struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
19984 +       dma_addr_t buff_addr = req->dma;
19985 +       int i;
19986 +       uint16_t *txsize;
19987 +
19988 +       txsize = concatval->wTxBytes;
19989 +
19990 +       for (i = 0; i < concatval->hdr.bDescCount; i++) {
19991 +               desc->buf = buff_addr;
19992 +               desc->status.b.bs = BS_HOST_BUSY;
19993 +               desc->status.b.l = 0;
19994 +               desc->status.b.ioc = 0;
19995 +               desc->status.b.sp = 0;
19996 +               desc->status.b.bytes = *txsize;
19997 +               desc->status.b.bs = BS_HOST_READY;
19998 +
19999 +               txsize++;
20000 +               /* Set the next address of the buffer */
20001 +               buff_addr += UGETW(ep->desc->wMaxPacketSize);
20002 +               desc_last = desc;
20003 +               desc++;
20004 +       }
20005 +
20006 +       /* Set the last, ioc and sp bits on the Last DMA Descriptor */
20007 +       desc_last->status.b.l = 1;
20008 +       desc_last->status.b.ioc = 1;
20009 +       desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
20010 +       cfiep->dma_desc_last = desc_last;
20011 +       cfiep->desc_count = concatval->hdr.bDescCount;
20012 +}
20013 +
20014 +/**
20015 + * This function builds the DMA descriptors for the Circular buffer mode
20016 + */
20017 +static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20018 +                                dwc_otg_pcd_request_t * req)
20019 +{
20020 +       /* @todo: MAS - add implementation when this feature needs to be tested */
20021 +}
20022 +
20023 +/**
20024 + * This function builds the DMA descriptors for the Alignment buffer mode
20025 + */
20026 +static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
20027 +                                 dwc_otg_pcd_request_t * req)
20028 +{
20029 +       struct dwc_otg_pcd_ep *ep = cfiep->ep;
20030 +       ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
20031 +       struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
20032 +       dma_addr_t buff_addr = req->dma;
20033 +
20034 +       desc->status.b.bs = BS_HOST_BUSY;
20035 +       desc->status.b.l = 1;
20036 +       desc->status.b.ioc = 1;
20037 +       desc->status.b.sp = ep->dwc_ep.sent_zlp;
20038 +       desc->status.b.bytes = req->length;
20039 +       /* Adjust the buffer alignment */
20040 +       desc->buf = (buff_addr + alignval->bAlign);
20041 +       desc->status.b.bs = BS_HOST_READY;
20042 +       cfiep->dma_desc_last = desc;
20043 +       cfiep->desc_count = 1;
20044 +}
20045 +
20046 +/**
20047 + * This function builds the DMA descriptors chain for different modes of the
20048 + * buffer setup of an endpoint.
20049 + */
20050 +static void cfi_build_descriptors(struct cfiobject *cfi,
20051 +                                 struct dwc_otg_pcd *pcd,
20052 +                                 struct dwc_otg_pcd_ep *ep,
20053 +                                 dwc_otg_pcd_request_t * req)
20054 +{
20055 +       cfi_ep_t *cfiep;
20056 +
20057 +       /* Get the cfiep by the dwc_otg_pcd_ep */
20058 +       cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
20059 +       if (NULL == cfiep) {
20060 +               CFI_INFO("%s: Unable to find a matching active endpoint\n",
20061 +                        __func__);
20062 +               return;
20063 +       }
20064 +
20065 +       cfiep->xfer_len = req->length;
20066 +
20067 +       /* Iterate through all the DMA descriptors */
20068 +       switch (cfiep->ep->dwc_ep.buff_mode) {
20069 +       case BM_SG:
20070 +               cfi_build_sg_descs(cfi, cfiep, req);
20071 +               break;
20072 +
20073 +       case BM_CONCAT:
20074 +               cfi_build_concat_descs(cfi, cfiep, req);
20075 +               break;
20076 +
20077 +       case BM_CIRCULAR:
20078 +               cfi_build_circ_descs(cfi, cfiep, req);
20079 +               break;
20080 +
20081 +       case BM_ALIGN:
20082 +               cfi_build_align_descs(cfi, cfiep, req);
20083 +               break;
20084 +
20085 +       default:
20086 +               break;
20087 +       }
20088 +}
20089 +
20090 +/**
20091 + * Allocate DMA buffer for different Buffer modes.
20092 + */
20093 +static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
20094 +                             struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
20095 +                             unsigned size, gfp_t flags)
20096 +{
20097 +       return DWC_DMA_ALLOC(size, dma);
20098 +}
20099 +
20100 +/**
20101 + * This function initializes the CFI object.
20102 + */
20103 +int init_cfi(cfiobject_t * cfiobj)
20104 +{
20105 +       CFI_INFO("%s\n", __func__);
20106 +
20107 +       /* Allocate a buffer for IN XFERs */
20108 +       cfiobj->buf_in.buf =
20109 +           DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
20110 +       if (NULL == cfiobj->buf_in.buf) {
20111 +               CFI_INFO("Unable to allocate buffer for INs\n");
20112 +               return -DWC_E_NO_MEMORY;
20113 +       }
20114 +
20115 +       /* Allocate a buffer for OUT XFERs */
20116 +       cfiobj->buf_out.buf =
20117 +           DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
20118 +       if (NULL == cfiobj->buf_out.buf) {
20119 +               CFI_INFO("Unable to allocate buffer for OUT\n");
20120 +               return -DWC_E_NO_MEMORY;
20121 +       }
20122 +
20123 +       /* Initialize the callback function pointers */
20124 +       cfiobj->ops.release = cfi_release;
20125 +       cfiobj->ops.ep_enable = cfi_ep_enable;
20126 +       cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
20127 +       cfiobj->ops.build_descriptors = cfi_build_descriptors;
20128 +       cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
20129 +
20130 +       /* Initialize the list of active endpoints in the CFI object */
20131 +       DWC_LIST_INIT(&cfiobj->active_eps);
20132 +
20133 +       return 0;
20134 +}
20135 +
20136 +/**
20137 + * This function reads the required feature's current value into the buffer
20138 + *
20139 + * @retval: Returns negative as error, or the data length of the feature
20140 + */
20141 +static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
20142 +                                struct dwc_otg_pcd *pcd,
20143 +                                struct cfi_usb_ctrlrequest *ctrl_req)
20144 +{
20145 +       int retval = -DWC_E_NOT_SUPPORTED;
20146 +       struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
20147 +       uint16_t dfifo, rxfifo, txfifo;
20148 +
20149 +       switch (ctrl_req->wIndex) {
20150 +               /* Whether the DDMA is enabled or not */
20151 +       case FT_ID_DMA_MODE:
20152 +               *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
20153 +               retval = 1;
20154 +               break;
20155 +
20156 +       case FT_ID_DMA_BUFFER_SETUP:
20157 +               retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
20158 +               break;
20159 +
20160 +       case FT_ID_DMA_BUFF_ALIGN:
20161 +               retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
20162 +               break;
20163 +
20164 +       case FT_ID_DMA_CONCAT_SETUP:
20165 +               retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
20166 +               break;
20167 +
20168 +       case FT_ID_DMA_CIRCULAR:
20169 +               CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
20170 +               break;
20171 +
20172 +       case FT_ID_THRESHOLD_SETUP:
20173 +               CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
20174 +               break;
20175 +
20176 +       case FT_ID_DFIFO_DEPTH:
20177 +               dfifo = get_dfifo_size(coreif);
20178 +               *((uint16_t *) buf) = dfifo;
20179 +               retval = sizeof(uint16_t);
20180 +               break;
20181 +
20182 +       case FT_ID_TX_FIFO_DEPTH:
20183 +               retval = get_txfifo_size(pcd, ctrl_req->wValue);
20184 +               if (retval >= 0) {
20185 +                       txfifo = retval;
20186 +                       *((uint16_t *) buf) = txfifo;
20187 +                       retval = sizeof(uint16_t);
20188 +               }
20189 +               break;
20190 +
20191 +       case FT_ID_RX_FIFO_DEPTH:
20192 +               retval = get_rxfifo_size(coreif, ctrl_req->wValue);
20193 +               if (retval >= 0) {
20194 +                       rxfifo = retval;
20195 +                       *((uint16_t *) buf) = rxfifo;
20196 +                       retval = sizeof(uint16_t);
20197 +               }
20198 +               break;
20199 +       }
20200 +
20201 +       return retval;
20202 +}
20203 +
20204 +/**
20205 + * This function resets the SG for the specified EP to its default value
20206 + */
20207 +static int cfi_reset_sg_val(cfi_ep_t * cfiep)
20208 +{
20209 +       dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
20210 +       return 0;
20211 +}
20212 +
20213 +/**
20214 + * This function resets the Alignment for the specified EP to its default value
20215 + */
20216 +static int cfi_reset_align_val(cfi_ep_t * cfiep)
20217 +{
20218 +       dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
20219 +       return 0;
20220 +}
20221 +
20222 +/**
20223 + * This function resets the Concatenation for the specified EP to its default value
20224 + * This function will also set the value of the wTxBytes field to NULL after
20225 + * freeing the memory previously allocated for this field.
20226 + */
20227 +static int cfi_reset_concat_val(cfi_ep_t * cfiep)
20228 +{
20229 +       /* First we need to free the wTxBytes field */
20230 +       if (cfiep->bm_concat->wTxBytes) {
20231 +               DWC_FREE(cfiep->bm_concat->wTxBytes);
20232 +               cfiep->bm_concat->wTxBytes = NULL;
20233 +       }
20234 +
20235 +       dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
20236 +       return 0;
20237 +}
20238 +
20239 +/**
20240 + * This function resets all the buffer setups of the specified endpoint
20241 + */
20242 +static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
20243 +{
20244 +       cfi_reset_sg_val(cfiep);
20245 +       cfi_reset_align_val(cfiep);
20246 +       cfi_reset_concat_val(cfiep);
20247 +       return 0;
20248 +}
20249 +
20250 +static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
20251 +                                    uint8_t rx_rst, uint8_t tx_rst)
20252 +{
20253 +       int retval = -DWC_E_INVALID;
20254 +       uint16_t tx_siz[15];
20255 +       uint16_t rx_siz = 0;
20256 +       dwc_otg_pcd_ep_t *ep = NULL;
20257 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
20258 +       dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
20259 +
20260 +       if (rx_rst) {
20261 +               rx_siz = params->dev_rx_fifo_size;
20262 +               params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
20263 +       }
20264 +
20265 +       if (tx_rst) {
20266 +               if (ep_addr == 0) {
20267 +                       int i;
20268 +
20269 +                       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20270 +                               tx_siz[i] =
20271 +                                   core_if->core_params->dev_tx_fifo_size[i];
20272 +                               core_if->core_params->dev_tx_fifo_size[i] =
20273 +                                   core_if->init_txfsiz[i];
20274 +                       }
20275 +               } else {
20276 +
20277 +                       ep = get_ep_by_addr(pcd, ep_addr);
20278 +
20279 +                       if (NULL == ep) {
20280 +                               CFI_INFO
20281 +                                   ("%s: Unable to get the endpoint addr=0x%02x\n",
20282 +                                    __func__, ep_addr);
20283 +                               return -DWC_E_INVALID;
20284 +                       }
20285 +
20286 +                       tx_siz[0] =
20287 +                           params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
20288 +                                                    1];
20289 +                       params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
20290 +                           GET_CORE_IF(pcd)->init_txfsiz[ep->
20291 +                                                         dwc_ep.tx_fifo_num -
20292 +                                                         1];
20293 +               }
20294 +       }
20295 +
20296 +       if (resize_fifos(GET_CORE_IF(pcd))) {
20297 +               retval = 0;
20298 +       } else {
20299 +               CFI_INFO
20300 +                   ("%s: Error resetting the feature Reset All(FIFO size)\n",
20301 +                    __func__);
20302 +               if (rx_rst) {
20303 +                       params->dev_rx_fifo_size = rx_siz;
20304 +               }
20305 +
20306 +               if (tx_rst) {
20307 +                       if (ep_addr == 0) {
20308 +                               int i;
20309 +                               for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
20310 +                                    i++) {
20311 +                                       core_if->
20312 +                                           core_params->dev_tx_fifo_size[i] =
20313 +                                           tx_siz[i];
20314 +                               }
20315 +                       } else {
20316 +                               params->dev_tx_fifo_size[ep->
20317 +                                                        dwc_ep.tx_fifo_num -
20318 +                                                        1] = tx_siz[0];
20319 +                       }
20320 +               }
20321 +               retval = -DWC_E_INVALID;
20322 +       }
20323 +       return retval;
20324 +}
20325 +
20326 +static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
20327 +{
20328 +       int retval = 0;
20329 +       cfi_ep_t *cfiep;
20330 +       cfiobject_t *cfi = pcd->cfi;
20331 +       dwc_list_link_t *tmp;
20332 +
20333 +       retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
20334 +       if (retval < 0) {
20335 +               return retval;
20336 +       }
20337 +
20338 +       /* If the EP address is known then reset the features for only that EP */
20339 +       if (addr) {
20340 +               cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20341 +               if (NULL == cfiep) {
20342 +                       CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20343 +                                __func__, addr);
20344 +                       return -DWC_E_INVALID;
20345 +               }
20346 +               retval = cfi_ep_reset_all_setup_vals(cfiep);
20347 +               cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
20348 +       }
20349 +       /* Otherwise (wValue == 0), reset all features of all EP's */
20350 +       else {
20351 +               /* Traverse all the active EP's and reset the feature(s) value(s) */
20352 +               //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20353 +               DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20354 +                       cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20355 +                       retval = cfi_ep_reset_all_setup_vals(cfiep);
20356 +                       cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
20357 +                       if (retval < 0) {
20358 +                               CFI_INFO
20359 +                                   ("%s: Error resetting the feature Reset All\n",
20360 +                                    __func__);
20361 +                               return retval;
20362 +                       }
20363 +               }
20364 +       }
20365 +       return retval;
20366 +}
20367 +
20368 +static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
20369 +                                          uint8_t addr)
20370 +{
20371 +       int retval = 0;
20372 +       cfi_ep_t *cfiep;
20373 +       cfiobject_t *cfi = pcd->cfi;
20374 +       dwc_list_link_t *tmp;
20375 +
20376 +       /* If the EP address is known then reset the features for only that EP */
20377 +       if (addr) {
20378 +               cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20379 +               if (NULL == cfiep) {
20380 +                       CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20381 +                                __func__, addr);
20382 +                       return -DWC_E_INVALID;
20383 +               }
20384 +               retval = cfi_reset_sg_val(cfiep);
20385 +       }
20386 +       /* Otherwise (wValue == 0), reset all features of all EP's */
20387 +       else {
20388 +               /* Traverse all the active EP's and reset the feature(s) value(s) */
20389 +               //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20390 +               DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20391 +                       cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20392 +                       retval = cfi_reset_sg_val(cfiep);
20393 +                       if (retval < 0) {
20394 +                               CFI_INFO
20395 +                                   ("%s: Error resetting the feature Buffer Setup\n",
20396 +                                    __func__);
20397 +                               return retval;
20398 +                       }
20399 +               }
20400 +       }
20401 +       return retval;
20402 +}
20403 +
20404 +static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
20405 +{
20406 +       int retval = 0;
20407 +       cfi_ep_t *cfiep;
20408 +       cfiobject_t *cfi = pcd->cfi;
20409 +       dwc_list_link_t *tmp;
20410 +
20411 +       /* If the EP address is known then reset the features for only that EP */
20412 +       if (addr) {
20413 +               cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20414 +               if (NULL == cfiep) {
20415 +                       CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20416 +                                __func__, addr);
20417 +                       return -DWC_E_INVALID;
20418 +               }
20419 +               retval = cfi_reset_concat_val(cfiep);
20420 +       }
20421 +       /* Otherwise (wValue == 0), reset all features of all EP's */
20422 +       else {
20423 +               /* Traverse all the active EP's and reset the feature(s) value(s) */
20424 +               //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20425 +               DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20426 +                       cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20427 +                       retval = cfi_reset_concat_val(cfiep);
20428 +                       if (retval < 0) {
20429 +                               CFI_INFO
20430 +                                   ("%s: Error resetting the feature Concatenation Value\n",
20431 +                                    __func__);
20432 +                               return retval;
20433 +                       }
20434 +               }
20435 +       }
20436 +       return retval;
20437 +}
20438 +
20439 +static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
20440 +{
20441 +       int retval = 0;
20442 +       cfi_ep_t *cfiep;
20443 +       cfiobject_t *cfi = pcd->cfi;
20444 +       dwc_list_link_t *tmp;
20445 +
20446 +       /* If the EP address is known then reset the features for only that EP */
20447 +       if (addr) {
20448 +               cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
20449 +               if (NULL == cfiep) {
20450 +                       CFI_INFO("%s: Error getting the EP address 0x%02x\n",
20451 +                                __func__, addr);
20452 +                       return -DWC_E_INVALID;
20453 +               }
20454 +               retval = cfi_reset_align_val(cfiep);
20455 +       }
20456 +       /* Otherwise (wValue == 0), reset all features of all EP's */
20457 +       else {
20458 +               /* Traverse all the active EP's and reset the feature(s) value(s) */
20459 +               //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
20460 +               DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
20461 +                       cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
20462 +                       retval = cfi_reset_align_val(cfiep);
20463 +                       if (retval < 0) {
20464 +                               CFI_INFO
20465 +                                   ("%s: Error resetting the feature Aliignment Value\n",
20466 +                                    __func__);
20467 +                               return retval;
20468 +                       }
20469 +               }
20470 +       }
20471 +       return retval;
20472 +
20473 +}
20474 +
20475 +static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
20476 +                            struct cfi_usb_ctrlrequest *req)
20477 +{
20478 +       int retval = 0;
20479 +
20480 +       switch (req->wIndex) {
20481 +       case 0:
20482 +               /* Reset all features */
20483 +               retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
20484 +               break;
20485 +
20486 +       case FT_ID_DMA_BUFFER_SETUP:
20487 +               /* Reset the SG buffer setup */
20488 +               retval =
20489 +                   cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
20490 +               break;
20491 +
20492 +       case FT_ID_DMA_CONCAT_SETUP:
20493 +               /* Reset the Concatenation buffer setup */
20494 +               retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
20495 +               break;
20496 +
20497 +       case FT_ID_DMA_BUFF_ALIGN:
20498 +               /* Reset the Alignment buffer setup */
20499 +               retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
20500 +               break;
20501 +
20502 +       case FT_ID_TX_FIFO_DEPTH:
20503 +               retval =
20504 +                   cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
20505 +               pcd->cfi->need_gadget_att = 0;
20506 +               break;
20507 +
20508 +       case FT_ID_RX_FIFO_DEPTH:
20509 +               retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
20510 +               pcd->cfi->need_gadget_att = 0;
20511 +               break;
20512 +       default:
20513 +               break;
20514 +       }
20515 +       return retval;
20516 +}
20517 +
20518 +/**
20519 + * This function sets a new value for the SG buffer setup.
20520 + */
20521 +static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20522 +{
20523 +       uint8_t inaddr, outaddr;
20524 +       cfi_ep_t *epin, *epout;
20525 +       ddma_sg_buffer_setup_t *psgval;
20526 +       uint32_t desccount, size;
20527 +
20528 +       CFI_INFO("%s\n", __func__);
20529 +
20530 +       psgval = (ddma_sg_buffer_setup_t *) buf;
20531 +       desccount = (uint32_t) psgval->bCount;
20532 +       size = (uint32_t) psgval->wSize;
20533 +
20534 +       /* Check the DMA descriptor count */
20535 +       if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
20536 +               CFI_INFO
20537 +                   ("%s: The count of DMA Descriptors should be between 1 and %d\n",
20538 +                    __func__, MAX_DMA_DESCS_PER_EP);
20539 +               return -DWC_E_INVALID;
20540 +       }
20541 +
20542 +       /* Check the DMA descriptor count */
20543 +
20544 +       if (size == 0) {
20545 +
20546 +               CFI_INFO("%s: The transfer size should be at least 1 byte\n",
20547 +                        __func__);
20548 +
20549 +               return -DWC_E_INVALID;
20550 +
20551 +       }
20552 +
20553 +       inaddr = psgval->bInEndpointAddress;
20554 +       outaddr = psgval->bOutEndpointAddress;
20555 +
20556 +       epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
20557 +       epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
20558 +
20559 +       if (NULL == epin || NULL == epout) {
20560 +               CFI_INFO
20561 +                   ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
20562 +                    __func__, inaddr, outaddr);
20563 +               return -DWC_E_INVALID;
20564 +       }
20565 +
20566 +       epin->ep->dwc_ep.buff_mode = BM_SG;
20567 +       dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
20568 +
20569 +       epout->ep->dwc_ep.buff_mode = BM_SG;
20570 +       dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
20571 +
20572 +       return 0;
20573 +}
20574 +
20575 +/**
20576 + * This function sets a new value for the buffer Alignment setup.
20577 + */
20578 +static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20579 +{
20580 +       cfi_ep_t *ep;
20581 +       uint8_t addr;
20582 +       ddma_align_buffer_setup_t *palignval;
20583 +
20584 +       palignval = (ddma_align_buffer_setup_t *) buf;
20585 +       addr = palignval->bEndpointAddress;
20586 +
20587 +       ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20588 +
20589 +       if (NULL == ep) {
20590 +               CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20591 +                        __func__, addr);
20592 +               return -DWC_E_INVALID;
20593 +       }
20594 +
20595 +       ep->ep->dwc_ep.buff_mode = BM_ALIGN;
20596 +       dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
20597 +
20598 +       return 0;
20599 +}
20600 +
20601 +/**
20602 + * This function sets a new value for the Concatenation buffer setup.
20603 + */
20604 +static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
20605 +{
20606 +       uint8_t addr;
20607 +       cfi_ep_t *ep;
20608 +       struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
20609 +       uint16_t *pVals;
20610 +       uint32_t desccount;
20611 +       int i;
20612 +       uint16_t mps;
20613 +
20614 +       pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
20615 +       desccount = (uint32_t) pConcatValHdr->bDescCount;
20616 +       pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
20617 +
20618 +       /* Check the DMA descriptor count */
20619 +       if (desccount > MAX_DMA_DESCS_PER_EP) {
20620 +               CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
20621 +                        __func__, MAX_DMA_DESCS_PER_EP);
20622 +               return -DWC_E_INVALID;
20623 +       }
20624 +
20625 +       addr = pConcatValHdr->bEndpointAddress;
20626 +       ep = get_cfi_ep_by_addr(pcd->cfi, addr);
20627 +       if (NULL == ep) {
20628 +               CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20629 +                        __func__, addr);
20630 +               return -DWC_E_INVALID;
20631 +       }
20632 +
20633 +       mps = UGETW(ep->ep->desc->wMaxPacketSize);
20634 +
20635 +#if 0
20636 +       for (i = 0; i < desccount; i++) {
20637 +               CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
20638 +       }
20639 +       CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
20640 +#endif
20641 +
20642 +       /* Check the wTxSizes to be less than or equal to the mps */
20643 +       for (i = 0; i < desccount; i++) {
20644 +               if (pVals[i] > mps) {
20645 +                       CFI_INFO
20646 +                           ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
20647 +                            __func__, i, pVals[i]);
20648 +                       return -DWC_E_INVALID;
20649 +               }
20650 +       }
20651 +
20652 +       ep->ep->dwc_ep.buff_mode = BM_CONCAT;
20653 +       dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
20654 +
20655 +       /* Free the previously allocated storage for the wTxBytes */
20656 +       if (ep->bm_concat->wTxBytes) {
20657 +               DWC_FREE(ep->bm_concat->wTxBytes);
20658 +       }
20659 +
20660 +       /* Allocate a new storage for the wTxBytes field */
20661 +       ep->bm_concat->wTxBytes =
20662 +           DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
20663 +       if (NULL == ep->bm_concat->wTxBytes) {
20664 +               CFI_INFO("%s: Unable to allocate memory\n", __func__);
20665 +               return -DWC_E_NO_MEMORY;
20666 +       }
20667 +
20668 +       /* Copy the new values into the wTxBytes filed */
20669 +       dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
20670 +                  sizeof(uint16_t) * pConcatValHdr->bDescCount);
20671 +
20672 +       return 0;
20673 +}
20674 +
20675 +/**
20676 + * This function calculates the total of all FIFO sizes
20677 + *
20678 + * @param core_if Programming view of DWC_otg controller
20679 + *
20680 + * @return The total of data FIFO sizes.
20681 + *
20682 + */
20683 +static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
20684 +{
20685 +       dwc_otg_core_params_t *params = core_if->core_params;
20686 +       uint16_t dfifo_total = 0;
20687 +       int i;
20688 +
20689 +       /* The shared RxFIFO size */
20690 +       dfifo_total =
20691 +           params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
20692 +
20693 +       /* Add up each TxFIFO size to the total */
20694 +       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20695 +               dfifo_total += params->dev_tx_fifo_size[i];
20696 +       }
20697 +
20698 +       return dfifo_total;
20699 +}
20700 +
20701 +/**
20702 + * This function returns Rx FIFO size
20703 + *
20704 + * @param core_if Programming view of DWC_otg controller
20705 + *
20706 + * @return The total of data FIFO sizes.
20707 + *
20708 + */
20709 +static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
20710 +{
20711 +       switch (wValue >> 8) {
20712 +       case 0:
20713 +               return (core_if->pwron_rxfsiz <
20714 +                       32768) ? core_if->pwron_rxfsiz : 32768;
20715 +               break;
20716 +       case 1:
20717 +               return core_if->core_params->dev_rx_fifo_size;
20718 +               break;
20719 +       default:
20720 +               return -DWC_E_INVALID;
20721 +               break;
20722 +       }
20723 +}
20724 +
20725 +/**
20726 + * This function returns Tx FIFO size for IN EP
20727 + *
20728 + * @param core_if Programming view of DWC_otg controller
20729 + *
20730 + * @return The total of data FIFO sizes.
20731 + *
20732 + */
20733 +static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
20734 +{
20735 +       dwc_otg_pcd_ep_t *ep;
20736 +
20737 +       ep = get_ep_by_addr(pcd, wValue & 0xff);
20738 +
20739 +       if (NULL == ep) {
20740 +               CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20741 +                        __func__, wValue & 0xff);
20742 +               return -DWC_E_INVALID;
20743 +       }
20744 +
20745 +       if (!ep->dwc_ep.is_in) {
20746 +               CFI_INFO
20747 +                   ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
20748 +                    __func__, wValue & 0xff);
20749 +               return -DWC_E_INVALID;
20750 +       }
20751 +
20752 +       switch (wValue >> 8) {
20753 +       case 0:
20754 +               return (GET_CORE_IF(pcd)->pwron_txfsiz
20755 +                       [ep->dwc_ep.tx_fifo_num - 1] <
20756 +                       768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
20757 +                                                             dwc_ep.tx_fifo_num
20758 +                                                             - 1] : 32768;
20759 +               break;
20760 +       case 1:
20761 +               return GET_CORE_IF(pcd)->core_params->
20762 +                   dev_tx_fifo_size[ep->dwc_ep.num - 1];
20763 +               break;
20764 +       default:
20765 +               return -DWC_E_INVALID;
20766 +               break;
20767 +       }
20768 +}
20769 +
20770 +/**
20771 + * This function checks if the submitted combination of
20772 + * device mode FIFO sizes is possible or not.
20773 + *
20774 + * @param core_if Programming view of DWC_otg controller
20775 + *
20776 + * @return 1 if possible, 0 otherwise.
20777 + *
20778 + */
20779 +static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
20780 +{
20781 +       uint16_t dfifo_actual = 0;
20782 +       dwc_otg_core_params_t *params = core_if->core_params;
20783 +       uint16_t start_addr = 0;
20784 +       int i;
20785 +
20786 +       dfifo_actual =
20787 +           params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
20788 +
20789 +       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20790 +               dfifo_actual += params->dev_tx_fifo_size[i];
20791 +       }
20792 +
20793 +       if (dfifo_actual > core_if->total_fifo_size) {
20794 +               return 0;
20795 +       }
20796 +
20797 +       if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
20798 +               return 0;
20799 +
20800 +       if (params->dev_nperio_tx_fifo_size > 32768
20801 +           || params->dev_nperio_tx_fifo_size < 16)
20802 +               return 0;
20803 +
20804 +       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20805 +
20806 +               if (params->dev_tx_fifo_size[i] > 768
20807 +                   || params->dev_tx_fifo_size[i] < 4)
20808 +                       return 0;
20809 +       }
20810 +
20811 +       if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
20812 +               return 0;
20813 +       start_addr = params->dev_rx_fifo_size;
20814 +
20815 +       if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
20816 +               return 0;
20817 +       start_addr += params->dev_nperio_tx_fifo_size;
20818 +
20819 +       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20820 +
20821 +               if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
20822 +                       return 0;
20823 +               start_addr += params->dev_tx_fifo_size[i];
20824 +       }
20825 +
20826 +       return 1;
20827 +}
20828 +
20829 +/**
20830 + * This function resizes Device mode FIFOs
20831 + *
20832 + * @param core_if Programming view of DWC_otg controller
20833 + *
20834 + * @return 1 if successful, 0 otherwise
20835 + *
20836 + */
20837 +static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
20838 +{
20839 +       int i = 0;
20840 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
20841 +       dwc_otg_core_params_t *params = core_if->core_params;
20842 +       uint32_t rx_fifo_size;
20843 +       fifosize_data_t nptxfifosize;
20844 +       fifosize_data_t txfifosize[15];
20845 +
20846 +       uint32_t rx_fsz_bak;
20847 +       uint32_t nptxfsz_bak;
20848 +       uint32_t txfsz_bak[15];
20849 +
20850 +       uint16_t start_address;
20851 +       uint8_t retval = 1;
20852 +
20853 +       if (!check_fifo_sizes(core_if)) {
20854 +               return 0;
20855 +       }
20856 +
20857 +       /* Configure data FIFO sizes */
20858 +       if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
20859 +               rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
20860 +               rx_fifo_size = params->dev_rx_fifo_size;
20861 +               DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
20862 +
20863 +               /*
20864 +                * Tx FIFOs These FIFOs are numbered from 1 to 15.
20865 +                * Indexes of the FIFO size module parameters in the
20866 +                * dev_tx_fifo_size array and the FIFO size registers in
20867 +                * the dtxfsiz array run from 0 to 14.
20868 +                */
20869 +
20870 +               /* Non-periodic Tx FIFO */
20871 +               nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
20872 +               nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
20873 +               start_address = params->dev_rx_fifo_size;
20874 +               nptxfifosize.b.startaddr = start_address;
20875 +
20876 +               DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
20877 +
20878 +               start_address += nptxfifosize.b.depth;
20879 +
20880 +               for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20881 +                       txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
20882 +
20883 +                       txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
20884 +                       txfifosize[i].b.startaddr = start_address;
20885 +                       DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
20886 +                                       txfifosize[i].d32);
20887 +
20888 +                       start_address += txfifosize[i].b.depth;
20889 +               }
20890 +
20891 +               /** Check if register values are set correctly */
20892 +               if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
20893 +                       retval = 0;
20894 +               }
20895 +
20896 +               if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
20897 +                       retval = 0;
20898 +               }
20899 +
20900 +               for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20901 +                       if (txfifosize[i].d32 !=
20902 +                           DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
20903 +                               retval = 0;
20904 +                       }
20905 +               }
20906 +
20907 +               /** If register values are not set correctly, reset old values */
20908 +               if (retval == 0) {
20909 +                       DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
20910 +
20911 +                       /* Non-periodic Tx FIFO */
20912 +                       DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
20913 +
20914 +                       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
20915 +                               DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
20916 +                                               txfsz_bak[i]);
20917 +                       }
20918 +               }
20919 +       } else {
20920 +               return 0;
20921 +       }
20922 +
20923 +       /* Flush the FIFOs */
20924 +       dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
20925 +       dwc_otg_flush_rx_fifo(core_if);
20926 +
20927 +       return retval;
20928 +}
20929 +
20930 +/**
20931 + * This function sets a new value for the buffer Alignment setup.
20932 + */
20933 +static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
20934 +{
20935 +       int retval;
20936 +       uint32_t fsiz;
20937 +       uint16_t size;
20938 +       uint16_t ep_addr;
20939 +       dwc_otg_pcd_ep_t *ep;
20940 +       dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
20941 +       tx_fifo_size_setup_t *ptxfifoval;
20942 +
20943 +       ptxfifoval = (tx_fifo_size_setup_t *) buf;
20944 +       ep_addr = ptxfifoval->bEndpointAddress;
20945 +       size = ptxfifoval->wDepth;
20946 +
20947 +       ep = get_ep_by_addr(pcd, ep_addr);
20948 +
20949 +       CFI_INFO
20950 +           ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
20951 +            __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
20952 +
20953 +       if (NULL == ep) {
20954 +               CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
20955 +                        __func__, ep_addr);
20956 +               return -DWC_E_INVALID;
20957 +       }
20958 +
20959 +       fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
20960 +       params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
20961 +
20962 +       if (resize_fifos(GET_CORE_IF(pcd))) {
20963 +               retval = 0;
20964 +       } else {
20965 +               CFI_INFO
20966 +                   ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
20967 +                    __func__, ep_addr);
20968 +               params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
20969 +               retval = -DWC_E_INVALID;
20970 +       }
20971 +
20972 +       return retval;
20973 +}
20974 +
20975 +/**
20976 + * This function sets a new value for the buffer Alignment setup.
20977 + */
20978 +static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
20979 +{
20980 +       int retval;
20981 +       uint32_t fsiz;
20982 +       uint16_t size;
20983 +       dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
20984 +       rx_fifo_size_setup_t *prxfifoval;
20985 +
20986 +       prxfifoval = (rx_fifo_size_setup_t *) buf;
20987 +       size = prxfifoval->wDepth;
20988 +
20989 +       fsiz = params->dev_rx_fifo_size;
20990 +       params->dev_rx_fifo_size = size;
20991 +
20992 +       if (resize_fifos(GET_CORE_IF(pcd))) {
20993 +               retval = 0;
20994 +       } else {
20995 +               CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
20996 +                        __func__);
20997 +               params->dev_rx_fifo_size = fsiz;
20998 +               retval = -DWC_E_INVALID;
20999 +       }
21000 +
21001 +       return retval;
21002 +}
21003 +
21004 +/**
21005 + * This function reads the SG of an EP's buffer setup into the buffer buf
21006 + */
21007 +static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21008 +                            struct cfi_usb_ctrlrequest *req)
21009 +{
21010 +       int retval = -DWC_E_INVALID;
21011 +       uint8_t addr;
21012 +       cfi_ep_t *ep;
21013 +
21014 +       /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21015 +       addr = req->wValue & 0xFF;
21016 +       if (addr == 0)          /* The address should be non-zero */
21017 +               return retval;
21018 +
21019 +       ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21020 +       if (NULL == ep) {
21021 +               CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21022 +                        __func__, addr);
21023 +               return retval;
21024 +       }
21025 +
21026 +       dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
21027 +       retval = BS_SG_VAL_DESC_LEN;
21028 +       return retval;
21029 +}
21030 +
21031 +/**
21032 + * This function reads the Concatenation value of an EP's buffer mode into
21033 + * the buffer buf
21034 + */
21035 +static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21036 +                                struct cfi_usb_ctrlrequest *req)
21037 +{
21038 +       int retval = -DWC_E_INVALID;
21039 +       uint8_t addr;
21040 +       cfi_ep_t *ep;
21041 +       uint8_t desc_count;
21042 +
21043 +       /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21044 +       addr = req->wValue & 0xFF;
21045 +       if (addr == 0)          /* The address should be non-zero */
21046 +               return retval;
21047 +
21048 +       ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21049 +       if (NULL == ep) {
21050 +               CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21051 +                        __func__, addr);
21052 +               return retval;
21053 +       }
21054 +
21055 +       /* Copy the header to the buffer */
21056 +       dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
21057 +       /* Advance the buffer pointer by the header size */
21058 +       buf += BS_CONCAT_VAL_HDR_LEN;
21059 +
21060 +       desc_count = ep->bm_concat->hdr.bDescCount;
21061 +       /* Copy alll the wTxBytes to the buffer */
21062 +       dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
21063 +
21064 +       retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
21065 +       return retval;
21066 +}
21067 +
21068 +/**
21069 + * This function reads the buffer Alignment value of an EP's buffer mode into
21070 + * the buffer buf
21071 + *
21072 + * @return The total number of bytes copied to the buffer or negative error code.
21073 + */
21074 +static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
21075 +                               struct cfi_usb_ctrlrequest *req)
21076 +{
21077 +       int retval = -DWC_E_INVALID;
21078 +       uint8_t addr;
21079 +       cfi_ep_t *ep;
21080 +
21081 +       /* The Low Byte of the wValue contains a non-zero address of the endpoint */
21082 +       addr = req->wValue & 0xFF;
21083 +       if (addr == 0)          /* The address should be non-zero */
21084 +               return retval;
21085 +
21086 +       ep = get_cfi_ep_by_addr(pcd->cfi, addr);
21087 +       if (NULL == ep) {
21088 +               CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
21089 +                        __func__, addr);
21090 +               return retval;
21091 +       }
21092 +
21093 +       dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
21094 +       retval = BS_ALIGN_VAL_HDR_LEN;
21095 +
21096 +       return retval;
21097 +}
21098 +
21099 +/**
21100 + * This function sets a new value for the specified feature
21101 + *
21102 + * @param      pcd     A pointer to the PCD object
21103 + *
21104 + * @return 0 if successful, negative error code otherwise to stall the DCE.
21105 + */
21106 +static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
21107 +{
21108 +       int retval = -DWC_E_NOT_SUPPORTED;
21109 +       uint16_t wIndex, wValue;
21110 +       uint8_t bRequest;
21111 +       struct dwc_otg_core_if *coreif;
21112 +       cfiobject_t *cfi = pcd->cfi;
21113 +       struct cfi_usb_ctrlrequest *ctrl_req;
21114 +       uint8_t *buf;
21115 +       ctrl_req = &cfi->ctrl_req;
21116 +
21117 +       buf = pcd->cfi->ctrl_req.data;
21118 +
21119 +       coreif = GET_CORE_IF(pcd);
21120 +       bRequest = ctrl_req->bRequest;
21121 +       wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
21122 +       wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
21123 +
21124 +       /* See which feature is to be modified */
21125 +       switch (wIndex) {
21126 +       case FT_ID_DMA_BUFFER_SETUP:
21127 +               /* Modify the feature */
21128 +               if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
21129 +                       return retval;
21130 +
21131 +               /* And send this request to the gadget */
21132 +               cfi->need_gadget_att = 1;
21133 +               break;
21134 +
21135 +       case FT_ID_DMA_BUFF_ALIGN:
21136 +               if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
21137 +                       return retval;
21138 +               cfi->need_gadget_att = 1;
21139 +               break;
21140 +
21141 +       case FT_ID_DMA_CONCAT_SETUP:
21142 +               /* Modify the feature */
21143 +               if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
21144 +                       return retval;
21145 +               cfi->need_gadget_att = 1;
21146 +               break;
21147 +
21148 +       case FT_ID_DMA_CIRCULAR:
21149 +               CFI_INFO("FT_ID_DMA_CIRCULAR\n");
21150 +               break;
21151 +
21152 +       case FT_ID_THRESHOLD_SETUP:
21153 +               CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
21154 +               break;
21155 +
21156 +       case FT_ID_DFIFO_DEPTH:
21157 +               CFI_INFO("FT_ID_DFIFO_DEPTH\n");
21158 +               break;
21159 +
21160 +       case FT_ID_TX_FIFO_DEPTH:
21161 +               CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
21162 +               if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
21163 +                       return retval;
21164 +               cfi->need_gadget_att = 0;
21165 +               break;
21166 +
21167 +       case FT_ID_RX_FIFO_DEPTH:
21168 +               CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
21169 +               if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
21170 +                       return retval;
21171 +               cfi->need_gadget_att = 0;
21172 +               break;
21173 +       }
21174 +
21175 +       return retval;
21176 +}
21177 +
21178 +#endif //DWC_UTE_CFI
21179 --- /dev/null
21180 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cfi.h
21181 @@ -0,0 +1,320 @@
21182 +/* ==========================================================================
21183 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
21184 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
21185 + * otherwise expressly agreed to in writing between Synopsys and you.
21186 + *
21187 + * The Software IS NOT an item of Licensed Software or Licensed Product under
21188 + * any End User Software License Agreement or Agreement for Licensed Product
21189 + * with Synopsys or any supplement thereto. You are permitted to use and
21190 + * redistribute this Software in source and binary forms, with or without
21191 + * modification, provided that redistributions of source code must retain this
21192 + * notice. You may not view, use, disclose, copy or distribute this file or
21193 + * any information contained herein except pursuant to this license grant from
21194 + * Synopsys. If you do not agree with this notice, including the disclaimer
21195 + * below, then you are not authorized to use the Software.
21196 + *
21197 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
21198 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21199 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21200 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
21201 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21202 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21203 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21204 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21205 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21206 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
21207 + * DAMAGE.
21208 + * ========================================================================== */
21209 +
21210 +#if !defined(__DWC_OTG_CFI_H__)
21211 +#define __DWC_OTG_CFI_H__
21212 +
21213 +#include "dwc_otg_pcd.h"
21214 +#include "dwc_cfi_common.h"
21215 +
21216 +/**
21217 + * @file
21218 + * This file contains the CFI related OTG PCD specific common constants,
21219 + * interfaces(functions and macros) and data structures.The CFI Protocol is an
21220 + * optional interface for internal testing purposes that a DUT may implement to
21221 + * support testing of configurable features.
21222 + *
21223 + */
21224 +
21225 +struct dwc_otg_pcd;
21226 +struct dwc_otg_pcd_ep;
21227 +
21228 +/** OTG CFI Features (properties) ID constants */
21229 +/** This is a request for all Core Features */
21230 +#define FT_ID_DMA_MODE                                 0x0001
21231 +#define FT_ID_DMA_BUFFER_SETUP                 0x0002
21232 +#define FT_ID_DMA_BUFF_ALIGN                   0x0003
21233 +#define FT_ID_DMA_CONCAT_SETUP                 0x0004
21234 +#define FT_ID_DMA_CIRCULAR                             0x0005
21235 +#define FT_ID_THRESHOLD_SETUP                  0x0006
21236 +#define FT_ID_DFIFO_DEPTH                              0x0007
21237 +#define FT_ID_TX_FIFO_DEPTH                            0x0008
21238 +#define FT_ID_RX_FIFO_DEPTH                            0x0009
21239 +
21240 +/**********************************************************/
21241 +#define CFI_INFO_DEF
21242 +
21243 +#ifdef CFI_INFO_DEF
21244 +#define CFI_INFO(fmt...)       DWC_PRINTF("CFI: " fmt);
21245 +#else
21246 +#define CFI_INFO(fmt...)
21247 +#endif
21248 +
21249 +#define min(x,y) ({ \
21250 +       x < y ? x : y; })
21251 +
21252 +#define max(x,y) ({ \
21253 +       x > y ? x : y; })
21254 +
21255 +/**
21256 + * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is
21257 + * also used for setting up a buffer for Circular DDMA.
21258 + */
21259 +struct _ddma_sg_buffer_setup {
21260 +#define BS_SG_VAL_DESC_LEN     6
21261 +       /* The OUT EP address */
21262 +       uint8_t bOutEndpointAddress;
21263 +       /* The IN EP address */
21264 +       uint8_t bInEndpointAddress;
21265 +       /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
21266 +       uint8_t bOffset;
21267 +       /* The number of transfer segments (a DMA descriptors per each segment) */
21268 +       uint8_t bCount;
21269 +       /* Size (in byte) of each transfer segment */
21270 +       uint16_t wSize;
21271 +} __attribute__ ((packed));
21272 +typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
21273 +
21274 +/** Descriptor DMA Concatenation Buffer setup structure */
21275 +struct _ddma_concat_buffer_setup_hdr {
21276 +#define BS_CONCAT_VAL_HDR_LEN  4
21277 +       /* The endpoint for which the buffer is to be set up */
21278 +       uint8_t bEndpointAddress;
21279 +       /* The count of descriptors to be used */
21280 +       uint8_t bDescCount;
21281 +       /* The total size of the transfer */
21282 +       uint16_t wSize;
21283 +} __attribute__ ((packed));
21284 +typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
21285 +
21286 +/** Descriptor DMA Concatenation Buffer setup structure */
21287 +struct _ddma_concat_buffer_setup {
21288 +       /* The SG header */
21289 +       ddma_concat_buffer_setup_hdr_t hdr;
21290 +
21291 +       /* The XFER sizes pointer (allocated dynamically) */
21292 +       uint16_t *wTxBytes;
21293 +} __attribute__ ((packed));
21294 +typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
21295 +
21296 +/** Descriptor DMA Alignment Buffer setup structure */
21297 +struct _ddma_align_buffer_setup {
21298 +#define BS_ALIGN_VAL_HDR_LEN   2
21299 +       uint8_t bEndpointAddress;
21300 +       uint8_t bAlign;
21301 +} __attribute__ ((packed));
21302 +typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
21303 +
21304 +/** Transmit FIFO Size setup structure */
21305 +struct _tx_fifo_size_setup {
21306 +       uint8_t bEndpointAddress;
21307 +       uint16_t wDepth;
21308 +} __attribute__ ((packed));
21309 +typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
21310 +
21311 +/** Transmit FIFO Size setup structure */
21312 +struct _rx_fifo_size_setup {
21313 +       uint16_t wDepth;
21314 +} __attribute__ ((packed));
21315 +typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
21316 +
21317 +/**
21318 + * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest
21319 + * This structure encapsulates the standard usb_ctrlrequest and adds a pointer
21320 + * to the data returned in the data stage of a 3-stage Control Write requests.
21321 + */
21322 +struct cfi_usb_ctrlrequest {
21323 +       uint8_t bRequestType;
21324 +       uint8_t bRequest;
21325 +       uint16_t wValue;
21326 +       uint16_t wIndex;
21327 +       uint16_t wLength;
21328 +       uint8_t *data;
21329 +} UPACKED;
21330 +
21331 +/*---------------------------------------------------------------------------*/
21332 +
21333 +/**
21334 + * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures.
21335 + * This structure is used to store the buffer setup data for any
21336 + * enabled endpoint in the PCD.
21337 + */
21338 +struct cfi_ep {
21339 +       /* Entry for the list container */
21340 +       dwc_list_link_t lh;
21341 +       /* Pointer to the active PCD endpoint structure */
21342 +       struct dwc_otg_pcd_ep *ep;
21343 +       /* The last descriptor in the chain of DMA descriptors of the endpoint */
21344 +       struct dwc_otg_dma_desc *dma_desc_last;
21345 +       /* The SG feature value */
21346 +       ddma_sg_buffer_setup_t *bm_sg;
21347 +       /* The Circular feature value */
21348 +       ddma_sg_buffer_setup_t *bm_circ;
21349 +       /* The Concatenation feature value */
21350 +       ddma_concat_buffer_setup_t *bm_concat;
21351 +       /* The Alignment feature value */
21352 +       ddma_align_buffer_setup_t *bm_align;
21353 +       /* XFER length */
21354 +       uint32_t xfer_len;
21355 +       /*
21356 +        * Count of DMA descriptors currently used.
21357 +        * The total should not exceed the MAX_DMA_DESCS_PER_EP value
21358 +        * defined in the dwc_otg_cil.h
21359 +        */
21360 +       uint32_t desc_count;
21361 +};
21362 +typedef struct cfi_ep cfi_ep_t;
21363 +
21364 +typedef struct cfi_dma_buff {
21365 +#define CFI_IN_BUF_LEN 1024
21366 +#define CFI_OUT_BUF_LEN        1024
21367 +       dma_addr_t addr;
21368 +       uint8_t *buf;
21369 +} cfi_dma_buff_t;
21370 +
21371 +struct cfiobject;
21372 +
21373 +/**
21374 + * This is the interface for the CFI operations.
21375 + *
21376 + * @param      ep_enable                       Called when any endpoint is enabled and activated.
21377 + * @param      release                         Called when the CFI object is released and it needs to correctly
21378 + *                                                             deallocate the dynamic memory
21379 + * @param      ctrl_write_complete     Called when the data stage of the request is complete
21380 + */
21381 +typedef struct cfi_ops {
21382 +       int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
21383 +                         struct dwc_otg_pcd_ep * ep);
21384 +       void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
21385 +                              struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
21386 +                              unsigned size, gfp_t flags);
21387 +       void (*release) (struct cfiobject * cfi);
21388 +       int (*ctrl_write_complete) (struct cfiobject * cfi,
21389 +                                   struct dwc_otg_pcd * pcd);
21390 +       void (*build_descriptors) (struct cfiobject * cfi,
21391 +                                  struct dwc_otg_pcd * pcd,
21392 +                                  struct dwc_otg_pcd_ep * ep,
21393 +                                  dwc_otg_pcd_request_t * req);
21394 +} cfi_ops_t;
21395 +
21396 +struct cfiobject {
21397 +       cfi_ops_t ops;
21398 +       struct dwc_otg_pcd *pcd;
21399 +       struct usb_gadget *gadget;
21400 +
21401 +       /* Buffers used to send/receive CFI-related request data */
21402 +       cfi_dma_buff_t buf_in;
21403 +       cfi_dma_buff_t buf_out;
21404 +
21405 +       /* CFI specific Control request wrapper */
21406 +       struct cfi_usb_ctrlrequest ctrl_req;
21407 +
21408 +       /* The list of active EP's in the PCD of type cfi_ep_t */
21409 +       dwc_list_link_t active_eps;
21410 +
21411 +       /* This flag shall control the propagation of a specific request
21412 +        * to the gadget's processing routines.
21413 +        * 0 - no gadget handling
21414 +        * 1 - the gadget needs to know about this request (w/o completing a status
21415 +        * phase - just return a 0 to the _setup callback)
21416 +        */
21417 +       uint8_t need_gadget_att;
21418 +
21419 +       /* Flag indicating whether the status IN phase needs to be
21420 +        * completed by the PCD
21421 +        */
21422 +       uint8_t need_status_in_complete;
21423 +};
21424 +typedef struct cfiobject cfiobject_t;
21425 +
21426 +#define DUMP_MSG
21427 +
21428 +#if defined(DUMP_MSG)
21429 +static inline void dump_msg(const u8 * buf, unsigned int length)
21430 +{
21431 +       unsigned int start, num, i;
21432 +       char line[52], *p;
21433 +
21434 +       if (length >= 512)
21435 +               return;
21436 +
21437 +       start = 0;
21438 +       while (length > 0) {
21439 +               num = min(length, 16u);
21440 +               p = line;
21441 +               for (i = 0; i < num; ++i) {
21442 +                       if (i == 8)
21443 +                               *p++ = ' ';
21444 +                       DWC_SPRINTF(p, " %02x", buf[i]);
21445 +                       p += 3;
21446 +               }
21447 +               *p = 0;
21448 +               DWC_DEBUG("%6x: %s\n", start, line);
21449 +               buf += num;
21450 +               start += num;
21451 +               length -= num;
21452 +       }
21453 +}
21454 +#else
21455 +static inline void dump_msg(const u8 * buf, unsigned int length)
21456 +{
21457 +}
21458 +#endif
21459 +
21460 +/**
21461 + * This function returns a pointer to cfi_ep_t object with the addr address.
21462 + */
21463 +static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
21464 +                                               uint8_t addr)
21465 +{
21466 +       struct cfi_ep *pcfiep;
21467 +       dwc_list_link_t *tmp;
21468 +
21469 +       DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
21470 +               pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
21471 +
21472 +               if (pcfiep->ep->desc->bEndpointAddress == addr) {
21473 +                       return pcfiep;
21474 +               }
21475 +       }
21476 +
21477 +       return NULL;
21478 +}
21479 +
21480 +/**
21481 + * This function returns a pointer to cfi_ep_t object that matches
21482 + * the dwc_otg_pcd_ep object.
21483 + */
21484 +static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
21485 +                                                 struct dwc_otg_pcd_ep *ep)
21486 +{
21487 +       struct cfi_ep *pcfiep = NULL;
21488 +       dwc_list_link_t *tmp;
21489 +
21490 +       DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
21491 +               pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
21492 +               if (pcfiep->ep == ep) {
21493 +                       return pcfiep;
21494 +               }
21495 +       }
21496 +       return NULL;
21497 +}
21498 +
21499 +int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
21500 +
21501 +#endif /* (__DWC_OTG_CFI_H__) */
21502 --- /dev/null
21503 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.c
21504 @@ -0,0 +1,7141 @@
21505 +/* ==========================================================================
21506 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
21507 + * $Revision: #191 $
21508 + * $Date: 2012/08/10 $
21509 + * $Change: 2047372 $
21510 + *
21511 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
21512 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
21513 + * otherwise expressly agreed to in writing between Synopsys and you.
21514 + *
21515 + * The Software IS NOT an item of Licensed Software or Licensed Product under
21516 + * any End User Software License Agreement or Agreement for Licensed Product
21517 + * with Synopsys or any supplement thereto. You are permitted to use and
21518 + * redistribute this Software in source and binary forms, with or without
21519 + * modification, provided that redistributions of source code must retain this
21520 + * notice. You may not view, use, disclose, copy or distribute this file or
21521 + * any information contained herein except pursuant to this license grant from
21522 + * Synopsys. If you do not agree with this notice, including the disclaimer
21523 + * below, then you are not authorized to use the Software.
21524 + *
21525 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
21526 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21527 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21528 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
21529 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21530 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21531 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21532 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21533 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21534 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
21535 + * DAMAGE.
21536 + * ========================================================================== */
21537 +
21538 +/** @file
21539 + *
21540 + * The Core Interface Layer provides basic services for accessing and
21541 + * managing the DWC_otg hardware. These services are used by both the
21542 + * Host Controller Driver and the Peripheral Controller Driver.
21543 + *
21544 + * The CIL manages the memory map for the core so that the HCD and PCD
21545 + * don't have to do this separately. It also handles basic tasks like
21546 + * reading/writing the registers and data FIFOs in the controller.
21547 + * Some of the data access functions provide encapsulation of several
21548 + * operations required to perform a task, such as writing multiple
21549 + * registers to start a transfer. Finally, the CIL performs basic
21550 + * services that are not specific to either the host or device modes
21551 + * of operation. These services include management of the OTG Host
21552 + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
21553 + * Diagnostic API is also provided to allow testing of the controller
21554 + * hardware.
21555 + *
21556 + * The Core Interface Layer has the following requirements:
21557 + * - Provides basic controller operations.
21558 + * - Minimal use of OS services.
21559 + * - The OS services used will be abstracted by using inline functions
21560 + *      or macros.
21561 + *
21562 + */
21563 +
21564 +#include "dwc_os.h"
21565 +#include "dwc_otg_regs.h"
21566 +#include "dwc_otg_cil.h"
21567 +
21568 +static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
21569 +
21570 +/**
21571 + * This function is called to initialize the DWC_otg CSR data
21572 + * structures. The register addresses in the device and host
21573 + * structures are initialized from the base address supplied by the
21574 + * caller. The calling function must make the OS calls to get the
21575 + * base address of the DWC_otg controller registers. The core_params
21576 + * argument holds the parameters that specify how the core should be
21577 + * configured.
21578 + *
21579 + * @param reg_base_addr Base address of DWC_otg core registers
21580 + *
21581 + */
21582 +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
21583 +{
21584 +       dwc_otg_core_if_t *core_if = 0;
21585 +       dwc_otg_dev_if_t *dev_if = 0;
21586 +       dwc_otg_host_if_t *host_if = 0;
21587 +       uint8_t *reg_base = (uint8_t *) reg_base_addr;
21588 +       int i = 0;
21589 +
21590 +       DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
21591 +
21592 +       core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
21593 +
21594 +       if (core_if == NULL) {
21595 +               DWC_DEBUGPL(DBG_CIL,
21596 +                           "Allocation of dwc_otg_core_if_t failed\n");
21597 +               return 0;
21598 +       }
21599 +       core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
21600 +
21601 +       /*
21602 +        * Allocate the Device Mode structures.
21603 +        */
21604 +       dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
21605 +
21606 +       if (dev_if == NULL) {
21607 +               DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
21608 +               DWC_FREE(core_if);
21609 +               return 0;
21610 +       }
21611 +
21612 +       dev_if->dev_global_regs =
21613 +           (dwc_otg_device_global_regs_t *) (reg_base +
21614 +                                             DWC_DEV_GLOBAL_REG_OFFSET);
21615 +
21616 +       for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21617 +               dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
21618 +                   (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
21619 +                    (i * DWC_EP_REG_OFFSET));
21620 +
21621 +               dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
21622 +                   (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
21623 +                    (i * DWC_EP_REG_OFFSET));
21624 +               DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
21625 +                           i, &dev_if->in_ep_regs[i]->diepctl);
21626 +               DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
21627 +                           i, &dev_if->out_ep_regs[i]->doepctl);
21628 +       }
21629 +
21630 +       dev_if->speed = 0;      // unknown
21631 +
21632 +       core_if->dev_if = dev_if;
21633 +
21634 +       /*
21635 +        * Allocate the Host Mode structures.
21636 +        */
21637 +       host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
21638 +
21639 +       if (host_if == NULL) {
21640 +               DWC_DEBUGPL(DBG_CIL,
21641 +                           "Allocation of dwc_otg_host_if_t failed\n");
21642 +               DWC_FREE(dev_if);
21643 +               DWC_FREE(core_if);
21644 +               return 0;
21645 +       }
21646 +
21647 +       host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
21648 +           (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
21649 +
21650 +       host_if->hprt0 =
21651 +           (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
21652 +
21653 +       for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21654 +               host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
21655 +                   (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
21656 +                    (i * DWC_OTG_CHAN_REGS_OFFSET));
21657 +               DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
21658 +                           i, &host_if->hc_regs[i]->hcchar);
21659 +       }
21660 +
21661 +       host_if->num_host_channels = MAX_EPS_CHANNELS;
21662 +       core_if->host_if = host_if;
21663 +
21664 +       for (i = 0; i < MAX_EPS_CHANNELS; i++) {
21665 +               core_if->data_fifo[i] =
21666 +                   (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
21667 +                                 (i * DWC_OTG_DATA_FIFO_SIZE));
21668 +               DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
21669 +                           i, (unsigned long)core_if->data_fifo[i]);
21670 +       }
21671 +
21672 +       core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
21673 +
21674 +       /* Initiate lx_state to L3 disconnected state */
21675 +       core_if->lx_state = DWC_OTG_L3;
21676 +       /*
21677 +        * Store the contents of the hardware configuration registers here for
21678 +        * easy access later.
21679 +        */
21680 +       core_if->hwcfg1.d32 =
21681 +           DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
21682 +       core_if->hwcfg2.d32 =
21683 +           DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
21684 +       core_if->hwcfg3.d32 =
21685 +           DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
21686 +       core_if->hwcfg4.d32 =
21687 +           DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
21688 +
21689 +       /* Force host mode to get HPTXFSIZ exact power on value */
21690 +       {
21691 +               gusbcfg_data_t gusbcfg = {.d32 = 0 };
21692 +               gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
21693 +               gusbcfg.b.force_host_mode = 1;
21694 +               DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
21695 +               dwc_mdelay(100);
21696 +               core_if->hptxfsiz.d32 =
21697 +               DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
21698 +               gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
21699 +               gusbcfg.b.force_host_mode = 1;
21700 +               DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
21701 +               dwc_mdelay(100);
21702 +       }
21703 +
21704 +       DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
21705 +       DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
21706 +       DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
21707 +       DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
21708 +
21709 +       core_if->hcfg.d32 =
21710 +           DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
21711 +       core_if->dcfg.d32 =
21712 +           DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
21713 +
21714 +       DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
21715 +       DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
21716 +
21717 +       DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
21718 +       DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
21719 +       DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
21720 +       DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
21721 +                   core_if->hwcfg2.b.num_host_chan);
21722 +       DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
21723 +                   core_if->hwcfg2.b.nonperio_tx_q_depth);
21724 +       DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
21725 +                   core_if->hwcfg2.b.host_perio_tx_q_depth);
21726 +       DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
21727 +                   core_if->hwcfg2.b.dev_token_q_depth);
21728 +
21729 +       DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
21730 +                   core_if->hwcfg3.b.dfifo_depth);
21731 +       DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
21732 +                   core_if->hwcfg3.b.xfer_size_cntr_width);
21733 +
21734 +       /*
21735 +        * Set the SRP sucess bit for FS-I2c
21736 +        */
21737 +       core_if->srp_success = 0;
21738 +       core_if->srp_timer_started = 0;
21739 +
21740 +       /*
21741 +        * Create new workqueue and init works
21742 +        */
21743 +       core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
21744 +       if (core_if->wq_otg == 0) {
21745 +               DWC_WARN("DWC_WORKQ_ALLOC failed\n");
21746 +               DWC_FREE(host_if);
21747 +               DWC_FREE(dev_if);
21748 +               DWC_FREE(core_if);
21749 +               return 0;
21750 +       }
21751 +
21752 +       core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
21753 +
21754 +       DWC_PRINTF("Core Release: %x.%x%x%x\n",
21755 +                  (core_if->snpsid >> 12 & 0xF),
21756 +                  (core_if->snpsid >> 8 & 0xF),
21757 +                  (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
21758 +
21759 +       core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
21760 +                                            w_wakeup_detected, core_if);
21761 +       if (core_if->wkp_timer == 0) {
21762 +               DWC_WARN("DWC_TIMER_ALLOC failed\n");
21763 +               DWC_FREE(host_if);
21764 +               DWC_FREE(dev_if);
21765 +               DWC_WORKQ_FREE(core_if->wq_otg);
21766 +               DWC_FREE(core_if);
21767 +               return 0;
21768 +       }
21769 +
21770 +       if (dwc_otg_setup_params(core_if)) {
21771 +               DWC_WARN("Error while setting core params\n");
21772 +       }
21773 +
21774 +       core_if->hibernation_suspend = 0;
21775 +
21776 +       /** ADP initialization */
21777 +       dwc_otg_adp_init(core_if);
21778 +
21779 +       return core_if;
21780 +}
21781 +
21782 +/**
21783 + * This function frees the structures allocated by dwc_otg_cil_init().
21784 + *
21785 + * @param core_if The core interface pointer returned from
21786 + *               dwc_otg_cil_init().
21787 + *
21788 + */
21789 +void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
21790 +{
21791 +       dctl_data_t dctl = {.d32 = 0 };
21792 +       DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
21793 +
21794 +       /* Disable all interrupts */
21795 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
21796 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
21797 +
21798 +       dctl.b.sftdiscon = 1;
21799 +       if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
21800 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
21801 +                                dctl.d32);
21802 +       }
21803 +
21804 +       if (core_if->wq_otg) {
21805 +               DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
21806 +               DWC_WORKQ_FREE(core_if->wq_otg);
21807 +       }
21808 +       if (core_if->dev_if) {
21809 +               DWC_FREE(core_if->dev_if);
21810 +       }
21811 +       if (core_if->host_if) {
21812 +               DWC_FREE(core_if->host_if);
21813 +       }
21814 +
21815 +       /** Remove ADP Stuff  */
21816 +       dwc_otg_adp_remove(core_if);
21817 +       if (core_if->core_params) {
21818 +               DWC_FREE(core_if->core_params);
21819 +       }
21820 +       if (core_if->wkp_timer) {
21821 +               DWC_TIMER_FREE(core_if->wkp_timer);
21822 +       }
21823 +       if (core_if->srp_timer) {
21824 +               DWC_TIMER_FREE(core_if->srp_timer);
21825 +       }
21826 +       DWC_FREE(core_if);
21827 +}
21828 +
21829 +/**
21830 + * This function enables the controller's Global Interrupt in the AHB Config
21831 + * register.
21832 + *
21833 + * @param core_if Programming view of DWC_otg controller.
21834 + */
21835 +void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
21836 +{
21837 +       gahbcfg_data_t ahbcfg = {.d32 = 0 };
21838 +       ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
21839 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
21840 +}
21841 +
21842 +/**
21843 + * This function disables the controller's Global Interrupt in the AHB Config
21844 + * register.
21845 + *
21846 + * @param core_if Programming view of DWC_otg controller.
21847 + */
21848 +void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
21849 +{
21850 +       gahbcfg_data_t ahbcfg = {.d32 = 0 };
21851 +       ahbcfg.b.glblintrmsk = 1;       /* Disable interrupts */
21852 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
21853 +}
21854 +
21855 +/**
21856 + * This function initializes the commmon interrupts, used in both
21857 + * device and host modes.
21858 + *
21859 + * @param core_if Programming view of the DWC_otg controller
21860 + *
21861 + */
21862 +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
21863 +{
21864 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
21865 +       gintmsk_data_t intr_mask = {.d32 = 0 };
21866 +
21867 +       /* Clear any pending OTG Interrupts */
21868 +       DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
21869 +
21870 +       /* Clear any pending interrupts */
21871 +       DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
21872 +
21873 +       /*
21874 +        * Enable the interrupts in the GINTMSK.
21875 +        */
21876 +       intr_mask.b.modemismatch = 1;
21877 +       intr_mask.b.otgintr = 1;
21878 +
21879 +       if (!core_if->dma_enable) {
21880 +               intr_mask.b.rxstsqlvl = 1;
21881 +       }
21882 +
21883 +       intr_mask.b.conidstschng = 1;
21884 +       intr_mask.b.wkupintr = 1;
21885 +       intr_mask.b.disconnect = 0;
21886 +       intr_mask.b.usbsuspend = 1;
21887 +       intr_mask.b.sessreqintr = 1;
21888 +#ifdef CONFIG_USB_DWC_OTG_LPM
21889 +       if (core_if->core_params->lpm_enable) {
21890 +               intr_mask.b.lpmtranrcvd = 1;
21891 +       }
21892 +#endif
21893 +       DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
21894 +}
21895 +
21896 +/*
21897 + * The restore operation is modified to support Synopsys Emulated Powerdown and
21898 + * Hibernation. This function is for exiting from Device mode hibernation by
21899 + * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
21900 + * @param core_if Programming view of DWC_otg controller.
21901 + * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
21902 + * @param reset - indicates whether resume is initiated by Reset.
21903 + */
21904 +int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
21905 +                                      int rem_wakeup, int reset)
21906 +{
21907 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
21908 +       pcgcctl_data_t pcgcctl = {.d32 = 0 };
21909 +       dctl_data_t dctl = {.d32 = 0 };
21910 +
21911 +       int timeout = 2000;
21912 +
21913 +       if (!core_if->hibernation_suspend) {
21914 +               DWC_PRINTF("Already exited from Hibernation\n");
21915 +               return 1;
21916 +       }
21917 +
21918 +       DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
21919 +       /* Switch-on voltage to the core */
21920 +       gpwrdn.b.pwrdnswtch = 1;
21921 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21922 +       dwc_udelay(10);
21923 +
21924 +       /* Reset core */
21925 +       gpwrdn.d32 = 0;
21926 +       gpwrdn.b.pwrdnrstn = 1;
21927 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21928 +       dwc_udelay(10);
21929 +
21930 +       /* Assert Restore signal */
21931 +       gpwrdn.d32 = 0;
21932 +       gpwrdn.b.restore = 1;
21933 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
21934 +       dwc_udelay(10);
21935 +
21936 +       /* Disable power clamps */
21937 +       gpwrdn.d32 = 0;
21938 +       gpwrdn.b.pwrdnclmp = 1;
21939 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21940 +
21941 +       if (rem_wakeup) {
21942 +               dwc_udelay(70);
21943 +       }
21944 +
21945 +       /* Deassert Reset core */
21946 +       gpwrdn.d32 = 0;
21947 +       gpwrdn.b.pwrdnrstn = 1;
21948 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
21949 +       dwc_udelay(10);
21950 +
21951 +       /* Disable PMU interrupt */
21952 +       gpwrdn.d32 = 0;
21953 +       gpwrdn.b.pmuintsel = 1;
21954 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21955 +
21956 +       /* Mask interrupts from gpwrdn */
21957 +       gpwrdn.d32 = 0;
21958 +       gpwrdn.b.connect_det_msk = 1;
21959 +       gpwrdn.b.srp_det_msk = 1;
21960 +       gpwrdn.b.disconn_det_msk = 1;
21961 +       gpwrdn.b.rst_det_msk = 1;
21962 +       gpwrdn.b.lnstchng_msk = 1;
21963 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
21964 +
21965 +       /* Indicates that we are going out from hibernation */
21966 +       core_if->hibernation_suspend = 0;
21967 +
21968 +       /*
21969 +        * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
21970 +        * indicates restore from remote_wakeup
21971 +        */
21972 +       restore_essential_regs(core_if, rem_wakeup, 0);
21973 +
21974 +       /*
21975 +        * Wait a little for seeing new value of variable hibernation_suspend if
21976 +        * Restore done interrupt received before polling
21977 +        */
21978 +       dwc_udelay(10);
21979 +
21980 +       if (core_if->hibernation_suspend == 0) {
21981 +               /*
21982 +                * Wait For Restore_done Interrupt. This mechanism of polling the
21983 +                * interrupt is introduced to avoid any possible race conditions
21984 +                */
21985 +               do {
21986 +                       gintsts_data_t gintsts;
21987 +                       gintsts.d32 =
21988 +                           DWC_READ_REG32(&core_if->core_global_regs->gintsts);
21989 +                       if (gintsts.b.restoredone) {
21990 +                               gintsts.d32 = 0;
21991 +                               gintsts.b.restoredone = 1;
21992 +                               DWC_WRITE_REG32(&core_if->core_global_regs->
21993 +                                               gintsts, gintsts.d32);
21994 +                               DWC_PRINTF("Restore Done Interrupt seen\n");
21995 +                               break;
21996 +                       }
21997 +                       dwc_udelay(10);
21998 +               } while (--timeout);
21999 +               if (!timeout) {
22000 +                       DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
22001 +               }
22002 +       }
22003 +       /* Clear all pending interupts */
22004 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22005 +
22006 +       /* De-assert Restore */
22007 +       gpwrdn.d32 = 0;
22008 +       gpwrdn.b.restore = 1;
22009 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22010 +       dwc_udelay(10);
22011 +
22012 +       if (!rem_wakeup) {
22013 +               pcgcctl.d32 = 0;
22014 +               pcgcctl.b.rstpdwnmodule = 1;
22015 +               DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
22016 +       }
22017 +
22018 +       /* Restore GUSBCFG and DCFG */
22019 +       DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
22020 +                       core_if->gr_backup->gusbcfg_local);
22021 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
22022 +                       core_if->dr_backup->dcfg);
22023 +
22024 +       /* De-assert Wakeup Logic */
22025 +       gpwrdn.d32 = 0;
22026 +       gpwrdn.b.pmuactv = 1;
22027 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22028 +       dwc_udelay(10);
22029 +
22030 +       if (!rem_wakeup) {
22031 +               /* Set Device programming done bit */
22032 +               dctl.b.pwronprgdone = 1;
22033 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
22034 +       } else {
22035 +               /* Start Remote Wakeup Signaling */
22036 +               dctl.d32 = core_if->dr_backup->dctl;
22037 +               dctl.b.rmtwkupsig = 1;
22038 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
22039 +       }
22040 +
22041 +       dwc_mdelay(2);
22042 +       /* Clear all pending interupts */
22043 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22044 +
22045 +       /* Restore global registers */
22046 +       dwc_otg_restore_global_regs(core_if);
22047 +       /* Restore device global registers */
22048 +       dwc_otg_restore_dev_regs(core_if, rem_wakeup);
22049 +
22050 +       if (rem_wakeup) {
22051 +               dwc_mdelay(7);
22052 +               dctl.d32 = 0;
22053 +               dctl.b.rmtwkupsig = 1;
22054 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
22055 +       }
22056 +
22057 +       core_if->hibernation_suspend = 0;
22058 +       /* The core will be in ON STATE */
22059 +       core_if->lx_state = DWC_OTG_L0;
22060 +       DWC_PRINTF("Hibernation recovery completes here\n");
22061 +
22062 +       return 1;
22063 +}
22064 +
22065 +/*
22066 + * The restore operation is modified to support Synopsys Emulated Powerdown and
22067 + * Hibernation. This function is for exiting from Host mode hibernation by
22068 + * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
22069 + * @param core_if Programming view of DWC_otg controller.
22070 + * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
22071 + * @param reset - indicates whether resume is initiated by Reset.
22072 + */
22073 +int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
22074 +                                    int rem_wakeup, int reset)
22075 +{
22076 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
22077 +       hprt0_data_t hprt0 = {.d32 = 0 };
22078 +
22079 +       int timeout = 2000;
22080 +
22081 +       DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
22082 +       /* Switch-on voltage to the core */
22083 +       gpwrdn.b.pwrdnswtch = 1;
22084 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22085 +       dwc_udelay(10);
22086 +
22087 +       /* Reset core */
22088 +       gpwrdn.d32 = 0;
22089 +       gpwrdn.b.pwrdnrstn = 1;
22090 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22091 +       dwc_udelay(10);
22092 +
22093 +       /* Assert Restore signal */
22094 +       gpwrdn.d32 = 0;
22095 +       gpwrdn.b.restore = 1;
22096 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22097 +       dwc_udelay(10);
22098 +
22099 +       /* Disable power clamps */
22100 +       gpwrdn.d32 = 0;
22101 +       gpwrdn.b.pwrdnclmp = 1;
22102 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22103 +
22104 +       if (!rem_wakeup) {
22105 +               dwc_udelay(50);
22106 +       }
22107 +
22108 +       /* Deassert Reset core */
22109 +       gpwrdn.d32 = 0;
22110 +       gpwrdn.b.pwrdnrstn = 1;
22111 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
22112 +       dwc_udelay(10);
22113 +
22114 +       /* Disable PMU interrupt */
22115 +       gpwrdn.d32 = 0;
22116 +       gpwrdn.b.pmuintsel = 1;
22117 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22118 +
22119 +       gpwrdn.d32 = 0;
22120 +       gpwrdn.b.connect_det_msk = 1;
22121 +       gpwrdn.b.srp_det_msk = 1;
22122 +       gpwrdn.b.disconn_det_msk = 1;
22123 +       gpwrdn.b.rst_det_msk = 1;
22124 +       gpwrdn.b.lnstchng_msk = 1;
22125 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22126 +
22127 +       /* Indicates that we are going out from hibernation */
22128 +       core_if->hibernation_suspend = 0;
22129 +
22130 +       /* Set Restore Essential Regs bit in PCGCCTL register */
22131 +       restore_essential_regs(core_if, rem_wakeup, 1);
22132 +
22133 +       /* Wait a little for seeing new value of variable hibernation_suspend if
22134 +        * Restore done interrupt received before polling */
22135 +       dwc_udelay(10);
22136 +
22137 +       if (core_if->hibernation_suspend == 0) {
22138 +               /* Wait For Restore_done Interrupt. This mechanism of polling the
22139 +                * interrupt is introduced to avoid any possible race conditions
22140 +                */
22141 +               do {
22142 +                       gintsts_data_t gintsts;
22143 +                       gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
22144 +                       if (gintsts.b.restoredone) {
22145 +                               gintsts.d32 = 0;
22146 +                               gintsts.b.restoredone = 1;
22147 +                       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
22148 +                               DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
22149 +                               break;
22150 +                       }
22151 +                       dwc_udelay(10);
22152 +               } while (--timeout);
22153 +               if (!timeout) {
22154 +                       DWC_WARN("Restore Done interrupt wasn't generated\n");
22155 +               }
22156 +       }
22157 +
22158 +       /* Set the flag's value to 0 again after receiving restore done interrupt */
22159 +       core_if->hibernation_suspend = 0;
22160 +
22161 +       /* This step is not described in functional spec but if not wait for this
22162 +        * delay, mismatch interrupts occurred because just after restore core is
22163 +        * in Device mode(gintsts.curmode == 0) */
22164 +       dwc_mdelay(100);
22165 +
22166 +       /* Clear all pending interrupts */
22167 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22168 +
22169 +       /* De-assert Restore */
22170 +       gpwrdn.d32 = 0;
22171 +       gpwrdn.b.restore = 1;
22172 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22173 +       dwc_udelay(10);
22174 +
22175 +       /* Restore GUSBCFG and HCFG */
22176 +       DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
22177 +                       core_if->gr_backup->gusbcfg_local);
22178 +       DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
22179 +                       core_if->hr_backup->hcfg_local);
22180 +
22181 +       /* De-assert Wakeup Logic */
22182 +       gpwrdn.d32 = 0;
22183 +       gpwrdn.b.pmuactv = 1;
22184 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
22185 +       dwc_udelay(10);
22186 +
22187 +       /* Start the Resume operation by programming HPRT0 */
22188 +       hprt0.d32 = core_if->hr_backup->hprt0_local;
22189 +       hprt0.b.prtpwr = 1;
22190 +       hprt0.b.prtena = 0;
22191 +       hprt0.b.prtsusp = 0;
22192 +       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22193 +
22194 +       DWC_PRINTF("Resume Starts Now\n");
22195 +       if (!reset) {           // Indicates it is Resume Operation
22196 +               hprt0.d32 = core_if->hr_backup->hprt0_local;
22197 +               hprt0.b.prtres = 1;
22198 +               hprt0.b.prtpwr = 1;
22199 +               hprt0.b.prtena = 0;
22200 +               hprt0.b.prtsusp = 0;
22201 +               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22202 +
22203 +               if (!rem_wakeup)
22204 +                       hprt0.b.prtres = 0;
22205 +               /* Wait for Resume time and then program HPRT again */
22206 +               dwc_mdelay(100);
22207 +               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22208 +
22209 +       } else {                // Indicates it is Reset Operation
22210 +               hprt0.d32 = core_if->hr_backup->hprt0_local;
22211 +               hprt0.b.prtrst = 1;
22212 +               hprt0.b.prtpwr = 1;
22213 +               hprt0.b.prtena = 0;
22214 +               hprt0.b.prtsusp = 0;
22215 +               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22216 +               /* Wait for Reset time and then program HPRT again */
22217 +               dwc_mdelay(60);
22218 +               hprt0.b.prtrst = 0;
22219 +               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22220 +       }
22221 +       /* Clear all interrupt status */
22222 +       hprt0.d32 = dwc_otg_read_hprt0(core_if);
22223 +       hprt0.b.prtconndet = 1;
22224 +       hprt0.b.prtenchng = 1;
22225 +       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
22226 +
22227 +       /* Clear all pending interupts */
22228 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22229 +
22230 +       /* Restore global registers */
22231 +       dwc_otg_restore_global_regs(core_if);
22232 +       /* Restore host global registers */
22233 +       dwc_otg_restore_host_regs(core_if, reset);
22234 +
22235 +       /* The core will be in ON STATE */
22236 +       core_if->lx_state = DWC_OTG_L0;
22237 +       DWC_PRINTF("Hibernation recovery is complete here\n");
22238 +       return 0;
22239 +}
22240 +
22241 +/** Saves some register values into system memory. */
22242 +int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
22243 +{
22244 +       struct dwc_otg_global_regs_backup *gr;
22245 +       int i;
22246 +
22247 +       gr = core_if->gr_backup;
22248 +       if (!gr) {
22249 +               gr = DWC_ALLOC(sizeof(*gr));
22250 +               if (!gr) {
22251 +                       return -DWC_E_NO_MEMORY;
22252 +               }
22253 +               core_if->gr_backup = gr;
22254 +       }
22255 +
22256 +       gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
22257 +       gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
22258 +       gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
22259 +       gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
22260 +       gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
22261 +       gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
22262 +       gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
22263 +#ifdef CONFIG_USB_DWC_OTG_LPM
22264 +       gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
22265 +#endif
22266 +       gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
22267 +       gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
22268 +       gr->gdfifocfg_local =
22269 +           DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
22270 +       for (i = 0; i < MAX_EPS_CHANNELS; i++) {
22271 +               gr->dtxfsiz_local[i] =
22272 +                   DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
22273 +       }
22274 +
22275 +       DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
22276 +       DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl   = %08x\n", gr->gotgctl_local);
22277 +       DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
22278 +       DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg   = %08x\n", gr->gahbcfg_local);
22279 +       DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg   = %08x\n", gr->gusbcfg_local);
22280 +       DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz   = %08x\n", gr->grxfsiz_local);
22281 +       DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
22282 +                   gr->gnptxfsiz_local);
22283 +       DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz  = %08x\n",
22284 +                   gr->hptxfsiz_local);
22285 +#ifdef CONFIG_USB_DWC_OTG_LPM
22286 +       DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg   = %08x\n", gr->glpmcfg_local);
22287 +#endif
22288 +       DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl   = %08x\n", gr->gi2cctl_local);
22289 +       DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl   = %08x\n", gr->pcgcctl_local);
22290 +       DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg   = %08x\n",gr->gdfifocfg_local);
22291 +
22292 +       return 0;
22293 +}
22294 +
22295 +/** Saves GINTMSK register before setting the msk bits. */
22296 +int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
22297 +{
22298 +       struct dwc_otg_global_regs_backup *gr;
22299 +
22300 +       gr = core_if->gr_backup;
22301 +       if (!gr) {
22302 +               gr = DWC_ALLOC(sizeof(*gr));
22303 +               if (!gr) {
22304 +                       return -DWC_E_NO_MEMORY;
22305 +               }
22306 +               core_if->gr_backup = gr;
22307 +       }
22308 +
22309 +       gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
22310 +
22311 +       DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
22312 +       DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
22313 +
22314 +       return 0;
22315 +}
22316 +
22317 +int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
22318 +{
22319 +       struct dwc_otg_dev_regs_backup *dr;
22320 +       int i;
22321 +
22322 +       dr = core_if->dr_backup;
22323 +       if (!dr) {
22324 +               dr = DWC_ALLOC(sizeof(*dr));
22325 +               if (!dr) {
22326 +                       return -DWC_E_NO_MEMORY;
22327 +               }
22328 +               core_if->dr_backup = dr;
22329 +       }
22330 +
22331 +       dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
22332 +       dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
22333 +       dr->daintmsk =
22334 +           DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
22335 +       dr->diepmsk =
22336 +           DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
22337 +       dr->doepmsk =
22338 +           DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
22339 +
22340 +       for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22341 +               dr->diepctl[i] =
22342 +                   DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
22343 +               dr->dieptsiz[i] =
22344 +                   DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
22345 +               dr->diepdma[i] =
22346 +                   DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
22347 +       }
22348 +
22349 +       DWC_DEBUGPL(DBG_ANY,
22350 +                   "=============Backing Host registers==============\n");
22351 +       DWC_DEBUGPL(DBG_ANY, "Backed up dcfg            = %08x\n", dr->dcfg);
22352 +       DWC_DEBUGPL(DBG_ANY, "Backed up dctl        = %08x\n", dr->dctl);
22353 +       DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk            = %08x\n",
22354 +                   dr->daintmsk);
22355 +       DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk        = %08x\n", dr->diepmsk);
22356 +       DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk        = %08x\n", dr->doepmsk);
22357 +       for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22358 +               DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d]        = %08x\n", i,
22359 +                           dr->diepctl[i]);
22360 +               DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d]        = %08x\n",
22361 +                           i, dr->dieptsiz[i]);
22362 +               DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d]        = %08x\n", i,
22363 +                           dr->diepdma[i]);
22364 +       }
22365 +
22366 +       return 0;
22367 +}
22368 +
22369 +int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
22370 +{
22371 +       struct dwc_otg_host_regs_backup *hr;
22372 +       int i;
22373 +
22374 +       hr = core_if->hr_backup;
22375 +       if (!hr) {
22376 +               hr = DWC_ALLOC(sizeof(*hr));
22377 +               if (!hr) {
22378 +                       return -DWC_E_NO_MEMORY;
22379 +               }
22380 +               core_if->hr_backup = hr;
22381 +       }
22382 +
22383 +       hr->hcfg_local =
22384 +           DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
22385 +       hr->haintmsk_local =
22386 +           DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
22387 +       for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22388 +               hr->hcintmsk_local[i] =
22389 +                   DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
22390 +       }
22391 +       hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
22392 +       hr->hfir_local =
22393 +           DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
22394 +
22395 +       DWC_DEBUGPL(DBG_ANY,
22396 +                   "=============Backing Host registers===============\n");
22397 +       DWC_DEBUGPL(DBG_ANY, "Backed up hcfg            = %08x\n",
22398 +                   hr->hcfg_local);
22399 +       DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
22400 +       for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22401 +               DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
22402 +                           hr->hcintmsk_local[i]);
22403 +       }
22404 +       DWC_DEBUGPL(DBG_ANY, "Backed up hprt0           = %08x\n",
22405 +                   hr->hprt0_local);
22406 +       DWC_DEBUGPL(DBG_ANY, "Backed up hfir           = %08x\n",
22407 +                   hr->hfir_local);
22408 +
22409 +       return 0;
22410 +}
22411 +
22412 +int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
22413 +{
22414 +       struct dwc_otg_global_regs_backup *gr;
22415 +       int i;
22416 +
22417 +       gr = core_if->gr_backup;
22418 +       if (!gr) {
22419 +               return -DWC_E_INVALID;
22420 +       }
22421 +
22422 +       DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
22423 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
22424 +       DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
22425 +       DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
22426 +       DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
22427 +       DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
22428 +                       gr->gnptxfsiz_local);
22429 +       DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
22430 +                       gr->hptxfsiz_local);
22431 +       DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
22432 +                       gr->gdfifocfg_local);
22433 +       for (i = 0; i < MAX_EPS_CHANNELS; i++) {
22434 +               DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
22435 +                               gr->dtxfsiz_local[i]);
22436 +       }
22437 +
22438 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22439 +       DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
22440 +       DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
22441 +                       (gr->gahbcfg_local));
22442 +       return 0;
22443 +}
22444 +
22445 +int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
22446 +{
22447 +       struct dwc_otg_dev_regs_backup *dr;
22448 +       int i;
22449 +
22450 +       dr = core_if->dr_backup;
22451 +
22452 +       if (!dr) {
22453 +               return -DWC_E_INVALID;
22454 +       }
22455 +
22456 +       if (!rem_wakeup) {
22457 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
22458 +                               dr->dctl);
22459 +       }
22460 +
22461 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
22462 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
22463 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
22464 +
22465 +       for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
22466 +               DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
22467 +               DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
22468 +               DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
22469 +       }
22470 +
22471 +       return 0;
22472 +}
22473 +
22474 +int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
22475 +{
22476 +       struct dwc_otg_host_regs_backup *hr;
22477 +       int i;
22478 +       hr = core_if->hr_backup;
22479 +
22480 +       if (!hr) {
22481 +               return -DWC_E_INVALID;
22482 +       }
22483 +
22484 +       DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
22485 +       //if (!reset)
22486 +       //{
22487 +       //      DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
22488 +       //}
22489 +
22490 +       DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
22491 +                       hr->haintmsk_local);
22492 +       for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
22493 +               DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
22494 +                               hr->hcintmsk_local[i]);
22495 +       }
22496 +
22497 +       return 0;
22498 +}
22499 +
22500 +int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
22501 +{
22502 +       struct dwc_otg_global_regs_backup *gr;
22503 +
22504 +       gr = core_if->gr_backup;
22505 +
22506 +       /* Restore values for LPM and I2C */
22507 +#ifdef CONFIG_USB_DWC_OTG_LPM
22508 +       DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
22509 +#endif
22510 +       DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
22511 +
22512 +       return 0;
22513 +}
22514 +
22515 +int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
22516 +{
22517 +       struct dwc_otg_global_regs_backup *gr;
22518 +       pcgcctl_data_t pcgcctl = {.d32 = 0 };
22519 +       gahbcfg_data_t gahbcfg = {.d32 = 0 };
22520 +       gusbcfg_data_t gusbcfg = {.d32 = 0 };
22521 +       gintmsk_data_t gintmsk = {.d32 = 0 };
22522 +
22523 +       /* Restore LPM and I2C registers */
22524 +       restore_lpm_i2c_regs(core_if);
22525 +
22526 +       /* Set PCGCCTL to 0 */
22527 +       DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
22528 +
22529 +       gr = core_if->gr_backup;
22530 +       /* Load restore values for [31:14] bits */
22531 +       DWC_WRITE_REG32(core_if->pcgcctl,
22532 +                       ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
22533 +
22534 +       /* Umnask global Interrupt in GAHBCFG and restore it */
22535 +       gahbcfg.d32 = gr->gahbcfg_local;
22536 +       gahbcfg.b.glblintrmsk = 1;
22537 +       DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
22538 +
22539 +       /* Clear all pending interupts */
22540 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
22541 +
22542 +       /* Unmask restore done interrupt */
22543 +       gintmsk.b.restoredone = 1;
22544 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
22545 +
22546 +       /* Restore GUSBCFG and HCFG/DCFG */
22547 +       gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
22548 +       DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
22549 +
22550 +       if (is_host) {
22551 +               hcfg_data_t hcfg = {.d32 = 0 };
22552 +               hcfg.d32 = core_if->hr_backup->hcfg_local;
22553 +               DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
22554 +                               hcfg.d32);
22555 +
22556 +               /* Load restore values for [31:14] bits */
22557 +               pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22558 +               pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22559 +
22560 +               if (rmode)
22561 +                       pcgcctl.b.restoremode = 1;
22562 +               DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22563 +               dwc_udelay(10);
22564 +
22565 +               /* Load restore values for [31:14] bits and set EssRegRestored bit */
22566 +               pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
22567 +               pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22568 +               pcgcctl.b.ess_reg_restored = 1;
22569 +               if (rmode)
22570 +                       pcgcctl.b.restoremode = 1;
22571 +               DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22572 +       } else {
22573 +               dcfg_data_t dcfg = {.d32 = 0 };
22574 +               dcfg.d32 = core_if->dr_backup->dcfg;
22575 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
22576 +
22577 +               /* Load restore values for [31:14] bits */
22578 +               pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22579 +               pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22580 +               if (!rmode) {
22581 +                       pcgcctl.d32 |= 0x208;
22582 +               }
22583 +               DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22584 +               dwc_udelay(10);
22585 +
22586 +               /* Load restore values for [31:14] bits */
22587 +               pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
22588 +               pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
22589 +               pcgcctl.b.ess_reg_restored = 1;
22590 +               if (!rmode)
22591 +                       pcgcctl.d32 |= 0x208;
22592 +               DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
22593 +       }
22594 +
22595 +       return 0;
22596 +}
22597 +
22598 +/**
22599 + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
22600 + * type.
22601 + */
22602 +static void init_fslspclksel(dwc_otg_core_if_t * core_if)
22603 +{
22604 +       uint32_t val;
22605 +       hcfg_data_t hcfg;
22606 +
22607 +       if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
22608 +            (core_if->hwcfg2.b.fs_phy_type == 1) &&
22609 +            (core_if->core_params->ulpi_fs_ls)) ||
22610 +           (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22611 +               /* Full speed PHY */
22612 +               val = DWC_HCFG_48_MHZ;
22613 +       } else {
22614 +               /* High speed PHY running at full speed or high speed */
22615 +               val = DWC_HCFG_30_60_MHZ;
22616 +       }
22617 +
22618 +       DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
22619 +       hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
22620 +       hcfg.b.fslspclksel = val;
22621 +       DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
22622 +}
22623 +
22624 +/**
22625 + * Initializes the DevSpd field of the DCFG register depending on the PHY type
22626 + * and the enumeration speed of the device.
22627 + */
22628 +static void init_devspd(dwc_otg_core_if_t * core_if)
22629 +{
22630 +       uint32_t val;
22631 +       dcfg_data_t dcfg;
22632 +
22633 +       if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
22634 +            (core_if->hwcfg2.b.fs_phy_type == 1) &&
22635 +            (core_if->core_params->ulpi_fs_ls)) ||
22636 +           (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22637 +               /* Full speed PHY */
22638 +               val = 0x3;
22639 +       } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
22640 +               /* High speed PHY running at full speed */
22641 +               val = 0x1;
22642 +       } else {
22643 +               /* High speed PHY running at high speed */
22644 +               val = 0x0;
22645 +       }
22646 +
22647 +       DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
22648 +
22649 +       dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
22650 +       dcfg.b.devspd = val;
22651 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
22652 +}
22653 +
22654 +/**
22655 + * This function calculates the number of IN EPS
22656 + * using GHWCFG1 and GHWCFG2 registers values
22657 + *
22658 + * @param core_if Programming view of the DWC_otg controller
22659 + */
22660 +static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
22661 +{
22662 +       uint32_t num_in_eps = 0;
22663 +       uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
22664 +       uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
22665 +       uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
22666 +       int i;
22667 +
22668 +       for (i = 0; i < num_eps; ++i) {
22669 +               if (!(hwcfg1 & 0x1))
22670 +                       num_in_eps++;
22671 +
22672 +               hwcfg1 >>= 2;
22673 +       }
22674 +
22675 +       if (core_if->hwcfg4.b.ded_fifo_en) {
22676 +               num_in_eps =
22677 +                   (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
22678 +       }
22679 +
22680 +       return num_in_eps;
22681 +}
22682 +
22683 +/**
22684 + * This function calculates the number of OUT EPS
22685 + * using GHWCFG1 and GHWCFG2 registers values
22686 + *
22687 + * @param core_if Programming view of the DWC_otg controller
22688 + */
22689 +static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
22690 +{
22691 +       uint32_t num_out_eps = 0;
22692 +       uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
22693 +       uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
22694 +       int i;
22695 +
22696 +       for (i = 0; i < num_eps; ++i) {
22697 +               if (!(hwcfg1 & 0x1))
22698 +                       num_out_eps++;
22699 +
22700 +               hwcfg1 >>= 2;
22701 +       }
22702 +       return num_out_eps;
22703 +}
22704 +
22705 +/**
22706 + * This function initializes the DWC_otg controller registers and
22707 + * prepares the core for device mode or host mode operation.
22708 + *
22709 + * @param core_if Programming view of the DWC_otg controller
22710 + *
22711 + */
22712 +void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
22713 +{
22714 +       int i = 0;
22715 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
22716 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
22717 +       gahbcfg_data_t ahbcfg = {.d32 = 0 };
22718 +       gusbcfg_data_t usbcfg = {.d32 = 0 };
22719 +       gi2cctl_data_t i2cctl = {.d32 = 0 };
22720 +
22721 +       DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n",
22722 +                    core_if, global_regs);
22723 +
22724 +       /* Common Initialization */
22725 +       usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22726 +
22727 +       /* Program the ULPI External VBUS bit if needed */
22728 +       usbcfg.b.ulpi_ext_vbus_drv =
22729 +           (core_if->core_params->phy_ulpi_ext_vbus ==
22730 +            DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
22731 +
22732 +       /* Set external TS Dline pulsing */
22733 +       usbcfg.b.term_sel_dl_pulse =
22734 +           (core_if->core_params->ts_dline == 1) ? 1 : 0;
22735 +       DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22736 +
22737 +       /* Reset the Controller */
22738 +       dwc_otg_core_reset(core_if);
22739 +
22740 +       core_if->adp_enable = core_if->core_params->adp_supp_enable;
22741 +       core_if->power_down = core_if->core_params->power_down;
22742 +       core_if->otg_sts = 0;
22743 +
22744 +       /* Initialize parameters from Hardware configuration registers. */
22745 +       dev_if->num_in_eps = calc_num_in_eps(core_if);
22746 +       dev_if->num_out_eps = calc_num_out_eps(core_if);
22747 +
22748 +       DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
22749 +                   core_if->hwcfg4.b.num_dev_perio_in_ep);
22750 +
22751 +       for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
22752 +               dev_if->perio_tx_fifo_size[i] =
22753 +                   DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
22754 +               DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
22755 +                           i, dev_if->perio_tx_fifo_size[i]);
22756 +       }
22757 +
22758 +       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
22759 +               dev_if->tx_fifo_size[i] =
22760 +                   DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
22761 +               DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
22762 +                           i, dev_if->tx_fifo_size[i]);
22763 +       }
22764 +
22765 +       core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
22766 +       core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
22767 +       core_if->nperio_tx_fifo_size =
22768 +           DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
22769 +
22770 +       DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
22771 +       DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
22772 +       DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
22773 +                   core_if->nperio_tx_fifo_size);
22774 +
22775 +       /* This programming sequence needs to happen in FS mode before any other
22776 +        * programming occurs */
22777 +       if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
22778 +           (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
22779 +               /* If FS mode with FS PHY */
22780 +
22781 +               /* core_init() is now called on every switch so only call the
22782 +                * following for the first time through. */
22783 +               if (!core_if->phy_init_done) {
22784 +                       core_if->phy_init_done = 1;
22785 +                       DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
22786 +                       usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22787 +                       usbcfg.b.physel = 1;
22788 +                       DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22789 +
22790 +                       /* Reset after a PHY select */
22791 +                       dwc_otg_core_reset(core_if);
22792 +               }
22793 +
22794 +               /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
22795 +                * do this on HNP Dev/Host mode switches (done in dev_init and
22796 +                * host_init). */
22797 +               if (dwc_otg_is_host_mode(core_if)) {
22798 +                       init_fslspclksel(core_if);
22799 +               } else {
22800 +                       init_devspd(core_if);
22801 +               }
22802 +
22803 +               if (core_if->core_params->i2c_enable) {
22804 +                       DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
22805 +                       /* Program GUSBCFG.OtgUtmifsSel to I2C */
22806 +                       usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22807 +                       usbcfg.b.otgutmifssel = 1;
22808 +                       DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22809 +
22810 +                       /* Program GI2CCTL.I2CEn */
22811 +                       i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
22812 +                       i2cctl.b.i2cdevaddr = 1;
22813 +                       i2cctl.b.i2cen = 0;
22814 +                       DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
22815 +                       i2cctl.b.i2cen = 1;
22816 +                       DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
22817 +               }
22818 +
22819 +       } /* endif speed == DWC_SPEED_PARAM_FULL */
22820 +       else {
22821 +               /* High speed PHY. */
22822 +               if (!core_if->phy_init_done) {
22823 +                       core_if->phy_init_done = 1;
22824 +                       /* HS PHY parameters.  These parameters are preserved
22825 +                        * during soft reset so only program the first time.  Do
22826 +                        * a soft reset immediately after setting phyif.  */
22827 +
22828 +                       if (core_if->core_params->phy_type == 2) {
22829 +                               /* ULPI interface */
22830 +                               usbcfg.b.ulpi_utmi_sel = 1;
22831 +                               usbcfg.b.phyif = 0;
22832 +                               usbcfg.b.ddrsel =
22833 +                                   core_if->core_params->phy_ulpi_ddr;
22834 +                       } else if (core_if->core_params->phy_type == 1) {
22835 +                               /* UTMI+ interface */
22836 +                               usbcfg.b.ulpi_utmi_sel = 0;
22837 +                               if (core_if->core_params->phy_utmi_width == 16) {
22838 +                                       usbcfg.b.phyif = 1;
22839 +
22840 +                               } else {
22841 +                                       usbcfg.b.phyif = 0;
22842 +                               }
22843 +                       } else {
22844 +                               DWC_ERROR("FS PHY TYPE\n");
22845 +                       }
22846 +                       DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22847 +                       /* Reset after setting the PHY parameters */
22848 +                       dwc_otg_core_reset(core_if);
22849 +               }
22850 +       }
22851 +
22852 +       if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
22853 +           (core_if->hwcfg2.b.fs_phy_type == 1) &&
22854 +           (core_if->core_params->ulpi_fs_ls)) {
22855 +               DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
22856 +               usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22857 +               usbcfg.b.ulpi_fsls = 1;
22858 +               usbcfg.b.ulpi_clk_sus_m = 1;
22859 +               DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22860 +       } else {
22861 +               usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22862 +               usbcfg.b.ulpi_fsls = 0;
22863 +               usbcfg.b.ulpi_clk_sus_m = 0;
22864 +               DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22865 +       }
22866 +
22867 +       /* Program the GAHBCFG Register. */
22868 +       switch (core_if->hwcfg2.b.architecture) {
22869 +
22870 +       case DWC_SLAVE_ONLY_ARCH:
22871 +               DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
22872 +               ahbcfg.b.nptxfemplvl_txfemplvl =
22873 +                   DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
22874 +               ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
22875 +               core_if->dma_enable = 0;
22876 +               core_if->dma_desc_enable = 0;
22877 +               break;
22878 +
22879 +       case DWC_EXT_DMA_ARCH:
22880 +               DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
22881 +               {
22882 +                       uint8_t brst_sz = core_if->core_params->dma_burst_size;
22883 +                       ahbcfg.b.hburstlen = 0;
22884 +                       while (brst_sz > 1) {
22885 +                               ahbcfg.b.hburstlen++;
22886 +                               brst_sz >>= 1;
22887 +                       }
22888 +               }
22889 +               core_if->dma_enable = (core_if->core_params->dma_enable != 0);
22890 +               core_if->dma_desc_enable =
22891 +                   (core_if->core_params->dma_desc_enable != 0);
22892 +               break;
22893 +
22894 +       case DWC_INT_DMA_ARCH:
22895 +               DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
22896 +               /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
22897 +                 Host mode ISOC in issue fix - vahrama */
22898 +               /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */
22899 +               ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4;
22900 +               core_if->dma_enable = (core_if->core_params->dma_enable != 0);
22901 +               core_if->dma_desc_enable =
22902 +                   (core_if->core_params->dma_desc_enable != 0);
22903 +               break;
22904 +
22905 +       }
22906 +       if (core_if->dma_enable) {
22907 +               if (core_if->dma_desc_enable) {
22908 +                       DWC_PRINTF("Using Descriptor DMA mode\n");
22909 +               } else {
22910 +                       DWC_PRINTF("Using Buffer DMA mode\n");
22911 +
22912 +               }
22913 +       } else {
22914 +               DWC_PRINTF("Using Slave mode\n");
22915 +               core_if->dma_desc_enable = 0;
22916 +       }
22917 +
22918 +       if (core_if->core_params->ahb_single) {
22919 +               ahbcfg.b.ahbsingle = 1;
22920 +       }
22921 +
22922 +       ahbcfg.b.dmaenable = core_if->dma_enable;
22923 +       DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
22924 +
22925 +       core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
22926 +
22927 +       core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
22928 +       core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
22929 +       DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
22930 +                  ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
22931 +       DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
22932 +                  ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
22933 +
22934 +       /*
22935 +        * Program the GUSBCFG register.
22936 +        */
22937 +       usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
22938 +
22939 +       switch (core_if->hwcfg2.b.op_mode) {
22940 +       case DWC_MODE_HNP_SRP_CAPABLE:
22941 +               usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
22942 +                                  DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
22943 +               usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
22944 +                                  DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
22945 +               break;
22946 +
22947 +       case DWC_MODE_SRP_ONLY_CAPABLE:
22948 +               usbcfg.b.hnpcap = 0;
22949 +               usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
22950 +                                  DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
22951 +               break;
22952 +
22953 +       case DWC_MODE_NO_HNP_SRP_CAPABLE:
22954 +               usbcfg.b.hnpcap = 0;
22955 +               usbcfg.b.srpcap = 0;
22956 +               break;
22957 +
22958 +       case DWC_MODE_SRP_CAPABLE_DEVICE:
22959 +               usbcfg.b.hnpcap = 0;
22960 +               usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
22961 +                                  DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
22962 +               break;
22963 +
22964 +       case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
22965 +               usbcfg.b.hnpcap = 0;
22966 +               usbcfg.b.srpcap = 0;
22967 +               break;
22968 +
22969 +       case DWC_MODE_SRP_CAPABLE_HOST:
22970 +               usbcfg.b.hnpcap = 0;
22971 +               usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
22972 +                                  DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
22973 +               break;
22974 +
22975 +       case DWC_MODE_NO_SRP_CAPABLE_HOST:
22976 +               usbcfg.b.hnpcap = 0;
22977 +               usbcfg.b.srpcap = 0;
22978 +               break;
22979 +       }
22980 +
22981 +       DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
22982 +
22983 +#ifdef CONFIG_USB_DWC_OTG_LPM
22984 +       if (core_if->core_params->lpm_enable) {
22985 +               glpmcfg_data_t lpmcfg = {.d32 = 0 };
22986 +
22987 +               /* To enable LPM support set lpm_cap_en bit */
22988 +               lpmcfg.b.lpm_cap_en = 1;
22989 +
22990 +               /* Make AppL1Res ACK */
22991 +               lpmcfg.b.appl_resp = 1;
22992 +
22993 +               /* Retry 3 times */
22994 +               lpmcfg.b.retry_count = 3;
22995 +
22996 +               DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
22997 +                                0, lpmcfg.d32);
22998 +
22999 +       }
23000 +#endif
23001 +       if (core_if->core_params->ic_usb_cap) {
23002 +               gusbcfg_data_t gusbcfg = {.d32 = 0 };
23003 +               gusbcfg.b.ic_usb_cap = 1;
23004 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
23005 +                                0, gusbcfg.d32);
23006 +       }
23007 +       {
23008 +               gotgctl_data_t gotgctl = {.d32 = 0 };
23009 +               gotgctl.b.otgver = core_if->core_params->otg_ver;
23010 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
23011 +                                gotgctl.d32);
23012 +               /* Set OTG version supported */
23013 +               core_if->otg_ver = core_if->core_params->otg_ver;
23014 +               DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
23015 +                          core_if->core_params->otg_ver, core_if->otg_ver);
23016 +       }
23017 +
23018 +
23019 +       /* Enable common interrupts */
23020 +       dwc_otg_enable_common_interrupts(core_if);
23021 +
23022 +       /* Do device or host intialization based on mode during PCD
23023 +        * and HCD initialization  */
23024 +       if (dwc_otg_is_host_mode(core_if)) {
23025 +               DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
23026 +               core_if->op_state = A_HOST;
23027 +       } else {
23028 +               DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
23029 +               core_if->op_state = B_PERIPHERAL;
23030 +#ifdef DWC_DEVICE_ONLY
23031 +               dwc_otg_core_dev_init(core_if);
23032 +#endif
23033 +       }
23034 +}
23035 +
23036 +/**
23037 + * This function enables the Device mode interrupts.
23038 + *
23039 + * @param core_if Programming view of DWC_otg controller
23040 + */
23041 +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
23042 +{
23043 +       gintmsk_data_t intr_mask = {.d32 = 0 };
23044 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23045 +
23046 +       DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
23047 +
23048 +       /* Disable all interrupts. */
23049 +       DWC_WRITE_REG32(&global_regs->gintmsk, 0);
23050 +
23051 +       /* Clear any pending interrupts */
23052 +       DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
23053 +
23054 +       /* Enable the common interrupts */
23055 +       dwc_otg_enable_common_interrupts(core_if);
23056 +
23057 +       /* Enable interrupts */
23058 +       intr_mask.b.usbreset = 1;
23059 +       intr_mask.b.enumdone = 1;
23060 +       /* Disable Disconnect interrupt in Device mode */
23061 +       intr_mask.b.disconnect = 0;
23062 +
23063 +       if (!core_if->multiproc_int_enable) {
23064 +               intr_mask.b.inepintr = 1;
23065 +               intr_mask.b.outepintr = 1;
23066 +       }
23067 +
23068 +       intr_mask.b.erlysuspend = 1;
23069 +
23070 +       if (core_if->en_multiple_tx_fifo == 0) {
23071 +               intr_mask.b.epmismatch = 1;
23072 +       }
23073 +
23074 +       //intr_mask.b.incomplisoout = 1;
23075 +       intr_mask.b.incomplisoin = 1;
23076 +
23077 +/* Enable the ignore frame number for ISOC xfers - MAS */
23078 +/* Disable to support high bandwith ISOC transfers - manukz */
23079 +#if 0
23080 +#ifdef DWC_UTE_PER_IO
23081 +       if (core_if->dma_enable) {
23082 +               if (core_if->dma_desc_enable) {
23083 +                       dctl_data_t dctl1 = {.d32 = 0 };
23084 +                       dctl1.b.ifrmnum = 1;
23085 +                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
23086 +                                        dctl, 0, dctl1.d32);
23087 +                       DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
23088 +                                 DWC_READ_REG32(&core_if->dev_if->
23089 +                                                dev_global_regs->dctl));
23090 +               }
23091 +       }
23092 +#endif
23093 +#endif
23094 +#ifdef DWC_EN_ISOC
23095 +       if (core_if->dma_enable) {
23096 +               if (core_if->dma_desc_enable == 0) {
23097 +                       if (core_if->pti_enh_enable) {
23098 +                               dctl_data_t dctl = {.d32 = 0 };
23099 +                               dctl.b.ifrmnum = 1;
23100 +                               DWC_MODIFY_REG32(&core_if->
23101 +                                                dev_if->dev_global_regs->dctl,
23102 +                                                0, dctl.d32);
23103 +                       } else {
23104 +                               intr_mask.b.incomplisoin = 1;
23105 +                               intr_mask.b.incomplisoout = 1;
23106 +                       }
23107 +               }
23108 +       } else {
23109 +               intr_mask.b.incomplisoin = 1;
23110 +               intr_mask.b.incomplisoout = 1;
23111 +       }
23112 +#endif /* DWC_EN_ISOC */
23113 +
23114 +       /** @todo NGS: Should this be a module parameter? */
23115 +#ifdef USE_PERIODIC_EP
23116 +       intr_mask.b.isooutdrop = 1;
23117 +       intr_mask.b.eopframe = 1;
23118 +       intr_mask.b.incomplisoin = 1;
23119 +       intr_mask.b.incomplisoout = 1;
23120 +#endif
23121 +
23122 +       DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
23123 +
23124 +       DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
23125 +                   DWC_READ_REG32(&global_regs->gintmsk));
23126 +}
23127 +
23128 +/**
23129 + * This function initializes the DWC_otg controller registers for
23130 + * device mode.
23131 + *
23132 + * @param core_if Programming view of DWC_otg controller
23133 + *
23134 + */
23135 +void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
23136 +{
23137 +       int i;
23138 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23139 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
23140 +       dwc_otg_core_params_t *params = core_if->core_params;
23141 +       dcfg_data_t dcfg = {.d32 = 0 };
23142 +       depctl_data_t diepctl = {.d32 = 0 };
23143 +       grstctl_t resetctl = {.d32 = 0 };
23144 +       uint32_t rx_fifo_size;
23145 +       fifosize_data_t nptxfifosize;
23146 +       fifosize_data_t txfifosize;
23147 +       dthrctl_data_t dthrctl;
23148 +       fifosize_data_t ptxfifosize;
23149 +       uint16_t rxfsiz, nptxfsiz;
23150 +       gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
23151 +       hwcfg3_data_t hwcfg3 = {.d32 = 0 };
23152 +
23153 +       /* Restart the Phy Clock */
23154 +       DWC_WRITE_REG32(core_if->pcgcctl, 0);
23155 +
23156 +       /* Device configuration register */
23157 +       init_devspd(core_if);
23158 +       dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
23159 +       dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
23160 +       dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
23161 +       /* Enable Device OUT NAK in case of DDMA mode*/
23162 +       if (core_if->core_params->dev_out_nak) {
23163 +               dcfg.b.endevoutnak = 1;
23164 +       }
23165 +
23166 +       if (core_if->core_params->cont_on_bna) {
23167 +               dctl_data_t dctl = {.d32 = 0 };
23168 +               dctl.b.encontonbna = 1;
23169 +               DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
23170 +       }
23171 +
23172 +
23173 +       DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
23174 +
23175 +       /* Configure data FIFO sizes */
23176 +       if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
23177 +               DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
23178 +                           core_if->total_fifo_size);
23179 +               DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
23180 +                           params->dev_rx_fifo_size);
23181 +               DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
23182 +                           params->dev_nperio_tx_fifo_size);
23183 +
23184 +               /* Rx FIFO */
23185 +               DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
23186 +                           DWC_READ_REG32(&global_regs->grxfsiz));
23187 +
23188 +#ifdef DWC_UTE_CFI
23189 +               core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
23190 +               core_if->init_rxfsiz = params->dev_rx_fifo_size;
23191 +#endif
23192 +               rx_fifo_size = params->dev_rx_fifo_size;
23193 +               DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
23194 +
23195 +               DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
23196 +                           DWC_READ_REG32(&global_regs->grxfsiz));
23197 +
23198 +               /** Set Periodic Tx FIFO Mask all bits 0 */
23199 +               core_if->p_tx_msk = 0;
23200 +
23201 +               /** Set Tx FIFO Mask all bits 0 */
23202 +               core_if->tx_msk = 0;
23203 +
23204 +               if (core_if->en_multiple_tx_fifo == 0) {
23205 +                       /* Non-periodic Tx FIFO */
23206 +                       DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23207 +                                   DWC_READ_REG32(&global_regs->gnptxfsiz));
23208 +
23209 +                       nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
23210 +                       nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
23211 +
23212 +                       DWC_WRITE_REG32(&global_regs->gnptxfsiz,
23213 +                                       nptxfifosize.d32);
23214 +
23215 +                       DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23216 +                                   DWC_READ_REG32(&global_regs->gnptxfsiz));
23217 +
23218 +                       /**@todo NGS: Fix Periodic FIFO Sizing! */
23219 +                       /*
23220 +                        * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
23221 +                        * Indexes of the FIFO size module parameters in the
23222 +                        * dev_perio_tx_fifo_size array and the FIFO size registers in
23223 +                        * the dptxfsiz array run from 0 to 14.
23224 +                        */
23225 +                       /** @todo Finish debug of this */
23226 +                       ptxfifosize.b.startaddr =
23227 +                           nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23228 +                       for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
23229 +                               ptxfifosize.b.depth =
23230 +                                   params->dev_perio_tx_fifo_size[i];
23231 +                               DWC_DEBUGPL(DBG_CIL,
23232 +                                           "initial dtxfsiz[%d]=%08x\n", i,
23233 +                                           DWC_READ_REG32(&global_regs->dtxfsiz
23234 +                                                          [i]));
23235 +                               DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
23236 +                                               ptxfifosize.d32);
23237 +                               DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
23238 +                                           i,
23239 +                                           DWC_READ_REG32(&global_regs->dtxfsiz
23240 +                                                          [i]));
23241 +                               ptxfifosize.b.startaddr += ptxfifosize.b.depth;
23242 +                       }
23243 +               } else {
23244 +                       /*
23245 +                        * Tx FIFOs These FIFOs are numbered from 1 to 15.
23246 +                        * Indexes of the FIFO size module parameters in the
23247 +                        * dev_tx_fifo_size array and the FIFO size registers in
23248 +                        * the dtxfsiz array run from 0 to 14.
23249 +                        */
23250 +
23251 +                       /* Non-periodic Tx FIFO */
23252 +                       DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23253 +                                   DWC_READ_REG32(&global_regs->gnptxfsiz));
23254 +
23255 +#ifdef DWC_UTE_CFI
23256 +                       core_if->pwron_gnptxfsiz =
23257 +                           (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23258 +                       core_if->init_gnptxfsiz =
23259 +                           params->dev_nperio_tx_fifo_size;
23260 +#endif
23261 +                       nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
23262 +                       nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
23263 +
23264 +                       DWC_WRITE_REG32(&global_regs->gnptxfsiz,
23265 +                                       nptxfifosize.d32);
23266 +
23267 +                       DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23268 +                                   DWC_READ_REG32(&global_regs->gnptxfsiz));
23269 +
23270 +                       txfifosize.b.startaddr =
23271 +                           nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23272 +
23273 +                       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
23274 +
23275 +                               txfifosize.b.depth =
23276 +                                   params->dev_tx_fifo_size[i];
23277 +
23278 +                               DWC_DEBUGPL(DBG_CIL,
23279 +                                           "initial dtxfsiz[%d]=%08x\n",
23280 +                                           i,
23281 +                                           DWC_READ_REG32(&global_regs->dtxfsiz
23282 +                                                          [i]));
23283 +
23284 +#ifdef DWC_UTE_CFI
23285 +                               core_if->pwron_txfsiz[i] =
23286 +                                   (DWC_READ_REG32
23287 +                                    (&global_regs->dtxfsiz[i]) >> 16);
23288 +                               core_if->init_txfsiz[i] =
23289 +                                   params->dev_tx_fifo_size[i];
23290 +#endif
23291 +                               DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
23292 +                                               txfifosize.d32);
23293 +
23294 +                               DWC_DEBUGPL(DBG_CIL,
23295 +                                           "new dtxfsiz[%d]=%08x\n",
23296 +                                           i,
23297 +                                           DWC_READ_REG32(&global_regs->dtxfsiz
23298 +                                                          [i]));
23299 +
23300 +                               txfifosize.b.startaddr += txfifosize.b.depth;
23301 +                       }
23302 +                       if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
23303 +                               /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
23304 +                               gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
23305 +                               hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
23306 +                               gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
23307 +                               DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23308 +                               rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
23309 +                               nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23310 +                               gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
23311 +                               DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23312 +                       }
23313 +               }
23314 +
23315 +               /* Flush the FIFOs */
23316 +               dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
23317 +               dwc_otg_flush_rx_fifo(core_if);
23318 +
23319 +               /* Flush the Learning Queue. */
23320 +               resetctl.b.intknqflsh = 1;
23321 +               DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
23322 +
23323 +               if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
23324 +                       core_if->start_predict = 0;
23325 +                       for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
23326 +                               core_if->nextep_seq[i] = 0xff;  // 0xff - EP not active
23327 +                       }
23328 +                       core_if->nextep_seq[0] = 0;
23329 +                       core_if->first_in_nextep_seq = 0;
23330 +                       diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
23331 +                       diepctl.b.nextep = 0;
23332 +                       DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
23333 +
23334 +                       /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
23335 +                       dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
23336 +                       dcfg.b.epmscnt = 2;
23337 +                       DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
23338 +
23339 +                       DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
23340 +                               __func__, core_if->first_in_nextep_seq);
23341 +                       for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
23342 +                               DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
23343 +                       }
23344 +                       DWC_DEBUGPL(DBG_CILV,"\n");
23345 +               }
23346 +
23347 +               /* Clear all pending Device Interrupts */
23348 +               /** @todo - if the condition needed to be checked
23349 +                *  or in any case all pending interrutps should be cleared?
23350 +            */
23351 +               if (core_if->multiproc_int_enable) {
23352 +                       for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
23353 +                               DWC_WRITE_REG32(&dev_if->
23354 +                                               dev_global_regs->diepeachintmsk[i], 0);
23355 +                       }
23356 +               }
23357 +
23358 +               for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
23359 +                       DWC_WRITE_REG32(&dev_if->
23360 +                                       dev_global_regs->doepeachintmsk[i], 0);
23361 +               }
23362 +
23363 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
23364 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
23365 +       } else {
23366 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
23367 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
23368 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
23369 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
23370 +       }
23371 +
23372 +       for (i = 0; i <= dev_if->num_in_eps; i++) {
23373 +               depctl_data_t depctl;
23374 +               depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
23375 +               if (depctl.b.epena) {
23376 +                       depctl.d32 = 0;
23377 +                       depctl.b.epdis = 1;
23378 +                       depctl.b.snak = 1;
23379 +               } else {
23380 +                       depctl.d32 = 0;
23381 +               }
23382 +
23383 +               DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
23384 +
23385 +               DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
23386 +               DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
23387 +               DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
23388 +       }
23389 +
23390 +       for (i = 0; i <= dev_if->num_out_eps; i++) {
23391 +               depctl_data_t depctl;
23392 +               depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
23393 +               if (depctl.b.epena) {
23394 +                       dctl_data_t dctl = {.d32 = 0 };
23395 +                       gintmsk_data_t gintsts = {.d32 = 0 };
23396 +                       doepint_data_t doepint = {.d32 = 0 };
23397 +                       dctl.b.sgoutnak = 1;
23398 +                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
23399 +                       do {
23400 +                               dwc_udelay(10);
23401 +                               gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
23402 +                       } while (!gintsts.b.goutnakeff);
23403 +                       gintsts.d32 = 0;
23404 +                       gintsts.b.goutnakeff = 1;
23405 +                       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
23406 +
23407 +                       depctl.d32 = 0;
23408 +                       depctl.b.epdis = 1;
23409 +                       depctl.b.snak = 1;
23410 +                       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
23411 +                       do {
23412 +                               dwc_udelay(10);
23413 +                               doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
23414 +                                       out_ep_regs[i]->doepint);
23415 +                       } while (!doepint.b.epdisabled);
23416 +
23417 +                       doepint.b.epdisabled = 1;
23418 +                       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
23419 +
23420 +                       dctl.d32 = 0;
23421 +                       dctl.b.cgoutnak = 1;
23422 +                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
23423 +               } else {
23424 +                       depctl.d32 = 0;
23425 +               }
23426 +
23427 +               DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
23428 +
23429 +               DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
23430 +               DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
23431 +               DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
23432 +       }
23433 +
23434 +       if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
23435 +               dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
23436 +               dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
23437 +               dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
23438 +
23439 +               dev_if->rx_thr_length = params->rx_thr_length;
23440 +               dev_if->tx_thr_length = params->tx_thr_length;
23441 +
23442 +               dev_if->setup_desc_index = 0;
23443 +
23444 +               dthrctl.d32 = 0;
23445 +               dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
23446 +               dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
23447 +               dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
23448 +               dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
23449 +               dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
23450 +               dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
23451 +
23452 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
23453 +                               dthrctl.d32);
23454 +
23455 +               DWC_DEBUGPL(DBG_CIL,
23456 +                           "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
23457 +                           dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
23458 +                           dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
23459 +                           dthrctl.b.rx_thr_len);
23460 +
23461 +       }
23462 +
23463 +       dwc_otg_enable_device_interrupts(core_if);
23464 +
23465 +       {
23466 +               diepmsk_data_t msk = {.d32 = 0 };
23467 +               msk.b.txfifoundrn = 1;
23468 +               if (core_if->multiproc_int_enable) {
23469 +                       DWC_MODIFY_REG32(&dev_if->dev_global_regs->
23470 +                                        diepeachintmsk[0], msk.d32, msk.d32);
23471 +               } else {
23472 +                       DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
23473 +                                        msk.d32, msk.d32);
23474 +               }
23475 +       }
23476 +
23477 +       if (core_if->multiproc_int_enable) {
23478 +               /* Set NAK on Babble */
23479 +               dctl_data_t dctl = {.d32 = 0 };
23480 +               dctl.b.nakonbble = 1;
23481 +               DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
23482 +       }
23483 +
23484 +       if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
23485 +               dctl_data_t dctl = {.d32 = 0 };
23486 +               dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
23487 +               dctl.b.sftdiscon = 0;
23488 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
23489 +       }
23490 +}
23491 +
23492 +/**
23493 + * This function enables the Host mode interrupts.
23494 + *
23495 + * @param core_if Programming view of DWC_otg controller
23496 + */
23497 +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
23498 +{
23499 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23500 +       gintmsk_data_t intr_mask = {.d32 = 0 };
23501 +
23502 +       DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if);
23503 +
23504 +       /* Disable all interrupts. */
23505 +       DWC_WRITE_REG32(&global_regs->gintmsk, 0);
23506 +
23507 +       /* Clear any pending interrupts. */
23508 +       DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
23509 +
23510 +       /* Enable the common interrupts */
23511 +       dwc_otg_enable_common_interrupts(core_if);
23512 +
23513 +       /*
23514 +        * Enable host mode interrupts without disturbing common
23515 +        * interrupts.
23516 +        */
23517 +
23518 +       intr_mask.b.disconnect = 1;
23519 +       intr_mask.b.portintr = 1;
23520 +       intr_mask.b.hcintr = 1;
23521 +
23522 +       DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
23523 +}
23524 +
23525 +/**
23526 + * This function disables the Host Mode interrupts.
23527 + *
23528 + * @param core_if Programming view of DWC_otg controller
23529 + */
23530 +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
23531 +{
23532 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23533 +       gintmsk_data_t intr_mask = {.d32 = 0 };
23534 +
23535 +       DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
23536 +
23537 +       /*
23538 +        * Disable host mode interrupts without disturbing common
23539 +        * interrupts.
23540 +        */
23541 +       intr_mask.b.sofintr = 1;
23542 +       intr_mask.b.portintr = 1;
23543 +       intr_mask.b.hcintr = 1;
23544 +       intr_mask.b.ptxfempty = 1;
23545 +       intr_mask.b.nptxfempty = 1;
23546 +
23547 +       DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
23548 +}
23549 +
23550 +/**
23551 + * This function initializes the DWC_otg controller registers for
23552 + * host mode.
23553 + *
23554 + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
23555 + * request queues. Host channels are reset to ensure that they are ready for
23556 + * performing transfers.
23557 + *
23558 + * @param core_if Programming view of DWC_otg controller
23559 + *
23560 + */
23561 +void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
23562 +{
23563 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
23564 +       dwc_otg_host_if_t *host_if = core_if->host_if;
23565 +       dwc_otg_core_params_t *params = core_if->core_params;
23566 +       hprt0_data_t hprt0 = {.d32 = 0 };
23567 +       fifosize_data_t nptxfifosize;
23568 +       fifosize_data_t ptxfifosize;
23569 +       uint16_t rxfsiz, nptxfsiz, hptxfsiz;
23570 +       gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
23571 +       int i;
23572 +       hcchar_data_t hcchar;
23573 +       hcfg_data_t hcfg;
23574 +       hfir_data_t hfir;
23575 +       dwc_otg_hc_regs_t *hc_regs;
23576 +       int num_channels;
23577 +       gotgctl_data_t gotgctl = {.d32 = 0 };
23578 +
23579 +       DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
23580 +
23581 +       /* Restart the Phy Clock */
23582 +       DWC_WRITE_REG32(core_if->pcgcctl, 0);
23583 +
23584 +       /* Initialize Host Configuration Register */
23585 +       init_fslspclksel(core_if);
23586 +       if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
23587 +               hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
23588 +               hcfg.b.fslssupp = 1;
23589 +               DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
23590 +
23591 +       }
23592 +
23593 +       /* This bit allows dynamic reloading of the HFIR register
23594 +        * during runtime. This bit needs to be programmed during
23595 +        * initial configuration and its value must not be changed
23596 +        * during runtime.*/
23597 +       if (core_if->core_params->reload_ctl == 1) {
23598 +               hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
23599 +               hfir.b.hfirrldctrl = 1;
23600 +               DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
23601 +       }
23602 +
23603 +       if (core_if->core_params->dma_desc_enable) {
23604 +               uint8_t op_mode = core_if->hwcfg2.b.op_mode;
23605 +               if (!
23606 +                   (core_if->hwcfg4.b.desc_dma
23607 +                    && (core_if->snpsid >= OTG_CORE_REV_2_90a)
23608 +                    && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
23609 +                        || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
23610 +                        || (op_mode ==
23611 +                            DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
23612 +                        || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
23613 +                        || (op_mode ==
23614 +                            DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
23615 +
23616 +                       DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
23617 +                                 "Either core version is below 2.90a or "
23618 +                                 "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
23619 +                                 "To run the driver in Buffer DMA host mode set dma_desc_enable "
23620 +                                 "module parameter to 0.\n");
23621 +                       return;
23622 +               }
23623 +               hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
23624 +               hcfg.b.descdma = 1;
23625 +               DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
23626 +       }
23627 +
23628 +       /* Configure data FIFO sizes */
23629 +       if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
23630 +               DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
23631 +                           core_if->total_fifo_size);
23632 +               DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
23633 +                           params->host_rx_fifo_size);
23634 +               DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
23635 +                           params->host_nperio_tx_fifo_size);
23636 +               DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
23637 +                           params->host_perio_tx_fifo_size);
23638 +
23639 +               /* Rx FIFO */
23640 +               DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
23641 +                           DWC_READ_REG32(&global_regs->grxfsiz));
23642 +               DWC_WRITE_REG32(&global_regs->grxfsiz,
23643 +                               params->host_rx_fifo_size);
23644 +               DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
23645 +                           DWC_READ_REG32(&global_regs->grxfsiz));
23646 +
23647 +               /* Non-periodic Tx FIFO */
23648 +               DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
23649 +                           DWC_READ_REG32(&global_regs->gnptxfsiz));
23650 +               nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
23651 +               nptxfifosize.b.startaddr = params->host_rx_fifo_size;
23652 +               DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
23653 +               DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
23654 +                           DWC_READ_REG32(&global_regs->gnptxfsiz));
23655 +
23656 +               /* Periodic Tx FIFO */
23657 +               DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
23658 +                           DWC_READ_REG32(&global_regs->hptxfsiz));
23659 +               ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
23660 +               ptxfifosize.b.startaddr =
23661 +                   nptxfifosize.b.startaddr + nptxfifosize.b.depth;
23662 +               DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
23663 +               DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
23664 +                           DWC_READ_REG32(&global_regs->hptxfsiz));
23665 +
23666 +               if (core_if->en_multiple_tx_fifo
23667 +                   && core_if->snpsid <= OTG_CORE_REV_2_94a) {
23668 +                       /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
23669 +                       gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
23670 +                       rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
23671 +                       nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
23672 +                       hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
23673 +                       gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
23674 +                       DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
23675 +               }
23676 +       }
23677 +
23678 +       /* TODO - check this */
23679 +       /* Clear Host Set HNP Enable in the OTG Control Register */
23680 +       gotgctl.b.hstsethnpen = 1;
23681 +       DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
23682 +       /* Make sure the FIFOs are flushed. */
23683 +       dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
23684 +       dwc_otg_flush_rx_fifo(core_if);
23685 +
23686 +       /* Clear Host Set HNP Enable in the OTG Control Register */
23687 +       gotgctl.b.hstsethnpen = 1;
23688 +       DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
23689 +
23690 +       if (!core_if->core_params->dma_desc_enable) {
23691 +               /* Flush out any leftover queued requests. */
23692 +               num_channels = core_if->core_params->host_channels;
23693 +
23694 +               for (i = 0; i < num_channels; i++) {
23695 +                       hc_regs = core_if->host_if->hc_regs[i];
23696 +                       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23697 +                       hcchar.b.chen = 0;
23698 +                       hcchar.b.chdis = 1;
23699 +                       hcchar.b.epdir = 0;
23700 +                       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23701 +               }
23702 +
23703 +               /* Halt all channels to put them into a known state. */
23704 +               for (i = 0; i < num_channels; i++) {
23705 +                       int count = 0;
23706 +                       hc_regs = core_if->host_if->hc_regs[i];
23707 +                       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23708 +                       hcchar.b.chen = 1;
23709 +                       hcchar.b.chdis = 1;
23710 +                       hcchar.b.epdir = 0;
23711 +                       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
23712 +                       DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs);
23713 +                       do {
23714 +                               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23715 +                               if (++count > 1000) {
23716 +                                       DWC_ERROR
23717 +                                           ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n",
23718 +                                            __func__, i, hcchar.d32, &hc_regs->hcchar);
23719 +                                       break;
23720 +                               }
23721 +                               dwc_udelay(1);
23722 +                       } while (hcchar.b.chen);
23723 +               }
23724 +       }
23725 +
23726 +       /* Turn on the vbus power. */
23727 +       DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
23728 +       if (core_if->op_state == A_HOST) {
23729 +               hprt0.d32 = dwc_otg_read_hprt0(core_if);
23730 +               DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
23731 +               if (hprt0.b.prtpwr == 0) {
23732 +                       hprt0.b.prtpwr = 1;
23733 +                       DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
23734 +               }
23735 +       }
23736 +
23737 +       dwc_otg_enable_host_interrupts(core_if);
23738 +}
23739 +
23740 +/**
23741 + * Prepares a host channel for transferring packets to/from a specific
23742 + * endpoint. The HCCHARn register is set up with the characteristics specified
23743 + * in _hc. Host channel interrupts that may need to be serviced while this
23744 + * transfer is in progress are enabled.
23745 + *
23746 + * @param core_if Programming view of DWC_otg controller
23747 + * @param hc Information needed to initialize the host channel
23748 + */
23749 +void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
23750 +{
23751 +       hcintmsk_data_t hc_intr_mask;
23752 +       hcchar_data_t hcchar;
23753 +       hcsplt_data_t hcsplt;
23754 +
23755 +       uint8_t hc_num = hc->hc_num;
23756 +       dwc_otg_host_if_t *host_if = core_if->host_if;
23757 +       dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
23758 +
23759 +       /* Clear old interrupt conditions for this host channel. */
23760 +       hc_intr_mask.d32 = 0xFFFFFFFF;
23761 +       hc_intr_mask.b.reserved14_31 = 0;
23762 +       DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
23763 +
23764 +       /* Enable channel interrupts required for this transfer. */
23765 +       hc_intr_mask.d32 = 0;
23766 +       hc_intr_mask.b.chhltd = 1;
23767 +       if (core_if->dma_enable) {
23768 +               /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
23769 +               if (!core_if->dma_desc_enable)
23770 +                       hc_intr_mask.b.ahberr = 1;
23771 +               else {
23772 +                       if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
23773 +                               hc_intr_mask.b.xfercompl = 1;
23774 +               }
23775 +
23776 +               if (hc->error_state && !hc->do_split &&
23777 +                   hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
23778 +                       hc_intr_mask.b.ack = 1;
23779 +                       if (hc->ep_is_in) {
23780 +                               hc_intr_mask.b.datatglerr = 1;
23781 +                               if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
23782 +                                       hc_intr_mask.b.nak = 1;
23783 +                               }
23784 +                       }
23785 +               }
23786 +       } else {
23787 +               switch (hc->ep_type) {
23788 +               case DWC_OTG_EP_TYPE_CONTROL:
23789 +               case DWC_OTG_EP_TYPE_BULK:
23790 +                       hc_intr_mask.b.xfercompl = 1;
23791 +                       hc_intr_mask.b.stall = 1;
23792 +                       hc_intr_mask.b.xacterr = 1;
23793 +                       hc_intr_mask.b.datatglerr = 1;
23794 +                       if (hc->ep_is_in) {
23795 +                               hc_intr_mask.b.bblerr = 1;
23796 +                       } else {
23797 +                               hc_intr_mask.b.nak = 1;
23798 +                               hc_intr_mask.b.nyet = 1;
23799 +                               if (hc->do_ping) {
23800 +                                       hc_intr_mask.b.ack = 1;
23801 +                               }
23802 +                       }
23803 +
23804 +                       if (hc->do_split) {
23805 +                               hc_intr_mask.b.nak = 1;
23806 +                               if (hc->complete_split) {
23807 +                                       hc_intr_mask.b.nyet = 1;
23808 +                               } else {
23809 +                                       hc_intr_mask.b.ack = 1;
23810 +                               }
23811 +                       }
23812 +
23813 +                       if (hc->error_state) {
23814 +                               hc_intr_mask.b.ack = 1;
23815 +                       }
23816 +                       break;
23817 +               case DWC_OTG_EP_TYPE_INTR:
23818 +                       hc_intr_mask.b.xfercompl = 1;
23819 +                       hc_intr_mask.b.nak = 1;
23820 +                       hc_intr_mask.b.stall = 1;
23821 +                       hc_intr_mask.b.xacterr = 1;
23822 +                       hc_intr_mask.b.datatglerr = 1;
23823 +                       hc_intr_mask.b.frmovrun = 1;
23824 +
23825 +                       if (hc->ep_is_in) {
23826 +                               hc_intr_mask.b.bblerr = 1;
23827 +                       }
23828 +                       if (hc->error_state) {
23829 +                               hc_intr_mask.b.ack = 1;
23830 +                       }
23831 +                       if (hc->do_split) {
23832 +                               if (hc->complete_split) {
23833 +                                       hc_intr_mask.b.nyet = 1;
23834 +                               } else {
23835 +                                       hc_intr_mask.b.ack = 1;
23836 +                               }
23837 +                       }
23838 +                       break;
23839 +               case DWC_OTG_EP_TYPE_ISOC:
23840 +                       hc_intr_mask.b.xfercompl = 1;
23841 +                       hc_intr_mask.b.frmovrun = 1;
23842 +                       hc_intr_mask.b.ack = 1;
23843 +
23844 +                       if (hc->ep_is_in) {
23845 +                               hc_intr_mask.b.xacterr = 1;
23846 +                               hc_intr_mask.b.bblerr = 1;
23847 +                       }
23848 +                       break;
23849 +               }
23850 +       }
23851 +       DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
23852 +
23853 +       /*
23854 +        * Program the HCCHARn register with the endpoint characteristics for
23855 +        * the current transfer.
23856 +        */
23857 +       hcchar.d32 = 0;
23858 +       hcchar.b.devaddr = hc->dev_addr;
23859 +       hcchar.b.epnum = hc->ep_num;
23860 +       hcchar.b.epdir = hc->ep_is_in;
23861 +       hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
23862 +       hcchar.b.eptype = hc->ep_type;
23863 +       hcchar.b.mps = hc->max_packet;
23864 +
23865 +       DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
23866 +
23867 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n",
23868 +                    __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum);
23869 +       DWC_DEBUGPL(DBG_HCDV, "  Is In %d, Is Low Speed %d, EP Type %d, "
23870 +                                "Max Pkt %d, Multi Cnt %d\n",
23871 +                    hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype,
23872 +                    hcchar.b.mps, hcchar.b.multicnt);
23873 +
23874 +       /*
23875 +        * Program the HCSPLIT register for SPLITs
23876 +        */
23877 +       hcsplt.d32 = 0;
23878 +       if (hc->do_split) {
23879 +               DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
23880 +                           hc->hc_num,
23881 +                           hc->complete_split ? "CSPLIT" : "SSPLIT");
23882 +               hcsplt.b.compsplt = hc->complete_split;
23883 +               hcsplt.b.xactpos = hc->xact_pos;
23884 +               hcsplt.b.hubaddr = hc->hub_addr;
23885 +               hcsplt.b.prtaddr = hc->port_addr;
23886 +               DWC_DEBUGPL(DBG_HCDV, "\t  comp split %d\n", hc->complete_split);
23887 +               DWC_DEBUGPL(DBG_HCDV, "\t  xact pos %d\n", hc->xact_pos);
23888 +               DWC_DEBUGPL(DBG_HCDV, "\t  hub addr %d\n", hc->hub_addr);
23889 +               DWC_DEBUGPL(DBG_HCDV, "\t  port addr %d\n", hc->port_addr);
23890 +               DWC_DEBUGPL(DBG_HCDV, "\t  is_in %d\n", hc->ep_is_in);
23891 +               DWC_DEBUGPL(DBG_HCDV, "\t  Max Pkt: %d\n", hcchar.b.mps);
23892 +               DWC_DEBUGPL(DBG_HCDV, "\t  xferlen: %d\n", hc->xfer_len);
23893 +       }
23894 +       DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
23895 +
23896 +}
23897 +
23898 +/**
23899 + * Attempts to halt a host channel. This function should only be called in
23900 + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
23901 + * normal circumstances in DMA mode, the controller halts the channel when the
23902 + * transfer is complete or a condition occurs that requires application
23903 + * intervention.
23904 + *
23905 + * In slave mode, checks for a free request queue entry, then sets the Channel
23906 + * Enable and Channel Disable bits of the Host Channel Characteristics
23907 + * register of the specified channel to intiate the halt. If there is no free
23908 + * request queue entry, sets only the Channel Disable bit of the HCCHARn
23909 + * register to flush requests for this channel. In the latter case, sets a
23910 + * flag to indicate that the host channel needs to be halted when a request
23911 + * queue slot is open.
23912 + *
23913 + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
23914 + * HCCHARn register. The controller ensures there is space in the request
23915 + * queue before submitting the halt request.
23916 + *
23917 + * Some time may elapse before the core flushes any posted requests for this
23918 + * host channel and halts. The Channel Halted interrupt handler completes the
23919 + * deactivation of the host channel.
23920 + *
23921 + * @param core_if Controller register interface.
23922 + * @param hc Host channel to halt.
23923 + * @param halt_status Reason for halting the channel.
23924 + */
23925 +void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
23926 +                    dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
23927 +{
23928 +       gnptxsts_data_t nptxsts;
23929 +       hptxsts_data_t hptxsts;
23930 +       hcchar_data_t hcchar;
23931 +       dwc_otg_hc_regs_t *hc_regs;
23932 +       dwc_otg_core_global_regs_t *global_regs;
23933 +       dwc_otg_host_global_regs_t *host_global_regs;
23934 +
23935 +       hc_regs = core_if->host_if->hc_regs[hc->hc_num];
23936 +       global_regs = core_if->core_global_regs;
23937 +       host_global_regs = core_if->host_if->host_global_regs;
23938 +
23939 +       DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
23940 +                  "halt_status = %d\n", halt_status);
23941 +
23942 +       if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
23943 +           halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
23944 +               /*
23945 +                * Disable all channel interrupts except Ch Halted. The QTD
23946 +                * and QH state associated with this transfer has been cleared
23947 +                * (in the case of URB_DEQUEUE), so the channel needs to be
23948 +                * shut down carefully to prevent crashes.
23949 +                */
23950 +               hcintmsk_data_t hcintmsk;
23951 +               hcintmsk.d32 = 0;
23952 +               hcintmsk.b.chhltd = 1;
23953 +               DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
23954 +
23955 +               /*
23956 +                * Make sure no other interrupts besides halt are currently
23957 +                * pending. Handling another interrupt could cause a crash due
23958 +                * to the QTD and QH state.
23959 +                */
23960 +               DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
23961 +
23962 +               /*
23963 +                * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
23964 +                * even if the channel was already halted for some other
23965 +                * reason.
23966 +                */
23967 +               hc->halt_status = halt_status;
23968 +
23969 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
23970 +               if (hcchar.b.chen == 0) {
23971 +                       /*
23972 +                        * The channel is either already halted or it hasn't
23973 +                        * started yet. In DMA mode, the transfer may halt if
23974 +                        * it finishes normally or a condition occurs that
23975 +                        * requires driver intervention. Don't want to halt
23976 +                        * the channel again. In either Slave or DMA mode,
23977 +                        * it's possible that the transfer has been assigned
23978 +                        * to a channel, but not started yet when an URB is
23979 +                        * dequeued. Don't want to halt a channel that hasn't
23980 +                        * started yet.
23981 +                        */
23982 +                       return;
23983 +               }
23984 +       }
23985 +       if (hc->halt_pending) {
23986 +               /*
23987 +                * A halt has already been issued for this channel. This might
23988 +                * happen when a transfer is aborted by a higher level in
23989 +                * the stack.
23990 +                */
23991 +#ifdef DEBUG
23992 +               DWC_PRINTF
23993 +                   ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
23994 +                    __func__, hc->hc_num);
23995 +
23996 +#endif
23997 +               return;
23998 +       }
23999 +
24000 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24001 +
24002 +       /* No need to set the bit in DDMA for disabling the channel */
24003 +       //TODO check it everywhere channel is disabled
24004 +       if (!core_if->core_params->dma_desc_enable)
24005 +               hcchar.b.chen = 1;
24006 +       hcchar.b.chdis = 1;
24007 +
24008 +       if (!core_if->dma_enable) {
24009 +               /* Check for space in the request queue to issue the halt. */
24010 +               if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
24011 +                   hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
24012 +                       nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
24013 +                       if (nptxsts.b.nptxqspcavail == 0) {
24014 +                               hcchar.b.chen = 0;
24015 +                       }
24016 +               } else {
24017 +                       hptxsts.d32 =
24018 +                           DWC_READ_REG32(&host_global_regs->hptxsts);
24019 +                       if ((hptxsts.b.ptxqspcavail == 0)
24020 +                           || (core_if->queuing_high_bandwidth)) {
24021 +                               hcchar.b.chen = 0;
24022 +                       }
24023 +               }
24024 +       }
24025 +       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24026 +
24027 +       hc->halt_status = halt_status;
24028 +
24029 +       if (hcchar.b.chen) {
24030 +               hc->halt_pending = 1;
24031 +               hc->halt_on_queue = 0;
24032 +       } else {
24033 +               hc->halt_on_queue = 1;
24034 +       }
24035 +
24036 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24037 +       DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
24038 +       DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
24039 +       DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
24040 +       DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
24041 +
24042 +       return;
24043 +}
24044 +
24045 +/**
24046 + * Clears the transfer state for a host channel. This function is normally
24047 + * called after a transfer is done and the host channel is being released.
24048 + *
24049 + * @param core_if Programming view of DWC_otg controller.
24050 + * @param hc Identifies the host channel to clean up.
24051 + */
24052 +void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24053 +{
24054 +       dwc_otg_hc_regs_t *hc_regs;
24055 +
24056 +       hc->xfer_started = 0;
24057 +
24058 +       /*
24059 +        * Clear channel interrupt enables and any unhandled channel interrupt
24060 +        * conditions.
24061 +        */
24062 +       hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24063 +       DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
24064 +       DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
24065 +#ifdef DEBUG
24066 +       DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
24067 +#endif
24068 +}
24069 +
24070 +/**
24071 + * Sets the channel property that indicates in which frame a periodic transfer
24072 + * should occur. This is always set to the _next_ frame. This function has no
24073 + * effect on non-periodic transfers.
24074 + *
24075 + * @param core_if Programming view of DWC_otg controller.
24076 + * @param hc Identifies the host channel to set up and its properties.
24077 + * @param hcchar Current value of the HCCHAR register for the specified host
24078 + * channel.
24079 + */
24080 +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
24081 +                                        dwc_hc_t * hc, hcchar_data_t * hcchar)
24082 +{
24083 +       if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24084 +           hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24085 +               hfnum_data_t hfnum;
24086 +               hfnum.d32 =
24087 +                   DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
24088 +
24089 +               /* 1 if _next_ frame is odd, 0 if it's even */
24090 +               hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
24091 +#ifdef DEBUG
24092 +               if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
24093 +                   && !hc->complete_split) {
24094 +                       switch (hfnum.b.frnum & 0x7) {
24095 +                       case 7:
24096 +                               core_if->hfnum_7_samples++;
24097 +                               core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
24098 +                               break;
24099 +                       case 0:
24100 +                               core_if->hfnum_0_samples++;
24101 +                               core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
24102 +                               break;
24103 +                       default:
24104 +                               core_if->hfnum_other_samples++;
24105 +                               core_if->hfnum_other_frrem_accum +=
24106 +                                   hfnum.b.frrem;
24107 +                               break;
24108 +                       }
24109 +               }
24110 +#endif
24111 +       }
24112 +}
24113 +
24114 +#ifdef DEBUG
24115 +void hc_xfer_timeout(void *ptr)
24116 +{
24117 +       hc_xfer_info_t *xfer_info = NULL;
24118 +       int hc_num = 0;
24119 +
24120 +       if (ptr)
24121 +               xfer_info = (hc_xfer_info_t *) ptr;
24122 +
24123 +       if (!xfer_info->hc) {
24124 +               DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
24125 +               return;
24126 +       }
24127 +
24128 +       hc_num = xfer_info->hc->hc_num;
24129 +       DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
24130 +       DWC_WARN("      start_hcchar_val 0x%08x\n",
24131 +                xfer_info->core_if->start_hcchar_val[hc_num]);
24132 +}
24133 +#endif
24134 +
24135 +void ep_xfer_timeout(void *ptr)
24136 +{
24137 +       ep_xfer_info_t *xfer_info = NULL;
24138 +       int ep_num = 0;
24139 +       dctl_data_t dctl = {.d32 = 0 };
24140 +       gintsts_data_t gintsts = {.d32 = 0 };
24141 +       gintmsk_data_t gintmsk = {.d32 = 0 };
24142 +
24143 +       if (ptr)
24144 +               xfer_info = (ep_xfer_info_t *) ptr;
24145 +
24146 +       if (!xfer_info->ep) {
24147 +               DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
24148 +               return;
24149 +       }
24150 +
24151 +       ep_num = xfer_info->ep->num;
24152 +       DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
24153 +       /* Put the sate to 2 as it was time outed */
24154 +       xfer_info->state = 2;
24155 +
24156 +       dctl.d32 =
24157 +           DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
24158 +       gintsts.d32 =
24159 +           DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
24160 +       gintmsk.d32 =
24161 +           DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
24162 +
24163 +       if (!gintmsk.b.goutnakeff) {
24164 +               /* Unmask it */
24165 +               gintmsk.b.goutnakeff = 1;
24166 +               DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
24167 +                               gintmsk.d32);
24168 +
24169 +       }
24170 +
24171 +       if (!gintsts.b.goutnakeff) {
24172 +               dctl.b.sgoutnak = 1;
24173 +       }
24174 +       DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
24175 +                       dctl.d32);
24176 +
24177 +}
24178 +
24179 +void set_pid_isoc(dwc_hc_t * hc)
24180 +{
24181 +       /* Set up the initial PID for the transfer. */
24182 +       if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
24183 +               if (hc->ep_is_in) {
24184 +                       if (hc->multi_count == 1) {
24185 +                               hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24186 +                       } else if (hc->multi_count == 2) {
24187 +                               hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
24188 +                       } else {
24189 +                               hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
24190 +                       }
24191 +               } else {
24192 +                       if (hc->multi_count == 1) {
24193 +                               hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24194 +                       } else {
24195 +                               hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
24196 +                       }
24197 +               }
24198 +       } else {
24199 +               hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
24200 +       }
24201 +}
24202 +
24203 +/**
24204 + * This function does the setup for a data transfer for a host channel and
24205 + * starts the transfer. May be called in either Slave mode or DMA mode. In
24206 + * Slave mode, the caller must ensure that there is sufficient space in the
24207 + * request queue and Tx Data FIFO.
24208 + *
24209 + * For an OUT transfer in Slave mode, it loads a data packet into the
24210 + * appropriate FIFO. If necessary, additional data packets will be loaded in
24211 + * the Host ISR.
24212 + *
24213 + * For an IN transfer in Slave mode, a data packet is requested. The data
24214 + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
24215 + * additional data packets are requested in the Host ISR.
24216 + *
24217 + * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
24218 + * register along with a packet count of 1 and the channel is enabled. This
24219 + * causes a single PING transaction to occur. Other fields in HCTSIZ are
24220 + * simply set to 0 since no data transfer occurs in this case.
24221 + *
24222 + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
24223 + * all the information required to perform the subsequent data transfer. In
24224 + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
24225 + * controller performs the entire PING protocol, then starts the data
24226 + * transfer.
24227 + *
24228 + * @param core_if Programming view of DWC_otg controller.
24229 + * @param hc Information needed to initialize the host channel. The xfer_len
24230 + * value may be reduced to accommodate the max widths of the XferSize and
24231 + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
24232 + * to reflect the final xfer_len value.
24233 + */
24234 +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24235 +{
24236 +       hcchar_data_t hcchar;
24237 +       hctsiz_data_t hctsiz;
24238 +       uint16_t num_packets;
24239 +       uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
24240 +       uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
24241 +       dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24242 +
24243 +       hctsiz.d32 = 0;
24244 +
24245 +       if (hc->do_ping) {
24246 +               if (!core_if->dma_enable) {
24247 +                       dwc_otg_hc_do_ping(core_if, hc);
24248 +                       hc->xfer_started = 1;
24249 +                       return;
24250 +               } else {
24251 +                       hctsiz.b.dopng = 1;
24252 +               }
24253 +       }
24254 +
24255 +       if (hc->do_split) {
24256 +               num_packets = 1;
24257 +
24258 +               if (hc->complete_split && !hc->ep_is_in) {
24259 +                       /* For CSPLIT OUT Transfer, set the size to 0 so the
24260 +                        * core doesn't expect any data written to the FIFO */
24261 +                       hc->xfer_len = 0;
24262 +               } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
24263 +                       hc->xfer_len = hc->max_packet;
24264 +               } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
24265 +                       hc->xfer_len = 188;
24266 +               }
24267 +
24268 +               hctsiz.b.xfersize = hc->xfer_len;
24269 +       } else {
24270 +               /*
24271 +                * Ensure that the transfer length and packet count will fit
24272 +                * in the widths allocated for them in the HCTSIZn register.
24273 +                */
24274 +               if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24275 +                   hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24276 +                       /*
24277 +                        * Make sure the transfer size is no larger than one
24278 +                        * (micro)frame's worth of data. (A check was done
24279 +                        * when the periodic transfer was accepted to ensure
24280 +                        * that a (micro)frame's worth of data can be
24281 +                        * programmed into a channel.)
24282 +                        */
24283 +                       uint32_t max_periodic_len =
24284 +                           hc->multi_count * hc->max_packet;
24285 +                       if (hc->xfer_len > max_periodic_len) {
24286 +                               hc->xfer_len = max_periodic_len;
24287 +                       } else {
24288 +                       }
24289 +               } else if (hc->xfer_len > max_hc_xfer_size) {
24290 +                       /* Make sure that xfer_len is a multiple of max packet size. */
24291 +                       hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
24292 +               }
24293 +
24294 +               if (hc->xfer_len > 0) {
24295 +                       num_packets =
24296 +                           (hc->xfer_len + hc->max_packet -
24297 +                            1) / hc->max_packet;
24298 +                       if (num_packets > max_hc_pkt_count) {
24299 +                               num_packets = max_hc_pkt_count;
24300 +                               hc->xfer_len = num_packets * hc->max_packet;
24301 +                       }
24302 +               } else {
24303 +                       /* Need 1 packet for transfer length of 0. */
24304 +                       num_packets = 1;
24305 +               }
24306 +
24307 +               if (hc->ep_is_in) {
24308 +                       /* Always program an integral # of max packets for IN transfers. */
24309 +                       hc->xfer_len = num_packets * hc->max_packet;
24310 +               }
24311 +
24312 +               if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24313 +                   hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24314 +                       /*
24315 +                        * Make sure that the multi_count field matches the
24316 +                        * actual transfer length.
24317 +                        */
24318 +                       hc->multi_count = num_packets;
24319 +               }
24320 +
24321 +               if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
24322 +                       set_pid_isoc(hc);
24323 +
24324 +               hctsiz.b.xfersize = hc->xfer_len;
24325 +       }
24326 +
24327 +       hc->start_pkt_count = num_packets;
24328 +       hctsiz.b.pktcnt = num_packets;
24329 +       hctsiz.b.pid = hc->data_pid_start;
24330 +       DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24331 +
24332 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24333 +       DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
24334 +       DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
24335 +       DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
24336 +
24337 +       if (core_if->dma_enable) {
24338 +               dwc_dma_t dma_addr;
24339 +               if (hc->align_buff) {
24340 +                       dma_addr = hc->align_buff;
24341 +               } else {
24342 +                       dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
24343 +               }
24344 +               DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
24345 +       }
24346 +
24347 +       /* Start the split */
24348 +       if (hc->do_split) {
24349 +               hcsplt_data_t hcsplt;
24350 +               hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
24351 +               hcsplt.b.spltena = 1;
24352 +               DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
24353 +       }
24354 +
24355 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24356 +       hcchar.b.multicnt = hc->multi_count;
24357 +       hc_set_even_odd_frame(core_if, hc, &hcchar);
24358 +#ifdef DEBUG
24359 +       core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
24360 +       if (hcchar.b.chdis) {
24361 +               DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
24362 +                        __func__, hc->hc_num, hcchar.d32);
24363 +       }
24364 +#endif
24365 +
24366 +       /* Set host channel enable after all other setup is complete. */
24367 +       hcchar.b.chen = 1;
24368 +       hcchar.b.chdis = 0;
24369 +       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24370 +
24371 +       hc->xfer_started = 1;
24372 +       hc->requests++;
24373 +
24374 +       if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
24375 +               /* Load OUT packet into the appropriate Tx FIFO. */
24376 +               dwc_otg_hc_write_packet(core_if, hc);
24377 +       }
24378 +#ifdef DEBUG
24379 +       if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
24380 +                DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n",
24381 +                            hc->hc_num, core_if);//GRAYG
24382 +               core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
24383 +               core_if->hc_xfer_info[hc->hc_num].hc = hc;
24384 +
24385 +               /* Start a timer for this transfer. */
24386 +               DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
24387 +       }
24388 +#endif
24389 +}
24390 +
24391 +/**
24392 + * This function does the setup for a data transfer for a host channel
24393 + * and starts the transfer in Descriptor DMA mode.
24394 + *
24395 + * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
24396 + * Sets PID and NTD values. For periodic transfers
24397 + * initializes SCHED_INFO field with micro-frame bitmap.
24398 + *
24399 + * Initializes HCDMA register with descriptor list address and CTD value
24400 + * then starts the transfer via enabling the channel.
24401 + *
24402 + * @param core_if Programming view of DWC_otg controller.
24403 + * @param hc Information needed to initialize the host channel.
24404 + */
24405 +void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24406 +{
24407 +       dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24408 +       hcchar_data_t hcchar;
24409 +       hctsiz_data_t hctsiz;
24410 +       hcdma_data_t hcdma;
24411 +
24412 +       hctsiz.d32 = 0;
24413 +
24414 +       if (hc->do_ping)
24415 +               hctsiz.b_ddma.dopng = 1;
24416 +
24417 +       if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
24418 +               set_pid_isoc(hc);
24419 +
24420 +       /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
24421 +       hctsiz.b_ddma.pid = hc->data_pid_start;
24422 +       hctsiz.b_ddma.ntd = hc->ntd - 1;        /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
24423 +       hctsiz.b_ddma.schinfo = hc->schinfo;    /* Non-zero only for high-speed interrupt endpoints */
24424 +
24425 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24426 +       DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
24427 +       DWC_DEBUGPL(DBG_HCDV, "  NTD: %d\n", hctsiz.b_ddma.ntd);
24428 +
24429 +       DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24430 +
24431 +       hcdma.d32 = 0;
24432 +       hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
24433 +
24434 +       /* Always start from first descriptor. */
24435 +       hcdma.b.ctd = 0;
24436 +       DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
24437 +
24438 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24439 +       hcchar.b.multicnt = hc->multi_count;
24440 +
24441 +#ifdef DEBUG
24442 +       core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
24443 +       if (hcchar.b.chdis) {
24444 +               DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
24445 +                        __func__, hc->hc_num, hcchar.d32);
24446 +       }
24447 +#endif
24448 +
24449 +       /* Set host channel enable after all other setup is complete. */
24450 +       hcchar.b.chen = 1;
24451 +       hcchar.b.chdis = 0;
24452 +
24453 +       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24454 +
24455 +       hc->xfer_started = 1;
24456 +       hc->requests++;
24457 +
24458 +#ifdef DEBUG
24459 +       if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
24460 +           && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
24461 +                DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n",
24462 +                            hc->hc_num, core_if);//GRAYG
24463 +               core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
24464 +               core_if->hc_xfer_info[hc->hc_num].hc = hc;
24465 +               /* Start a timer for this transfer. */
24466 +               DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
24467 +       }
24468 +#endif
24469 +
24470 +}
24471 +
24472 +/**
24473 + * This function continues a data transfer that was started by previous call
24474 + * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
24475 + * sufficient space in the request queue and Tx Data FIFO. This function
24476 + * should only be called in Slave mode. In DMA mode, the controller acts
24477 + * autonomously to complete transfers programmed to a host channel.
24478 + *
24479 + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
24480 + * if there is any data remaining to be queued. For an IN transfer, another
24481 + * data packet is always requested. For the SETUP phase of a control transfer,
24482 + * this function does nothing.
24483 + *
24484 + * @return 1 if a new request is queued, 0 if no more requests are required
24485 + * for this transfer.
24486 + */
24487 +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24488 +{
24489 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24490 +
24491 +       if (hc->do_split) {
24492 +               /* SPLITs always queue just once per channel */
24493 +               return 0;
24494 +       } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
24495 +               /* SETUPs are queued only once since they can't be NAKed. */
24496 +               return 0;
24497 +       } else if (hc->ep_is_in) {
24498 +               /*
24499 +                * Always queue another request for other IN transfers. If
24500 +                * back-to-back INs are issued and NAKs are received for both,
24501 +                * the driver may still be processing the first NAK when the
24502 +                * second NAK is received. When the interrupt handler clears
24503 +                * the NAK interrupt for the first NAK, the second NAK will
24504 +                * not be seen. So we can't depend on the NAK interrupt
24505 +                * handler to requeue a NAKed request. Instead, IN requests
24506 +                * are issued each time this function is called. When the
24507 +                * transfer completes, the extra requests for the channel will
24508 +                * be flushed.
24509 +                */
24510 +               hcchar_data_t hcchar;
24511 +               dwc_otg_hc_regs_t *hc_regs =
24512 +                   core_if->host_if->hc_regs[hc->hc_num];
24513 +
24514 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24515 +               hc_set_even_odd_frame(core_if, hc, &hcchar);
24516 +               hcchar.b.chen = 1;
24517 +               hcchar.b.chdis = 0;
24518 +               DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n",
24519 +                           hcchar.d32);
24520 +               DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24521 +               hc->requests++;
24522 +               return 1;
24523 +       } else {
24524 +               /* OUT transfers. */
24525 +               if (hc->xfer_count < hc->xfer_len) {
24526 +                       if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
24527 +                           hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
24528 +                               hcchar_data_t hcchar;
24529 +                               dwc_otg_hc_regs_t *hc_regs;
24530 +                               hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24531 +                               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24532 +                               hc_set_even_odd_frame(core_if, hc, &hcchar);
24533 +                       }
24534 +
24535 +                       /* Load OUT packet into the appropriate Tx FIFO. */
24536 +                       dwc_otg_hc_write_packet(core_if, hc);
24537 +                       hc->requests++;
24538 +                       return 1;
24539 +               } else {
24540 +                       return 0;
24541 +               }
24542 +       }
24543 +}
24544 +
24545 +/**
24546 + * Starts a PING transfer. This function should only be called in Slave mode.
24547 + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
24548 + */
24549 +void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24550 +{
24551 +       hcchar_data_t hcchar;
24552 +       hctsiz_data_t hctsiz;
24553 +       dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
24554 +
24555 +       DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
24556 +
24557 +       hctsiz.d32 = 0;
24558 +       hctsiz.b.dopng = 1;
24559 +       hctsiz.b.pktcnt = 1;
24560 +       DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
24561 +
24562 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
24563 +       hcchar.b.chen = 1;
24564 +       hcchar.b.chdis = 0;
24565 +       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
24566 +}
24567 +
24568 +/*
24569 + * This function writes a packet into the Tx FIFO associated with the Host
24570 + * Channel. For a channel associated with a non-periodic EP, the non-periodic
24571 + * Tx FIFO is written. For a channel associated with a periodic EP, the
24572 + * periodic Tx FIFO is written. This function should only be called in Slave
24573 + * mode.
24574 + *
24575 + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
24576 + * then number of bytes written to the Tx FIFO.
24577 + */
24578 +void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
24579 +{
24580 +       uint32_t i;
24581 +       uint32_t remaining_count;
24582 +       uint32_t byte_count;
24583 +       uint32_t dword_count;
24584 +
24585 +       uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
24586 +       uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
24587 +
24588 +       remaining_count = hc->xfer_len - hc->xfer_count;
24589 +       if (remaining_count > hc->max_packet) {
24590 +               byte_count = hc->max_packet;
24591 +       } else {
24592 +               byte_count = remaining_count;
24593 +       }
24594 +
24595 +       dword_count = (byte_count + 3) / 4;
24596 +
24597 +       if ((((unsigned long)data_buff) & 0x3) == 0) {
24598 +               /* xfer_buff is DWORD aligned. */
24599 +               for (i = 0; i < dword_count; i++, data_buff++) {
24600 +                       DWC_WRITE_REG32(data_fifo, *data_buff);
24601 +               }
24602 +       } else {
24603 +               /* xfer_buff is not DWORD aligned. */
24604 +               for (i = 0; i < dword_count; i++, data_buff++) {
24605 +                       uint32_t data;
24606 +                       data =
24607 +                           (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
24608 +                            16 | data_buff[3] << 24);
24609 +                       DWC_WRITE_REG32(data_fifo, data);
24610 +               }
24611 +       }
24612 +
24613 +       hc->xfer_count += byte_count;
24614 +       hc->xfer_buff += byte_count;
24615 +}
24616 +
24617 +/**
24618 + * Gets the current USB frame number. This is the frame number from the last
24619 + * SOF packet.
24620 + */
24621 +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
24622 +{
24623 +       dsts_data_t dsts;
24624 +       dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
24625 +
24626 +       /* read current frame/microframe number from DSTS register */
24627 +       return dsts.b.soffn;
24628 +}
24629 +
24630 +/**
24631 + * Calculates and gets the frame Interval value of HFIR register according PHY
24632 + * type and speed.The application can modify a value of HFIR register only after
24633 + * the Port Enable bit of the Host Port Control and Status register
24634 + * (HPRT.PrtEnaPort) has been set.
24635 +*/
24636 +
24637 +uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
24638 +{
24639 +       gusbcfg_data_t usbcfg;
24640 +       hwcfg2_data_t hwcfg2;
24641 +       hprt0_data_t hprt0;
24642 +       int clock = 60;         // default value
24643 +       usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
24644 +       hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
24645 +       hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
24646 +       if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
24647 +               clock = 60;
24648 +       if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
24649 +               clock = 48;
24650 +       if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24651 +           !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
24652 +               clock = 30;
24653 +       if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24654 +           !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
24655 +               clock = 60;
24656 +       if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
24657 +           !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
24658 +               clock = 48;
24659 +       if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
24660 +               clock = 48;
24661 +       if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
24662 +               clock = 48;
24663 +       if (hprt0.b.prtspd == 0)
24664 +               /* High speed case */
24665 +               return 125 * clock;
24666 +       else
24667 +               /* FS/LS case */
24668 +               return 1000 * clock;
24669 +}
24670 +
24671 +/**
24672 + * This function reads a setup packet from the Rx FIFO into the destination
24673 + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
24674 + * Interrupt routine when a SETUP packet has been received in Slave mode.
24675 + *
24676 + * @param core_if Programming view of DWC_otg controller.
24677 + * @param dest Destination buffer for packet data.
24678 + */
24679 +void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
24680 +{
24681 +       device_grxsts_data_t status;
24682 +       /* Get the 8 bytes of a setup transaction data */
24683 +
24684 +       /* Pop 2 DWORDS off the receive data FIFO into memory */
24685 +       dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
24686 +       dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
24687 +       if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
24688 +               status.d32 =
24689 +                   DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
24690 +               DWC_DEBUGPL(DBG_ANY,
24691 +                           "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
24692 +                           status.b.epnum, status.b.bcnt, status.b.pktsts,
24693 +                           status.b.fn, status.b.fn);
24694 +       }
24695 +}
24696 +
24697 +/**
24698 + * This function enables EP0 OUT to receive SETUP packets and configures EP0
24699 + * IN for transmitting packets. It is normally called when the
24700 + * "Enumeration Done" interrupt occurs.
24701 + *
24702 + * @param core_if Programming view of DWC_otg controller.
24703 + * @param ep The EP0 data.
24704 + */
24705 +void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24706 +{
24707 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
24708 +       dsts_data_t dsts;
24709 +       depctl_data_t diepctl;
24710 +       depctl_data_t doepctl;
24711 +       dctl_data_t dctl = {.d32 = 0 };
24712 +
24713 +       ep->stp_rollover = 0;
24714 +       /* Read the Device Status and Endpoint 0 Control registers */
24715 +       dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
24716 +       diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
24717 +       doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
24718 +
24719 +       /* Set the MPS of the IN EP based on the enumeration speed */
24720 +       switch (dsts.b.enumspd) {
24721 +       case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
24722 +       case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
24723 +       case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
24724 +               diepctl.b.mps = DWC_DEP0CTL_MPS_64;
24725 +               break;
24726 +       case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
24727 +               diepctl.b.mps = DWC_DEP0CTL_MPS_8;
24728 +               break;
24729 +       }
24730 +
24731 +       DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
24732 +
24733 +       /* Enable OUT EP for receive */
24734 +       if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
24735 +       doepctl.b.epena = 1;
24736 +       DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
24737 +       }
24738 +#ifdef VERBOSE
24739 +       DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
24740 +                   DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
24741 +       DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
24742 +                   DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
24743 +#endif
24744 +       dctl.b.cgnpinnak = 1;
24745 +
24746 +       DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
24747 +       DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
24748 +                   DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
24749 +
24750 +}
24751 +
24752 +/**
24753 + * This function activates an EP.  The Device EP control register for
24754 + * the EP is configured as defined in the ep structure. Note: This
24755 + * function is not used for EP0.
24756 + *
24757 + * @param core_if Programming view of DWC_otg controller.
24758 + * @param ep The EP to activate.
24759 + */
24760 +void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24761 +{
24762 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
24763 +       depctl_data_t depctl;
24764 +       volatile uint32_t *addr;
24765 +       daint_data_t daintmsk = {.d32 = 0 };
24766 +       dcfg_data_t dcfg;
24767 +       uint8_t i;
24768 +
24769 +       DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
24770 +                   (ep->is_in ? "IN" : "OUT"));
24771 +
24772 +#ifdef DWC_UTE_PER_IO
24773 +       ep->xiso_frame_num = 0xFFFFFFFF;
24774 +       ep->xiso_active_xfers = 0;
24775 +       ep->xiso_queued_xfers = 0;
24776 +#endif
24777 +       /* Read DEPCTLn register */
24778 +       if (ep->is_in == 1) {
24779 +               addr = &dev_if->in_ep_regs[ep->num]->diepctl;
24780 +               daintmsk.ep.in = 1 << ep->num;
24781 +       } else {
24782 +               addr = &dev_if->out_ep_regs[ep->num]->doepctl;
24783 +               daintmsk.ep.out = 1 << ep->num;
24784 +       }
24785 +
24786 +       /* If the EP is already active don't change the EP Control
24787 +        * register. */
24788 +       depctl.d32 = DWC_READ_REG32(addr);
24789 +       if (!depctl.b.usbactep) {
24790 +               depctl.b.mps = ep->maxpacket;
24791 +               depctl.b.eptype = ep->type;
24792 +               depctl.b.txfnum = ep->tx_fifo_num;
24793 +
24794 +               if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
24795 +                       depctl.b.setd0pid = 1;  // ???
24796 +               } else {
24797 +                       depctl.b.setd0pid = 1;
24798 +               }
24799 +               depctl.b.usbactep = 1;
24800 +
24801 +               /* Update nextep_seq array and EPMSCNT in DCFG*/
24802 +               if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {       // NP IN EP
24803 +                       for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
24804 +                               if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
24805 +                               break;
24806 +                       }
24807 +                       core_if->nextep_seq[i] = ep->num;
24808 +                       core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
24809 +                       depctl.b.nextep = core_if->nextep_seq[ep->num];
24810 +                       dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
24811 +                       dcfg.b.epmscnt++;
24812 +                       DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
24813 +
24814 +                       DWC_DEBUGPL(DBG_PCDV,
24815 +                                   "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
24816 +                               __func__, core_if->first_in_nextep_seq);
24817 +                       for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
24818 +                               DWC_DEBUGPL(DBG_PCDV, "%2d\n",
24819 +                                           core_if->nextep_seq[i]);
24820 +                       }
24821 +
24822 +               }
24823 +
24824 +
24825 +               DWC_WRITE_REG32(addr, depctl.d32);
24826 +               DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
24827 +       }
24828 +
24829 +       /* Enable the Interrupt for this EP */
24830 +       if (core_if->multiproc_int_enable) {
24831 +               if (ep->is_in == 1) {
24832 +                       diepmsk_data_t diepmsk = {.d32 = 0 };
24833 +                       diepmsk.b.xfercompl = 1;
24834 +                       diepmsk.b.timeout = 1;
24835 +                       diepmsk.b.epdisabled = 1;
24836 +                       diepmsk.b.ahberr = 1;
24837 +                       diepmsk.b.intknepmis = 1;
24838 +                       if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
24839 +                               diepmsk.b.intknepmis = 0;
24840 +                       diepmsk.b.txfifoundrn = 1;      //?????
24841 +                       if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
24842 +                               diepmsk.b.nak = 1;
24843 +                       }
24844 +
24845 +
24846 +
24847 +/*
24848 +                       if (core_if->dma_desc_enable) {
24849 +                               diepmsk.b.bna = 1;
24850 +                       }
24851 +*/
24852 +/*
24853 +                       if (core_if->dma_enable) {
24854 +                               doepmsk.b.nak = 1;
24855 +                       }
24856 +*/
24857 +                       DWC_WRITE_REG32(&dev_if->dev_global_regs->
24858 +                                       diepeachintmsk[ep->num], diepmsk.d32);
24859 +
24860 +               } else {
24861 +                       doepmsk_data_t doepmsk = {.d32 = 0 };
24862 +                       doepmsk.b.xfercompl = 1;
24863 +                       doepmsk.b.ahberr = 1;
24864 +                       doepmsk.b.epdisabled = 1;
24865 +                       if (ep->type == DWC_OTG_EP_TYPE_ISOC)
24866 +                               doepmsk.b.outtknepdis = 1;
24867 +
24868 +/*
24869 +
24870 +                       if (core_if->dma_desc_enable) {
24871 +                               doepmsk.b.bna = 1;
24872 +                       }
24873 +*/
24874 +/*
24875 +                       doepmsk.b.babble = 1;
24876 +                       doepmsk.b.nyet = 1;
24877 +                       doepmsk.b.nak = 1;
24878 +*/
24879 +                       DWC_WRITE_REG32(&dev_if->dev_global_regs->
24880 +                                       doepeachintmsk[ep->num], doepmsk.d32);
24881 +               }
24882 +               DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
24883 +                                0, daintmsk.d32);
24884 +       } else {
24885 +               if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
24886 +                       if (ep->is_in) {
24887 +                               diepmsk_data_t diepmsk = {.d32 = 0 };
24888 +                               diepmsk.b.nak = 1;
24889 +                               DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
24890 +                       } else {
24891 +                               doepmsk_data_t doepmsk = {.d32 = 0 };
24892 +                               doepmsk.b.outtknepdis = 1;
24893 +                               DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
24894 +                       }
24895 +               }
24896 +               DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
24897 +                                0, daintmsk.d32);
24898 +       }
24899 +
24900 +       DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
24901 +                   DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
24902 +
24903 +       ep->stall_clear_flag = 0;
24904 +
24905 +       return;
24906 +}
24907 +
24908 +/**
24909 + * This function deactivates an EP. This is done by clearing the USB Active
24910 + * EP bit in the Device EP control register. Note: This function is not used
24911 + * for EP0. EP0 cannot be deactivated.
24912 + *
24913 + * @param core_if Programming view of DWC_otg controller.
24914 + * @param ep The EP to deactivate.
24915 + */
24916 +void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
24917 +{
24918 +       depctl_data_t depctl = {.d32 = 0 };
24919 +       volatile uint32_t *addr;
24920 +       daint_data_t daintmsk = {.d32 = 0 };
24921 +       dcfg_data_t dcfg;
24922 +       uint8_t i = 0;
24923 +
24924 +#ifdef DWC_UTE_PER_IO
24925 +       ep->xiso_frame_num = 0xFFFFFFFF;
24926 +       ep->xiso_active_xfers = 0;
24927 +       ep->xiso_queued_xfers = 0;
24928 +#endif
24929 +
24930 +       /* Read DEPCTLn register */
24931 +       if (ep->is_in == 1) {
24932 +               addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
24933 +               daintmsk.ep.in = 1 << ep->num;
24934 +       } else {
24935 +               addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
24936 +               daintmsk.ep.out = 1 << ep->num;
24937 +       }
24938 +
24939 +       depctl.d32 = DWC_READ_REG32(addr);
24940 +
24941 +       depctl.b.usbactep = 0;
24942 +
24943 +       /* Update nextep_seq array and EPMSCNT in DCFG*/
24944 +       if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
24945 +               for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
24946 +                       if (core_if->nextep_seq[i] == ep->num)
24947 +                       break;
24948 +               }
24949 +               core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
24950 +               if (core_if->first_in_nextep_seq == ep->num)
24951 +                       core_if->first_in_nextep_seq = i;
24952 +               core_if->nextep_seq[ep->num] = 0xff;
24953 +               depctl.b.nextep = 0;
24954 +               dcfg.d32 =
24955 +                   DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
24956 +               dcfg.b.epmscnt--;
24957 +               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
24958 +                               dcfg.d32);
24959 +
24960 +               DWC_DEBUGPL(DBG_PCDV,
24961 +                           "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
24962 +                               __func__, core_if->first_in_nextep_seq);
24963 +                       for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
24964 +                               DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
24965 +                       }
24966 +       }
24967 +
24968 +       if (ep->is_in == 1)
24969 +               depctl.b.txfnum = 0;
24970 +
24971 +       if (core_if->dma_desc_enable)
24972 +               depctl.b.epdis = 1;
24973 +
24974 +       DWC_WRITE_REG32(addr, depctl.d32);
24975 +       depctl.d32 = DWC_READ_REG32(addr);
24976 +       if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
24977 +           && depctl.b.epena) {
24978 +               depctl_data_t depctl = {.d32 = 0};
24979 +               if (ep->is_in) {
24980 +                       diepint_data_t diepint = {.d32 = 0};
24981 +
24982 +                       depctl.b.snak = 1;
24983 +                       DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
24984 +                                       diepctl, depctl.d32);
24985 +                       do {
24986 +                               dwc_udelay(10);
24987 +                               diepint.d32 =
24988 +                                   DWC_READ_REG32(&core_if->
24989 +                                                  dev_if->in_ep_regs[ep->num]->
24990 +                                                  diepint);
24991 +                       } while (!diepint.b.inepnakeff);
24992 +                       diepint.b.inepnakeff = 1;
24993 +                       DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
24994 +                                       diepint, diepint.d32);
24995 +                       depctl.d32 = 0;
24996 +                       depctl.b.epdis = 1;
24997 +                       DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
24998 +                                       diepctl, depctl.d32);
24999 +                       do {
25000 +                               dwc_udelay(10);
25001 +                               diepint.d32 =
25002 +                                   DWC_READ_REG32(&core_if->
25003 +                                                  dev_if->in_ep_regs[ep->num]->
25004 +                                                  diepint);
25005 +                       } while (!diepint.b.epdisabled);
25006 +                       diepint.b.epdisabled = 1;
25007 +                       DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
25008 +                                       diepint, diepint.d32);
25009 +               } else {
25010 +                       dctl_data_t dctl = {.d32 = 0};
25011 +                       gintmsk_data_t gintsts = {.d32 = 0};
25012 +                       doepint_data_t doepint = {.d32 = 0};
25013 +                       dctl.b.sgoutnak = 1;
25014 +                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
25015 +                                        dctl, 0, dctl.d32);
25016 +                       do {
25017 +                               dwc_udelay(10);
25018 +                               gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
25019 +                       } while (!gintsts.b.goutnakeff);
25020 +                       gintsts.d32 = 0;
25021 +                       gintsts.b.goutnakeff = 1;
25022 +                       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
25023 +
25024 +                       depctl.d32 = 0;
25025 +                       depctl.b.epdis = 1;
25026 +                       depctl.b.snak = 1;
25027 +                       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
25028 +                       do
25029 +                       {
25030 +                               dwc_udelay(10);
25031 +                               doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
25032 +                                                                                       out_ep_regs[ep->num]->doepint);
25033 +                       } while (!doepint.b.epdisabled);
25034 +
25035 +                       doepint.b.epdisabled = 1;
25036 +                       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
25037 +
25038 +                       dctl.d32 = 0;
25039 +                       dctl.b.cgoutnak = 1;
25040 +                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
25041 +               }
25042 +       }
25043 +
25044 +       /* Disable the Interrupt for this EP */
25045 +       if (core_if->multiproc_int_enable) {
25046 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
25047 +                                daintmsk.d32, 0);
25048 +
25049 +               if (ep->is_in == 1) {
25050 +                       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
25051 +                                       diepeachintmsk[ep->num], 0);
25052 +               } else {
25053 +                       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
25054 +                                       doepeachintmsk[ep->num], 0);
25055 +               }
25056 +       } else {
25057 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
25058 +                                daintmsk.d32, 0);
25059 +       }
25060 +
25061 +}
25062 +
25063 +/**
25064 + * This function initializes dma descriptor chain.
25065 + *
25066 + * @param core_if Programming view of DWC_otg controller.
25067 + * @param ep The EP to start the transfer on.
25068 + */
25069 +static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25070 +{
25071 +       dwc_otg_dev_dma_desc_t *dma_desc;
25072 +       uint32_t offset;
25073 +       uint32_t xfer_est;
25074 +       int i;
25075 +       unsigned maxxfer_local, total_len;
25076 +
25077 +       if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
25078 +                                       (ep->maxpacket%4)) {
25079 +               maxxfer_local = ep->maxpacket;
25080 +               total_len = ep->xfer_len;
25081 +       } else {
25082 +               maxxfer_local = ep->maxxfer;
25083 +               total_len = ep->total_len;
25084 +       }
25085 +
25086 +       ep->desc_cnt = (total_len / maxxfer_local) +
25087 +            ((total_len % maxxfer_local) ? 1 : 0);
25088 +
25089 +       if (!ep->desc_cnt)
25090 +               ep->desc_cnt = 1;
25091 +
25092 +       if (ep->desc_cnt > MAX_DMA_DESC_CNT)
25093 +               ep->desc_cnt = MAX_DMA_DESC_CNT;
25094 +
25095 +       dma_desc = ep->desc_addr;
25096 +       if (maxxfer_local == ep->maxpacket) {
25097 +               if ((total_len % maxxfer_local) &&
25098 +                               (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
25099 +                       xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
25100 +                                       (total_len % maxxfer_local);
25101 +               } else
25102 +                       xfer_est = ep->desc_cnt * maxxfer_local;
25103 +       } else
25104 +               xfer_est = total_len;
25105 +       offset = 0;
25106 +       for (i = 0; i < ep->desc_cnt; ++i) {
25107 +               /** DMA Descriptor Setup */
25108 +               if (xfer_est > maxxfer_local) {
25109 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
25110 +                       dma_desc->status.b.l = 0;
25111 +                       dma_desc->status.b.ioc = 0;
25112 +                       dma_desc->status.b.sp = 0;
25113 +                       dma_desc->status.b.bytes = maxxfer_local;
25114 +                       dma_desc->buf = ep->dma_addr + offset;
25115 +                       dma_desc->status.b.sts = 0;
25116 +                       dma_desc->status.b.bs = BS_HOST_READY;
25117 +
25118 +                       xfer_est -= maxxfer_local;
25119 +                       offset += maxxfer_local;
25120 +               } else {
25121 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
25122 +                       dma_desc->status.b.l = 1;
25123 +                       dma_desc->status.b.ioc = 1;
25124 +                       if (ep->is_in) {
25125 +                               dma_desc->status.b.sp =
25126 +                                   (xfer_est %
25127 +                                    ep->maxpacket) ? 1 : ((ep->
25128 +                                                           sent_zlp) ? 1 : 0);
25129 +                               dma_desc->status.b.bytes = xfer_est;
25130 +                       } else {
25131 +                               if (maxxfer_local == ep->maxpacket)
25132 +                                       dma_desc->status.b.bytes = xfer_est;
25133 +                               else
25134 +                                       dma_desc->status.b.bytes =
25135 +                                               xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
25136 +                       }
25137 +
25138 +                       dma_desc->buf = ep->dma_addr + offset;
25139 +                       dma_desc->status.b.sts = 0;
25140 +                       dma_desc->status.b.bs = BS_HOST_READY;
25141 +               }
25142 +               dma_desc++;
25143 +       }
25144 +}
25145 +/**
25146 + * This function is called when to write ISOC data into appropriate dedicated
25147 + * periodic FIFO.
25148 + */
25149 +static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
25150 +{
25151 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
25152 +       dwc_otg_dev_in_ep_regs_t *ep_regs;
25153 +       dtxfsts_data_t txstatus = {.d32 = 0 };
25154 +       uint32_t len = 0;
25155 +       int epnum = dwc_ep->num;
25156 +       int dwords;
25157 +
25158 +       DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
25159 +
25160 +       ep_regs = core_if->dev_if->in_ep_regs[epnum];
25161 +
25162 +       len = dwc_ep->xfer_len - dwc_ep->xfer_count;
25163 +
25164 +       if (len > dwc_ep->maxpacket) {
25165 +               len = dwc_ep->maxpacket;
25166 +       }
25167 +
25168 +       dwords = (len + 3) / 4;
25169 +
25170 +       /* While there is space in the queue and space in the FIFO and
25171 +        * More data to tranfer, Write packets to the Tx FIFO */
25172 +       txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
25173 +       DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
25174 +
25175 +       while (txstatus.b.txfspcavail > dwords &&
25176 +              dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
25177 +               /* Write the FIFO */
25178 +               dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
25179 +
25180 +               len = dwc_ep->xfer_len - dwc_ep->xfer_count;
25181 +               if (len > dwc_ep->maxpacket) {
25182 +                       len = dwc_ep->maxpacket;
25183 +               }
25184 +
25185 +               dwords = (len + 3) / 4;
25186 +               txstatus.d32 =
25187 +                   DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
25188 +               DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
25189 +                           txstatus.d32);
25190 +       }
25191 +
25192 +       DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
25193 +                   DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
25194 +
25195 +       return 1;
25196 +}
25197 +/**
25198 + * This function does the setup for a data transfer for an EP and
25199 + * starts the transfer. For an IN transfer, the packets will be
25200 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
25201 + * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
25202 + *
25203 + * @param core_if Programming view of DWC_otg controller.
25204 + * @param ep The EP to start the transfer on.
25205 + */
25206 +
25207 +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25208 +{
25209 +       depctl_data_t depctl;
25210 +       deptsiz_data_t deptsiz;
25211 +       gintmsk_data_t intr_mask = {.d32 = 0 };
25212 +
25213 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
25214 +       DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
25215 +                   "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
25216 +                   ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
25217 +                   ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
25218 +                   ep->total_len);
25219 +       /* IN endpoint */
25220 +       if (ep->is_in == 1) {
25221 +               dwc_otg_dev_in_ep_regs_t *in_regs =
25222 +                   core_if->dev_if->in_ep_regs[ep->num];
25223 +
25224 +               gnptxsts_data_t gtxstatus;
25225 +
25226 +               gtxstatus.d32 =
25227 +                   DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25228 +
25229 +               if (core_if->en_multiple_tx_fifo == 0
25230 +                   && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
25231 +#ifdef DEBUG
25232 +                       DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
25233 +#endif
25234 +                       return;
25235 +               }
25236 +
25237 +               depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
25238 +               deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
25239 +
25240 +               if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
25241 +                       ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
25242 +                               ep->maxxfer : (ep->total_len - ep->xfer_len);
25243 +               else
25244 +                       ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
25245 +                                MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
25246 +
25247 +
25248 +               /* Zero Length Packet? */
25249 +               if ((ep->xfer_len - ep->xfer_count) == 0) {
25250 +                       deptsiz.b.xfersize = 0;
25251 +                       deptsiz.b.pktcnt = 1;
25252 +               } else {
25253 +                       /* Program the transfer size and packet count
25254 +                        *      as follows: xfersize = N * maxpacket +
25255 +                        *      short_packet pktcnt = N + (short_packet
25256 +                        *      exist ? 1 : 0)
25257 +                        */
25258 +                       deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
25259 +                       deptsiz.b.pktcnt =
25260 +                           (ep->xfer_len - ep->xfer_count - 1 +
25261 +                            ep->maxpacket) / ep->maxpacket;
25262 +                       if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
25263 +                               deptsiz.b.pktcnt = MAX_PKT_CNT;
25264 +                               deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
25265 +                       }
25266 +                       if (ep->type == DWC_OTG_EP_TYPE_ISOC)
25267 +                               deptsiz.b.mc = deptsiz.b.pktcnt;
25268 +               }
25269 +
25270 +               /* Write the DMA register */
25271 +               if (core_if->dma_enable) {
25272 +                       if (core_if->dma_desc_enable == 0) {
25273 +                               if (ep->type != DWC_OTG_EP_TYPE_ISOC)
25274 +                                       deptsiz.b.mc = 1;
25275 +                               DWC_WRITE_REG32(&in_regs->dieptsiz,
25276 +                                               deptsiz.d32);
25277 +                               DWC_WRITE_REG32(&(in_regs->diepdma),
25278 +                                               (uint32_t) ep->dma_addr);
25279 +                       } else {
25280 +#ifdef DWC_UTE_CFI
25281 +                               /* The descriptor chain should be already initialized by now */
25282 +                               if (ep->buff_mode != BM_STANDARD) {
25283 +                                       DWC_WRITE_REG32(&in_regs->diepdma,
25284 +                                                       ep->descs_dma_addr);
25285 +                               } else {
25286 +#endif
25287 +                                       init_dma_desc_chain(core_if, ep);
25288 +                               /** DIEPDMAn Register write */
25289 +                                       DWC_WRITE_REG32(&in_regs->diepdma,
25290 +                                                       ep->dma_desc_addr);
25291 +#ifdef DWC_UTE_CFI
25292 +                               }
25293 +#endif
25294 +                       }
25295 +               } else {
25296 +                       DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25297 +                       if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
25298 +                               /**
25299 +                                * Enable the Non-Periodic Tx FIFO empty interrupt,
25300 +                                * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
25301 +                                * the data will be written into the fifo by the ISR.
25302 +                                */
25303 +                               if (core_if->en_multiple_tx_fifo == 0) {
25304 +                                       intr_mask.b.nptxfempty = 1;
25305 +                                       DWC_MODIFY_REG32
25306 +                                           (&core_if->core_global_regs->gintmsk,
25307 +                                            intr_mask.d32, intr_mask.d32);
25308 +                               } else {
25309 +                                       /* Enable the Tx FIFO Empty Interrupt for this EP */
25310 +                                       if (ep->xfer_len > 0) {
25311 +                                               uint32_t fifoemptymsk = 0;
25312 +                                               fifoemptymsk = 1 << ep->num;
25313 +                                               DWC_MODIFY_REG32
25314 +                                                   (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25315 +                                                    0, fifoemptymsk);
25316 +
25317 +                                       }
25318 +                               }
25319 +                       }  else {
25320 +                                        write_isoc_tx_fifo(core_if, ep);
25321 +                       }
25322 +               }
25323 +               if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25324 +                       depctl.b.nextep = core_if->nextep_seq[ep->num];
25325 +
25326 +               if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25327 +                       dsts_data_t dsts = {.d32 = 0};
25328 +                       if (ep->bInterval == 1) {
25329 +                               dsts.d32 =
25330 +                                   DWC_READ_REG32(&core_if->dev_if->
25331 +                                                  dev_global_regs->dsts);
25332 +                               ep->frame_num = dsts.b.soffn + ep->bInterval;
25333 +                               if (ep->frame_num > 0x3FFF) {
25334 +                                       ep->frm_overrun = 1;
25335 +                                       ep->frame_num &= 0x3FFF;
25336 +                               } else
25337 +                                       ep->frm_overrun = 0;
25338 +                               if (ep->frame_num & 0x1) {
25339 +                                       depctl.b.setd1pid = 1;
25340 +                               } else {
25341 +                                       depctl.b.setd0pid = 1;
25342 +                               }
25343 +                       }
25344 +               }
25345 +               /* EP enable, IN data in FIFO */
25346 +               depctl.b.cnak = 1;
25347 +               depctl.b.epena = 1;
25348 +               DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25349 +
25350 +       } else {
25351 +               /* OUT endpoint */
25352 +               dwc_otg_dev_out_ep_regs_t *out_regs =
25353 +                   core_if->dev_if->out_ep_regs[ep->num];
25354 +
25355 +               depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
25356 +               deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
25357 +
25358 +               if (!core_if->dma_desc_enable) {
25359 +                       if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
25360 +                               ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
25361 +                               ep->maxxfer : (ep->total_len - ep->xfer_len);
25362 +                else
25363 +                                       ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
25364 +                                       - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
25365 +               }
25366 +
25367 +               /* Program the transfer size and packet count as follows:
25368 +                *
25369 +                *      pktcnt = N
25370 +                *      xfersize = N * maxpacket
25371 +                */
25372 +               if ((ep->xfer_len - ep->xfer_count) == 0) {
25373 +                       /* Zero Length Packet */
25374 +                       deptsiz.b.xfersize = ep->maxpacket;
25375 +                       deptsiz.b.pktcnt = 1;
25376 +               } else {
25377 +                       deptsiz.b.pktcnt =
25378 +                           (ep->xfer_len - ep->xfer_count +
25379 +                            (ep->maxpacket - 1)) / ep->maxpacket;
25380 +                       if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
25381 +                               deptsiz.b.pktcnt = MAX_PKT_CNT;
25382 +                       }
25383 +                       if (!core_if->dma_desc_enable) {
25384 +                               ep->xfer_len =
25385 +                                       deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
25386 +                       }
25387 +                       deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
25388 +               }
25389 +
25390 +               DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
25391 +                           ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
25392 +
25393 +               if (core_if->dma_enable) {
25394 +                       if (!core_if->dma_desc_enable) {
25395 +                               DWC_WRITE_REG32(&out_regs->doeptsiz,
25396 +                                               deptsiz.d32);
25397 +
25398 +                               DWC_WRITE_REG32(&(out_regs->doepdma),
25399 +                                               (uint32_t) ep->dma_addr);
25400 +                       } else {
25401 +#ifdef DWC_UTE_CFI
25402 +                               /* The descriptor chain should be already initialized by now */
25403 +                               if (ep->buff_mode != BM_STANDARD) {
25404 +                                       DWC_WRITE_REG32(&out_regs->doepdma,
25405 +                                                       ep->descs_dma_addr);
25406 +                               } else {
25407 +#endif
25408 +                                       /** This is used for interrupt out transfers*/
25409 +                                       if (!ep->xfer_len)
25410 +                                               ep->xfer_len = ep->total_len;
25411 +                                       init_dma_desc_chain(core_if, ep);
25412 +
25413 +                                       if (core_if->core_params->dev_out_nak) {
25414 +                                               if (ep->type == DWC_OTG_EP_TYPE_BULK) {
25415 +                                                       deptsiz.b.pktcnt = (ep->total_len +
25416 +                                                               (ep->maxpacket - 1)) / ep->maxpacket;
25417 +                                                       deptsiz.b.xfersize = ep->total_len;
25418 +                                                       /* Remember initial value of doeptsiz */
25419 +                                                       core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
25420 +                                                       DWC_WRITE_REG32(&out_regs->doeptsiz,
25421 +                                                               deptsiz.d32);
25422 +                                               }
25423 +                                       }
25424 +                               /** DOEPDMAn Register write */
25425 +                                       DWC_WRITE_REG32(&out_regs->doepdma,
25426 +                                                       ep->dma_desc_addr);
25427 +#ifdef DWC_UTE_CFI
25428 +                               }
25429 +#endif
25430 +                       }
25431 +               } else {
25432 +                       DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25433 +               }
25434 +
25435 +               if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
25436 +                       dsts_data_t dsts = {.d32 = 0};
25437 +                       if (ep->bInterval == 1) {
25438 +                               dsts.d32 =
25439 +                                   DWC_READ_REG32(&core_if->dev_if->
25440 +                                                  dev_global_regs->dsts);
25441 +                               ep->frame_num = dsts.b.soffn + ep->bInterval;
25442 +                               if (ep->frame_num > 0x3FFF) {
25443 +                                       ep->frm_overrun = 1;
25444 +                                       ep->frame_num &= 0x3FFF;
25445 +                               } else
25446 +                                       ep->frm_overrun = 0;
25447 +
25448 +                               if (ep->frame_num & 0x1) {
25449 +                                       depctl.b.setd1pid = 1;
25450 +                               } else {
25451 +                                       depctl.b.setd0pid = 1;
25452 +                               }
25453 +                       }
25454 +               }
25455 +
25456 +               /* EP enable */
25457 +               depctl.b.cnak = 1;
25458 +               depctl.b.epena = 1;
25459 +
25460 +               DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25461 +
25462 +               DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
25463 +                           DWC_READ_REG32(&out_regs->doepctl),
25464 +                           DWC_READ_REG32(&out_regs->doeptsiz));
25465 +               DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
25466 +                           DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
25467 +                                          daintmsk),
25468 +                           DWC_READ_REG32(&core_if->core_global_regs->
25469 +                                          gintmsk));
25470 +
25471 +               /* Timer is scheduling only for out bulk transfers for
25472 +                * "Device DDMA OUT NAK Enhancement" feature to inform user
25473 +                * about received data payload in case of timeout
25474 +                */
25475 +               if (core_if->core_params->dev_out_nak) {
25476 +                       if (ep->type == DWC_OTG_EP_TYPE_BULK) {
25477 +                               core_if->ep_xfer_info[ep->num].core_if = core_if;
25478 +                               core_if->ep_xfer_info[ep->num].ep = ep;
25479 +                               core_if->ep_xfer_info[ep->num].state = 1;
25480 +
25481 +                               /* Start a timer for this transfer. */
25482 +                               DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
25483 +                       }
25484 +               }
25485 +       }
25486 +}
25487 +
25488 +/**
25489 + * This function setup a zero length transfer in Buffer DMA and
25490 + * Slave modes for usb requests with zero field set
25491 + *
25492 + * @param core_if Programming view of DWC_otg controller.
25493 + * @param ep The EP to start the transfer on.
25494 + *
25495 + */
25496 +void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25497 +{
25498 +
25499 +       depctl_data_t depctl;
25500 +       deptsiz_data_t deptsiz;
25501 +       gintmsk_data_t intr_mask = {.d32 = 0 };
25502 +
25503 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
25504 +       DWC_PRINTF("zero length transfer is called\n");
25505 +
25506 +       /* IN endpoint */
25507 +       if (ep->is_in == 1) {
25508 +               dwc_otg_dev_in_ep_regs_t *in_regs =
25509 +                   core_if->dev_if->in_ep_regs[ep->num];
25510 +
25511 +               depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
25512 +               deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
25513 +
25514 +               deptsiz.b.xfersize = 0;
25515 +               deptsiz.b.pktcnt = 1;
25516 +
25517 +               /* Write the DMA register */
25518 +               if (core_if->dma_enable) {
25519 +                       if (core_if->dma_desc_enable == 0) {
25520 +                               deptsiz.b.mc = 1;
25521 +                               DWC_WRITE_REG32(&in_regs->dieptsiz,
25522 +                                               deptsiz.d32);
25523 +                               DWC_WRITE_REG32(&(in_regs->diepdma),
25524 +                                               (uint32_t) ep->dma_addr);
25525 +                       }
25526 +               } else {
25527 +                       DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25528 +                       /**
25529 +                        * Enable the Non-Periodic Tx FIFO empty interrupt,
25530 +                        * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
25531 +                        * the data will be written into the fifo by the ISR.
25532 +                        */
25533 +                       if (core_if->en_multiple_tx_fifo == 0) {
25534 +                               intr_mask.b.nptxfempty = 1;
25535 +                               DWC_MODIFY_REG32(&core_if->
25536 +                                                core_global_regs->gintmsk,
25537 +                                                intr_mask.d32, intr_mask.d32);
25538 +                       } else {
25539 +                               /* Enable the Tx FIFO Empty Interrupt for this EP */
25540 +                               if (ep->xfer_len > 0) {
25541 +                                       uint32_t fifoemptymsk = 0;
25542 +                                       fifoemptymsk = 1 << ep->num;
25543 +                                       DWC_MODIFY_REG32(&core_if->
25544 +                                                        dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25545 +                                                        0, fifoemptymsk);
25546 +                               }
25547 +                       }
25548 +               }
25549 +
25550 +               if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25551 +                       depctl.b.nextep = core_if->nextep_seq[ep->num];
25552 +               /* EP enable, IN data in FIFO */
25553 +               depctl.b.cnak = 1;
25554 +               depctl.b.epena = 1;
25555 +               DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25556 +
25557 +       } else {
25558 +               /* OUT endpoint */
25559 +               dwc_otg_dev_out_ep_regs_t *out_regs =
25560 +                   core_if->dev_if->out_ep_regs[ep->num];
25561 +
25562 +               depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
25563 +               deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
25564 +
25565 +               /* Zero Length Packet */
25566 +               deptsiz.b.xfersize = ep->maxpacket;
25567 +               deptsiz.b.pktcnt = 1;
25568 +
25569 +               if (core_if->dma_enable) {
25570 +                       if (!core_if->dma_desc_enable) {
25571 +                               DWC_WRITE_REG32(&out_regs->doeptsiz,
25572 +                                               deptsiz.d32);
25573 +
25574 +                               DWC_WRITE_REG32(&(out_regs->doepdma),
25575 +                                               (uint32_t) ep->dma_addr);
25576 +                       }
25577 +               } else {
25578 +                       DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25579 +               }
25580 +
25581 +               /* EP enable */
25582 +               depctl.b.cnak = 1;
25583 +               depctl.b.epena = 1;
25584 +
25585 +               DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25586 +
25587 +       }
25588 +}
25589 +
25590 +/**
25591 + * This function does the setup for a data transfer for EP0 and starts
25592 + * the transfer.  For an IN transfer, the packets will be loaded into
25593 + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
25594 + * unloaded from the Rx FIFO in the ISR.
25595 + *
25596 + * @param core_if Programming view of DWC_otg controller.
25597 + * @param ep The EP0 data.
25598 + */
25599 +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25600 +{
25601 +       depctl_data_t depctl;
25602 +       deptsiz0_data_t deptsiz;
25603 +       gintmsk_data_t intr_mask = {.d32 = 0 };
25604 +       dwc_otg_dev_dma_desc_t *dma_desc;
25605 +
25606 +       DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
25607 +                   "xfer_buff=%p start_xfer_buff=%p \n",
25608 +                   ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
25609 +                   ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
25610 +
25611 +       ep->total_len = ep->xfer_len;
25612 +
25613 +       /* IN endpoint */
25614 +       if (ep->is_in == 1) {
25615 +               dwc_otg_dev_in_ep_regs_t *in_regs =
25616 +                   core_if->dev_if->in_ep_regs[0];
25617 +
25618 +               gnptxsts_data_t gtxstatus;
25619 +
25620 +               if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
25621 +                       depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25622 +                       if (depctl.b.epena)
25623 +                               return;
25624 +               }
25625 +
25626 +               gtxstatus.d32 =
25627 +                   DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25628 +
25629 +               /* If dedicated FIFO every time flush fifo before enable ep*/
25630 +               if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
25631 +                       dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
25632 +
25633 +               if (core_if->en_multiple_tx_fifo == 0
25634 +                   && gtxstatus.b.nptxqspcavail == 0
25635 +                   && !core_if->dma_enable) {
25636 +#ifdef DEBUG
25637 +                       deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25638 +                       DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
25639 +                                   DWC_READ_REG32(&in_regs->diepctl));
25640 +                       DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
25641 +                                   deptsiz.d32,
25642 +                                   deptsiz.b.xfersize, deptsiz.b.pktcnt);
25643 +                       DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
25644 +                                  gtxstatus.d32);
25645 +#endif
25646 +                       return;
25647 +               }
25648 +
25649 +               depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25650 +               deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25651 +
25652 +               /* Zero Length Packet? */
25653 +               if (ep->xfer_len == 0) {
25654 +                       deptsiz.b.xfersize = 0;
25655 +                       deptsiz.b.pktcnt = 1;
25656 +               } else {
25657 +                       /* Program the transfer size and packet count
25658 +                        *      as follows: xfersize = N * maxpacket +
25659 +                        *      short_packet pktcnt = N + (short_packet
25660 +                        *      exist ? 1 : 0)
25661 +                        */
25662 +                       if (ep->xfer_len > ep->maxpacket) {
25663 +                               ep->xfer_len = ep->maxpacket;
25664 +                               deptsiz.b.xfersize = ep->maxpacket;
25665 +                       } else {
25666 +                               deptsiz.b.xfersize = ep->xfer_len;
25667 +                       }
25668 +                       deptsiz.b.pktcnt = 1;
25669 +
25670 +               }
25671 +               DWC_DEBUGPL(DBG_PCDV,
25672 +                           "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
25673 +                           ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
25674 +                           deptsiz.d32);
25675 +
25676 +               /* Write the DMA register */
25677 +               if (core_if->dma_enable) {
25678 +                       if (core_if->dma_desc_enable == 0) {
25679 +                               DWC_WRITE_REG32(&in_regs->dieptsiz,
25680 +                                               deptsiz.d32);
25681 +
25682 +                               DWC_WRITE_REG32(&(in_regs->diepdma),
25683 +                                               (uint32_t) ep->dma_addr);
25684 +                       } else {
25685 +                               dma_desc = core_if->dev_if->in_desc_addr;
25686 +
25687 +                               /** DMA Descriptor Setup */
25688 +                               dma_desc->status.b.bs = BS_HOST_BUSY;
25689 +                               dma_desc->status.b.l = 1;
25690 +                               dma_desc->status.b.ioc = 1;
25691 +                               dma_desc->status.b.sp =
25692 +                                   (ep->xfer_len == ep->maxpacket) ? 0 : 1;
25693 +                               dma_desc->status.b.bytes = ep->xfer_len;
25694 +                               dma_desc->buf = ep->dma_addr;
25695 +                               dma_desc->status.b.sts = 0;
25696 +                               dma_desc->status.b.bs = BS_HOST_READY;
25697 +
25698 +                               /** DIEPDMA0 Register write */
25699 +                               DWC_WRITE_REG32(&in_regs->diepdma,
25700 +                                               core_if->
25701 +                                               dev_if->dma_in_desc_addr);
25702 +                       }
25703 +               } else {
25704 +                       DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25705 +               }
25706 +
25707 +               if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25708 +                       depctl.b.nextep = core_if->nextep_seq[ep->num];
25709 +               /* EP enable, IN data in FIFO */
25710 +               depctl.b.cnak = 1;
25711 +               depctl.b.epena = 1;
25712 +               DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25713 +
25714 +               /**
25715 +                * Enable the Non-Periodic Tx FIFO empty interrupt, the
25716 +                * data will be written into the fifo by the ISR.
25717 +                */
25718 +               if (!core_if->dma_enable) {
25719 +                       if (core_if->en_multiple_tx_fifo == 0) {
25720 +                               intr_mask.b.nptxfempty = 1;
25721 +                               DWC_MODIFY_REG32(&core_if->
25722 +                                                core_global_regs->gintmsk,
25723 +                                                intr_mask.d32, intr_mask.d32);
25724 +                       } else {
25725 +                               /* Enable the Tx FIFO Empty Interrupt for this EP */
25726 +                               if (ep->xfer_len > 0) {
25727 +                                       uint32_t fifoemptymsk = 0;
25728 +                                       fifoemptymsk |= 1 << ep->num;
25729 +                                       DWC_MODIFY_REG32(&core_if->
25730 +                                                        dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25731 +                                                        0, fifoemptymsk);
25732 +                               }
25733 +                       }
25734 +               }
25735 +       } else {
25736 +               /* OUT endpoint */
25737 +               dwc_otg_dev_out_ep_regs_t *out_regs =
25738 +                   core_if->dev_if->out_ep_regs[0];
25739 +
25740 +               depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
25741 +               deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
25742 +
25743 +               /* Program the transfer size and packet count as follows:
25744 +                *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
25745 +                *      pktcnt = N                                                                                      */
25746 +               /* Zero Length Packet */
25747 +               deptsiz.b.xfersize = ep->maxpacket;
25748 +               deptsiz.b.pktcnt = 1;
25749 +               if (core_if->snpsid >= OTG_CORE_REV_3_00a)
25750 +                       deptsiz.b.supcnt = 3;
25751 +
25752 +               DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
25753 +                           ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
25754 +
25755 +               if (core_if->dma_enable) {
25756 +                       if (!core_if->dma_desc_enable) {
25757 +                               DWC_WRITE_REG32(&out_regs->doeptsiz,
25758 +                                               deptsiz.d32);
25759 +
25760 +                               DWC_WRITE_REG32(&(out_regs->doepdma),
25761 +                                               (uint32_t) ep->dma_addr);
25762 +                       } else {
25763 +                               dma_desc = core_if->dev_if->out_desc_addr;
25764 +
25765 +                               /** DMA Descriptor Setup */
25766 +                               dma_desc->status.b.bs = BS_HOST_BUSY;
25767 +                               if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
25768 +                                       dma_desc->status.b.mtrf = 0;
25769 +                                       dma_desc->status.b.sr = 0;
25770 +                               }
25771 +                               dma_desc->status.b.l = 1;
25772 +                               dma_desc->status.b.ioc = 1;
25773 +                               dma_desc->status.b.bytes = ep->maxpacket;
25774 +                               dma_desc->buf = ep->dma_addr;
25775 +                               dma_desc->status.b.sts = 0;
25776 +                               dma_desc->status.b.bs = BS_HOST_READY;
25777 +
25778 +                               /** DOEPDMA0 Register write */
25779 +                               DWC_WRITE_REG32(&out_regs->doepdma,
25780 +                                               core_if->dev_if->
25781 +                                               dma_out_desc_addr);
25782 +                       }
25783 +               } else {
25784 +                       DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25785 +               }
25786 +
25787 +               /* EP enable */
25788 +               depctl.b.cnak = 1;
25789 +               depctl.b.epena = 1;
25790 +               DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
25791 +       }
25792 +}
25793 +
25794 +/**
25795 + * This function continues control IN transfers started by
25796 + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
25797 + * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
25798 + * bit for the packet count.
25799 + *
25800 + * @param core_if Programming view of DWC_otg controller.
25801 + * @param ep The EP0 data.
25802 + */
25803 +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
25804 +{
25805 +       depctl_data_t depctl;
25806 +       deptsiz0_data_t deptsiz;
25807 +       gintmsk_data_t intr_mask = {.d32 = 0 };
25808 +       dwc_otg_dev_dma_desc_t *dma_desc;
25809 +
25810 +       if (ep->is_in == 1) {
25811 +               dwc_otg_dev_in_ep_regs_t *in_regs =
25812 +                   core_if->dev_if->in_ep_regs[0];
25813 +               gnptxsts_data_t tx_status = {.d32 = 0 };
25814 +
25815 +               tx_status.d32 =
25816 +                   DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
25817 +               /** @todo Should there be check for room in the Tx
25818 +                * Status Queue.  If not remove the code above this comment. */
25819 +
25820 +               depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
25821 +               deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
25822 +
25823 +               /* Program the transfer size and packet count
25824 +                *      as follows: xfersize = N * maxpacket +
25825 +                *      short_packet pktcnt = N + (short_packet
25826 +                *      exist ? 1 : 0)
25827 +                */
25828 +
25829 +               if (core_if->dma_desc_enable == 0) {
25830 +                       deptsiz.b.xfersize =
25831 +                           (ep->total_len - ep->xfer_count) >
25832 +                           ep->maxpacket ? ep->maxpacket : (ep->total_len -
25833 +                                                            ep->xfer_count);
25834 +                       deptsiz.b.pktcnt = 1;
25835 +                       if (core_if->dma_enable == 0) {
25836 +                               ep->xfer_len += deptsiz.b.xfersize;
25837 +                       } else {
25838 +                               ep->xfer_len = deptsiz.b.xfersize;
25839 +                       }
25840 +                       DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
25841 +               } else {
25842 +                       ep->xfer_len =
25843 +                           (ep->total_len - ep->xfer_count) >
25844 +                           ep->maxpacket ? ep->maxpacket : (ep->total_len -
25845 +                                                            ep->xfer_count);
25846 +
25847 +                       dma_desc = core_if->dev_if->in_desc_addr;
25848 +
25849 +                       /** DMA Descriptor Setup */
25850 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
25851 +                       dma_desc->status.b.l = 1;
25852 +                       dma_desc->status.b.ioc = 1;
25853 +                       dma_desc->status.b.sp =
25854 +                           (ep->xfer_len == ep->maxpacket) ? 0 : 1;
25855 +                       dma_desc->status.b.bytes = ep->xfer_len;
25856 +                       dma_desc->buf = ep->dma_addr;
25857 +                       dma_desc->status.b.sts = 0;
25858 +                       dma_desc->status.b.bs = BS_HOST_READY;
25859 +
25860 +                       /** DIEPDMA0 Register write */
25861 +                       DWC_WRITE_REG32(&in_regs->diepdma,
25862 +                                       core_if->dev_if->dma_in_desc_addr);
25863 +               }
25864 +
25865 +               DWC_DEBUGPL(DBG_PCDV,
25866 +                           "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
25867 +                           ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
25868 +                           deptsiz.d32);
25869 +
25870 +               /* Write the DMA register */
25871 +               if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
25872 +                       if (core_if->dma_desc_enable == 0)
25873 +                               DWC_WRITE_REG32(&(in_regs->diepdma),
25874 +                                               (uint32_t) ep->dma_addr);
25875 +               }
25876 +               if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
25877 +                       depctl.b.nextep = core_if->nextep_seq[ep->num];
25878 +               /* EP enable, IN data in FIFO */
25879 +               depctl.b.cnak = 1;
25880 +               depctl.b.epena = 1;
25881 +               DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
25882 +
25883 +               /**
25884 +                * Enable the Non-Periodic Tx FIFO empty interrupt, the
25885 +                * data will be written into the fifo by the ISR.
25886 +                */
25887 +               if (!core_if->dma_enable) {
25888 +                       if (core_if->en_multiple_tx_fifo == 0) {
25889 +                               /* First clear it from GINTSTS */
25890 +                               intr_mask.b.nptxfempty = 1;
25891 +                               DWC_MODIFY_REG32(&core_if->
25892 +                                                core_global_regs->gintmsk,
25893 +                                                intr_mask.d32, intr_mask.d32);
25894 +
25895 +                       } else {
25896 +                               /* Enable the Tx FIFO Empty Interrupt for this EP */
25897 +                               if (ep->xfer_len > 0) {
25898 +                                       uint32_t fifoemptymsk = 0;
25899 +                                       fifoemptymsk |= 1 << ep->num;
25900 +                                       DWC_MODIFY_REG32(&core_if->
25901 +                                                        dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
25902 +                                                        0, fifoemptymsk);
25903 +                               }
25904 +                       }
25905 +               }
25906 +       } else {
25907 +               dwc_otg_dev_out_ep_regs_t *out_regs =
25908 +                   core_if->dev_if->out_ep_regs[0];
25909 +
25910 +               depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
25911 +               deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
25912 +
25913 +               /* Program the transfer size and packet count
25914 +                *      as follows: xfersize = N * maxpacket +
25915 +                *      short_packet pktcnt = N + (short_packet
25916 +                *      exist ? 1 : 0)
25917 +                */
25918 +               deptsiz.b.xfersize = ep->maxpacket;
25919 +               deptsiz.b.pktcnt = 1;
25920 +
25921 +               if (core_if->dma_desc_enable == 0) {
25922 +                       DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
25923 +               } else {
25924 +                       dma_desc = core_if->dev_if->out_desc_addr;
25925 +
25926 +                       /** DMA Descriptor Setup */
25927 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
25928 +                       dma_desc->status.b.l = 1;
25929 +                       dma_desc->status.b.ioc = 1;
25930 +                       dma_desc->status.b.bytes = ep->maxpacket;
25931 +                       dma_desc->buf = ep->dma_addr;
25932 +                       dma_desc->status.b.sts = 0;
25933 +                       dma_desc->status.b.bs = BS_HOST_READY;
25934 +
25935 +                       /** DOEPDMA0 Register write */
25936 +                       DWC_WRITE_REG32(&out_regs->doepdma,
25937 +                                       core_if->dev_if->dma_out_desc_addr);
25938 +               }
25939 +
25940 +               DWC_DEBUGPL(DBG_PCDV,
25941 +                           "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
25942 +                           ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
25943 +                           deptsiz.d32);
25944 +
25945 +               /* Write the DMA register */
25946 +               if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
25947 +                       if (core_if->dma_desc_enable == 0)
25948 +                               DWC_WRITE_REG32(&(out_regs->doepdma),
25949 +                                               (uint32_t) ep->dma_addr);
25950 +
25951 +               }
25952 +
25953 +               /* EP enable, IN data in FIFO */
25954 +               depctl.b.cnak = 1;
25955 +               depctl.b.epena = 1;
25956 +               DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
25957 +
25958 +       }
25959 +}
25960 +
25961 +#ifdef DEBUG
25962 +void dump_msg(const u8 * buf, unsigned int length)
25963 +{
25964 +       unsigned int start, num, i;
25965 +       char line[52], *p;
25966 +
25967 +       if (length >= 512)
25968 +               return;
25969 +       start = 0;
25970 +       while (length > 0) {
25971 +               num = length < 16u ? length : 16u;
25972 +               p = line;
25973 +               for (i = 0; i < num; ++i) {
25974 +                       if (i == 8)
25975 +                               *p++ = ' ';
25976 +                       DWC_SPRINTF(p, " %02x", buf[i]);
25977 +                       p += 3;
25978 +               }
25979 +               *p = 0;
25980 +               DWC_PRINTF("%6x: %s\n", start, line);
25981 +               buf += num;
25982 +               start += num;
25983 +               length -= num;
25984 +       }
25985 +}
25986 +#else
25987 +static inline void dump_msg(const u8 * buf, unsigned int length)
25988 +{
25989 +}
25990 +#endif
25991 +
25992 +/**
25993 + * This function writes a packet into the Tx FIFO associated with the
25994 + * EP. For non-periodic EPs the non-periodic Tx FIFO is written.  For
25995 + * periodic EPs the periodic Tx FIFO associated with the EP is written
25996 + * with all packets for the next micro-frame.
25997 + *
25998 + * @param core_if Programming view of DWC_otg controller.
25999 + * @param ep The EP to write packet for.
26000 + * @param dma Indicates if DMA is being used.
26001 + */
26002 +void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
26003 +                            int dma)
26004 +{
26005 +       /**
26006 +        * The buffer is padded to DWORD on a per packet basis in
26007 +        * slave/dma mode if the MPS is not DWORD aligned. The last
26008 +        * packet, if short, is also padded to a multiple of DWORD.
26009 +        *
26010 +        * ep->xfer_buff always starts DWORD aligned in memory and is a
26011 +        * multiple of DWORD in length
26012 +        *
26013 +        * ep->xfer_len can be any number of bytes
26014 +        *
26015 +        * ep->xfer_count is a multiple of ep->maxpacket until the last
26016 +        *      packet
26017 +        *
26018 +        * FIFO access is DWORD */
26019 +
26020 +       uint32_t i;
26021 +       uint32_t byte_count;
26022 +       uint32_t dword_count;
26023 +       uint32_t *fifo;
26024 +       uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
26025 +
26026 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
26027 +                   ep);
26028 +       if (ep->xfer_count >= ep->xfer_len) {
26029 +               DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
26030 +               return;
26031 +       }
26032 +
26033 +       /* Find the byte length of the packet either short packet or MPS */
26034 +       if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
26035 +               byte_count = ep->xfer_len - ep->xfer_count;
26036 +       } else {
26037 +               byte_count = ep->maxpacket;
26038 +       }
26039 +
26040 +       /* Find the DWORD length, padded by extra bytes as neccessary if MPS
26041 +        * is not a multiple of DWORD */
26042 +       dword_count = (byte_count + 3) / 4;
26043 +
26044 +#ifdef VERBOSE
26045 +       dump_msg(ep->xfer_buff, byte_count);
26046 +#endif
26047 +
26048 +       /**@todo NGS Where are the Periodic Tx FIFO addresses
26049 +        * intialized?  What should this be? */
26050 +
26051 +       fifo = core_if->data_fifo[ep->num];
26052 +
26053 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
26054 +                   fifo, data_buff, *data_buff, byte_count);
26055 +
26056 +       if (!dma) {
26057 +               for (i = 0; i < dword_count; i++, data_buff++) {
26058 +                       DWC_WRITE_REG32(fifo, *data_buff);
26059 +               }
26060 +       }
26061 +
26062 +       ep->xfer_count += byte_count;
26063 +       ep->xfer_buff += byte_count;
26064 +       ep->dma_addr += byte_count;
26065 +}
26066 +
26067 +/**
26068 + * Set the EP STALL.
26069 + *
26070 + * @param core_if Programming view of DWC_otg controller.
26071 + * @param ep The EP to set the stall on.
26072 + */
26073 +void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26074 +{
26075 +       depctl_data_t depctl;
26076 +       volatile uint32_t *depctl_addr;
26077 +
26078 +       DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
26079 +                   (ep->is_in ? "IN" : "OUT"));
26080 +
26081 +       if (ep->is_in == 1) {
26082 +               depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
26083 +               depctl.d32 = DWC_READ_REG32(depctl_addr);
26084 +
26085 +               /* set the disable and stall bits */
26086 +               if (depctl.b.epena) {
26087 +                       depctl.b.epdis = 1;
26088 +               }
26089 +               depctl.b.stall = 1;
26090 +               DWC_WRITE_REG32(depctl_addr, depctl.d32);
26091 +       } else {
26092 +               depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
26093 +               depctl.d32 = DWC_READ_REG32(depctl_addr);
26094 +
26095 +               /* set the stall bit */
26096 +               depctl.b.stall = 1;
26097 +               DWC_WRITE_REG32(depctl_addr, depctl.d32);
26098 +       }
26099 +
26100 +       DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
26101 +
26102 +       return;
26103 +}
26104 +
26105 +/**
26106 + * Clear the EP STALL.
26107 + *
26108 + * @param core_if Programming view of DWC_otg controller.
26109 + * @param ep The EP to clear stall from.
26110 + */
26111 +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26112 +{
26113 +       depctl_data_t depctl;
26114 +       volatile uint32_t *depctl_addr;
26115 +
26116 +       DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
26117 +                   (ep->is_in ? "IN" : "OUT"));
26118 +
26119 +       if (ep->is_in == 1) {
26120 +               depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
26121 +       } else {
26122 +               depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
26123 +       }
26124 +
26125 +       depctl.d32 = DWC_READ_REG32(depctl_addr);
26126 +
26127 +       /* clear the stall bits */
26128 +       depctl.b.stall = 0;
26129 +
26130 +       /*
26131 +        * USB Spec 9.4.5: For endpoints using data toggle, regardless
26132 +        * of whether an endpoint has the Halt feature set, a
26133 +        * ClearFeature(ENDPOINT_HALT) request always results in the
26134 +        * data toggle being reinitialized to DATA0.
26135 +        */
26136 +       if (ep->type == DWC_OTG_EP_TYPE_INTR ||
26137 +           ep->type == DWC_OTG_EP_TYPE_BULK) {
26138 +               depctl.b.setd0pid = 1;  /* DATA0 */
26139 +       }
26140 +
26141 +       DWC_WRITE_REG32(depctl_addr, depctl.d32);
26142 +       DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
26143 +       return;
26144 +}
26145 +
26146 +/**
26147 + * This function reads a packet from the Rx FIFO into the destination
26148 + * buffer. To read SETUP data use dwc_otg_read_setup_packet.
26149 + *
26150 + * @param core_if Programming view of DWC_otg controller.
26151 + * @param dest   Destination buffer for the packet.
26152 + * @param bytes  Number of bytes to copy to the destination.
26153 + */
26154 +void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
26155 +                        uint8_t * dest, uint16_t bytes)
26156 +{
26157 +       int i;
26158 +       int word_count = (bytes + 3) / 4;
26159 +
26160 +       volatile uint32_t *fifo = core_if->data_fifo[0];
26161 +       uint32_t *data_buff = (uint32_t *) dest;
26162 +
26163 +       /**
26164 +        * @todo Account for the case where _dest is not dword aligned. This
26165 +        * requires reading data from the FIFO into a uint32_t temp buffer,
26166 +        * then moving it into the data buffer.
26167 +        */
26168 +
26169 +       DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
26170 +                   core_if, dest, bytes);
26171 +
26172 +       for (i = 0; i < word_count; i++, data_buff++) {
26173 +               *data_buff = DWC_READ_REG32(fifo);
26174 +       }
26175 +
26176 +       return;
26177 +}
26178 +
26179 +/**
26180 + * This functions reads the device registers and prints them
26181 + *
26182 + * @param core_if Programming view of DWC_otg controller.
26183 + */
26184 +void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
26185 +{
26186 +       int i;
26187 +       volatile uint32_t *addr;
26188 +
26189 +       DWC_PRINTF("Device Global Registers\n");
26190 +       addr = &core_if->dev_if->dev_global_regs->dcfg;
26191 +       DWC_PRINTF("DCFG                 @0x%08lX : 0x%08X\n",
26192 +                  (unsigned long)addr, DWC_READ_REG32(addr));
26193 +       addr = &core_if->dev_if->dev_global_regs->dctl;
26194 +       DWC_PRINTF("DCTL                 @0x%08lX : 0x%08X\n",
26195 +                  (unsigned long)addr, DWC_READ_REG32(addr));
26196 +       addr = &core_if->dev_if->dev_global_regs->dsts;
26197 +       DWC_PRINTF("DSTS                 @0x%08lX : 0x%08X\n",
26198 +                  (unsigned long)addr, DWC_READ_REG32(addr));
26199 +       addr = &core_if->dev_if->dev_global_regs->diepmsk;
26200 +       DWC_PRINTF("DIEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26201 +                  DWC_READ_REG32(addr));
26202 +       addr = &core_if->dev_if->dev_global_regs->doepmsk;
26203 +       DWC_PRINTF("DOEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26204 +                  DWC_READ_REG32(addr));
26205 +       addr = &core_if->dev_if->dev_global_regs->daint;
26206 +       DWC_PRINTF("DAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
26207 +                  DWC_READ_REG32(addr));
26208 +       addr = &core_if->dev_if->dev_global_regs->daintmsk;
26209 +       DWC_PRINTF("DAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
26210 +                  DWC_READ_REG32(addr));
26211 +       addr = &core_if->dev_if->dev_global_regs->dtknqr1;
26212 +       DWC_PRINTF("DTKNQR1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26213 +                  DWC_READ_REG32(addr));
26214 +       if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
26215 +               addr = &core_if->dev_if->dev_global_regs->dtknqr2;
26216 +               DWC_PRINTF("DTKNQR2      @0x%08lX : 0x%08X\n",
26217 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26218 +       }
26219 +
26220 +       addr = &core_if->dev_if->dev_global_regs->dvbusdis;
26221 +       DWC_PRINTF("DVBUSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26222 +                  DWC_READ_REG32(addr));
26223 +
26224 +       addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
26225 +       DWC_PRINTF("DVBUSPULSE  @0x%08lX : 0x%08X\n",
26226 +                  (unsigned long)addr, DWC_READ_REG32(addr));
26227 +
26228 +       addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
26229 +       DWC_PRINTF("DTKNQR3_DTHRCTL      @0x%08lX : 0x%08X\n",
26230 +                  (unsigned long)addr, DWC_READ_REG32(addr));
26231 +
26232 +       if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
26233 +               addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
26234 +               DWC_PRINTF("DTKNQR4      @0x%08lX : 0x%08X\n",
26235 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26236 +       }
26237 +
26238 +       addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
26239 +       DWC_PRINTF("FIFOEMPMSK   @0x%08lX : 0x%08X\n", (unsigned long)addr,
26240 +                  DWC_READ_REG32(addr));
26241 +
26242 +       if (core_if->hwcfg2.b.multi_proc_int) {
26243 +
26244 +               addr = &core_if->dev_if->dev_global_regs->deachint;
26245 +               DWC_PRINTF("DEACHINT     @0x%08lX : 0x%08X\n",
26246 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26247 +               addr = &core_if->dev_if->dev_global_regs->deachintmsk;
26248 +               DWC_PRINTF("DEACHINTMSK  @0x%08lX : 0x%08X\n",
26249 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26250 +
26251 +               for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
26252 +                       addr =
26253 +                           &core_if->dev_if->
26254 +                           dev_global_regs->diepeachintmsk[i];
26255 +                       DWC_PRINTF("DIEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
26256 +                                  i, (unsigned long)addr,
26257 +                                  DWC_READ_REG32(addr));
26258 +               }
26259 +
26260 +               for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
26261 +                       addr =
26262 +                           &core_if->dev_if->
26263 +                           dev_global_regs->doepeachintmsk[i];
26264 +                       DWC_PRINTF("DOEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
26265 +                                  i, (unsigned long)addr,
26266 +                                  DWC_READ_REG32(addr));
26267 +               }
26268 +       }
26269 +
26270 +       for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
26271 +               DWC_PRINTF("Device IN EP %d Registers\n", i);
26272 +               addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
26273 +               DWC_PRINTF("DIEPCTL      @0x%08lX : 0x%08X\n",
26274 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26275 +               addr = &core_if->dev_if->in_ep_regs[i]->diepint;
26276 +               DWC_PRINTF("DIEPINT      @0x%08lX : 0x%08X\n",
26277 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26278 +               addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
26279 +               DWC_PRINTF("DIETSIZ      @0x%08lX : 0x%08X\n",
26280 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26281 +               addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
26282 +               DWC_PRINTF("DIEPDMA      @0x%08lX : 0x%08X\n",
26283 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26284 +               addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
26285 +               DWC_PRINTF("DTXFSTS      @0x%08lX : 0x%08X\n",
26286 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26287 +               addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
26288 +               DWC_PRINTF("DIEPDMAB     @0x%08lX : 0x%08X\n",
26289 +                          (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
26290 +       }
26291 +
26292 +       for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
26293 +               DWC_PRINTF("Device OUT EP %d Registers\n", i);
26294 +               addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
26295 +               DWC_PRINTF("DOEPCTL      @0x%08lX : 0x%08X\n",
26296 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26297 +               addr = &core_if->dev_if->out_ep_regs[i]->doepint;
26298 +               DWC_PRINTF("DOEPINT      @0x%08lX : 0x%08X\n",
26299 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26300 +               addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
26301 +               DWC_PRINTF("DOETSIZ      @0x%08lX : 0x%08X\n",
26302 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26303 +               addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
26304 +               DWC_PRINTF("DOEPDMA      @0x%08lX : 0x%08X\n",
26305 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26306 +               if (core_if->dma_enable) {      /* Don't access this register in SLAVE mode */
26307 +                       addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
26308 +                       DWC_PRINTF("DOEPDMAB     @0x%08lX : 0x%08X\n",
26309 +                                  (unsigned long)addr, DWC_READ_REG32(addr));
26310 +               }
26311 +
26312 +       }
26313 +}
26314 +
26315 +/**
26316 + * This functions reads the SPRAM and prints its content
26317 + *
26318 + * @param core_if Programming view of DWC_otg controller.
26319 + */
26320 +void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
26321 +{
26322 +       volatile uint8_t *addr, *start_addr, *end_addr;
26323 +
26324 +       DWC_PRINTF("SPRAM Data:\n");
26325 +       start_addr = (void *)core_if->core_global_regs;
26326 +       DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
26327 +       start_addr += 0x00028000;
26328 +       end_addr = (void *)core_if->core_global_regs;
26329 +       end_addr += 0x000280e0;
26330 +
26331 +       for (addr = start_addr; addr < end_addr; addr += 16) {
26332 +               DWC_PRINTF
26333 +                   ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
26334 +                    (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
26335 +                    addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
26336 +                    addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
26337 +                   );
26338 +       }
26339 +
26340 +       return;
26341 +}
26342 +
26343 +/**
26344 + * This function reads the host registers and prints them
26345 + *
26346 + * @param core_if Programming view of DWC_otg controller.
26347 + */
26348 +void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
26349 +{
26350 +       int i;
26351 +       volatile uint32_t *addr;
26352 +
26353 +       DWC_PRINTF("Host Global Registers\n");
26354 +       addr = &core_if->host_if->host_global_regs->hcfg;
26355 +       DWC_PRINTF("HCFG                 @0x%08lX : 0x%08X\n",
26356 +                  (unsigned long)addr, DWC_READ_REG32(addr));
26357 +       addr = &core_if->host_if->host_global_regs->hfir;
26358 +       DWC_PRINTF("HFIR                 @0x%08lX : 0x%08X\n",
26359 +                  (unsigned long)addr, DWC_READ_REG32(addr));
26360 +       addr = &core_if->host_if->host_global_regs->hfnum;
26361 +       DWC_PRINTF("HFNUM        @0x%08lX : 0x%08X\n", (unsigned long)addr,
26362 +                  DWC_READ_REG32(addr));
26363 +       addr = &core_if->host_if->host_global_regs->hptxsts;
26364 +       DWC_PRINTF("HPTXSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26365 +                  DWC_READ_REG32(addr));
26366 +       addr = &core_if->host_if->host_global_regs->haint;
26367 +       DWC_PRINTF("HAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
26368 +                  DWC_READ_REG32(addr));
26369 +       addr = &core_if->host_if->host_global_regs->haintmsk;
26370 +       DWC_PRINTF("HAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
26371 +                  DWC_READ_REG32(addr));
26372 +       if (core_if->dma_desc_enable) {
26373 +               addr = &core_if->host_if->host_global_regs->hflbaddr;
26374 +               DWC_PRINTF("HFLBADDR     @0x%08lX : 0x%08X\n",
26375 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26376 +       }
26377 +
26378 +       addr = core_if->host_if->hprt0;
26379 +       DWC_PRINTF("HPRT0        @0x%08lX : 0x%08X\n", (unsigned long)addr,
26380 +                  DWC_READ_REG32(addr));
26381 +
26382 +       for (i = 0; i < core_if->core_params->host_channels; i++) {
26383 +               DWC_PRINTF("Host Channel %d Specific Registers\n", i);
26384 +               addr = &core_if->host_if->hc_regs[i]->hcchar;
26385 +               DWC_PRINTF("HCCHAR       @0x%08lX : 0x%08X\n",
26386 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26387 +               addr = &core_if->host_if->hc_regs[i]->hcsplt;
26388 +               DWC_PRINTF("HCSPLT       @0x%08lX : 0x%08X\n",
26389 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26390 +               addr = &core_if->host_if->hc_regs[i]->hcint;
26391 +               DWC_PRINTF("HCINT        @0x%08lX : 0x%08X\n",
26392 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26393 +               addr = &core_if->host_if->hc_regs[i]->hcintmsk;
26394 +               DWC_PRINTF("HCINTMSK     @0x%08lX : 0x%08X\n",
26395 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26396 +               addr = &core_if->host_if->hc_regs[i]->hctsiz;
26397 +               DWC_PRINTF("HCTSIZ       @0x%08lX : 0x%08X\n",
26398 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26399 +               addr = &core_if->host_if->hc_regs[i]->hcdma;
26400 +               DWC_PRINTF("HCDMA        @0x%08lX : 0x%08X\n",
26401 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26402 +               if (core_if->dma_desc_enable) {
26403 +                       addr = &core_if->host_if->hc_regs[i]->hcdmab;
26404 +                       DWC_PRINTF("HCDMAB       @0x%08lX : 0x%08X\n",
26405 +                                  (unsigned long)addr, DWC_READ_REG32(addr));
26406 +               }
26407 +
26408 +       }
26409 +       return;
26410 +}
26411 +
26412 +/**
26413 + * This function reads the core global registers and prints them
26414 + *
26415 + * @param core_if Programming view of DWC_otg controller.
26416 + */
26417 +void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
26418 +{
26419 +       int i, ep_num;
26420 +       volatile uint32_t *addr;
26421 +       char *txfsiz;
26422 +
26423 +       DWC_PRINTF("Core Global Registers\n");
26424 +       addr = &core_if->core_global_regs->gotgctl;
26425 +       DWC_PRINTF("GOTGCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26426 +                  DWC_READ_REG32(addr));
26427 +       addr = &core_if->core_global_regs->gotgint;
26428 +       DWC_PRINTF("GOTGINT      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26429 +                  DWC_READ_REG32(addr));
26430 +       addr = &core_if->core_global_regs->gahbcfg;
26431 +       DWC_PRINTF("GAHBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26432 +                  DWC_READ_REG32(addr));
26433 +       addr = &core_if->core_global_regs->gusbcfg;
26434 +       DWC_PRINTF("GUSBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26435 +                  DWC_READ_REG32(addr));
26436 +       addr = &core_if->core_global_regs->grstctl;
26437 +       DWC_PRINTF("GRSTCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26438 +                  DWC_READ_REG32(addr));
26439 +       addr = &core_if->core_global_regs->gintsts;
26440 +       DWC_PRINTF("GINTSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26441 +                  DWC_READ_REG32(addr));
26442 +       addr = &core_if->core_global_regs->gintmsk;
26443 +       DWC_PRINTF("GINTMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26444 +                  DWC_READ_REG32(addr));
26445 +       addr = &core_if->core_global_regs->grxstsr;
26446 +       DWC_PRINTF("GRXSTSR      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26447 +                  DWC_READ_REG32(addr));
26448 +       addr = &core_if->core_global_regs->grxfsiz;
26449 +       DWC_PRINTF("GRXFSIZ      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26450 +                  DWC_READ_REG32(addr));
26451 +       addr = &core_if->core_global_regs->gnptxfsiz;
26452 +       DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
26453 +                  DWC_READ_REG32(addr));
26454 +       addr = &core_if->core_global_regs->gnptxsts;
26455 +       DWC_PRINTF("GNPTXSTS     @0x%08lX : 0x%08X\n", (unsigned long)addr,
26456 +                  DWC_READ_REG32(addr));
26457 +       addr = &core_if->core_global_regs->gi2cctl;
26458 +       DWC_PRINTF("GI2CCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26459 +                  DWC_READ_REG32(addr));
26460 +       addr = &core_if->core_global_regs->gpvndctl;
26461 +       DWC_PRINTF("GPVNDCTL     @0x%08lX : 0x%08X\n", (unsigned long)addr,
26462 +                  DWC_READ_REG32(addr));
26463 +       addr = &core_if->core_global_regs->ggpio;
26464 +       DWC_PRINTF("GGPIO        @0x%08lX : 0x%08X\n", (unsigned long)addr,
26465 +                  DWC_READ_REG32(addr));
26466 +       addr = &core_if->core_global_regs->guid;
26467 +       DWC_PRINTF("GUID                 @0x%08lX : 0x%08X\n",
26468 +                  (unsigned long)addr, DWC_READ_REG32(addr));
26469 +       addr = &core_if->core_global_regs->gsnpsid;
26470 +       DWC_PRINTF("GSNPSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26471 +                  DWC_READ_REG32(addr));
26472 +       addr = &core_if->core_global_regs->ghwcfg1;
26473 +       DWC_PRINTF("GHWCFG1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26474 +                  DWC_READ_REG32(addr));
26475 +       addr = &core_if->core_global_regs->ghwcfg2;
26476 +       DWC_PRINTF("GHWCFG2      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26477 +                  DWC_READ_REG32(addr));
26478 +       addr = &core_if->core_global_regs->ghwcfg3;
26479 +       DWC_PRINTF("GHWCFG3      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26480 +                  DWC_READ_REG32(addr));
26481 +       addr = &core_if->core_global_regs->ghwcfg4;
26482 +       DWC_PRINTF("GHWCFG4      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26483 +                  DWC_READ_REG32(addr));
26484 +       addr = &core_if->core_global_regs->glpmcfg;
26485 +       DWC_PRINTF("GLPMCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26486 +                  DWC_READ_REG32(addr));
26487 +       addr = &core_if->core_global_regs->gpwrdn;
26488 +       DWC_PRINTF("GPWRDN       @0x%08lX : 0x%08X\n", (unsigned long)addr,
26489 +                  DWC_READ_REG32(addr));
26490 +       addr = &core_if->core_global_regs->gdfifocfg;
26491 +       DWC_PRINTF("GDFIFOCFG    @0x%08lX : 0x%08X\n", (unsigned long)addr,
26492 +                  DWC_READ_REG32(addr));
26493 +       addr = &core_if->core_global_regs->adpctl;
26494 +       DWC_PRINTF("ADPCTL       @0x%08lX : 0x%08X\n", (unsigned long)addr,
26495 +                  dwc_otg_adp_read_reg(core_if));
26496 +       addr = &core_if->core_global_regs->hptxfsiz;
26497 +       DWC_PRINTF("HPTXFSIZ     @0x%08lX : 0x%08X\n", (unsigned long)addr,
26498 +                  DWC_READ_REG32(addr));
26499 +
26500 +       if (core_if->en_multiple_tx_fifo == 0) {
26501 +               ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
26502 +               txfsiz = "DPTXFSIZ";
26503 +       } else {
26504 +               ep_num = core_if->hwcfg4.b.num_in_eps;
26505 +               txfsiz = "DIENPTXF";
26506 +       }
26507 +       for (i = 0; i < ep_num; i++) {
26508 +               addr = &core_if->core_global_regs->dtxfsiz[i];
26509 +               DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
26510 +                          (unsigned long)addr, DWC_READ_REG32(addr));
26511 +       }
26512 +       addr = core_if->pcgcctl;
26513 +       DWC_PRINTF("PCGCCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
26514 +                  DWC_READ_REG32(addr));
26515 +}
26516 +
26517 +/**
26518 + * Flush a Tx FIFO.
26519 + *
26520 + * @param core_if Programming view of DWC_otg controller.
26521 + * @param num Tx FIFO to flush.
26522 + */
26523 +void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
26524 +{
26525 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26526 +       volatile grstctl_t greset = {.d32 = 0 };
26527 +       int count = 0;
26528 +
26529 +       DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
26530 +
26531 +       greset.b.txfflsh = 1;
26532 +       greset.b.txfnum = num;
26533 +       DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26534 +
26535 +       do {
26536 +               greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26537 +               if (++count > 10000) {
26538 +                       DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
26539 +                                __func__, greset.d32,
26540 +                                DWC_READ_REG32(&global_regs->gnptxsts));
26541 +                       break;
26542 +               }
26543 +               dwc_udelay(1);
26544 +       } while (greset.b.txfflsh == 1);
26545 +
26546 +       /* Wait for 3 PHY Clocks */
26547 +       dwc_udelay(1);
26548 +}
26549 +
26550 +/**
26551 + * Flush Rx FIFO.
26552 + *
26553 + * @param core_if Programming view of DWC_otg controller.
26554 + */
26555 +void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
26556 +{
26557 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26558 +       volatile grstctl_t greset = {.d32 = 0 };
26559 +       int count = 0;
26560 +
26561 +       DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
26562 +       /*
26563 +        *
26564 +        */
26565 +       greset.b.rxfflsh = 1;
26566 +       DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26567 +
26568 +       do {
26569 +               greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26570 +               if (++count > 10000) {
26571 +                       DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
26572 +                                greset.d32);
26573 +                       break;
26574 +               }
26575 +               dwc_udelay(1);
26576 +       } while (greset.b.rxfflsh == 1);
26577 +
26578 +       /* Wait for 3 PHY Clocks */
26579 +       dwc_udelay(1);
26580 +}
26581 +
26582 +/**
26583 + * Do core a soft reset of the core.  Be careful with this because it
26584 + * resets all the internal state machines of the core.
26585 + */
26586 +void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
26587 +{
26588 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
26589 +       volatile grstctl_t greset = {.d32 = 0 };
26590 +       int count = 0;
26591 +
26592 +       DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
26593 +       /* Wait for AHB master IDLE state. */
26594 +       do {
26595 +               dwc_udelay(10);
26596 +               greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26597 +               if (++count > 100000) {
26598 +                       DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
26599 +                                greset.d32);
26600 +                       return;
26601 +               }
26602 +       }
26603 +       while (greset.b.ahbidle == 0);
26604 +
26605 +       /* Core Soft Reset */
26606 +       count = 0;
26607 +       greset.b.csftrst = 1;
26608 +       DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
26609 +       do {
26610 +               greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
26611 +               if (++count > 10000) {
26612 +                       DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
26613 +                                __func__, greset.d32);
26614 +                       break;
26615 +               }
26616 +               dwc_udelay(1);
26617 +       }
26618 +       while (greset.b.csftrst == 1);
26619 +
26620 +       /* Wait for 3 PHY Clocks */
26621 +       dwc_mdelay(100);
26622 +}
26623 +
26624 +uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
26625 +{
26626 +       return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
26627 +}
26628 +
26629 +uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
26630 +{
26631 +       return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
26632 +}
26633 +
26634 +/**
26635 + * Register HCD callbacks. The callbacks are used to start and stop
26636 + * the HCD for interrupt processing.
26637 + *
26638 + * @param core_if Programming view of DWC_otg controller.
26639 + * @param cb the HCD callback structure.
26640 + * @param p pointer to be passed to callback function (usb_hcd*).
26641 + */
26642 +void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
26643 +                                       dwc_otg_cil_callbacks_t * cb, void *p)
26644 +{
26645 +       core_if->hcd_cb = cb;
26646 +       cb->p = p;
26647 +}
26648 +
26649 +/**
26650 + * Register PCD callbacks. The callbacks are used to start and stop
26651 + * the PCD for interrupt processing.
26652 + *
26653 + * @param core_if Programming view of DWC_otg controller.
26654 + * @param cb the PCD callback structure.
26655 + * @param p pointer to be passed to callback function (pcd*).
26656 + */
26657 +void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
26658 +                                       dwc_otg_cil_callbacks_t * cb, void *p)
26659 +{
26660 +       core_if->pcd_cb = cb;
26661 +       cb->p = p;
26662 +}
26663 +
26664 +#ifdef DWC_EN_ISOC
26665 +
26666 +/**
26667 + * This function writes isoc data per 1 (micro)frame into tx fifo
26668 + *
26669 + * @param core_if Programming view of DWC_otg controller.
26670 + * @param ep The EP to start the transfer on.
26671 + *
26672 + */
26673 +void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
26674 +{
26675 +       dwc_otg_dev_in_ep_regs_t *ep_regs;
26676 +       dtxfsts_data_t txstatus = {.d32 = 0 };
26677 +       uint32_t len = 0;
26678 +       uint32_t dwords;
26679 +
26680 +       ep->xfer_len = ep->data_per_frame;
26681 +       ep->xfer_count = 0;
26682 +
26683 +       ep_regs = core_if->dev_if->in_ep_regs[ep->num];
26684 +
26685 +       len = ep->xfer_len - ep->xfer_count;
26686 +
26687 +       if (len > ep->maxpacket) {
26688 +               len = ep->maxpacket;
26689 +       }
26690 +
26691 +       dwords = (len + 3) / 4;
26692 +
26693 +       /* While there is space in the queue and space in the FIFO and
26694 +        * More data to tranfer, Write packets to the Tx FIFO */
26695 +       txstatus.d32 =
26696 +           DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
26697 +       DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
26698 +
26699 +       while (txstatus.b.txfspcavail > dwords &&
26700 +              ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
26701 +               /* Write the FIFO */
26702 +               dwc_otg_ep_write_packet(core_if, ep, 0);
26703 +
26704 +               len = ep->xfer_len - ep->xfer_count;
26705 +               if (len > ep->maxpacket) {
26706 +                       len = ep->maxpacket;
26707 +               }
26708 +
26709 +               dwords = (len + 3) / 4;
26710 +               txstatus.d32 =
26711 +                   DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
26712 +                                  dtxfsts);
26713 +               DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
26714 +                           txstatus.d32);
26715 +       }
26716 +}
26717 +
26718 +/**
26719 + * This function initializes a descriptor chain for Isochronous transfer
26720 + *
26721 + * @param core_if Programming view of DWC_otg controller.
26722 + * @param ep The EP to start the transfer on.
26723 + *
26724 + */
26725 +void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
26726 +                                      dwc_ep_t * ep)
26727 +{
26728 +       deptsiz_data_t deptsiz = {.d32 = 0 };
26729 +       depctl_data_t depctl = {.d32 = 0 };
26730 +       dsts_data_t dsts = {.d32 = 0 };
26731 +       volatile uint32_t *addr;
26732 +
26733 +       if (ep->is_in) {
26734 +               addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
26735 +       } else {
26736 +               addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
26737 +       }
26738 +
26739 +       ep->xfer_len = ep->data_per_frame;
26740 +       ep->xfer_count = 0;
26741 +       ep->xfer_buff = ep->cur_pkt_addr;
26742 +       ep->dma_addr = ep->cur_pkt_dma_addr;
26743 +
26744 +       if (ep->is_in) {
26745 +               /* Program the transfer size and packet count
26746 +                *      as follows: xfersize = N * maxpacket +
26747 +                *      short_packet pktcnt = N + (short_packet
26748 +                *      exist ? 1 : 0)
26749 +                */
26750 +               deptsiz.b.xfersize = ep->xfer_len;
26751 +               deptsiz.b.pktcnt =
26752 +                   (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
26753 +               deptsiz.b.mc = deptsiz.b.pktcnt;
26754 +               DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
26755 +                               deptsiz.d32);
26756 +
26757 +               /* Write the DMA register */
26758 +               if (core_if->dma_enable) {
26759 +                       DWC_WRITE_REG32(&
26760 +                                       (core_if->dev_if->in_ep_regs[ep->num]->
26761 +                                        diepdma), (uint32_t) ep->dma_addr);
26762 +               }
26763 +       } else {
26764 +               deptsiz.b.pktcnt =
26765 +                   (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
26766 +               deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
26767 +
26768 +               DWC_WRITE_REG32(&core_if->dev_if->
26769 +                               out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
26770 +
26771 +               if (core_if->dma_enable) {
26772 +                       DWC_WRITE_REG32(&
26773 +                                       (core_if->dev_if->
26774 +                                        out_ep_regs[ep->num]->doepdma),
26775 +                                       (uint32_t) ep->dma_addr);
26776 +               }
26777 +       }
26778 +
26779 +       /** Enable endpoint, clear nak  */
26780 +
26781 +       depctl.d32 = 0;
26782 +       if (ep->bInterval == 1) {
26783 +               dsts.d32 =
26784 +                   DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
26785 +               ep->next_frame = dsts.b.soffn + ep->bInterval;
26786 +
26787 +               if (ep->next_frame & 0x1) {
26788 +                       depctl.b.setd1pid = 1;
26789 +               } else {
26790 +                       depctl.b.setd0pid = 1;
26791 +               }
26792 +       } else {
26793 +               ep->next_frame += ep->bInterval;
26794 +
26795 +               if (ep->next_frame & 0x1) {
26796 +                       depctl.b.setd1pid = 1;
26797 +               } else {
26798 +                       depctl.b.setd0pid = 1;
26799 +               }
26800 +       }
26801 +       depctl.b.epena = 1;
26802 +       depctl.b.cnak = 1;
26803 +
26804 +       DWC_MODIFY_REG32(addr, 0, depctl.d32);
26805 +       depctl.d32 = DWC_READ_REG32(addr);
26806 +
26807 +       if (ep->is_in && core_if->dma_enable == 0) {
26808 +               write_isoc_frame_data(core_if, ep);
26809 +       }
26810 +
26811 +}
26812 +#endif /* DWC_EN_ISOC */
26813 +
26814 +static void dwc_otg_set_uninitialized(int32_t * p, int size)
26815 +{
26816 +       int i;
26817 +       for (i = 0; i < size; i++) {
26818 +               p[i] = -1;
26819 +       }
26820 +}
26821 +
26822 +static int dwc_otg_param_initialized(int32_t val)
26823 +{
26824 +       return val != -1;
26825 +}
26826 +
26827 +static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
26828 +{
26829 +       int i;
26830 +       core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
26831 +       if (!core_if->core_params) {
26832 +               return -DWC_E_NO_MEMORY;
26833 +       }
26834 +       dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
26835 +                                 sizeof(*core_if->core_params) /
26836 +                                 sizeof(int32_t));
26837 +       DWC_PRINTF("Setting default values for core params\n");
26838 +       dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
26839 +       dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
26840 +       dwc_otg_set_param_dma_desc_enable(core_if,
26841 +                                         dwc_param_dma_desc_enable_default);
26842 +       dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
26843 +       dwc_otg_set_param_dma_burst_size(core_if,
26844 +                                        dwc_param_dma_burst_size_default);
26845 +       dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
26846 +                                                      dwc_param_host_support_fs_ls_low_power_default);
26847 +       dwc_otg_set_param_enable_dynamic_fifo(core_if,
26848 +                                             dwc_param_enable_dynamic_fifo_default);
26849 +       dwc_otg_set_param_data_fifo_size(core_if,
26850 +                                        dwc_param_data_fifo_size_default);
26851 +       dwc_otg_set_param_dev_rx_fifo_size(core_if,
26852 +                                          dwc_param_dev_rx_fifo_size_default);
26853 +       dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
26854 +                                                 dwc_param_dev_nperio_tx_fifo_size_default);
26855 +       dwc_otg_set_param_host_rx_fifo_size(core_if,
26856 +                                           dwc_param_host_rx_fifo_size_default);
26857 +       dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
26858 +                                                  dwc_param_host_nperio_tx_fifo_size_default);
26859 +       dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
26860 +                                                 dwc_param_host_perio_tx_fifo_size_default);
26861 +       dwc_otg_set_param_max_transfer_size(core_if,
26862 +                                           dwc_param_max_transfer_size_default);
26863 +       dwc_otg_set_param_max_packet_count(core_if,
26864 +                                          dwc_param_max_packet_count_default);
26865 +       dwc_otg_set_param_host_channels(core_if,
26866 +                                       dwc_param_host_channels_default);
26867 +       dwc_otg_set_param_dev_endpoints(core_if,
26868 +                                       dwc_param_dev_endpoints_default);
26869 +       dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
26870 +       dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
26871 +       dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
26872 +                                                   dwc_param_host_ls_low_power_phy_clk_default);
26873 +       dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
26874 +       dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
26875 +                                           dwc_param_phy_ulpi_ext_vbus_default);
26876 +       dwc_otg_set_param_phy_utmi_width(core_if,
26877 +                                        dwc_param_phy_utmi_width_default);
26878 +       dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
26879 +       dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
26880 +       dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
26881 +       dwc_otg_set_param_en_multiple_tx_fifo(core_if,
26882 +                                             dwc_param_en_multiple_tx_fifo_default);
26883 +       for (i = 0; i < 15; i++) {
26884 +               dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
26885 +                                                        dwc_param_dev_perio_tx_fifo_size_default,
26886 +                                                        i);
26887 +       }
26888 +
26889 +       for (i = 0; i < 15; i++) {
26890 +               dwc_otg_set_param_dev_tx_fifo_size(core_if,
26891 +                                                  dwc_param_dev_tx_fifo_size_default,
26892 +                                                  i);
26893 +       }
26894 +       dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
26895 +       dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
26896 +       dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
26897 +       dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
26898 +       dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
26899 +       dwc_otg_set_param_tx_thr_length(core_if,
26900 +                                       dwc_param_tx_thr_length_default);
26901 +       dwc_otg_set_param_rx_thr_length(core_if,
26902 +                                       dwc_param_rx_thr_length_default);
26903 +       dwc_otg_set_param_ahb_thr_ratio(core_if,
26904 +                                       dwc_param_ahb_thr_ratio_default);
26905 +       dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
26906 +       dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
26907 +       dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
26908 +       dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
26909 +       dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
26910 +       dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
26911 +       dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
26912 +       DWC_PRINTF("Finished setting default values for core params\n");
26913 +
26914 +       return 0;
26915 +}
26916 +
26917 +uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
26918 +{
26919 +       return core_if->dma_enable;
26920 +}
26921 +
26922 +/* Checks if the parameter is outside of its valid range of values */
26923 +#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
26924 +               (((_param_) < (_low_)) || \
26925 +               ((_param_) > (_high_)))
26926 +
26927 +/* Parameter access functions */
26928 +int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
26929 +{
26930 +       int valid;
26931 +       int retval = 0;
26932 +       if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
26933 +               DWC_WARN("Wrong value for otg_cap parameter\n");
26934 +               DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
26935 +               retval = -DWC_E_INVALID;
26936 +               goto out;
26937 +       }
26938 +
26939 +       valid = 1;
26940 +       switch (val) {
26941 +       case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
26942 +               if (core_if->hwcfg2.b.op_mode !=
26943 +                   DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
26944 +                       valid = 0;
26945 +               break;
26946 +       case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
26947 +               if ((core_if->hwcfg2.b.op_mode !=
26948 +                    DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
26949 +                   && (core_if->hwcfg2.b.op_mode !=
26950 +                       DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
26951 +                   && (core_if->hwcfg2.b.op_mode !=
26952 +                       DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
26953 +                   && (core_if->hwcfg2.b.op_mode !=
26954 +                       DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
26955 +                       valid = 0;
26956 +               }
26957 +               break;
26958 +       case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
26959 +               /* always valid */
26960 +               break;
26961 +       }
26962 +       if (!valid) {
26963 +               if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
26964 +                       DWC_ERROR
26965 +                           ("%d invalid for otg_cap paremter. Check HW configuration.\n",
26966 +                            val);
26967 +               }
26968 +               val =
26969 +                   (((core_if->hwcfg2.b.op_mode ==
26970 +                      DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
26971 +                     || (core_if->hwcfg2.b.op_mode ==
26972 +                         DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
26973 +                     || (core_if->hwcfg2.b.op_mode ==
26974 +                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
26975 +                     || (core_if->hwcfg2.b.op_mode ==
26976 +                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
26977 +                    DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
26978 +                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
26979 +               retval = -DWC_E_INVALID;
26980 +       }
26981 +
26982 +       core_if->core_params->otg_cap = val;
26983 +out:
26984 +       return retval;
26985 +}
26986 +
26987 +int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
26988 +{
26989 +       return core_if->core_params->otg_cap;
26990 +}
26991 +
26992 +int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
26993 +{
26994 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
26995 +               DWC_WARN("Wrong value for opt parameter\n");
26996 +               return -DWC_E_INVALID;
26997 +       }
26998 +       core_if->core_params->opt = val;
26999 +       return 0;
27000 +}
27001 +
27002 +int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
27003 +{
27004 +       return core_if->core_params->opt;
27005 +}
27006 +
27007 +int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
27008 +{
27009 +       int retval = 0;
27010 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27011 +               DWC_WARN("Wrong value for dma enable\n");
27012 +               return -DWC_E_INVALID;
27013 +       }
27014 +
27015 +       if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
27016 +               if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
27017 +                       DWC_ERROR
27018 +                           ("%d invalid for dma_enable paremter. Check HW configuration.\n",
27019 +                            val);
27020 +               }
27021 +               val = 0;
27022 +               retval = -DWC_E_INVALID;
27023 +       }
27024 +
27025 +       core_if->core_params->dma_enable = val;
27026 +       if (val == 0) {
27027 +               dwc_otg_set_param_dma_desc_enable(core_if, 0);
27028 +       }
27029 +       return retval;
27030 +}
27031 +
27032 +int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
27033 +{
27034 +       return core_if->core_params->dma_enable;
27035 +}
27036 +
27037 +int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
27038 +{
27039 +       int retval = 0;
27040 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27041 +               DWC_WARN("Wrong value for dma_enable\n");
27042 +               DWC_WARN("dma_desc_enable must be 0 or 1\n");
27043 +               return -DWC_E_INVALID;
27044 +       }
27045 +
27046 +       if ((val == 1)
27047 +           && ((dwc_otg_get_param_dma_enable(core_if) == 0)
27048 +               || (core_if->hwcfg4.b.desc_dma == 0))) {
27049 +               if (dwc_otg_param_initialized
27050 +                   (core_if->core_params->dma_desc_enable)) {
27051 +                       DWC_ERROR
27052 +                           ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
27053 +                            val);
27054 +               }
27055 +               val = 0;
27056 +               retval = -DWC_E_INVALID;
27057 +       }
27058 +       core_if->core_params->dma_desc_enable = val;
27059 +       return retval;
27060 +}
27061 +
27062 +int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
27063 +{
27064 +       return core_if->core_params->dma_desc_enable;
27065 +}
27066 +
27067 +int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
27068 +                                                  int32_t val)
27069 +{
27070 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27071 +               DWC_WARN("Wrong value for host_support_fs_low_power\n");
27072 +               DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
27073 +               return -DWC_E_INVALID;
27074 +       }
27075 +       core_if->core_params->host_support_fs_ls_low_power = val;
27076 +       return 0;
27077 +}
27078 +
27079 +int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
27080 +                                                      core_if)
27081 +{
27082 +       return core_if->core_params->host_support_fs_ls_low_power;
27083 +}
27084 +
27085 +int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
27086 +                                         int32_t val)
27087 +{
27088 +       int retval = 0;
27089 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27090 +               DWC_WARN("Wrong value for enable_dynamic_fifo\n");
27091 +               DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
27092 +               return -DWC_E_INVALID;
27093 +       }
27094 +
27095 +       if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
27096 +               if (dwc_otg_param_initialized
27097 +                   (core_if->core_params->enable_dynamic_fifo)) {
27098 +                       DWC_ERROR
27099 +                           ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
27100 +                            val);
27101 +               }
27102 +               val = 0;
27103 +               retval = -DWC_E_INVALID;
27104 +       }
27105 +       core_if->core_params->enable_dynamic_fifo = val;
27106 +       return retval;
27107 +}
27108 +
27109 +int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
27110 +{
27111 +       return core_if->core_params->enable_dynamic_fifo;
27112 +}
27113 +
27114 +int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
27115 +{
27116 +       int retval = 0;
27117 +       if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
27118 +               DWC_WARN("Wrong value for data_fifo_size\n");
27119 +               DWC_WARN("data_fifo_size must be 32-32768\n");
27120 +               return -DWC_E_INVALID;
27121 +       }
27122 +
27123 +       if (val > core_if->hwcfg3.b.dfifo_depth) {
27124 +               if (dwc_otg_param_initialized
27125 +                   (core_if->core_params->data_fifo_size)) {
27126 +                       DWC_ERROR
27127 +                           ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
27128 +                            val);
27129 +               }
27130 +               val = core_if->hwcfg3.b.dfifo_depth;
27131 +               retval = -DWC_E_INVALID;
27132 +       }
27133 +
27134 +       core_if->core_params->data_fifo_size = val;
27135 +       return retval;
27136 +}
27137 +
27138 +int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
27139 +{
27140 +       return core_if->core_params->data_fifo_size;
27141 +}
27142 +
27143 +int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
27144 +{
27145 +       int retval = 0;
27146 +       if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27147 +               DWC_WARN("Wrong value for dev_rx_fifo_size\n");
27148 +               DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
27149 +               return -DWC_E_INVALID;
27150 +       }
27151 +
27152 +       if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
27153 +               if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
27154 +               DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
27155 +               }
27156 +               val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
27157 +               retval = -DWC_E_INVALID;
27158 +       }
27159 +
27160 +       core_if->core_params->dev_rx_fifo_size = val;
27161 +       return retval;
27162 +}
27163 +
27164 +int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
27165 +{
27166 +       return core_if->core_params->dev_rx_fifo_size;
27167 +}
27168 +
27169 +int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27170 +                                             int32_t val)
27171 +{
27172 +       int retval = 0;
27173 +
27174 +       if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27175 +               DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
27176 +               DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
27177 +               return -DWC_E_INVALID;
27178 +       }
27179 +
27180 +       if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
27181 +               if (dwc_otg_param_initialized
27182 +                   (core_if->core_params->dev_nperio_tx_fifo_size)) {
27183 +                       DWC_ERROR
27184 +                           ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
27185 +                            val);
27186 +               }
27187 +               val =
27188 +                   (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
27189 +                    16);
27190 +               retval = -DWC_E_INVALID;
27191 +       }
27192 +
27193 +       core_if->core_params->dev_nperio_tx_fifo_size = val;
27194 +       return retval;
27195 +}
27196 +
27197 +int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27198 +{
27199 +       return core_if->core_params->dev_nperio_tx_fifo_size;
27200 +}
27201 +
27202 +int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
27203 +                                       int32_t val)
27204 +{
27205 +       int retval = 0;
27206 +
27207 +       if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27208 +               DWC_WARN("Wrong value for host_rx_fifo_size\n");
27209 +               DWC_WARN("host_rx_fifo_size must be 16-32768\n");
27210 +               return -DWC_E_INVALID;
27211 +       }
27212 +
27213 +       if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
27214 +               if (dwc_otg_param_initialized
27215 +                   (core_if->core_params->host_rx_fifo_size)) {
27216 +                       DWC_ERROR
27217 +                           ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
27218 +                            val);
27219 +               }
27220 +               val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
27221 +               retval = -DWC_E_INVALID;
27222 +       }
27223 +
27224 +       core_if->core_params->host_rx_fifo_size = val;
27225 +       return retval;
27226 +
27227 +}
27228 +
27229 +int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
27230 +{
27231 +       return core_if->core_params->host_rx_fifo_size;
27232 +}
27233 +
27234 +int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27235 +                                              int32_t val)
27236 +{
27237 +       int retval = 0;
27238 +
27239 +       if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27240 +               DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
27241 +               DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
27242 +               return -DWC_E_INVALID;
27243 +       }
27244 +
27245 +       if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
27246 +               if (dwc_otg_param_initialized
27247 +                   (core_if->core_params->host_nperio_tx_fifo_size)) {
27248 +                       DWC_ERROR
27249 +                           ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
27250 +                            val);
27251 +               }
27252 +               val =
27253 +                   (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
27254 +                    16);
27255 +               retval = -DWC_E_INVALID;
27256 +       }
27257 +
27258 +       core_if->core_params->host_nperio_tx_fifo_size = val;
27259 +       return retval;
27260 +}
27261 +
27262 +int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27263 +{
27264 +       return core_if->core_params->host_nperio_tx_fifo_size;
27265 +}
27266 +
27267 +int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27268 +                                             int32_t val)
27269 +{
27270 +       int retval = 0;
27271 +       if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
27272 +               DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
27273 +               DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
27274 +               return -DWC_E_INVALID;
27275 +       }
27276 +
27277 +       if (val > ((core_if->hptxfsiz.d32) >> 16)) {
27278 +               if (dwc_otg_param_initialized
27279 +                   (core_if->core_params->host_perio_tx_fifo_size)) {
27280 +                       DWC_ERROR
27281 +                           ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
27282 +                            val);
27283 +               }
27284 +               val = (core_if->hptxfsiz.d32) >> 16;
27285 +               retval = -DWC_E_INVALID;
27286 +       }
27287 +
27288 +       core_if->core_params->host_perio_tx_fifo_size = val;
27289 +       return retval;
27290 +}
27291 +
27292 +int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
27293 +{
27294 +       return core_if->core_params->host_perio_tx_fifo_size;
27295 +}
27296 +
27297 +int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
27298 +                                       int32_t val)
27299 +{
27300 +       int retval = 0;
27301 +
27302 +       if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
27303 +               DWC_WARN("Wrong value for max_transfer_size\n");
27304 +               DWC_WARN("max_transfer_size must be 2047-524288\n");
27305 +               return -DWC_E_INVALID;
27306 +       }
27307 +
27308 +       if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
27309 +               if (dwc_otg_param_initialized
27310 +                   (core_if->core_params->max_transfer_size)) {
27311 +                       DWC_ERROR
27312 +                           ("%d invalid for max_transfer_size. Check HW configuration.\n",
27313 +                            val);
27314 +               }
27315 +               val =
27316 +                   ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
27317 +                    1);
27318 +               retval = -DWC_E_INVALID;
27319 +       }
27320 +
27321 +       core_if->core_params->max_transfer_size = val;
27322 +       return retval;
27323 +}
27324 +
27325 +int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
27326 +{
27327 +       return core_if->core_params->max_transfer_size;
27328 +}
27329 +
27330 +int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
27331 +{
27332 +       int retval = 0;
27333 +
27334 +       if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
27335 +               DWC_WARN("Wrong value for max_packet_count\n");
27336 +               DWC_WARN("max_packet_count must be 15-511\n");
27337 +               return -DWC_E_INVALID;
27338 +       }
27339 +
27340 +       if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
27341 +               if (dwc_otg_param_initialized
27342 +                   (core_if->core_params->max_packet_count)) {
27343 +                       DWC_ERROR
27344 +                           ("%d invalid for max_packet_count. Check HW configuration.\n",
27345 +                            val);
27346 +               }
27347 +               val =
27348 +                   ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
27349 +               retval = -DWC_E_INVALID;
27350 +       }
27351 +
27352 +       core_if->core_params->max_packet_count = val;
27353 +       return retval;
27354 +}
27355 +
27356 +int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
27357 +{
27358 +       return core_if->core_params->max_packet_count;
27359 +}
27360 +
27361 +int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
27362 +{
27363 +       int retval = 0;
27364 +
27365 +       if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
27366 +               DWC_WARN("Wrong value for host_channels\n");
27367 +               DWC_WARN("host_channels must be 1-16\n");
27368 +               return -DWC_E_INVALID;
27369 +       }
27370 +
27371 +       if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
27372 +               if (dwc_otg_param_initialized
27373 +                   (core_if->core_params->host_channels)) {
27374 +                       DWC_ERROR
27375 +                           ("%d invalid for host_channels. Check HW configurations.\n",
27376 +                            val);
27377 +               }
27378 +               val = (core_if->hwcfg2.b.num_host_chan + 1);
27379 +               retval = -DWC_E_INVALID;
27380 +       }
27381 +
27382 +       core_if->core_params->host_channels = val;
27383 +       return retval;
27384 +}
27385 +
27386 +int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
27387 +{
27388 +       return core_if->core_params->host_channels;
27389 +}
27390 +
27391 +int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
27392 +{
27393 +       int retval = 0;
27394 +
27395 +       if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
27396 +               DWC_WARN("Wrong value for dev_endpoints\n");
27397 +               DWC_WARN("dev_endpoints must be 1-15\n");
27398 +               return -DWC_E_INVALID;
27399 +       }
27400 +
27401 +       if (val > (core_if->hwcfg2.b.num_dev_ep)) {
27402 +               if (dwc_otg_param_initialized
27403 +                   (core_if->core_params->dev_endpoints)) {
27404 +                       DWC_ERROR
27405 +                           ("%d invalid for dev_endpoints. Check HW configurations.\n",
27406 +                            val);
27407 +               }
27408 +               val = core_if->hwcfg2.b.num_dev_ep;
27409 +               retval = -DWC_E_INVALID;
27410 +       }
27411 +
27412 +       core_if->core_params->dev_endpoints = val;
27413 +       return retval;
27414 +}
27415 +
27416 +int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
27417 +{
27418 +       return core_if->core_params->dev_endpoints;
27419 +}
27420 +
27421 +int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
27422 +{
27423 +       int retval = 0;
27424 +       int valid = 0;
27425 +
27426 +       if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
27427 +               DWC_WARN("Wrong value for phy_type\n");
27428 +               DWC_WARN("phy_type must be 0,1 or 2\n");
27429 +               return -DWC_E_INVALID;
27430 +       }
27431 +#ifndef NO_FS_PHY_HW_CHECKS
27432 +       if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
27433 +           ((core_if->hwcfg2.b.hs_phy_type == 1) ||
27434 +            (core_if->hwcfg2.b.hs_phy_type == 3))) {
27435 +               valid = 1;
27436 +       } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
27437 +                  ((core_if->hwcfg2.b.hs_phy_type == 2) ||
27438 +                   (core_if->hwcfg2.b.hs_phy_type == 3))) {
27439 +               valid = 1;
27440 +       } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
27441 +                  (core_if->hwcfg2.b.fs_phy_type == 1)) {
27442 +               valid = 1;
27443 +       }
27444 +       if (!valid) {
27445 +               if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
27446 +                       DWC_ERROR
27447 +                           ("%d invalid for phy_type. Check HW configurations.\n",
27448 +                            val);
27449 +               }
27450 +               if (core_if->hwcfg2.b.hs_phy_type) {
27451 +                       if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
27452 +                           (core_if->hwcfg2.b.hs_phy_type == 1)) {
27453 +                               val = DWC_PHY_TYPE_PARAM_UTMI;
27454 +                       } else {
27455 +                               val = DWC_PHY_TYPE_PARAM_ULPI;
27456 +                       }
27457 +               }
27458 +               retval = -DWC_E_INVALID;
27459 +       }
27460 +#endif
27461 +       core_if->core_params->phy_type = val;
27462 +       return retval;
27463 +}
27464 +
27465 +int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
27466 +{
27467 +       return core_if->core_params->phy_type;
27468 +}
27469 +
27470 +int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
27471 +{
27472 +       int retval = 0;
27473 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27474 +               DWC_WARN("Wrong value for speed parameter\n");
27475 +               DWC_WARN("max_speed parameter must be 0 or 1\n");
27476 +               return -DWC_E_INVALID;
27477 +       }
27478 +       if ((val == 0)
27479 +           && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
27480 +               if (dwc_otg_param_initialized(core_if->core_params->speed)) {
27481 +                       DWC_ERROR
27482 +                           ("%d invalid for speed paremter. Check HW configuration.\n",
27483 +                            val);
27484 +               }
27485 +               val =
27486 +                   (dwc_otg_get_param_phy_type(core_if) ==
27487 +                    DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
27488 +               retval = -DWC_E_INVALID;
27489 +       }
27490 +       core_if->core_params->speed = val;
27491 +       return retval;
27492 +}
27493 +
27494 +int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
27495 +{
27496 +       return core_if->core_params->speed;
27497 +}
27498 +
27499 +int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
27500 +                                               int32_t val)
27501 +{
27502 +       int retval = 0;
27503 +
27504 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27505 +               DWC_WARN
27506 +                   ("Wrong value for host_ls_low_power_phy_clk parameter\n");
27507 +               DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
27508 +               return -DWC_E_INVALID;
27509 +       }
27510 +
27511 +       if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
27512 +           && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
27513 +               if (dwc_otg_param_initialized
27514 +                   (core_if->core_params->host_ls_low_power_phy_clk)) {
27515 +                       DWC_ERROR
27516 +                           ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
27517 +                            val);
27518 +               }
27519 +               val =
27520 +                   (dwc_otg_get_param_phy_type(core_if) ==
27521 +                    DWC_PHY_TYPE_PARAM_FS) ?
27522 +                   DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
27523 +                   DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
27524 +               retval = -DWC_E_INVALID;
27525 +       }
27526 +
27527 +       core_if->core_params->host_ls_low_power_phy_clk = val;
27528 +       return retval;
27529 +}
27530 +
27531 +int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
27532 +{
27533 +       return core_if->core_params->host_ls_low_power_phy_clk;
27534 +}
27535 +
27536 +int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
27537 +{
27538 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27539 +               DWC_WARN("Wrong value for phy_ulpi_ddr\n");
27540 +               DWC_WARN("phy_upli_ddr must be 0 or 1\n");
27541 +               return -DWC_E_INVALID;
27542 +       }
27543 +
27544 +       core_if->core_params->phy_ulpi_ddr = val;
27545 +       return 0;
27546 +}
27547 +
27548 +int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
27549 +{
27550 +       return core_if->core_params->phy_ulpi_ddr;
27551 +}
27552 +
27553 +int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
27554 +                                       int32_t val)
27555 +{
27556 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27557 +               DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
27558 +               DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
27559 +               return -DWC_E_INVALID;
27560 +       }
27561 +
27562 +       core_if->core_params->phy_ulpi_ext_vbus = val;
27563 +       return 0;
27564 +}
27565 +
27566 +int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
27567 +{
27568 +       return core_if->core_params->phy_ulpi_ext_vbus;
27569 +}
27570 +
27571 +int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
27572 +{
27573 +       if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
27574 +               DWC_WARN("Wrong valaue for phy_utmi_width\n");
27575 +               DWC_WARN("phy_utmi_width must be 8 or 16\n");
27576 +               return -DWC_E_INVALID;
27577 +       }
27578 +
27579 +       core_if->core_params->phy_utmi_width = val;
27580 +       return 0;
27581 +}
27582 +
27583 +int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
27584 +{
27585 +       return core_if->core_params->phy_utmi_width;
27586 +}
27587 +
27588 +int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
27589 +{
27590 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27591 +               DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
27592 +               DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
27593 +               return -DWC_E_INVALID;
27594 +       }
27595 +
27596 +       core_if->core_params->ulpi_fs_ls = val;
27597 +       return 0;
27598 +}
27599 +
27600 +int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
27601 +{
27602 +       return core_if->core_params->ulpi_fs_ls;
27603 +}
27604 +
27605 +int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
27606 +{
27607 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27608 +               DWC_WARN("Wrong valaue for ts_dline\n");
27609 +               DWC_WARN("ts_dline must be 0 or 1\n");
27610 +               return -DWC_E_INVALID;
27611 +       }
27612 +
27613 +       core_if->core_params->ts_dline = val;
27614 +       return 0;
27615 +}
27616 +
27617 +int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
27618 +{
27619 +       return core_if->core_params->ts_dline;
27620 +}
27621 +
27622 +int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
27623 +{
27624 +       int retval = 0;
27625 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27626 +               DWC_WARN("Wrong valaue for i2c_enable\n");
27627 +               DWC_WARN("i2c_enable must be 0 or 1\n");
27628 +               return -DWC_E_INVALID;
27629 +       }
27630 +#ifndef NO_FS_PHY_HW_CHECK
27631 +       if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
27632 +               if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
27633 +                       DWC_ERROR
27634 +                           ("%d invalid for i2c_enable. Check HW configuration.\n",
27635 +                            val);
27636 +               }
27637 +               val = 0;
27638 +               retval = -DWC_E_INVALID;
27639 +       }
27640 +#endif
27641 +
27642 +       core_if->core_params->i2c_enable = val;
27643 +       return retval;
27644 +}
27645 +
27646 +int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
27647 +{
27648 +       return core_if->core_params->i2c_enable;
27649 +}
27650 +
27651 +int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27652 +                                            int32_t val, int fifo_num)
27653 +{
27654 +       int retval = 0;
27655 +
27656 +       if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
27657 +               DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
27658 +               DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
27659 +               return -DWC_E_INVALID;
27660 +       }
27661 +
27662 +       if (val >
27663 +           (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
27664 +               if (dwc_otg_param_initialized
27665 +                   (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
27666 +                       DWC_ERROR
27667 +                           ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
27668 +                            val, fifo_num);
27669 +               }
27670 +               val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
27671 +               retval = -DWC_E_INVALID;
27672 +       }
27673 +
27674 +       core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
27675 +       return retval;
27676 +}
27677 +
27678 +int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
27679 +                                                int fifo_num)
27680 +{
27681 +       return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
27682 +}
27683 +
27684 +int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
27685 +                                         int32_t val)
27686 +{
27687 +       int retval = 0;
27688 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27689 +               DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
27690 +               DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
27691 +               return -DWC_E_INVALID;
27692 +       }
27693 +
27694 +       if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
27695 +               if (dwc_otg_param_initialized
27696 +                   (core_if->core_params->en_multiple_tx_fifo)) {
27697 +                       DWC_ERROR
27698 +                           ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
27699 +                            val);
27700 +               }
27701 +               val = 0;
27702 +               retval = -DWC_E_INVALID;
27703 +       }
27704 +
27705 +       core_if->core_params->en_multiple_tx_fifo = val;
27706 +       return retval;
27707 +}
27708 +
27709 +int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
27710 +{
27711 +       return core_if->core_params->en_multiple_tx_fifo;
27712 +}
27713 +
27714 +int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
27715 +                                      int fifo_num)
27716 +{
27717 +       int retval = 0;
27718 +
27719 +       if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
27720 +               DWC_WARN("Wrong value for dev_tx_fifo_size\n");
27721 +               DWC_WARN("dev_tx_fifo_size must be 4-768\n");
27722 +               return -DWC_E_INVALID;
27723 +       }
27724 +
27725 +       if (val >
27726 +           (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
27727 +               if (dwc_otg_param_initialized
27728 +                   (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
27729 +                       DWC_ERROR
27730 +                           ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
27731 +                            val, fifo_num);
27732 +               }
27733 +               val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
27734 +               retval = -DWC_E_INVALID;
27735 +       }
27736 +
27737 +       core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
27738 +       return retval;
27739 +}
27740 +
27741 +int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
27742 +                                          int fifo_num)
27743 +{
27744 +       return core_if->core_params->dev_tx_fifo_size[fifo_num];
27745 +}
27746 +
27747 +int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
27748 +{
27749 +       int retval = 0;
27750 +
27751 +       if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
27752 +               DWC_WARN("Wrong value for thr_ctl\n");
27753 +               DWC_WARN("thr_ctl must be 0-7\n");
27754 +               return -DWC_E_INVALID;
27755 +       }
27756 +
27757 +       if ((val != 0) &&
27758 +           (!dwc_otg_get_param_dma_enable(core_if) ||
27759 +            !core_if->hwcfg4.b.ded_fifo_en)) {
27760 +               if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
27761 +                       DWC_ERROR
27762 +                           ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
27763 +                            val);
27764 +               }
27765 +               val = 0;
27766 +               retval = -DWC_E_INVALID;
27767 +       }
27768 +
27769 +       core_if->core_params->thr_ctl = val;
27770 +       return retval;
27771 +}
27772 +
27773 +int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
27774 +{
27775 +       return core_if->core_params->thr_ctl;
27776 +}
27777 +
27778 +int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
27779 +{
27780 +       int retval = 0;
27781 +
27782 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27783 +               DWC_WARN("Wrong value for lpm_enable\n");
27784 +               DWC_WARN("lpm_enable must be 0 or 1\n");
27785 +               return -DWC_E_INVALID;
27786 +       }
27787 +
27788 +       if (val && !core_if->hwcfg3.b.otg_lpm_en) {
27789 +               if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
27790 +                       DWC_ERROR
27791 +                           ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
27792 +                            val);
27793 +               }
27794 +               val = 0;
27795 +               retval = -DWC_E_INVALID;
27796 +       }
27797 +
27798 +       core_if->core_params->lpm_enable = val;
27799 +       return retval;
27800 +}
27801 +
27802 +int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
27803 +{
27804 +       return core_if->core_params->lpm_enable;
27805 +}
27806 +
27807 +int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
27808 +{
27809 +       if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
27810 +               DWC_WARN("Wrong valaue for tx_thr_length\n");
27811 +               DWC_WARN("tx_thr_length must be 8 - 128\n");
27812 +               return -DWC_E_INVALID;
27813 +       }
27814 +
27815 +       core_if->core_params->tx_thr_length = val;
27816 +       return 0;
27817 +}
27818 +
27819 +int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
27820 +{
27821 +       return core_if->core_params->tx_thr_length;
27822 +}
27823 +
27824 +int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
27825 +{
27826 +       if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
27827 +               DWC_WARN("Wrong valaue for rx_thr_length\n");
27828 +               DWC_WARN("rx_thr_length must be 8 - 128\n");
27829 +               return -DWC_E_INVALID;
27830 +       }
27831 +
27832 +       core_if->core_params->rx_thr_length = val;
27833 +       return 0;
27834 +}
27835 +
27836 +int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
27837 +{
27838 +       return core_if->core_params->rx_thr_length;
27839 +}
27840 +
27841 +int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
27842 +{
27843 +       if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
27844 +           DWC_OTG_PARAM_TEST(val, 4, 4) &&
27845 +           DWC_OTG_PARAM_TEST(val, 8, 8) &&
27846 +           DWC_OTG_PARAM_TEST(val, 16, 16) &&
27847 +           DWC_OTG_PARAM_TEST(val, 32, 32) &&
27848 +           DWC_OTG_PARAM_TEST(val, 64, 64) &&
27849 +           DWC_OTG_PARAM_TEST(val, 128, 128) &&
27850 +           DWC_OTG_PARAM_TEST(val, 256, 256)) {
27851 +               DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
27852 +               return -DWC_E_INVALID;
27853 +       }
27854 +       core_if->core_params->dma_burst_size = val;
27855 +       return 0;
27856 +}
27857 +
27858 +int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
27859 +{
27860 +       return core_if->core_params->dma_burst_size;
27861 +}
27862 +
27863 +int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
27864 +{
27865 +       int retval = 0;
27866 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27867 +               DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
27868 +               return -DWC_E_INVALID;
27869 +       }
27870 +       if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
27871 +               if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
27872 +                       DWC_ERROR
27873 +                           ("%d invalid for parameter pti_enable. Check HW configuration.\n",
27874 +                            val);
27875 +               }
27876 +               retval = -DWC_E_INVALID;
27877 +               val = 0;
27878 +       }
27879 +       core_if->core_params->pti_enable = val;
27880 +       return retval;
27881 +}
27882 +
27883 +int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
27884 +{
27885 +       return core_if->core_params->pti_enable;
27886 +}
27887 +
27888 +int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
27889 +{
27890 +       int retval = 0;
27891 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27892 +               DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
27893 +               return -DWC_E_INVALID;
27894 +       }
27895 +       if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
27896 +               if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
27897 +                       DWC_ERROR
27898 +                           ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
27899 +                            val);
27900 +               }
27901 +               retval = -DWC_E_INVALID;
27902 +               val = 0;
27903 +       }
27904 +       core_if->core_params->mpi_enable = val;
27905 +       return retval;
27906 +}
27907 +
27908 +int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
27909 +{
27910 +       return core_if->core_params->mpi_enable;
27911 +}
27912 +
27913 +int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
27914 +{
27915 +       int retval = 0;
27916 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27917 +               DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
27918 +               return -DWC_E_INVALID;
27919 +       }
27920 +       if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
27921 +               if (dwc_otg_param_initialized
27922 +                   (core_if->core_params->adp_supp_enable)) {
27923 +                       DWC_ERROR
27924 +                           ("%d invalid for parameter adp_enable. Check HW configuration.\n",
27925 +                            val);
27926 +               }
27927 +               retval = -DWC_E_INVALID;
27928 +               val = 0;
27929 +       }
27930 +       core_if->core_params->adp_supp_enable = val;
27931 +       /*Set OTG version 2.0 in case of enabling ADP*/
27932 +       if (val)
27933 +               dwc_otg_set_param_otg_ver(core_if, 1);
27934 +
27935 +       return retval;
27936 +}
27937 +
27938 +int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
27939 +{
27940 +       return core_if->core_params->adp_supp_enable;
27941 +}
27942 +
27943 +int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
27944 +{
27945 +       int retval = 0;
27946 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
27947 +               DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
27948 +               DWC_WARN("ic_usb_cap must be 0 or 1\n");
27949 +               return -DWC_E_INVALID;
27950 +       }
27951 +
27952 +       if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
27953 +               if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
27954 +                       DWC_ERROR
27955 +                           ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
27956 +                            val);
27957 +               }
27958 +               retval = -DWC_E_INVALID;
27959 +               val = 0;
27960 +       }
27961 +       core_if->core_params->ic_usb_cap = val;
27962 +       return retval;
27963 +}
27964 +
27965 +int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
27966 +{
27967 +       return core_if->core_params->ic_usb_cap;
27968 +}
27969 +
27970 +int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
27971 +{
27972 +       int retval = 0;
27973 +       int valid = 1;
27974 +
27975 +       if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
27976 +               DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
27977 +               DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
27978 +               return -DWC_E_INVALID;
27979 +       }
27980 +
27981 +       if (val
27982 +           && (core_if->snpsid < OTG_CORE_REV_2_81a
27983 +               || !dwc_otg_get_param_thr_ctl(core_if))) {
27984 +               valid = 0;
27985 +       } else if (val
27986 +                  && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
27987 +                      4)) {
27988 +               valid = 0;
27989 +       }
27990 +       if (valid == 0) {
27991 +               if (dwc_otg_param_initialized
27992 +                   (core_if->core_params->ahb_thr_ratio)) {
27993 +                       DWC_ERROR
27994 +                           ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
27995 +                            val);
27996 +               }
27997 +               retval = -DWC_E_INVALID;
27998 +               val = 0;
27999 +       }
28000 +
28001 +       core_if->core_params->ahb_thr_ratio = val;
28002 +       return retval;
28003 +}
28004 +
28005 +int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
28006 +{
28007 +       return core_if->core_params->ahb_thr_ratio;
28008 +}
28009 +
28010 +int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
28011 +{
28012 +       int retval = 0;
28013 +       int valid = 1;
28014 +       hwcfg4_data_t hwcfg4 = {.d32 = 0 };
28015 +       hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
28016 +
28017 +       if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
28018 +               DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
28019 +               DWC_WARN("power_down must be 0 - 2\n");
28020 +               return -DWC_E_INVALID;
28021 +       }
28022 +
28023 +       if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
28024 +               valid = 0;
28025 +       }
28026 +       if ((val == 3)
28027 +           && ((core_if->snpsid < OTG_CORE_REV_3_00a)
28028 +               || (hwcfg4.b.xhiber == 0))) {
28029 +               valid = 0;
28030 +       }
28031 +       if (valid == 0) {
28032 +               if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
28033 +                       DWC_ERROR
28034 +                           ("%d invalid for parameter power_down. Check HW configuration.\n",
28035 +                            val);
28036 +               }
28037 +               retval = -DWC_E_INVALID;
28038 +               val = 0;
28039 +       }
28040 +       core_if->core_params->power_down = val;
28041 +       return retval;
28042 +}
28043 +
28044 +int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
28045 +{
28046 +       return core_if->core_params->power_down;
28047 +}
28048 +
28049 +int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
28050 +{
28051 +       int retval = 0;
28052 +       int valid = 1;
28053 +
28054 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28055 +               DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
28056 +               DWC_WARN("reload_ctl must be 0 or 1\n");
28057 +               return -DWC_E_INVALID;
28058 +       }
28059 +
28060 +       if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
28061 +               valid = 0;
28062 +       }
28063 +       if (valid == 0) {
28064 +               if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
28065 +                       DWC_ERROR("%d invalid for parameter reload_ctl."
28066 +                                 "Check HW configuration.\n", val);
28067 +               }
28068 +               retval = -DWC_E_INVALID;
28069 +               val = 0;
28070 +       }
28071 +       core_if->core_params->reload_ctl = val;
28072 +       return retval;
28073 +}
28074 +
28075 +int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
28076 +{
28077 +       return core_if->core_params->reload_ctl;
28078 +}
28079 +
28080 +int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
28081 +{
28082 +       int retval = 0;
28083 +       int valid = 1;
28084 +
28085 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28086 +               DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
28087 +               DWC_WARN("dev_out_nak must be 0 or 1\n");
28088 +               return -DWC_E_INVALID;
28089 +       }
28090 +
28091 +       if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
28092 +               !(core_if->core_params->dma_desc_enable))) {
28093 +               valid = 0;
28094 +       }
28095 +       if (valid == 0) {
28096 +               if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
28097 +                       DWC_ERROR("%d invalid for parameter dev_out_nak."
28098 +                               "Check HW configuration.\n", val);
28099 +               }
28100 +               retval = -DWC_E_INVALID;
28101 +               val = 0;
28102 +       }
28103 +       core_if->core_params->dev_out_nak = val;
28104 +       return retval;
28105 +}
28106 +
28107 +int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
28108 +{
28109 +       return core_if->core_params->dev_out_nak;
28110 +}
28111 +
28112 +int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
28113 +{
28114 +       int retval = 0;
28115 +       int valid = 1;
28116 +
28117 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28118 +               DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
28119 +               DWC_WARN("cont_on_bna must be 0 or 1\n");
28120 +               return -DWC_E_INVALID;
28121 +       }
28122 +
28123 +       if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
28124 +               !(core_if->core_params->dma_desc_enable))) {
28125 +                       valid = 0;
28126 +       }
28127 +       if (valid == 0) {
28128 +               if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
28129 +                       DWC_ERROR("%d invalid for parameter cont_on_bna."
28130 +                               "Check HW configuration.\n", val);
28131 +               }
28132 +               retval = -DWC_E_INVALID;
28133 +               val = 0;
28134 +       }
28135 +       core_if->core_params->cont_on_bna = val;
28136 +       return retval;
28137 +}
28138 +
28139 +int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
28140 +{
28141 +       return core_if->core_params->cont_on_bna;
28142 +}
28143 +
28144 +int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
28145 +{
28146 +       int retval = 0;
28147 +       int valid = 1;
28148 +
28149 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28150 +               DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
28151 +               DWC_WARN("ahb_single must be 0 or 1\n");
28152 +               return -DWC_E_INVALID;
28153 +       }
28154 +
28155 +       if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
28156 +                       valid = 0;
28157 +       }
28158 +       if (valid == 0) {
28159 +               if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
28160 +                       DWC_ERROR("%d invalid for parameter ahb_single."
28161 +                               "Check HW configuration.\n", val);
28162 +               }
28163 +               retval = -DWC_E_INVALID;
28164 +               val = 0;
28165 +       }
28166 +       core_if->core_params->ahb_single = val;
28167 +       return retval;
28168 +}
28169 +
28170 +int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
28171 +{
28172 +       return core_if->core_params->ahb_single;
28173 +}
28174 +
28175 +int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
28176 +{
28177 +       int retval = 0;
28178 +
28179 +       if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
28180 +               DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
28181 +               DWC_WARN
28182 +                   ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
28183 +               return -DWC_E_INVALID;
28184 +       }
28185 +
28186 +       core_if->core_params->otg_ver = val;
28187 +       return retval;
28188 +}
28189 +
28190 +int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
28191 +{
28192 +       return core_if->core_params->otg_ver;
28193 +}
28194 +
28195 +uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
28196 +{
28197 +       gotgctl_data_t otgctl;
28198 +       otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28199 +       return otgctl.b.hstnegscs;
28200 +}
28201 +
28202 +uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
28203 +{
28204 +       gotgctl_data_t otgctl;
28205 +       otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28206 +       return otgctl.b.sesreqscs;
28207 +}
28208 +
28209 +void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
28210 +{
28211 +       if(core_if->otg_ver == 0) {
28212 +               gotgctl_data_t otgctl;
28213 +               otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28214 +               otgctl.b.hnpreq = val;
28215 +               DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
28216 +       } else {
28217 +               core_if->otg_sts = val;
28218 +       }
28219 +}
28220 +
28221 +uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
28222 +{
28223 +       return core_if->snpsid;
28224 +}
28225 +
28226 +uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
28227 +{
28228 +       gintsts_data_t gintsts;
28229 +       gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
28230 +       return gintsts.b.curmode;
28231 +}
28232 +
28233 +uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
28234 +{
28235 +       gusbcfg_data_t usbcfg;
28236 +       usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28237 +       return usbcfg.b.hnpcap;
28238 +}
28239 +
28240 +void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
28241 +{
28242 +       gusbcfg_data_t usbcfg;
28243 +       usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28244 +       usbcfg.b.hnpcap = val;
28245 +       DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
28246 +}
28247 +
28248 +uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
28249 +{
28250 +       gusbcfg_data_t usbcfg;
28251 +       usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28252 +       return usbcfg.b.srpcap;
28253 +}
28254 +
28255 +void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
28256 +{
28257 +       gusbcfg_data_t usbcfg;
28258 +       usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28259 +       usbcfg.b.srpcap = val;
28260 +       DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
28261 +}
28262 +
28263 +uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
28264 +{
28265 +       dcfg_data_t dcfg;
28266 +       /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */
28267 +
28268 +        dcfg.d32 = -1; //GRAYG
28269 +        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if);
28270 +        if (NULL == core_if)
28271 +                DWC_ERROR("reg request with NULL core_if\n");
28272 +        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__,
28273 +                    core_if, core_if->dev_if);
28274 +        if (NULL == core_if->dev_if)
28275 +                DWC_ERROR("reg request with NULL dev_if\n");
28276 +        DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->"
28277 +                    "dev_global_regs(%p)\n", __func__,
28278 +                    core_if, core_if->dev_if,
28279 +                    core_if->dev_if->dev_global_regs);
28280 +        if (NULL == core_if->dev_if->dev_global_regs)
28281 +                DWC_ERROR("reg request with NULL dev_global_regs\n");
28282 +        else {
28283 +                DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->"
28284 +                            "dev_global_regs(%p)->dcfg = %p\n", __func__,
28285 +                            core_if, core_if->dev_if,
28286 +                            core_if->dev_if->dev_global_regs,
28287 +                            &core_if->dev_if->dev_global_regs->dcfg);
28288 +               dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
28289 +        }
28290 +       return dcfg.b.devspd;
28291 +}
28292 +
28293 +void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
28294 +{
28295 +       dcfg_data_t dcfg;
28296 +       dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
28297 +       dcfg.b.devspd = val;
28298 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
28299 +}
28300 +
28301 +uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
28302 +{
28303 +       hprt0_data_t hprt0;
28304 +       hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28305 +       return hprt0.b.prtconnsts;
28306 +}
28307 +
28308 +uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
28309 +{
28310 +       dsts_data_t dsts;
28311 +       dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
28312 +       return dsts.b.enumspd;
28313 +}
28314 +
28315 +uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
28316 +{
28317 +       hprt0_data_t hprt0;
28318 +       hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28319 +       return hprt0.b.prtpwr;
28320 +
28321 +}
28322 +
28323 +uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
28324 +{
28325 +       return core_if->hibernation_suspend;
28326 +}
28327 +
28328 +void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
28329 +{
28330 +       hprt0_data_t hprt0;
28331 +       hprt0.d32 = dwc_otg_read_hprt0(core_if);
28332 +       hprt0.b.prtpwr = val;
28333 +       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28334 +}
28335 +
28336 +uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
28337 +{
28338 +       hprt0_data_t hprt0;
28339 +       hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
28340 +       return hprt0.b.prtsusp;
28341 +
28342 +}
28343 +
28344 +void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
28345 +{
28346 +       hprt0_data_t hprt0;
28347 +       hprt0.d32 = dwc_otg_read_hprt0(core_if);
28348 +       hprt0.b.prtsusp = val;
28349 +       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28350 +}
28351 +
28352 +uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
28353 +{
28354 +       hfir_data_t hfir;
28355 +       hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
28356 +       return hfir.b.frint;
28357 +
28358 +}
28359 +
28360 +void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
28361 +{
28362 +       hfir_data_t hfir;
28363 +       uint32_t fram_int;
28364 +       fram_int = calc_frame_interval(core_if);
28365 +       hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
28366 +       if (!core_if->core_params->reload_ctl) {
28367 +               DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
28368 +                        "not set to 1.\nShould load driver with reload_ctl=1"
28369 +                        " module parameter\n");
28370 +               return;
28371 +       }
28372 +       switch (fram_int) {
28373 +       case 3750:
28374 +               if ((val < 3350) || (val > 4150)) {
28375 +                       DWC_WARN("HFIR interval for HS core and 30 MHz"
28376 +                                "clock freq should be from 3350 to 4150\n");
28377 +                       return;
28378 +               }
28379 +               break;
28380 +       case 30000:
28381 +               if ((val < 26820) || (val > 33180)) {
28382 +                       DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
28383 +                                "clock freq should be from 26820 to 33180\n");
28384 +                       return;
28385 +               }
28386 +               break;
28387 +       case 6000:
28388 +               if ((val < 5360) || (val > 6640)) {
28389 +                       DWC_WARN("HFIR interval for HS core and 48 MHz"
28390 +                                "clock freq should be from 5360 to 6640\n");
28391 +                       return;
28392 +               }
28393 +               break;
28394 +       case 48000:
28395 +               if ((val < 42912) || (val > 53088)) {
28396 +                       DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
28397 +                                "clock freq should be from 42912 to 53088\n");
28398 +                       return;
28399 +               }
28400 +               break;
28401 +       case 7500:
28402 +               if ((val < 6700) || (val > 8300)) {
28403 +                       DWC_WARN("HFIR interval for HS core and 60 MHz"
28404 +                                "clock freq should be from 6700 to 8300\n");
28405 +                       return;
28406 +               }
28407 +               break;
28408 +       case 60000:
28409 +               if ((val < 53640) || (val > 65536)) {
28410 +                       DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
28411 +                                "clock freq should be from 53640 to 65536\n");
28412 +                       return;
28413 +               }
28414 +               break;
28415 +       default:
28416 +               DWC_WARN("Unknown frame interval\n");
28417 +               return;
28418 +               break;
28419 +
28420 +       }
28421 +       hfir.b.frint = val;
28422 +       DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
28423 +}
28424 +
28425 +uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
28426 +{
28427 +       hcfg_data_t hcfg;
28428 +       hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
28429 +       return hcfg.b.modechtimen;
28430 +
28431 +}
28432 +
28433 +void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
28434 +{
28435 +       hcfg_data_t hcfg;
28436 +       hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
28437 +       hcfg.b.modechtimen = val;
28438 +       DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
28439 +}
28440 +
28441 +void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
28442 +{
28443 +       hprt0_data_t hprt0;
28444 +       hprt0.d32 = dwc_otg_read_hprt0(core_if);
28445 +       hprt0.b.prtres = val;
28446 +       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
28447 +}
28448 +
28449 +uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
28450 +{
28451 +       dctl_data_t dctl;
28452 +       dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
28453 +       return dctl.b.rmtwkupsig;
28454 +}
28455 +
28456 +uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
28457 +{
28458 +       glpmcfg_data_t lpmcfg;
28459 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28460 +
28461 +       DWC_ASSERT(!
28462 +                  ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
28463 +                  "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
28464 +                  core_if->lx_state, lpmcfg.b.prt_sleep_sts);
28465 +
28466 +       return lpmcfg.b.prt_sleep_sts;
28467 +}
28468 +
28469 +uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
28470 +{
28471 +       glpmcfg_data_t lpmcfg;
28472 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28473 +       return lpmcfg.b.rem_wkup_en;
28474 +}
28475 +
28476 +uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
28477 +{
28478 +       glpmcfg_data_t lpmcfg;
28479 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28480 +       return lpmcfg.b.appl_resp;
28481 +}
28482 +
28483 +void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
28484 +{
28485 +       glpmcfg_data_t lpmcfg;
28486 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28487 +       lpmcfg.b.appl_resp = val;
28488 +       DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28489 +}
28490 +
28491 +uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
28492 +{
28493 +       glpmcfg_data_t lpmcfg;
28494 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28495 +       return lpmcfg.b.hsic_connect;
28496 +}
28497 +
28498 +void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
28499 +{
28500 +       glpmcfg_data_t lpmcfg;
28501 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28502 +       lpmcfg.b.hsic_connect = val;
28503 +       DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28504 +}
28505 +
28506 +uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
28507 +{
28508 +       glpmcfg_data_t lpmcfg;
28509 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28510 +       return lpmcfg.b.inv_sel_hsic;
28511 +
28512 +}
28513 +
28514 +void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
28515 +{
28516 +       glpmcfg_data_t lpmcfg;
28517 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
28518 +       lpmcfg.b.inv_sel_hsic = val;
28519 +       DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
28520 +}
28521 +
28522 +uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
28523 +{
28524 +       return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
28525 +}
28526 +
28527 +void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
28528 +{
28529 +       DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
28530 +}
28531 +
28532 +uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
28533 +{
28534 +       return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
28535 +}
28536 +
28537 +void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
28538 +{
28539 +       DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
28540 +}
28541 +
28542 +uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
28543 +{
28544 +       return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
28545 +}
28546 +
28547 +void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
28548 +{
28549 +       DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
28550 +}
28551 +
28552 +uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
28553 +{
28554 +       return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
28555 +}
28556 +
28557 +void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
28558 +{
28559 +       DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
28560 +}
28561 +
28562 +uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
28563 +{
28564 +       return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
28565 +}
28566 +
28567 +void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
28568 +{
28569 +       DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
28570 +}
28571 +
28572 +uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
28573 +{
28574 +       return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
28575 +}
28576 +
28577 +void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
28578 +{
28579 +       DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
28580 +}
28581 +
28582 +uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
28583 +{
28584 +       return DWC_READ_REG32(core_if->host_if->hprt0);
28585 +
28586 +}
28587 +
28588 +void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
28589 +{
28590 +       DWC_WRITE_REG32(core_if->host_if->hprt0, val);
28591 +}
28592 +
28593 +uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
28594 +{
28595 +       return DWC_READ_REG32(&core_if->core_global_regs->guid);
28596 +}
28597 +
28598 +void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
28599 +{
28600 +       DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
28601 +}
28602 +
28603 +uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
28604 +{
28605 +       return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
28606 +}
28607 +
28608 +uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
28609 +{
28610 +       return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
28611 +}
28612 +
28613 +/**
28614 + * Start the SRP timer to detect when the SRP does not complete within
28615 + * 6 seconds.
28616 + *
28617 + * @param core_if the pointer to core_if strucure.
28618 + */
28619 +void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
28620 +{
28621 +       core_if->srp_timer_started = 1;
28622 +       DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
28623 +}
28624 +
28625 +void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
28626 +{
28627 +       uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
28628 +       gotgctl_data_t mem;
28629 +       gotgctl_data_t val;
28630 +
28631 +       val.d32 = DWC_READ_REG32(addr);
28632 +       if (val.b.sesreq) {
28633 +               DWC_ERROR("Session Request Already active!\n");
28634 +               return;
28635 +       }
28636 +
28637 +       DWC_INFO("Session Request Initated\n"); //NOTICE
28638 +       mem.d32 = DWC_READ_REG32(addr);
28639 +       mem.b.sesreq = 1;
28640 +       DWC_WRITE_REG32(addr, mem.d32);
28641 +
28642 +       /* Start the SRP timer */
28643 +       dwc_otg_pcd_start_srp_timer(core_if);
28644 +       return;
28645 +}
28646 --- /dev/null
28647 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil.h
28648 @@ -0,0 +1,1464 @@
28649 +/* ==========================================================================
28650 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
28651 + * $Revision: #123 $
28652 + * $Date: 2012/08/10 $
28653 + * $Change: 2047372 $
28654 + *
28655 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
28656 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
28657 + * otherwise expressly agreed to in writing between Synopsys and you.
28658 + *
28659 + * The Software IS NOT an item of Licensed Software or Licensed Product under
28660 + * any End User Software License Agreement or Agreement for Licensed Product
28661 + * with Synopsys or any supplement thereto. You are permitted to use and
28662 + * redistribute this Software in source and binary forms, with or without
28663 + * modification, provided that redistributions of source code must retain this
28664 + * notice. You may not view, use, disclose, copy or distribute this file or
28665 + * any information contained herein except pursuant to this license grant from
28666 + * Synopsys. If you do not agree with this notice, including the disclaimer
28667 + * below, then you are not authorized to use the Software.
28668 + *
28669 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
28670 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28671 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28672 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
28673 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28674 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28675 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28676 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28677 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28678 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
28679 + * DAMAGE.
28680 + * ========================================================================== */
28681 +
28682 +#if !defined(__DWC_CIL_H__)
28683 +#define __DWC_CIL_H__
28684 +
28685 +#include "dwc_list.h"
28686 +#include "dwc_otg_dbg.h"
28687 +#include "dwc_otg_regs.h"
28688 +
28689 +#include "dwc_otg_core_if.h"
28690 +#include "dwc_otg_adp.h"
28691 +
28692 +/**
28693 + * @file
28694 + * This file contains the interface to the Core Interface Layer.
28695 + */
28696 +
28697 +#ifdef DWC_UTE_CFI
28698 +
28699 +#define MAX_DMA_DESCS_PER_EP   256
28700 +
28701 +/**
28702 + * Enumeration for the data buffer mode
28703 + */
28704 +typedef enum _data_buffer_mode {
28705 +       BM_STANDARD = 0,        /* data buffer is in normal mode */
28706 +       BM_SG = 1,              /* data buffer uses the scatter/gather mode */
28707 +       BM_CONCAT = 2,          /* data buffer uses the concatenation mode */
28708 +       BM_CIRCULAR = 3,        /* data buffer uses the circular DMA mode */
28709 +       BM_ALIGN = 4            /* data buffer is in buffer alignment mode */
28710 +} data_buffer_mode_e;
28711 +#endif //DWC_UTE_CFI
28712 +
28713 +/** Macros defined for DWC OTG HW Release version */
28714 +
28715 +#define OTG_CORE_REV_2_60a     0x4F54260A
28716 +#define OTG_CORE_REV_2_71a     0x4F54271A
28717 +#define OTG_CORE_REV_2_72a     0x4F54272A
28718 +#define OTG_CORE_REV_2_80a     0x4F54280A
28719 +#define OTG_CORE_REV_2_81a     0x4F54281A
28720 +#define OTG_CORE_REV_2_90a     0x4F54290A
28721 +#define OTG_CORE_REV_2_91a     0x4F54291A
28722 +#define OTG_CORE_REV_2_92a     0x4F54292A
28723 +#define OTG_CORE_REV_2_93a     0x4F54293A
28724 +#define OTG_CORE_REV_2_94a     0x4F54294A
28725 +#define OTG_CORE_REV_3_00a     0x4F54300A
28726 +
28727 +/**
28728 + * Information for each ISOC packet.
28729 + */
28730 +typedef struct iso_pkt_info {
28731 +       uint32_t offset;
28732 +       uint32_t length;
28733 +       int32_t status;
28734 +} iso_pkt_info_t;
28735 +
28736 +/**
28737 + * The <code>dwc_ep</code> structure represents the state of a single
28738 + * endpoint when acting in device mode. It contains the data items
28739 + * needed for an endpoint to be activated and transfer packets.
28740 + */
28741 +typedef struct dwc_ep {
28742 +       /** EP number used for register address lookup */
28743 +       uint8_t num;
28744 +       /** EP direction 0 = OUT */
28745 +       unsigned is_in:1;
28746 +       /** EP active. */
28747 +       unsigned active:1;
28748 +
28749 +       /**
28750 +        * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic
28751 +        * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/
28752 +       unsigned tx_fifo_num:4;
28753 +       /** EP type: 0 - Control, 1 - ISOC,      2 - BULK,      3 - INTR */
28754 +       unsigned type:2;
28755 +#define DWC_OTG_EP_TYPE_CONTROL           0
28756 +#define DWC_OTG_EP_TYPE_ISOC      1
28757 +#define DWC_OTG_EP_TYPE_BULK      2
28758 +#define DWC_OTG_EP_TYPE_INTR      3
28759 +
28760 +       /** DATA start PID for INTR and BULK EP */
28761 +       unsigned data_pid_start:1;
28762 +       /** Frame (even/odd) for ISOC EP */
28763 +       unsigned even_odd_frame:1;
28764 +       /** Max Packet bytes */
28765 +       unsigned maxpacket:11;
28766 +
28767 +       /** Max Transfer size */
28768 +       uint32_t maxxfer;
28769 +
28770 +       /** @name Transfer state */
28771 +       /** @{ */
28772 +
28773 +       /**
28774 +        * Pointer to the beginning of the transfer buffer -- do not modify
28775 +        * during transfer.
28776 +        */
28777 +
28778 +       dwc_dma_t dma_addr;
28779 +
28780 +       dwc_dma_t dma_desc_addr;
28781 +       dwc_otg_dev_dma_desc_t *desc_addr;
28782 +
28783 +       uint8_t *start_xfer_buff;
28784 +       /** pointer to the transfer buffer */
28785 +       uint8_t *xfer_buff;
28786 +       /** Number of bytes to transfer */
28787 +       unsigned xfer_len:19;
28788 +       /** Number of bytes transferred. */
28789 +       unsigned xfer_count:19;
28790 +       /** Sent ZLP */
28791 +       unsigned sent_zlp:1;
28792 +       /** Total len for control transfer */
28793 +       unsigned total_len:19;
28794 +
28795 +       /** stall clear flag */
28796 +       unsigned stall_clear_flag:1;
28797 +
28798 +       /** SETUP pkt cnt rollover flag for EP0 out*/
28799 +       unsigned stp_rollover;
28800 +
28801 +#ifdef DWC_UTE_CFI
28802 +       /* The buffer mode */
28803 +       data_buffer_mode_e buff_mode;
28804 +
28805 +       /* The chain of DMA descriptors.
28806 +        * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
28807 +        */
28808 +       dwc_otg_dma_desc_t *descs;
28809 +
28810 +       /* The DMA address of the descriptors chain start */
28811 +       dma_addr_t descs_dma_addr;
28812 +       /** This variable stores the length of the last enqueued request */
28813 +       uint32_t cfi_req_len;
28814 +#endif                         //DWC_UTE_CFI
28815 +
28816 +/** Max DMA Descriptor count for any EP */
28817 +#define MAX_DMA_DESC_CNT 256
28818 +       /** Allocated DMA Desc count */
28819 +       uint32_t desc_cnt;
28820 +
28821 +       /** bInterval */
28822 +       uint32_t bInterval;
28823 +       /** Next frame num to setup next ISOC transfer */
28824 +       uint32_t frame_num;
28825 +       /** Indicates SOF number overrun in DSTS */
28826 +       uint8_t frm_overrun;
28827 +
28828 +#ifdef DWC_UTE_PER_IO
28829 +       /** Next frame num for which will be setup DMA Desc */
28830 +       uint32_t xiso_frame_num;
28831 +       /** bInterval */
28832 +       uint32_t xiso_bInterval;
28833 +       /** Count of currently active transfers - shall be either 0 or 1 */
28834 +       int xiso_active_xfers;
28835 +       int xiso_queued_xfers;
28836 +#endif
28837 +#ifdef DWC_EN_ISOC
28838 +       /**
28839 +        * Variables specific for ISOC EPs
28840 +        *
28841 +        */
28842 +       /** DMA addresses of ISOC buffers */
28843 +       dwc_dma_t dma_addr0;
28844 +       dwc_dma_t dma_addr1;
28845 +
28846 +       dwc_dma_t iso_dma_desc_addr;
28847 +       dwc_otg_dev_dma_desc_t *iso_desc_addr;
28848 +
28849 +       /** pointer to the transfer buffers */
28850 +       uint8_t *xfer_buff0;
28851 +       uint8_t *xfer_buff1;
28852 +
28853 +       /** number of ISOC Buffer is processing */
28854 +       uint32_t proc_buf_num;
28855 +       /** Interval of ISOC Buffer processing */
28856 +       uint32_t buf_proc_intrvl;
28857 +       /** Data size for regular frame */
28858 +       uint32_t data_per_frame;
28859 +
28860 +       /* todo - pattern data support is to be implemented in the future */
28861 +       /** Data size for pattern frame */
28862 +       uint32_t data_pattern_frame;
28863 +       /** Frame number of pattern data */
28864 +       uint32_t sync_frame;
28865 +
28866 +       /** bInterval */
28867 +       uint32_t bInterval;
28868 +       /** ISO Packet number per frame */
28869 +       uint32_t pkt_per_frm;
28870 +       /** Next frame num for which will be setup DMA Desc */
28871 +       uint32_t next_frame;
28872 +       /** Number of packets per buffer processing */
28873 +       uint32_t pkt_cnt;
28874 +       /** Info for all isoc packets */
28875 +       iso_pkt_info_t *pkt_info;
28876 +       /** current pkt number */
28877 +       uint32_t cur_pkt;
28878 +       /** current pkt number */
28879 +       uint8_t *cur_pkt_addr;
28880 +       /** current pkt number */
28881 +       uint32_t cur_pkt_dma_addr;
28882 +#endif                         /* DWC_EN_ISOC */
28883 +
28884 +/** @} */
28885 +} dwc_ep_t;
28886 +
28887 +/*
28888 + * Reasons for halting a host channel.
28889 + */
28890 +typedef enum dwc_otg_halt_status {
28891 +       DWC_OTG_HC_XFER_NO_HALT_STATUS,
28892 +       DWC_OTG_HC_XFER_COMPLETE,
28893 +       DWC_OTG_HC_XFER_URB_COMPLETE,
28894 +       DWC_OTG_HC_XFER_ACK,
28895 +       DWC_OTG_HC_XFER_NAK,
28896 +       DWC_OTG_HC_XFER_NYET,
28897 +       DWC_OTG_HC_XFER_STALL,
28898 +       DWC_OTG_HC_XFER_XACT_ERR,
28899 +       DWC_OTG_HC_XFER_FRAME_OVERRUN,
28900 +       DWC_OTG_HC_XFER_BABBLE_ERR,
28901 +       DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
28902 +       DWC_OTG_HC_XFER_AHB_ERR,
28903 +       DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
28904 +       DWC_OTG_HC_XFER_URB_DEQUEUE
28905 +} dwc_otg_halt_status_e;
28906 +
28907 +/**
28908 + * Host channel descriptor. This structure represents the state of a single
28909 + * host channel when acting in host mode. It contains the data items needed to
28910 + * transfer packets to an endpoint via a host channel.
28911 + */
28912 +typedef struct dwc_hc {
28913 +       /** Host channel number used for register address lookup */
28914 +       uint8_t hc_num;
28915 +
28916 +       /** Device to access */
28917 +       unsigned dev_addr:7;
28918 +
28919 +       /** EP to access */
28920 +       unsigned ep_num:4;
28921 +
28922 +       /** EP direction. 0: OUT, 1: IN */
28923 +       unsigned ep_is_in:1;
28924 +
28925 +       /**
28926 +        * EP speed.
28927 +        * One of the following values:
28928 +        *      - DWC_OTG_EP_SPEED_LOW
28929 +        *      - DWC_OTG_EP_SPEED_FULL
28930 +        *      - DWC_OTG_EP_SPEED_HIGH
28931 +        */
28932 +       unsigned speed:2;
28933 +#define DWC_OTG_EP_SPEED_LOW   0
28934 +#define DWC_OTG_EP_SPEED_FULL  1
28935 +#define DWC_OTG_EP_SPEED_HIGH  2
28936 +
28937 +       /**
28938 +        * Endpoint type.
28939 +        * One of the following values:
28940 +        *      - DWC_OTG_EP_TYPE_CONTROL: 0
28941 +        *      - DWC_OTG_EP_TYPE_ISOC: 1
28942 +        *      - DWC_OTG_EP_TYPE_BULK: 2
28943 +        *      - DWC_OTG_EP_TYPE_INTR: 3
28944 +        */
28945 +       unsigned ep_type:2;
28946 +
28947 +       /** Max packet size in bytes */
28948 +       unsigned max_packet:11;
28949 +
28950 +       /**
28951 +        * PID for initial transaction.
28952 +        * 0: DATA0,<br>
28953 +        * 1: DATA2,<br>
28954 +        * 2: DATA1,<br>
28955 +        * 3: MDATA (non-Control EP),
28956 +        *        SETUP (Control EP)
28957 +        */
28958 +       unsigned data_pid_start:2;
28959 +#define DWC_OTG_HC_PID_DATA0 0
28960 +#define DWC_OTG_HC_PID_DATA2 1
28961 +#define DWC_OTG_HC_PID_DATA1 2
28962 +#define DWC_OTG_HC_PID_MDATA 3
28963 +#define DWC_OTG_HC_PID_SETUP 3
28964 +
28965 +       /** Number of periodic transactions per (micro)frame */
28966 +       unsigned multi_count:2;
28967 +
28968 +       /** @name Transfer State */
28969 +       /** @{ */
28970 +
28971 +       /** Pointer to the current transfer buffer position. */
28972 +       uint8_t *xfer_buff;
28973 +       /**
28974 +        * In Buffer DMA mode this buffer will be used
28975 +        * if xfer_buff is not DWORD aligned.
28976 +        */
28977 +       dwc_dma_t align_buff;
28978 +       /** Total number of bytes to transfer. */
28979 +       uint32_t xfer_len;
28980 +       /** Number of bytes transferred so far. */
28981 +       uint32_t xfer_count;
28982 +       /** Packet count at start of transfer.*/
28983 +       uint16_t start_pkt_count;
28984 +
28985 +       /**
28986 +        * Flag to indicate whether the transfer has been started. Set to 1 if
28987 +        * it has been started, 0 otherwise.
28988 +        */
28989 +       uint8_t xfer_started;
28990 +
28991 +       /**
28992 +        * Set to 1 to indicate that a PING request should be issued on this
28993 +        * channel. If 0, process normally.
28994 +        */
28995 +       uint8_t do_ping;
28996 +
28997 +       /**
28998 +        * Set to 1 to indicate that the error count for this transaction is
28999 +        * non-zero. Set to 0 if the error count is 0.
29000 +        */
29001 +       uint8_t error_state;
29002 +
29003 +       /**
29004 +        * Set to 1 to indicate that this channel should be halted the next
29005 +        * time a request is queued for the channel. This is necessary in
29006 +        * slave mode if no request queue space is available when an attempt
29007 +        * is made to halt the channel.
29008 +        */
29009 +       uint8_t halt_on_queue;
29010 +
29011 +       /**
29012 +        * Set to 1 if the host channel has been halted, but the core is not
29013 +        * finished flushing queued requests. Otherwise 0.
29014 +        */
29015 +       uint8_t halt_pending;
29016 +
29017 +       /**
29018 +        * Reason for halting the host channel.
29019 +        */
29020 +       dwc_otg_halt_status_e halt_status;
29021 +
29022 +       /*
29023 +        * Split settings for the host channel
29024 +        */
29025 +       uint8_t do_split;                  /**< Enable split for the channel */
29026 +       uint8_t complete_split;    /**< Enable complete split */
29027 +       uint8_t hub_addr;                  /**< Address of high speed hub */
29028 +
29029 +       uint8_t port_addr;                 /**< Port of the low/full speed device */
29030 +       /** Split transaction position
29031 +        * One of the following values:
29032 +        *        - DWC_HCSPLIT_XACTPOS_MID
29033 +        *        - DWC_HCSPLIT_XACTPOS_BEGIN
29034 +        *        - DWC_HCSPLIT_XACTPOS_END
29035 +        *        - DWC_HCSPLIT_XACTPOS_ALL */
29036 +       uint8_t xact_pos;
29037 +
29038 +       /** Set when the host channel does a short read. */
29039 +       uint8_t short_read;
29040 +
29041 +       /**
29042 +        * Number of requests issued for this channel since it was assigned to
29043 +        * the current transfer (not counting PINGs).
29044 +        */
29045 +       uint8_t requests;
29046 +
29047 +       /**
29048 +        * Queue Head for the transfer being processed by this channel.
29049 +        */
29050 +       struct dwc_otg_qh *qh;
29051 +
29052 +       /** @} */
29053 +
29054 +       /** Entry in list of host channels. */
29055 +        DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
29056 +
29057 +       /** @name Descriptor DMA support */
29058 +       /** @{ */
29059 +
29060 +       /** Number of Transfer Descriptors */
29061 +       uint16_t ntd;
29062 +
29063 +       /** Descriptor List DMA address */
29064 +       dwc_dma_t desc_list_addr;
29065 +
29066 +       /** Scheduling micro-frame bitmap. */
29067 +       uint8_t schinfo;
29068 +
29069 +       /** @} */
29070 +} dwc_hc_t;
29071 +
29072 +/**
29073 + * The following parameters may be specified when starting the module. These
29074 + * parameters define how the DWC_otg controller should be configured.
29075 + */
29076 +typedef struct dwc_otg_core_params {
29077 +       int32_t opt;
29078 +
29079 +       /**
29080 +        * Specifies the OTG capabilities. The driver will automatically
29081 +        * detect the value for this parameter if none is specified.
29082 +        * 0 - HNP and SRP capable (default)
29083 +        * 1 - SRP Only capable
29084 +        * 2 - No HNP/SRP capable
29085 +        */
29086 +       int32_t otg_cap;
29087 +
29088 +       /**
29089 +        * Specifies whether to use slave or DMA mode for accessing the data
29090 +        * FIFOs. The driver will automatically detect the value for this
29091 +        * parameter if none is specified.
29092 +        * 0 - Slave
29093 +        * 1 - DMA (default, if available)
29094 +        */
29095 +       int32_t dma_enable;
29096 +
29097 +       /**
29098 +        * When DMA mode is enabled specifies whether to use address DMA or DMA
29099 +        * Descriptor mode for accessing the data FIFOs in device mode. The driver
29100 +        * will automatically detect the value for this if none is specified.
29101 +        * 0 - address DMA
29102 +        * 1 - DMA Descriptor(default, if available)
29103 +        */
29104 +       int32_t dma_desc_enable;
29105 +       /** The DMA Burst size (applicable only for External DMA
29106 +        * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
29107 +        */
29108 +       int32_t dma_burst_size; /* Translate this to GAHBCFG values */
29109 +
29110 +       /**
29111 +        * Specifies the maximum speed of operation in host and device mode.
29112 +        * The actual speed depends on the speed of the attached device and
29113 +        * the value of phy_type. The actual speed depends on the speed of the
29114 +        * attached device.
29115 +        * 0 - High Speed (default)
29116 +        * 1 - Full Speed
29117 +        */
29118 +       int32_t speed;
29119 +       /** Specifies whether low power mode is supported when attached
29120 +        *      to a Full Speed or Low Speed device in host mode.
29121 +        * 0 - Don't support low power mode (default)
29122 +        * 1 - Support low power mode
29123 +        */
29124 +       int32_t host_support_fs_ls_low_power;
29125 +
29126 +       /** Specifies the PHY clock rate in low power mode when connected to a
29127 +        * Low Speed device in host mode. This parameter is applicable only if
29128 +        * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
29129 +        * then defaults to 6 MHZ otherwise 48 MHZ.
29130 +        *
29131 +        * 0 - 48 MHz
29132 +        * 1 - 6 MHz
29133 +        */
29134 +       int32_t host_ls_low_power_phy_clk;
29135 +
29136 +       /**
29137 +        * 0 - Use cC FIFO size parameters
29138 +        * 1 - Allow dynamic FIFO sizing (default)
29139 +        */
29140 +       int32_t enable_dynamic_fifo;
29141 +
29142 +       /** Total number of 4-byte words in the data FIFO memory. This
29143 +        * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
29144 +        * Tx FIFOs.
29145 +        * 32 to 32768 (default 8192)
29146 +        * Note: The total FIFO memory depth in the FPGA configuration is 8192.
29147 +        */
29148 +       int32_t data_fifo_size;
29149 +
29150 +       /** Number of 4-byte words in the Rx FIFO in device mode when dynamic
29151 +        * FIFO sizing is enabled.
29152 +        * 16 to 32768 (default 1064)
29153 +        */
29154 +       int32_t dev_rx_fifo_size;
29155 +
29156 +       /** Number of 4-byte words in the non-periodic Tx FIFO in device mode
29157 +        * when dynamic FIFO sizing is enabled.
29158 +        * 16 to 32768 (default 1024)
29159 +        */
29160 +       int32_t dev_nperio_tx_fifo_size;
29161 +
29162 +       /** Number of 4-byte words in each of the periodic Tx FIFOs in device
29163 +        * mode when dynamic FIFO sizing is enabled.
29164 +        * 4 to 768 (default 256)
29165 +        */
29166 +       uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
29167 +
29168 +       /** Number of 4-byte words in the Rx FIFO in host mode when dynamic
29169 +        * FIFO sizing is enabled.
29170 +        * 16 to 32768 (default 1024)
29171 +        */
29172 +       int32_t host_rx_fifo_size;
29173 +
29174 +       /** Number of 4-byte words in the non-periodic Tx FIFO in host mode
29175 +        * when Dynamic FIFO sizing is enabled in the core.
29176 +        * 16 to 32768 (default 1024)
29177 +        */
29178 +       int32_t host_nperio_tx_fifo_size;
29179 +
29180 +       /** Number of 4-byte words in the host periodic Tx FIFO when dynamic
29181 +        * FIFO sizing is enabled.
29182 +        * 16 to 32768 (default 1024)
29183 +        */
29184 +       int32_t host_perio_tx_fifo_size;
29185 +
29186 +       /** The maximum transfer size supported in bytes.
29187 +        * 2047 to 65,535  (default 65,535)
29188 +        */
29189 +       int32_t max_transfer_size;
29190 +
29191 +       /** The maximum number of packets in a transfer.
29192 +        * 15 to 511  (default 511)
29193 +        */
29194 +       int32_t max_packet_count;
29195 +
29196 +       /** The number of host channel registers to use.
29197 +        * 1 to 16 (default 12)
29198 +        * Note: The FPGA configuration supports a maximum of 12 host channels.
29199 +        */
29200 +       int32_t host_channels;
29201 +
29202 +       /** The number of endpoints in addition to EP0 available for device
29203 +        * mode operations.
29204 +        * 1 to 15 (default 6 IN and OUT)
29205 +        * Note: The FPGA configuration supports a maximum of 6 IN and OUT
29206 +        * endpoints in addition to EP0.
29207 +        */
29208 +       int32_t dev_endpoints;
29209 +
29210 +               /**
29211 +                * Specifies the type of PHY interface to use. By default, the driver
29212 +                * will automatically detect the phy_type.
29213 +                *
29214 +                * 0 - Full Speed PHY
29215 +                * 1 - UTMI+ (default)
29216 +                * 2 - ULPI
29217 +                */
29218 +       int32_t phy_type;
29219 +
29220 +       /**
29221 +        * Specifies the UTMI+ Data Width. This parameter is
29222 +        * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
29223 +        * PHY_TYPE, this parameter indicates the data width between
29224 +        * the MAC and the ULPI Wrapper.) Also, this parameter is
29225 +        * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
29226 +        * to "8 and 16 bits", meaning that the core has been
29227 +        * configured to work at either data path width.
29228 +        *
29229 +        * 8 or 16 bits (default 16)
29230 +        */
29231 +       int32_t phy_utmi_width;
29232 +
29233 +       /**
29234 +        * Specifies whether the ULPI operates at double or single
29235 +        * data rate. This parameter is only applicable if PHY_TYPE is
29236 +        * ULPI.
29237 +        *
29238 +        * 0 - single data rate ULPI interface with 8 bit wide data
29239 +        * bus (default)
29240 +        * 1 - double data rate ULPI interface with 4 bit wide data
29241 +        * bus
29242 +        */
29243 +       int32_t phy_ulpi_ddr;
29244 +
29245 +       /**
29246 +        * Specifies whether to use the internal or external supply to
29247 +        * drive the vbus with a ULPI phy.
29248 +        */
29249 +       int32_t phy_ulpi_ext_vbus;
29250 +
29251 +       /**
29252 +        * Specifies whether to use the I2Cinterface for full speed PHY. This
29253 +        * parameter is only applicable if PHY_TYPE is FS.
29254 +        * 0 - No (default)
29255 +        * 1 - Yes
29256 +        */
29257 +       int32_t i2c_enable;
29258 +
29259 +       int32_t ulpi_fs_ls;
29260 +
29261 +       int32_t ts_dline;
29262 +
29263 +       /**
29264 +        * Specifies whether dedicated transmit FIFOs are
29265 +        * enabled for non periodic IN endpoints in device mode
29266 +        * 0 - No
29267 +        * 1 - Yes
29268 +        */
29269 +       int32_t en_multiple_tx_fifo;
29270 +
29271 +       /** Number of 4-byte words in each of the Tx FIFOs in device
29272 +        * mode when dynamic FIFO sizing is enabled.
29273 +        * 4 to 768 (default 256)
29274 +        */
29275 +       uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
29276 +
29277 +       /** Thresholding enable flag-
29278 +        * bit 0 - enable non-ISO Tx thresholding
29279 +        * bit 1 - enable ISO Tx thresholding
29280 +        * bit 2 - enable Rx thresholding
29281 +        */
29282 +       uint32_t thr_ctl;
29283 +
29284 +       /** Thresholding length for Tx
29285 +        *      FIFOs in 32 bit DWORDs
29286 +        */
29287 +       uint32_t tx_thr_length;
29288 +
29289 +       /** Thresholding length for Rx
29290 +        *      FIFOs in 32 bit DWORDs
29291 +        */
29292 +       uint32_t rx_thr_length;
29293 +
29294 +       /**
29295 +        * Specifies whether LPM (Link Power Management) support is enabled
29296 +        */
29297 +       int32_t lpm_enable;
29298 +
29299 +       /** Per Transfer Interrupt
29300 +        *      mode enable flag
29301 +        * 1 - Enabled
29302 +        * 0 - Disabled
29303 +        */
29304 +       int32_t pti_enable;
29305 +
29306 +       /** Multi Processor Interrupt
29307 +        *      mode enable flag
29308 +        * 1 - Enabled
29309 +        * 0 - Disabled
29310 +        */
29311 +       int32_t mpi_enable;
29312 +
29313 +       /** IS_USB Capability
29314 +        * 1 - Enabled
29315 +        * 0 - Disabled
29316 +        */
29317 +       int32_t ic_usb_cap;
29318 +
29319 +       /** AHB Threshold Ratio
29320 +        * 2'b00 AHB Threshold =        MAC Threshold
29321 +        * 2'b01 AHB Threshold = 1/2    MAC Threshold
29322 +        * 2'b10 AHB Threshold = 1/4    MAC Threshold
29323 +        * 2'b11 AHB Threshold = 1/8    MAC Threshold
29324 +        */
29325 +       int32_t ahb_thr_ratio;
29326 +
29327 +       /** ADP Support
29328 +        * 1 - Enabled
29329 +        * 0 - Disabled
29330 +        */
29331 +       int32_t adp_supp_enable;
29332 +
29333 +       /** HFIR Reload Control
29334 +        * 0 - The HFIR cannot be reloaded dynamically.
29335 +        * 1 - Allow dynamic reloading of the HFIR register during runtime.
29336 +        */
29337 +       int32_t reload_ctl;
29338 +
29339 +       /** DCFG: Enable device Out NAK
29340 +        * 0 - The core does not set NAK after Bulk Out transfer complete.
29341 +        * 1 - The core sets NAK after Bulk OUT transfer complete.
29342 +        */
29343 +       int32_t dev_out_nak;
29344 +
29345 +       /** DCFG: Enable Continue on BNA
29346 +        * After receiving BNA interrupt the core disables the endpoint,when the
29347 +        * endpoint is re-enabled by the application the core starts processing
29348 +        * 0 - from the DOEPDMA descriptor
29349 +        * 1 - from the descriptor which received the BNA.
29350 +        */
29351 +       int32_t cont_on_bna;
29352 +
29353 +       /** GAHBCFG: AHB Single Support
29354 +        * This bit when programmed supports SINGLE transfers for remainder
29355 +        * data in a transfer for DMA mode of operation.
29356 +        * 0 - in this case the remainder data will be sent using INCR burst size.
29357 +        * 1 - in this case the remainder data will be sent using SINGLE burst size.
29358 +        */
29359 +       int32_t ahb_single;
29360 +
29361 +       /** Core Power down mode
29362 +        * 0 - No Power Down is enabled
29363 +        * 1 - Reserved
29364 +        * 2 - Complete Power Down (Hibernation)
29365 +        */
29366 +       int32_t power_down;
29367 +
29368 +       /** OTG revision supported
29369 +        * 0 - OTG 1.3 revision
29370 +        * 1 - OTG 2.0 revision
29371 +        */
29372 +       int32_t otg_ver;
29373 +
29374 +} dwc_otg_core_params_t;
29375 +
29376 +#ifdef DEBUG
29377 +struct dwc_otg_core_if;
29378 +typedef struct hc_xfer_info {
29379 +       struct dwc_otg_core_if *core_if;
29380 +       dwc_hc_t *hc;
29381 +} hc_xfer_info_t;
29382 +#endif
29383 +
29384 +typedef struct ep_xfer_info {
29385 +       struct dwc_otg_core_if *core_if;
29386 +       dwc_ep_t *ep;
29387 +       uint8_t state;
29388 +} ep_xfer_info_t;
29389 +/*
29390 + * Device States
29391 + */
29392 +typedef enum dwc_otg_lx_state {
29393 +       /** On state */
29394 +       DWC_OTG_L0,
29395 +       /** LPM sleep state*/
29396 +       DWC_OTG_L1,
29397 +       /** USB suspend state*/
29398 +       DWC_OTG_L2,
29399 +       /** Off state*/
29400 +       DWC_OTG_L3
29401 +} dwc_otg_lx_state_e;
29402 +
29403 +struct dwc_otg_global_regs_backup {
29404 +       uint32_t gotgctl_local;
29405 +       uint32_t gintmsk_local;
29406 +       uint32_t gahbcfg_local;
29407 +       uint32_t gusbcfg_local;
29408 +       uint32_t grxfsiz_local;
29409 +       uint32_t gnptxfsiz_local;
29410 +#ifdef CONFIG_USB_DWC_OTG_LPM
29411 +       uint32_t glpmcfg_local;
29412 +#endif
29413 +       uint32_t gi2cctl_local;
29414 +       uint32_t hptxfsiz_local;
29415 +       uint32_t pcgcctl_local;
29416 +       uint32_t gdfifocfg_local;
29417 +       uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
29418 +       uint32_t gpwrdn_local;
29419 +       uint32_t xhib_pcgcctl;
29420 +       uint32_t xhib_gpwrdn;
29421 +};
29422 +
29423 +struct dwc_otg_host_regs_backup {
29424 +       uint32_t hcfg_local;
29425 +       uint32_t haintmsk_local;
29426 +       uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
29427 +       uint32_t hprt0_local;
29428 +       uint32_t hfir_local;
29429 +};
29430 +
29431 +struct dwc_otg_dev_regs_backup {
29432 +       uint32_t dcfg;
29433 +       uint32_t dctl;
29434 +       uint32_t daintmsk;
29435 +       uint32_t diepmsk;
29436 +       uint32_t doepmsk;
29437 +       uint32_t diepctl[MAX_EPS_CHANNELS];
29438 +       uint32_t dieptsiz[MAX_EPS_CHANNELS];
29439 +       uint32_t diepdma[MAX_EPS_CHANNELS];
29440 +};
29441 +/**
29442 + * The <code>dwc_otg_core_if</code> structure contains information needed to manage
29443 + * the DWC_otg controller acting in either host or device mode. It
29444 + * represents the programming view of the controller as a whole.
29445 + */
29446 +struct dwc_otg_core_if {
29447 +       /** Parameters that define how the core should be configured.*/
29448 +       dwc_otg_core_params_t *core_params;
29449 +
29450 +       /** Core Global registers starting at offset 000h. */
29451 +       dwc_otg_core_global_regs_t *core_global_regs;
29452 +
29453 +       /** Device-specific information */
29454 +       dwc_otg_dev_if_t *dev_if;
29455 +       /** Host-specific information */
29456 +       dwc_otg_host_if_t *host_if;
29457 +
29458 +       /** Value from SNPSID register */
29459 +       uint32_t snpsid;
29460 +
29461 +       /*
29462 +        * Set to 1 if the core PHY interface bits in USBCFG have been
29463 +        * initialized.
29464 +        */
29465 +       uint8_t phy_init_done;
29466 +
29467 +       /*
29468 +        * SRP Success flag, set by srp success interrupt in FS I2C mode
29469 +        */
29470 +       uint8_t srp_success;
29471 +       uint8_t srp_timer_started;
29472 +       /** Timer for SRP. If it expires before SRP is successful
29473 +        * clear the SRP. */
29474 +       dwc_timer_t *srp_timer;
29475 +
29476 +#ifdef DWC_DEV_SRPCAP
29477 +       /* This timer is needed to power on the hibernated host core if SRP is not
29478 +        * initiated on connected SRP capable device for limited period of time
29479 +        */
29480 +       uint8_t pwron_timer_started;
29481 +       dwc_timer_t *pwron_timer;
29482 +#endif
29483 +       /* Common configuration information */
29484 +       /** Power and Clock Gating Control Register */
29485 +       volatile uint32_t *pcgcctl;
29486 +#define DWC_OTG_PCGCCTL_OFFSET 0xE00
29487 +
29488 +       /** Push/pop addresses for endpoints or host channels.*/
29489 +       uint32_t *data_fifo[MAX_EPS_CHANNELS];
29490 +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000
29491 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000
29492 +
29493 +       /** Total RAM for FIFOs (Bytes) */
29494 +       uint16_t total_fifo_size;
29495 +       /** Size of Rx FIFO (Bytes) */
29496 +       uint16_t rx_fifo_size;
29497 +       /** Size of Non-periodic Tx FIFO (Bytes) */
29498 +       uint16_t nperio_tx_fifo_size;
29499 +
29500 +       /** 1 if DMA is enabled, 0 otherwise. */
29501 +       uint8_t dma_enable;
29502 +
29503 +       /** 1 if DMA descriptor is enabled, 0 otherwise. */
29504 +       uint8_t dma_desc_enable;
29505 +
29506 +       /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */
29507 +       uint8_t pti_enh_enable;
29508 +
29509 +       /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */
29510 +       uint8_t multiproc_int_enable;
29511 +
29512 +       /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */
29513 +       uint8_t en_multiple_tx_fifo;
29514 +
29515 +       /** Set to 1 if multiple packets of a high-bandwidth transfer is in
29516 +        * process of being queued */
29517 +       uint8_t queuing_high_bandwidth;
29518 +
29519 +       /** Hardware Configuration -- stored here for convenience.*/
29520 +       hwcfg1_data_t hwcfg1;
29521 +       hwcfg2_data_t hwcfg2;
29522 +       hwcfg3_data_t hwcfg3;
29523 +       hwcfg4_data_t hwcfg4;
29524 +       fifosize_data_t hptxfsiz;
29525 +
29526 +       /** Host and Device Configuration -- stored here for convenience.*/
29527 +       hcfg_data_t hcfg;
29528 +       dcfg_data_t dcfg;
29529 +
29530 +       /** The operational State, during transations
29531 +        * (a_host>>a_peripherial and b_device=>b_host) this may not
29532 +        * match the core but allows the software to determine
29533 +        * transitions.
29534 +        */
29535 +       uint8_t op_state;
29536 +
29537 +       /**
29538 +        * Set to 1 if the HCD needs to be restarted on a session request
29539 +        * interrupt. This is required if no connector ID status change has
29540 +        * occurred since the HCD was last disconnected.
29541 +        */
29542 +       uint8_t restart_hcd_on_session_req;
29543 +
29544 +       /** HCD callbacks */
29545 +       /** A-Device is a_host */
29546 +#define A_HOST         (1)
29547 +       /** A-Device is a_suspend */
29548 +#define A_SUSPEND      (2)
29549 +       /** A-Device is a_peripherial */
29550 +#define A_PERIPHERAL   (3)
29551 +       /** B-Device is operating as a Peripheral. */
29552 +#define B_PERIPHERAL   (4)
29553 +       /** B-Device is operating as a Host. */
29554 +#define B_HOST         (5)
29555 +
29556 +       /** HCD callbacks */
29557 +       struct dwc_otg_cil_callbacks *hcd_cb;
29558 +       /** PCD callbacks */
29559 +       struct dwc_otg_cil_callbacks *pcd_cb;
29560 +
29561 +       /** Device mode Periodic Tx FIFO Mask */
29562 +       uint32_t p_tx_msk;
29563 +       /** Device mode Periodic Tx FIFO Mask */
29564 +       uint32_t tx_msk;
29565 +
29566 +       /** Workqueue object used for handling several interrupts */
29567 +       dwc_workq_t *wq_otg;
29568 +
29569 +       /** Timer object used for handling "Wakeup Detected" Interrupt */
29570 +       dwc_timer_t *wkp_timer;
29571 +       /** This arrays used for debug purposes for DEV OUT NAK enhancement */
29572 +       uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
29573 +       ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
29574 +       dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
29575 +#ifdef DEBUG
29576 +       uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
29577 +
29578 +       hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
29579 +       dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
29580 +
29581 +       uint32_t hfnum_7_samples;
29582 +       uint64_t hfnum_7_frrem_accum;
29583 +       uint32_t hfnum_0_samples;
29584 +       uint64_t hfnum_0_frrem_accum;
29585 +       uint32_t hfnum_other_samples;
29586 +       uint64_t hfnum_other_frrem_accum;
29587 +#endif
29588 +
29589 +#ifdef DWC_UTE_CFI
29590 +       uint16_t pwron_rxfsiz;
29591 +       uint16_t pwron_gnptxfsiz;
29592 +       uint16_t pwron_txfsiz[15];
29593 +
29594 +       uint16_t init_rxfsiz;
29595 +       uint16_t init_gnptxfsiz;
29596 +       uint16_t init_txfsiz[15];
29597 +#endif
29598 +
29599 +       /** Lx state of device */
29600 +       dwc_otg_lx_state_e lx_state;
29601 +
29602 +       /** Saved Core Global registers */
29603 +       struct dwc_otg_global_regs_backup *gr_backup;
29604 +       /** Saved Host registers */
29605 +       struct dwc_otg_host_regs_backup *hr_backup;
29606 +       /** Saved Device registers */
29607 +       struct dwc_otg_dev_regs_backup *dr_backup;
29608 +
29609 +       /** Power Down Enable */
29610 +       uint32_t power_down;
29611 +
29612 +       /** ADP support Enable */
29613 +       uint32_t adp_enable;
29614 +
29615 +       /** ADP structure object */
29616 +       dwc_otg_adp_t adp;
29617 +
29618 +       /** hibernation/suspend flag */
29619 +       int hibernation_suspend;
29620 +
29621 +       /** Device mode extended hibernation flag */
29622 +       int xhib;
29623 +
29624 +       /** OTG revision supported */
29625 +       uint32_t otg_ver;
29626 +
29627 +       /** OTG status flag used for HNP polling */
29628 +       uint8_t otg_sts;
29629 +
29630 +       /** Pointer to either hcd->lock or pcd->lock */
29631 +       dwc_spinlock_t *lock;
29632 +
29633 +       /** Start predict NextEP based on Learning Queue if equal 1,
29634 +        * also used as counter of disabled NP IN EP's */
29635 +       uint8_t start_predict;
29636 +
29637 +       /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and
29638 +        * active, 0xff otherwise */
29639 +       uint8_t nextep_seq[MAX_EPS_CHANNELS];
29640 +
29641 +       /** Index of fisrt EP in nextep_seq array which should be re-enabled **/
29642 +       uint8_t first_in_nextep_seq;
29643 +
29644 +       /** Frame number while entering to ISR - needed for ISOCs **/
29645 +       uint32_t frame_num;
29646 +
29647 +};
29648 +
29649 +#ifdef DEBUG
29650 +/*
29651 + * This function is called when transfer is timed out.
29652 + */
29653 +extern void hc_xfer_timeout(void *ptr);
29654 +#endif
29655 +
29656 +/*
29657 + * This function is called when transfer is timed out on endpoint.
29658 + */
29659 +extern void ep_xfer_timeout(void *ptr);
29660 +
29661 +/*
29662 + * The following functions are functions for works
29663 + * using during handling some interrupts
29664 + */
29665 +extern void w_conn_id_status_change(void *p);
29666 +
29667 +extern void w_wakeup_detected(void *p);
29668 +
29669 +/** Saves global register values into system memory. */
29670 +extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
29671 +/** Saves device register values into system memory. */
29672 +extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
29673 +/** Saves host register values into system memory. */
29674 +extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
29675 +/** Restore global register values. */
29676 +extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
29677 +/** Restore host register values. */
29678 +extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
29679 +/** Restore device register values. */
29680 +extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
29681 +                                   int rem_wakeup);
29682 +extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
29683 +extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
29684 +                                 int is_host);
29685 +
29686 +extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
29687 +                                           int restore_mode, int reset);
29688 +extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
29689 +                                             int rem_wakeup, int reset);
29690 +
29691 +/*
29692 + * The following functions support initialization of the CIL driver component
29693 + * and the DWC_otg controller.
29694 + */
29695 +extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
29696 +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
29697 +
29698 +/** @name Device CIL Functions
29699 + * The following functions support managing the DWC_otg controller in device
29700 + * mode.
29701 + */
29702 +/**@{*/
29703 +extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
29704 +extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
29705 +                                     uint32_t * _dest);
29706 +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
29707 +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29708 +extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29709 +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29710 +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
29711 +                                     dwc_ep_t * _ep);
29712 +extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
29713 +                                        dwc_ep_t * _ep);
29714 +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
29715 +                                      dwc_ep_t * _ep);
29716 +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
29717 +                                         dwc_ep_t * _ep);
29718 +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
29719 +                                   dwc_ep_t * _ep, int _dma);
29720 +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
29721 +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
29722 +                                  dwc_ep_t * _ep);
29723 +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
29724 +
29725 +#ifdef DWC_EN_ISOC
29726 +extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
29727 +                                             dwc_ep_t * ep);
29728 +extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
29729 +                                             dwc_ep_t * ep);
29730 +#endif /* DWC_EN_ISOC */
29731 +/**@}*/
29732 +
29733 +/** @name Host CIL Functions
29734 + * The following functions support managing the DWC_otg controller in host
29735 + * mode.
29736 + */
29737 +/**@{*/
29738 +extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29739 +extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
29740 +                           dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
29741 +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29742 +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
29743 +                                     dwc_hc_t * _hc);
29744 +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
29745 +                                       dwc_hc_t * _hc);
29746 +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
29747 +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
29748 +                                   dwc_hc_t * _hc);
29749 +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
29750 +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
29751 +
29752 +extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
29753 +                                          dwc_hc_t * hc);
29754 +
29755 +extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
29756 +
29757 +/* Macro used to clear one channel interrupt */
29758 +#define clear_hc_int(_hc_regs_, _intr_) \
29759 +do { \
29760 +       hcint_data_t hcint_clear = {.d32 = 0}; \
29761 +       hcint_clear.b._intr_ = 1; \
29762 +       DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
29763 +} while (0)
29764 +
29765 +/*
29766 + * Macro used to disable one channel interrupt. Channel interrupts are
29767 + * disabled when the channel is halted or released by the interrupt handler.
29768 + * There is no need to handle further interrupts of that type until the
29769 + * channel is re-assigned. In fact, subsequent handling may cause crashes
29770 + * because the channel structures are cleaned up when the channel is released.
29771 + */
29772 +#define disable_hc_int(_hc_regs_, _intr_) \
29773 +do { \
29774 +       hcintmsk_data_t hcintmsk = {.d32 = 0}; \
29775 +       hcintmsk.b._intr_ = 1; \
29776 +       DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
29777 +} while (0)
29778 +
29779 +/**
29780 + * This function Reads HPRT0 in preparation to modify. It keeps the
29781 + * WC bits 0 so that if they are read as 1, they won't clear when you
29782 + * write it back
29783 + */
29784 +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
29785 +{
29786 +       hprt0_data_t hprt0;
29787 +       hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
29788 +       hprt0.b.prtena = 0;
29789 +       hprt0.b.prtconndet = 0;
29790 +       hprt0.b.prtenchng = 0;
29791 +       hprt0.b.prtovrcurrchng = 0;
29792 +       return hprt0.d32;
29793 +}
29794 +
29795 +/**@}*/
29796 +
29797 +/** @name Common CIL Functions
29798 + * The following functions support managing the DWC_otg controller in either
29799 + * device or host mode.
29800 + */
29801 +/**@{*/
29802 +
29803 +extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
29804 +                               uint8_t * dest, uint16_t bytes);
29805 +
29806 +extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
29807 +extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
29808 +extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
29809 +
29810 +/**
29811 + * This function returns the Core Interrupt register.
29812 + */
29813 +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
29814 +{
29815 +       return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
29816 +               DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
29817 +}
29818 +
29819 +/**
29820 + * This function returns the OTG Interrupt register.
29821 + */
29822 +static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
29823 +{
29824 +       return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
29825 +}
29826 +
29827 +/**
29828 + * This function reads the Device All Endpoints Interrupt register and
29829 + * returns the IN endpoint interrupt bits.
29830 + */
29831 +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
29832 +                                                      core_if)
29833 +{
29834 +
29835 +       uint32_t v;
29836 +
29837 +       if (core_if->multiproc_int_enable) {
29838 +               v = DWC_READ_REG32(&core_if->dev_if->
29839 +                                  dev_global_regs->deachint) &
29840 +                   DWC_READ_REG32(&core_if->
29841 +                                  dev_if->dev_global_regs->deachintmsk);
29842 +       } else {
29843 +               v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
29844 +                   DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
29845 +       }
29846 +       return (v & 0xffff);
29847 +}
29848 +
29849 +/**
29850 + * This function reads the Device All Endpoints Interrupt register and
29851 + * returns the OUT endpoint interrupt bits.
29852 + */
29853 +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
29854 +                                                       core_if)
29855 +{
29856 +       uint32_t v;
29857 +
29858 +       if (core_if->multiproc_int_enable) {
29859 +               v = DWC_READ_REG32(&core_if->dev_if->
29860 +                                  dev_global_regs->deachint) &
29861 +                   DWC_READ_REG32(&core_if->
29862 +                                  dev_if->dev_global_regs->deachintmsk);
29863 +       } else {
29864 +               v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
29865 +                   DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
29866 +       }
29867 +
29868 +       return ((v & 0xffff0000) >> 16);
29869 +}
29870 +
29871 +/**
29872 + * This function returns the Device IN EP Interrupt register
29873 + */
29874 +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
29875 +                                                  dwc_ep_t * ep)
29876 +{
29877 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
29878 +       uint32_t v, msk, emp;
29879 +
29880 +       if (core_if->multiproc_int_enable) {
29881 +               msk =
29882 +                   DWC_READ_REG32(&dev_if->
29883 +                                  dev_global_regs->diepeachintmsk[ep->num]);
29884 +               emp =
29885 +                   DWC_READ_REG32(&dev_if->
29886 +                                  dev_global_regs->dtknqr4_fifoemptymsk);
29887 +               msk |= ((emp >> ep->num) & 0x1) << 7;
29888 +               v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
29889 +       } else {
29890 +               msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
29891 +               emp =
29892 +                   DWC_READ_REG32(&dev_if->
29893 +                                  dev_global_regs->dtknqr4_fifoemptymsk);
29894 +               msk |= ((emp >> ep->num) & 0x1) << 7;
29895 +               v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
29896 +       }
29897 +
29898 +       return v;
29899 +}
29900 +
29901 +/**
29902 + * This function returns the Device OUT EP Interrupt register
29903 + */
29904 +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
29905 +                                                   _core_if, dwc_ep_t * _ep)
29906 +{
29907 +       dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
29908 +       uint32_t v;
29909 +       doepmsk_data_t msk = {.d32 = 0 };
29910 +
29911 +       if (_core_if->multiproc_int_enable) {
29912 +               msk.d32 =
29913 +                   DWC_READ_REG32(&dev_if->
29914 +                                  dev_global_regs->doepeachintmsk[_ep->num]);
29915 +               if (_core_if->pti_enh_enable) {
29916 +                       msk.b.pktdrpsts = 1;
29917 +               }
29918 +               v = DWC_READ_REG32(&dev_if->
29919 +                                  out_ep_regs[_ep->num]->doepint) & msk.d32;
29920 +       } else {
29921 +               msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
29922 +               if (_core_if->pti_enh_enable) {
29923 +                       msk.b.pktdrpsts = 1;
29924 +               }
29925 +               v = DWC_READ_REG32(&dev_if->
29926 +                                  out_ep_regs[_ep->num]->doepint) & msk.d32;
29927 +       }
29928 +       return v;
29929 +}
29930 +
29931 +/**
29932 + * This function returns the Host All Channel Interrupt register
29933 + */
29934 +static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
29935 +                                                          _core_if)
29936 +{
29937 +       return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
29938 +}
29939 +
29940 +static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
29941 +                                                     _core_if, dwc_hc_t * _hc)
29942 +{
29943 +       return (DWC_READ_REG32
29944 +               (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
29945 +}
29946 +
29947 +/**
29948 + * This function returns the mode of the operation, host or device.
29949 + *
29950 + * @return 0 - Device Mode, 1 - Host Mode
29951 + */
29952 +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
29953 +{
29954 +       return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
29955 +}
29956 +
29957 +/**@}*/
29958 +
29959 +/**
29960 + * DWC_otg CIL callback structure. This structure allows the HCD and
29961 + * PCD to register functions used for starting and stopping the PCD
29962 + * and HCD for role change on for a DRD.
29963 + */
29964 +typedef struct dwc_otg_cil_callbacks {
29965 +       /** Start function for role change */
29966 +       int (*start) (void *_p);
29967 +       /** Stop Function for role change */
29968 +       int (*stop) (void *_p);
29969 +       /** Disconnect Function for role change */
29970 +       int (*disconnect) (void *_p);
29971 +       /** Resume/Remote wakeup Function */
29972 +       int (*resume_wakeup) (void *_p);
29973 +       /** Suspend function */
29974 +       int (*suspend) (void *_p);
29975 +       /** Session Start (SRP) */
29976 +       int (*session_start) (void *_p);
29977 +#ifdef CONFIG_USB_DWC_OTG_LPM
29978 +       /** Sleep (switch to L0 state) */
29979 +       int (*sleep) (void *_p);
29980 +#endif
29981 +       /** Pointer passed to start() and stop() */
29982 +       void *p;
29983 +} dwc_otg_cil_callbacks_t;
29984 +
29985 +extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
29986 +                                              dwc_otg_cil_callbacks_t * _cb,
29987 +                                              void *_p);
29988 +extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
29989 +                                              dwc_otg_cil_callbacks_t * _cb,
29990 +                                              void *_p);
29991 +
29992 +void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
29993 +
29994 +//////////////////////////////////////////////////////////////////////
29995 +/** Start the HCD.  Helper function for using the HCD callbacks.
29996 + *
29997 + * @param core_if Programming view of DWC_otg controller.
29998 + */
29999 +static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
30000 +{
30001 +       if (core_if->hcd_cb && core_if->hcd_cb->start) {
30002 +               core_if->hcd_cb->start(core_if->hcd_cb->p);
30003 +       }
30004 +}
30005 +
30006 +/** Stop the HCD.  Helper function for using the HCD callbacks.
30007 + *
30008 + * @param core_if Programming view of DWC_otg controller.
30009 + */
30010 +static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
30011 +{
30012 +       if (core_if->hcd_cb && core_if->hcd_cb->stop) {
30013 +               core_if->hcd_cb->stop(core_if->hcd_cb->p);
30014 +       }
30015 +}
30016 +
30017 +/** Disconnect the HCD.  Helper function for using the HCD callbacks.
30018 + *
30019 + * @param core_if Programming view of DWC_otg controller.
30020 + */
30021 +static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
30022 +{
30023 +       if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
30024 +               core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
30025 +       }
30026 +}
30027 +
30028 +/** Inform the HCD the a New Session has begun.  Helper function for
30029 + * using the HCD callbacks.
30030 + *
30031 + * @param core_if Programming view of DWC_otg controller.
30032 + */
30033 +static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
30034 +{
30035 +       if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
30036 +               core_if->hcd_cb->session_start(core_if->hcd_cb->p);
30037 +       }
30038 +}
30039 +
30040 +#ifdef CONFIG_USB_DWC_OTG_LPM
30041 +/**
30042 + * Inform the HCD about LPM sleep.
30043 + * Helper function for using the HCD callbacks.
30044 + *
30045 + * @param core_if Programming view of DWC_otg controller.
30046 + */
30047 +static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
30048 +{
30049 +       if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
30050 +               core_if->hcd_cb->sleep(core_if->hcd_cb->p);
30051 +       }
30052 +}
30053 +#endif
30054 +
30055 +/** Resume the HCD.  Helper function for using the HCD callbacks.
30056 + *
30057 + * @param core_if Programming view of DWC_otg controller.
30058 + */
30059 +static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
30060 +{
30061 +       if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
30062 +               core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
30063 +       }
30064 +}
30065 +
30066 +/** Start the PCD.  Helper function for using the PCD callbacks.
30067 + *
30068 + * @param core_if Programming view of DWC_otg controller.
30069 + */
30070 +static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
30071 +{
30072 +       if (core_if->pcd_cb && core_if->pcd_cb->start) {
30073 +               core_if->pcd_cb->start(core_if->pcd_cb->p);
30074 +       }
30075 +}
30076 +
30077 +/** Stop the PCD.  Helper function for using the PCD callbacks.
30078 + *
30079 + * @param core_if Programming view of DWC_otg controller.
30080 + */
30081 +static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
30082 +{
30083 +       if (core_if->pcd_cb && core_if->pcd_cb->stop) {
30084 +               core_if->pcd_cb->stop(core_if->pcd_cb->p);
30085 +       }
30086 +}
30087 +
30088 +/** Suspend the PCD.  Helper function for using the PCD callbacks.
30089 + *
30090 + * @param core_if Programming view of DWC_otg controller.
30091 + */
30092 +static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
30093 +{
30094 +       if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
30095 +               core_if->pcd_cb->suspend(core_if->pcd_cb->p);
30096 +       }
30097 +}
30098 +
30099 +/** Resume the PCD.  Helper function for using the PCD callbacks.
30100 + *
30101 + * @param core_if Programming view of DWC_otg controller.
30102 + */
30103 +static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
30104 +{
30105 +       if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
30106 +               core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
30107 +       }
30108 +}
30109 +
30110 +//////////////////////////////////////////////////////////////////////
30111 +
30112 +#endif
30113 --- /dev/null
30114 +++ b/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c
30115 @@ -0,0 +1,1594 @@
30116 +/* ==========================================================================
30117 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
30118 + * $Revision: #32 $
30119 + * $Date: 2012/08/10 $
30120 + * $Change: 2047372 $
30121 + *
30122 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
30123 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
30124 + * otherwise expressly agreed to in writing between Synopsys and you.
30125 + *
30126 + * The Software IS NOT an item of Licensed Software or Licensed Product under
30127 + * any End User Software License Agreement or Agreement for Licensed Product
30128 + * with Synopsys or any supplement thereto. You are permitted to use and
30129 + * redistribute this Software in source and binary forms, with or without
30130 + * modification, provided that redistributions of source code must retain this
30131 + * notice. You may not view, use, disclose, copy or distribute this file or
30132 + * any information contained herein except pursuant to this license grant from
30133 + * Synopsys. If you do not agree with this notice, including the disclaimer
30134 + * below, then you are not authorized to use the Software.
30135 + *
30136 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
30137 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30138 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30139 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
30140 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30141 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30142 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
30143 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30144 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30145 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
30146 + * DAMAGE.
30147 + * ========================================================================== */
30148 +
30149 +/** @file
30150 + *
30151 + * The Core Interface Layer provides basic services for accessing and
30152 + * managing the DWC_otg hardware. These services are used by both the
30153 + * Host Controller Driver and the Peripheral Controller Driver.
30154 + *
30155 + * This file contains the Common Interrupt handlers.
30156 + */
30157 +#include "dwc_os.h"
30158 +#include "dwc_otg_regs.h"
30159 +#include "dwc_otg_cil.h"
30160 +#include "dwc_otg_driver.h"
30161 +#include "dwc_otg_pcd.h"
30162 +#include "dwc_otg_hcd.h"
30163 +
30164 +#ifdef DEBUG
30165 +inline const char *op_state_str(dwc_otg_core_if_t * core_if)
30166 +{
30167 +       return (core_if->op_state == A_HOST ? "a_host" :
30168 +               (core_if->op_state == A_SUSPEND ? "a_suspend" :
30169 +                (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
30170 +                 (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
30171 +                  (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
30172 +}
30173 +#endif
30174 +
30175 +/** This function will log a debug message
30176 + *
30177 + * @param core_if Programming view of DWC_otg controller.
30178 + */
30179 +int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
30180 +{
30181 +       gintsts_data_t gintsts;
30182 +       DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
30183 +                dwc_otg_mode(core_if) ? "Host" : "Device");
30184 +
30185 +       /* Clear interrupt */
30186 +       gintsts.d32 = 0;
30187 +       gintsts.b.modemismatch = 1;
30188 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30189 +       return 1;
30190 +}
30191 +
30192 +/**
30193 + * This function handles the OTG Interrupts. It reads the OTG
30194 + * Interrupt Register (GOTGINT) to determine what interrupt has
30195 + * occurred.
30196 + *
30197 + * @param core_if Programming view of DWC_otg controller.
30198 + */
30199 +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
30200 +{
30201 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
30202 +       gotgint_data_t gotgint;
30203 +       gotgctl_data_t gotgctl;
30204 +       gintmsk_data_t gintmsk;
30205 +       gpwrdn_data_t gpwrdn;
30206 +
30207 +       gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
30208 +       gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30209 +       DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
30210 +                   op_state_str(core_if));
30211 +
30212 +       if (gotgint.b.sesenddet) {
30213 +               DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30214 +                           "Session End Detected++ (%s)\n",
30215 +                           op_state_str(core_if));
30216 +               gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30217 +
30218 +               if (core_if->op_state == B_HOST) {
30219 +                       cil_pcd_start(core_if);
30220 +                       core_if->op_state = B_PERIPHERAL;
30221 +               } else {
30222 +                       /* If not B_HOST and Device HNP still set. HNP
30223 +                        * Did not succeed!*/
30224 +                       if (gotgctl.b.devhnpen) {
30225 +                               DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
30226 +                               __DWC_ERROR("Device Not Connected/Responding!\n");
30227 +                       }
30228 +
30229 +                       /* If Session End Detected the B-Cable has
30230 +                        * been disconnected. */
30231 +                       /* Reset PCD and Gadget driver to a
30232 +                        * clean state. */
30233 +                       core_if->lx_state = DWC_OTG_L0;
30234 +                       DWC_SPINUNLOCK(core_if->lock);
30235 +                       cil_pcd_stop(core_if);
30236 +                       DWC_SPINLOCK(core_if->lock);
30237 +
30238 +                       if (core_if->adp_enable) {
30239 +                               if (core_if->power_down == 2) {
30240 +                                       gpwrdn.d32 = 0;
30241 +                                       gpwrdn.b.pwrdnswtch = 1;
30242 +                                       DWC_MODIFY_REG32(&core_if->
30243 +                                                        core_global_regs->
30244 +                                                        gpwrdn, gpwrdn.d32, 0);
30245 +                               }
30246 +
30247 +                               gpwrdn.d32 = 0;
30248 +                               gpwrdn.b.pmuintsel = 1;
30249 +                               gpwrdn.b.pmuactv = 1;
30250 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
30251 +                                                gpwrdn, 0, gpwrdn.d32);
30252 +
30253 +                               dwc_otg_adp_sense_start(core_if);
30254 +                       }
30255 +               }
30256 +
30257 +               gotgctl.d32 = 0;
30258 +               gotgctl.b.devhnpen = 1;
30259 +               DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
30260 +       }
30261 +       if (gotgint.b.sesreqsucstschng) {
30262 +               DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30263 +                           "Session Reqeust Success Status Change++\n");
30264 +               gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30265 +               if (gotgctl.b.sesreqscs) {
30266 +
30267 +                       if ((core_if->core_params->phy_type ==
30268 +                            DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
30269 +                               core_if->srp_success = 1;
30270 +                       } else {
30271 +                               DWC_SPINUNLOCK(core_if->lock);
30272 +                               cil_pcd_resume(core_if);
30273 +                               DWC_SPINLOCK(core_if->lock);
30274 +                               /* Clear Session Request */
30275 +                               gotgctl.d32 = 0;
30276 +                               gotgctl.b.sesreq = 1;
30277 +                               DWC_MODIFY_REG32(&global_regs->gotgctl,
30278 +                                                gotgctl.d32, 0);
30279 +                       }
30280 +               }
30281 +       }
30282 +       if (gotgint.b.hstnegsucstschng) {
30283 +               /* Print statements during the HNP interrupt handling
30284 +                * can cause it to fail.*/
30285 +               gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
30286 +               /* WA for 3.00a- HW is not setting cur_mode, even sometimes
30287 +                * this does not help*/
30288 +               if (core_if->snpsid >= OTG_CORE_REV_3_00a)
30289 +                       dwc_udelay(100);
30290 +               if (gotgctl.b.hstnegscs) {
30291 +                       if (dwc_otg_is_host_mode(core_if)) {
30292 +                               core_if->op_state = B_HOST;
30293 +                               /*
30294 +                                * Need to disable SOF interrupt immediately.
30295 +                                * When switching from device to host, the PCD
30296 +                                * interrupt handler won't handle the
30297 +                                * interrupt if host mode is already set. The
30298 +                                * HCD interrupt handler won't get called if
30299 +                                * the HCD state is HALT. This means that the
30300 +                                * interrupt does not get handled and Linux
30301 +                                * complains loudly.
30302 +                                */
30303 +                               gintmsk.d32 = 0;
30304 +                               gintmsk.b.sofintr = 1;
30305 +                               DWC_MODIFY_REG32(&global_regs->gintmsk,
30306 +                                                gintmsk.d32, 0);
30307 +                               /* Call callback function with spin lock released */
30308 +                               DWC_SPINUNLOCK(core_if->lock);
30309 +                               cil_pcd_stop(core_if);
30310 +                               /*
30311 +                                * Initialize the Core for Host mode.
30312 +                                */
30313 +                               cil_hcd_start(core_if);
30314 +                               DWC_SPINLOCK(core_if->lock);
30315 +                               core_if->op_state = B_HOST;
30316 +                       }
30317 +               } else {
30318 +                       gotgctl.d32 = 0;
30319 +                       gotgctl.b.hnpreq = 1;
30320 +                       gotgctl.b.devhnpen = 1;
30321 +                       DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
30322 +                       DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
30323 +                       __DWC_ERROR("Device Not Connected/Responding\n");
30324 +               }
30325 +       }
30326 +       if (gotgint.b.hstnegdet) {
30327 +               /* The disconnect interrupt is set at the same time as
30328 +                * Host Negotiation Detected.  During the mode
30329 +                * switch all interrupts are cleared so the disconnect
30330 +                * interrupt handler will not get executed.
30331 +                */
30332 +               DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30333 +                           "Host Negotiation Detected++ (%s)\n",
30334 +                           (dwc_otg_is_host_mode(core_if) ? "Host" :
30335 +                            "Device"));
30336 +               if (dwc_otg_is_device_mode(core_if)) {
30337 +                       DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
30338 +                                   core_if->op_state);
30339 +                       DWC_SPINUNLOCK(core_if->lock);
30340 +                       cil_hcd_disconnect(core_if);
30341 +                       cil_pcd_start(core_if);
30342 +                       DWC_SPINLOCK(core_if->lock);
30343 +                       core_if->op_state = A_PERIPHERAL;
30344 +               } else {
30345 +                       /*
30346 +                        * Need to disable SOF interrupt immediately. When
30347 +                        * switching from device to host, the PCD interrupt
30348 +                        * handler won't handle the interrupt if host mode is
30349 +                        * already set. The HCD interrupt handler won't get
30350 +                        * called if the HCD state is HALT. This means that
30351 +                        * the interrupt does not get handled and Linux
30352 +                        * complains loudly.
30353 +                        */
30354 +                       gintmsk.d32 = 0;
30355 +                       gintmsk.b.sofintr = 1;
30356 +                       DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
30357 +                       DWC_SPINUNLOCK(core_if->lock);
30358 +                       cil_pcd_stop(core_if);
30359 +                       cil_hcd_start(core_if);
30360 +                       DWC_SPINLOCK(core_if->lock);
30361 +                       core_if->op_state = A_HOST;
30362 +               }
30363 +       }
30364 +       if (gotgint.b.adevtoutchng) {
30365 +               DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
30366 +                           "A-Device Timeout Change++\n");
30367 +       }
30368 +       if (gotgint.b.debdone) {
30369 +               DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
30370 +       }
30371 +
30372 +       /* Clear GOTGINT */
30373 +       DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
30374 +
30375 +       return 1;
30376 +}
30377 +
30378 +void w_conn_id_status_change(void *p)
30379 +{
30380 +       dwc_otg_core_if_t *core_if = p;
30381 +       uint32_t count = 0;
30382 +       gotgctl_data_t gotgctl = {.d32 = 0 };
30383 +
30384 +       gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
30385 +       DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
30386 +       DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
30387 +
30388 +       /* B-Device connector (Device Mode) */
30389 +       if (gotgctl.b.conidsts) {
30390 +               /* Wait for switch to device mode. */
30391 +               while (!dwc_otg_is_device_mode(core_if)) {
30392 +                       DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
30393 +                                  (dwc_otg_is_host_mode(core_if) ? "Host" :
30394 +                                   "Peripheral"));
30395 +                       dwc_mdelay(100);
30396 +                       if (++count > 10000)
30397 +                               break;
30398 +               }
30399 +               DWC_ASSERT(++count < 10000,
30400 +                          "Connection id status change timed out");
30401 +               core_if->op_state = B_PERIPHERAL;
30402 +               dwc_otg_core_init(core_if);
30403 +               dwc_otg_enable_global_interrupts(core_if);
30404 +               cil_pcd_start(core_if);
30405 +       } else {
30406 +               /* A-Device connector (Host Mode) */
30407 +               while (!dwc_otg_is_host_mode(core_if)) {
30408 +                       DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
30409 +                                  (dwc_otg_is_host_mode(core_if) ? "Host" :
30410 +                                   "Peripheral"));
30411 +                       dwc_mdelay(100);
30412 +                       if (++count > 10000)
30413 +                               break;
30414 +               }
30415 +               DWC_ASSERT(++count < 10000,
30416 +                          "Connection id status change timed out");
30417 +               core_if->op_state = A_HOST;
30418 +               /*
30419 +                * Initialize the Core for Host mode.
30420 +                */
30421 +               dwc_otg_core_init(core_if);
30422 +               dwc_otg_enable_global_interrupts(core_if);
30423 +               cil_hcd_start(core_if);
30424 +       }
30425 +}
30426 +
30427 +/**
30428 + * This function handles the Connector ID Status Change Interrupt.  It
30429 + * reads the OTG Interrupt Register (GOTCTL) to determine whether this
30430 + * is a Device to Host Mode transition or a Host Mode to Device
30431 + * Transition.
30432 + *
30433 + * This only occurs when the cable is connected/removed from the PHY
30434 + * connector.
30435 + *
30436 + * @param core_if Programming view of DWC_otg controller.
30437 + */
30438 +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
30439 +{
30440 +
30441 +       /*
30442 +        * Need to disable SOF interrupt immediately. If switching from device
30443 +        * to host, the PCD interrupt handler won't handle the interrupt if
30444 +        * host mode is already set. The HCD interrupt handler won't get
30445 +        * called if the HCD state is HALT. This means that the interrupt does
30446 +        * not get handled and Linux complains loudly.
30447 +        */
30448 +       gintmsk_data_t gintmsk = {.d32 = 0 };
30449 +       gintsts_data_t gintsts = {.d32 = 0 };
30450 +
30451 +       gintmsk.b.sofintr = 1;
30452 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
30453 +
30454 +       DWC_DEBUGPL(DBG_CIL,
30455 +                   " ++Connector ID Status Change Interrupt++  (%s)\n",
30456 +                   (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
30457 +
30458 +       DWC_SPINUNLOCK(core_if->lock);
30459 +
30460 +       /*
30461 +        * Need to schedule a work, as there are possible DELAY function calls
30462 +        * Release lock before scheduling workq as it holds spinlock during scheduling
30463 +        */
30464 +
30465 +       DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
30466 +                          core_if, "connection id status change");
30467 +       DWC_SPINLOCK(core_if->lock);
30468 +
30469 +       /* Set flag and clear interrupt */
30470 +       gintsts.b.conidstschng = 1;
30471 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30472 +
30473 +       return 1;
30474 +}
30475 +
30476 +/**
30477 + * This interrupt indicates that a device is initiating the Session
30478 + * Request Protocol to request the host to turn on bus power so a new
30479 + * session can begin. The handler responds by turning on bus power. If
30480 + * the DWC_otg controller is in low power mode, the handler brings the
30481 + * controller out of low power mode before turning on bus power.
30482 + *
30483 + * @param core_if Programming view of DWC_otg controller.
30484 + */
30485 +int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
30486 +{
30487 +       gintsts_data_t gintsts;
30488 +
30489 +#ifndef DWC_HOST_ONLY
30490 +       DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
30491 +
30492 +       if (dwc_otg_is_device_mode(core_if)) {
30493 +               DWC_PRINTF("SRP: Device mode\n");
30494 +       } else {
30495 +               hprt0_data_t hprt0;
30496 +               DWC_PRINTF("SRP: Host mode\n");
30497 +
30498 +               /* Turn on the port power bit. */
30499 +               hprt0.d32 = dwc_otg_read_hprt0(core_if);
30500 +               hprt0.b.prtpwr = 1;
30501 +               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
30502 +
30503 +               /* Start the Connection timer. So a message can be displayed
30504 +                * if connect does not occur within 10 seconds. */
30505 +               cil_hcd_session_start(core_if);
30506 +       }
30507 +#endif
30508 +
30509 +       /* Clear interrupt */
30510 +       gintsts.d32 = 0;
30511 +       gintsts.b.sessreqintr = 1;
30512 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30513 +
30514 +       return 1;
30515 +}
30516 +
30517 +void w_wakeup_detected(void *p)
30518 +{
30519 +       dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
30520 +       /*
30521 +        * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
30522 +        * so that OPT tests pass with all PHYs).
30523 +        */
30524 +       hprt0_data_t hprt0 = {.d32 = 0 };
30525 +#if 0
30526 +       pcgcctl_data_t pcgcctl = {.d32 = 0 };
30527 +       /* Restart the Phy Clock */
30528 +       pcgcctl.b.stoppclk = 1;
30529 +       DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
30530 +       dwc_udelay(10);
30531 +#endif //0
30532 +       hprt0.d32 = dwc_otg_read_hprt0(core_if);
30533 +       DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
30534 +//      dwc_mdelay(70);
30535 +       hprt0.b.prtres = 0;     /* Resume */
30536 +       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
30537 +       DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
30538 +                   DWC_READ_REG32(core_if->host_if->hprt0));
30539 +
30540 +       cil_hcd_resume(core_if);
30541 +
30542 +       /** Change to L0 state*/
30543 +       core_if->lx_state = DWC_OTG_L0;
30544 +}
30545 +
30546 +/**
30547 + * This interrupt indicates that the DWC_otg controller has detected a
30548 + * resume or remote wakeup sequence. If the DWC_otg controller is in
30549 + * low power mode, the handler must brings the controller out of low
30550 + * power mode. The controller automatically begins resume
30551 + * signaling. The handler schedules a time to stop resume signaling.
30552 + */
30553 +int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
30554 +{
30555 +       gintsts_data_t gintsts;
30556 +
30557 +       DWC_DEBUGPL(DBG_ANY,
30558 +                   "++Resume and Remote Wakeup Detected Interrupt++\n");
30559 +
30560 +       DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
30561 +
30562 +       if (dwc_otg_is_device_mode(core_if)) {
30563 +               dctl_data_t dctl = {.d32 = 0 };
30564 +               DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
30565 +                           DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
30566 +                                          dsts));
30567 +               if (core_if->lx_state == DWC_OTG_L2) {
30568 +#ifdef PARTIAL_POWER_DOWN
30569 +                       if (core_if->hwcfg4.b.power_optimiz) {
30570 +                               pcgcctl_data_t power = {.d32 = 0 };
30571 +
30572 +                               power.d32 = DWC_READ_REG32(core_if->pcgcctl);
30573 +                               DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
30574 +                                           power.d32);
30575 +
30576 +                               power.b.stoppclk = 0;
30577 +                               DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30578 +
30579 +                               power.b.pwrclmp = 0;
30580 +                               DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30581 +
30582 +                               power.b.rstpdwnmodule = 0;
30583 +                               DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
30584 +                       }
30585 +#endif
30586 +                       /* Clear the Remote Wakeup Signaling */
30587 +                       dctl.b.rmtwkupsig = 1;
30588 +                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
30589 +                                        dctl, dctl.d32, 0);
30590 +
30591 +                       DWC_SPINUNLOCK(core_if->lock);
30592 +                       if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
30593 +                               core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
30594 +                       }
30595 +                       DWC_SPINLOCK(core_if->lock);
30596 +               } else {
30597 +                       glpmcfg_data_t lpmcfg;
30598 +                       lpmcfg.d32 =
30599 +                           DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
30600 +                       lpmcfg.b.hird_thres &= (~(1 << 4));
30601 +                       DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
30602 +                                       lpmcfg.d32);
30603 +               }
30604 +               /** Change to L0 state*/
30605 +               core_if->lx_state = DWC_OTG_L0;
30606 +       } else {
30607 +               if (core_if->lx_state != DWC_OTG_L1) {
30608 +                       pcgcctl_data_t pcgcctl = {.d32 = 0 };
30609 +
30610 +                       /* Restart the Phy Clock */
30611 +                       pcgcctl.b.stoppclk = 1;
30612 +                       DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
30613 +                       DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
30614 +               } else {
30615 +                       /** Change to L0 state*/
30616 +                       core_if->lx_state = DWC_OTG_L0;
30617 +               }
30618 +       }
30619 +
30620 +       /* Clear interrupt */
30621 +       gintsts.d32 = 0;
30622 +       gintsts.b.wkupintr = 1;
30623 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
30624 +
30625 +       return 1;
30626 +}
30627 +
30628 +/**
30629 + * This interrupt indicates that the Wakeup Logic has detected a
30630 + * Device disconnect.
30631 + */
30632 +static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
30633 +{
30634 +       gpwrdn_data_t gpwrdn = { .d32 = 0 };
30635 +       gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
30636 +       gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30637 +
30638 +       DWC_PRINTF("%s called\n", __FUNCTION__);
30639 +
30640 +       if (!core_if->hibernation_suspend) {
30641 +               DWC_PRINTF("Already exited from Hibernation\n");
30642 +               return 1;
30643 +       }
30644 +
30645 +       /* Switch on the voltage to the core */
30646 +       gpwrdn.b.pwrdnswtch = 1;
30647 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30648 +       dwc_udelay(10);
30649 +
30650 +       /* Reset the core */
30651 +       gpwrdn.d32 = 0;
30652 +       gpwrdn.b.pwrdnrstn = 1;
30653 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30654 +       dwc_udelay(10);
30655 +
30656 +       /* Disable power clamps*/
30657 +       gpwrdn.d32 = 0;
30658 +       gpwrdn.b.pwrdnclmp = 1;
30659 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30660 +
30661 +       /* Remove reset the core signal */
30662 +       gpwrdn.d32 = 0;
30663 +       gpwrdn.b.pwrdnrstn = 1;
30664 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30665 +       dwc_udelay(10);
30666 +
30667 +       /* Disable PMU interrupt */
30668 +       gpwrdn.d32 = 0;
30669 +       gpwrdn.b.pmuintsel = 1;
30670 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30671 +
30672 +       core_if->hibernation_suspend = 0;
30673 +
30674 +       /* Disable PMU */
30675 +       gpwrdn.d32 = 0;
30676 +       gpwrdn.b.pmuactv = 1;
30677 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30678 +       dwc_udelay(10);
30679 +
30680 +       if (gpwrdn_temp.b.idsts) {
30681 +               core_if->op_state = B_PERIPHERAL;
30682 +               dwc_otg_core_init(core_if);
30683 +               dwc_otg_enable_global_interrupts(core_if);
30684 +               cil_pcd_start(core_if);
30685 +       } else {
30686 +               core_if->op_state = A_HOST;
30687 +               dwc_otg_core_init(core_if);
30688 +               dwc_otg_enable_global_interrupts(core_if);
30689 +               cil_hcd_start(core_if);
30690 +       }
30691 +
30692 +       return 1;
30693 +}
30694 +
30695 +/**
30696 + * This interrupt indicates that the Wakeup Logic has detected a
30697 + * remote wakeup sequence.
30698 + */
30699 +static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
30700 +{
30701 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
30702 +       DWC_DEBUGPL(DBG_ANY,
30703 +                   "++Powerdown Remote Wakeup Detected Interrupt++\n");
30704 +
30705 +       if (!core_if->hibernation_suspend) {
30706 +               DWC_PRINTF("Already exited from Hibernation\n");
30707 +               return 1;
30708 +       }
30709 +
30710 +       gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30711 +       if (gpwrdn.b.idsts) {   // Device Mode
30712 +               if ((core_if->power_down == 2)
30713 +                   && (core_if->hibernation_suspend == 1)) {
30714 +                       dwc_otg_device_hibernation_restore(core_if, 0, 0);
30715 +               }
30716 +       } else {
30717 +               if ((core_if->power_down == 2)
30718 +                   && (core_if->hibernation_suspend == 1)) {
30719 +                       dwc_otg_host_hibernation_restore(core_if, 1, 0);
30720 +               }
30721 +       }
30722 +       return 1;
30723 +}
30724 +
30725 +static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
30726 +{
30727 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
30728 +       gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
30729 +       dwc_otg_core_if_t *core_if = otg_dev->core_if;
30730 +
30731 +       DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
30732 +       gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30733 +       if (core_if->power_down == 2) {
30734 +               if (!core_if->hibernation_suspend) {
30735 +                       DWC_PRINTF("Already exited from Hibernation\n");
30736 +                       return 1;
30737 +               }
30738 +               DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
30739 +               /* Switch on the voltage to the core */
30740 +               gpwrdn.b.pwrdnswtch = 1;
30741 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30742 +               dwc_udelay(10);
30743 +
30744 +               /* Reset the core */
30745 +               gpwrdn.d32 = 0;
30746 +               gpwrdn.b.pwrdnrstn = 1;
30747 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30748 +               dwc_udelay(10);
30749 +
30750 +               /* Disable power clamps */
30751 +               gpwrdn.d32 = 0;
30752 +               gpwrdn.b.pwrdnclmp = 1;
30753 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30754 +
30755 +               /* Remove reset the core signal */
30756 +               gpwrdn.d32 = 0;
30757 +               gpwrdn.b.pwrdnrstn = 1;
30758 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30759 +               dwc_udelay(10);
30760 +
30761 +               /* Disable PMU interrupt */
30762 +               gpwrdn.d32 = 0;
30763 +               gpwrdn.b.pmuintsel = 1;
30764 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30765 +
30766 +               /*Indicates that we are exiting from hibernation */
30767 +               core_if->hibernation_suspend = 0;
30768 +
30769 +               /* Disable PMU */
30770 +               gpwrdn.d32 = 0;
30771 +               gpwrdn.b.pmuactv = 1;
30772 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30773 +               dwc_udelay(10);
30774 +
30775 +               gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
30776 +               if (gpwrdn.b.dis_vbus == 1) {
30777 +                       gpwrdn.d32 = 0;
30778 +                       gpwrdn.b.dis_vbus = 1;
30779 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30780 +               }
30781 +
30782 +               if (gpwrdn_temp.b.idsts) {
30783 +                       core_if->op_state = B_PERIPHERAL;
30784 +                       dwc_otg_core_init(core_if);
30785 +                       dwc_otg_enable_global_interrupts(core_if);
30786 +                       cil_pcd_start(core_if);
30787 +               } else {
30788 +                       core_if->op_state = A_HOST;
30789 +                       dwc_otg_core_init(core_if);
30790 +                       dwc_otg_enable_global_interrupts(core_if);
30791 +                       cil_hcd_start(core_if);
30792 +               }
30793 +       }
30794 +
30795 +       if (core_if->adp_enable) {
30796 +               uint8_t is_host = 0;
30797 +               DWC_SPINUNLOCK(core_if->lock);
30798 +               /* Change the core_if's lock to hcd/pcd lock depend on mode? */
30799 +#ifndef DWC_HOST_ONLY
30800 +               if (gpwrdn_temp.b.idsts)
30801 +                       core_if->lock = otg_dev->pcd->lock;
30802 +#endif
30803 +#ifndef DWC_DEVICE_ONLY
30804 +               if (!gpwrdn_temp.b.idsts) {
30805 +                               core_if->lock = otg_dev->hcd->lock;
30806 +                               is_host = 1;
30807 +               }
30808 +#endif
30809 +               DWC_PRINTF("RESTART ADP\n");
30810 +               if (core_if->adp.probe_enabled)
30811 +                       dwc_otg_adp_probe_stop(core_if);
30812 +               if (core_if->adp.sense_enabled)
30813 +                       dwc_otg_adp_sense_stop(core_if);
30814 +               if (core_if->adp.sense_timer_started)
30815 +                       DWC_TIMER_CANCEL(core_if->adp.sense_timer);
30816 +               if (core_if->adp.vbuson_timer_started)
30817 +                       DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
30818 +               core_if->adp.probe_timer_values[0] = -1;
30819 +               core_if->adp.probe_timer_values[1] = -1;
30820 +               core_if->adp.sense_timer_started = 0;
30821 +               core_if->adp.vbuson_timer_started = 0;
30822 +               core_if->adp.probe_counter = 0;
30823 +               core_if->adp.gpwrdn = 0;
30824 +
30825 +               /* Disable PMU and restart ADP */
30826 +               gpwrdn_temp.d32 = 0;
30827 +               gpwrdn_temp.b.pmuactv = 1;
30828 +               gpwrdn_temp.b.pmuintsel = 1;
30829 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30830 +               DWC_PRINTF("Check point 1\n");
30831 +               dwc_mdelay(110);
30832 +               dwc_otg_adp_start(core_if, is_host);
30833 +               DWC_SPINLOCK(core_if->lock);
30834 +       }
30835 +
30836 +
30837 +       return 1;
30838 +}
30839 +
30840 +static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
30841 +{
30842 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
30843 +       int32_t otg_cap_param = core_if->core_params->otg_cap;
30844 +       DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
30845 +
30846 +       gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30847 +       if (core_if->power_down == 2) {
30848 +               if (!core_if->hibernation_suspend) {
30849 +                       DWC_PRINTF("Already exited from Hibernation\n");
30850 +                       return 1;
30851 +               }
30852 +
30853 +               if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
30854 +                        otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
30855 +                       gpwrdn.b.bsessvld == 0) {
30856 +                       /* Save gpwrdn register for further usage if stschng interrupt */
30857 +                       core_if->gr_backup->gpwrdn_local =
30858 +                               DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30859 +                       /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
30860 +                       return 1;
30861 +               }
30862 +
30863 +               /* Switch on the voltage to the core */
30864 +               gpwrdn.d32 = 0;
30865 +               gpwrdn.b.pwrdnswtch = 1;
30866 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30867 +               dwc_udelay(10);
30868 +
30869 +               /* Reset the core */
30870 +               gpwrdn.d32 = 0;
30871 +               gpwrdn.b.pwrdnrstn = 1;
30872 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30873 +               dwc_udelay(10);
30874 +
30875 +               /* Disable power clamps */
30876 +               gpwrdn.d32 = 0;
30877 +               gpwrdn.b.pwrdnclmp = 1;
30878 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30879 +
30880 +               /* Remove reset the core signal */
30881 +               gpwrdn.d32 = 0;
30882 +               gpwrdn.b.pwrdnrstn = 1;
30883 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30884 +               dwc_udelay(10);
30885 +
30886 +               /* Disable PMU interrupt */
30887 +               gpwrdn.d32 = 0;
30888 +               gpwrdn.b.pmuintsel = 1;
30889 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30890 +               dwc_udelay(10);
30891 +
30892 +               /*Indicates that we are exiting from hibernation */
30893 +               core_if->hibernation_suspend = 0;
30894 +
30895 +               /* Disable PMU */
30896 +               gpwrdn.d32 = 0;
30897 +               gpwrdn.b.pmuactv = 1;
30898 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30899 +               dwc_udelay(10);
30900 +
30901 +               core_if->op_state = B_PERIPHERAL;
30902 +               dwc_otg_core_init(core_if);
30903 +               dwc_otg_enable_global_interrupts(core_if);
30904 +               cil_pcd_start(core_if);
30905 +
30906 +               if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
30907 +                       otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
30908 +                       /*
30909 +                        * Initiate SRP after initial ADP probe.
30910 +                        */
30911 +                       dwc_otg_initiate_srp(core_if);
30912 +               }
30913 +       }
30914 +
30915 +       return 1;
30916 +}
30917 +/**
30918 + * This interrupt indicates that the Wakeup Logic has detected a
30919 + * status change either on IDDIG or BSessVld.
30920 + */
30921 +static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
30922 +{
30923 +       int retval;
30924 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
30925 +       gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
30926 +       dwc_otg_core_if_t *core_if = otg_dev->core_if;
30927 +
30928 +       DWC_PRINTF("%s called\n", __FUNCTION__);
30929 +
30930 +       if (core_if->power_down == 2) {
30931 +               if (core_if->hibernation_suspend <= 0) {
30932 +                       DWC_PRINTF("Already exited from Hibernation\n");
30933 +                       return 1;
30934 +               } else
30935 +                       gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
30936 +
30937 +       } else {
30938 +               gpwrdn_temp.d32 = core_if->adp.gpwrdn;
30939 +       }
30940 +
30941 +       gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
30942 +
30943 +       if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
30944 +               retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
30945 +       } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
30946 +               retval = dwc_otg_handle_pwrdn_session_change(core_if);
30947 +       }
30948 +
30949 +       return retval;
30950 +}
30951 +
30952 +/**
30953 + * This interrupt indicates that the Wakeup Logic has detected a
30954 + * SRP.
30955 + */
30956 +static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
30957 +{
30958 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
30959 +
30960 +       DWC_PRINTF("%s called\n", __FUNCTION__);
30961 +
30962 +       if (!core_if->hibernation_suspend) {
30963 +               DWC_PRINTF("Already exited from Hibernation\n");
30964 +               return 1;
30965 +       }
30966 +#ifdef DWC_DEV_SRPCAP
30967 +       if (core_if->pwron_timer_started) {
30968 +               core_if->pwron_timer_started = 0;
30969 +               DWC_TIMER_CANCEL(core_if->pwron_timer);
30970 +       }
30971 +#endif
30972 +
30973 +       /* Switch on the voltage to the core */
30974 +       gpwrdn.b.pwrdnswtch = 1;
30975 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30976 +       dwc_udelay(10);
30977 +
30978 +       /* Reset the core */
30979 +       gpwrdn.d32 = 0;
30980 +       gpwrdn.b.pwrdnrstn = 1;
30981 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30982 +       dwc_udelay(10);
30983 +
30984 +       /* Disable power clamps */
30985 +       gpwrdn.d32 = 0;
30986 +       gpwrdn.b.pwrdnclmp = 1;
30987 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30988 +
30989 +       /* Remove reset the core signal */
30990 +       gpwrdn.d32 = 0;
30991 +       gpwrdn.b.pwrdnrstn = 1;
30992 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
30993 +       dwc_udelay(10);
30994 +
30995 +       /* Disable PMU interrupt */
30996 +       gpwrdn.d32 = 0;
30997 +       gpwrdn.b.pmuintsel = 1;
30998 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
30999 +
31000 +       /* Indicates that we are exiting from hibernation */
31001 +       core_if->hibernation_suspend = 0;
31002 +
31003 +       /* Disable PMU */
31004 +       gpwrdn.d32 = 0;
31005 +       gpwrdn.b.pmuactv = 1;
31006 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31007 +       dwc_udelay(10);
31008 +
31009 +       /* Programm Disable VBUS to 0 */
31010 +       gpwrdn.d32 = 0;
31011 +       gpwrdn.b.dis_vbus = 1;
31012 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31013 +
31014 +       /*Initialize the core as Host */
31015 +       core_if->op_state = A_HOST;
31016 +       dwc_otg_core_init(core_if);
31017 +       dwc_otg_enable_global_interrupts(core_if);
31018 +       cil_hcd_start(core_if);
31019 +
31020 +       return 1;
31021 +}
31022 +
31023 +/** This interrupt indicates that restore command after Hibernation
31024 + * was completed by the core. */
31025 +int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
31026 +{
31027 +       pcgcctl_data_t pcgcctl;
31028 +       DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
31029 +
31030 +       //TODO De-assert restore signal. 8.a
31031 +       pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
31032 +       if (pcgcctl.b.restoremode == 1) {
31033 +               gintmsk_data_t gintmsk = {.d32 = 0 };
31034 +               /*
31035 +                * If restore mode is Remote Wakeup,
31036 +                * unmask Remote Wakeup interrupt.
31037 +                */
31038 +               gintmsk.b.wkupintr = 1;
31039 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
31040 +                                0, gintmsk.d32);
31041 +       }
31042 +
31043 +       return 1;
31044 +}
31045 +
31046 +/**
31047 + * This interrupt indicates that a device has been disconnected from
31048 + * the root port.
31049 + */
31050 +int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
31051 +{
31052 +       gintsts_data_t gintsts;
31053 +
31054 +       DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
31055 +                   (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
31056 +                   op_state_str(core_if));
31057 +
31058 +/** @todo Consolidate this if statement. */
31059 +#ifndef DWC_HOST_ONLY
31060 +       if (core_if->op_state == B_HOST) {
31061 +               /* If in device mode Disconnect and stop the HCD, then
31062 +                * start the PCD. */
31063 +               DWC_SPINUNLOCK(core_if->lock);
31064 +               cil_hcd_disconnect(core_if);
31065 +               cil_pcd_start(core_if);
31066 +               DWC_SPINLOCK(core_if->lock);
31067 +               core_if->op_state = B_PERIPHERAL;
31068 +       } else if (dwc_otg_is_device_mode(core_if)) {
31069 +               gotgctl_data_t gotgctl = {.d32 = 0 };
31070 +               gotgctl.d32 =
31071 +                   DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
31072 +               if (gotgctl.b.hstsethnpen == 1) {
31073 +                       /* Do nothing, if HNP in process the OTG
31074 +                        * interrupt "Host Negotiation Detected"
31075 +                        * interrupt will do the mode switch.
31076 +                        */
31077 +               } else if (gotgctl.b.devhnpen == 0) {
31078 +                       /* If in device mode Disconnect and stop the HCD, then
31079 +                        * start the PCD. */
31080 +                       DWC_SPINUNLOCK(core_if->lock);
31081 +                       cil_hcd_disconnect(core_if);
31082 +                       cil_pcd_start(core_if);
31083 +                       DWC_SPINLOCK(core_if->lock);
31084 +                       core_if->op_state = B_PERIPHERAL;
31085 +               } else {
31086 +                       DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
31087 +               }
31088 +       } else {
31089 +               if (core_if->op_state == A_HOST) {
31090 +                       /* A-Cable still connected but device disconnected. */
31091 +                       cil_hcd_disconnect(core_if);
31092 +                       if (core_if->adp_enable) {
31093 +                               gpwrdn_data_t gpwrdn = { .d32 = 0 };
31094 +                               cil_hcd_stop(core_if);
31095 +                               /* Enable Power Down Logic */
31096 +                               gpwrdn.b.pmuintsel = 1;
31097 +                               gpwrdn.b.pmuactv = 1;
31098 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
31099 +                                                gpwrdn, 0, gpwrdn.d32);
31100 +                               dwc_otg_adp_probe_start(core_if);
31101 +
31102 +                               /* Power off the core */
31103 +                               if (core_if->power_down == 2) {
31104 +                                       gpwrdn.d32 = 0;
31105 +                                       gpwrdn.b.pwrdnswtch = 1;
31106 +                                       DWC_MODIFY_REG32
31107 +                                           (&core_if->core_global_regs->gpwrdn,
31108 +                                            gpwrdn.d32, 0);
31109 +                               }
31110 +                       }
31111 +               }
31112 +       }
31113 +#endif
31114 +       /* Change to L3(OFF) state */
31115 +       core_if->lx_state = DWC_OTG_L3;
31116 +
31117 +       gintsts.d32 = 0;
31118 +       gintsts.b.disconnect = 1;
31119 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31120 +       return 1;
31121 +}
31122 +
31123 +/**
31124 + * This interrupt indicates that SUSPEND state has been detected on
31125 + * the USB.
31126 + *
31127 + * For HNP the USB Suspend interrupt signals the change from
31128 + * "a_peripheral" to "a_host".
31129 + *
31130 + * When power management is enabled the core will be put in low power
31131 + * mode.
31132 + */
31133 +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
31134 +{
31135 +       dsts_data_t dsts;
31136 +       gintsts_data_t gintsts;
31137 +       dcfg_data_t dcfg;
31138 +
31139 +       DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
31140 +
31141 +       if (dwc_otg_is_device_mode(core_if)) {
31142 +               /* Check the Device status register to determine if the Suspend
31143 +                * state is active. */
31144 +               dsts.d32 =
31145 +                   DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
31146 +               DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
31147 +               DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
31148 +                           "HWCFG4.power Optimize=%d\n",
31149 +                           dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
31150 +
31151 +#ifdef PARTIAL_POWER_DOWN
31152 +/** @todo Add a module parameter for power management. */
31153 +
31154 +               if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
31155 +                       pcgcctl_data_t power = {.d32 = 0 };
31156 +                       DWC_DEBUGPL(DBG_CIL, "suspend\n");
31157 +
31158 +                       power.b.pwrclmp = 1;
31159 +                       DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
31160 +
31161 +                       power.b.rstpdwnmodule = 1;
31162 +                       DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
31163 +
31164 +                       power.b.stoppclk = 1;
31165 +                       DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
31166 +
31167 +               } else {
31168 +                       DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
31169 +               }
31170 +#endif
31171 +               /* PCD callback for suspend. Release the lock inside of callback function */
31172 +               cil_pcd_suspend(core_if);
31173 +               if (core_if->power_down == 2)
31174 +               {
31175 +                       dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
31176 +                       DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
31177 +                       DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
31178 +
31179 +                       if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
31180 +                               pcgcctl_data_t pcgcctl = {.d32 = 0 };
31181 +                               gpwrdn_data_t gpwrdn = {.d32 = 0 };
31182 +                               gusbcfg_data_t gusbcfg = {.d32 = 0 };
31183 +
31184 +                               /* Change to L2(suspend) state */
31185 +                               core_if->lx_state = DWC_OTG_L2;
31186 +
31187 +                               /* Clear interrupt in gintsts */
31188 +                               gintsts.d32 = 0;
31189 +                               gintsts.b.usbsuspend = 1;
31190 +                               DWC_WRITE_REG32(&core_if->core_global_regs->
31191 +                                               gintsts, gintsts.d32);
31192 +                               DWC_PRINTF("Start of hibernation completed\n");
31193 +                               dwc_otg_save_global_regs(core_if);
31194 +                               dwc_otg_save_dev_regs(core_if);
31195 +
31196 +                               gusbcfg.d32 =
31197 +                                   DWC_READ_REG32(&core_if->core_global_regs->
31198 +                                                  gusbcfg);
31199 +                               if (gusbcfg.b.ulpi_utmi_sel == 1) {
31200 +                                       /* ULPI interface */
31201 +                                       /* Suspend the Phy Clock */
31202 +                                       pcgcctl.d32 = 0;
31203 +                                       pcgcctl.b.stoppclk = 1;
31204 +                                       DWC_MODIFY_REG32(core_if->pcgcctl, 0,
31205 +                                                        pcgcctl.d32);
31206 +                                       dwc_udelay(10);
31207 +                                       gpwrdn.b.pmuactv = 1;
31208 +                                       DWC_MODIFY_REG32(&core_if->
31209 +                                                        core_global_regs->
31210 +                                                        gpwrdn, 0, gpwrdn.d32);
31211 +                               } else {
31212 +                                       /* UTMI+ Interface */
31213 +                                       gpwrdn.b.pmuactv = 1;
31214 +                                       DWC_MODIFY_REG32(&core_if->
31215 +                                                        core_global_regs->
31216 +                                                        gpwrdn, 0, gpwrdn.d32);
31217 +                                       dwc_udelay(10);
31218 +                                       pcgcctl.b.stoppclk = 1;
31219 +                                       DWC_MODIFY_REG32(core_if->pcgcctl, 0,
31220 +                                                        pcgcctl.d32);
31221 +                                       dwc_udelay(10);
31222 +                               }
31223 +
31224 +                               /* Set flag to indicate that we are in hibernation */
31225 +                               core_if->hibernation_suspend = 1;
31226 +                               /* Enable interrupts from wake up logic */
31227 +                               gpwrdn.d32 = 0;
31228 +                               gpwrdn.b.pmuintsel = 1;
31229 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
31230 +                                                gpwrdn, 0, gpwrdn.d32);
31231 +                               dwc_udelay(10);
31232 +
31233 +                               /* Unmask device mode interrupts in GPWRDN */
31234 +                               gpwrdn.d32 = 0;
31235 +                               gpwrdn.b.rst_det_msk = 1;
31236 +                               gpwrdn.b.lnstchng_msk = 1;
31237 +                               gpwrdn.b.sts_chngint_msk = 1;
31238 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
31239 +                                                gpwrdn, 0, gpwrdn.d32);
31240 +                               dwc_udelay(10);
31241 +
31242 +                               /* Enable Power Down Clamp */
31243 +                               gpwrdn.d32 = 0;
31244 +                               gpwrdn.b.pwrdnclmp = 1;
31245 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
31246 +                                                gpwrdn, 0, gpwrdn.d32);
31247 +                               dwc_udelay(10);
31248 +
31249 +                               /* Switch off VDD */
31250 +                               gpwrdn.d32 = 0;
31251 +                               gpwrdn.b.pwrdnswtch = 1;
31252 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
31253 +                                                gpwrdn, 0, gpwrdn.d32);
31254 +
31255 +                               /* Save gpwrdn register for further usage if stschng interrupt */
31256 +                               core_if->gr_backup->gpwrdn_local =
31257 +                                                       DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31258 +                               DWC_PRINTF("Hibernation completed\n");
31259 +
31260 +                               return 1;
31261 +                       }
31262 +               } else if (core_if->power_down == 3) {
31263 +                       pcgcctl_data_t pcgcctl = {.d32 = 0 };
31264 +                       dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
31265 +                       DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state);
31266 +                       DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr);
31267 +
31268 +                       if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
31269 +                               DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n");
31270 +                               core_if->xhib = 1;
31271 +
31272 +                               /* Clear interrupt in gintsts */
31273 +                               gintsts.d32 = 0;
31274 +                               gintsts.b.usbsuspend = 1;
31275 +                               DWC_WRITE_REG32(&core_if->core_global_regs->
31276 +                                       gintsts, gintsts.d32);
31277 +
31278 +                               dwc_otg_save_global_regs(core_if);
31279 +                               dwc_otg_save_dev_regs(core_if);
31280 +
31281 +                               /* Wait for 10 PHY clocks */
31282 +                               dwc_udelay(10);
31283 +
31284 +                               /* Program GPIO register while entering to xHib */
31285 +                               DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1);
31286 +
31287 +                               pcgcctl.b.enbl_extnd_hiber = 1;
31288 +                               DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31289 +                               DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31290 +
31291 +                               pcgcctl.d32 = 0;
31292 +                               pcgcctl.b.extnd_hiber_pwrclmp = 1;
31293 +                               DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31294 +
31295 +                               pcgcctl.d32 = 0;
31296 +                               pcgcctl.b.extnd_hiber_switch = 1;
31297 +                               core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31298 +                               core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32;
31299 +                               DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
31300 +
31301 +                               DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n");
31302 +
31303 +                               return 1;
31304 +                       }
31305 +               }
31306 +       } else {
31307 +               if (core_if->op_state == A_PERIPHERAL) {
31308 +                       DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
31309 +                       /* Clear the a_peripheral flag, back to a_host. */
31310 +                       DWC_SPINUNLOCK(core_if->lock);
31311 +                       cil_pcd_stop(core_if);
31312 +                       cil_hcd_start(core_if);
31313 +                       DWC_SPINLOCK(core_if->lock);
31314 +                       core_if->op_state = A_HOST;
31315 +               }
31316 +       }
31317 +
31318 +       /* Change to L2(suspend) state */
31319 +       core_if->lx_state = DWC_OTG_L2;
31320 +
31321 +       /* Clear interrupt */
31322 +       gintsts.d32 = 0;
31323 +       gintsts.b.usbsuspend = 1;
31324 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31325 +
31326 +       return 1;
31327 +}
31328 +
31329 +static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if)
31330 +{
31331 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
31332 +       pcgcctl_data_t pcgcctl = {.d32 = 0 };
31333 +       gahbcfg_data_t gahbcfg = {.d32 = 0 };
31334 +
31335 +       dwc_udelay(10);
31336 +
31337 +       /* Program GPIO register while entering to xHib */
31338 +       DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0);
31339 +
31340 +       pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl;
31341 +       pcgcctl.b.extnd_hiber_pwrclmp = 0;
31342 +       DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31343 +       dwc_udelay(10);
31344 +
31345 +       gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn;
31346 +       gpwrdn.b.restore = 1;
31347 +       DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32);
31348 +       dwc_udelay(10);
31349 +
31350 +       restore_lpm_i2c_regs(core_if);
31351 +
31352 +       pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31353 +       pcgcctl.b.max_xcvrselect = 1;
31354 +       pcgcctl.b.ess_reg_restored = 0;
31355 +       pcgcctl.b.extnd_hiber_switch = 0;
31356 +       pcgcctl.b.extnd_hiber_pwrclmp = 0;
31357 +       pcgcctl.b.enbl_extnd_hiber = 1;
31358 +       DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31359 +
31360 +       gahbcfg.d32 = core_if->gr_backup->gahbcfg_local;
31361 +       gahbcfg.b.glblintrmsk = 1;
31362 +       DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
31363 +
31364 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
31365 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16);
31366 +
31367 +       DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
31368 +                       core_if->gr_backup->gusbcfg_local);
31369 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
31370 +                       core_if->dr_backup->dcfg);
31371 +
31372 +       pcgcctl.d32 = 0;
31373 +       pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31374 +       pcgcctl.b.max_xcvrselect = 1;
31375 +       pcgcctl.d32 |= 0x608;
31376 +       DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31377 +       dwc_udelay(10);
31378 +
31379 +       pcgcctl.d32 = 0;
31380 +       pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14);
31381 +       pcgcctl.b.max_xcvrselect = 1;
31382 +       pcgcctl.b.ess_reg_restored = 1;
31383 +       pcgcctl.b.enbl_extnd_hiber = 1;
31384 +       pcgcctl.b.rstpdwnmodule = 1;
31385 +       pcgcctl.b.restoremode = 1;
31386 +       DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
31387 +
31388 +       DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
31389 +
31390 +       return 1;
31391 +}
31392 +
31393 +#ifdef CONFIG_USB_DWC_OTG_LPM
31394 +/**
31395 + * This function hadles LPM transaction received interrupt.
31396 + */
31397 +static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
31398 +{
31399 +       glpmcfg_data_t lpmcfg;
31400 +       gintsts_data_t gintsts;
31401 +
31402 +       if (!core_if->core_params->lpm_enable) {
31403 +               DWC_PRINTF("Unexpected LPM interrupt\n");
31404 +       }
31405 +
31406 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
31407 +       DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
31408 +
31409 +       if (dwc_otg_is_host_mode(core_if)) {
31410 +               cil_hcd_sleep(core_if);
31411 +       } else {
31412 +               lpmcfg.b.hird_thres |= (1 << 4);
31413 +               DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
31414 +                               lpmcfg.d32);
31415 +       }
31416 +
31417 +       /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
31418 +       dwc_udelay(10);
31419 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
31420 +       if (lpmcfg.b.prt_sleep_sts) {
31421 +               /* Save the current state */
31422 +               core_if->lx_state = DWC_OTG_L1;
31423 +       }
31424 +
31425 +       /* Clear interrupt  */
31426 +       gintsts.d32 = 0;
31427 +       gintsts.b.lpmtranrcvd = 1;
31428 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
31429 +       return 1;
31430 +}
31431 +#endif /* CONFIG_USB_DWC_OTG_LPM */
31432 +
31433 +/**
31434 + * This function returns the Core Interrupt register.
31435 + */
31436 +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd)
31437 +{
31438 +       gahbcfg_data_t gahbcfg = {.d32 = 0 };
31439 +       gintsts_data_t gintsts;
31440 +       gintmsk_data_t gintmsk;
31441 +       gintmsk_data_t gintmsk_common = {.d32 = 0 };
31442 +       gintmsk_common.b.wkupintr = 1;
31443 +       gintmsk_common.b.sessreqintr = 1;
31444 +       gintmsk_common.b.conidstschng = 1;
31445 +       gintmsk_common.b.otgintr = 1;
31446 +       gintmsk_common.b.modemismatch = 1;
31447 +       gintmsk_common.b.disconnect = 1;
31448 +       gintmsk_common.b.usbsuspend = 1;
31449 +#ifdef CONFIG_USB_DWC_OTG_LPM
31450 +       gintmsk_common.b.lpmtranrcvd = 1;
31451 +#endif
31452 +       gintmsk_common.b.restoredone = 1;
31453 +       if(dwc_otg_is_device_mode(core_if))
31454 +       {
31455 +               /** @todo: The port interrupt occurs while in device
31456 +                * mode. Added code to CIL to clear the interrupt for now!
31457 +                */
31458 +               gintmsk_common.b.portintr = 1;
31459 +       }
31460 +       gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
31461 +       gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
31462 +       if(fiq_enable) {
31463 +               local_fiq_disable();
31464 +               /* Pull in the interrupts that the FIQ has masked */
31465 +               gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32);
31466 +               gintmsk.d32 |= gintmsk_common.d32;
31467 +               /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */
31468 +               reenable_gintmsk->d32 = gintmsk.d32;
31469 +               local_fiq_enable();
31470 +       }
31471 +
31472 +       gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
31473 +
31474 +#ifdef DEBUG
31475 +       /* if any common interrupts set */
31476 +       if (gintsts.d32 & gintmsk_common.d32) {
31477 +               DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x  gintmsk=%08x\n",
31478 +                           gintsts.d32, gintmsk.d32);
31479 +       }
31480 +#endif
31481 +       if (!fiq_enable){
31482 +               if (gahbcfg.b.glblintrmsk)
31483 +                       return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
31484 +               else
31485 +                       return 0;
31486 +       } else {
31487 +               /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface.
31488 +                * Can't trust the global interrupt mask bit in this case.
31489 +                */
31490 +               return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
31491 +       }
31492 +
31493 +}
31494 +
31495 +/* MACRO for clearing interupt bits in GPWRDN register */
31496 +#define CLEAR_GPWRDN_INTR(__core_if,__intr) \
31497 +do { \
31498 +               gpwrdn_data_t gpwrdn = {.d32=0}; \
31499 +               gpwrdn.b.__intr = 1; \
31500 +               DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
31501 +               0, gpwrdn.d32); \
31502 +} while (0)
31503 +
31504 +/**
31505 + * Common interrupt handler.
31506 + *
31507 + * The common interrupts are those that occur in both Host and Device mode.
31508 + * This handler handles the following interrupts:
31509 + * - Mode Mismatch Interrupt
31510 + * - Disconnect Interrupt
31511 + * - OTG Interrupt
31512 + * - Connector ID Status Change Interrupt
31513 + * - Session Request Interrupt.
31514 + * - Resume / Remote Wakeup Detected Interrupt.
31515 + * - LPM Transaction Received Interrupt
31516 + * - ADP Transaction Received Interrupt
31517 + *
31518 + */
31519 +int32_t dwc_otg_handle_common_intr(void *dev)
31520 +{
31521 +       int retval = 0;
31522 +       gintsts_data_t gintsts;
31523 +       gintmsk_data_t gintmsk_reenable = { .d32 = 0 };
31524 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
31525 +       dwc_otg_device_t *otg_dev = dev;
31526 +       dwc_otg_core_if_t *core_if = otg_dev->core_if;
31527 +       gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
31528 +       if (dwc_otg_is_device_mode(core_if))
31529 +               core_if->frame_num = dwc_otg_get_frame_number(core_if);
31530 +
31531 +       if (core_if->lock)
31532 +               DWC_SPINLOCK(core_if->lock);
31533 +
31534 +       if (core_if->power_down == 3 && core_if->xhib == 1) {
31535 +               DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n");
31536 +               retval |= dwc_otg_handle_xhib_exit_intr(core_if);
31537 +               core_if->xhib = 2;
31538 +               if (core_if->lock)
31539 +                       DWC_SPINUNLOCK(core_if->lock);
31540 +
31541 +               return retval;
31542 +       }
31543 +
31544 +       if (core_if->hibernation_suspend <= 0) {
31545 +               /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end
31546 +                * of this handler - god only knows why it's done like this
31547 +                */
31548 +               gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd);
31549 +
31550 +               if (gintsts.b.modemismatch) {
31551 +                       retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
31552 +               }
31553 +               if (gintsts.b.otgintr) {
31554 +                       retval |= dwc_otg_handle_otg_intr(core_if);
31555 +               }
31556 +               if (gintsts.b.conidstschng) {
31557 +                       retval |=
31558 +                           dwc_otg_handle_conn_id_status_change_intr(core_if);
31559 +               }
31560 +               if (gintsts.b.disconnect) {
31561 +                       retval |= dwc_otg_handle_disconnect_intr(core_if);
31562 +               }
31563 +               if (gintsts.b.sessreqintr) {
31564 +                       retval |= dwc_otg_handle_session_req_intr(core_if);
31565 +               }
31566 +               if (gintsts.b.wkupintr) {
31567 +                       retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
31568 +               }
31569 +               if (gintsts.b.usbsuspend) {
31570 +                       retval |= dwc_otg_handle_usb_suspend_intr(core_if);
31571 +               }
31572 +#ifdef CONFIG_USB_DWC_OTG_LPM
31573 +               if (gintsts.b.lpmtranrcvd) {
31574 +                       retval |= dwc_otg_handle_lpm_intr(core_if);
31575 +               }
31576 +#endif
31577 +               if (gintsts.b.restoredone) {
31578 +                       gintsts.d32 = 0;
31579 +                       if (core_if->power_down == 2)
31580 +                               core_if->hibernation_suspend = -1;
31581 +                       else if (core_if->power_down == 3 && core_if->xhib == 2) {
31582 +                               gpwrdn_data_t gpwrdn = {.d32 = 0 };
31583 +                               pcgcctl_data_t pcgcctl = {.d32 = 0 };
31584 +                               dctl_data_t dctl = {.d32 = 0 };
31585 +
31586 +                               DWC_WRITE_REG32(&core_if->core_global_regs->
31587 +                                               gintsts, 0xFFFFFFFF);
31588 +
31589 +                               DWC_DEBUGPL(DBG_ANY,
31590 +                                           "RESTORE DONE generated\n");
31591 +
31592 +                               gpwrdn.b.restore = 1;
31593 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
31594 +                               dwc_udelay(10);
31595 +
31596 +                               pcgcctl.b.rstpdwnmodule = 1;
31597 +                               DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
31598 +
31599 +                               DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local);
31600 +                               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg);
31601 +                               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl);
31602 +                               dwc_udelay(50);
31603 +
31604 +                               dctl.b.pwronprgdone = 1;
31605 +                               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
31606 +                               dwc_udelay(10);
31607 +
31608 +                               dwc_otg_restore_global_regs(core_if);
31609 +                               dwc_otg_restore_dev_regs(core_if, 0);
31610 +
31611 +                               dctl.d32 = 0;
31612 +                               dctl.b.pwronprgdone = 1;
31613 +                               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
31614 +                               dwc_udelay(10);
31615 +
31616 +                               pcgcctl.d32 = 0;
31617 +                               pcgcctl.b.enbl_extnd_hiber = 1;
31618 +                               DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
31619 +
31620 +                               /* The core will be in ON STATE */
31621 +                               core_if->lx_state = DWC_OTG_L0;
31622 +                               core_if->xhib = 0;
31623 +
31624 +                               DWC_SPINUNLOCK(core_if->lock);
31625 +                               if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
31626 +                                       core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
31627 +                               }
31628 +                               DWC_SPINLOCK(core_if->lock);
31629 +
31630 +                       }
31631 +
31632 +                       gintsts.b.restoredone = 1;
31633 +                       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
31634 +                       DWC_PRINTF(" --Restore done interrupt received-- \n");
31635 +                       retval |= 1;
31636 +               }
31637 +               if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
31638 +                       /* The port interrupt occurs while in device mode with HPRT0
31639 +                        * Port Enable/Disable.
31640 +                        */
31641 +                       gintsts.d32 = 0;
31642 +                       gintsts.b.portintr = 1;
31643 +                       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
31644 +                       retval |= 1;
31645 +                       gintmsk_reenable.b.portintr = 1;
31646 +
31647 +               }
31648 +               /* Did we actually handle anything? if so, unmask the interrupt */
31649 +//             fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval);
31650 +//             fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32);
31651 +//             fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32);
31652 +               if (retval && fiq_enable) {
31653 +                       DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32);
31654 +               }
31655 +
31656 +       } else {
31657 +               DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
31658 +
31659 +               if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
31660 +                       CLEAR_GPWRDN_INTR(core_if, disconn_det);
31661 +                       if (gpwrdn.b.linestate == 0) {
31662 +                               dwc_otg_handle_pwrdn_disconnect_intr(core_if);
31663 +                       } else {
31664 +                               DWC_PRINTF("Disconnect detected while linestate is not 0\n");
31665 +                       }
31666 +
31667 +                       retval |= 1;
31668 +               }
31669 +               if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
31670 +                       CLEAR_GPWRDN_INTR(core_if, lnstschng);
31671 +                       /* remote wakeup from hibernation */
31672 +                       if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
31673 +                               dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
31674 +                       } else {
31675 +                               DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
31676 +                       }
31677 +                       retval |= 1;
31678 +               }
31679 +               if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
31680 +                       CLEAR_GPWRDN_INTR(core_if, rst_det);
31681 +                       if (gpwrdn.b.linestate == 0) {
31682 +                               DWC_PRINTF("Reset detected\n");
31683 +                               retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
31684 +                       }
31685 +               }
31686 +               if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
31687 +                       CLEAR_GPWRDN_INTR(core_if, srp_det);
31688 +                       dwc_otg_handle_pwrdn_srp_intr(core_if);
31689 +                       retval |= 1;
31690 +               }
31691 +       }
31692 +       /* Handle ADP interrupt here */
31693 +       if (gpwrdn.b.adp_int) {
31694 +               DWC_PRINTF("ADP interrupt\n");
31695 +               CLEAR_GPWRDN_INTR(core_if, adp_int);
31696 +               dwc_otg_adp_handle_intr(core_if);
31697 +               retval |= 1;
31698 +       }
31699 +       if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
31700 +               DWC_PRINTF("STS CHNG interrupt asserted\n");
31701 +               CLEAR_GPWRDN_INTR(core_if, sts_chngint);
31702 +               dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
31703 +
31704 +               retval |= 1;
31705 +       }
31706 +       if (core_if->lock)
31707 +               DWC_SPINUNLOCK(core_if->lock);
31708 +       return retval;
31709 +}
31710 --- /dev/null
31711 +++ b/drivers/usb/host/dwc_otg/dwc_otg_core_if.h
31712 @@ -0,0 +1,705 @@
31713 +/* ==========================================================================
31714 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
31715 + * $Revision: #13 $
31716 + * $Date: 2012/08/10 $
31717 + * $Change: 2047372 $
31718 + *
31719 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
31720 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
31721 + * otherwise expressly agreed to in writing between Synopsys and you.
31722 + *
31723 + * The Software IS NOT an item of Licensed Software or Licensed Product under
31724 + * any End User Software License Agreement or Agreement for Licensed Product
31725 + * with Synopsys or any supplement thereto. You are permitted to use and
31726 + * redistribute this Software in source and binary forms, with or without
31727 + * modification, provided that redistributions of source code must retain this
31728 + * notice. You may not view, use, disclose, copy or distribute this file or
31729 + * any information contained herein except pursuant to this license grant from
31730 + * Synopsys. If you do not agree with this notice, including the disclaimer
31731 + * below, then you are not authorized to use the Software.
31732 + *
31733 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
31734 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31735 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31736 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
31737 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31738 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31739 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31740 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31741 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31742 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31743 + * DAMAGE.
31744 + * ========================================================================== */
31745 +#if !defined(__DWC_CORE_IF_H__)
31746 +#define __DWC_CORE_IF_H__
31747 +
31748 +#include "dwc_os.h"
31749 +
31750 +/** @file
31751 + * This file defines DWC_OTG Core API
31752 + */
31753 +
31754 +struct dwc_otg_core_if;
31755 +typedef struct dwc_otg_core_if dwc_otg_core_if_t;
31756 +
31757 +/** Maximum number of Periodic FIFOs */
31758 +#define MAX_PERIO_FIFOS 15
31759 +/** Maximum number of Periodic FIFOs */
31760 +#define MAX_TX_FIFOS 15
31761 +
31762 +/** Maximum number of Endpoints/HostChannels */
31763 +#define MAX_EPS_CHANNELS 16
31764 +
31765 +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
31766 +extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
31767 +extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
31768 +
31769 +extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
31770 +extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
31771 +
31772 +extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
31773 +extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
31774 +
31775 +extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
31776 +
31777 +/** This function should be called on every hardware interrupt. */
31778 +extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
31779 +
31780 +/** @name OTG Core Parameters */
31781 +/** @{ */
31782 +
31783 +/**
31784 + * Specifies the OTG capabilities. The driver will automatically
31785 + * detect the value for this parameter if none is specified.
31786 + * 0 - HNP and SRP capable (default)
31787 + * 1 - SRP Only capable
31788 + * 2 - No HNP/SRP capable
31789 + */
31790 +extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
31791 +extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
31792 +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
31793 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
31794 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
31795 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
31796 +
31797 +extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
31798 +extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
31799 +#define dwc_param_opt_default 1
31800 +
31801 +/**
31802 + * Specifies whether to use slave or DMA mode for accessing the data
31803 + * FIFOs. The driver will automatically detect the value for this
31804 + * parameter if none is specified.
31805 + * 0 - Slave
31806 + * 1 - DMA (default, if available)
31807 + */
31808 +extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
31809 +                                       int32_t val);
31810 +extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
31811 +#define dwc_param_dma_enable_default 1
31812 +
31813 +/**
31814 + * When DMA mode is enabled specifies whether to use
31815 + * address DMA or DMA Descritor mode for accessing the data
31816 + * FIFOs in device mode. The driver will automatically detect
31817 + * the value for this parameter if none is specified.
31818 + * 0 - address DMA
31819 + * 1 - DMA Descriptor(default, if available)
31820 + */
31821 +extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
31822 +                                            int32_t val);
31823 +extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
31824 +//#define dwc_param_dma_desc_enable_default 1
31825 +#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708
31826 +
31827 +/** The DMA Burst size (applicable only for External DMA
31828 + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
31829 + */
31830 +extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
31831 +                                           int32_t val);
31832 +extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
31833 +#define dwc_param_dma_burst_size_default 32
31834 +
31835 +/**
31836 + * Specifies the maximum speed of operation in host and device mode.
31837 + * The actual speed depends on the speed of the attached device and
31838 + * the value of phy_type. The actual speed depends on the speed of the
31839 + * attached device.
31840 + * 0 - High Speed (default)
31841 + * 1 - Full Speed
31842 + */
31843 +extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
31844 +extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
31845 +#define dwc_param_speed_default 0
31846 +#define DWC_SPEED_PARAM_HIGH 0
31847 +#define DWC_SPEED_PARAM_FULL 1
31848 +
31849 +/** Specifies whether low power mode is supported when attached
31850 + *     to a Full Speed or Low Speed device in host mode.
31851 + * 0 - Don't support low power mode (default)
31852 + * 1 - Support low power mode
31853 + */
31854 +extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
31855 +                                                         core_if, int32_t val);
31856 +extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
31857 +                                                             * core_if);
31858 +#define dwc_param_host_support_fs_ls_low_power_default 0
31859 +
31860 +/** Specifies the PHY clock rate in low power mode when connected to a
31861 + * Low Speed device in host mode. This parameter is applicable only if
31862 + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
31863 + * then defaults to 6 MHZ otherwise 48 MHZ.
31864 + *
31865 + * 0 - 48 MHz
31866 + * 1 - 6 MHz
31867 + */
31868 +extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
31869 +                                                      core_if, int32_t val);
31870 +extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
31871 +                                                          core_if);
31872 +#define dwc_param_host_ls_low_power_phy_clk_default 0
31873 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
31874 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
31875 +
31876 +/**
31877 + * 0 - Use cC FIFO size parameters
31878 + * 1 - Allow dynamic FIFO sizing (default)
31879 + */
31880 +extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
31881 +                                                int32_t val);
31882 +extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
31883 +                                                    core_if);
31884 +#define dwc_param_enable_dynamic_fifo_default 1
31885 +
31886 +/** Total number of 4-byte words in the data FIFO memory. This
31887 + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
31888 + * Tx FIFOs.
31889 + * 32 to 32768 (default 8192)
31890 + * Note: The total FIFO memory depth in the FPGA configuration is 8192.
31891 + */
31892 +extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
31893 +                                           int32_t val);
31894 +extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
31895 +//#define dwc_param_data_fifo_size_default 8192
31896 +#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708
31897 +
31898 +/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
31899 + * FIFO sizing is enabled.
31900 + * 16 to 32768 (default 1064)
31901 + */
31902 +extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
31903 +                                             int32_t val);
31904 +extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
31905 +#define dwc_param_dev_rx_fifo_size_default 1064
31906 +
31907 +/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
31908 + * when dynamic FIFO sizing is enabled.
31909 + * 16 to 32768 (default 1024)
31910 + */
31911 +extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
31912 +                                                    core_if, int32_t val);
31913 +extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
31914 +                                                        core_if);
31915 +#define dwc_param_dev_nperio_tx_fifo_size_default 1024
31916 +
31917 +/** Number of 4-byte words in each of the periodic Tx FIFOs in device
31918 + * mode when dynamic FIFO sizing is enabled.
31919 + * 4 to 768 (default 256)
31920 + */
31921 +extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
31922 +                                                   int32_t val, int fifo_num);
31923 +extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
31924 +                                                       core_if, int fifo_num);
31925 +#define dwc_param_dev_perio_tx_fifo_size_default 256
31926 +
31927 +/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
31928 + * FIFO sizing is enabled.
31929 + * 16 to 32768 (default 1024)
31930 + */
31931 +extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
31932 +                                              int32_t val);
31933 +extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
31934 +//#define dwc_param_host_rx_fifo_size_default 1024
31935 +#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708
31936 +
31937 +/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
31938 + * when Dynamic FIFO sizing is enabled in the core.
31939 + * 16 to 32768 (default 1024)
31940 + */
31941 +extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
31942 +                                                     core_if, int32_t val);
31943 +extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
31944 +                                                         core_if);
31945 +//#define dwc_param_host_nperio_tx_fifo_size_default 1024
31946 +#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708
31947 +
31948 +/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
31949 + * FIFO sizing is enabled.
31950 + * 16 to 32768 (default 1024)
31951 + */
31952 +extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
31953 +                                                    core_if, int32_t val);
31954 +extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
31955 +                                                        core_if);
31956 +//#define dwc_param_host_perio_tx_fifo_size_default 1024
31957 +#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708
31958 +
31959 +/** The maximum transfer size supported in bytes.
31960 + * 2047 to 65,535  (default 65,535)
31961 + */
31962 +extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
31963 +                                              int32_t val);
31964 +extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
31965 +#define dwc_param_max_transfer_size_default 65535
31966 +
31967 +/** The maximum number of packets in a transfer.
31968 + * 15 to 511  (default 511)
31969 + */
31970 +extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
31971 +                                             int32_t val);
31972 +extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
31973 +#define dwc_param_max_packet_count_default 511
31974 +
31975 +/** The number of host channel registers to use.
31976 + * 1 to 16 (default 12)
31977 + * Note: The FPGA configuration supports a maximum of 12 host channels.
31978 + */
31979 +extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
31980 +                                          int32_t val);
31981 +extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
31982 +//#define dwc_param_host_channels_default 12
31983 +#define dwc_param_host_channels_default 8 // Broadcom BCM2708
31984 +
31985 +/** The number of endpoints in addition to EP0 available for device
31986 + * mode operations.
31987 + * 1 to 15 (default 6 IN and OUT)
31988 + * Note: The FPGA configuration supports a maximum of 6 IN and OUT
31989 + * endpoints in addition to EP0.
31990 + */
31991 +extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
31992 +                                          int32_t val);
31993 +extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
31994 +#define dwc_param_dev_endpoints_default 6
31995 +
31996 +/**
31997 + * Specifies the type of PHY interface to use. By default, the driver
31998 + * will automatically detect the phy_type.
31999 + *
32000 + * 0 - Full Speed PHY
32001 + * 1 - UTMI+ (default)
32002 + * 2 - ULPI
32003 + */
32004 +extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
32005 +extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
32006 +#define DWC_PHY_TYPE_PARAM_FS 0
32007 +#define DWC_PHY_TYPE_PARAM_UTMI 1
32008 +#define DWC_PHY_TYPE_PARAM_ULPI 2
32009 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
32010 +
32011 +/**
32012 + * Specifies the UTMI+ Data Width. This parameter is
32013 + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
32014 + * PHY_TYPE, this parameter indicates the data width between
32015 + * the MAC and the ULPI Wrapper.) Also, this parameter is
32016 + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
32017 + * to "8 and 16 bits", meaning that the core has been
32018 + * configured to work at either data path width.
32019 + *
32020 + * 8 or 16 bits (default 16)
32021 + */
32022 +extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
32023 +                                           int32_t val);
32024 +extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
32025 +//#define dwc_param_phy_utmi_width_default 16
32026 +#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708
32027 +
32028 +/**
32029 + * Specifies whether the ULPI operates at double or single
32030 + * data rate. This parameter is only applicable if PHY_TYPE is
32031 + * ULPI.
32032 + *
32033 + * 0 - single data rate ULPI interface with 8 bit wide data
32034 + * bus (default)
32035 + * 1 - double data rate ULPI interface with 4 bit wide data
32036 + * bus
32037 + */
32038 +extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
32039 +                                         int32_t val);
32040 +extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
32041 +#define dwc_param_phy_ulpi_ddr_default 0
32042 +
32043 +/**
32044 + * Specifies whether to use the internal or external supply to
32045 + * drive the vbus with a ULPI phy.
32046 + */
32047 +extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
32048 +                                              int32_t val);
32049 +extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
32050 +#define DWC_PHY_ULPI_INTERNAL_VBUS 0
32051 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
32052 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
32053 +
32054 +/**
32055 + * Specifies whether to use the I2Cinterface for full speed PHY. This
32056 + * parameter is only applicable if PHY_TYPE is FS.
32057 + * 0 - No (default)
32058 + * 1 - Yes
32059 + */
32060 +extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
32061 +                                       int32_t val);
32062 +extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
32063 +#define dwc_param_i2c_enable_default 0
32064 +
32065 +extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
32066 +                                       int32_t val);
32067 +extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
32068 +#define dwc_param_ulpi_fs_ls_default 0
32069 +
32070 +extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
32071 +extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
32072 +#define dwc_param_ts_dline_default 0
32073 +
32074 +/**
32075 + * Specifies whether dedicated transmit FIFOs are
32076 + * enabled for non periodic IN endpoints in device mode
32077 + * 0 - No
32078 + * 1 - Yes
32079 + */
32080 +extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
32081 +                                                int32_t val);
32082 +extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
32083 +                                                    core_if);
32084 +#define dwc_param_en_multiple_tx_fifo_default 1
32085 +
32086 +/** Number of 4-byte words in each of the Tx FIFOs in device
32087 + * mode when dynamic FIFO sizing is enabled.
32088 + * 4 to 768 (default 256)
32089 + */
32090 +extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
32091 +                                             int fifo_num, int32_t val);
32092 +extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
32093 +                                                 int fifo_num);
32094 +#define dwc_param_dev_tx_fifo_size_default 768
32095 +
32096 +/** Thresholding enable flag-
32097 + * bit 0 - enable non-ISO Tx thresholding
32098 + * bit 1 - enable ISO Tx thresholding
32099 + * bit 2 - enable Rx thresholding
32100 + */
32101 +extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
32102 +extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
32103 +#define dwc_param_thr_ctl_default 0
32104 +
32105 +/** Thresholding length for Tx
32106 + * FIFOs in 32 bit DWORDs
32107 + */
32108 +extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
32109 +                                          int32_t val);
32110 +extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
32111 +#define dwc_param_tx_thr_length_default 64
32112 +
32113 +/** Thresholding length for Rx
32114 + *     FIFOs in 32 bit DWORDs
32115 + */
32116 +extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
32117 +                                          int32_t val);
32118 +extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
32119 +#define dwc_param_rx_thr_length_default 64
32120 +
32121 +/**
32122 + * Specifies whether LPM (Link Power Management) support is enabled
32123 + */
32124 +extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
32125 +                                       int32_t val);
32126 +extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
32127 +#define dwc_param_lpm_enable_default 1
32128 +
32129 +/**
32130 + * Specifies whether PTI enhancement is enabled
32131 + */
32132 +extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
32133 +                                       int32_t val);
32134 +extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
32135 +#define dwc_param_pti_enable_default 0
32136 +
32137 +/**
32138 + * Specifies whether MPI enhancement is enabled
32139 + */
32140 +extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
32141 +                                       int32_t val);
32142 +extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
32143 +#define dwc_param_mpi_enable_default 0
32144 +
32145 +/**
32146 + * Specifies whether ADP capability is enabled
32147 + */
32148 +extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
32149 +                                       int32_t val);
32150 +extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
32151 +#define dwc_param_adp_enable_default 0
32152 +
32153 +/**
32154 + * Specifies whether IC_USB capability is enabled
32155 + */
32156 +
32157 +extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
32158 +                                       int32_t val);
32159 +extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
32160 +#define dwc_param_ic_usb_cap_default 0
32161 +
32162 +extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
32163 +                                          int32_t val);
32164 +extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
32165 +#define dwc_param_ahb_thr_ratio_default 0
32166 +
32167 +extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
32168 +                                       int32_t val);
32169 +extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
32170 +#define dwc_param_power_down_default 0
32171 +
32172 +extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
32173 +                                       int32_t val);
32174 +extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
32175 +#define dwc_param_reload_ctl_default 0
32176 +
32177 +extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
32178 +                                                                               int32_t val);
32179 +extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
32180 +#define dwc_param_dev_out_nak_default 0
32181 +
32182 +extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
32183 +                                                                                int32_t val);
32184 +extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
32185 +#define dwc_param_cont_on_bna_default 0
32186 +
32187 +extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
32188 +                                                                                int32_t val);
32189 +extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
32190 +#define dwc_param_ahb_single_default 0
32191 +
32192 +extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
32193 +extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
32194 +#define dwc_param_otg_ver_default 0
32195 +
32196 +/** @} */
32197 +
32198 +/** @name Access to registers and bit-fields */
32199 +
32200 +/**
32201 + * Dump core registers and SPRAM
32202 + */
32203 +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
32204 +extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
32205 +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
32206 +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
32207 +
32208 +/**
32209 + * Get host negotiation status.
32210 + */
32211 +extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
32212 +
32213 +/**
32214 + * Get srp status
32215 + */
32216 +extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
32217 +
32218 +/**
32219 + * Set hnpreq bit in the GOTGCTL register.
32220 + */
32221 +extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
32222 +
32223 +/**
32224 + * Get Content of SNPSID register.
32225 + */
32226 +extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
32227 +
32228 +/**
32229 + * Get current mode.
32230 + * Returns 0 if in device mode, and 1 if in host mode.
32231 + */
32232 +extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
32233 +
32234 +/**
32235 + * Get value of hnpcapable field in the GUSBCFG register
32236 + */
32237 +extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
32238 +/**
32239 + * Set value of hnpcapable field in the GUSBCFG register
32240 + */
32241 +extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
32242 +
32243 +/**
32244 + * Get value of srpcapable field in the GUSBCFG register
32245 + */
32246 +extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
32247 +/**
32248 + * Set value of srpcapable field in the GUSBCFG register
32249 + */
32250 +extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
32251 +
32252 +/**
32253 + * Get value of devspeed field in the DCFG register
32254 + */
32255 +extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
32256 +/**
32257 + * Set value of devspeed field in the DCFG register
32258 + */
32259 +extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
32260 +
32261 +/**
32262 + * Get the value of busconnected field from the HPRT0 register
32263 + */
32264 +extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
32265 +
32266 +/**
32267 + * Gets the device enumeration Speed.
32268 + */
32269 +extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
32270 +
32271 +/**
32272 + * Get value of prtpwr field from the HPRT0 register
32273 + */
32274 +extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
32275 +
32276 +/**
32277 + * Get value of flag indicating core state - hibernated or not
32278 + */
32279 +extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
32280 +
32281 +/**
32282 + * Set value of prtpwr field from the HPRT0 register
32283 + */
32284 +extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
32285 +
32286 +/**
32287 + * Get value of prtsusp field from the HPRT0 regsiter
32288 + */
32289 +extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
32290 +/**
32291 + * Set value of prtpwr field from the HPRT0 register
32292 + */
32293 +extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
32294 +
32295 +/**
32296 + * Get value of ModeChTimEn field from the HCFG regsiter
32297 + */
32298 +extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
32299 +/**
32300 + * Set value of ModeChTimEn field from the HCFG regsiter
32301 + */
32302 +extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
32303 +
32304 +/**
32305 + * Get value of Fram Interval field from the HFIR regsiter
32306 + */
32307 +extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
32308 +/**
32309 + * Set value of Frame Interval field from the HFIR regsiter
32310 + */
32311 +extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
32312 +
32313 +/**
32314 + * Set value of prtres field from the HPRT0 register
32315 + *FIXME Remove?
32316 + */
32317 +extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
32318 +
32319 +/**
32320 + * Get value of rmtwkupsig bit in DCTL register
32321 + */
32322 +extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
32323 +
32324 +/**
32325 + * Get value of prt_sleep_sts field from the GLPMCFG register
32326 + */
32327 +extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
32328 +
32329 +/**
32330 + * Get value of rem_wkup_en field from the GLPMCFG register
32331 + */
32332 +extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
32333 +
32334 +/**
32335 + * Get value of appl_resp field from the GLPMCFG register
32336 + */
32337 +extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
32338 +/**
32339 + * Set value of appl_resp field from the GLPMCFG register
32340 + */
32341 +extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
32342 +
32343 +/**
32344 + * Get value of hsic_connect field from the GLPMCFG register
32345 + */
32346 +extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
32347 +/**
32348 + * Set value of hsic_connect field from the GLPMCFG register
32349 + */
32350 +extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
32351 +
32352 +/**
32353 + * Get value of inv_sel_hsic field from the GLPMCFG register.
32354 + */
32355 +extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
32356 +/**
32357 + * Set value of inv_sel_hsic field from the GLPMFG register.
32358 + */
32359 +extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
32360 +
32361 +/*
32362 + * Some functions for accessing registers
32363 + */
32364 +
32365 +/**
32366 + *  GOTGCTL register
32367 + */
32368 +extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
32369 +extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
32370 +
32371 +/**
32372 + * GUSBCFG register
32373 + */
32374 +extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
32375 +extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
32376 +
32377 +/**
32378 + * GRXFSIZ register
32379 + */
32380 +extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
32381 +extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
32382 +
32383 +/**
32384 + * GNPTXFSIZ register
32385 + */
32386 +extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
32387 +extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
32388 +
32389 +extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
32390 +extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
32391 +
32392 +/**
32393 + * GGPIO register
32394 + */
32395 +extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
32396 +extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
32397 +
32398 +/**
32399 + * GUID register
32400 + */
32401 +extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
32402 +extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
32403 +
32404 +/**
32405 + * HPRT0 register
32406 + */
32407 +extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
32408 +extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
32409 +
32410 +/**
32411 + * GHPTXFSIZE
32412 + */
32413 +extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
32414 +
32415 +/** @} */
32416 +
32417 +#endif                         /* __DWC_CORE_IF_H__ */
32418 --- /dev/null
32419 +++ b/drivers/usb/host/dwc_otg/dwc_otg_dbg.h
32420 @@ -0,0 +1,117 @@
32421 +/* ==========================================================================
32422 + *
32423 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
32424 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
32425 + * otherwise expressly agreed to in writing between Synopsys and you.
32426 + *
32427 + * The Software IS NOT an item of Licensed Software or Licensed Product under
32428 + * any End User Software License Agreement or Agreement for Licensed Product
32429 + * with Synopsys or any supplement thereto. You are permitted to use and
32430 + * redistribute this Software in source and binary forms, with or without
32431 + * modification, provided that redistributions of source code must retain this
32432 + * notice. You may not view, use, disclose, copy or distribute this file or
32433 + * any information contained herein except pursuant to this license grant from
32434 + * Synopsys. If you do not agree with this notice, including the disclaimer
32435 + * below, then you are not authorized to use the Software.
32436 + *
32437 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
32438 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32439 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32440 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
32441 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32442 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32443 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32444 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32445 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32446 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32447 + * DAMAGE.
32448 + * ========================================================================== */
32449 +
32450 +#ifndef __DWC_OTG_DBG_H__
32451 +#define __DWC_OTG_DBG_H__
32452 +
32453 +/** @file
32454 + * This file defines debug levels.
32455 + * Debugging support vanishes in non-debug builds.
32456 + */
32457 +
32458 +/**
32459 + * The Debug Level bit-mask variable.
32460 + */
32461 +extern uint32_t g_dbg_lvl;
32462 +/**
32463 + * Set the Debug Level variable.
32464 + */
32465 +static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
32466 +{
32467 +       uint32_t old = g_dbg_lvl;
32468 +       g_dbg_lvl = new;
32469 +       return old;
32470 +}
32471 +
32472 +#define DBG_USER       (0x1)
32473 +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
32474 +#define DBG_CIL                (0x2)
32475 +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
32476 + * messages */
32477 +#define DBG_CILV       (0x20)
32478 +/**  When debug level has the DBG_PCD bit set, display PCD (Device) debug
32479 + *  messages */
32480 +#define DBG_PCD                (0x4)
32481 +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
32482 + * messages */
32483 +#define DBG_PCDV       (0x40)
32484 +/** When debug level has the DBG_HCD bit set, display Host debug messages */
32485 +#define DBG_HCD                (0x8)
32486 +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
32487 + * messages */
32488 +#define DBG_HCDV       (0x80)
32489 +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
32490 + *  mode. */
32491 +#define DBG_HCD_URB    (0x800)
32492 +/** When debug level has the DBG_HCDI bit set, display host interrupt
32493 + *  messages. */
32494 +#define DBG_HCDI       (0x1000)
32495 +
32496 +/** When debug level has any bit set, display debug messages */
32497 +#define DBG_ANY                (0xFF)
32498 +
32499 +/** All debug messages off */
32500 +#define DBG_OFF                0
32501 +
32502 +/** Prefix string for DWC_DEBUG print macros. */
32503 +#define USB_DWC "DWC_otg: "
32504 +
32505 +/**
32506 + * Print a debug message when the Global debug level variable contains
32507 + * the bit defined in <code>lvl</code>.
32508 + *
32509 + * @param[in] lvl - Debug level, use one of the DBG_ constants above.
32510 + * @param[in] x - like printf
32511 + *
32512 + *    Example:<p>
32513 + * <code>
32514 + *      DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
32515 + * </code>
32516 + * <br>
32517 + * results in:<br>
32518 + * <code>
32519 + * usb-DWC_otg: dwc_otg_cil_init(ca867000)
32520 + * </code>
32521 + */
32522 +#ifdef DEBUG
32523 +
32524 +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
32525 +# define DWC_DEBUGP(x...)      DWC_DEBUGPL(DBG_ANY, x )
32526 +
32527 +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
32528 +
32529 +#else
32530 +
32531 +# define DWC_DEBUGPL(lvl, x...) do{}while(0)
32532 +# define DWC_DEBUGP(x...)
32533 +
32534 +# define CHK_DEBUG_LEVEL(level) (0)
32535 +
32536 +#endif /*DEBUG*/
32537 +#endif
32538 --- /dev/null
32539 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c
32540 @@ -0,0 +1,1757 @@
32541 +/* ==========================================================================
32542 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
32543 + * $Revision: #92 $
32544 + * $Date: 2012/08/10 $
32545 + * $Change: 2047372 $
32546 + *
32547 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
32548 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
32549 + * otherwise expressly agreed to in writing between Synopsys and you.
32550 + *
32551 + * The Software IS NOT an item of Licensed Software or Licensed Product under
32552 + * any End User Software License Agreement or Agreement for Licensed Product
32553 + * with Synopsys or any supplement thereto. You are permitted to use and
32554 + * redistribute this Software in source and binary forms, with or without
32555 + * modification, provided that redistributions of source code must retain this
32556 + * notice. You may not view, use, disclose, copy or distribute this file or
32557 + * any information contained herein except pursuant to this license grant from
32558 + * Synopsys. If you do not agree with this notice, including the disclaimer
32559 + * below, then you are not authorized to use the Software.
32560 + *
32561 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
32562 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32563 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32564 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
32565 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32566 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32567 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
32568 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32569 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32570 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32571 + * DAMAGE.
32572 + * ========================================================================== */
32573 +
32574 +/** @file
32575 + * The dwc_otg_driver module provides the initialization and cleanup entry
32576 + * points for the DWC_otg driver. This module will be dynamically installed
32577 + * after Linux is booted using the insmod command. When the module is
32578 + * installed, the dwc_otg_driver_init function is called. When the module is
32579 + * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
32580 + *
32581 + * This module also defines a data structure for the dwc_otg_driver, which is
32582 + * used in conjunction with the standard ARM lm_device structure. These
32583 + * structures allow the OTG driver to comply with the standard Linux driver
32584 + * model in which devices and drivers are registered with a bus driver. This
32585 + * has the benefit that Linux can expose attributes of the driver and device
32586 + * in its special sysfs file system. Users can then read or write files in
32587 + * this file system to perform diagnostics on the driver components or the
32588 + * device.
32589 + */
32590 +
32591 +#include "dwc_otg_os_dep.h"
32592 +#include "dwc_os.h"
32593 +#include "dwc_otg_dbg.h"
32594 +#include "dwc_otg_driver.h"
32595 +#include "dwc_otg_attr.h"
32596 +#include "dwc_otg_core_if.h"
32597 +#include "dwc_otg_pcd_if.h"
32598 +#include "dwc_otg_hcd_if.h"
32599 +#include "dwc_otg_fiq_fsm.h"
32600 +
32601 +#define DWC_DRIVER_VERSION     "3.00a 10-AUG-2012"
32602 +#define DWC_DRIVER_DESC                "HS OTG USB Controller driver"
32603 +
32604 +bool microframe_schedule=true;
32605 +
32606 +static const char dwc_driver_name[] = "dwc_otg";
32607 +
32608 +
32609 +extern int pcd_init(
32610 +#ifdef LM_INTERFACE
32611 +                          struct lm_device *_dev
32612 +#elif  defined(PCI_INTERFACE)
32613 +                          struct pci_dev *_dev
32614 +#elif  defined(PLATFORM_INTERFACE)
32615 +       struct platform_device *dev
32616 +#endif
32617 +    );
32618 +extern int hcd_init(
32619 +#ifdef LM_INTERFACE
32620 +                          struct lm_device *_dev
32621 +#elif  defined(PCI_INTERFACE)
32622 +                          struct pci_dev *_dev
32623 +#elif  defined(PLATFORM_INTERFACE)
32624 +       struct platform_device *dev
32625 +#endif
32626 +    );
32627 +
32628 +extern int pcd_remove(
32629 +#ifdef LM_INTERFACE
32630 +                            struct lm_device *_dev
32631 +#elif  defined(PCI_INTERFACE)
32632 +                            struct pci_dev *_dev
32633 +#elif  defined(PLATFORM_INTERFACE)
32634 +       struct platform_device *_dev
32635 +#endif
32636 +    );
32637 +
32638 +extern void hcd_remove(
32639 +#ifdef LM_INTERFACE
32640 +                             struct lm_device *_dev
32641 +#elif  defined(PCI_INTERFACE)
32642 +                             struct pci_dev *_dev
32643 +#elif  defined(PLATFORM_INTERFACE)
32644 +       struct platform_device *_dev
32645 +#endif
32646 +    );
32647 +
32648 +extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
32649 +
32650 +/*-------------------------------------------------------------------------*/
32651 +/* Encapsulate the module parameter settings */
32652 +
32653 +struct dwc_otg_driver_module_params {
32654 +       int32_t opt;
32655 +       int32_t otg_cap;
32656 +       int32_t dma_enable;
32657 +       int32_t dma_desc_enable;
32658 +       int32_t dma_burst_size;
32659 +       int32_t speed;
32660 +       int32_t host_support_fs_ls_low_power;
32661 +       int32_t host_ls_low_power_phy_clk;
32662 +       int32_t enable_dynamic_fifo;
32663 +       int32_t data_fifo_size;
32664 +       int32_t dev_rx_fifo_size;
32665 +       int32_t dev_nperio_tx_fifo_size;
32666 +       uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
32667 +       int32_t host_rx_fifo_size;
32668 +       int32_t host_nperio_tx_fifo_size;
32669 +       int32_t host_perio_tx_fifo_size;
32670 +       int32_t max_transfer_size;
32671 +       int32_t max_packet_count;
32672 +       int32_t host_channels;
32673 +       int32_t dev_endpoints;
32674 +       int32_t phy_type;
32675 +       int32_t phy_utmi_width;
32676 +       int32_t phy_ulpi_ddr;
32677 +       int32_t phy_ulpi_ext_vbus;
32678 +       int32_t i2c_enable;
32679 +       int32_t ulpi_fs_ls;
32680 +       int32_t ts_dline;
32681 +       int32_t en_multiple_tx_fifo;
32682 +       uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
32683 +       uint32_t thr_ctl;
32684 +       uint32_t tx_thr_length;
32685 +       uint32_t rx_thr_length;
32686 +       int32_t pti_enable;
32687 +       int32_t mpi_enable;
32688 +       int32_t lpm_enable;
32689 +       int32_t ic_usb_cap;
32690 +       int32_t ahb_thr_ratio;
32691 +       int32_t power_down;
32692 +       int32_t reload_ctl;
32693 +       int32_t dev_out_nak;
32694 +       int32_t cont_on_bna;
32695 +       int32_t ahb_single;
32696 +       int32_t otg_ver;
32697 +       int32_t adp_enable;
32698 +};
32699 +
32700 +static struct dwc_otg_driver_module_params dwc_otg_module_params = {
32701 +       .opt = -1,
32702 +       .otg_cap = -1,
32703 +       .dma_enable = -1,
32704 +       .dma_desc_enable = -1,
32705 +       .dma_burst_size = -1,
32706 +       .speed = -1,
32707 +       .host_support_fs_ls_low_power = -1,
32708 +       .host_ls_low_power_phy_clk = -1,
32709 +       .enable_dynamic_fifo = -1,
32710 +       .data_fifo_size = -1,
32711 +       .dev_rx_fifo_size = -1,
32712 +       .dev_nperio_tx_fifo_size = -1,
32713 +       .dev_perio_tx_fifo_size = {
32714 +                                  /* dev_perio_tx_fifo_size_1 */
32715 +                                  -1,
32716 +                                  -1,
32717 +                                  -1,
32718 +                                  -1,
32719 +                                  -1,
32720 +                                  -1,
32721 +                                  -1,
32722 +                                  -1,
32723 +                                  -1,
32724 +                                  -1,
32725 +                                  -1,
32726 +                                  -1,
32727 +                                  -1,
32728 +                                  -1,
32729 +                                  -1
32730 +                                  /* 15 */
32731 +                                  },
32732 +       .host_rx_fifo_size = -1,
32733 +       .host_nperio_tx_fifo_size = -1,
32734 +       .host_perio_tx_fifo_size = -1,
32735 +       .max_transfer_size = -1,
32736 +       .max_packet_count = -1,
32737 +       .host_channels = -1,
32738 +       .dev_endpoints = -1,
32739 +       .phy_type = -1,
32740 +       .phy_utmi_width = -1,
32741 +       .phy_ulpi_ddr = -1,
32742 +       .phy_ulpi_ext_vbus = -1,
32743 +       .i2c_enable = -1,
32744 +       .ulpi_fs_ls = -1,
32745 +       .ts_dline = -1,
32746 +       .en_multiple_tx_fifo = -1,
32747 +       .dev_tx_fifo_size = {
32748 +                            /* dev_tx_fifo_size */
32749 +                            -1,
32750 +                            -1,
32751 +                            -1,
32752 +                            -1,
32753 +                            -1,
32754 +                            -1,
32755 +                            -1,
32756 +                            -1,
32757 +                            -1,
32758 +                            -1,
32759 +                            -1,
32760 +                            -1,
32761 +                            -1,
32762 +                            -1,
32763 +                            -1
32764 +                            /* 15 */
32765 +                            },
32766 +       .thr_ctl = -1,
32767 +       .tx_thr_length = -1,
32768 +       .rx_thr_length = -1,
32769 +       .pti_enable = -1,
32770 +       .mpi_enable = -1,
32771 +       .lpm_enable = 0,
32772 +       .ic_usb_cap = -1,
32773 +       .ahb_thr_ratio = -1,
32774 +       .power_down = -1,
32775 +       .reload_ctl = -1,
32776 +       .dev_out_nak = -1,
32777 +       .cont_on_bna = -1,
32778 +       .ahb_single = -1,
32779 +       .otg_ver = -1,
32780 +       .adp_enable = -1,
32781 +};
32782 +
32783 +//Global variable to switch the fiq fix on or off
32784 +bool fiq_enable = 1;
32785 +// Global variable to enable the split transaction fix
32786 +bool fiq_fsm_enable = true;
32787 +//Bulk split-transaction NAK holdoff in microframes
32788 +uint16_t nak_holdoff = 8;
32789 +
32790 +unsigned short fiq_fsm_mask = 0x07;
32791 +
32792 +/**
32793 + * This function shows the Driver Version.
32794 + */
32795 +static ssize_t version_show(struct device_driver *dev, char *buf)
32796 +{
32797 +       return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
32798 +                       DWC_DRIVER_VERSION);
32799 +}
32800 +
32801 +static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
32802 +
32803 +/**
32804 + * Global Debug Level Mask.
32805 + */
32806 +uint32_t g_dbg_lvl = 0;                /* OFF */
32807 +
32808 +/**
32809 + * This function shows the driver Debug Level.
32810 + */
32811 +static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
32812 +{
32813 +       return sprintf(buf, "0x%0x\n", g_dbg_lvl);
32814 +}
32815 +
32816 +/**
32817 + * This function stores the driver Debug Level.
32818 + */
32819 +static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
32820 +                              size_t count)
32821 +{
32822 +       g_dbg_lvl = simple_strtoul(buf, NULL, 16);
32823 +       return count;
32824 +}
32825 +
32826 +static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
32827 +                  dbg_level_store);
32828 +
32829 +/**
32830 + * This function is called during module intialization
32831 + * to pass module parameters to the DWC_OTG CORE.
32832 + */
32833 +static int set_parameters(dwc_otg_core_if_t * core_if)
32834 +{
32835 +       int retval = 0;
32836 +       int i;
32837 +
32838 +       if (dwc_otg_module_params.otg_cap != -1) {
32839 +               retval +=
32840 +                   dwc_otg_set_param_otg_cap(core_if,
32841 +                                             dwc_otg_module_params.otg_cap);
32842 +       }
32843 +       if (dwc_otg_module_params.dma_enable != -1) {
32844 +               retval +=
32845 +                   dwc_otg_set_param_dma_enable(core_if,
32846 +                                                dwc_otg_module_params.
32847 +                                                dma_enable);
32848 +       }
32849 +       if (dwc_otg_module_params.dma_desc_enable != -1) {
32850 +               retval +=
32851 +                   dwc_otg_set_param_dma_desc_enable(core_if,
32852 +                                                     dwc_otg_module_params.
32853 +                                                     dma_desc_enable);
32854 +       }
32855 +       if (dwc_otg_module_params.opt != -1) {
32856 +               retval +=
32857 +                   dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
32858 +       }
32859 +       if (dwc_otg_module_params.dma_burst_size != -1) {
32860 +               retval +=
32861 +                   dwc_otg_set_param_dma_burst_size(core_if,
32862 +                                                    dwc_otg_module_params.
32863 +                                                    dma_burst_size);
32864 +       }
32865 +       if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
32866 +               retval +=
32867 +                   dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
32868 +                                                                  dwc_otg_module_params.
32869 +                                                                  host_support_fs_ls_low_power);
32870 +       }
32871 +       if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
32872 +               retval +=
32873 +                   dwc_otg_set_param_enable_dynamic_fifo(core_if,
32874 +                                                         dwc_otg_module_params.
32875 +                                                         enable_dynamic_fifo);
32876 +       }
32877 +       if (dwc_otg_module_params.data_fifo_size != -1) {
32878 +               retval +=
32879 +                   dwc_otg_set_param_data_fifo_size(core_if,
32880 +                                                    dwc_otg_module_params.
32881 +                                                    data_fifo_size);
32882 +       }
32883 +       if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
32884 +               retval +=
32885 +                   dwc_otg_set_param_dev_rx_fifo_size(core_if,
32886 +                                                      dwc_otg_module_params.
32887 +                                                      dev_rx_fifo_size);
32888 +       }
32889 +       if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
32890 +               retval +=
32891 +                   dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
32892 +                                                             dwc_otg_module_params.
32893 +                                                             dev_nperio_tx_fifo_size);
32894 +       }
32895 +       if (dwc_otg_module_params.host_rx_fifo_size != -1) {
32896 +               retval +=
32897 +                   dwc_otg_set_param_host_rx_fifo_size(core_if,
32898 +                                                       dwc_otg_module_params.host_rx_fifo_size);
32899 +       }
32900 +       if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
32901 +               retval +=
32902 +                   dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
32903 +                                                              dwc_otg_module_params.
32904 +                                                              host_nperio_tx_fifo_size);
32905 +       }
32906 +       if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
32907 +               retval +=
32908 +                   dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
32909 +                                                             dwc_otg_module_params.
32910 +                                                             host_perio_tx_fifo_size);
32911 +       }
32912 +       if (dwc_otg_module_params.max_transfer_size != -1) {
32913 +               retval +=
32914 +                   dwc_otg_set_param_max_transfer_size(core_if,
32915 +                                                       dwc_otg_module_params.
32916 +                                                       max_transfer_size);
32917 +       }
32918 +       if (dwc_otg_module_params.max_packet_count != -1) {
32919 +               retval +=
32920 +                   dwc_otg_set_param_max_packet_count(core_if,
32921 +                                                      dwc_otg_module_params.
32922 +                                                      max_packet_count);
32923 +       }
32924 +       if (dwc_otg_module_params.host_channels != -1) {
32925 +               retval +=
32926 +                   dwc_otg_set_param_host_channels(core_if,
32927 +                                                   dwc_otg_module_params.
32928 +                                                   host_channels);
32929 +       }
32930 +       if (dwc_otg_module_params.dev_endpoints != -1) {
32931 +               retval +=
32932 +                   dwc_otg_set_param_dev_endpoints(core_if,
32933 +                                                   dwc_otg_module_params.
32934 +                                                   dev_endpoints);
32935 +       }
32936 +       if (dwc_otg_module_params.phy_type != -1) {
32937 +               retval +=
32938 +                   dwc_otg_set_param_phy_type(core_if,
32939 +                                              dwc_otg_module_params.phy_type);
32940 +       }
32941 +       if (dwc_otg_module_params.speed != -1) {
32942 +               retval +=
32943 +                   dwc_otg_set_param_speed(core_if,
32944 +                                           dwc_otg_module_params.speed);
32945 +       }
32946 +       if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
32947 +               retval +=
32948 +                   dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
32949 +                                                               dwc_otg_module_params.
32950 +                                                               host_ls_low_power_phy_clk);
32951 +       }
32952 +       if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
32953 +               retval +=
32954 +                   dwc_otg_set_param_phy_ulpi_ddr(core_if,
32955 +                                                  dwc_otg_module_params.
32956 +                                                  phy_ulpi_ddr);
32957 +       }
32958 +       if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
32959 +               retval +=
32960 +                   dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
32961 +                                                       dwc_otg_module_params.
32962 +                                                       phy_ulpi_ext_vbus);
32963 +       }
32964 +       if (dwc_otg_module_params.phy_utmi_width != -1) {
32965 +               retval +=
32966 +                   dwc_otg_set_param_phy_utmi_width(core_if,
32967 +                                                    dwc_otg_module_params.
32968 +                                                    phy_utmi_width);
32969 +       }
32970 +       if (dwc_otg_module_params.ulpi_fs_ls != -1) {
32971 +               retval +=
32972 +                   dwc_otg_set_param_ulpi_fs_ls(core_if,
32973 +                                                dwc_otg_module_params.ulpi_fs_ls);
32974 +       }
32975 +       if (dwc_otg_module_params.ts_dline != -1) {
32976 +               retval +=
32977 +                   dwc_otg_set_param_ts_dline(core_if,
32978 +                                              dwc_otg_module_params.ts_dline);
32979 +       }
32980 +       if (dwc_otg_module_params.i2c_enable != -1) {
32981 +               retval +=
32982 +                   dwc_otg_set_param_i2c_enable(core_if,
32983 +                                                dwc_otg_module_params.
32984 +                                                i2c_enable);
32985 +       }
32986 +       if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
32987 +               retval +=
32988 +                   dwc_otg_set_param_en_multiple_tx_fifo(core_if,
32989 +                                                         dwc_otg_module_params.
32990 +                                                         en_multiple_tx_fifo);
32991 +       }
32992 +       for (i = 0; i < 15; i++) {
32993 +               if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
32994 +                       retval +=
32995 +                           dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
32996 +                                                                    dwc_otg_module_params.
32997 +                                                                    dev_perio_tx_fifo_size
32998 +                                                                    [i], i);
32999 +               }
33000 +       }
33001 +
33002 +       for (i = 0; i < 15; i++) {
33003 +               if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
33004 +                       retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
33005 +                                                                    dwc_otg_module_params.
33006 +                                                                    dev_tx_fifo_size
33007 +                                                                    [i], i);
33008 +               }
33009 +       }
33010 +       if (dwc_otg_module_params.thr_ctl != -1) {
33011 +               retval +=
33012 +                   dwc_otg_set_param_thr_ctl(core_if,
33013 +                                             dwc_otg_module_params.thr_ctl);
33014 +       }
33015 +       if (dwc_otg_module_params.mpi_enable != -1) {
33016 +               retval +=
33017 +                   dwc_otg_set_param_mpi_enable(core_if,
33018 +                                                dwc_otg_module_params.
33019 +                                                mpi_enable);
33020 +       }
33021 +       if (dwc_otg_module_params.pti_enable != -1) {
33022 +               retval +=
33023 +                   dwc_otg_set_param_pti_enable(core_if,
33024 +                                                dwc_otg_module_params.
33025 +                                                pti_enable);
33026 +       }
33027 +       if (dwc_otg_module_params.lpm_enable != -1) {
33028 +               retval +=
33029 +                   dwc_otg_set_param_lpm_enable(core_if,
33030 +                                                dwc_otg_module_params.
33031 +                                                lpm_enable);
33032 +       }
33033 +       if (dwc_otg_module_params.ic_usb_cap != -1) {
33034 +               retval +=
33035 +                   dwc_otg_set_param_ic_usb_cap(core_if,
33036 +                                                dwc_otg_module_params.
33037 +                                                ic_usb_cap);
33038 +       }
33039 +       if (dwc_otg_module_params.tx_thr_length != -1) {
33040 +               retval +=
33041 +                   dwc_otg_set_param_tx_thr_length(core_if,
33042 +                                                   dwc_otg_module_params.tx_thr_length);
33043 +       }
33044 +       if (dwc_otg_module_params.rx_thr_length != -1) {
33045 +               retval +=
33046 +                   dwc_otg_set_param_rx_thr_length(core_if,
33047 +                                                   dwc_otg_module_params.
33048 +                                                   rx_thr_length);
33049 +       }
33050 +       if (dwc_otg_module_params.ahb_thr_ratio != -1) {
33051 +               retval +=
33052 +                   dwc_otg_set_param_ahb_thr_ratio(core_if,
33053 +                                                   dwc_otg_module_params.ahb_thr_ratio);
33054 +       }
33055 +       if (dwc_otg_module_params.power_down != -1) {
33056 +               retval +=
33057 +                   dwc_otg_set_param_power_down(core_if,
33058 +                                                dwc_otg_module_params.power_down);
33059 +       }
33060 +       if (dwc_otg_module_params.reload_ctl != -1) {
33061 +               retval +=
33062 +                   dwc_otg_set_param_reload_ctl(core_if,
33063 +                                                dwc_otg_module_params.reload_ctl);
33064 +       }
33065 +
33066 +       if (dwc_otg_module_params.dev_out_nak != -1) {
33067 +               retval +=
33068 +                       dwc_otg_set_param_dev_out_nak(core_if,
33069 +                       dwc_otg_module_params.dev_out_nak);
33070 +       }
33071 +
33072 +       if (dwc_otg_module_params.cont_on_bna != -1) {
33073 +               retval +=
33074 +                       dwc_otg_set_param_cont_on_bna(core_if,
33075 +                       dwc_otg_module_params.cont_on_bna);
33076 +       }
33077 +
33078 +       if (dwc_otg_module_params.ahb_single != -1) {
33079 +               retval +=
33080 +                       dwc_otg_set_param_ahb_single(core_if,
33081 +                       dwc_otg_module_params.ahb_single);
33082 +       }
33083 +
33084 +       if (dwc_otg_module_params.otg_ver != -1) {
33085 +               retval +=
33086 +                   dwc_otg_set_param_otg_ver(core_if,
33087 +                                             dwc_otg_module_params.otg_ver);
33088 +       }
33089 +       if (dwc_otg_module_params.adp_enable != -1) {
33090 +               retval +=
33091 +                   dwc_otg_set_param_adp_enable(core_if,
33092 +                                                dwc_otg_module_params.
33093 +                                                adp_enable);
33094 +       }
33095 +       return retval;
33096 +}
33097 +
33098 +/**
33099 + * This function is the top level interrupt handler for the Common
33100 + * (Device and host modes) interrupts.
33101 + */
33102 +static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
33103 +{
33104 +       int32_t retval = IRQ_NONE;
33105 +
33106 +       retval = dwc_otg_handle_common_intr(dev);
33107 +       if (retval != 0) {
33108 +               S3C2410X_CLEAR_EINTPEND();
33109 +       }
33110 +       return IRQ_RETVAL(retval);
33111 +}
33112 +
33113 +/**
33114 + * This function is called when a lm_device is unregistered with the
33115 + * dwc_otg_driver. This happens, for example, when the rmmod command is
33116 + * executed. The device may or may not be electrically present. If it is
33117 + * present, the driver stops device processing. Any resources used on behalf
33118 + * of this device are freed.
33119 + *
33120 + * @param _dev
33121 + */
33122 +#ifdef LM_INTERFACE
33123 +#define REM_RETVAL(n)
33124 +static void dwc_otg_driver_remove(      struct lm_device *_dev )
33125 +{       dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
33126 +#elif  defined(PCI_INTERFACE)
33127 +#define REM_RETVAL(n)
33128 +static void dwc_otg_driver_remove(      struct pci_dev *_dev )
33129 +{      dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
33130 +#elif  defined(PLATFORM_INTERFACE)
33131 +#define REM_RETVAL(n) n
33132 +static int dwc_otg_driver_remove(        struct platform_device *_dev )
33133 +{       dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev);
33134 +#endif
33135 +
33136 +       DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
33137 +
33138 +       if (!otg_dev) {
33139 +               /* Memory allocation for the dwc_otg_device failed. */
33140 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
33141 +                return REM_RETVAL(-ENOMEM);
33142 +       }
33143 +#ifndef DWC_DEVICE_ONLY
33144 +       if (otg_dev->hcd) {
33145 +               hcd_remove(_dev);
33146 +       } else {
33147 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
33148 +                return REM_RETVAL(-EINVAL);
33149 +       }
33150 +#endif
33151 +
33152 +#ifndef DWC_HOST_ONLY
33153 +       if (otg_dev->pcd) {
33154 +               pcd_remove(_dev);
33155 +       } else {
33156 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
33157 +                return REM_RETVAL(-EINVAL);
33158 +       }
33159 +#endif
33160 +       /*
33161 +        * Free the IRQ
33162 +        */
33163 +       if (otg_dev->common_irq_installed) {
33164 +#ifdef PLATFORM_INTERFACE
33165 +               free_irq(platform_get_irq(_dev, 0), otg_dev);
33166 +#else
33167 +               free_irq(_dev->irq, otg_dev);
33168 +#endif
33169 +        } else {
33170 +               DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
33171 +               return REM_RETVAL(-ENXIO);
33172 +       }
33173 +
33174 +       if (otg_dev->core_if) {
33175 +               dwc_otg_cil_remove(otg_dev->core_if);
33176 +       } else {
33177 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
33178 +               return REM_RETVAL(-ENXIO);
33179 +       }
33180 +
33181 +       /*
33182 +        * Remove the device attributes
33183 +        */
33184 +       dwc_otg_attr_remove(_dev);
33185 +
33186 +       /*
33187 +        * Return the memory.
33188 +        */
33189 +       if (otg_dev->os_dep.base) {
33190 +               iounmap(otg_dev->os_dep.base);
33191 +       }
33192 +       DWC_FREE(otg_dev);
33193 +
33194 +       /*
33195 +        * Clear the drvdata pointer.
33196 +        */
33197 +#ifdef LM_INTERFACE
33198 +       lm_set_drvdata(_dev, 0);
33199 +#elif defined(PCI_INTERFACE)
33200 +        release_mem_region(otg_dev->os_dep.rsrc_start,
33201 +                           otg_dev->os_dep.rsrc_len);
33202 +       pci_set_drvdata(_dev, 0);
33203 +#elif  defined(PLATFORM_INTERFACE)
33204 +        platform_set_drvdata(_dev, 0);
33205 +#endif
33206 +        return REM_RETVAL(0);
33207 +}
33208 +
33209 +/**
33210 + * This function is called when an lm_device is bound to a
33211 + * dwc_otg_driver. It creates the driver components required to
33212 + * control the device (CIL, HCD, and PCD) and it initializes the
33213 + * device. The driver components are stored in a dwc_otg_device
33214 + * structure. A reference to the dwc_otg_device is saved in the
33215 + * lm_device. This allows the driver to access the dwc_otg_device
33216 + * structure on subsequent calls to driver methods for this device.
33217 + *
33218 + * @param _dev Bus device
33219 + */
33220 +static int dwc_otg_driver_probe(
33221 +#ifdef LM_INTERFACE
33222 +                                      struct lm_device *_dev
33223 +#elif defined(PCI_INTERFACE)
33224 +                                      struct pci_dev *_dev,
33225 +                                      const struct pci_device_id *id
33226 +#elif  defined(PLATFORM_INTERFACE)
33227 +                                       struct platform_device *_dev
33228 +#endif
33229 +    )
33230 +{
33231 +       int retval = 0;
33232 +       dwc_otg_device_t *dwc_otg_device;
33233 +        int devirq;
33234 +
33235 +       dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
33236 +#ifdef LM_INTERFACE
33237 +       dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
33238 +#elif defined(PCI_INTERFACE)
33239 +       if (!id) {
33240 +               DWC_ERROR("Invalid pci_device_id %p", id);
33241 +               return -EINVAL;
33242 +       }
33243 +
33244 +       if (!_dev || (pci_enable_device(_dev) < 0)) {
33245 +               DWC_ERROR("Invalid pci_device %p", _dev);
33246 +               return -ENODEV;
33247 +       }
33248 +       dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
33249 +       /* other stuff needed as well? */
33250 +
33251 +#elif  defined(PLATFORM_INTERFACE)
33252 +       dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n",
33253 +                (unsigned)_dev->resource->start,
33254 +                (unsigned)(_dev->resource->end - _dev->resource->start));
33255 +#endif
33256 +
33257 +       dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
33258 +
33259 +       if (!dwc_otg_device) {
33260 +               dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
33261 +               return -ENOMEM;
33262 +       }
33263 +
33264 +       memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
33265 +       dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
33266 +       dwc_otg_device->os_dep.platformdev = _dev;
33267 +
33268 +       /*
33269 +        * Map the DWC_otg Core memory into virtual address space.
33270 +        */
33271 +#ifdef LM_INTERFACE
33272 +       dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
33273 +
33274 +       if (!dwc_otg_device->os_dep.base) {
33275 +               dev_err(&_dev->dev, "ioremap() failed\n");
33276 +               DWC_FREE(dwc_otg_device);
33277 +               return -ENOMEM;
33278 +       }
33279 +       dev_dbg(&_dev->dev, "base=0x%08x\n",
33280 +               (unsigned)dwc_otg_device->os_dep.base);
33281 +#elif defined(PCI_INTERFACE)
33282 +       _dev->current_state = PCI_D0;
33283 +       _dev->dev.power.power_state = PMSG_ON;
33284 +
33285 +       if (!_dev->irq) {
33286 +               DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
33287 +                         pci_name(_dev));
33288 +               iounmap(dwc_otg_device->os_dep.base);
33289 +               DWC_FREE(dwc_otg_device);
33290 +               return -ENODEV;
33291 +       }
33292 +
33293 +       dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
33294 +       dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
33295 +       DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
33296 +                   (unsigned)dwc_otg_device->os_dep.rsrc_start,
33297 +                   (unsigned)dwc_otg_device->os_dep.rsrc_len);
33298 +       if (!request_mem_region
33299 +           (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
33300 +            "dwc_otg")) {
33301 +               dev_dbg(&_dev->dev, "error requesting memory\n");
33302 +               iounmap(dwc_otg_device->os_dep.base);
33303 +               DWC_FREE(dwc_otg_device);
33304 +               return -EFAULT;
33305 +       }
33306 +
33307 +       dwc_otg_device->os_dep.base =
33308 +           ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
33309 +                           dwc_otg_device->os_dep.rsrc_len);
33310 +       if (dwc_otg_device->os_dep.base == NULL) {
33311 +               dev_dbg(&_dev->dev, "error mapping memory\n");
33312 +               release_mem_region(dwc_otg_device->os_dep.rsrc_start,
33313 +                                  dwc_otg_device->os_dep.rsrc_len);
33314 +               iounmap(dwc_otg_device->os_dep.base);
33315 +               DWC_FREE(dwc_otg_device);
33316 +               return -EFAULT;
33317 +       }
33318 +       dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
33319 +               dwc_otg_device->os_dep.base);
33320 +       dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
33321 +       dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
33322 +               dwc_otg_device->os_dep.base);
33323 +       dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
33324 +               (unsigned)dwc_otg_device->os_dep.rsrc_start,
33325 +               dwc_otg_device->os_dep.base);
33326 +
33327 +       pci_set_master(_dev);
33328 +       pci_set_drvdata(_dev, dwc_otg_device);
33329 +#elif defined(PLATFORM_INTERFACE)
33330 +        DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
33331 +                    _dev->resource->start,
33332 +                    _dev->resource->end - _dev->resource->start + 1);
33333 +#if 1
33334 +        if (!request_mem_region(_dev->resource[0].start,
33335 +                                _dev->resource[0].end - _dev->resource[0].start + 1,
33336 +                                "dwc_otg")) {
33337 +          dev_dbg(&_dev->dev, "error reserving mapped memory\n");
33338 +          retval = -EFAULT;
33339 +          goto fail;
33340 +        }
33341 +
33342 +       dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
33343 +                                                      _dev->resource[0].end -
33344 +                                                      _dev->resource[0].start+1);
33345 +       if (fiq_enable)
33346 +       {
33347 +               if (!request_mem_region(_dev->resource[1].start,
33348 +                                       _dev->resource[1].end - _dev->resource[1].start + 1,
33349 +                                       "dwc_otg")) {
33350 +                 dev_dbg(&_dev->dev, "error reserving mapped memory\n");
33351 +                 retval = -EFAULT;
33352 +                 goto fail;
33353 +       }
33354 +
33355 +               dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start,
33356 +                                                           _dev->resource[1].end -
33357 +                                                           _dev->resource[1].start + 1);
33358 +       }
33359 +
33360 +#else
33361 +        {
33362 +                struct map_desc desc = {
33363 +                    .virtual = IO_ADDRESS((unsigned)_dev->resource->start),
33364 +                    .pfn     = __phys_to_pfn((unsigned)_dev->resource->start),
33365 +                    .length  = SZ_128K,
33366 +                    .type    = MT_DEVICE
33367 +                };
33368 +                iotable_init(&desc, 1);
33369 +                dwc_otg_device->os_dep.base = (void *)desc.virtual;
33370 +        }
33371 +#endif
33372 +       if (!dwc_otg_device->os_dep.base) {
33373 +               dev_err(&_dev->dev, "ioremap() failed\n");
33374 +               retval = -ENOMEM;
33375 +               goto fail;
33376 +       }
33377 +       dev_dbg(&_dev->dev, "base=0x%08x\n",
33378 +                (unsigned)dwc_otg_device->os_dep.base);
33379 +#endif
33380 +
33381 +       /*
33382 +        * Initialize driver data to point to the global DWC_otg
33383 +        * Device structure.
33384 +        */
33385 +#ifdef LM_INTERFACE
33386 +       lm_set_drvdata(_dev, dwc_otg_device);
33387 +#elif defined(PLATFORM_INTERFACE)
33388 +       platform_set_drvdata(_dev, dwc_otg_device);
33389 +#endif
33390 +       dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
33391 +
33392 +       dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
33393 +        DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
33394 +                    dwc_otg_device, dwc_otg_device->core_if);//GRAYG
33395 +
33396 +       if (!dwc_otg_device->core_if) {
33397 +               dev_err(&_dev->dev, "CIL initialization failed!\n");
33398 +               retval = -ENOMEM;
33399 +               goto fail;
33400 +       }
33401 +
33402 +       dev_dbg(&_dev->dev, "Calling get_gsnpsid\n");
33403 +       /*
33404 +        * Attempt to ensure this device is really a DWC_otg Controller.
33405 +        * Read and verify the SNPSID register contents. The value should be
33406 +        * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
33407 +        * as in "OTG version 2.XX" or "OTG version 3.XX".
33408 +        */
33409 +
33410 +       if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=     0x4F542000) &&
33411 +               ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
33412 +               dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
33413 +                       dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
33414 +               retval = -EINVAL;
33415 +               goto fail;
33416 +       }
33417 +
33418 +       /*
33419 +        * Validate parameter values.
33420 +        */
33421 +       dev_dbg(&_dev->dev, "Calling set_parameters\n");
33422 +       if (set_parameters(dwc_otg_device->core_if)) {
33423 +               retval = -EINVAL;
33424 +               goto fail;
33425 +       }
33426 +
33427 +       /*
33428 +        * Create Device Attributes in sysfs
33429 +        */
33430 +       dev_dbg(&_dev->dev, "Calling attr_create\n");
33431 +       dwc_otg_attr_create(_dev);
33432 +
33433 +       /*
33434 +        * Disable the global interrupt until all the interrupt
33435 +        * handlers are installed.
33436 +        */
33437 +       dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n");
33438 +       dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
33439 +
33440 +       /*
33441 +        * Install the interrupt handler for the common interrupts before
33442 +        * enabling common interrupts in core_init below.
33443 +        */
33444 +
33445 +#if defined(PLATFORM_INTERFACE)
33446 +       devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1);
33447 +#else
33448 +       devirq = _dev->irq;
33449 +#endif
33450 +       DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
33451 +                   devirq);
33452 +       dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq);
33453 +       retval = request_irq(devirq, dwc_otg_common_irq,
33454 +                             IRQF_SHARED,
33455 +                             "dwc_otg", dwc_otg_device);
33456 +       if (retval) {
33457 +               DWC_ERROR("request of irq%d failed\n", devirq);
33458 +               retval = -EBUSY;
33459 +               goto fail;
33460 +       } else {
33461 +               dwc_otg_device->common_irq_installed = 1;
33462 +       }
33463 +
33464 +#ifndef IRQF_TRIGGER_LOW
33465 +#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
33466 +       dev_dbg(&_dev->dev, "Calling set_irq_type\n");
33467 +       set_irq_type(devirq,
33468 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
33469 +                     IRQT_LOW
33470 +#else
33471 +                     IRQ_TYPE_LEVEL_LOW
33472 +#endif
33473 +                    );
33474 +#endif
33475 +#endif /*IRQF_TRIGGER_LOW*/
33476 +
33477 +       /*
33478 +        * Initialize the DWC_otg core.
33479 +        */
33480 +       dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n");
33481 +       dwc_otg_core_init(dwc_otg_device->core_if);
33482 +
33483 +#ifndef DWC_HOST_ONLY
33484 +       /*
33485 +        * Initialize the PCD
33486 +        */
33487 +       dev_dbg(&_dev->dev, "Calling pcd_init\n");
33488 +       retval = pcd_init(_dev);
33489 +       if (retval != 0) {
33490 +               DWC_ERROR("pcd_init failed\n");
33491 +               dwc_otg_device->pcd = NULL;
33492 +               goto fail;
33493 +       }
33494 +#endif
33495 +#ifndef DWC_DEVICE_ONLY
33496 +       /*
33497 +        * Initialize the HCD
33498 +        */
33499 +       dev_dbg(&_dev->dev, "Calling hcd_init\n");
33500 +       retval = hcd_init(_dev);
33501 +       if (retval != 0) {
33502 +               DWC_ERROR("hcd_init failed\n");
33503 +               dwc_otg_device->hcd = NULL;
33504 +               goto fail;
33505 +       }
33506 +#endif
33507 +        /* Recover from drvdata having been overwritten by hcd_init() */
33508 +#ifdef LM_INTERFACE
33509 +       lm_set_drvdata(_dev, dwc_otg_device);
33510 +#elif defined(PLATFORM_INTERFACE)
33511 +       platform_set_drvdata(_dev, dwc_otg_device);
33512 +#elif defined(PCI_INTERFACE)
33513 +       pci_set_drvdata(_dev, dwc_otg_device);
33514 +       dwc_otg_device->os_dep.pcidev = _dev;
33515 +#endif
33516 +
33517 +       /*
33518 +        * Enable the global interrupt after all the interrupt
33519 +        * handlers are installed if there is no ADP support else
33520 +        * perform initial actions required for Internal ADP logic.
33521 +        */
33522 +       if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
33523 +               dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n");
33524 +               dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
33525 +               dev_dbg(&_dev->dev, "Done\n");
33526 +       } else
33527 +               dwc_otg_adp_start(dwc_otg_device->core_if,
33528 +                                                       dwc_otg_is_host_mode(dwc_otg_device->core_if));
33529 +
33530 +       return 0;
33531 +
33532 +fail:
33533 +       dwc_otg_driver_remove(_dev);
33534 +       return retval;
33535 +}
33536 +
33537 +/**
33538 + * This structure defines the methods to be called by a bus driver
33539 + * during the lifecycle of a device on that bus. Both drivers and
33540 + * devices are registered with a bus driver. The bus driver matches
33541 + * devices to drivers based on information in the device and driver
33542 + * structures.
33543 + *
33544 + * The probe function is called when the bus driver matches a device
33545 + * to this driver. The remove function is called when a device is
33546 + * unregistered with the bus driver.
33547 + */
33548 +#ifdef LM_INTERFACE
33549 +static struct lm_driver dwc_otg_driver = {
33550 +       .drv = {.name = (char *)dwc_driver_name,},
33551 +       .probe = dwc_otg_driver_probe,
33552 +       .remove = dwc_otg_driver_remove,
33553 +        // 'suspend' and 'resume' absent
33554 +};
33555 +#elif defined(PCI_INTERFACE)
33556 +static const struct pci_device_id pci_ids[] = { {
33557 +                                                PCI_DEVICE(0x16c3, 0xabcd),
33558 +                                                .driver_data =
33559 +                                                (unsigned long)0xdeadbeef,
33560 +                                                }, { /* end: all zeroes */ }
33561 +};
33562 +
33563 +MODULE_DEVICE_TABLE(pci, pci_ids);
33564 +
33565 +/* pci driver glue; this is a "new style" PCI driver module */
33566 +static struct pci_driver dwc_otg_driver = {
33567 +       .name = "dwc_otg",
33568 +       .id_table = pci_ids,
33569 +
33570 +       .probe = dwc_otg_driver_probe,
33571 +       .remove = dwc_otg_driver_remove,
33572 +
33573 +       .driver = {
33574 +                  .name = (char *)dwc_driver_name,
33575 +                  },
33576 +};
33577 +#elif defined(PLATFORM_INTERFACE)
33578 +static struct platform_device_id platform_ids[] = {
33579 +        {
33580 +              .name = "bcm2708_usb",
33581 +              .driver_data = (kernel_ulong_t) 0xdeadbeef,
33582 +        },
33583 +        { /* end: all zeroes */ }
33584 +};
33585 +MODULE_DEVICE_TABLE(platform, platform_ids);
33586 +
33587 +static const struct of_device_id dwc_otg_of_match_table[] = {
33588 +       { .compatible = "brcm,bcm2708-usb", },
33589 +       {},
33590 +};
33591 +MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table);
33592 +
33593 +static struct platform_driver dwc_otg_driver = {
33594 +       .driver = {
33595 +               .name = (char *)dwc_driver_name,
33596 +               .of_match_table = dwc_otg_of_match_table,
33597 +               },
33598 +        .id_table = platform_ids,
33599 +
33600 +       .probe = dwc_otg_driver_probe,
33601 +       .remove = dwc_otg_driver_remove,
33602 +        // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early'
33603 +};
33604 +#endif
33605 +
33606 +/**
33607 + * This function is called when the dwc_otg_driver is installed with the
33608 + * insmod command. It registers the dwc_otg_driver structure with the
33609 + * appropriate bus driver. This will cause the dwc_otg_driver_probe function
33610 + * to be called. In addition, the bus driver will automatically expose
33611 + * attributes defined for the device and driver in the special sysfs file
33612 + * system.
33613 + *
33614 + * @return
33615 + */
33616 +static int __init dwc_otg_driver_init(void)
33617 +{
33618 +       int retval = 0;
33619 +       int error;
33620 +        struct device_driver *drv;
33621 +
33622 +       if(fiq_fsm_enable && !fiq_enable) {
33623 +               printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n");
33624 +               fiq_enable = 1;
33625 +       }
33626 +
33627 +       printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name,
33628 +              DWC_DRIVER_VERSION,
33629 +#ifdef LM_INTERFACE
33630 +               "logicmodule");
33631 +       retval = lm_driver_register(&dwc_otg_driver);
33632 +        drv = &dwc_otg_driver.drv;
33633 +#elif defined(PCI_INTERFACE)
33634 +               "pci");
33635 +       retval = pci_register_driver(&dwc_otg_driver);
33636 +        drv = &dwc_otg_driver.driver;
33637 +#elif defined(PLATFORM_INTERFACE)
33638 +               "platform");
33639 +       retval = platform_driver_register(&dwc_otg_driver);
33640 +        drv = &dwc_otg_driver.driver;
33641 +#endif
33642 +       if (retval < 0) {
33643 +               printk(KERN_ERR "%s retval=%d\n", __func__, retval);
33644 +               return retval;
33645 +       }
33646 +       printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled");
33647 +       printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled");
33648 +       printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled");
33649 +
33650 +       error = driver_create_file(drv, &driver_attr_version);
33651 +#ifdef DEBUG
33652 +       error = driver_create_file(drv, &driver_attr_debuglevel);
33653 +#endif
33654 +       return retval;
33655 +}
33656 +
33657 +module_init(dwc_otg_driver_init);
33658 +
33659 +/**
33660 + * This function is called when the driver is removed from the kernel
33661 + * with the rmmod command. The driver unregisters itself with its bus
33662 + * driver.
33663 + *
33664 + */
33665 +static void __exit dwc_otg_driver_cleanup(void)
33666 +{
33667 +       printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
33668 +
33669 +#ifdef LM_INTERFACE
33670 +       driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
33671 +       driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
33672 +       lm_driver_unregister(&dwc_otg_driver);
33673 +#elif defined(PCI_INTERFACE)
33674 +       driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
33675 +       driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
33676 +       pci_unregister_driver(&dwc_otg_driver);
33677 +#elif defined(PLATFORM_INTERFACE)
33678 +       driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
33679 +       driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
33680 +       platform_driver_unregister(&dwc_otg_driver);
33681 +#endif
33682 +
33683 +       printk(KERN_INFO "%s module removed\n", dwc_driver_name);
33684 +}
33685 +
33686 +module_exit(dwc_otg_driver_cleanup);
33687 +
33688 +MODULE_DESCRIPTION(DWC_DRIVER_DESC);
33689 +MODULE_AUTHOR("Synopsys Inc.");
33690 +MODULE_LICENSE("GPL");
33691 +
33692 +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
33693 +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
33694 +module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
33695 +MODULE_PARM_DESC(opt, "OPT Mode");
33696 +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
33697 +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
33698 +
33699 +module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
33700 +                  0444);
33701 +MODULE_PARM_DESC(dma_desc_enable,
33702 +                "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
33703 +
33704 +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
33705 +                  0444);
33706 +MODULE_PARM_DESC(dma_burst_size,
33707 +                "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
33708 +module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
33709 +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
33710 +module_param_named(host_support_fs_ls_low_power,
33711 +                  dwc_otg_module_params.host_support_fs_ls_low_power, int,
33712 +                  0444);
33713 +MODULE_PARM_DESC(host_support_fs_ls_low_power,
33714 +                "Support Low Power w/FS or LS 0=Support 1=Don't Support");
33715 +module_param_named(host_ls_low_power_phy_clk,
33716 +                  dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
33717 +MODULE_PARM_DESC(host_ls_low_power_phy_clk,
33718 +                "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
33719 +module_param_named(enable_dynamic_fifo,
33720 +                  dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
33721 +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
33722 +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
33723 +                  0444);
33724 +MODULE_PARM_DESC(data_fifo_size,
33725 +                "Total number of words in the data FIFO memory 32-32768");
33726 +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
33727 +                  int, 0444);
33728 +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
33729 +module_param_named(dev_nperio_tx_fifo_size,
33730 +                  dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
33731 +MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
33732 +                "Number of words in the non-periodic Tx FIFO 16-32768");
33733 +module_param_named(dev_perio_tx_fifo_size_1,
33734 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
33735 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
33736 +                "Number of words in the periodic Tx FIFO 4-768");
33737 +module_param_named(dev_perio_tx_fifo_size_2,
33738 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
33739 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
33740 +                "Number of words in the periodic Tx FIFO 4-768");
33741 +module_param_named(dev_perio_tx_fifo_size_3,
33742 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
33743 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
33744 +                "Number of words in the periodic Tx FIFO 4-768");
33745 +module_param_named(dev_perio_tx_fifo_size_4,
33746 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
33747 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
33748 +                "Number of words in the periodic Tx FIFO 4-768");
33749 +module_param_named(dev_perio_tx_fifo_size_5,
33750 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
33751 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
33752 +                "Number of words in the periodic Tx FIFO 4-768");
33753 +module_param_named(dev_perio_tx_fifo_size_6,
33754 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
33755 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
33756 +                "Number of words in the periodic Tx FIFO 4-768");
33757 +module_param_named(dev_perio_tx_fifo_size_7,
33758 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
33759 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
33760 +                "Number of words in the periodic Tx FIFO 4-768");
33761 +module_param_named(dev_perio_tx_fifo_size_8,
33762 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
33763 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
33764 +                "Number of words in the periodic Tx FIFO 4-768");
33765 +module_param_named(dev_perio_tx_fifo_size_9,
33766 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
33767 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
33768 +                "Number of words in the periodic Tx FIFO 4-768");
33769 +module_param_named(dev_perio_tx_fifo_size_10,
33770 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
33771 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
33772 +                "Number of words in the periodic Tx FIFO 4-768");
33773 +module_param_named(dev_perio_tx_fifo_size_11,
33774 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
33775 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
33776 +                "Number of words in the periodic Tx FIFO 4-768");
33777 +module_param_named(dev_perio_tx_fifo_size_12,
33778 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
33779 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
33780 +                "Number of words in the periodic Tx FIFO 4-768");
33781 +module_param_named(dev_perio_tx_fifo_size_13,
33782 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
33783 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
33784 +                "Number of words in the periodic Tx FIFO 4-768");
33785 +module_param_named(dev_perio_tx_fifo_size_14,
33786 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
33787 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
33788 +                "Number of words in the periodic Tx FIFO 4-768");
33789 +module_param_named(dev_perio_tx_fifo_size_15,
33790 +                  dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
33791 +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
33792 +                "Number of words in the periodic Tx FIFO 4-768");
33793 +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
33794 +                  int, 0444);
33795 +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
33796 +module_param_named(host_nperio_tx_fifo_size,
33797 +                  dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
33798 +MODULE_PARM_DESC(host_nperio_tx_fifo_size,
33799 +                "Number of words in the non-periodic Tx FIFO 16-32768");
33800 +module_param_named(host_perio_tx_fifo_size,
33801 +                  dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
33802 +MODULE_PARM_DESC(host_perio_tx_fifo_size,
33803 +                "Number of words in the host periodic Tx FIFO 16-32768");
33804 +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
33805 +                  int, 0444);
33806 +/** @todo Set the max to 512K, modify checks */
33807 +MODULE_PARM_DESC(max_transfer_size,
33808 +                "The maximum transfer size supported in bytes 2047-65535");
33809 +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
33810 +                  int, 0444);
33811 +MODULE_PARM_DESC(max_packet_count,
33812 +                "The maximum number of packets in a transfer 15-511");
33813 +module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
33814 +                  0444);
33815 +MODULE_PARM_DESC(host_channels,
33816 +                "The number of host channel registers to use 1-16");
33817 +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
33818 +                  0444);
33819 +MODULE_PARM_DESC(dev_endpoints,
33820 +                "The number of endpoints in addition to EP0 available for device mode 1-15");
33821 +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
33822 +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
33823 +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
33824 +                  0444);
33825 +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
33826 +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
33827 +MODULE_PARM_DESC(phy_ulpi_ddr,
33828 +                "ULPI at double or single data rate 0=Single 1=Double");
33829 +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
33830 +                  int, 0444);
33831 +MODULE_PARM_DESC(phy_ulpi_ext_vbus,
33832 +                "ULPI PHY using internal or external vbus 0=Internal");
33833 +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
33834 +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
33835 +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
33836 +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
33837 +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
33838 +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
33839 +module_param_named(debug, g_dbg_lvl, int, 0444);
33840 +MODULE_PARM_DESC(debug, "");
33841 +
33842 +module_param_named(en_multiple_tx_fifo,
33843 +                  dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
33844 +MODULE_PARM_DESC(en_multiple_tx_fifo,
33845 +                "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
33846 +module_param_named(dev_tx_fifo_size_1,
33847 +                  dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
33848 +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
33849 +module_param_named(dev_tx_fifo_size_2,
33850 +                  dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
33851 +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
33852 +module_param_named(dev_tx_fifo_size_3,
33853 +                  dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
33854 +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
33855 +module_param_named(dev_tx_fifo_size_4,
33856 +                  dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
33857 +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
33858 +module_param_named(dev_tx_fifo_size_5,
33859 +                  dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
33860 +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
33861 +module_param_named(dev_tx_fifo_size_6,
33862 +                  dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
33863 +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
33864 +module_param_named(dev_tx_fifo_size_7,
33865 +                  dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
33866 +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
33867 +module_param_named(dev_tx_fifo_size_8,
33868 +                  dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
33869 +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
33870 +module_param_named(dev_tx_fifo_size_9,
33871 +                  dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
33872 +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
33873 +module_param_named(dev_tx_fifo_size_10,
33874 +                  dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
33875 +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
33876 +module_param_named(dev_tx_fifo_size_11,
33877 +                  dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
33878 +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
33879 +module_param_named(dev_tx_fifo_size_12,
33880 +                  dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
33881 +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
33882 +module_param_named(dev_tx_fifo_size_13,
33883 +                  dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
33884 +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
33885 +module_param_named(dev_tx_fifo_size_14,
33886 +                  dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
33887 +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
33888 +module_param_named(dev_tx_fifo_size_15,
33889 +                  dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
33890 +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
33891 +
33892 +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
33893 +MODULE_PARM_DESC(thr_ctl,
33894 +                "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
33895 +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
33896 +                  0444);
33897 +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
33898 +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
33899 +                  0444);
33900 +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
33901 +
33902 +module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
33903 +module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
33904 +module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
33905 +MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
33906 +module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
33907 +MODULE_PARM_DESC(ic_usb_cap,
33908 +                "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
33909 +module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
33910 +                  0444);
33911 +MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
33912 +module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
33913 +MODULE_PARM_DESC(power_down, "Power Down Mode");
33914 +module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
33915 +MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
33916 +module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
33917 +MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
33918 +module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
33919 +MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
33920 +module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
33921 +MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
33922 +module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
33923 +MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
33924 +module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
33925 +MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
33926 +module_param(microframe_schedule, bool, 0444);
33927 +MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler");
33928 +
33929 +module_param(fiq_enable, bool, 0444);
33930 +MODULE_PARM_DESC(fiq_enable, "Enable the FIQ");
33931 +module_param(nak_holdoff, ushort, 0644);
33932 +MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8");
33933 +module_param(fiq_fsm_enable, bool, 0444);
33934 +MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask");
33935 +module_param(fiq_fsm_mask, ushort, 0444);
33936 +MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n"
33937 +                                       "Bit 0 : Non-periodic split transactions\n"
33938 +                                       "Bit 1 : Periodic split transactions\n"
33939 +                                       "Bit 2 : High-speed multi-transfer isochronous\n"
33940 +                                       "All other bits should be set 0.");
33941 +
33942 +
33943 +/** @page "Module Parameters"
33944 + *
33945 + * The following parameters may be specified when starting the module.
33946 + * These parameters define how the DWC_otg controller should be
33947 + * configured. Parameter values are passed to the CIL initialization
33948 + * function dwc_otg_cil_init
33949 + *
33950 + * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
33951 + *
33952 +
33953 + <table>
33954 + <tr><td>Parameter Name</td><td>Meaning</td></tr>
33955 +
33956 + <tr>
33957 + <td>otg_cap</td>
33958 + <td>Specifies the OTG capabilities. The driver will automatically detect the
33959 + value for this parameter if none is specified.
33960 + - 0: HNP and SRP capable (default, if available)
33961 + - 1: SRP Only capable
33962 + - 2: No HNP/SRP capable
33963 + </td></tr>
33964 +
33965 + <tr>
33966 + <td>dma_enable</td>
33967 + <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
33968 + The driver will automatically detect the value for this parameter if none is
33969 + specified.
33970 + - 0: Slave
33971 + - 1: DMA (default, if available)
33972 + </td></tr>
33973 +
33974 + <tr>
33975 + <td>dma_burst_size</td>
33976 + <td>The DMA Burst size (applicable only for External DMA Mode).
33977 + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
33978 + </td></tr>
33979 +
33980 + <tr>
33981 + <td>speed</td>
33982 + <td>Specifies the maximum speed of operation in host and device mode. The
33983 + actual speed depends on the speed of the attached device and the value of
33984 + phy_type.
33985 + - 0: High Speed (default)
33986 + - 1: Full Speed
33987 + </td></tr>
33988 +
33989 + <tr>
33990 + <td>host_support_fs_ls_low_power</td>
33991 + <td>Specifies whether low power mode is supported when attached to a Full
33992 + Speed or Low Speed device in host mode.
33993 + - 0: Don't support low power mode (default)
33994 + - 1: Support low power mode
33995 + </td></tr>
33996 +
33997 + <tr>
33998 + <td>host_ls_low_power_phy_clk</td>
33999 + <td>Specifies the PHY clock rate in low power mode when connected to a Low
34000 + Speed device in host mode. This parameter is applicable only if
34001 + HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
34002 + - 0: 48 MHz (default)
34003 + - 1: 6 MHz
34004 + </td></tr>
34005 +
34006 + <tr>
34007 + <td>enable_dynamic_fifo</td>
34008 + <td> Specifies whether FIFOs may be resized by the driver software.
34009 + - 0: Use cC FIFO size parameters
34010 + - 1: Allow dynamic FIFO sizing (default)
34011 + </td></tr>
34012 +
34013 + <tr>
34014 + <td>data_fifo_size</td>
34015 + <td>Total number of 4-byte words in the data FIFO memory. This memory
34016 + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
34017 + - Values: 32 to 32768 (default 8192)
34018 +
34019 + Note: The total FIFO memory depth in the FPGA configuration is 8192.
34020 + </td></tr>
34021 +
34022 + <tr>
34023 + <td>dev_rx_fifo_size</td>
34024 + <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
34025 + FIFO sizing is enabled.
34026 + - Values: 16 to 32768 (default 1064)
34027 + </td></tr>
34028 +
34029 + <tr>
34030 + <td>dev_nperio_tx_fifo_size</td>
34031 + <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
34032 + dynamic FIFO sizing is enabled.
34033 + - Values: 16 to 32768 (default 1024)
34034 + </td></tr>
34035 +
34036 + <tr>
34037 + <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
34038 + <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
34039 + when dynamic FIFO sizing is enabled.
34040 + - Values: 4 to 768 (default 256)
34041 + </td></tr>
34042 +
34043 + <tr>
34044 + <td>host_rx_fifo_size</td>
34045 + <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
34046 + sizing is enabled.
34047 + - Values: 16 to 32768 (default 1024)
34048 + </td></tr>
34049 +
34050 + <tr>
34051 + <td>host_nperio_tx_fifo_size</td>
34052 + <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
34053 + dynamic FIFO sizing is enabled in the core.
34054 + - Values: 16 to 32768 (default 1024)
34055 + </td></tr>
34056 +
34057 + <tr>
34058 + <td>host_perio_tx_fifo_size</td>
34059 + <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
34060 + sizing is enabled.
34061 + - Values: 16 to 32768 (default 1024)
34062 + </td></tr>
34063 +
34064 + <tr>
34065 + <td>max_transfer_size</td>
34066 + <td>The maximum transfer size supported in bytes.
34067 + - Values: 2047 to 65,535 (default 65,535)
34068 + </td></tr>
34069 +
34070 + <tr>
34071 + <td>max_packet_count</td>
34072 + <td>The maximum number of packets in a transfer.
34073 + - Values: 15 to 511 (default 511)
34074 + </td></tr>
34075 +
34076 + <tr>
34077 + <td>host_channels</td>
34078 + <td>The number of host channel registers to use.
34079 + - Values: 1 to 16 (default 12)
34080 +
34081 + Note: The FPGA configuration supports a maximum of 12 host channels.
34082 + </td></tr>
34083 +
34084 + <tr>
34085 + <td>dev_endpoints</td>
34086 + <td>The number of endpoints in addition to EP0 available for device mode
34087 + operations.
34088 + - Values: 1 to 15 (default 6 IN and OUT)
34089 +
34090 + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
34091 + addition to EP0.
34092 + </td></tr>
34093 +
34094 + <tr>
34095 + <td>phy_type</td>
34096 + <td>Specifies the type of PHY interface to use. By default, the driver will
34097 + automatically detect the phy_type.
34098 + - 0: Full Speed
34099 + - 1: UTMI+ (default, if available)
34100 + - 2: ULPI
34101 + </td></tr>
34102 +
34103 + <tr>
34104 + <td>phy_utmi_width</td>
34105 + <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
34106 + phy_type of UTMI+. Also, this parameter is applicable only if the
34107 + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
34108 + core has been configured to work at either data path width.
34109 + - Values: 8 or 16 bits (default 16)
34110 + </td></tr>
34111 +
34112 + <tr>
34113 + <td>phy_ulpi_ddr</td>
34114 + <td>Specifies whether the ULPI operates at double or single data rate. This
34115 + parameter is only applicable if phy_type is ULPI.
34116 + - 0: single data rate ULPI interface with 8 bit wide data bus (default)
34117 + - 1: double data rate ULPI interface with 4 bit wide data bus
34118 + </td></tr>
34119 +
34120 + <tr>
34121 + <td>i2c_enable</td>
34122 + <td>Specifies whether to use the I2C interface for full speed PHY. This
34123 + parameter is only applicable if PHY_TYPE is FS.
34124 + - 0: Disabled (default)
34125 + - 1: Enabled
34126 + </td></tr>
34127 +
34128 + <tr>
34129 + <td>ulpi_fs_ls</td>
34130 + <td>Specifies whether to use ULPI FS/LS mode only.
34131 + - 0: Disabled (default)
34132 + - 1: Enabled
34133 + </td></tr>
34134 +
34135 + <tr>
34136 + <td>ts_dline</td>
34137 + <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
34138 + - 0: Disabled (default)
34139 + - 1: Enabled
34140 + </td></tr>
34141 +
34142 + <tr>
34143 + <td>en_multiple_tx_fifo</td>
34144 + <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
34145 + The driver will automatically detect the value for this parameter if none is
34146 + specified.
34147 + - 0: Disabled
34148 + - 1: Enabled (default, if available)
34149 + </td></tr>
34150 +
34151 + <tr>
34152 + <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
34153 + <td>Number of 4-byte words in each of the Tx FIFOs in device mode
34154 + when dynamic FIFO sizing is enabled.
34155 + - Values: 4 to 768 (default 256)
34156 + </td></tr>
34157 +
34158 + <tr>
34159 + <td>tx_thr_length</td>
34160 + <td>Transmit Threshold length in 32 bit double words
34161 + - Values: 8 to 128 (default 64)
34162 + </td></tr>
34163 +
34164 + <tr>
34165 + <td>rx_thr_length</td>
34166 + <td>Receive Threshold length in 32 bit double words
34167 + - Values: 8 to 128 (default 64)
34168 + </td></tr>
34169 +
34170 +<tr>
34171 + <td>thr_ctl</td>
34172 + <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
34173 + this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
34174 + Rx transfers accordingly.
34175 + The driver will automatically detect the value for this parameter if none is
34176 + specified.
34177 + - Values: 0 to 7 (default 0)
34178 + Bit values indicate:
34179 + - 0: Thresholding disabled
34180 + - 1: Thresholding enabled
34181 + </td></tr>
34182 +
34183 +<tr>
34184 + <td>dma_desc_enable</td>
34185 + <td>Specifies whether to enable Descriptor DMA mode.
34186 + The driver will automatically detect the value for this parameter if none is
34187 + specified.
34188 + - 0: Descriptor DMA disabled
34189 + - 1: Descriptor DMA (default, if available)
34190 + </td></tr>
34191 +
34192 +<tr>
34193 + <td>mpi_enable</td>
34194 + <td>Specifies whether to enable MPI enhancement mode.
34195 + The driver will automatically detect the value for this parameter if none is
34196 + specified.
34197 + - 0: MPI disabled (default)
34198 + - 1: MPI enable
34199 + </td></tr>
34200 +
34201 +<tr>
34202 + <td>pti_enable</td>
34203 + <td>Specifies whether to enable PTI enhancement support.
34204 + The driver will automatically detect the value for this parameter if none is
34205 + specified.
34206 + - 0: PTI disabled (default)
34207 + - 1: PTI enable
34208 + </td></tr>
34209 +
34210 +<tr>
34211 + <td>lpm_enable</td>
34212 + <td>Specifies whether to enable LPM support.
34213 + The driver will automatically detect the value for this parameter if none is
34214 + specified.
34215 + - 0: LPM disabled
34216 + - 1: LPM enable (default, if available)
34217 + </td></tr>
34218 +
34219 +<tr>
34220 + <td>ic_usb_cap</td>
34221 + <td>Specifies whether to enable IC_USB capability.
34222 + The driver will automatically detect the value for this parameter if none is
34223 + specified.
34224 + - 0: IC_USB disabled (default, if available)
34225 + - 1: IC_USB enable
34226 + </td></tr>
34227 +
34228 +<tr>
34229 + <td>ahb_thr_ratio</td>
34230 + <td>Specifies AHB Threshold ratio.
34231 + - Values: 0 to 3 (default 0)
34232 + </td></tr>
34233 +
34234 +<tr>
34235 + <td>power_down</td>
34236 + <td>Specifies Power Down(Hibernation) Mode.
34237 + The driver will automatically detect the value for this parameter if none is
34238 + specified.
34239 + - 0: Power Down disabled (default)
34240 + - 2: Power Down enabled
34241 + </td></tr>
34242 +
34243 + <tr>
34244 + <td>reload_ctl</td>
34245 + <td>Specifies whether dynamic reloading of the HFIR register is allowed during
34246 + run time. The driver will automatically detect the value for this parameter if
34247 + none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
34248 + the core might misbehave.
34249 + - 0: Reload Control disabled (default)
34250 + - 1: Reload Control enabled
34251 + </td></tr>
34252 +
34253 + <tr>
34254 + <td>dev_out_nak</td>
34255 + <td>Specifies whether  Device OUT NAK enhancement enabled or no.
34256 + The driver will automatically detect the value for this parameter if
34257 + none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
34258 + - 0: The core does not set NAK after Bulk OUT transfer complete (default)
34259 + - 1: The core sets NAK after Bulk OUT transfer complete
34260 + </td></tr>
34261 +
34262 + <tr>
34263 + <td>cont_on_bna</td>
34264 + <td>Specifies whether Enable Continue on BNA enabled or no.
34265 + After receiving BNA interrupt the core disables the endpoint,when the
34266 + endpoint is re-enabled by the application the
34267 + - 0: Core starts processing from the DOEPDMA descriptor (default)
34268 + - 1: Core starts processing from the descriptor which received the BNA.
34269 + This parameter is valid only when OTG_EN_DESC_DMA == 1b1.
34270 + </td></tr>
34271 +
34272 + <tr>
34273 + <td>ahb_single</td>
34274 + <td>This bit when programmed supports SINGLE transfers for remainder data
34275 + in a transfer for DMA mode of operation.
34276 + - 0: The remainder data will be sent using INCR burst size (default)
34277 + - 1: The remainder data will be sent using SINGLE burst size.
34278 + </td></tr>
34279 +
34280 +<tr>
34281 + <td>adp_enable</td>
34282 + <td>Specifies whether ADP feature is enabled.
34283 + The driver will automatically detect the value for this parameter if none is
34284 + specified.
34285 + - 0: ADP feature disabled (default)
34286 + - 1: ADP feature enabled
34287 + </td></tr>
34288 +
34289 +  <tr>
34290 + <td>otg_ver</td>
34291 + <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
34292 + USB OTG device.
34293 + - 0: OTG 2.0 support disabled (default)
34294 + - 1: OTG 2.0 support enabled
34295 + </td></tr>
34296 +
34297 +*/
34298 --- /dev/null
34299 +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.h
34300 @@ -0,0 +1,86 @@
34301 +/* ==========================================================================
34302 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
34303 + * $Revision: #19 $
34304 + * $Date: 2010/11/15 $
34305 + * $Change: 1627671 $
34306 + *
34307 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
34308 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
34309 + * otherwise expressly agreed to in writing between Synopsys and you.
34310 + *
34311 + * The Software IS NOT an item of Licensed Software or Licensed Product under
34312 + * any End User Software License Agreement or Agreement for Licensed Product
34313 + * with Synopsys or any supplement thereto. You are permitted to use and
34314 + * redistribute this Software in source and binary forms, with or without
34315 + * modification, provided that redistributions of source code must retain this
34316 + * notice. You may not view, use, disclose, copy or distribute this file or
34317 + * any information contained herein except pursuant to this license grant from
34318 + * Synopsys. If you do not agree with this notice, including the disclaimer
34319 + * below, then you are not authorized to use the Software.
34320 + *
34321 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
34322 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34323 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34324 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
34325 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34326 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34327 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34328 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34329 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34330 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
34331 + * DAMAGE.
34332 + * ========================================================================== */
34333 +
34334 +#ifndef __DWC_OTG_DRIVER_H__
34335 +#define __DWC_OTG_DRIVER_H__
34336 +
34337 +/** @file
34338 + * This file contains the interface to the Linux driver.
34339 + */
34340 +#include "dwc_otg_os_dep.h"
34341 +#include "dwc_otg_core_if.h"
34342 +
34343 +/* Type declarations */
34344 +struct dwc_otg_pcd;
34345 +struct dwc_otg_hcd;
34346 +
34347 +/**
34348 + * This structure is a wrapper that encapsulates the driver components used to
34349 + * manage a single DWC_otg controller.
34350 + */
34351 +typedef struct dwc_otg_device {
34352 +       /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
34353 +        * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
34354 +        * require this. */
34355 +       struct os_dependent os_dep;
34356 +
34357 +       /** Pointer to the core interface structure. */
34358 +       dwc_otg_core_if_t *core_if;
34359 +
34360 +       /** Pointer to the PCD structure. */
34361 +       struct dwc_otg_pcd *pcd;
34362 +
34363 +       /** Pointer to the HCD structure. */
34364 +       struct dwc_otg_hcd *hcd;
34365 +
34366 +       /** Flag to indicate whether the common IRQ handler is installed. */
34367 +       uint8_t common_irq_installed;
34368 +
34369 +} dwc_otg_device_t;
34370 +
34371 +/*We must clear S3C24XX_EINTPEND external interrupt register
34372 + * because after clearing in this register trigerred IRQ from
34373 + * H/W core in kernel interrupt can be occured again before OTG
34374 + * handlers clear all IRQ sources of Core registers because of
34375 + * timing latencies and Low Level IRQ Type.
34376 + */
34377 +#ifdef CONFIG_MACH_IPMATE
34378 +#define  S3C2410X_CLEAR_EINTPEND()   \
34379 +do { \
34380 +       __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
34381 +} while (0)
34382 +#else
34383 +#define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
34384 +#endif
34385 +
34386 +#endif
34387 --- /dev/null
34388 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c
34389 @@ -0,0 +1,1355 @@
34390 +/*
34391 + * dwc_otg_fiq_fsm.c - The finite state machine FIQ
34392 + *
34393 + * Copyright (c) 2013 Raspberry Pi Foundation
34394 + *
34395 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
34396 + * All rights reserved.
34397 + *
34398 + * Redistribution and use in source and binary forms, with or without
34399 + * modification, are permitted provided that the following conditions are met:
34400 + *     * Redistributions of source code must retain the above copyright
34401 + *       notice, this list of conditions and the following disclaimer.
34402 + *     * Redistributions in binary form must reproduce the above copyright
34403 + *       notice, this list of conditions and the following disclaimer in the
34404 + *       documentation and/or other materials provided with the distribution.
34405 + *     * Neither the name of Raspberry Pi nor the
34406 + *       names of its contributors may be used to endorse or promote products
34407 + *       derived from this software without specific prior written permission.
34408 + *
34409 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34410 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34411 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34412 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
34413 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34414 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34415 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
34416 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34417 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34418 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34419 + *
34420 + * This FIQ implements functionality that performs split transactions on
34421 + * the dwc_otg hardware without any outside intervention. A split transaction
34422 + * is "queued" by nominating a specific host channel to perform the entirety
34423 + * of a split transaction. This FIQ will then perform the microframe-precise
34424 + * scheduling required in each phase of the transaction until completion.
34425 + *
34426 + * The FIQ functionality is glued into the Synopsys driver via the entry point
34427 + * in the FSM enqueue function, and at the exit point in handling a HC interrupt
34428 + * for a FSM-enabled channel.
34429 + *
34430 + * NB: Large parts of this implementation have architecture-specific code.
34431 + * For porting this functionality to other ARM machines, the minimum is required:
34432 + * - An interrupt controller allowing the top-level dwc USB interrupt to be routed
34433 + *   to the FIQ
34434 + * - A method of forcing a software generated interrupt from FIQ mode that then
34435 + *   triggers an IRQ entry (with the dwc USB handler called by this IRQ number)
34436 + * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same
34437 + *   processor core - there is no locking between the FIQ and IRQ (aside from
34438 + *   local_fiq_disable)
34439 + *
34440 + */
34441 +
34442 +#include "dwc_otg_fiq_fsm.h"
34443 +
34444 +
34445 +char buffer[1000*16];
34446 +int wptr;
34447 +void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...)
34448 +{
34449 +       enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR;
34450 +       va_list args;
34451 +       char text[17];
34452 +       hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) };
34453 +
34454 +       if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR)
34455 +       {
34456 +               snprintf(text, 9, " %4d:%1u  ", hfnum.b.frnum/8, hfnum.b.frnum & 7);
34457 +               va_start(args, fmt);
34458 +               vsnprintf(text+8, 9, fmt, args);
34459 +               va_end(args);
34460 +
34461 +               memcpy(buffer + wptr, text, 16);
34462 +               wptr = (wptr + 16) % sizeof(buffer);
34463 +       }
34464 +}
34465 +
34466 +/**
34467 + * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock
34468 + * Must be called with local interrupts and FIQ disabled.
34469 + */
34470 +#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP)
34471 +inline void fiq_fsm_spin_lock(fiq_lock_t *lock)
34472 +{
34473 +       unsigned long tmp;
34474 +       uint32_t newval;
34475 +       fiq_lock_t lockval;
34476 +       smp_mb__before_spinlock();
34477 +       /* Nested locking, yay. If we are on the same CPU as the fiq, then the disable
34478 +        * will be sufficient. If we are on a different CPU, then the lock protects us. */
34479 +       prefetchw(&lock->slock);
34480 +       asm volatile (
34481 +       "1:     ldrex   %0, [%3]\n"
34482 +       "       add     %1, %0, %4\n"
34483 +       "       strex   %2, %1, [%3]\n"
34484 +       "       teq     %2, #0\n"
34485 +       "       bne     1b"
34486 +       : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
34487 +       : "r" (&lock->slock), "I" (1 << 16)
34488 +       : "cc");
34489 +
34490 +       while (lockval.tickets.next != lockval.tickets.owner) {
34491 +               wfe();
34492 +               lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
34493 +       }
34494 +       smp_mb();
34495 +}
34496 +#else
34497 +inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { }
34498 +#endif
34499 +
34500 +/**
34501 + * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock
34502 + */
34503 +#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP)
34504 +inline void fiq_fsm_spin_unlock(fiq_lock_t *lock)
34505 +{
34506 +       smp_mb();
34507 +       lock->tickets.owner++;
34508 +       dsb_sev();
34509 +}
34510 +#else
34511 +inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { }
34512 +#endif
34513 +
34514 +/**
34515 + * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction
34516 + * @channel: channel to re-enable
34517 + */
34518 +static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force)
34519 +{
34520 +       hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) };
34521 +
34522 +       hcchar.b.chen = 0;
34523 +       if (st->channel[n].hcchar_copy.b.eptype & 0x1) {
34524 +               hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
34525 +               /* Hardware bug workaround: update the ssplit index */
34526 +               if (st->channel[n].hcsplt_copy.b.spltena)
34527 +                       st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
34528 +
34529 +               hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0     : 1;
34530 +       }
34531 +
34532 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
34533 +       hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
34534 +       hcchar.b.chen = 1;
34535 +
34536 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32);
34537 +       fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force);
34538 +}
34539 +
34540 +/**
34541 + * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage
34542 + * @st: Pointer to the channel's state
34543 + * @n : channel number
34544 + *
34545 + * Change host channel registers to perform a complete-split transaction. Being mindful of the
34546 + * endpoint direction, set control regs up correctly.
34547 + */
34548 +static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n)
34549 +{
34550 +       hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) };
34551 +       hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
34552 +
34553 +       hcsplt.b.compsplt = 1;
34554 +       if (st->channel[n].hcchar_copy.b.epdir == 1) {
34555 +               // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket.
34556 +               hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
34557 +       } else {
34558 +               // If OUT, the CSPLIT result contains handshake only.
34559 +               hctsiz.b.xfersize = 0;
34560 +       }
34561 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
34562 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
34563 +       mb();
34564 +}
34565 +
34566 +static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n)
34567 +{
34568 +       /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */
34569 +       hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
34570 +
34571 +       if (st->channel[n].hcchar_copy.b.epdir == 0) {
34572 +               return st->channel[n].hctsiz_copy.b.xfersize;
34573 +       } else {
34574 +               return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize;
34575 +       }
34576 +
34577 +}
34578 +
34579 +
34580 +/**
34581 + * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT
34582 + *
34583 + * Of use only for IN periodic transfers.
34584 + */
34585 +static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n)
34586 +{
34587 +       hcdma_data_t hcdma;
34588 +       int i = st->channel[n].dma_info.index;
34589 +       int len;
34590 +       struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
34591 +
34592 +       len = fiq_get_xfer_len(st, n);
34593 +       fiq_print(FIQDBG_INT, st, "LEN: %03d", len);
34594 +       st->channel[n].dma_info.slot_len[i] = len;
34595 +       i++;
34596 +       if (i > 6)
34597 +               BUG();
34598 +
34599 +       hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0];
34600 +       FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
34601 +       st->channel[n].dma_info.index = i;
34602 +       return 0;
34603 +}
34604 +
34605 +/**
34606 + * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ
34607 + */
34608 +static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n)
34609 +{
34610 +       hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) };
34611 +       hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize;
34612 +       hctsiz.b.pktcnt = 1;
34613 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
34614 +}
34615 +
34616 +/**
34617 + * fiq_iso_out_advance() - update DMA address and split position bits
34618 + * for isochronous OUT transactions.
34619 + *
34620 + * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and
34621 + * Split-BEGIN states are not handled - this is done when the transaction was queued.
34622 + *
34623 + * This function must only be called from the FIQ_ISO_OUT_ACTIVE state.
34624 + */
34625 +static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n)
34626 +{
34627 +       hcsplt_data_t hcsplt;
34628 +       hctsiz_data_t hctsiz;
34629 +       hcdma_data_t hcdma;
34630 +       struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base;
34631 +       int last = 0;
34632 +       int i = st->channel[n].dma_info.index;
34633 +
34634 +       fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i);
34635 +       i++;
34636 +       if (i == 4)
34637 +               last = 1;
34638 +       if (st->channel[n].dma_info.slot_len[i+1] == 255)
34639 +               last = 1;
34640 +
34641 +       /* New DMA address - address of bounce buffer referred to in index */
34642 +       hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0];
34643 +       //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n));
34644 +       //hcdma.d32 += st->channel[n].dma_info.slot_len[i];
34645 +       fiq_print(FIQDBG_INT, st, "LAST: %01d ", last);
34646 +       fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]);
34647 +       hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT);
34648 +       hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ);
34649 +       hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID;
34650 +       /* Set up new packet length */
34651 +       hctsiz.b.pktcnt = 1;
34652 +       hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i];
34653 +       fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32);
34654 +
34655 +       st->channel[n].dma_info.index++;
34656 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32);
34657 +       FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32);
34658 +       FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
34659 +       return last;
34660 +}
34661 +
34662 +/**
34663 + * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT
34664 + *
34665 + * Despite the limitations of the DWC core, we can force a microframe pipeline of
34666 + * isochronous OUT start-split transactions while waiting for a corresponding other-type
34667 + * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it
34668 + * is very unlikely that filling the start-split FIFO will cause data loss.
34669 + * This allows much better interleaving of transactions in an order-independent way-
34670 + * there is no requirement to prioritise isochronous, just a state-space search has
34671 + * to be performed on each periodic start-split complete interrupt.
34672 + */
34673 +static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n)
34674 +{
34675 +       int hub_addr = st->channel[n].hub_addr;
34676 +       int port_addr = st->channel[n].port_addr;
34677 +       int i, poked = 0;
34678 +       for (i = 0; i < num_channels; i++) {
34679 +               if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
34680 +                       continue;
34681 +               if (st->channel[i].hub_addr == hub_addr &&
34682 +                       st->channel[i].port_addr == port_addr) {
34683 +                       switch (st->channel[i].fsm) {
34684 +                       case FIQ_PER_ISO_OUT_PENDING:
34685 +                               if (st->channel[i].nrpackets == 1) {
34686 +                                       st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST;
34687 +                               } else {
34688 +                                       st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE;
34689 +                               }
34690 +                               fiq_fsm_restart_channel(st, i, 0);
34691 +                               poked = 1;
34692 +                               break;
34693 +
34694 +                       default:
34695 +                               break;
34696 +                       }
34697 +               }
34698 +               if (poked)
34699 +                       break;
34700 +       }
34701 +       return poked;
34702 +}
34703 +
34704 +/**
34705 + * fiq_fsm_tt_in_use() - search for host channels using this TT
34706 + * @n: Channel to use as reference
34707 + *
34708 + */
34709 +int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n)
34710 +{
34711 +       int hub_addr = st->channel[n].hub_addr;
34712 +       int port_addr = st->channel[n].port_addr;
34713 +       int i, in_use = 0;
34714 +       for (i = 0; i < num_channels; i++) {
34715 +               if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH)
34716 +                       continue;
34717 +               switch (st->channel[i].fsm) {
34718 +               /* TT is reserved for channels that are in the middle of a periodic
34719 +                * split transaction.
34720 +                */
34721 +               case FIQ_PER_SSPLIT_STARTED:
34722 +               case FIQ_PER_CSPLIT_WAIT:
34723 +               case FIQ_PER_CSPLIT_NYET1:
34724 +               //case FIQ_PER_CSPLIT_POLL:
34725 +               case FIQ_PER_ISO_OUT_ACTIVE:
34726 +               case FIQ_PER_ISO_OUT_LAST:
34727 +                       if (st->channel[i].hub_addr == hub_addr &&
34728 +                               st->channel[i].port_addr == port_addr) {
34729 +                               in_use = 1;
34730 +                       }
34731 +                       break;
34732 +               default:
34733 +                       break;
34734 +               }
34735 +               if (in_use)
34736 +                       break;
34737 +       }
34738 +       return in_use;
34739 +}
34740 +
34741 +/**
34742 + * fiq_fsm_more_csplits() - determine whether additional CSPLITs need
34743 + *                     to be issued for this IN transaction.
34744 + *
34745 + * We cannot tell the inbound PID of a data packet due to hardware limitations.
34746 + * we need to make an educated guess as to whether we need to queue another CSPLIT
34747 + * or not. A no-brainer is when we have received enough data to fill the endpoint
34748 + * size, but for endpoints that give variable-length data then we have to resort
34749 + * to heuristics.
34750 + *
34751 + * We also return whether this is the last CSPLIT to be queued, again based on
34752 + * heuristics. This is to allow a 1-uframe overlap of periodic split transactions.
34753 + * Note: requires at least 1 CSPLIT to have been performed prior to being called.
34754 + */
34755 +
34756 +/*
34757 + * We need some way of guaranteeing if a returned periodic packet of size X
34758 + * has a DATA0 PID.
34759 + * The heuristic value of 144 bytes assumes that the received data has maximal
34760 + * bit-stuffing and the clock frequency of the transmitting device is at the lowest
34761 + * permissible limit. If the transfer length results in a final packet size
34762 + * 144 < p <= 188, then an erroneous CSPLIT will be issued.
34763 + * Also used to ensure that an endpoint will nominally only return a single
34764 + * complete-split worth of data.
34765 + */
34766 +#define DATA0_PID_HEURISTIC 144
34767 +
34768 +static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last)
34769 +{
34770 +
34771 +       int i;
34772 +       int total_len = 0;
34773 +       int more_needed = 1;
34774 +       struct fiq_channel_state *st = &state->channel[n];
34775 +
34776 +       for (i = 0; i < st->dma_info.index; i++) {
34777 +                       total_len += st->dma_info.slot_len[i];
34778 +       }
34779 +
34780 +       *probably_last = 0;
34781 +
34782 +       if (st->hcchar_copy.b.eptype == 0x3) {
34783 +               /*
34784 +                * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data
34785 +                * then this is definitely the last CSPLIT.
34786 +                */
34787 +               *probably_last = 1;
34788 +       } else {
34789 +               /* Isoc IN. This is a bit risky if we are the first transaction:
34790 +                * we may have been held off slightly. */
34791 +               if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) {
34792 +                       more_needed = 0;
34793 +               }
34794 +               /* If in the next uframe we will receive enough data to fill the endpoint,
34795 +                * then only issue 1 more csplit.
34796 +                */
34797 +               if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC)
34798 +                       *probably_last = 1;
34799 +       }
34800 +
34801 +       if (total_len >= st->hctsiz_copy.b.xfersize ||
34802 +               i == 6 || total_len == 0)
34803 +               /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for
34804 +                * a single endpoint. Accepting more would completely break our scheduling mechanism though
34805 +                * - in these extreme cases we will pass through a truncated packet.
34806 +                */
34807 +               more_needed = 0;
34808 +
34809 +       return more_needed;
34810 +}
34811 +
34812 +/**
34813 + * fiq_fsm_too_late() - Test transaction for lateness
34814 + *
34815 + * If a SSPLIT for a large IN transaction is issued too late in a frame,
34816 + * the hub will disable the port to the device and respond with ERR handshakes.
34817 + * The hub status endpoint will not reflect this change.
34818 + * Returns 1 if we will issue a SSPLIT that will result in a device babble.
34819 + */
34820 +int notrace fiq_fsm_too_late(struct fiq_state *st, int n)
34821 +{
34822 +       int uframe;
34823 +       hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
34824 +       uframe = hfnum.b.frnum & 0x7;
34825 +       if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) {
34826 +               return 1;
34827 +       } else {
34828 +               return 0;
34829 +       }
34830 +}
34831 +
34832 +
34833 +/**
34834 + * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline
34835 + *
34836 + * Search pending transactions in the start-split pending state and queue them.
34837 + * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4).
34838 + * Note: we specifically don't do isochronous OUT transactions first because better
34839 + * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT.
34840 + */
34841 +static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels)
34842 +{
34843 +       int n;
34844 +       hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) };
34845 +       if ((hfnum.b.frnum & 0x7) == 5)
34846 +               return;
34847 +       for (n = 0; n < num_channels; n++) {
34848 +               if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) {
34849 +                       /* Check to see if any other transactions are using this TT */
34850 +                       if(!fiq_fsm_tt_in_use(st, num_channels, n)) {
34851 +                               if (!fiq_fsm_too_late(st, n)) {
34852 +                                       st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
34853 +                                       fiq_print(FIQDBG_INT, st, "NEXTPER ");
34854 +                                       fiq_fsm_restart_channel(st, n, 0);
34855 +                               } else {
34856 +                                       st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
34857 +                               }
34858 +                               break;
34859 +                       }
34860 +               }
34861 +       }
34862 +       for (n = 0; n < num_channels; n++) {
34863 +               if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) {
34864 +                       if (!fiq_fsm_tt_in_use(st, num_channels, n)) {
34865 +                               fiq_print(FIQDBG_INT, st, "NEXTISO ");
34866 +                               st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
34867 +                               fiq_fsm_restart_channel(st, n, 0);
34868 +                               break;
34869 +                       }
34870 +               }
34871 +       }
34872 +}
34873 +
34874 +/**
34875 + * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data
34876 + * @state:     Pointer to fiq_state
34877 + * @n:         Channel transaction is active on
34878 + * @hcint:     Copy of host channel interrupt register
34879 + *
34880 + * Returns 0 if there are no more transactions for this HC to do, 1
34881 + * otherwise.
34882 + */
34883 +static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint)
34884 +{
34885 +       struct fiq_channel_state *st = &state->channel[n];
34886 +       int xfer_len = 0, nrpackets = 0;
34887 +       hcdma_data_t hcdma;
34888 +       fiq_print(FIQDBG_INT, state, "HSISO %02d", n);
34889 +
34890 +       xfer_len = fiq_get_xfer_len(state, n);
34891 +       st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len;
34892 +
34893 +       st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32;
34894 +
34895 +       st->hs_isoc_info.index++;
34896 +       if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) {
34897 +               return 0;
34898 +       }
34899 +
34900 +       /* grab the next DMA address offset from the array */
34901 +       hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset;
34902 +       FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32);
34903 +
34904 +       /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
34905 +        * the core needs to be told to send the correct number. Caution: for IN transfers,
34906 +        * this is always set to the maximum size of the endpoint. */
34907 +       xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length;
34908 +       /* Integer divide in a FIQ: fun. FIXME: make this not suck */
34909 +       nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
34910 +       if (nrpackets == 0)
34911 +               nrpackets = 1;
34912 +       st->hcchar_copy.b.multicnt = nrpackets;
34913 +       st->hctsiz_copy.b.pktcnt = nrpackets;
34914 +
34915 +       /* Initial PID also needs to be set */
34916 +       if (st->hcchar_copy.b.epdir == 0) {
34917 +               st->hctsiz_copy.b.xfersize = xfer_len;
34918 +               switch (st->hcchar_copy.b.multicnt) {
34919 +               case 1:
34920 +                       st->hctsiz_copy.b.pid = DWC_PID_DATA0;
34921 +                       break;
34922 +               case 2:
34923 +               case 3:
34924 +                       st->hctsiz_copy.b.pid = DWC_PID_MDATA;
34925 +                       break;
34926 +               }
34927 +
34928 +       } else {
34929 +               switch (st->hcchar_copy.b.multicnt) {
34930 +               st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
34931 +               case 1:
34932 +                       st->hctsiz_copy.b.pid = DWC_PID_DATA0;
34933 +                       break;
34934 +               case 2:
34935 +                       st->hctsiz_copy.b.pid = DWC_PID_DATA1;
34936 +                       break;
34937 +               case 3:
34938 +                       st->hctsiz_copy.b.pid = DWC_PID_DATA2;
34939 +                       break;
34940 +               }
34941 +       }
34942 +       FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32);
34943 +       FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32);
34944 +       /* Channel is enabled on hcint handler exit */
34945 +       fiq_print(FIQDBG_INT, state, "HSISOOUT");
34946 +       return 1;
34947 +}
34948 +
34949 +
34950 +/**
34951 + * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler
34952 + * @state:     Pointer to the state struct passed from banked FIQ mode registers.
34953 + * @num_channels:      set according to the DWC hardware configuration
34954 + *
34955 + * The SOF handler in FSM mode has two functions
34956 + * 1. Hold off SOF from causing schedule advancement in IRQ context if there's
34957 + *    nothing to do
34958 + * 2. Advance certain FSM states that require either a microframe delay, or a microframe
34959 + *    of holdoff.
34960 + *
34961 + * The second part is architecture-specific to mach-bcm2835 -
34962 + * a sane interrupt controller would have a mask register for ARM interrupt sources
34963 + * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt
34964 + * number (USB) can be enabled. This means that certain parts of the USB specification
34965 + * that require "wait a little while, then issue another packet" cannot be fulfilled with
34966 + * the timing granularity required to achieve optimal throughout. The workaround is to use
34967 + * the SOF "timer" (125uS) to perform this task.
34968 + */
34969 +static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels)
34970 +{
34971 +       hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) };
34972 +       int n;
34973 +       int kick_irq = 0;
34974 +
34975 +       if ((hfnum.b.frnum & 0x7) == 1) {
34976 +               /* We cannot issue csplits for transactions in the last frame past (n+1).1
34977 +                * Check to see if there are any transactions that are stale.
34978 +                * Boot them out.
34979 +                */
34980 +               for (n = 0; n < num_channels; n++) {
34981 +                       switch (state->channel[n].fsm) {
34982 +                       case FIQ_PER_CSPLIT_WAIT:
34983 +                       case FIQ_PER_CSPLIT_NYET1:
34984 +                       case FIQ_PER_CSPLIT_POLL:
34985 +                       case FIQ_PER_CSPLIT_LAST:
34986 +                               /* Check if we are no longer in the same full-speed frame. */
34987 +                               if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) <
34988 +                                               (hfnum.b.frnum & ~0x7))
34989 +                                       state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
34990 +                               break;
34991 +                       default:
34992 +                               break;
34993 +                       }
34994 +               }
34995 +       }
34996 +
34997 +       for (n = 0; n < num_channels; n++) {
34998 +               switch (state->channel[n].fsm) {
34999 +
35000 +               case FIQ_NP_SSPLIT_RETRY:
35001 +               case FIQ_NP_IN_CSPLIT_RETRY:
35002 +               case FIQ_NP_OUT_CSPLIT_RETRY:
35003 +                       fiq_fsm_restart_channel(state, n, 0);
35004 +                       break;
35005 +
35006 +               case FIQ_HS_ISOC_SLEEPING:
35007 +                       /* Is it time to wake this channel yet? */
35008 +                       if (--state->channel[n].uframe_sleeps == 0) {
35009 +                               state->channel[n].fsm = FIQ_HS_ISOC_TURBO;
35010 +                               fiq_fsm_restart_channel(state, n, 0);
35011 +                       }
35012 +                       break;
35013 +
35014 +               case FIQ_PER_SSPLIT_QUEUED:
35015 +                       if ((hfnum.b.frnum & 0x7) == 5)
35016 +                               break;
35017 +                       if(!fiq_fsm_tt_in_use(state, num_channels, n)) {
35018 +                               if (!fiq_fsm_too_late(state, n)) {
35019 +                                       fiq_print(FIQDBG_INT, state, "SOF GO %01d", n);
35020 +                                       fiq_fsm_restart_channel(state, n, 0);
35021 +                                       state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED;
35022 +                               } else {
35023 +                                       /* Transaction cannot be started without risking a device babble error */
35024 +                                       state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT;
35025 +                                       state->haintmsk_saved.b2.chint &= ~(1 << n);
35026 +                                       FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
35027 +                                       kick_irq |= 1;
35028 +                               }
35029 +                       }
35030 +                       break;
35031 +
35032 +               case FIQ_PER_ISO_OUT_PENDING:
35033 +                       /* Ordinarily, this should be poked after the SSPLIT
35034 +                        * complete interrupt for a competing transfer on the same
35035 +                        * TT. Doesn't happen for aborted transactions though.
35036 +                        */
35037 +                       if ((hfnum.b.frnum & 0x7) >= 5)
35038 +                               break;
35039 +                       if (!fiq_fsm_tt_in_use(state, num_channels, n)) {
35040 +                               /* Hardware bug. SOF can sometimes occur after the channel halt interrupt
35041 +                                * that caused this.
35042 +                                */
35043 +                                       fiq_fsm_restart_channel(state, n, 0);
35044 +                                       fiq_print(FIQDBG_INT, state, "SOF ISOC");
35045 +                                       if (state->channel[n].nrpackets == 1) {
35046 +                                               state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST;
35047 +                                       } else {
35048 +                                               state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE;
35049 +                                       }
35050 +                       }
35051 +                       break;
35052 +
35053 +               case FIQ_PER_CSPLIT_WAIT:
35054 +                       /* we are guaranteed to be in this state if and only if the SSPLIT interrupt
35055 +                        * occurred when the bus transaction occurred. The SOF interrupt reversal bug
35056 +                        * will utterly bugger this up though.
35057 +                        */
35058 +                       if (hfnum.b.frnum != state->channel[n].expected_uframe) {
35059 +                               fiq_print(FIQDBG_INT, state, "SOFCS %d ", n);
35060 +                               state->channel[n].fsm = FIQ_PER_CSPLIT_POLL;
35061 +                               fiq_fsm_restart_channel(state, n, 0);
35062 +                               fiq_fsm_start_next_periodic(state, num_channels);
35063 +
35064 +                       }
35065 +                       break;
35066 +
35067 +               case FIQ_PER_SPLIT_TIMEOUT:
35068 +               case FIQ_DEQUEUE_ISSUED:
35069 +                       /* Ugly: we have to force a HCD interrupt.
35070 +                        * Poke the mask for the channel in question.
35071 +                        * We will take a fake SOF because of this, but
35072 +                        * that's OK.
35073 +                        */
35074 +                       state->haintmsk_saved.b2.chint &= ~(1 << n);
35075 +                       FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0);
35076 +                       kick_irq |= 1;
35077 +                       break;
35078 +
35079 +               default:
35080 +                       break;
35081 +               }
35082 +       }
35083 +
35084 +       if (state->kick_np_queues ||
35085 +                       dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum))
35086 +               kick_irq |= 1;
35087 +
35088 +       return !kick_irq;
35089 +}
35090 +
35091 +
35092 +/**
35093 + * fiq_fsm_do_hcintr() - FSM host channel interrupt handler
35094 + * @state: Pointer to the FIQ state struct
35095 + * @num_channels: Number of channels as per hardware config
35096 + * @n: channel for which HAINT(i) was raised
35097 + *
35098 + * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well.
35099 + */
35100 +static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n)
35101 +{
35102 +       hcint_data_t hcint;
35103 +       hcintmsk_data_t hcintmsk;
35104 +       hcint_data_t hcint_probe;
35105 +       hcchar_data_t hcchar;
35106 +       int handled = 0;
35107 +       int restart = 0;
35108 +       int last_csplit = 0;
35109 +       int start_next_periodic = 0;
35110 +       struct fiq_channel_state *st = &state->channel[n];
35111 +       hfnum_data_t hfnum;
35112 +
35113 +       hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT);
35114 +       hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK);
35115 +       hcint_probe.d32 = hcint.d32 & hcintmsk.d32;
35116 +
35117 +       if (st->fsm != FIQ_PASSTHROUGH) {
35118 +               fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm);
35119 +               fiq_print(FIQDBG_INT, state, "%08x", hcint.d32);
35120 +       }
35121 +
35122 +       switch (st->fsm) {
35123 +
35124 +       case FIQ_PASSTHROUGH:
35125 +       case FIQ_DEQUEUE_ISSUED:
35126 +               /* doesn't belong to us, kick it upstairs */
35127 +               break;
35128 +
35129 +       case FIQ_PASSTHROUGH_ERRORSTATE:
35130 +               /* We are here to emulate the error recovery mechanism of the dwc HCD.
35131 +                * Several interrupts are unmasked if a previous transaction failed - it's
35132 +                * death for the FIQ to attempt to handle them as the channel isn't halted.
35133 +                * Emulate what the HCD does in this situation: mask and continue.
35134 +                * The FSM has no other state setup so this has to be handled out-of-band.
35135 +                */
35136 +               fiq_print(FIQDBG_ERR, state, "ERRST %02d", n);
35137 +               if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) {
35138 +                       fiq_print(FIQDBG_ERR, state, "RESET %02d", n);
35139 +                       /* In some random cases we can get a NAK interrupt coincident with a Xacterr
35140 +                        * interrupt, after the device has disappeared.
35141 +                        */
35142 +                       if (!hcint.b.xacterr)
35143 +                               st->nr_errors = 0;
35144 +                       hcintmsk.b.nak = 0;
35145 +                       hcintmsk.b.ack = 0;
35146 +                       hcintmsk.b.datatglerr = 0;
35147 +                       FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32);
35148 +                       return 1;
35149 +               }
35150 +               if (hcint_probe.b.chhltd) {
35151 +                       fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n);
35152 +                       fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32);
35153 +                       return 0;
35154 +               }
35155 +               break;
35156 +
35157 +       /* Non-periodic state groups */
35158 +       case FIQ_NP_SSPLIT_STARTED:
35159 +       case FIQ_NP_SSPLIT_RETRY:
35160 +               /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */
35161 +               if (hcint.b.ack) {
35162 +                       /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction
35163 +                        * will start shortly. SOF needs to kick the transaction to prevent a NYET flood.
35164 +                        */
35165 +                       if(st->hcchar_copy.b.epdir == 1)
35166 +                               st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
35167 +                       else
35168 +                               st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35169 +                       st->nr_errors = 0;
35170 +                       handled = 1;
35171 +                       fiq_fsm_setup_csplit(state, n);
35172 +               } else if (hcint.b.nak) {
35173 +                       // No buffer space in TT. Retry on a uframe boundary.
35174 +                       st->fsm = FIQ_NP_SSPLIT_RETRY;
35175 +                       handled = 1;
35176 +               } else if (hcint.b.xacterr) {
35177 +                       // The only other one we care about is xacterr. This implies HS bus error - retry.
35178 +                       st->nr_errors++;
35179 +                       st->fsm = FIQ_NP_SSPLIT_RETRY;
35180 +                       if (st->nr_errors >= 3) {
35181 +                               st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35182 +                       } else {
35183 +                               handled = 1;
35184 +                               restart = 1;
35185 +                       }
35186 +               } else {
35187 +                       st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35188 +                       handled = 0;
35189 +                       restart = 0;
35190 +               }
35191 +               break;
35192 +
35193 +       case FIQ_NP_IN_CSPLIT_RETRY:
35194 +               /* Received a CSPLIT done interrupt.
35195 +                * Expected Data/NAK/STALL/NYET for IN.
35196 +                */
35197 +               if (hcint.b.xfercomp) {
35198 +                       /* For IN, data is present. */
35199 +                       st->fsm = FIQ_NP_SPLIT_DONE;
35200 +               } else if (hcint.b.nak) {
35201 +                       /* no endpoint data. Punt it upstairs */
35202 +                       st->fsm = FIQ_NP_SPLIT_DONE;
35203 +               } else if (hcint.b.nyet) {
35204 +                       /* CSPLIT NYET - retry on a uframe boundary. */
35205 +                       handled = 1;
35206 +                       st->nr_errors = 0;
35207 +               } else if (hcint.b.datatglerr) {
35208 +                       /* data toggle errors do not set the xfercomp bit. */
35209 +                       st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35210 +               } else if (hcint.b.xacterr) {
35211 +                       /* HS error. Retry immediate */
35212 +                       st->fsm = FIQ_NP_IN_CSPLIT_RETRY;
35213 +                       st->nr_errors++;
35214 +                       if (st->nr_errors >= 3) {
35215 +                               st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35216 +                       } else {
35217 +                               handled = 1;
35218 +                               restart = 1;
35219 +                       }
35220 +               } else if (hcint.b.stall || hcint.b.bblerr) {
35221 +                       /* A STALL implies either a LS bus error or a genuine STALL. */
35222 +                       st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35223 +               } else {
35224 +                       /*  Hardware bug. It's possible in some cases to
35225 +                        *  get a channel halt with nothing else set when
35226 +                        *  the response was a NYET. Treat as local 3-strikes retry.
35227 +                        */
35228 +                       hcint_data_t hcint_test = hcint;
35229 +                       hcint_test.b.chhltd = 0;
35230 +                       if (!hcint_test.d32) {
35231 +                               st->nr_errors++;
35232 +                               if (st->nr_errors >= 3) {
35233 +                                       st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35234 +                               } else {
35235 +                                       handled = 1;
35236 +                               }
35237 +                       } else {
35238 +                               /* Bail out if something unexpected happened */
35239 +                               st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35240 +                       }
35241 +               }
35242 +               break;
35243 +
35244 +       case FIQ_NP_OUT_CSPLIT_RETRY:
35245 +               /* Received a CSPLIT done interrupt.
35246 +                * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/
35247 +               if (hcint.b.xfercomp) {
35248 +                       st->fsm = FIQ_NP_SPLIT_DONE;
35249 +               } else if (hcint.b.nak) {
35250 +                       // The HCD will implement the holdoff on frame boundaries.
35251 +                       st->fsm = FIQ_NP_SPLIT_DONE;
35252 +               } else if (hcint.b.nyet) {
35253 +                       // Hub still processing.
35254 +                       st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35255 +                       handled = 1;
35256 +                       st->nr_errors = 0;
35257 +                       //restart = 1;
35258 +               } else if (hcint.b.xacterr) {
35259 +                       /* HS error. retry immediate */
35260 +                       st->fsm = FIQ_NP_OUT_CSPLIT_RETRY;
35261 +                       st->nr_errors++;
35262 +                       if (st->nr_errors >= 3) {
35263 +                               st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35264 +                       } else {
35265 +                               handled = 1;
35266 +                               restart = 1;
35267 +                       }
35268 +               } else if (hcint.b.stall) {
35269 +                       /* LS bus error or genuine stall */
35270 +                       st->fsm = FIQ_NP_SPLIT_LS_ABORTED;
35271 +               } else {
35272 +                       /*
35273 +                        * Hardware bug. It's possible in some cases to get a
35274 +                        * channel halt with nothing else set when the response was a NYET.
35275 +                        * Treat as local 3-strikes retry.
35276 +                        */
35277 +                       hcint_data_t hcint_test = hcint;
35278 +                       hcint_test.b.chhltd = 0;
35279 +                       if (!hcint_test.d32) {
35280 +                               st->nr_errors++;
35281 +                               if (st->nr_errors >= 3) {
35282 +                                       st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35283 +                               } else {
35284 +                                       handled = 1;
35285 +                               }
35286 +                       } else {
35287 +                               // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it.
35288 +                               st->fsm = FIQ_NP_SPLIT_HS_ABORTED;
35289 +                       }
35290 +               }
35291 +               break;
35292 +
35293 +       /* Periodic split states (except isoc out) */
35294 +       case FIQ_PER_SSPLIT_STARTED:
35295 +               /* Expect an ACK or failure for SSPLIT */
35296 +               if (hcint.b.ack) {
35297 +                       /*
35298 +                        * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs.
35299 +                        * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1
35300 +                        * point for microframe n-3, the packet will not appear on the bus until microframe n.
35301 +                        * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus
35302 +                        * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1
35303 +                        * coincident with SOF for n+1.
35304 +                        * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place.
35305 +                        * These appear to be caused by timing/clock crossing bugs within the core itself.
35306 +                        * State machine workaround.
35307 +                        */
35308 +                       hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35309 +                       hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35310 +                       fiq_fsm_setup_csplit(state, n);
35311 +                       /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct
35312 +                        * time. If not, then we're in the next SOF.
35313 +                        */
35314 +                       if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) {
35315 +                               fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n);
35316 +                               st->expected_uframe = hfnum.b.frnum;
35317 +                               st->fsm = FIQ_PER_CSPLIT_WAIT;
35318 +                       } else {
35319 +                               fiq_print(FIQDBG_INT, state, "CSPOL  %01d", n);
35320 +                               /* For isochronous IN endpoints,
35321 +                                * we need to hold off if we are expecting a lot of data */
35322 +                               if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) {
35323 +                                       start_next_periodic = 1;
35324 +                               }
35325 +                               /* Danger will robinson: we are in a broken state. If our first interrupt after
35326 +                                * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable
35327 +                                * lag. Unmask the NYET interrupt.
35328 +                                */
35329 +                               st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF;
35330 +                               st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1;
35331 +                               restart = 1;
35332 +                       }
35333 +                       handled = 1;
35334 +               } else if (hcint.b.xacterr) {
35335 +                       /* 3-strikes retry is enabled, we have hit our max nr_errors */
35336 +                       st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35337 +                       start_next_periodic = 1;
35338 +               } else {
35339 +                       st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35340 +                       start_next_periodic = 1;
35341 +               }
35342 +               /* We can now queue the next isochronous OUT transaction, if one is pending. */
35343 +               if(fiq_fsm_tt_next_isoc(state, num_channels, n)) {
35344 +                       fiq_print(FIQDBG_INT, state, "NEXTISO ");
35345 +               }
35346 +               break;
35347 +
35348 +       case FIQ_PER_CSPLIT_NYET1:
35349 +               /* First CSPLIT attempt was a NYET. If we get a subsequent NYET,
35350 +                * we are too late and the TT has dropped its CSPLIT fifo.
35351 +                */
35352 +               hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35353 +               hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35354 +               start_next_periodic = 1;
35355 +               if (hcint.b.nak) {
35356 +                       st->fsm = FIQ_PER_SPLIT_DONE;
35357 +               } else if (hcint.b.xfercomp) {
35358 +                       fiq_increment_dma_buf(state, num_channels, n);
35359 +                       st->fsm = FIQ_PER_CSPLIT_POLL;
35360 +                       st->nr_errors = 0;
35361 +                       if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35362 +                               handled = 1;
35363 +                               restart = 1;
35364 +                               if (!last_csplit)
35365 +                                       start_next_periodic = 0;
35366 +                       } else {
35367 +                               st->fsm = FIQ_PER_SPLIT_DONE;
35368 +                       }
35369 +               } else if (hcint.b.nyet) {
35370 +                       /* Doh. Data lost. */
35371 +                       st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35372 +               } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35373 +                       st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35374 +               } else {
35375 +                       st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35376 +               }
35377 +               break;
35378 +
35379 +       case FIQ_PER_CSPLIT_BROKEN_NYET1:
35380 +               /*
35381 +                * we got here because our host channel is in the delayed-interrupt
35382 +                * state and we cannot take a NYET interrupt any later than when it
35383 +                * occurred. Disable then re-enable the channel if this happens to force
35384 +                * CSPLITs to occur at the right time.
35385 +                */
35386 +               hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35387 +               hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35388 +               fiq_print(FIQDBG_INT, state, "BROK: %01d ", n);
35389 +               if (hcint.b.nak) {
35390 +                       st->fsm = FIQ_PER_SPLIT_DONE;
35391 +                       start_next_periodic = 1;
35392 +               } else if (hcint.b.xfercomp) {
35393 +                       fiq_increment_dma_buf(state, num_channels, n);
35394 +                       if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35395 +                               st->fsm = FIQ_PER_CSPLIT_POLL;
35396 +                               handled = 1;
35397 +                               restart = 1;
35398 +                               start_next_periodic = 1;
35399 +                               /* Reload HCTSIZ for the next transfer */
35400 +                               fiq_fsm_reload_hctsiz(state, n);
35401 +                               if (!last_csplit)
35402 +                                       start_next_periodic = 0;
35403 +                       } else {
35404 +                               st->fsm = FIQ_PER_SPLIT_DONE;
35405 +                       }
35406 +               } else if (hcint.b.nyet) {
35407 +                       st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35408 +                       start_next_periodic = 1;
35409 +               } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35410 +                       /* Local 3-strikes retry is handled by the core. This is a ERR response.*/
35411 +                       st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35412 +               } else {
35413 +                       st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35414 +               }
35415 +               break;
35416 +
35417 +       case FIQ_PER_CSPLIT_POLL:
35418 +               hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35419 +               hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR);
35420 +               start_next_periodic = 1;
35421 +               if (hcint.b.nak) {
35422 +                       st->fsm = FIQ_PER_SPLIT_DONE;
35423 +               } else if (hcint.b.xfercomp) {
35424 +                       fiq_increment_dma_buf(state, num_channels, n);
35425 +                       if (fiq_fsm_more_csplits(state, n, &last_csplit)) {
35426 +                               handled = 1;
35427 +                               restart = 1;
35428 +                               /* Reload HCTSIZ for the next transfer */
35429 +                               fiq_fsm_reload_hctsiz(state, n);
35430 +                               if (!last_csplit)
35431 +                                       start_next_periodic = 0;
35432 +                       } else {
35433 +                               st->fsm = FIQ_PER_SPLIT_DONE;
35434 +                       }
35435 +               } else if (hcint.b.nyet) {
35436 +                       /* Are we a NYET after the first data packet? */
35437 +                       if (st->nrpackets == 0) {
35438 +                               st->fsm = FIQ_PER_CSPLIT_NYET1;
35439 +                               handled = 1;
35440 +                               restart = 1;
35441 +                       } else {
35442 +                               /* We got a NYET when polling CSPLITs. Can happen
35443 +                                * if our heuristic fails, or if someone disables us
35444 +                                * for any significant length of time.
35445 +                                */
35446 +                               if (st->nr_errors >= 3) {
35447 +                                       st->fsm = FIQ_PER_SPLIT_NYET_ABORTED;
35448 +                               } else {
35449 +                                       st->fsm = FIQ_PER_SPLIT_DONE;
35450 +                               }
35451 +                       }
35452 +               } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) {
35453 +                       /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/
35454 +                       st->fsm = FIQ_PER_SPLIT_LS_ABORTED;
35455 +               } else {
35456 +                       st->fsm = FIQ_PER_SPLIT_HS_ABORTED;
35457 +               }
35458 +               break;
35459 +
35460 +       case FIQ_HS_ISOC_TURBO:
35461 +               if (fiq_fsm_update_hs_isoc(state, n, hcint)) {
35462 +                       /* more transactions to come */
35463 +                       handled = 1;
35464 +                       fiq_print(FIQDBG_INT, state, "HSISO M ");
35465 +                       /* For strided transfers, put ourselves to sleep */
35466 +                       if (st->hs_isoc_info.stride > 1) {
35467 +                               st->uframe_sleeps = st->hs_isoc_info.stride - 1;
35468 +                               st->fsm = FIQ_HS_ISOC_SLEEPING;
35469 +                       } else {
35470 +                               restart = 1;
35471 +                       }
35472 +               } else {
35473 +                       st->fsm = FIQ_HS_ISOC_DONE;
35474 +                       fiq_print(FIQDBG_INT, state, "HSISO F ");
35475 +               }
35476 +               break;
35477 +
35478 +       case FIQ_HS_ISOC_ABORTED:
35479 +               /* This abort is called by the driver rewriting the state mid-transaction
35480 +                * which allows the dequeue mechanism to work more effectively.
35481 +                */
35482 +               break;
35483 +
35484 +       case FIQ_PER_ISO_OUT_ACTIVE:
35485 +               if (hcint.b.ack) {
35486 +                       if(fiq_iso_out_advance(state, num_channels, n)) {
35487 +                               /* last OUT transfer */
35488 +                               st->fsm = FIQ_PER_ISO_OUT_LAST;
35489 +                               /*
35490 +                                * Assuming the periodic FIFO in the dwc core
35491 +                                * actually does its job properly, we can queue
35492 +                                * the next ssplit now and in theory, the wire
35493 +                                * transactions will be in-order.
35494 +                                */
35495 +                               // No it doesn't. It appears to process requests in host channel order.
35496 +                               //start_next_periodic = 1;
35497 +                       }
35498 +                       handled = 1;
35499 +                       restart = 1;
35500 +               } else {
35501 +                       /*
35502 +                        * Isochronous transactions carry on regardless. Log the error
35503 +                        * and continue.
35504 +                        */
35505 +                       //explode += 1;
35506 +                       st->nr_errors++;
35507 +                       if(fiq_iso_out_advance(state, num_channels, n)) {
35508 +                               st->fsm = FIQ_PER_ISO_OUT_LAST;
35509 +                               //start_next_periodic = 1;
35510 +                       }
35511 +                       handled = 1;
35512 +                       restart = 1;
35513 +               }
35514 +               break;
35515 +
35516 +       case FIQ_PER_ISO_OUT_LAST:
35517 +               if (hcint.b.ack) {
35518 +                       /* All done here */
35519 +                       st->fsm = FIQ_PER_ISO_OUT_DONE;
35520 +               } else {
35521 +                       st->fsm = FIQ_PER_ISO_OUT_DONE;
35522 +                       st->nr_errors++;
35523 +               }
35524 +               start_next_periodic = 1;
35525 +               break;
35526 +
35527 +       case FIQ_PER_SPLIT_TIMEOUT:
35528 +               /* SOF kicked us because we overran. */
35529 +               start_next_periodic = 1;
35530 +               break;
35531 +
35532 +       default:
35533 +               break;
35534 +       }
35535 +
35536 +       if (handled) {
35537 +               FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32);
35538 +       } else {
35539 +               /* Copy the regs into the state so the IRQ knows what to do */
35540 +               st->hcint_copy.d32 = hcint.d32;
35541 +       }
35542 +
35543 +       if (restart) {
35544 +               /* Restart always implies handled. */
35545 +               if (restart == 2) {
35546 +                       /* For complete-split INs, the show must go on.
35547 +                        * Force a channel restart */
35548 +                       fiq_fsm_restart_channel(state, n, 1);
35549 +               } else {
35550 +                       fiq_fsm_restart_channel(state, n, 0);
35551 +               }
35552 +       }
35553 +       if (start_next_periodic) {
35554 +               fiq_fsm_start_next_periodic(state, num_channels);
35555 +       }
35556 +       if (st->fsm != FIQ_PASSTHROUGH)
35557 +               fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm);
35558 +
35559 +       return handled;
35560 +}
35561 +
35562 +
35563 +/**
35564 + * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ
35565 + * @state:             pointer to state struct passed from the banked FIQ mode registers.
35566 + * @num_channels:      set according to the DWC hardware configuration
35567 + * @dma:               pointer to DMA bounce buffers for split transaction slots
35568 + *
35569 + * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode
35570 + * inside an EHCI or similar host controller regarding split transactions. The DWC core
35571 + * interrupts each and every time a split transaction packet is received or sent successfully.
35572 + * This results in either an interrupt storm when everything is working "properly", or
35573 + * the interrupt latency of the system in general breaks time-sensitive periodic split
35574 + * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ
35575 + * solves these problems.
35576 + *
35577 + * Return: void
35578 + */
35579 +void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels)
35580 +{
35581 +       gintsts_data_t gintsts, gintsts_handled;
35582 +       gintmsk_data_t gintmsk;
35583 +       //hfnum_data_t hfnum;
35584 +       haint_data_t haint, haint_handled;
35585 +       haintmsk_data_t haintmsk;
35586 +       int kick_irq = 0;
35587 +
35588 +       gintsts_handled.d32 = 0;
35589 +       haint_handled.d32 = 0;
35590 +
35591 +       fiq_fsm_spin_lock(&state->lock);
35592 +       gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
35593 +       gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
35594 +       gintsts.d32 &= gintmsk.d32;
35595 +
35596 +       if (gintsts.b.sofintr) {
35597 +               /* For FSM mode, SOF is required to keep the state machine advance for
35598 +                * certain stages of the periodic pipeline. It's death to mask this
35599 +                * interrupt in that case.
35600 +                */
35601 +
35602 +               if (!fiq_fsm_do_sof(state, num_channels)) {
35603 +                       /* Kick IRQ once. Queue advancement means that all pending transactions
35604 +                        * will get serviced when the IRQ finally executes.
35605 +                        */
35606 +                       if (state->gintmsk_saved.b.sofintr == 1)
35607 +                               kick_irq |= 1;
35608 +                       state->gintmsk_saved.b.sofintr = 0;
35609 +               }
35610 +               gintsts_handled.b.sofintr = 1;
35611 +       }
35612 +
35613 +       if (gintsts.b.hcintr) {
35614 +               int i;
35615 +               haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT);
35616 +               haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK);
35617 +               haint.d32 &= haintmsk.d32;
35618 +               haint_handled.d32 = 0;
35619 +               for (i=0; i<num_channels; i++) {
35620 +                       if (haint.b2.chint & (1 << i)) {
35621 +                               if(!fiq_fsm_do_hcintr(state, num_channels, i)) {
35622 +                                       /* HCINT was not handled in FIQ
35623 +                                        * HAINT is level-sensitive, leading to level-sensitive ginststs.b.hcint bit.
35624 +                                        * Mask HAINT(i) but keep top-level hcint unmasked.
35625 +                                        */
35626 +                                       state->haintmsk_saved.b2.chint &= ~(1 << i);
35627 +                               } else {
35628 +                                       /* do_hcintr cleaned up after itself, but clear haint */
35629 +                                       haint_handled.b2.chint |= (1 << i);
35630 +                               }
35631 +                       }
35632 +               }
35633 +
35634 +               if (haint_handled.b2.chint) {
35635 +                       FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32);
35636 +               }
35637 +
35638 +               if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) {
35639 +                       /*
35640 +                        * This is necessary to avoid multiple retriggers of the MPHI in the case
35641 +                        * where interrupts are held off and HCINTs start to pile up.
35642 +                        * Only wake up the IRQ if a new interrupt came in, was not handled and was
35643 +                        * masked.
35644 +                        */
35645 +                       haintmsk.d32 &= state->haintmsk_saved.d32;
35646 +                       FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32);
35647 +                       kick_irq |= 1;
35648 +               }
35649 +               /* Top-Level interrupt - always handled because it's level-sensitive */
35650 +               gintsts_handled.b.hcintr = 1;
35651 +       }
35652 +
35653 +
35654 +       /* Clear the bits in the saved register that were not handled but were triggered. */
35655 +       state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
35656 +
35657 +       /* FIQ didn't handle something - mask has changed - write new mask */
35658 +       if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) {
35659 +               gintmsk.d32 &= state->gintmsk_saved.d32;
35660 +               gintmsk.b.sofintr = 1;
35661 +               FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
35662 +//             fiq_print(FIQDBG_INT, state, "KICKGINT");
35663 +//             fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32);
35664 +//             fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32);
35665 +               kick_irq |= 1;
35666 +       }
35667 +
35668 +       if (gintsts_handled.d32) {
35669 +               /* Only applies to edge-sensitive bits in GINTSTS */
35670 +               FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
35671 +       }
35672 +
35673 +       /* We got an interrupt, didn't handle it. */
35674 +       if (kick_irq) {
35675 +               state->mphi_int_count++;
35676 +               FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
35677 +               FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
35678 +
35679 +       }
35680 +       state->fiq_done++;
35681 +       mb();
35682 +       fiq_fsm_spin_unlock(&state->lock);
35683 +}
35684 +
35685 +
35686 +/**
35687 + * dwc_otg_fiq_nop() - FIQ "lite"
35688 + * @state:     pointer to state struct passed from the banked FIQ mode registers.
35689 + *
35690 + * The "nop" handler does not intervene on any interrupts other than SOF.
35691 + * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals
35692 + * with non-periodic/periodic queues) needs to be kicked.
35693 + *
35694 + * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second.
35695 + *
35696 + * Return: void
35697 + */
35698 +void notrace dwc_otg_fiq_nop(struct fiq_state *state)
35699 +{
35700 +       gintsts_data_t gintsts, gintsts_handled;
35701 +       gintmsk_data_t gintmsk;
35702 +       hfnum_data_t hfnum;
35703 +
35704 +       fiq_fsm_spin_lock(&state->lock);
35705 +       hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM);
35706 +       gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS);
35707 +       gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK);
35708 +       gintsts.d32 &= gintmsk.d32;
35709 +       gintsts_handled.d32 = 0;
35710 +
35711 +       if (gintsts.b.sofintr) {
35712 +               if (!state->kick_np_queues &&
35713 +                               dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) {
35714 +                       /* SOF handled, no work to do, just ACK interrupt */
35715 +                       gintsts_handled.b.sofintr = 1;
35716 +               } else {
35717 +                       /* Kick IRQ */
35718 +                       state->gintmsk_saved.b.sofintr = 0;
35719 +               }
35720 +       }
35721 +
35722 +       /* Reset handled interrupts */
35723 +       if(gintsts_handled.d32) {
35724 +               FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32);
35725 +       }
35726 +
35727 +       /* Clear the bits in the saved register that were not handled but were triggered. */
35728 +       state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32);
35729 +
35730 +       /* We got an interrupt, didn't handle it and want to mask it */
35731 +       if (~(state->gintmsk_saved.d32)) {
35732 +               state->mphi_int_count++;
35733 +               gintmsk.d32 &= state->gintmsk_saved.d32;
35734 +               FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32);
35735 +               /* Force a clear before another dummy send */
35736 +               FIQ_WRITE(state->mphi_regs.intstat, (1<<29));
35737 +               FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send);
35738 +               FIQ_WRITE(state->mphi_regs.outddb, (1<<29));
35739 +
35740 +       }
35741 +       state->fiq_done++;
35742 +       mb();
35743 +       fiq_fsm_spin_unlock(&state->lock);
35744 +}
35745 --- /dev/null
35746 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h
35747 @@ -0,0 +1,370 @@
35748 +/*
35749 + * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions
35750 + *
35751 + * Copyright (c) 2013 Raspberry Pi Foundation
35752 + *
35753 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
35754 + * All rights reserved.
35755 + *
35756 + * Redistribution and use in source and binary forms, with or without
35757 + * modification, are permitted provided that the following conditions are met:
35758 + *     * Redistributions of source code must retain the above copyright
35759 + *       notice, this list of conditions and the following disclaimer.
35760 + *     * Redistributions in binary form must reproduce the above copyright
35761 + *       notice, this list of conditions and the following disclaimer in the
35762 + *       documentation and/or other materials provided with the distribution.
35763 + *     * Neither the name of Raspberry Pi nor the
35764 + *       names of its contributors may be used to endorse or promote products
35765 + *       derived from this software without specific prior written permission.
35766 + *
35767 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35768 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35769 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35770 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
35771 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35772 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
35773 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
35774 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35775 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35776 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35777 + *
35778 + * This FIQ implements functionality that performs split transactions on
35779 + * the dwc_otg hardware without any outside intervention. A split transaction
35780 + * is "queued" by nominating a specific host channel to perform the entirety
35781 + * of a split transaction. This FIQ will then perform the microframe-precise
35782 + * scheduling required in each phase of the transaction until completion.
35783 + *
35784 + * The FIQ functionality has been surgically implanted into the Synopsys
35785 + * vendor-provided driver.
35786 + *
35787 + */
35788 +
35789 +#ifndef DWC_OTG_FIQ_FSM_H_
35790 +#define DWC_OTG_FIQ_FSM_H_
35791 +
35792 +#include "dwc_otg_regs.h"
35793 +#include "dwc_otg_cil.h"
35794 +#include "dwc_otg_hcd.h"
35795 +#include <linux/kernel.h>
35796 +#include <linux/irqflags.h>
35797 +#include <linux/string.h>
35798 +#include <asm/barrier.h>
35799 +
35800 +#if 0
35801 +#define FLAME_ON(x)                                    \
35802 +do {                                                   \
35803 +       int gpioreg;                                    \
35804 +                                                       \
35805 +       gpioreg = readl(__io_address(0x20200000+0x8));  \
35806 +       gpioreg &= ~(7 << (x-20)*3);                    \
35807 +       gpioreg |= 0x1 << (x-20)*3;                     \
35808 +       writel(gpioreg, __io_address(0x20200000+0x8));  \
35809 +                                                       \
35810 +       writel(1<<x, __io_address(0x20200000+(0x1C)));  \
35811 +} while (0)
35812 +
35813 +#define FLAME_OFF(x)                                   \
35814 +do {                                                   \
35815 +       writel(1<<x, __io_address(0x20200000+(0x28)));  \
35816 +} while (0)
35817 +#else
35818 +#define FLAME_ON(x) do { } while (0)
35819 +#define FLAME_OFF(X) do { } while (0)
35820 +#endif
35821 +
35822 +/* This is a quick-and-dirty arch-specific register read/write. We know that
35823 + * writes to a peripheral on BCM2835 will always arrive in-order, also that
35824 + * reads and writes are executed in-order therefore the need for memory barriers
35825 + * is obviated if we're only talking to USB.
35826 + */
35827 +#define FIQ_WRITE(_addr_,_data_) (*(volatile unsigned int *) (_addr_) = (_data_))
35828 +#define FIQ_READ(_addr_) (*(volatile unsigned int *) (_addr_))
35829 +
35830 +/* FIQ-ified register definitions. Offsets are from dwc_regs_base. */
35831 +#define GINTSTS                0x014
35832 +#define GINTMSK                0x018
35833 +/* Debug register. Poll the top of the received packets FIFO. */
35834 +#define GRXSTSR                0x01C
35835 +#define HFNUM          0x408
35836 +#define HAINT          0x414
35837 +#define HAINTMSK       0x418
35838 +#define HPRT0          0x440
35839 +
35840 +/* HC_regs start from an offset of 0x500 */
35841 +#define HC_START       0x500
35842 +#define HC_OFFSET      0x020
35843 +
35844 +#define HC_DMA         0x514
35845 +
35846 +#define HCCHAR         0x00
35847 +#define HCSPLT         0x04
35848 +#define HCINT          0x08
35849 +#define HCINTMSK       0x0C
35850 +#define HCTSIZ         0x10
35851 +
35852 +#define ISOC_XACTPOS_ALL       0b11
35853 +#define ISOC_XACTPOS_BEGIN     0b10
35854 +#define ISOC_XACTPOS_MID       0b00
35855 +#define ISOC_XACTPOS_END       0b01
35856 +
35857 +#define DWC_PID_DATA2  0b01
35858 +#define DWC_PID_MDATA  0b11
35859 +#define DWC_PID_DATA1  0b10
35860 +#define DWC_PID_DATA0  0b00
35861 +
35862 +typedef struct {
35863 +       volatile void* base;
35864 +       volatile void* ctrl;
35865 +       volatile void* outdda;
35866 +       volatile void* outddb;
35867 +       volatile void* intstat;
35868 +} mphi_regs_t;
35869 +
35870 +enum fiq_debug_level {
35871 +       FIQDBG_SCHED = (1 << 0),
35872 +       FIQDBG_INT   = (1 << 1),
35873 +       FIQDBG_ERR   = (1 << 2),
35874 +       FIQDBG_PORTHUB = (1 << 3),
35875 +};
35876 +
35877 +typedef struct {
35878 +       union {
35879 +               uint32_t slock;
35880 +               struct _tickets {
35881 +                       uint16_t owner;
35882 +                       uint16_t next;
35883 +               } tickets;
35884 +       };
35885 +} fiq_lock_t;
35886 +
35887 +struct fiq_state;
35888 +
35889 +extern void _fiq_print (enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...);
35890 +#if 0
35891 +#define fiq_print _fiq_print
35892 +#else
35893 +#define fiq_print(x, y, ...)
35894 +#endif
35895 +
35896 +extern bool fiq_enable, fiq_fsm_enable;
35897 +extern ushort nak_holdoff;
35898 +
35899 +/**
35900 + * enum fiq_fsm_state - The FIQ FSM states.
35901 + *
35902 + * This is the "core" of the FIQ FSM. Broadly, the FSM states follow the
35903 + * USB2.0 specification for host responses to various transaction states.
35904 + * There are modifications to this host state machine because of a variety of
35905 + * quirks and limitations in the dwc_otg hardware.
35906 + *
35907 + * The fsm state is also used to communicate back to the driver on completion of
35908 + * a split transaction. The end states are used in conjunction with the interrupts
35909 + * raised by the final transaction.
35910 + */
35911 +enum fiq_fsm_state {
35912 +       /* FIQ isn't enabled for this host channel */
35913 +       FIQ_PASSTHROUGH = 0,
35914 +       /* For the first interrupt received for this channel,
35915 +        * the FIQ has to ack any interrupts indicating success. */
35916 +       FIQ_PASSTHROUGH_ERRORSTATE = 31,
35917 +       /* Nonperiodic state groups */
35918 +       FIQ_NP_SSPLIT_STARTED = 1,
35919 +       FIQ_NP_SSPLIT_RETRY = 2,
35920 +       FIQ_NP_OUT_CSPLIT_RETRY = 3,
35921 +       FIQ_NP_IN_CSPLIT_RETRY = 4,
35922 +       FIQ_NP_SPLIT_DONE = 5,
35923 +       FIQ_NP_SPLIT_LS_ABORTED = 6,
35924 +       /* This differentiates a HS transaction error from a LS one
35925 +        * (handling the hub state is different) */
35926 +       FIQ_NP_SPLIT_HS_ABORTED = 7,
35927 +
35928 +       /* Periodic state groups */
35929 +       /* Periodic transactions are either started directly by the IRQ handler
35930 +        * or deferred if the TT is already in use.
35931 +        */
35932 +       FIQ_PER_SSPLIT_QUEUED = 8,
35933 +       FIQ_PER_SSPLIT_STARTED = 9,
35934 +       FIQ_PER_SSPLIT_LAST = 10,
35935 +
35936 +
35937 +       FIQ_PER_ISO_OUT_PENDING = 11,
35938 +       FIQ_PER_ISO_OUT_ACTIVE = 12,
35939 +       FIQ_PER_ISO_OUT_LAST = 13,
35940 +       FIQ_PER_ISO_OUT_DONE = 27,
35941 +
35942 +       FIQ_PER_CSPLIT_WAIT = 14,
35943 +       FIQ_PER_CSPLIT_NYET1 = 15,
35944 +       FIQ_PER_CSPLIT_BROKEN_NYET1 = 28,
35945 +       FIQ_PER_CSPLIT_NYET_FAFF = 29,
35946 +       /* For multiple CSPLITs (large isoc IN, or delayed interrupt) */
35947 +       FIQ_PER_CSPLIT_POLL = 16,
35948 +       /* The last CSPLIT for a transaction has been issued, differentiates
35949 +        * for the state machine to queue the next packet.
35950 +        */
35951 +       FIQ_PER_CSPLIT_LAST = 17,
35952 +
35953 +       FIQ_PER_SPLIT_DONE = 18,
35954 +       FIQ_PER_SPLIT_LS_ABORTED = 19,
35955 +       FIQ_PER_SPLIT_HS_ABORTED = 20,
35956 +       FIQ_PER_SPLIT_NYET_ABORTED = 21,
35957 +       /* Frame rollover has occurred without the transaction finishing. */
35958 +       FIQ_PER_SPLIT_TIMEOUT = 22,
35959 +
35960 +       /* FIQ-accelerated HS Isochronous state groups */
35961 +       FIQ_HS_ISOC_TURBO = 23,
35962 +       /* For interval > 1, SOF wakes up the isochronous FSM */
35963 +       FIQ_HS_ISOC_SLEEPING = 24,
35964 +       FIQ_HS_ISOC_DONE = 25,
35965 +       FIQ_HS_ISOC_ABORTED = 26,
35966 +       FIQ_DEQUEUE_ISSUED = 30,
35967 +       FIQ_TEST = 32,
35968 +};
35969 +
35970 +struct fiq_stack {
35971 +       int magic1;
35972 +       uint8_t stack[2048];
35973 +       int magic2;
35974 +};
35975 +
35976 +
35977 +/**
35978 + * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel)
35979 + * @index:     Number of slots reported used for IN transactions / number of slots
35980 + *                     transmitted for an OUT transaction
35981 + * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused)
35982 + *
35983 + * Split transaction transfers can have variable length depending on other bus
35984 + * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore
35985 + * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers
35986 + * can happen per-frame.
35987 + */
35988 +struct fiq_dma_info {
35989 +       u8 index;
35990 +       u8 slot_len[6];
35991 +};
35992 +
35993 +struct __attribute__((packed)) fiq_split_dma_slot {
35994 +       u8 buf[188];
35995 +};
35996 +
35997 +struct fiq_dma_channel {
35998 +       struct __attribute__((packed)) fiq_split_dma_slot index[6];
35999 +};
36000 +
36001 +struct fiq_dma_blob {
36002 +       struct __attribute__((packed)) fiq_dma_channel channel[0];
36003 +};
36004 +
36005 +/**
36006 + * struct fiq_hs_isoc_info - USB2.0 isochronous data
36007 + * @iso_frame: Pointer to the array of OTG URB iso_frame_descs.
36008 + * @nrframes:  Total length of iso_frame_desc array
36009 + * @index:     Current index (FIQ-maintained)
36010 + * @stride:    Interval in uframes between HS isoc transactions
36011 + */
36012 +struct fiq_hs_isoc_info {
36013 +       struct dwc_otg_hcd_iso_packet_desc *iso_desc;
36014 +       unsigned int nrframes;
36015 +       unsigned int index;
36016 +       unsigned int stride;
36017 +};
36018 +
36019 +/**
36020 + * struct fiq_channel_state - FIQ state machine storage
36021 + * @fsm:       Current state of the channel as understood by the FIQ
36022 + * @nr_errors: Number of transaction errors on this split-transaction
36023 + * @hub_addr:   SSPLIT/CSPLIT destination hub
36024 + * @port_addr:  SSPLIT/CSPLIT destination port - always 1 if single TT hub
36025 + * @nrpackets:  For isoc OUT, the number of split-OUT packets to transmit. For
36026 + *             split-IN, number of CSPLIT data packets that were received.
36027 + * @hcchar_copy:
36028 + * @hcsplt_copy:
36029 + * @hcintmsk_copy:
36030 + * @hctsiz_copy:       Copies of the host channel registers.
36031 + *                     For use as scratch, or for returning state.
36032 + *
36033 + * The fiq_channel_state is state storage between interrupts for a host channel. The
36034 + * FSM state is stored here. Members of this structure must only be set up by the
36035 + * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ
36036 + * has updated the state to either a COMPLETE state group or ABORT state group.
36037 + */
36038 +
36039 +struct fiq_channel_state {
36040 +       enum fiq_fsm_state fsm;
36041 +       unsigned int nr_errors;
36042 +       unsigned int hub_addr;
36043 +       unsigned int port_addr;
36044 +       /* Hardware bug workaround: sometimes channel halt interrupts are
36045 +        * delayed until the next SOF. Keep track of when we expected to get interrupted. */
36046 +       unsigned int expected_uframe;
36047 +       /* number of uframes remaining (for interval > 1 HS isoc transfers) before next transfer */
36048 +       unsigned int uframe_sleeps;
36049 +       /* in/out for communicating number of dma buffers used, or number of ISOC to do */
36050 +       unsigned int nrpackets;
36051 +       struct fiq_dma_info dma_info;
36052 +       struct fiq_hs_isoc_info hs_isoc_info;
36053 +       /* Copies of HC registers - in/out communication from/to IRQ handler
36054 +        * and for ease of channel setup. A bit of mungeing is performed - for
36055 +        * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint.
36056 +        */
36057 +       hcchar_data_t hcchar_copy;
36058 +       hcsplt_data_t hcsplt_copy;
36059 +       hcint_data_t hcint_copy;
36060 +       hcintmsk_data_t hcintmsk_copy;
36061 +       hctsiz_data_t hctsiz_copy;
36062 +       hcdma_data_t hcdma_copy;
36063 +};
36064 +
36065 +/**
36066 + * struct fiq_state - top-level FIQ state machine storage
36067 + * @mphi_regs:         virtual address of the MPHI peripheral register file
36068 + * @dwc_regs_base:     virtual address of the base of the DWC core register file
36069 + * @dma_base:          physical address for the base of the DMA bounce buffers
36070 + * @dummy_send:                Scratch area for sending a fake message to the MPHI peripheral
36071 + * @gintmsk_saved:     Top-level mask of interrupts that the FIQ has not handled.
36072 + *                     Used for determining which interrupts fired to set off the IRQ handler.
36073 + * @haintmsk_saved:    Mask of interrupts from host channels that the FIQ did not handle internally.
36074 + * @np_count:          Non-periodic transactions in the active queue
36075 + * @np_sent:           Count of non-periodic transactions that have completed
36076 + * @next_sched_frame:  For periodic transactions handled by the driver's SOF-driven queuing mechanism,
36077 + *                     this is the next frame on which a SOF interrupt is required. Used to hold off
36078 + *                     passing SOF through to the driver until necessary.
36079 + * @channel[n]:                Per-channel FIQ state. Allocated during init depending on the number of host
36080 + *                     channels configured into the core logic.
36081 + *
36082 + * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub.
36083 + * It contains top-level state information.
36084 + */
36085 +struct fiq_state {
36086 +       fiq_lock_t lock;
36087 +       mphi_regs_t mphi_regs;
36088 +       void *dwc_regs_base;
36089 +       dma_addr_t dma_base;
36090 +       struct fiq_dma_blob *fiq_dmab;
36091 +       void *dummy_send;
36092 +       gintmsk_data_t gintmsk_saved;
36093 +       haintmsk_data_t haintmsk_saved;
36094 +       int mphi_int_count;
36095 +       unsigned int fiq_done;
36096 +       unsigned int kick_np_queues;
36097 +       unsigned int next_sched_frame;
36098 +#ifdef FIQ_DEBUG
36099 +       char * buffer;
36100 +       unsigned int bufsiz;
36101 +#endif
36102 +       struct fiq_channel_state channel[0];
36103 +};
36104 +
36105 +extern void fiq_fsm_spin_lock(fiq_lock_t *lock);
36106 +
36107 +extern void fiq_fsm_spin_unlock(fiq_lock_t *lock);
36108 +
36109 +extern int fiq_fsm_too_late(struct fiq_state *st, int n);
36110 +
36111 +extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n);
36112 +
36113 +extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels);
36114 +
36115 +extern void dwc_otg_fiq_nop(struct fiq_state *state);
36116 +
36117 +#endif /* DWC_OTG_FIQ_FSM_H_ */
36118 --- /dev/null
36119 +++ b/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S
36120 @@ -0,0 +1,80 @@
36121 +/*
36122 + * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ
36123 + *
36124 + * Copyright (c) 2013 Raspberry Pi Foundation
36125 + *
36126 + * Author: Jonathan Bell <jonathan@raspberrypi.org>
36127 + * All rights reserved.
36128 + *
36129 + * Redistribution and use in source and binary forms, with or without
36130 + * modification, are permitted provided that the following conditions are met:
36131 + *     * Redistributions of source code must retain the above copyright
36132 + *       notice, this list of conditions and the following disclaimer.
36133 + *     * Redistributions in binary form must reproduce the above copyright
36134 + *       notice, this list of conditions and the following disclaimer in the
36135 + *       documentation and/or other materials provided with the distribution.
36136 + *     * Neither the name of Raspberry Pi nor the
36137 + *       names of its contributors may be used to endorse or promote products
36138 + *       derived from this software without specific prior written permission.
36139 + *
36140 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
36141 + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36142 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36143 + * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
36144 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36145 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36146 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36147 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36148 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36149 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36150 + */
36151 +
36152 +
36153 +#include <asm/assembler.h>
36154 +#include <linux/linkage.h>
36155 +
36156 +
36157 +.text
36158 +
36159 +.global _dwc_otg_fiq_stub_end;
36160 +
36161 +/**
36162 +  * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow
36163 +  * a C-style function call with arguments from the FIQ banked registers.
36164 +  * r0 = &hcd->fiq_state
36165 +  * r1 = &hcd->num_channels
36166 +  * r2 = &hcd->dma_buffers
36167 +  * Tramples: r0, r1, r2, r4, fp, ip
36168 +  */
36169 +
36170 +ENTRY(_dwc_otg_fiq_stub)
36171 +       /* Stash unbanked regs - SP will have been set up for us */
36172 +       mov ip, sp;
36173 +       stmdb sp!, {r0-r12, lr};
36174 +#ifdef FIQ_DEBUG
36175 +       // Cycle profiling - read cycle counter at start
36176 +       mrc p15, 0, r5, c15, c12, 1;
36177 +#endif
36178 +       /* r11 = fp, don't trample it */
36179 +       mov r4, fp;
36180 +       /* set EABI frame size */
36181 +       sub fp, ip, #512;
36182 +
36183 +       /* for fiq NOP mode - just need state */
36184 +       mov r0, r8;
36185 +       /* r9 = num_channels */
36186 +       mov r1, r9;
36187 +       /* r10 = struct *dma_bufs */
36188 +//     mov r2, r10;
36189 +
36190 +       /* r4 = &fiq_c_function */
36191 +       blx r4;
36192 +#ifdef FIQ_DEBUG
36193 +       mrc p15, 0, r4, c15, c12, 1;
36194 +       subs r5, r5, r4;
36195 +       // r5 is now the cycle count time for executing the FIQ. Store it somewhere?
36196 +#endif
36197 +       ldmia sp!, {r0-r12, lr};
36198 +       subs pc, lr, #4;
36199 +_dwc_otg_fiq_stub_end:
36200 +END(_dwc_otg_fiq_stub)
36201 --- /dev/null
36202 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
36203 @@ -0,0 +1,4257 @@
36204 +
36205 +/* ==========================================================================
36206 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
36207 + * $Revision: #104 $
36208 + * $Date: 2011/10/24 $
36209 + * $Change: 1871159 $
36210 + *
36211 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
36212 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
36213 + * otherwise expressly agreed to in writing between Synopsys and you.
36214 + *
36215 + * The Software IS NOT an item of Licensed Software or Licensed Product under
36216 + * any End User Software License Agreement or Agreement for Licensed Product
36217 + * with Synopsys or any supplement thereto. You are permitted to use and
36218 + * redistribute this Software in source and binary forms, with or without
36219 + * modification, provided that redistributions of source code must retain this
36220 + * notice. You may not view, use, disclose, copy or distribute this file or
36221 + * any information contained herein except pursuant to this license grant from
36222 + * Synopsys. If you do not agree with this notice, including the disclaimer
36223 + * below, then you are not authorized to use the Software.
36224 + *
36225 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
36226 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36227 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36228 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
36229 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36230 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36231 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36232 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36233 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36234 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
36235 + * DAMAGE.
36236 + * ========================================================================== */
36237 +#ifndef DWC_DEVICE_ONLY
36238 +
36239 +/** @file
36240 + * This file implements HCD Core. All code in this file is portable and doesn't
36241 + * use any OS specific functions.
36242 + * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
36243 + * header file.
36244 + */
36245 +
36246 +#include <linux/usb.h>
36247 +#include <linux/usb/hcd.h>
36248 +
36249 +#include "dwc_otg_hcd.h"
36250 +#include "dwc_otg_regs.h"
36251 +#include "dwc_otg_fiq_fsm.h"
36252 +
36253 +extern bool microframe_schedule;
36254 +extern uint16_t fiq_fsm_mask, nak_holdoff;
36255 +
36256 +//#define DEBUG_HOST_CHANNELS
36257 +#ifdef DEBUG_HOST_CHANNELS
36258 +static int last_sel_trans_num_per_scheduled = 0;
36259 +static int last_sel_trans_num_nonper_scheduled = 0;
36260 +static int last_sel_trans_num_avail_hc_at_start = 0;
36261 +static int last_sel_trans_num_avail_hc_at_end = 0;
36262 +#endif /* DEBUG_HOST_CHANNELS */
36263 +
36264 +
36265 +dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
36266 +{
36267 +       return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
36268 +}
36269 +
36270 +/**
36271 + * Connection timeout function.  An OTG host is required to display a
36272 + * message if the device does not connect within 10 seconds.
36273 + */
36274 +void dwc_otg_hcd_connect_timeout(void *ptr)
36275 +{
36276 +       DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
36277 +       DWC_PRINTF("Connect Timeout\n");
36278 +       __DWC_ERROR("Device Not Connected/Responding\n");
36279 +}
36280 +
36281 +#if defined(DEBUG)
36282 +static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
36283 +{
36284 +       if (qh->channel != NULL) {
36285 +               dwc_hc_t *hc = qh->channel;
36286 +               dwc_list_link_t *item;
36287 +               dwc_otg_qh_t *qh_item;
36288 +               int num_channels = hcd->core_if->core_params->host_channels;
36289 +               int i;
36290 +
36291 +               dwc_otg_hc_regs_t *hc_regs;
36292 +               hcchar_data_t hcchar;
36293 +               hcsplt_data_t hcsplt;
36294 +               hctsiz_data_t hctsiz;
36295 +               uint32_t hcdma;
36296 +
36297 +               hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
36298 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
36299 +               hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
36300 +               hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
36301 +               hcdma = DWC_READ_REG32(&hc_regs->hcdma);
36302 +
36303 +               DWC_PRINTF("  Assigned to channel %p:\n", hc);
36304 +               DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
36305 +                          hcsplt.d32);
36306 +               DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
36307 +                          hcdma);
36308 +               DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
36309 +                          hc->dev_addr, hc->ep_num, hc->ep_is_in);
36310 +               DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
36311 +               DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
36312 +               DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
36313 +               DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
36314 +               DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
36315 +               DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
36316 +               DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
36317 +               DWC_PRINTF("    qh: %p\n", hc->qh);
36318 +               DWC_PRINTF("  NP inactive sched:\n");
36319 +               DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
36320 +                       qh_item =
36321 +                           DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
36322 +                       DWC_PRINTF("    %p\n", qh_item);
36323 +               }
36324 +               DWC_PRINTF("  NP active sched:\n");
36325 +               DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
36326 +                       qh_item =
36327 +                           DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
36328 +                       DWC_PRINTF("    %p\n", qh_item);
36329 +               }
36330 +               DWC_PRINTF("  Channels: \n");
36331 +               for (i = 0; i < num_channels; i++) {
36332 +                       dwc_hc_t *hc = hcd->hc_ptr_array[i];
36333 +                       DWC_PRINTF("    %2d: %p\n", i, hc);
36334 +               }
36335 +       }
36336 +}
36337 +#else
36338 +#define dump_channel_info(hcd, qh)
36339 +#endif /* DEBUG */
36340 +
36341 +/**
36342 + * Work queue function for starting the HCD when A-Cable is connected.
36343 + * The hcd_start() must be called in a process context.
36344 + */
36345 +static void hcd_start_func(void *_vp)
36346 +{
36347 +       dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
36348 +
36349 +       DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
36350 +       if (hcd) {
36351 +               hcd->fops->start(hcd);
36352 +       }
36353 +}
36354 +
36355 +static void del_xfer_timers(dwc_otg_hcd_t * hcd)
36356 +{
36357 +#ifdef DEBUG
36358 +       int i;
36359 +       int num_channels = hcd->core_if->core_params->host_channels;
36360 +       for (i = 0; i < num_channels; i++) {
36361 +               DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
36362 +       }
36363 +#endif
36364 +}
36365 +
36366 +static void del_timers(dwc_otg_hcd_t * hcd)
36367 +{
36368 +       del_xfer_timers(hcd);
36369 +       DWC_TIMER_CANCEL(hcd->conn_timer);
36370 +}
36371 +
36372 +/**
36373 + * Processes all the URBs in a single list of QHs. Completes them with
36374 + * -ESHUTDOWN and frees the QTD.
36375 + */
36376 +static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
36377 +{
36378 +       dwc_list_link_t *qh_item, *qh_tmp;
36379 +       dwc_otg_qh_t *qh;
36380 +       dwc_otg_qtd_t *qtd, *qtd_tmp;
36381 +
36382 +       DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) {
36383 +               qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
36384 +               DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
36385 +                                        &qh->qtd_list, qtd_list_entry) {
36386 +                       qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
36387 +                       if (qtd->urb != NULL) {
36388 +                               hcd->fops->complete(hcd, qtd->urb->priv,
36389 +                                                   qtd->urb, -DWC_E_SHUTDOWN);
36390 +                               dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
36391 +                       }
36392 +
36393 +               }
36394 +               if(qh->channel) {
36395 +                       /* Using hcchar.chen == 1 is not a reliable test.
36396 +                        * It is possible that the channel has already halted
36397 +                        * but not yet been through the IRQ handler.
36398 +                        */
36399 +                       dwc_otg_hc_halt(hcd->core_if, qh->channel,
36400 +                               DWC_OTG_HC_XFER_URB_DEQUEUE);
36401 +                       if(microframe_schedule)
36402 +                               hcd->available_host_channels++;
36403 +                       qh->channel = NULL;
36404 +               }
36405 +               dwc_otg_hcd_qh_remove(hcd, qh);
36406 +       }
36407 +}
36408 +
36409 +/**
36410 + * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic
36411 + * and periodic schedules. The QTD associated with each URB is removed from
36412 + * the schedule and freed. This function may be called when a disconnect is
36413 + * detected or when the HCD is being stopped.
36414 + */
36415 +static void kill_all_urbs(dwc_otg_hcd_t * hcd)
36416 +{
36417 +       kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
36418 +       kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
36419 +       kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
36420 +       kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
36421 +       kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
36422 +       kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
36423 +}
36424 +
36425 +/**
36426 + * Start the connection timer.  An OTG host is required to display a
36427 + * message if the device does not connect within 10 seconds.  The
36428 + * timer is deleted if a port connect interrupt occurs before the
36429 + * timer expires.
36430 + */
36431 +static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
36432 +{
36433 +       DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
36434 +}
36435 +
36436 +/**
36437 + * HCD Callback function for disconnect of the HCD.
36438 + *
36439 + * @param p void pointer to the <code>struct usb_hcd</code>
36440 + */
36441 +static int32_t dwc_otg_hcd_session_start_cb(void *p)
36442 +{
36443 +       dwc_otg_hcd_t *dwc_otg_hcd;
36444 +       DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
36445 +       dwc_otg_hcd = p;
36446 +       dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
36447 +       return 1;
36448 +}
36449 +
36450 +/**
36451 + * HCD Callback function for starting the HCD when A-Cable is
36452 + * connected.
36453 + *
36454 + * @param p void pointer to the <code>struct usb_hcd</code>
36455 + */
36456 +static int32_t dwc_otg_hcd_start_cb(void *p)
36457 +{
36458 +       dwc_otg_hcd_t *dwc_otg_hcd = p;
36459 +       dwc_otg_core_if_t *core_if;
36460 +       hprt0_data_t hprt0;
36461 +
36462 +       core_if = dwc_otg_hcd->core_if;
36463 +
36464 +       if (core_if->op_state == B_HOST) {
36465 +               /*
36466 +                * Reset the port.  During a HNP mode switch the reset
36467 +                * needs to occur within 1ms and have a duration of at
36468 +                * least 50ms.
36469 +                */
36470 +               hprt0.d32 = dwc_otg_read_hprt0(core_if);
36471 +               hprt0.b.prtrst = 1;
36472 +               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36473 +       }
36474 +       DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
36475 +                                  hcd_start_func, dwc_otg_hcd, 50,
36476 +                                  "start hcd");
36477 +
36478 +       return 1;
36479 +}
36480 +
36481 +/**
36482 + * HCD Callback function for disconnect of the HCD.
36483 + *
36484 + * @param p void pointer to the <code>struct usb_hcd</code>
36485 + */
36486 +static int32_t dwc_otg_hcd_disconnect_cb(void *p)
36487 +{
36488 +       gintsts_data_t intr;
36489 +       dwc_otg_hcd_t *dwc_otg_hcd = p;
36490 +
36491 +       /*
36492 +        * Set status flags for the hub driver.
36493 +        */
36494 +       dwc_otg_hcd->flags.b.port_connect_status_change = 1;
36495 +       dwc_otg_hcd->flags.b.port_connect_status = 0;
36496 +       if(fiq_enable)
36497 +               local_fiq_disable();
36498 +       /*
36499 +        * Shutdown any transfers in process by clearing the Tx FIFO Empty
36500 +        * interrupt mask and status bits and disabling subsequent host
36501 +        * channel interrupts.
36502 +        */
36503 +       intr.d32 = 0;
36504 +       intr.b.nptxfempty = 1;
36505 +       intr.b.ptxfempty = 1;
36506 +       intr.b.hcintr = 1;
36507 +       DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
36508 +                        intr.d32, 0);
36509 +       DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
36510 +                        intr.d32, 0);
36511 +
36512 +       del_timers(dwc_otg_hcd);
36513 +
36514 +       /*
36515 +        * Turn off the vbus power only if the core has transitioned to device
36516 +        * mode. If still in host mode, need to keep power on to detect a
36517 +        * reconnection.
36518 +        */
36519 +       if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
36520 +               if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
36521 +                       hprt0_data_t hprt0 = {.d32 = 0 };
36522 +                       DWC_PRINTF("Disconnect: PortPower off\n");
36523 +                       hprt0.b.prtpwr = 0;
36524 +                       DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
36525 +                                       hprt0.d32);
36526 +               }
36527 +
36528 +               dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
36529 +       }
36530 +
36531 +       /* Respond with an error status to all URBs in the schedule. */
36532 +       kill_all_urbs(dwc_otg_hcd);
36533 +
36534 +       if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
36535 +               /* Clean up any host channels that were in use. */
36536 +               int num_channels;
36537 +               int i;
36538 +               dwc_hc_t *channel;
36539 +               dwc_otg_hc_regs_t *hc_regs;
36540 +               hcchar_data_t hcchar;
36541 +
36542 +               num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
36543 +
36544 +               if (!dwc_otg_hcd->core_if->dma_enable) {
36545 +                       /* Flush out any channel requests in slave mode. */
36546 +                       for (i = 0; i < num_channels; i++) {
36547 +                               channel = dwc_otg_hcd->hc_ptr_array[i];
36548 +                               if (DWC_CIRCLEQ_EMPTY_ENTRY
36549 +                                   (channel, hc_list_entry)) {
36550 +                                       hc_regs =
36551 +                                           dwc_otg_hcd->core_if->
36552 +                                           host_if->hc_regs[i];
36553 +                                       hcchar.d32 =
36554 +                                           DWC_READ_REG32(&hc_regs->hcchar);
36555 +                                       if (hcchar.b.chen) {
36556 +                                               hcchar.b.chen = 0;
36557 +                                               hcchar.b.chdis = 1;
36558 +                                               hcchar.b.epdir = 0;
36559 +                                               DWC_WRITE_REG32
36560 +                                                   (&hc_regs->hcchar,
36561 +                                                    hcchar.d32);
36562 +                                       }
36563 +                               }
36564 +                       }
36565 +               }
36566 +
36567 +               for (i = 0; i < num_channels; i++) {
36568 +                       channel = dwc_otg_hcd->hc_ptr_array[i];
36569 +                       if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
36570 +                               hc_regs =
36571 +                                   dwc_otg_hcd->core_if->host_if->hc_regs[i];
36572 +                               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
36573 +                               if (hcchar.b.chen) {
36574 +                                       /* Halt the channel. */
36575 +                                       hcchar.b.chdis = 1;
36576 +                                       DWC_WRITE_REG32(&hc_regs->hcchar,
36577 +                                                       hcchar.d32);
36578 +                               }
36579 +
36580 +                               dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
36581 +                                                  channel);
36582 +                               DWC_CIRCLEQ_INSERT_TAIL
36583 +                                   (&dwc_otg_hcd->free_hc_list, channel,
36584 +                                    hc_list_entry);
36585 +                               /*
36586 +                                * Added for Descriptor DMA to prevent channel double cleanup
36587 +                                * in release_channel_ddma(). Which called from ep_disable
36588 +                                * when device disconnect.
36589 +                                */
36590 +                               channel->qh = NULL;
36591 +                       }
36592 +               }
36593 +               if(fiq_fsm_enable) {
36594 +                       for(i=0; i < 128; i++) {
36595 +                               dwc_otg_hcd->hub_port[i] = 0;
36596 +                       }
36597 +               }
36598 +
36599 +       }
36600 +
36601 +       if(fiq_enable)
36602 +               local_fiq_enable();
36603 +
36604 +       if (dwc_otg_hcd->fops->disconnect) {
36605 +               dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
36606 +       }
36607 +
36608 +       return 1;
36609 +}
36610 +
36611 +/**
36612 + * HCD Callback function for stopping the HCD.
36613 + *
36614 + * @param p void pointer to the <code>struct usb_hcd</code>
36615 + */
36616 +static int32_t dwc_otg_hcd_stop_cb(void *p)
36617 +{
36618 +       dwc_otg_hcd_t *dwc_otg_hcd = p;
36619 +
36620 +       DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
36621 +       dwc_otg_hcd_stop(dwc_otg_hcd);
36622 +       return 1;
36623 +}
36624 +
36625 +#ifdef CONFIG_USB_DWC_OTG_LPM
36626 +/**
36627 + * HCD Callback function for sleep of HCD.
36628 + *
36629 + * @param p void pointer to the <code>struct usb_hcd</code>
36630 + */
36631 +static int dwc_otg_hcd_sleep_cb(void *p)
36632 +{
36633 +       dwc_otg_hcd_t *hcd = p;
36634 +
36635 +       dwc_otg_hcd_free_hc_from_lpm(hcd);
36636 +
36637 +       return 0;
36638 +}
36639 +#endif
36640 +
36641 +
36642 +/**
36643 + * HCD Callback function for Remote Wakeup.
36644 + *
36645 + * @param p void pointer to the <code>struct usb_hcd</code>
36646 + */
36647 +static int dwc_otg_hcd_rem_wakeup_cb(void *p)
36648 +{
36649 +       dwc_otg_hcd_t *hcd = p;
36650 +
36651 +       if (hcd->core_if->lx_state == DWC_OTG_L2) {
36652 +               hcd->flags.b.port_suspend_change = 1;
36653 +       }
36654 +#ifdef CONFIG_USB_DWC_OTG_LPM
36655 +       else {
36656 +               hcd->flags.b.port_l1_change = 1;
36657 +       }
36658 +#endif
36659 +       return 0;
36660 +}
36661 +
36662 +/**
36663 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
36664 + * stopped.
36665 + */
36666 +void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
36667 +{
36668 +       hprt0_data_t hprt0 = {.d32 = 0 };
36669 +
36670 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
36671 +
36672 +       /*
36673 +        * The root hub should be disconnected before this function is called.
36674 +        * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
36675 +        * and the QH lists (via ..._hcd_endpoint_disable).
36676 +        */
36677 +
36678 +       /* Turn off all host-specific interrupts. */
36679 +       dwc_otg_disable_host_interrupts(hcd->core_if);
36680 +
36681 +       /* Turn off the vbus power */
36682 +       DWC_PRINTF("PortPower off\n");
36683 +       hprt0.b.prtpwr = 0;
36684 +       DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
36685 +       dwc_mdelay(1);
36686 +}
36687 +
36688 +int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
36689 +                           dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
36690 +                           int atomic_alloc)
36691 +{
36692 +       int retval = 0;
36693 +       uint8_t needs_scheduling = 0;
36694 +       dwc_otg_transaction_type_e tr_type;
36695 +       dwc_otg_qtd_t *qtd;
36696 +       gintmsk_data_t intr_mask = {.d32 = 0 };
36697 +       hprt0_data_t hprt0 = { .d32 = 0 };
36698 +
36699 +#ifdef DEBUG /* integrity checks (Broadcom) */
36700 +       if (NULL == hcd->core_if) {
36701 +               DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n");
36702 +               /* No longer connected. */
36703 +               return -DWC_E_INVALID;
36704 +       }
36705 +#endif
36706 +       if (!hcd->flags.b.port_connect_status) {
36707 +               /* No longer connected. */
36708 +               DWC_ERROR("Not connected\n");
36709 +               return -DWC_E_NO_DEVICE;
36710 +       }
36711 +
36712 +       /* Some core configurations cannot support LS traffic on a FS root port */
36713 +       if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) &&
36714 +               (hcd->core_if->hwcfg2.b.fs_phy_type == 1) &&
36715 +               (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) {
36716 +                       hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
36717 +                       if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
36718 +                               return -DWC_E_NO_DEVICE;
36719 +                       }
36720 +       }
36721 +
36722 +       qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
36723 +       if (qtd == NULL) {
36724 +               DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
36725 +               return -DWC_E_NO_MEMORY;
36726 +       }
36727 +#ifdef DEBUG /* integrity checks (Broadcom) */
36728 +       if (qtd->urb == NULL) {
36729 +               DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n");
36730 +               return -DWC_E_NO_MEMORY;
36731 +       }
36732 +       if (qtd->urb->priv == NULL) {
36733 +               DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n");
36734 +               return -DWC_E_NO_MEMORY;
36735 +       }
36736 +#endif
36737 +       intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
36738 +       if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1;
36739 +       if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP))
36740 +               /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
36741 +               needs_scheduling = 0;
36742 +
36743 +       retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
36744 +            // creates a new queue in ep_handle if it doesn't exist already
36745 +       if (retval < 0) {
36746 +               DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
36747 +                         "Error status %d\n", retval);
36748 +               dwc_otg_hcd_qtd_free(qtd);
36749 +               return retval;
36750 +       }
36751 +
36752 +       if(needs_scheduling) {
36753 +               tr_type = dwc_otg_hcd_select_transactions(hcd);
36754 +               if (tr_type != DWC_OTG_TRANSACTION_NONE) {
36755 +                       dwc_otg_hcd_queue_transactions(hcd, tr_type);
36756 +               }
36757 +       }
36758 +       return retval;
36759 +}
36760 +
36761 +int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
36762 +                           dwc_otg_hcd_urb_t * dwc_otg_urb)
36763 +{
36764 +       dwc_otg_qh_t *qh;
36765 +       dwc_otg_qtd_t *urb_qtd;
36766 +       BUG_ON(!hcd);
36767 +       BUG_ON(!dwc_otg_urb);
36768 +
36769 +#ifdef DEBUG /* integrity checks (Broadcom) */
36770 +
36771 +       if (hcd == NULL) {
36772 +               DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n");
36773 +               return -DWC_E_INVALID;
36774 +       }
36775 +       if (dwc_otg_urb == NULL) {
36776 +               DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n");
36777 +               return -DWC_E_INVALID;
36778 +       }
36779 +       if (dwc_otg_urb->qtd == NULL) {
36780 +               DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n");
36781 +               return -DWC_E_INVALID;
36782 +       }
36783 +       urb_qtd = dwc_otg_urb->qtd;
36784 +       BUG_ON(!urb_qtd);
36785 +       if (urb_qtd->qh == NULL) {
36786 +               DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n");
36787 +               return -DWC_E_INVALID;
36788 +       }
36789 +#else
36790 +       urb_qtd = dwc_otg_urb->qtd;
36791 +       BUG_ON(!urb_qtd);
36792 +#endif
36793 +       qh = urb_qtd->qh;
36794 +       BUG_ON(!qh);
36795 +       if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
36796 +               if (urb_qtd->in_process) {
36797 +                       dump_channel_info(hcd, qh);
36798 +               }
36799 +       }
36800 +#ifdef DEBUG /* integrity checks (Broadcom) */
36801 +       if (hcd->core_if == NULL) {
36802 +               DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n");
36803 +               return -DWC_E_INVALID;
36804 +       }
36805 +#endif
36806 +       if (urb_qtd->in_process && qh->channel) {
36807 +               /* The QTD is in process (it has been assigned to a channel). */
36808 +               if (hcd->flags.b.port_connect_status) {
36809 +                       int n = qh->channel->hc_num;
36810 +                       /*
36811 +                        * If still connected (i.e. in host mode), halt the
36812 +                        * channel so it can be used for other transfers. If
36813 +                        * no longer connected, the host registers can't be
36814 +                        * written to halt the channel since the core is in
36815 +                        * device mode.
36816 +                        */
36817 +                       /* In FIQ FSM mode, we need to shut down carefully.
36818 +                        * The FIQ may attempt to restart a disabled channel */
36819 +                       if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) {
36820 +                               qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE;
36821 +                               qh->channel->halt_pending = 1;
36822 +                               hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED;
36823 +                       } else {
36824 +                               dwc_otg_hc_halt(hcd->core_if, qh->channel,
36825 +                                               DWC_OTG_HC_XFER_URB_DEQUEUE);
36826 +                       }
36827 +               }
36828 +       }
36829 +
36830 +       /*
36831 +        * Free the QTD and clean up the associated QH. Leave the QH in the
36832 +        * schedule if it has any remaining QTDs.
36833 +        */
36834 +
36835 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - "
36836 +                    "delete %sQueue handler\n",
36837 +                    hcd->core_if->dma_desc_enable?"DMA ":"");
36838 +       if (!hcd->core_if->dma_desc_enable) {
36839 +               uint8_t b = urb_qtd->in_process;
36840 +               dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
36841 +               if (b) {
36842 +                       dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
36843 +                       qh->channel = NULL;
36844 +               } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
36845 +                       dwc_otg_hcd_qh_remove(hcd, qh);
36846 +               }
36847 +       } else {
36848 +               dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
36849 +       }
36850 +       return 0;
36851 +}
36852 +
36853 +int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
36854 +                                int retry)
36855 +{
36856 +       dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
36857 +       int retval = 0;
36858 +       dwc_irqflags_t flags;
36859 +
36860 +       if (retry < 0) {
36861 +               retval = -DWC_E_INVALID;
36862 +               goto done;
36863 +       }
36864 +
36865 +       if (!qh) {
36866 +               retval = -DWC_E_INVALID;
36867 +               goto done;
36868 +       }
36869 +
36870 +       DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
36871 +
36872 +       while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
36873 +               DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
36874 +               retry--;
36875 +               dwc_msleep(5);
36876 +               DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
36877 +       }
36878 +
36879 +       dwc_otg_hcd_qh_remove(hcd, qh);
36880 +
36881 +       DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
36882 +       /*
36883 +        * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
36884 +        * and qh_free to prevent stack dump on DWC_DMA_FREE() with
36885 +        * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
36886 +        * and dwc_otg_hcd_frame_list_alloc().
36887 +        */
36888 +       dwc_otg_hcd_qh_free(hcd, qh);
36889 +
36890 +done:
36891 +       return retval;
36892 +}
36893 +
36894 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
36895 +int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
36896 +{
36897 +       int retval = 0;
36898 +       dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
36899 +       if (!qh)
36900 +               return -DWC_E_INVALID;
36901 +
36902 +       qh->data_toggle = DWC_OTG_HC_PID_DATA0;
36903 +       return retval;
36904 +}
36905 +#endif
36906 +
36907 +/**
36908 + * HCD Callback structure for handling mode switching.
36909 + */
36910 +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
36911 +       .start = dwc_otg_hcd_start_cb,
36912 +       .stop = dwc_otg_hcd_stop_cb,
36913 +       .disconnect = dwc_otg_hcd_disconnect_cb,
36914 +       .session_start = dwc_otg_hcd_session_start_cb,
36915 +       .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
36916 +#ifdef CONFIG_USB_DWC_OTG_LPM
36917 +       .sleep = dwc_otg_hcd_sleep_cb,
36918 +#endif
36919 +       .p = 0,
36920 +};
36921 +
36922 +/**
36923 + * Reset tasklet function
36924 + */
36925 +static void reset_tasklet_func(void *data)
36926 +{
36927 +       dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
36928 +       dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
36929 +       hprt0_data_t hprt0;
36930 +
36931 +       DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
36932 +
36933 +       hprt0.d32 = dwc_otg_read_hprt0(core_if);
36934 +       hprt0.b.prtrst = 1;
36935 +       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36936 +       dwc_mdelay(60);
36937 +
36938 +       hprt0.b.prtrst = 0;
36939 +       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
36940 +       dwc_otg_hcd->flags.b.port_reset_change = 1;
36941 +}
36942 +
36943 +static void completion_tasklet_func(void *ptr)
36944 +{
36945 +       dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr;
36946 +       struct urb *urb;
36947 +       urb_tq_entry_t *item;
36948 +       dwc_irqflags_t flags;
36949 +
36950 +       /* This could just be spin_lock_irq */
36951 +       DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
36952 +       while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) {
36953 +               item = DWC_TAILQ_FIRST(&hcd->completed_urb_list);
36954 +               urb = item->urb;
36955 +               DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item,
36956 +                               urb_tq_entries);
36957 +               DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
36958 +               DWC_FREE(item);
36959 +
36960 +               usb_hcd_giveback_urb(hcd->priv, urb, urb->status);
36961 +
36962 +
36963 +               DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
36964 +       }
36965 +       DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
36966 +       return;
36967 +}
36968 +
36969 +static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
36970 +{
36971 +       dwc_list_link_t *item;
36972 +       dwc_otg_qh_t *qh;
36973 +       dwc_irqflags_t flags;
36974 +
36975 +       if (!qh_list->next) {
36976 +               /* The list hasn't been initialized yet. */
36977 +               return;
36978 +       }
36979 +       /*
36980 +        * Hold spinlock here. Not needed in that case if bellow
36981 +        * function is being called from ISR
36982 +        */
36983 +       DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
36984 +       /* Ensure there are no QTDs or URBs left. */
36985 +       kill_urbs_in_qh_list(hcd, qh_list);
36986 +       DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
36987 +
36988 +       DWC_LIST_FOREACH(item, qh_list) {
36989 +               qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
36990 +               dwc_otg_hcd_qh_remove_and_free(hcd, qh);
36991 +       }
36992 +}
36993 +
36994 +/**
36995 + * Exit from Hibernation if Host did not detect SRP from connected SRP capable
36996 + * Device during SRP time by host power up.
36997 + */
36998 +void dwc_otg_hcd_power_up(void *ptr)
36999 +{
37000 +       gpwrdn_data_t gpwrdn = {.d32 = 0 };
37001 +       dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
37002 +
37003 +       DWC_PRINTF("%s called\n", __FUNCTION__);
37004 +
37005 +       if (!core_if->hibernation_suspend) {
37006 +               DWC_PRINTF("Already exited from Hibernation\n");
37007 +               return;
37008 +       }
37009 +
37010 +       /* Switch on the voltage to the core */
37011 +       gpwrdn.b.pwrdnswtch = 1;
37012 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37013 +       dwc_udelay(10);
37014 +
37015 +       /* Reset the core */
37016 +       gpwrdn.d32 = 0;
37017 +       gpwrdn.b.pwrdnrstn = 1;
37018 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37019 +       dwc_udelay(10);
37020 +
37021 +       /* Disable power clamps */
37022 +       gpwrdn.d32 = 0;
37023 +       gpwrdn.b.pwrdnclmp = 1;
37024 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37025 +
37026 +       /* Remove reset the core signal */
37027 +       gpwrdn.d32 = 0;
37028 +       gpwrdn.b.pwrdnrstn = 1;
37029 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
37030 +       dwc_udelay(10);
37031 +
37032 +       /* Disable PMU interrupt */
37033 +       gpwrdn.d32 = 0;
37034 +       gpwrdn.b.pmuintsel = 1;
37035 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37036 +
37037 +       core_if->hibernation_suspend = 0;
37038 +
37039 +       /* Disable PMU */
37040 +       gpwrdn.d32 = 0;
37041 +       gpwrdn.b.pmuactv = 1;
37042 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37043 +       dwc_udelay(10);
37044 +
37045 +       /* Enable VBUS */
37046 +       gpwrdn.d32 = 0;
37047 +       gpwrdn.b.dis_vbus = 1;
37048 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
37049 +
37050 +       core_if->op_state = A_HOST;
37051 +       dwc_otg_core_init(core_if);
37052 +       dwc_otg_enable_global_interrupts(core_if);
37053 +       cil_hcd_start(core_if);
37054 +}
37055 +
37056 +void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num)
37057 +{
37058 +       struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
37059 +       struct fiq_dma_blob *blob = hcd->fiq_dmab;
37060 +       int i;
37061 +
37062 +       st->fsm = FIQ_PASSTHROUGH;
37063 +       st->hcchar_copy.d32 = 0;
37064 +       st->hcsplt_copy.d32 = 0;
37065 +       st->hcint_copy.d32 = 0;
37066 +       st->hcintmsk_copy.d32 = 0;
37067 +       st->hctsiz_copy.d32 = 0;
37068 +       st->hcdma_copy.d32 = 0;
37069 +       st->nr_errors = 0;
37070 +       st->hub_addr = 0;
37071 +       st->port_addr = 0;
37072 +       st->expected_uframe = 0;
37073 +       st->nrpackets = 0;
37074 +       st->dma_info.index = 0;
37075 +       for (i = 0; i < 6; i++)
37076 +               st->dma_info.slot_len[i] = 255;
37077 +       st->hs_isoc_info.index = 0;
37078 +       st->hs_isoc_info.iso_desc = NULL;
37079 +       st->hs_isoc_info.nrframes = 0;
37080 +
37081 +       DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128);
37082 +}
37083 +
37084 +/**
37085 + * Frees secondary storage associated with the dwc_otg_hcd structure contained
37086 + * in the struct usb_hcd field.
37087 + */
37088 +static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
37089 +{
37090 +       int i;
37091 +
37092 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
37093 +
37094 +       del_timers(dwc_otg_hcd);
37095 +
37096 +       /* Free memory for QH/QTD lists */
37097 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
37098 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
37099 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
37100 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
37101 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
37102 +       qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
37103 +
37104 +       /* Free memory for the host channels. */
37105 +       for (i = 0; i < MAX_EPS_CHANNELS; i++) {
37106 +               dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
37107 +
37108 +#ifdef DEBUG
37109 +               if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
37110 +                       DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
37111 +               }
37112 +#endif
37113 +               if (hc != NULL) {
37114 +                       DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
37115 +                                   i, hc);
37116 +                       DWC_FREE(hc);
37117 +               }
37118 +       }
37119 +
37120 +       if (dwc_otg_hcd->core_if->dma_enable) {
37121 +               if (dwc_otg_hcd->status_buf_dma) {
37122 +                       DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
37123 +                                    dwc_otg_hcd->status_buf,
37124 +                                    dwc_otg_hcd->status_buf_dma);
37125 +               }
37126 +       } else if (dwc_otg_hcd->status_buf != NULL) {
37127 +               DWC_FREE(dwc_otg_hcd->status_buf);
37128 +       }
37129 +       DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock);
37130 +       DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
37131 +       /* Set core_if's lock pointer to NULL */
37132 +       dwc_otg_hcd->core_if->lock = NULL;
37133 +
37134 +       DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
37135 +       DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
37136 +       DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet);
37137 +       DWC_FREE(dwc_otg_hcd->fiq_state);
37138 +
37139 +#ifdef DWC_DEV_SRPCAP
37140 +       if (dwc_otg_hcd->core_if->power_down == 2 &&
37141 +           dwc_otg_hcd->core_if->pwron_timer) {
37142 +               DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
37143 +       }
37144 +#endif
37145 +       DWC_FREE(dwc_otg_hcd);
37146 +}
37147 +
37148 +int init_hcd_usecs(dwc_otg_hcd_t *_hcd);
37149 +
37150 +int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
37151 +{
37152 +       int retval = 0;
37153 +       int num_channels;
37154 +       int i;
37155 +       dwc_hc_t *channel;
37156 +
37157 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
37158 +       DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock);
37159 +       DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock);
37160 +#else
37161 +       hcd->lock = DWC_SPINLOCK_ALLOC();
37162 +       hcd->channel_lock = DWC_SPINLOCK_ALLOC();
37163 +#endif
37164 +        DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n",
37165 +                    hcd, core_if);
37166 +       if (!hcd->lock) {
37167 +               DWC_ERROR("Could not allocate lock for pcd");
37168 +               DWC_FREE(hcd);
37169 +               retval = -DWC_E_NO_MEMORY;
37170 +               goto out;
37171 +       }
37172 +       hcd->core_if = core_if;
37173 +
37174 +       /* Register the HCD CIL Callbacks */
37175 +       dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
37176 +                                          &hcd_cil_callbacks, hcd);
37177 +
37178 +       /* Initialize the non-periodic schedule. */
37179 +       DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
37180 +       DWC_LIST_INIT(&hcd->non_periodic_sched_active);
37181 +
37182 +       /* Initialize the periodic schedule. */
37183 +       DWC_LIST_INIT(&hcd->periodic_sched_inactive);
37184 +       DWC_LIST_INIT(&hcd->periodic_sched_ready);
37185 +       DWC_LIST_INIT(&hcd->periodic_sched_assigned);
37186 +       DWC_LIST_INIT(&hcd->periodic_sched_queued);
37187 +       DWC_TAILQ_INIT(&hcd->completed_urb_list);
37188 +       /*
37189 +        * Create a host channel descriptor for each host channel implemented
37190 +        * in the controller. Initialize the channel descriptor array.
37191 +        */
37192 +       DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
37193 +       num_channels = hcd->core_if->core_params->host_channels;
37194 +       DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
37195 +       for (i = 0; i < num_channels; i++) {
37196 +               channel = DWC_ALLOC(sizeof(dwc_hc_t));
37197 +               if (channel == NULL) {
37198 +                       retval = -DWC_E_NO_MEMORY;
37199 +                       DWC_ERROR("%s: host channel allocation failed\n",
37200 +                                 __func__);
37201 +                       dwc_otg_hcd_free(hcd);
37202 +                       goto out;
37203 +               }
37204 +               channel->hc_num = i;
37205 +               hcd->hc_ptr_array[i] = channel;
37206 +#ifdef DEBUG
37207 +               hcd->core_if->hc_xfer_timer[i] =
37208 +                   DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
37209 +                                   &hcd->core_if->hc_xfer_info[i]);
37210 +#endif
37211 +               DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
37212 +                           channel);
37213 +       }
37214 +
37215 +       if (fiq_enable) {
37216 +               hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels));
37217 +               if (!hcd->fiq_state) {
37218 +                       retval = -DWC_E_NO_MEMORY;
37219 +                       DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__);
37220 +                       dwc_otg_hcd_free(hcd);
37221 +                       goto out;
37222 +               }
37223 +               DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)));
37224 +
37225 +               for (i = 0; i < num_channels; i++) {
37226 +                       hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH;
37227 +               }
37228 +               hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16);
37229 +
37230 +               hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack));
37231 +               if (!hcd->fiq_stack) {
37232 +                       retval = -DWC_E_NO_MEMORY;
37233 +                       DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__);
37234 +                       dwc_otg_hcd_free(hcd);
37235 +                       goto out;
37236 +               }
37237 +               hcd->fiq_stack->magic1 = 0xDEADBEEF;
37238 +               hcd->fiq_stack->magic2 = 0xD00DFEED;
37239 +               hcd->fiq_state->gintmsk_saved.d32 = ~0;
37240 +               hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
37241 +
37242 +               /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools
37243 +                * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels)
37244 +                * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some
37245 +                * moderately readable array casts.
37246 +                */
37247 +               hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base);
37248 +               DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d",
37249 +                               (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base,
37250 +                               sizeof(struct fiq_dma_channel) * num_channels);
37251 +
37252 +               DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024);
37253 +
37254 +               /* pointer for debug in fiq_print */
37255 +               hcd->fiq_state->fiq_dmab = hcd->fiq_dmab;
37256 +               if (fiq_fsm_enable) {
37257 +                       int i;
37258 +                       for (i=0; i < hcd->core_if->core_params->host_channels; i++) {
37259 +                               dwc_otg_cleanup_fiq_channel(hcd, i);
37260 +                       }
37261 +                       DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s",
37262 +                               (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "",
37263 +                               (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "",
37264 +                               (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "",
37265 +                               (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : "");
37266 +               }
37267 +       }
37268 +
37269 +       /* Initialize the Connection timeout timer. */
37270 +       hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
37271 +                                         dwc_otg_hcd_connect_timeout, 0);
37272 +
37273 +       printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled");
37274 +       if (microframe_schedule)
37275 +               init_hcd_usecs(hcd);
37276 +
37277 +       /* Initialize reset tasklet. */
37278 +       hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
37279 +
37280 +       hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet",
37281 +                                               completion_tasklet_func, hcd);
37282 +#ifdef DWC_DEV_SRPCAP
37283 +       if (hcd->core_if->power_down == 2) {
37284 +               /* Initialize Power on timer for Host power up in case hibernation */
37285 +               hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
37286 +                                                                       dwc_otg_hcd_power_up, core_if);
37287 +       }
37288 +#endif
37289 +
37290 +       /*
37291 +        * Allocate space for storing data on status transactions. Normally no
37292 +        * data is sent, but this space acts as a bit bucket. This must be
37293 +        * done after usb_add_hcd since that function allocates the DMA buffer
37294 +        * pool.
37295 +        */
37296 +       if (hcd->core_if->dma_enable) {
37297 +               hcd->status_buf =
37298 +                   DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
37299 +                                 &hcd->status_buf_dma);
37300 +       } else {
37301 +               hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
37302 +       }
37303 +       if (!hcd->status_buf) {
37304 +               retval = -DWC_E_NO_MEMORY;
37305 +               DWC_ERROR("%s: status_buf allocation failed\n", __func__);
37306 +               dwc_otg_hcd_free(hcd);
37307 +               goto out;
37308 +       }
37309 +
37310 +       hcd->otg_port = 1;
37311 +       hcd->frame_list = NULL;
37312 +       hcd->frame_list_dma = 0;
37313 +       hcd->periodic_qh_count = 0;
37314 +
37315 +       DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port));
37316 +#ifdef FIQ_DEBUG
37317 +       DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc));
37318 +#endif
37319 +
37320 +out:
37321 +       return retval;
37322 +}
37323 +
37324 +void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
37325 +{
37326 +       /* Turn off all host-specific interrupts. */
37327 +       dwc_otg_disable_host_interrupts(hcd->core_if);
37328 +
37329 +       dwc_otg_hcd_free(hcd);
37330 +}
37331 +
37332 +/**
37333 + * Initializes dynamic portions of the DWC_otg HCD state.
37334 + */
37335 +static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
37336 +{
37337 +       int num_channels;
37338 +       int i;
37339 +       dwc_hc_t *channel;
37340 +       dwc_hc_t *channel_tmp;
37341 +
37342 +       hcd->flags.d32 = 0;
37343 +
37344 +       hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
37345 +       if (!microframe_schedule) {
37346 +               hcd->non_periodic_channels = 0;
37347 +               hcd->periodic_channels = 0;
37348 +       } else {
37349 +               hcd->available_host_channels = hcd->core_if->core_params->host_channels;
37350 +       }
37351 +       /*
37352 +        * Put all channels in the free channel list and clean up channel
37353 +        * states.
37354 +        */
37355 +       DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
37356 +                                &hcd->free_hc_list, hc_list_entry) {
37357 +               DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
37358 +       }
37359 +
37360 +       num_channels = hcd->core_if->core_params->host_channels;
37361 +       for (i = 0; i < num_channels; i++) {
37362 +               channel = hcd->hc_ptr_array[i];
37363 +               DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
37364 +                                       hc_list_entry);
37365 +               dwc_otg_hc_cleanup(hcd->core_if, channel);
37366 +       }
37367 +
37368 +       /* Initialize the DWC core for host mode operation. */
37369 +       dwc_otg_core_host_init(hcd->core_if);
37370 +
37371 +       /* Set core_if's lock pointer to the hcd->lock */
37372 +       hcd->core_if->lock = hcd->lock;
37373 +}
37374 +
37375 +/**
37376 + * Assigns transactions from a QTD to a free host channel and initializes the
37377 + * host channel to perform the transactions. The host channel is removed from
37378 + * the free list.
37379 + *
37380 + * @param hcd The HCD state structure.
37381 + * @param qh Transactions from the first QTD for this QH are selected and
37382 + * assigned to a free host channel.
37383 + */
37384 +static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
37385 +{
37386 +       dwc_hc_t *hc;
37387 +       dwc_otg_qtd_t *qtd;
37388 +       dwc_otg_hcd_urb_t *urb;
37389 +       void* ptr = NULL;
37390 +       uint32_t intr_enable;
37391 +       unsigned long flags;
37392 +       gintmsk_data_t gintmsk = { .d32 = 0, };
37393 +
37394 +       qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
37395 +
37396 +       urb = qtd->urb;
37397 +
37398 +       DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length);
37399 +
37400 +       if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info))
37401 +               urb->actual_length = urb->length;
37402 +
37403 +
37404 +       hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
37405 +
37406 +       /* Remove the host channel from the free list. */
37407 +       DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
37408 +
37409 +       qh->channel = hc;
37410 +
37411 +       qtd->in_process = 1;
37412 +
37413 +       /*
37414 +        * Use usb_pipedevice to determine device address. This address is
37415 +        * 0 before the SET_ADDRESS command and the correct address afterward.
37416 +        */
37417 +       hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
37418 +       hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
37419 +       hc->speed = qh->dev_speed;
37420 +       hc->max_packet = dwc_max_packet(qh->maxp);
37421 +
37422 +       hc->xfer_started = 0;
37423 +       hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
37424 +       hc->error_state = (qtd->error_count > 0);
37425 +       hc->halt_on_queue = 0;
37426 +       hc->halt_pending = 0;
37427 +       hc->requests = 0;
37428 +
37429 +       /*
37430 +        * The following values may be modified in the transfer type section
37431 +        * below. The xfer_len value may be reduced when the transfer is
37432 +        * started to accommodate the max widths of the XferSize and PktCnt
37433 +        * fields in the HCTSIZn register.
37434 +        */
37435 +
37436 +       hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
37437 +       if (hc->ep_is_in) {
37438 +               hc->do_ping = 0;
37439 +       } else {
37440 +               hc->do_ping = qh->ping_state;
37441 +       }
37442 +
37443 +       hc->data_pid_start = qh->data_toggle;
37444 +       hc->multi_count = 1;
37445 +
37446 +       if (hcd->core_if->dma_enable) {
37447 +               hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
37448 +
37449 +               /* For non-dword aligned case */
37450 +               if (((unsigned long)hc->xfer_buff & 0x3)
37451 +                   && !hcd->core_if->dma_desc_enable) {
37452 +                       ptr = (uint8_t *) urb->buf + urb->actual_length;
37453 +               }
37454 +       } else {
37455 +               hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
37456 +       }
37457 +       hc->xfer_len = urb->length - urb->actual_length;
37458 +       hc->xfer_count = 0;
37459 +
37460 +       /*
37461 +        * Set the split attributes
37462 +        */
37463 +       hc->do_split = 0;
37464 +       if (qh->do_split) {
37465 +               uint32_t hub_addr, port_addr;
37466 +               hc->do_split = 1;
37467 +               hc->xact_pos = qtd->isoc_split_pos;
37468 +               /* We don't need to do complete splits anymore */
37469 +//             if(fiq_fsm_enable)
37470 +               if (0)
37471 +                       hc->complete_split = qtd->complete_split = 0;
37472 +               else
37473 +                       hc->complete_split = qtd->complete_split;
37474 +
37475 +               hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
37476 +               hc->hub_addr = (uint8_t) hub_addr;
37477 +               hc->port_addr = (uint8_t) port_addr;
37478 +       }
37479 +
37480 +       switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
37481 +       case UE_CONTROL:
37482 +               hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
37483 +               switch (qtd->control_phase) {
37484 +               case DWC_OTG_CONTROL_SETUP:
37485 +                       DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
37486 +                       hc->do_ping = 0;
37487 +                       hc->ep_is_in = 0;
37488 +                       hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
37489 +                       if (hcd->core_if->dma_enable) {
37490 +                               hc->xfer_buff = (uint8_t *) urb->setup_dma;
37491 +                       } else {
37492 +                               hc->xfer_buff = (uint8_t *) urb->setup_packet;
37493 +                       }
37494 +                       hc->xfer_len = 8;
37495 +                       ptr = NULL;
37496 +                       break;
37497 +               case DWC_OTG_CONTROL_DATA:
37498 +                       DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
37499 +                       hc->data_pid_start = qtd->data_toggle;
37500 +                       break;
37501 +               case DWC_OTG_CONTROL_STATUS:
37502 +                       /*
37503 +                        * Direction is opposite of data direction or IN if no
37504 +                        * data.
37505 +                        */
37506 +                       DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
37507 +                       if (urb->length == 0) {
37508 +                               hc->ep_is_in = 1;
37509 +                       } else {
37510 +                               hc->ep_is_in =
37511 +                                   dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
37512 +                       }
37513 +                       if (hc->ep_is_in) {
37514 +                               hc->do_ping = 0;
37515 +                       }
37516 +
37517 +                       hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
37518 +
37519 +                       hc->xfer_len = 0;
37520 +                       if (hcd->core_if->dma_enable) {
37521 +                               hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
37522 +                       } else {
37523 +                               hc->xfer_buff = (uint8_t *) hcd->status_buf;
37524 +                       }
37525 +                       ptr = NULL;
37526 +                       break;
37527 +               }
37528 +               break;
37529 +       case UE_BULK:
37530 +               hc->ep_type = DWC_OTG_EP_TYPE_BULK;
37531 +               break;
37532 +       case UE_INTERRUPT:
37533 +               hc->ep_type = DWC_OTG_EP_TYPE_INTR;
37534 +               break;
37535 +       case UE_ISOCHRONOUS:
37536 +               {
37537 +                       struct dwc_otg_hcd_iso_packet_desc *frame_desc;
37538 +
37539 +                       hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
37540 +
37541 +                       if (hcd->core_if->dma_desc_enable)
37542 +                               break;
37543 +
37544 +                       frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
37545 +
37546 +                       frame_desc->status = 0;
37547 +
37548 +                       if (hcd->core_if->dma_enable) {
37549 +                               hc->xfer_buff = (uint8_t *) urb->dma;
37550 +                       } else {
37551 +                               hc->xfer_buff = (uint8_t *) urb->buf;
37552 +                       }
37553 +                       hc->xfer_buff +=
37554 +                           frame_desc->offset + qtd->isoc_split_offset;
37555 +                       hc->xfer_len =
37556 +                           frame_desc->length - qtd->isoc_split_offset;
37557 +
37558 +                       /* For non-dword aligned buffers */
37559 +                       if (((unsigned long)hc->xfer_buff & 0x3)
37560 +                           && hcd->core_if->dma_enable) {
37561 +                               ptr =
37562 +                                   (uint8_t *) urb->buf + frame_desc->offset +
37563 +                                   qtd->isoc_split_offset;
37564 +                       } else
37565 +                               ptr = NULL;
37566 +
37567 +                       if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
37568 +                               if (hc->xfer_len <= 188) {
37569 +                                       hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
37570 +                               } else {
37571 +                                       hc->xact_pos =
37572 +                                           DWC_HCSPLIT_XACTPOS_BEGIN;
37573 +                               }
37574 +                       }
37575 +               }
37576 +               break;
37577 +       }
37578 +       /* non DWORD-aligned buffer case */
37579 +       if (ptr) {
37580 +               uint32_t buf_size;
37581 +               if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
37582 +                       buf_size = hcd->core_if->core_params->max_transfer_size;
37583 +               } else {
37584 +                       buf_size = 4096;
37585 +               }
37586 +               if (!qh->dw_align_buf) {
37587 +                       qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
37588 +                                                        &qh->dw_align_buf_dma);
37589 +                       if (!qh->dw_align_buf) {
37590 +                               DWC_ERROR
37591 +                                   ("%s: Failed to allocate memory to handle "
37592 +                                    "non-dword aligned buffer case\n",
37593 +                                    __func__);
37594 +                               return;
37595 +                       }
37596 +               }
37597 +               if (!hc->ep_is_in) {
37598 +                       dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
37599 +               }
37600 +               hc->align_buff = qh->dw_align_buf_dma;
37601 +       } else {
37602 +               hc->align_buff = 0;
37603 +       }
37604 +
37605 +       if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
37606 +           hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
37607 +               /*
37608 +                * This value may be modified when the transfer is started to
37609 +                * reflect the actual transfer length.
37610 +                */
37611 +               hc->multi_count = dwc_hb_mult(qh->maxp);
37612 +       }
37613 +
37614 +       if (hcd->core_if->dma_desc_enable)
37615 +               hc->desc_list_addr = qh->desc_list_dma;
37616 +
37617 +       dwc_otg_hc_init(hcd->core_if, hc);
37618 +
37619 +       local_irq_save(flags);
37620 +
37621 +       if (fiq_enable) {
37622 +               local_fiq_disable();
37623 +               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
37624 +       }
37625 +
37626 +       /* Enable the top level host channel interrupt. */
37627 +       intr_enable = (1 << hc->hc_num);
37628 +       DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable);
37629 +
37630 +       /* Make sure host channel interrupts are enabled. */
37631 +       gintmsk.b.hcintr = 1;
37632 +       DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
37633 +
37634 +       if (fiq_enable) {
37635 +               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
37636 +               local_fiq_enable();
37637 +       }
37638 +
37639 +       local_irq_restore(flags);
37640 +       hc->qh = qh;
37641 +}
37642 +
37643 +
37644 +/**
37645 + * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ
37646 + * @qh:        pointer to the endpoint's queue head
37647 + *
37648 + * Transaction start/end control flow is grafted onto the existing dwc_otg
37649 + * mechanisms, to avoid spaghettifying the functions more than they already are.
37650 + * This function's eligibility check is altered by debug parameter.
37651 + *
37652 + * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction.
37653 + */
37654 +
37655 +int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh)
37656 +{
37657 +       if (qh->do_split) {
37658 +               switch (qh->ep_type) {
37659 +               case UE_CONTROL:
37660 +               case UE_BULK:
37661 +                       if (fiq_fsm_mask & (1 << 0))
37662 +                               return 1;
37663 +                       break;
37664 +               case UE_INTERRUPT:
37665 +               case UE_ISOCHRONOUS:
37666 +                       if (fiq_fsm_mask & (1 << 1))
37667 +                               return 1;
37668 +                       break;
37669 +               default:
37670 +                       break;
37671 +               }
37672 +       } else if (qh->ep_type == UE_ISOCHRONOUS) {
37673 +               if (fiq_fsm_mask & (1 << 2)) {
37674 +                       /* HS ISOCH support. We test for compatibility:
37675 +                        * - DWORD aligned buffers
37676 +                        * - Must be at least 2 transfers (otherwise pointless to use the FIQ)
37677 +                        * If yes, then the fsm enqueue function will handle the state machine setup.
37678 +                        */
37679 +                       dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
37680 +                       dwc_otg_hcd_urb_t *urb = qtd->urb;
37681 +                       struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs;
37682 +                       int nr_iso_frames = urb->packet_count;
37683 +                       int i;
37684 +                       uint32_t ptr;
37685 +
37686 +                       if (nr_iso_frames < 2)
37687 +                               return 0;
37688 +                       for (i = 0; i < nr_iso_frames; i++) {
37689 +                               ptr = urb->dma + iso_descs[i]->offset;
37690 +                               if (ptr & 0x3) {
37691 +                                       printk_ratelimited("%s: Non-Dword aligned isochronous frame offset."
37692 +                                                       " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n",
37693 +                                                       __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num);
37694 +                                       return 0;
37695 +                               }
37696 +                       }
37697 +                       return 1;
37698 +               }
37699 +       }
37700 +       return 0;
37701 +}
37702 +
37703 +/**
37704 + * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers
37705 + * @hcd: Pointer to the dwc_otg_hcd struct
37706 + * @qh: Pointer to the endpoint's queue head
37707 + *
37708 + * Periodic split transactions are transmitted modulo 188 bytes.
37709 + * This necessitates slicing data up into buckets for isochronous out
37710 + * and fixing up the DMA address for all IN transfers.
37711 + *
37712 + * Returns 1 if the DMA bounce buffers have been used, 0 if the default
37713 + * HC buffer has been used.
37714 + */
37715 +int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh)
37716 + {
37717 +       int frame_length, i = 0;
37718 +       uint8_t *ptr = NULL;
37719 +       dwc_hc_t *hc = qh->channel;
37720 +       struct fiq_dma_blob *blob;
37721 +       struct dwc_otg_hcd_iso_packet_desc *frame_desc;
37722 +
37723 +       for (i = 0; i < 6; i++) {
37724 +               st->dma_info.slot_len[i] = 255;
37725 +       }
37726 +       st->dma_info.index = 0;
37727 +       i = 0;
37728 +       if (hc->ep_is_in) {
37729 +               /*
37730 +                * Set dma_regs to bounce buffer. FIQ will update the
37731 +                * state depending on transaction progress.
37732 +                */
37733 +               blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
37734 +               st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
37735 +               /* Calculate the max number of CSPLITS such that the FIQ can time out
37736 +                * a transaction if it fails.
37737 +                */
37738 +               frame_length = st->hcchar_copy.b.mps;
37739 +               do {
37740 +                       i++;
37741 +                       frame_length -= 188;
37742 +               } while (frame_length >= 0);
37743 +               st->nrpackets = i;
37744 +               return 1;
37745 +       } else {
37746 +               if (qh->ep_type == UE_ISOCHRONOUS) {
37747 +
37748 +                       dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
37749 +
37750 +                       frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
37751 +                       frame_length = frame_desc->length;
37752 +
37753 +                       /* Virtual address for bounce buffers */
37754 +                       blob = hcd->fiq_dmab;
37755 +
37756 +                       ptr = qtd->urb->buf + frame_desc->offset;
37757 +                       if (frame_length == 0) {
37758 +                               /*
37759 +                                * for isochronous transactions, we must still transmit a packet
37760 +                                * even if the length is zero.
37761 +                                */
37762 +                               st->dma_info.slot_len[0] = 0;
37763 +                               st->nrpackets = 1;
37764 +                       } else {
37765 +                               do {
37766 +                                       if (frame_length <= 188) {
37767 +                                               dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length);
37768 +                                               st->dma_info.slot_len[i] = frame_length;
37769 +                                               ptr += frame_length;
37770 +                                       } else {
37771 +                                               dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188);
37772 +                                               st->dma_info.slot_len[i] = 188;
37773 +                                               ptr += 188;
37774 +                                       }
37775 +                                       i++;
37776 +                                       frame_length -= 188;
37777 +                               } while (frame_length > 0);
37778 +                               st->nrpackets = i;
37779 +                       }
37780 +                       ptr = qtd->urb->buf + frame_desc->offset;
37781 +                       /* Point the HC at the DMA address of the bounce buffers */
37782 +                       blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base;
37783 +                       st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0];
37784 +
37785 +                       /* fixup xfersize to the actual packet size */
37786 +                       st->hctsiz_copy.b.pid = 0;
37787 +                       st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0];
37788 +                       return 1;
37789 +               } else {
37790 +                       /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */
37791 +                       return 0;
37792 +               }
37793 +       }
37794 +}
37795 +
37796 +/*
37797 + * Pushing a periodic request into the queue near the EOF1 point
37798 + * in a microframe causes erroneous behaviour (frmovrun) interrupt.
37799 + * Usually, the request goes out on the bus causing a transfer but
37800 + * the core does not transfer the data to memory.
37801 + * This guard interval (in number of 60MHz clocks) is required which
37802 + * must cater for CPU latency between reading the value and enabling
37803 + * the channel.
37804 + */
37805 +#define PERIODIC_FRREM_BACKOFF 1000
37806 +
37807 +int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
37808 +{
37809 +       dwc_hc_t *hc = qh->channel;
37810 +       dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
37811 +       dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
37812 +       int frame;
37813 +       struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
37814 +       int xfer_len, nrpackets;
37815 +       hcdma_data_t hcdma;
37816 +       hfnum_data_t hfnum;
37817 +
37818 +       if (st->fsm != FIQ_PASSTHROUGH)
37819 +               return 0;
37820 +
37821 +       st->nr_errors = 0;
37822 +
37823 +       st->hcchar_copy.d32 = 0;
37824 +       st->hcchar_copy.b.mps = hc->max_packet;
37825 +       st->hcchar_copy.b.epdir = hc->ep_is_in;
37826 +       st->hcchar_copy.b.devaddr = hc->dev_addr;
37827 +       st->hcchar_copy.b.epnum = hc->ep_num;
37828 +       st->hcchar_copy.b.eptype = hc->ep_type;
37829 +
37830 +       st->hcintmsk_copy.b.chhltd = 1;
37831 +
37832 +       frame = dwc_otg_hcd_get_frame_number(hcd);
37833 +       st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
37834 +
37835 +       st->hcchar_copy.b.lspddev = 0;
37836 +       /* Enable the channel later as a final register write. */
37837 +
37838 +       st->hcsplt_copy.d32 = 0;
37839 +
37840 +       st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs;
37841 +       st->hs_isoc_info.nrframes = qtd->urb->packet_count;
37842 +       /* grab the next DMA address offset from the array */
37843 +       st->hcdma_copy.d32 = qtd->urb->dma;
37844 +       hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset;
37845 +
37846 +       /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as
37847 +        * the core needs to be told to send the correct number. Caution: for IN transfers,
37848 +        * this is always set to the maximum size of the endpoint. */
37849 +       xfer_len = st->hs_isoc_info.iso_desc[0].length;
37850 +       nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps;
37851 +       if (nrpackets == 0)
37852 +               nrpackets = 1;
37853 +       st->hcchar_copy.b.multicnt = nrpackets;
37854 +       st->hctsiz_copy.b.pktcnt = nrpackets;
37855 +
37856 +       /* Initial PID also needs to be set */
37857 +       if (st->hcchar_copy.b.epdir == 0) {
37858 +               st->hctsiz_copy.b.xfersize = xfer_len;
37859 +               switch (st->hcchar_copy.b.multicnt) {
37860 +               case 1:
37861 +                       st->hctsiz_copy.b.pid = DWC_PID_DATA0;
37862 +                       break;
37863 +               case 2:
37864 +               case 3:
37865 +                       st->hctsiz_copy.b.pid = DWC_PID_MDATA;
37866 +                       break;
37867 +               }
37868 +
37869 +       } else {
37870 +               st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps;
37871 +               switch (st->hcchar_copy.b.multicnt) {
37872 +               case 1:
37873 +                       st->hctsiz_copy.b.pid = DWC_PID_DATA0;
37874 +                       break;
37875 +               case 2:
37876 +                       st->hctsiz_copy.b.pid = DWC_PID_DATA1;
37877 +                       break;
37878 +               case 3:
37879 +                       st->hctsiz_copy.b.pid = DWC_PID_DATA2;
37880 +                       break;
37881 +               }
37882 +       }
37883 +
37884 +       st->hs_isoc_info.stride = qh->interval;
37885 +       st->uframe_sleeps = 0;
37886 +
37887 +       fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ  %01d ", hc->hc_num);
37888 +       fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32);
37889 +       fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
37890 +       fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
37891 +       hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
37892 +       local_fiq_disable();
37893 +       fiq_fsm_spin_lock(&hcd->fiq_state->lock);
37894 +       DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
37895 +       DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
37896 +       DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
37897 +       DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
37898 +       DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
37899 +       if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
37900 +               /* Prevent queueing near EOF1. Bad things happen if a periodic
37901 +                * split transaction is queued very close to EOF. SOF interrupt handler
37902 +                * will wake this channel at the next interrupt.
37903 +                */
37904 +               st->fsm = FIQ_HS_ISOC_SLEEPING;
37905 +               st->uframe_sleeps = 1;
37906 +       } else {
37907 +               st->fsm = FIQ_HS_ISOC_TURBO;
37908 +               st->hcchar_copy.b.chen = 1;
37909 +               DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
37910 +       }
37911 +       mb();
37912 +       st->hcchar_copy.b.chen = 0;
37913 +       fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
37914 +       local_fiq_enable();
37915 +       return 0;
37916 +}
37917 +
37918 +
37919 +/**
37920 + * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state
37921 + * @hcd: Pointer to the dwc_otg_hcd struct
37922 + * @qh: Pointer to the endpoint's queue head
37923 + *
37924 + * This overrides the dwc_otg driver's normal method of queueing a transaction.
37925 + * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup
37926 + * for the nominated host channel.
37927 + *
37928 + * For periodic transfers, it also peeks at the FIQ state to see if an immediate
37929 + * start is possible. If not, then the FIQ is left to start the transfer.
37930 + */
37931 +int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
37932 +{
37933 +       int start_immediate = 1, i;
37934 +       hfnum_data_t hfnum;
37935 +       dwc_hc_t *hc = qh->channel;
37936 +       dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
37937 +       /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */
37938 +       int hub_addr, port_addr, frame, uframe;
37939 +       struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num];
37940 +
37941 +       if (st->fsm != FIQ_PASSTHROUGH)
37942 +               return 0;
37943 +       st->nr_errors = 0;
37944 +
37945 +       st->hcchar_copy.d32 = 0;
37946 +       st->hcchar_copy.b.mps = hc->max_packet;
37947 +       st->hcchar_copy.b.epdir = hc->ep_is_in;
37948 +       st->hcchar_copy.b.devaddr = hc->dev_addr;
37949 +       st->hcchar_copy.b.epnum = hc->ep_num;
37950 +       st->hcchar_copy.b.eptype = hc->ep_type;
37951 +       if (hc->ep_type & 0x1) {
37952 +               if (hc->ep_is_in)
37953 +                       st->hcchar_copy.b.multicnt = 3;
37954 +               else
37955 +                       /* Docs say set this to 1, but driver sets to 0! */
37956 +                       st->hcchar_copy.b.multicnt = 0;
37957 +       } else {
37958 +               st->hcchar_copy.b.multicnt = 1;
37959 +               st->hcchar_copy.b.oddfrm = 0;
37960 +       }
37961 +       st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0;
37962 +       /* Enable the channel later as a final register write. */
37963 +
37964 +       st->hcsplt_copy.d32 = 0;
37965 +       if(qh->do_split) {
37966 +               hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr);
37967 +               st->hcsplt_copy.b.compsplt = 0;
37968 +               st->hcsplt_copy.b.spltena = 1;
37969 +               // XACTPOS is for isoc-out only but needs initialising anyway.
37970 +               st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL;
37971 +               if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) {
37972 +                       /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL.
37973 +                        * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ
37974 +                        * will update as necessary.
37975 +                        */
37976 +                       if (hc->xfer_len > 188) {
37977 +                               st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN;
37978 +                       }
37979 +               }
37980 +               st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr;
37981 +               st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr;
37982 +               st->hub_addr = hub_addr;
37983 +               st->port_addr = port_addr;
37984 +       }
37985 +
37986 +       st->hctsiz_copy.d32 = 0;
37987 +       st->hctsiz_copy.b.dopng = 0;
37988 +       st->hctsiz_copy.b.pid = hc->data_pid_start;
37989 +
37990 +       if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
37991 +               hc->xfer_len = hc->max_packet;
37992 +       } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
37993 +               hc->xfer_len = 188;
37994 +       }
37995 +       st->hctsiz_copy.b.xfersize = hc->xfer_len;
37996 +
37997 +       st->hctsiz_copy.b.pktcnt = 1;
37998 +
37999 +       if (hc->ep_type & 0x1) {
38000 +               /*
38001 +                * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers,
38002 +                * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array.
38003 +                * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt
38004 +                * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set
38005 +                * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ
38006 +                * must not touch internal driver state.
38007 +                */
38008 +               if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) {
38009 +                       if (hc->align_buff) {
38010 +                               st->hcdma_copy.d32 = hc->align_buff;
38011 +                       } else {
38012 +                               st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38013 +                       }
38014 +               }
38015 +       } else {
38016 +               if (hc->align_buff) {
38017 +                       st->hcdma_copy.d32 = hc->align_buff;
38018 +               } else {
38019 +                       st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38020 +               }
38021 +       }
38022 +       /* The FIQ depends upon no other interrupts being enabled except channel halt.
38023 +        * Fixup channel interrupt mask. */
38024 +       st->hcintmsk_copy.d32 = 0;
38025 +       st->hcintmsk_copy.b.chhltd = 1;
38026 +       st->hcintmsk_copy.b.ahberr = 1;
38027 +
38028 +       /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions
38029 +        * as Control puts the transfer into the non-periodic request queue and the
38030 +        * non-periodic handler in the hub. Makes things lots easier.
38031 +        */
38032 +       if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) {
38033 +               st->hcchar_copy.b.multicnt = 0;
38034 +               st->hcchar_copy.b.oddfrm = 0;
38035 +               st->hcchar_copy.b.eptype = UE_CONTROL;
38036 +               if (hc->align_buff) {
38037 +                       st->hcdma_copy.d32 = hc->align_buff;
38038 +               } else {
38039 +                       st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF);
38040 +               }
38041 +       }
38042 +       DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32);
38043 +       DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32);
38044 +       DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32);
38045 +       DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38046 +       DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32);
38047 +
38048 +       local_fiq_disable();
38049 +       fiq_fsm_spin_lock(&hcd->fiq_state->lock);
38050 +
38051 +       if (hc->ep_type & 0x1) {
38052 +               hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
38053 +               frame = (hfnum.b.frnum & ~0x7) >> 3;
38054 +               uframe = hfnum.b.frnum & 0x7;
38055 +               if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) {
38056 +                       /* Prevent queueing near EOF1. Bad things happen if a periodic
38057 +                        * split transaction is queued very close to EOF.
38058 +                        */
38059 +                       start_immediate = 0;
38060 +               } else if (uframe == 5) {
38061 +                       start_immediate = 0;
38062 +               } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) {
38063 +                       start_immediate = 0;
38064 +               } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) {
38065 +                       start_immediate = 0;
38066 +               } else {
38067 +                       /* Search through all host channels to determine if a transaction
38068 +                        * is currently in progress */
38069 +                       for (i = 0; i < hcd->core_if->core_params->host_channels; i++) {
38070 +                               if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH)
38071 +                                       continue;
38072 +                               switch (hcd->fiq_state->channel[i].fsm) {
38073 +                               /* TT is reserved for channels that are in the middle of a periodic
38074 +                                * split transaction.
38075 +                                */
38076 +                               case FIQ_PER_SSPLIT_STARTED:
38077 +                               case FIQ_PER_CSPLIT_WAIT:
38078 +                               case FIQ_PER_CSPLIT_NYET1:
38079 +                               case FIQ_PER_CSPLIT_POLL:
38080 +                               case FIQ_PER_ISO_OUT_ACTIVE:
38081 +                               case FIQ_PER_ISO_OUT_LAST:
38082 +                                       if (hcd->fiq_state->channel[i].hub_addr == hub_addr &&
38083 +                                                       hcd->fiq_state->channel[i].port_addr == port_addr) {
38084 +                                               start_immediate = 0;
38085 +                                       }
38086 +                                       break;
38087 +                               default:
38088 +                                       break;
38089 +                               }
38090 +                               if (!start_immediate)
38091 +                                       break;
38092 +                       }
38093 +               }
38094 +       }
38095 +       if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT)
38096 +               start_immediate = 1;
38097 +
38098 +       fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate);
38099 +       fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem);
38100 +       //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr);
38101 +       //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32);
38102 +       //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32);
38103 +       switch (hc->ep_type) {
38104 +               case UE_CONTROL:
38105 +               case UE_BULK:
38106 +                       st->fsm = FIQ_NP_SSPLIT_STARTED;
38107 +                       break;
38108 +               case UE_ISOCHRONOUS:
38109 +                       if (hc->ep_is_in) {
38110 +                               if (start_immediate) {
38111 +                                       st->fsm = FIQ_PER_SSPLIT_STARTED;
38112 +                               } else {
38113 +                                       st->fsm = FIQ_PER_SSPLIT_QUEUED;
38114 +                               }
38115 +                       } else {
38116 +                               if (start_immediate) {
38117 +                                       /* Single-isoc OUT packets don't require FIQ involvement */
38118 +                                       if (st->nrpackets == 1) {
38119 +                                               st->fsm = FIQ_PER_ISO_OUT_LAST;
38120 +                                       } else {
38121 +                                               st->fsm = FIQ_PER_ISO_OUT_ACTIVE;
38122 +                                       }
38123 +                               } else {
38124 +                                       st->fsm = FIQ_PER_ISO_OUT_PENDING;
38125 +                               }
38126 +                       }
38127 +                       break;
38128 +               case UE_INTERRUPT:
38129 +                       if (fiq_fsm_mask & 0x8) {
38130 +                               st->fsm = FIQ_NP_SSPLIT_STARTED;
38131 +                       } else if (start_immediate) {
38132 +                                       st->fsm = FIQ_PER_SSPLIT_STARTED;
38133 +                       } else {
38134 +                               st->fsm = FIQ_PER_SSPLIT_QUEUED;
38135 +                       }
38136 +               default:
38137 +                       break;
38138 +       }
38139 +       if (start_immediate) {
38140 +               /* Set the oddfrm bit as close as possible to actual queueing */
38141 +               frame = dwc_otg_hcd_get_frame_number(hcd);
38142 +               st->expected_uframe = (frame + 1) & 0x3FFF;
38143 +               st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1;
38144 +               st->hcchar_copy.b.chen = 1;
38145 +               DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32);
38146 +       }
38147 +       mb();
38148 +       fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
38149 +       local_fiq_enable();
38150 +       return 0;
38151 +}
38152 +
38153 +
38154 +/**
38155 + * This function selects transactions from the HCD transfer schedule and
38156 + * assigns them to available host channels. It is called from HCD interrupt
38157 + * handler functions.
38158 + *
38159 + * @param hcd The HCD state structure.
38160 + *
38161 + * @return The types of new transactions that were assigned to host channels.
38162 + */
38163 +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
38164 +{
38165 +       dwc_list_link_t *qh_ptr;
38166 +       dwc_otg_qh_t *qh;
38167 +       int num_channels;
38168 +       dwc_irqflags_t flags;
38169 +       dwc_spinlock_t *channel_lock = hcd->channel_lock;
38170 +       dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
38171 +
38172 +#ifdef DEBUG_HOST_CHANNELS
38173 +       last_sel_trans_num_per_scheduled = 0;
38174 +       last_sel_trans_num_nonper_scheduled = 0;
38175 +       last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels;
38176 +#endif /* DEBUG_HOST_CHANNELS */
38177 +
38178 +       /* Process entries in the periodic ready list. */
38179 +       qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
38180 +
38181 +       while (qh_ptr != &hcd->periodic_sched_ready &&
38182 +              !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
38183 +
38184 +               qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38185 +
38186 +               if (microframe_schedule) {
38187 +                       // Make sure we leave one channel for non periodic transactions.
38188 +                       DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38189 +                       if (hcd->available_host_channels <= 1) {
38190 +                               DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38191 +                               break;
38192 +                       }
38193 +                       hcd->available_host_channels--;
38194 +                       DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38195 +#ifdef DEBUG_HOST_CHANNELS
38196 +                       last_sel_trans_num_per_scheduled++;
38197 +#endif /* DEBUG_HOST_CHANNELS */
38198 +               }
38199 +               qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38200 +               assign_and_init_hc(hcd, qh);
38201 +
38202 +               /*
38203 +                * Move the QH from the periodic ready schedule to the
38204 +                * periodic assigned schedule.
38205 +                */
38206 +               qh_ptr = DWC_LIST_NEXT(qh_ptr);
38207 +               DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38208 +               DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
38209 +                                  &qh->qh_list_entry);
38210 +               DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38211 +       }
38212 +
38213 +       /*
38214 +        * Process entries in the inactive portion of the non-periodic
38215 +        * schedule. Some free host channels may not be used if they are
38216 +        * reserved for periodic transfers.
38217 +        */
38218 +       qh_ptr = hcd->non_periodic_sched_inactive.next;
38219 +       num_channels = hcd->core_if->core_params->host_channels;
38220 +       while (qh_ptr != &hcd->non_periodic_sched_inactive &&
38221 +              (microframe_schedule || hcd->non_periodic_channels <
38222 +               num_channels - hcd->periodic_channels) &&
38223 +              !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
38224 +
38225 +               qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38226 +               /*
38227 +                * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission
38228 +                * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed
38229 +                * cheeky devices that just hold off using NAKs
38230 +                */
38231 +               if (fiq_enable && nak_holdoff && qh->do_split) {
38232 +                       if (qh->nak_frame != 0xffff) {
38233 +                               uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8);
38234 +                               uint16_t frame = dwc_otg_hcd_get_frame_number(hcd);
38235 +                               if (dwc_frame_num_le(frame, next_frame)) {
38236 +                                       if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) {
38237 +                                               hcd->fiq_state->next_sched_frame = next_frame;
38238 +                                       }
38239 +                                       qh_ptr = DWC_LIST_NEXT(qh_ptr);
38240 +                                       continue;
38241 +                               } else {
38242 +                                       qh->nak_frame = 0xFFFF;
38243 +                               }
38244 +                       }
38245 +               }
38246 +
38247 +               if (microframe_schedule) {
38248 +                               DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38249 +                               if (hcd->available_host_channels < 1) {
38250 +                                       DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38251 +                                       break;
38252 +                               }
38253 +                               hcd->available_host_channels--;
38254 +                               DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38255 +#ifdef DEBUG_HOST_CHANNELS
38256 +                               last_sel_trans_num_nonper_scheduled++;
38257 +#endif /* DEBUG_HOST_CHANNELS */
38258 +               }
38259 +
38260 +               assign_and_init_hc(hcd, qh);
38261 +
38262 +               /*
38263 +                * Move the QH from the non-periodic inactive schedule to the
38264 +                * non-periodic active schedule.
38265 +                */
38266 +               qh_ptr = DWC_LIST_NEXT(qh_ptr);
38267 +               DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
38268 +               DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
38269 +                                  &qh->qh_list_entry);
38270 +               DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
38271 +
38272 +
38273 +               if (!microframe_schedule)
38274 +                       hcd->non_periodic_channels++;
38275 +       }
38276 +       /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty,
38277 +        * stop the FIQ from kicking us. We could potentially still have elements here if we
38278 +        * ran out of host channels.
38279 +        */
38280 +       if (fiq_enable) {
38281 +               if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) {
38282 +                       hcd->fiq_state->kick_np_queues = 0;
38283 +               } else {
38284 +                       /* For each entry remaining in the NP inactive queue,
38285 +                       * if this a NAK'd retransmit then don't set the kick flag.
38286 +                       */
38287 +                       if(nak_holdoff) {
38288 +                               DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) {
38289 +                                       qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38290 +                                       if (qh->nak_frame == 0xFFFF) {
38291 +                                               hcd->fiq_state->kick_np_queues = 1;
38292 +                                       }
38293 +                               }
38294 +                       }
38295 +               }
38296 +       }
38297 +       if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned))
38298 +               ret_val |= DWC_OTG_TRANSACTION_PERIODIC;
38299 +
38300 +       if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active))
38301 +               ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC;
38302 +
38303 +
38304 +#ifdef DEBUG_HOST_CHANNELS
38305 +       last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels;
38306 +#endif /* DEBUG_HOST_CHANNELS */
38307 +       return ret_val;
38308 +}
38309 +
38310 +/**
38311 + * Attempts to queue a single transaction request for a host channel
38312 + * associated with either a periodic or non-periodic transfer. This function
38313 + * assumes that there is space available in the appropriate request queue. For
38314 + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
38315 + * is available in the appropriate Tx FIFO.
38316 + *
38317 + * @param hcd The HCD state structure.
38318 + * @param hc Host channel descriptor associated with either a periodic or
38319 + * non-periodic transfer.
38320 + * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
38321 + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
38322 + * transfers.
38323 + *
38324 + * @return 1 if a request is queued and more requests may be needed to
38325 + * complete the transfer, 0 if no more requests are required for this
38326 + * transfer, -1 if there is insufficient space in the Tx FIFO.
38327 + */
38328 +static int queue_transaction(dwc_otg_hcd_t * hcd,
38329 +                            dwc_hc_t * hc, uint16_t fifo_dwords_avail)
38330 +{
38331 +       int retval;
38332 +
38333 +       if (hcd->core_if->dma_enable) {
38334 +               if (hcd->core_if->dma_desc_enable) {
38335 +                       if (!hc->xfer_started
38336 +                           || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
38337 +                               dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
38338 +                               hc->qh->ping_state = 0;
38339 +                       }
38340 +               } else if (!hc->xfer_started) {
38341 +                       if (fiq_fsm_enable && hc->error_state) {
38342 +                               hcd->fiq_state->channel[hc->hc_num].nr_errors =
38343 +                                       DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count;
38344 +                               hcd->fiq_state->channel[hc->hc_num].fsm =
38345 +                                       FIQ_PASSTHROUGH_ERRORSTATE;
38346 +                       }
38347 +                       dwc_otg_hc_start_transfer(hcd->core_if, hc);
38348 +                       hc->qh->ping_state = 0;
38349 +               }
38350 +               retval = 0;
38351 +       } else if (hc->halt_pending) {
38352 +               /* Don't queue a request if the channel has been halted. */
38353 +               retval = 0;
38354 +       } else if (hc->halt_on_queue) {
38355 +               dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
38356 +               retval = 0;
38357 +       } else if (hc->do_ping) {
38358 +               if (!hc->xfer_started) {
38359 +                       dwc_otg_hc_start_transfer(hcd->core_if, hc);
38360 +               }
38361 +               retval = 0;
38362 +       } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
38363 +               if ((fifo_dwords_avail * 4) >= hc->max_packet) {
38364 +                       if (!hc->xfer_started) {
38365 +                               dwc_otg_hc_start_transfer(hcd->core_if, hc);
38366 +                               retval = 1;
38367 +                       } else {
38368 +                               retval =
38369 +                                   dwc_otg_hc_continue_transfer(hcd->core_if,
38370 +                                                                hc);
38371 +                       }
38372 +               } else {
38373 +                       retval = -1;
38374 +               }
38375 +       } else {
38376 +               if (!hc->xfer_started) {
38377 +                       dwc_otg_hc_start_transfer(hcd->core_if, hc);
38378 +                       retval = 1;
38379 +               } else {
38380 +                       retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
38381 +               }
38382 +       }
38383 +
38384 +       return retval;
38385 +}
38386 +
38387 +/**
38388 + * Processes periodic channels for the next frame and queues transactions for
38389 + * these channels to the DWC_otg controller. After queueing transactions, the
38390 + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
38391 + * to queue as Periodic Tx FIFO or request queue space becomes available.
38392 + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
38393 + */
38394 +static void process_periodic_channels(dwc_otg_hcd_t * hcd)
38395 +{
38396 +       hptxsts_data_t tx_status;
38397 +       dwc_list_link_t *qh_ptr;
38398 +       dwc_otg_qh_t *qh;
38399 +       int status = 0;
38400 +       int no_queue_space = 0;
38401 +       int no_fifo_space = 0;
38402 +
38403 +       dwc_otg_host_global_regs_t *host_regs;
38404 +       host_regs = hcd->core_if->host_if->host_global_regs;
38405 +
38406 +       DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
38407 +#ifdef DEBUG
38408 +       tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
38409 +       DWC_DEBUGPL(DBG_HCDV,
38410 +                   "  P Tx Req Queue Space Avail (before queue): %d\n",
38411 +                   tx_status.b.ptxqspcavail);
38412 +       DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
38413 +                   tx_status.b.ptxfspcavail);
38414 +#endif
38415 +
38416 +       qh_ptr = hcd->periodic_sched_assigned.next;
38417 +       while (qh_ptr != &hcd->periodic_sched_assigned) {
38418 +               tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
38419 +               if (tx_status.b.ptxqspcavail == 0) {
38420 +                       no_queue_space = 1;
38421 +                       break;
38422 +               }
38423 +
38424 +               qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
38425 +
38426 +               // Do not send a split start transaction any later than frame .6
38427 +               // Note, we have to schedule a periodic in .5 to make it go in .6
38428 +               if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6)
38429 +               {
38430 +                       qh_ptr = qh_ptr->next;
38431 +                       hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7;
38432 +                       continue;
38433 +               }
38434 +
38435 +               if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
38436 +                       if (qh->do_split)
38437 +                               fiq_fsm_queue_split_transaction(hcd, qh);
38438 +                       else
38439 +                               fiq_fsm_queue_isoc_transaction(hcd, qh);
38440 +               } else {
38441 +
38442 +                       /*
38443 +                        * Set a flag if we're queueing high-bandwidth in slave mode.
38444 +                        * The flag prevents any halts to get into the request queue in
38445 +                        * the middle of multiple high-bandwidth packets getting queued.
38446 +                        */
38447 +                       if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
38448 +                               hcd->core_if->queuing_high_bandwidth = 1;
38449 +                       }
38450 +                       status = queue_transaction(hcd, qh->channel,
38451 +                                                       tx_status.b.ptxfspcavail);
38452 +                       if (status < 0) {
38453 +                               no_fifo_space = 1;
38454 +                               break;
38455 +                       }
38456 +               }
38457 +
38458 +               /*
38459 +                * In Slave mode, stay on the current transfer until there is
38460 +                * nothing more to do or the high-bandwidth request count is
38461 +                * reached. In DMA mode, only need to queue one request. The
38462 +                * controller automatically handles multiple packets for
38463 +                * high-bandwidth transfers.
38464 +                */
38465 +               if (hcd->core_if->dma_enable || status == 0 ||
38466 +                   qh->channel->requests == qh->channel->multi_count) {
38467 +                       qh_ptr = qh_ptr->next;
38468 +                       /*
38469 +                        * Move the QH from the periodic assigned schedule to
38470 +                        * the periodic queued schedule.
38471 +                        */
38472 +                       DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
38473 +                                          &qh->qh_list_entry);
38474 +
38475 +                       /* done queuing high bandwidth */
38476 +                       hcd->core_if->queuing_high_bandwidth = 0;
38477 +               }
38478 +       }
38479 +
38480 +       if (!hcd->core_if->dma_enable) {
38481 +               dwc_otg_core_global_regs_t *global_regs;
38482 +               gintmsk_data_t intr_mask = {.d32 = 0 };
38483 +
38484 +               global_regs = hcd->core_if->core_global_regs;
38485 +               intr_mask.b.ptxfempty = 1;
38486 +#ifdef DEBUG
38487 +               tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
38488 +               DWC_DEBUGPL(DBG_HCDV,
38489 +                           "  P Tx Req Queue Space Avail (after queue): %d\n",
38490 +                           tx_status.b.ptxqspcavail);
38491 +               DWC_DEBUGPL(DBG_HCDV,
38492 +                           "  P Tx FIFO Space Avail (after queue): %d\n",
38493 +                           tx_status.b.ptxfspcavail);
38494 +#endif
38495 +               if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
38496 +                   no_queue_space || no_fifo_space) {
38497 +                       /*
38498 +                        * May need to queue more transactions as the request
38499 +                        * queue or Tx FIFO empties. Enable the periodic Tx
38500 +                        * FIFO empty interrupt. (Always use the half-empty
38501 +                        * level to ensure that new requests are loaded as
38502 +                        * soon as possible.)
38503 +                        */
38504 +                       DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
38505 +                                        intr_mask.d32);
38506 +               } else {
38507 +                       /*
38508 +                        * Disable the Tx FIFO empty interrupt since there are
38509 +                        * no more transactions that need to be queued right
38510 +                        * now. This function is called from interrupt
38511 +                        * handlers to queue more transactions as transfer
38512 +                        * states change.
38513 +                        */
38514 +                       DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
38515 +                                        0);
38516 +               }
38517 +       }
38518 +}
38519 +
38520 +/**
38521 + * Processes active non-periodic channels and queues transactions for these
38522 + * channels to the DWC_otg controller. After queueing transactions, the NP Tx
38523 + * FIFO Empty interrupt is enabled if there are more transactions to queue as
38524 + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
38525 + * FIFO Empty interrupt is disabled.
38526 + */
38527 +static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
38528 +{
38529 +       gnptxsts_data_t tx_status;
38530 +       dwc_list_link_t *orig_qh_ptr;
38531 +       dwc_otg_qh_t *qh;
38532 +       int status;
38533 +       int no_queue_space = 0;
38534 +       int no_fifo_space = 0;
38535 +       int more_to_do = 0;
38536 +
38537 +       dwc_otg_core_global_regs_t *global_regs =
38538 +           hcd->core_if->core_global_regs;
38539 +
38540 +       DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
38541 +#ifdef DEBUG
38542 +       tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
38543 +       DWC_DEBUGPL(DBG_HCDV,
38544 +                   "  NP Tx Req Queue Space Avail (before queue): %d\n",
38545 +                   tx_status.b.nptxqspcavail);
38546 +       DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
38547 +                   tx_status.b.nptxfspcavail);
38548 +#endif
38549 +       /*
38550 +        * Keep track of the starting point. Skip over the start-of-list
38551 +        * entry.
38552 +        */
38553 +       if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
38554 +               hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
38555 +       }
38556 +       orig_qh_ptr = hcd->non_periodic_qh_ptr;
38557 +
38558 +       /*
38559 +        * Process once through the active list or until no more space is
38560 +        * available in the request queue or the Tx FIFO.
38561 +        */
38562 +       do {
38563 +               tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
38564 +               if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
38565 +                       no_queue_space = 1;
38566 +                       break;
38567 +               }
38568 +
38569 +               qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
38570 +                                   qh_list_entry);
38571 +
38572 +               if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) {
38573 +                       fiq_fsm_queue_split_transaction(hcd, qh);
38574 +               } else {
38575 +                       status = queue_transaction(hcd, qh->channel,
38576 +                                               tx_status.b.nptxfspcavail);
38577 +
38578 +                       if (status > 0) {
38579 +                               more_to_do = 1;
38580 +                       } else if (status < 0) {
38581 +                               no_fifo_space = 1;
38582 +                               break;
38583 +                       }
38584 +               }
38585 +               /* Advance to next QH, skipping start-of-list entry. */
38586 +               hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
38587 +               if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
38588 +                       hcd->non_periodic_qh_ptr =
38589 +                           hcd->non_periodic_qh_ptr->next;
38590 +               }
38591 +
38592 +       } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
38593 +
38594 +       if (!hcd->core_if->dma_enable) {
38595 +               gintmsk_data_t intr_mask = {.d32 = 0 };
38596 +               intr_mask.b.nptxfempty = 1;
38597 +
38598 +#ifdef DEBUG
38599 +               tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
38600 +               DWC_DEBUGPL(DBG_HCDV,
38601 +                           "  NP Tx Req Queue Space Avail (after queue): %d\n",
38602 +                           tx_status.b.nptxqspcavail);
38603 +               DWC_DEBUGPL(DBG_HCDV,
38604 +                           "  NP Tx FIFO Space Avail (after queue): %d\n",
38605 +                           tx_status.b.nptxfspcavail);
38606 +#endif
38607 +               if (more_to_do || no_queue_space || no_fifo_space) {
38608 +                       /*
38609 +                        * May need to queue more transactions as the request
38610 +                        * queue or Tx FIFO empties. Enable the non-periodic
38611 +                        * Tx FIFO empty interrupt. (Always use the half-empty
38612 +                        * level to ensure that new requests are loaded as
38613 +                        * soon as possible.)
38614 +                        */
38615 +                       DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
38616 +                                        intr_mask.d32);
38617 +               } else {
38618 +                       /*
38619 +                        * Disable the Tx FIFO empty interrupt since there are
38620 +                        * no more transactions that need to be queued right
38621 +                        * now. This function is called from interrupt
38622 +                        * handlers to queue more transactions as transfer
38623 +                        * states change.
38624 +                        */
38625 +                       DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
38626 +                                        0);
38627 +               }
38628 +       }
38629 +}
38630 +
38631 +/**
38632 + * This function processes the currently active host channels and queues
38633 + * transactions for these channels to the DWC_otg controller. It is called
38634 + * from HCD interrupt handler functions.
38635 + *
38636 + * @param hcd The HCD state structure.
38637 + * @param tr_type The type(s) of transactions to queue (non-periodic,
38638 + * periodic, or both).
38639 + */
38640 +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
38641 +                                   dwc_otg_transaction_type_e tr_type)
38642 +{
38643 +#ifdef DEBUG_SOF
38644 +       DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
38645 +#endif
38646 +       /* Process host channels associated with periodic transfers. */
38647 +       if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
38648 +            tr_type == DWC_OTG_TRANSACTION_ALL) &&
38649 +           !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
38650 +
38651 +               process_periodic_channels(hcd);
38652 +       }
38653 +
38654 +       /* Process host channels associated with non-periodic transfers. */
38655 +       if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
38656 +           tr_type == DWC_OTG_TRANSACTION_ALL) {
38657 +               if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
38658 +                       process_non_periodic_channels(hcd);
38659 +               } else {
38660 +                       /*
38661 +                        * Ensure NP Tx FIFO empty interrupt is disabled when
38662 +                        * there are no non-periodic transfers to process.
38663 +                        */
38664 +                       gintmsk_data_t gintmsk = {.d32 = 0 };
38665 +                       gintmsk.b.nptxfempty = 1;
38666 +
38667 +                       if (fiq_enable) {
38668 +                               local_fiq_disable();
38669 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
38670 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
38671 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
38672 +                               local_fiq_enable();
38673 +                       } else {
38674 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
38675 +                       }
38676 +               }
38677 +       }
38678 +}
38679 +
38680 +#ifdef DWC_HS_ELECT_TST
38681 +/*
38682 + * Quick and dirty hack to implement the HS Electrical Test
38683 + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
38684 + *
38685 + * This code was copied from our userspace app "hset". It sends a
38686 + * Get Device Descriptor control sequence in two parts, first the
38687 + * Setup packet by itself, followed some time later by the In and
38688 + * Ack packets. Rather than trying to figure out how to add this
38689 + * functionality to the normal driver code, we just hijack the
38690 + * hardware, using these two function to drive the hardware
38691 + * directly.
38692 + */
38693 +
38694 +static dwc_otg_core_global_regs_t *global_regs;
38695 +static dwc_otg_host_global_regs_t *hc_global_regs;
38696 +static dwc_otg_hc_regs_t *hc_regs;
38697 +static uint32_t *data_fifo;
38698 +
38699 +static void do_setup(void)
38700 +{
38701 +       gintsts_data_t gintsts;
38702 +       hctsiz_data_t hctsiz;
38703 +       hcchar_data_t hcchar;
38704 +       haint_data_t haint;
38705 +       hcint_data_t hcint;
38706 +
38707 +       /* Enable HAINTs */
38708 +       DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
38709 +
38710 +       /* Enable HCINTs */
38711 +       DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
38712 +
38713 +       /* Read GINTSTS */
38714 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38715 +
38716 +       /* Read HAINT */
38717 +       haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
38718 +
38719 +       /* Read HCINT */
38720 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
38721 +
38722 +       /* Read HCCHAR */
38723 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38724 +
38725 +       /* Clear HCINT */
38726 +       DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
38727 +
38728 +       /* Clear HAINT */
38729 +       DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
38730 +
38731 +       /* Clear GINTSTS */
38732 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38733 +
38734 +       /* Read GINTSTS */
38735 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38736 +
38737 +       /*
38738 +        * Send Setup packet (Get Device Descriptor)
38739 +        */
38740 +
38741 +       /* Make sure channel is disabled */
38742 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38743 +       if (hcchar.b.chen) {
38744 +               hcchar.b.chdis = 1;
38745 +//              hcchar.b.chen = 1;
38746 +               DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
38747 +               //sleep(1);
38748 +               dwc_mdelay(1000);
38749 +
38750 +               /* Read GINTSTS */
38751 +               gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38752 +
38753 +               /* Read HAINT */
38754 +               haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
38755 +
38756 +               /* Read HCINT */
38757 +               hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
38758 +
38759 +               /* Read HCCHAR */
38760 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38761 +
38762 +               /* Clear HCINT */
38763 +               DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
38764 +
38765 +               /* Clear HAINT */
38766 +               DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
38767 +
38768 +               /* Clear GINTSTS */
38769 +               DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38770 +
38771 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38772 +       }
38773 +
38774 +       /* Set HCTSIZ */
38775 +       hctsiz.d32 = 0;
38776 +       hctsiz.b.xfersize = 8;
38777 +       hctsiz.b.pktcnt = 1;
38778 +       hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
38779 +       DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
38780 +
38781 +       /* Set HCCHAR */
38782 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38783 +       hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
38784 +       hcchar.b.epdir = 0;
38785 +       hcchar.b.epnum = 0;
38786 +       hcchar.b.mps = 8;
38787 +       hcchar.b.chen = 1;
38788 +       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
38789 +
38790 +       /* Fill FIFO with Setup data for Get Device Descriptor */
38791 +       data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
38792 +       DWC_WRITE_REG32(data_fifo++, 0x01000680);
38793 +       DWC_WRITE_REG32(data_fifo++, 0x00080000);
38794 +
38795 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38796 +
38797 +       /* Wait for host channel interrupt */
38798 +       do {
38799 +               gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38800 +       } while (gintsts.b.hcintr == 0);
38801 +
38802 +       /* Disable HCINTs */
38803 +       DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
38804 +
38805 +       /* Disable HAINTs */
38806 +       DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
38807 +
38808 +       /* Read HAINT */
38809 +       haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
38810 +
38811 +       /* Read HCINT */
38812 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
38813 +
38814 +       /* Read HCCHAR */
38815 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38816 +
38817 +       /* Clear HCINT */
38818 +       DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
38819 +
38820 +       /* Clear HAINT */
38821 +       DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
38822 +
38823 +       /* Clear GINTSTS */
38824 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38825 +
38826 +       /* Read GINTSTS */
38827 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38828 +}
38829 +
38830 +static void do_in_ack(void)
38831 +{
38832 +       gintsts_data_t gintsts;
38833 +       hctsiz_data_t hctsiz;
38834 +       hcchar_data_t hcchar;
38835 +       haint_data_t haint;
38836 +       hcint_data_t hcint;
38837 +       host_grxsts_data_t grxsts;
38838 +
38839 +       /* Enable HAINTs */
38840 +       DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
38841 +
38842 +       /* Enable HCINTs */
38843 +       DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
38844 +
38845 +       /* Read GINTSTS */
38846 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38847 +
38848 +       /* Read HAINT */
38849 +       haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
38850 +
38851 +       /* Read HCINT */
38852 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
38853 +
38854 +       /* Read HCCHAR */
38855 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38856 +
38857 +       /* Clear HCINT */
38858 +       DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
38859 +
38860 +       /* Clear HAINT */
38861 +       DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
38862 +
38863 +       /* Clear GINTSTS */
38864 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38865 +
38866 +       /* Read GINTSTS */
38867 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38868 +
38869 +       /*
38870 +        * Receive Control In packet
38871 +        */
38872 +
38873 +       /* Make sure channel is disabled */
38874 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38875 +       if (hcchar.b.chen) {
38876 +               hcchar.b.chdis = 1;
38877 +               hcchar.b.chen = 1;
38878 +               DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
38879 +               //sleep(1);
38880 +               dwc_mdelay(1000);
38881 +
38882 +               /* Read GINTSTS */
38883 +               gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38884 +
38885 +               /* Read HAINT */
38886 +               haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
38887 +
38888 +               /* Read HCINT */
38889 +               hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
38890 +
38891 +               /* Read HCCHAR */
38892 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38893 +
38894 +               /* Clear HCINT */
38895 +               DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
38896 +
38897 +               /* Clear HAINT */
38898 +               DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
38899 +
38900 +               /* Clear GINTSTS */
38901 +               DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38902 +
38903 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38904 +       }
38905 +
38906 +       /* Set HCTSIZ */
38907 +       hctsiz.d32 = 0;
38908 +       hctsiz.b.xfersize = 8;
38909 +       hctsiz.b.pktcnt = 1;
38910 +       hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
38911 +       DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
38912 +
38913 +       /* Set HCCHAR */
38914 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38915 +       hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
38916 +       hcchar.b.epdir = 1;
38917 +       hcchar.b.epnum = 0;
38918 +       hcchar.b.mps = 8;
38919 +       hcchar.b.chen = 1;
38920 +       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
38921 +
38922 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38923 +
38924 +       /* Wait for receive status queue interrupt */
38925 +       do {
38926 +               gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38927 +       } while (gintsts.b.rxstsqlvl == 0);
38928 +
38929 +       /* Read RXSTS */
38930 +       grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
38931 +
38932 +       /* Clear RXSTSQLVL in GINTSTS */
38933 +       gintsts.d32 = 0;
38934 +       gintsts.b.rxstsqlvl = 1;
38935 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38936 +
38937 +       switch (grxsts.b.pktsts) {
38938 +       case DWC_GRXSTS_PKTSTS_IN:
38939 +               /* Read the data into the host buffer */
38940 +               if (grxsts.b.bcnt > 0) {
38941 +                       int i;
38942 +                       int word_count = (grxsts.b.bcnt + 3) / 4;
38943 +
38944 +                       data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
38945 +
38946 +                       for (i = 0; i < word_count; i++) {
38947 +                               (void)DWC_READ_REG32(data_fifo++);
38948 +                       }
38949 +               }
38950 +               break;
38951 +
38952 +       default:
38953 +               break;
38954 +       }
38955 +
38956 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38957 +
38958 +       /* Wait for receive status queue interrupt */
38959 +       do {
38960 +               gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38961 +       } while (gintsts.b.rxstsqlvl == 0);
38962 +
38963 +       /* Read RXSTS */
38964 +       grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
38965 +
38966 +       /* Clear RXSTSQLVL in GINTSTS */
38967 +       gintsts.d32 = 0;
38968 +       gintsts.b.rxstsqlvl = 1;
38969 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
38970 +
38971 +       switch (grxsts.b.pktsts) {
38972 +       case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
38973 +               break;
38974 +
38975 +       default:
38976 +               break;
38977 +       }
38978 +
38979 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38980 +
38981 +       /* Wait for host channel interrupt */
38982 +       do {
38983 +               gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
38984 +       } while (gintsts.b.hcintr == 0);
38985 +
38986 +       /* Read HAINT */
38987 +       haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
38988 +
38989 +       /* Read HCINT */
38990 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
38991 +
38992 +       /* Read HCCHAR */
38993 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
38994 +
38995 +       /* Clear HCINT */
38996 +       DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
38997 +
38998 +       /* Clear HAINT */
38999 +       DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39000 +
39001 +       /* Clear GINTSTS */
39002 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39003 +
39004 +       /* Read GINTSTS */
39005 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39006 +
39007 +//      usleep(100000);
39008 +//      mdelay(100);
39009 +       dwc_mdelay(1);
39010 +
39011 +       /*
39012 +        * Send handshake packet
39013 +        */
39014 +
39015 +       /* Read HAINT */
39016 +       haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39017 +
39018 +       /* Read HCINT */
39019 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39020 +
39021 +       /* Read HCCHAR */
39022 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39023 +
39024 +       /* Clear HCINT */
39025 +       DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39026 +
39027 +       /* Clear HAINT */
39028 +       DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39029 +
39030 +       /* Clear GINTSTS */
39031 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39032 +
39033 +       /* Read GINTSTS */
39034 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39035 +
39036 +       /* Make sure channel is disabled */
39037 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39038 +       if (hcchar.b.chen) {
39039 +               hcchar.b.chdis = 1;
39040 +               hcchar.b.chen = 1;
39041 +               DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39042 +               //sleep(1);
39043 +               dwc_mdelay(1000);
39044 +
39045 +               /* Read GINTSTS */
39046 +               gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39047 +
39048 +               /* Read HAINT */
39049 +               haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39050 +
39051 +               /* Read HCINT */
39052 +               hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39053 +
39054 +               /* Read HCCHAR */
39055 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39056 +
39057 +               /* Clear HCINT */
39058 +               DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39059 +
39060 +               /* Clear HAINT */
39061 +               DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39062 +
39063 +               /* Clear GINTSTS */
39064 +               DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39065 +
39066 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39067 +       }
39068 +
39069 +       /* Set HCTSIZ */
39070 +       hctsiz.d32 = 0;
39071 +       hctsiz.b.xfersize = 0;
39072 +       hctsiz.b.pktcnt = 1;
39073 +       hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
39074 +       DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
39075 +
39076 +       /* Set HCCHAR */
39077 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39078 +       hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
39079 +       hcchar.b.epdir = 0;
39080 +       hcchar.b.epnum = 0;
39081 +       hcchar.b.mps = 8;
39082 +       hcchar.b.chen = 1;
39083 +       DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
39084 +
39085 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39086 +
39087 +       /* Wait for host channel interrupt */
39088 +       do {
39089 +               gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39090 +       } while (gintsts.b.hcintr == 0);
39091 +
39092 +       /* Disable HCINTs */
39093 +       DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
39094 +
39095 +       /* Disable HAINTs */
39096 +       DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
39097 +
39098 +       /* Read HAINT */
39099 +       haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
39100 +
39101 +       /* Read HCINT */
39102 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
39103 +
39104 +       /* Read HCCHAR */
39105 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
39106 +
39107 +       /* Clear HCINT */
39108 +       DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
39109 +
39110 +       /* Clear HAINT */
39111 +       DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
39112 +
39113 +       /* Clear GINTSTS */
39114 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
39115 +
39116 +       /* Read GINTSTS */
39117 +       gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
39118 +}
39119 +#endif
39120 +
39121 +/** Handles hub class-specific requests. */
39122 +int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
39123 +                           uint16_t typeReq,
39124 +                           uint16_t wValue,
39125 +                           uint16_t wIndex, uint8_t * buf, uint16_t wLength)
39126 +{
39127 +       int retval = 0;
39128 +
39129 +       dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
39130 +       usb_hub_descriptor_t *hub_desc;
39131 +       hprt0_data_t hprt0 = {.d32 = 0 };
39132 +
39133 +       uint32_t port_status;
39134 +
39135 +       switch (typeReq) {
39136 +       case UCR_CLEAR_HUB_FEATURE:
39137 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39138 +                           "ClearHubFeature 0x%x\n", wValue);
39139 +               switch (wValue) {
39140 +               case UHF_C_HUB_LOCAL_POWER:
39141 +               case UHF_C_HUB_OVER_CURRENT:
39142 +                       /* Nothing required here */
39143 +                       break;
39144 +               default:
39145 +                       retval = -DWC_E_INVALID;
39146 +                       DWC_ERROR("DWC OTG HCD - "
39147 +                                 "ClearHubFeature request %xh unknown\n",
39148 +                                 wValue);
39149 +               }
39150 +               break;
39151 +       case UCR_CLEAR_PORT_FEATURE:
39152 +#ifdef CONFIG_USB_DWC_OTG_LPM
39153 +               if (wValue != UHF_PORT_L1)
39154 +#endif
39155 +                       if (!wIndex || wIndex > 1)
39156 +                               goto error;
39157 +
39158 +               switch (wValue) {
39159 +               case UHF_PORT_ENABLE:
39160 +                       DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
39161 +                                   "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
39162 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
39163 +                       hprt0.b.prtena = 1;
39164 +                       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39165 +                       break;
39166 +               case UHF_PORT_SUSPEND:
39167 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39168 +                                   "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
39169 +
39170 +                       if (core_if->power_down == 2) {
39171 +                               dwc_otg_host_hibernation_restore(core_if, 0, 0);
39172 +                       } else {
39173 +                               DWC_WRITE_REG32(core_if->pcgcctl, 0);
39174 +                               dwc_mdelay(5);
39175 +
39176 +                               hprt0.d32 = dwc_otg_read_hprt0(core_if);
39177 +                               hprt0.b.prtres = 1;
39178 +                               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39179 +                               hprt0.b.prtsusp = 0;
39180 +                               /* Clear Resume bit */
39181 +                               dwc_mdelay(100);
39182 +                               hprt0.b.prtres = 0;
39183 +                               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39184 +                       }
39185 +                       break;
39186 +#ifdef CONFIG_USB_DWC_OTG_LPM
39187 +               case UHF_PORT_L1:
39188 +                       {
39189 +                               pcgcctl_data_t pcgcctl = {.d32 = 0 };
39190 +                               glpmcfg_data_t lpmcfg = {.d32 = 0 };
39191 +
39192 +                               lpmcfg.d32 =
39193 +                                   DWC_READ_REG32(&core_if->
39194 +                                                  core_global_regs->glpmcfg);
39195 +                               lpmcfg.b.en_utmi_sleep = 0;
39196 +                               lpmcfg.b.hird_thres &= (~(1 << 4));
39197 +                               lpmcfg.b.prt_sleep_sts = 1;
39198 +                               DWC_WRITE_REG32(&core_if->
39199 +                                               core_global_regs->glpmcfg,
39200 +                                               lpmcfg.d32);
39201 +
39202 +                               /* Clear Enbl_L1Gating bit. */
39203 +                               pcgcctl.b.enbl_sleep_gating = 1;
39204 +                               DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
39205 +                                                0);
39206 +
39207 +                               dwc_mdelay(5);
39208 +
39209 +                               hprt0.d32 = dwc_otg_read_hprt0(core_if);
39210 +                               hprt0.b.prtres = 1;
39211 +                               DWC_WRITE_REG32(core_if->host_if->hprt0,
39212 +                                               hprt0.d32);
39213 +                               /* This bit will be cleared in wakeup interrupt handle */
39214 +                               break;
39215 +                       }
39216 +#endif
39217 +               case UHF_PORT_POWER:
39218 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39219 +                                   "ClearPortFeature USB_PORT_FEAT_POWER\n");
39220 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
39221 +                       hprt0.b.prtpwr = 0;
39222 +                       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39223 +                       break;
39224 +               case UHF_PORT_INDICATOR:
39225 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39226 +                                   "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
39227 +                       /* Port inidicator not supported */
39228 +                       break;
39229 +               case UHF_C_PORT_CONNECTION:
39230 +                       /* Clears drivers internal connect status change
39231 +                        * flag */
39232 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39233 +                                   "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
39234 +                       dwc_otg_hcd->flags.b.port_connect_status_change = 0;
39235 +                       break;
39236 +               case UHF_C_PORT_RESET:
39237 +                       /* Clears the driver's internal Port Reset Change
39238 +                        * flag */
39239 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39240 +                                   "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
39241 +                       dwc_otg_hcd->flags.b.port_reset_change = 0;
39242 +                       break;
39243 +               case UHF_C_PORT_ENABLE:
39244 +                       /* Clears the driver's internal Port
39245 +                        * Enable/Disable Change flag */
39246 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39247 +                                   "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
39248 +                       dwc_otg_hcd->flags.b.port_enable_change = 0;
39249 +                       break;
39250 +               case UHF_C_PORT_SUSPEND:
39251 +                       /* Clears the driver's internal Port Suspend
39252 +                        * Change flag, which is set when resume signaling on
39253 +                        * the host port is complete */
39254 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39255 +                                   "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
39256 +                       dwc_otg_hcd->flags.b.port_suspend_change = 0;
39257 +                       break;
39258 +#ifdef CONFIG_USB_DWC_OTG_LPM
39259 +               case UHF_C_PORT_L1:
39260 +                       dwc_otg_hcd->flags.b.port_l1_change = 0;
39261 +                       break;
39262 +#endif
39263 +               case UHF_C_PORT_OVER_CURRENT:
39264 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39265 +                                   "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
39266 +                       dwc_otg_hcd->flags.b.port_over_current_change = 0;
39267 +                       break;
39268 +               default:
39269 +                       retval = -DWC_E_INVALID;
39270 +                       DWC_ERROR("DWC OTG HCD - "
39271 +                                 "ClearPortFeature request %xh "
39272 +                                 "unknown or unsupported\n", wValue);
39273 +               }
39274 +               break;
39275 +       case UCR_GET_HUB_DESCRIPTOR:
39276 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39277 +                           "GetHubDescriptor\n");
39278 +               hub_desc = (usb_hub_descriptor_t *) buf;
39279 +               hub_desc->bDescLength = 9;
39280 +               hub_desc->bDescriptorType = 0x29;
39281 +               hub_desc->bNbrPorts = 1;
39282 +               USETW(hub_desc->wHubCharacteristics, 0x08);
39283 +               hub_desc->bPwrOn2PwrGood = 1;
39284 +               hub_desc->bHubContrCurrent = 0;
39285 +               hub_desc->DeviceRemovable[0] = 0;
39286 +               hub_desc->DeviceRemovable[1] = 0xff;
39287 +               break;
39288 +       case UCR_GET_HUB_STATUS:
39289 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39290 +                           "GetHubStatus\n");
39291 +               DWC_MEMSET(buf, 0, 4);
39292 +               break;
39293 +       case UCR_GET_PORT_STATUS:
39294 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39295 +                           "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
39296 +                           wIndex, dwc_otg_hcd->flags.d32);
39297 +               if (!wIndex || wIndex > 1)
39298 +                       goto error;
39299 +
39300 +               port_status = 0;
39301 +
39302 +               if (dwc_otg_hcd->flags.b.port_connect_status_change)
39303 +                       port_status |= (1 << UHF_C_PORT_CONNECTION);
39304 +
39305 +               if (dwc_otg_hcd->flags.b.port_enable_change)
39306 +                       port_status |= (1 << UHF_C_PORT_ENABLE);
39307 +
39308 +               if (dwc_otg_hcd->flags.b.port_suspend_change)
39309 +                       port_status |= (1 << UHF_C_PORT_SUSPEND);
39310 +
39311 +               if (dwc_otg_hcd->flags.b.port_l1_change)
39312 +                       port_status |= (1 << UHF_C_PORT_L1);
39313 +
39314 +               if (dwc_otg_hcd->flags.b.port_reset_change) {
39315 +                       port_status |= (1 << UHF_C_PORT_RESET);
39316 +               }
39317 +
39318 +               if (dwc_otg_hcd->flags.b.port_over_current_change) {
39319 +                       DWC_WARN("Overcurrent change detected\n");
39320 +                       port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
39321 +               }
39322 +
39323 +               if (!dwc_otg_hcd->flags.b.port_connect_status) {
39324 +                       /*
39325 +                        * The port is disconnected, which means the core is
39326 +                        * either in device mode or it soon will be. Just
39327 +                        * return 0's for the remainder of the port status
39328 +                        * since the port register can't be read if the core
39329 +                        * is in device mode.
39330 +                        */
39331 +                       *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
39332 +                       break;
39333 +               }
39334 +
39335 +               hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
39336 +               DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
39337 +
39338 +               if (hprt0.b.prtconnsts)
39339 +                       port_status |= (1 << UHF_PORT_CONNECTION);
39340 +
39341 +               if (hprt0.b.prtena)
39342 +                       port_status |= (1 << UHF_PORT_ENABLE);
39343 +
39344 +               if (hprt0.b.prtsusp)
39345 +                       port_status |= (1 << UHF_PORT_SUSPEND);
39346 +
39347 +               if (hprt0.b.prtovrcurract)
39348 +                       port_status |= (1 << UHF_PORT_OVER_CURRENT);
39349 +
39350 +               if (hprt0.b.prtrst)
39351 +                       port_status |= (1 << UHF_PORT_RESET);
39352 +
39353 +               if (hprt0.b.prtpwr)
39354 +                       port_status |= (1 << UHF_PORT_POWER);
39355 +
39356 +               if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
39357 +                       port_status |= (1 << UHF_PORT_HIGH_SPEED);
39358 +               else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
39359 +                       port_status |= (1 << UHF_PORT_LOW_SPEED);
39360 +
39361 +               if (hprt0.b.prttstctl)
39362 +                       port_status |= (1 << UHF_PORT_TEST);
39363 +               if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
39364 +                       port_status |= (1 << UHF_PORT_L1);
39365 +               }
39366 +               /*
39367 +                  For Synopsys HW emulation of Power down wkup_control asserts the
39368 +                  hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
39369 +                  We intentionally tell the software that port is in L2Suspend state.
39370 +                  Only for STE.
39371 +               */
39372 +               if ((core_if->power_down == 2)
39373 +                   && (core_if->hibernation_suspend == 1)) {
39374 +                       port_status |= (1 << UHF_PORT_SUSPEND);
39375 +               }
39376 +               /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
39377 +
39378 +               *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
39379 +
39380 +               break;
39381 +       case UCR_SET_HUB_FEATURE:
39382 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39383 +                           "SetHubFeature\n");
39384 +               /* No HUB features supported */
39385 +               break;
39386 +       case UCR_SET_PORT_FEATURE:
39387 +               if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
39388 +                       goto error;
39389 +
39390 +               if (!dwc_otg_hcd->flags.b.port_connect_status) {
39391 +                       /*
39392 +                        * The port is disconnected, which means the core is
39393 +                        * either in device mode or it soon will be. Just
39394 +                        * return without doing anything since the port
39395 +                        * register can't be written if the core is in device
39396 +                        * mode.
39397 +                        */
39398 +                       break;
39399 +               }
39400 +
39401 +               switch (wValue) {
39402 +               case UHF_PORT_SUSPEND:
39403 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39404 +                                   "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
39405 +                       if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
39406 +                               goto error;
39407 +                       }
39408 +                       if (core_if->power_down == 2) {
39409 +                               int timeout = 300;
39410 +                               dwc_irqflags_t flags;
39411 +                               pcgcctl_data_t pcgcctl = {.d32 = 0 };
39412 +                               gpwrdn_data_t gpwrdn = {.d32 = 0 };
39413 +                               gusbcfg_data_t gusbcfg = {.d32 = 0 };
39414 +#ifdef DWC_DEV_SRPCAP
39415 +                               int32_t otg_cap_param = core_if->core_params->otg_cap;
39416 +#endif
39417 +                               DWC_PRINTF("Preparing for complete power-off\n");
39418 +
39419 +                               /* Save registers before hibernation */
39420 +                               dwc_otg_save_global_regs(core_if);
39421 +                               dwc_otg_save_host_regs(core_if);
39422 +
39423 +                               hprt0.d32 = dwc_otg_read_hprt0(core_if);
39424 +                               hprt0.b.prtsusp = 1;
39425 +                               hprt0.b.prtena = 0;
39426 +                               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39427 +                               /* Spin hprt0.b.prtsusp to became 1 */
39428 +                               do {
39429 +                                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
39430 +                                       if (hprt0.b.prtsusp) {
39431 +                                               break;
39432 +                                       }
39433 +                                       dwc_mdelay(1);
39434 +                               } while (--timeout);
39435 +                               if (!timeout) {
39436 +                                       DWC_WARN("Suspend wasn't genereted\n");
39437 +                               }
39438 +                               dwc_udelay(10);
39439 +
39440 +                               /*
39441 +                                * We need to disable interrupts to prevent servicing of any IRQ
39442 +                                * during going to hibernation
39443 +                                */
39444 +                               DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
39445 +                               core_if->lx_state = DWC_OTG_L2;
39446 +#ifdef DWC_DEV_SRPCAP
39447 +                               hprt0.d32 = dwc_otg_read_hprt0(core_if);
39448 +                               hprt0.b.prtpwr = 0;
39449 +                               hprt0.b.prtena = 0;
39450 +                               DWC_WRITE_REG32(core_if->host_if->hprt0,
39451 +                                               hprt0.d32);
39452 +#endif
39453 +                               gusbcfg.d32 =
39454 +                                   DWC_READ_REG32(&core_if->core_global_regs->
39455 +                                                  gusbcfg);
39456 +                               if (gusbcfg.b.ulpi_utmi_sel == 1) {
39457 +                                       /* ULPI interface */
39458 +                                       /* Suspend the Phy Clock */
39459 +                                       pcgcctl.d32 = 0;
39460 +                                       pcgcctl.b.stoppclk = 1;
39461 +                                       DWC_MODIFY_REG32(core_if->pcgcctl, 0,
39462 +                                                        pcgcctl.d32);
39463 +                                       dwc_udelay(10);
39464 +                                       gpwrdn.b.pmuactv = 1;
39465 +                                       DWC_MODIFY_REG32(&core_if->
39466 +                                                        core_global_regs->
39467 +                                                        gpwrdn, 0, gpwrdn.d32);
39468 +                               } else {
39469 +                                       /* UTMI+ Interface */
39470 +                                       gpwrdn.b.pmuactv = 1;
39471 +                                       DWC_MODIFY_REG32(&core_if->
39472 +                                                        core_global_regs->
39473 +                                                        gpwrdn, 0, gpwrdn.d32);
39474 +                                       dwc_udelay(10);
39475 +                                       pcgcctl.b.stoppclk = 1;
39476 +                                       DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
39477 +                                       dwc_udelay(10);
39478 +                               }
39479 +#ifdef DWC_DEV_SRPCAP
39480 +                               gpwrdn.d32 = 0;
39481 +                               gpwrdn.b.dis_vbus = 1;
39482 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
39483 +                                                gpwrdn, 0, gpwrdn.d32);
39484 +#endif
39485 +                               gpwrdn.d32 = 0;
39486 +                               gpwrdn.b.pmuintsel = 1;
39487 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
39488 +                                                gpwrdn, 0, gpwrdn.d32);
39489 +                               dwc_udelay(10);
39490 +
39491 +                               gpwrdn.d32 = 0;
39492 +#ifdef DWC_DEV_SRPCAP
39493 +                               gpwrdn.b.srp_det_msk = 1;
39494 +#endif
39495 +                               gpwrdn.b.disconn_det_msk = 1;
39496 +                               gpwrdn.b.lnstchng_msk = 1;
39497 +                               gpwrdn.b.sts_chngint_msk = 1;
39498 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
39499 +                                                gpwrdn, 0, gpwrdn.d32);
39500 +                               dwc_udelay(10);
39501 +
39502 +                               /* Enable Power Down Clamp and all interrupts in GPWRDN */
39503 +                               gpwrdn.d32 = 0;
39504 +                               gpwrdn.b.pwrdnclmp = 1;
39505 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
39506 +                                                gpwrdn, 0, gpwrdn.d32);
39507 +                               dwc_udelay(10);
39508 +
39509 +                               /* Switch off VDD */
39510 +                               gpwrdn.d32 = 0;
39511 +                               gpwrdn.b.pwrdnswtch = 1;
39512 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
39513 +                                                gpwrdn, 0, gpwrdn.d32);
39514 +
39515 +#ifdef DWC_DEV_SRPCAP
39516 +                               if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
39517 +                               {
39518 +                                       core_if->pwron_timer_started = 1;
39519 +                                       DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
39520 +                               }
39521 +#endif
39522 +                               /* Save gpwrdn register for further usage if stschng interrupt */
39523 +                               core_if->gr_backup->gpwrdn_local =
39524 +                                               DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
39525 +
39526 +                               /* Set flag to indicate that we are in hibernation */
39527 +                               core_if->hibernation_suspend = 1;
39528 +                               DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
39529 +
39530 +                               DWC_PRINTF("Host hibernation completed\n");
39531 +                               // Exit from case statement
39532 +                               break;
39533 +
39534 +                       }
39535 +                       if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
39536 +                           dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
39537 +                               gotgctl_data_t gotgctl = {.d32 = 0 };
39538 +                               gotgctl.b.hstsethnpen = 1;
39539 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
39540 +                                                gotgctl, 0, gotgctl.d32);
39541 +                               core_if->op_state = A_SUSPEND;
39542 +                       }
39543 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
39544 +                       hprt0.b.prtsusp = 1;
39545 +                       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39546 +                       {
39547 +                               dwc_irqflags_t flags;
39548 +                               /* Update lx_state */
39549 +                               DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
39550 +                               core_if->lx_state = DWC_OTG_L2;
39551 +                               DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
39552 +                       }
39553 +                       /* Suspend the Phy Clock */
39554 +                       {
39555 +                               pcgcctl_data_t pcgcctl = {.d32 = 0 };
39556 +                               pcgcctl.b.stoppclk = 1;
39557 +                               DWC_MODIFY_REG32(core_if->pcgcctl, 0,
39558 +                                                pcgcctl.d32);
39559 +                               dwc_udelay(10);
39560 +                       }
39561 +
39562 +                       /* For HNP the bus must be suspended for at least 200ms. */
39563 +                       if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
39564 +                               pcgcctl_data_t pcgcctl = {.d32 = 0 };
39565 +                               pcgcctl.b.stoppclk = 1;
39566 +                DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
39567 +                               dwc_mdelay(200);
39568 +                       }
39569 +
39570 +                       /** @todo - check how sw can wait for 1 sec to check asesvld??? */
39571 +#if 0 //vahrama !!!!!!!!!!!!!!!!!!
39572 +                       if (core_if->adp_enable) {
39573 +                               gotgctl_data_t gotgctl = {.d32 = 0 };
39574 +                               gpwrdn_data_t gpwrdn;
39575 +
39576 +                               while (gotgctl.b.asesvld == 1) {
39577 +                                       gotgctl.d32 =
39578 +                                           DWC_READ_REG32(&core_if->
39579 +                                                          core_global_regs->
39580 +                                                          gotgctl);
39581 +                                       dwc_mdelay(100);
39582 +                               }
39583 +
39584 +                               /* Enable Power Down Logic */
39585 +                               gpwrdn.d32 = 0;
39586 +                               gpwrdn.b.pmuactv = 1;
39587 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
39588 +                                                gpwrdn, 0, gpwrdn.d32);
39589 +
39590 +                               /* Unmask SRP detected interrupt from Power Down Logic */
39591 +                               gpwrdn.d32 = 0;
39592 +                               gpwrdn.b.srp_det_msk = 1;
39593 +                               DWC_MODIFY_REG32(&core_if->core_global_regs->
39594 +                                                gpwrdn, 0, gpwrdn.d32);
39595 +
39596 +                               dwc_otg_adp_probe_start(core_if);
39597 +                       }
39598 +#endif
39599 +                       break;
39600 +               case UHF_PORT_POWER:
39601 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39602 +                                   "SetPortFeature - USB_PORT_FEAT_POWER\n");
39603 +                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
39604 +                       hprt0.b.prtpwr = 1;
39605 +                       DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39606 +                       break;
39607 +               case UHF_PORT_RESET:
39608 +                       if ((core_if->power_down == 2)
39609 +                           && (core_if->hibernation_suspend == 1)) {
39610 +                               /* If we are going to exit from Hibernated
39611 +                                * state via USB RESET.
39612 +                                */
39613 +                               dwc_otg_host_hibernation_restore(core_if, 0, 1);
39614 +                       } else {
39615 +                               hprt0.d32 = dwc_otg_read_hprt0(core_if);
39616 +
39617 +                               DWC_DEBUGPL(DBG_HCD,
39618 +                                           "DWC OTG HCD HUB CONTROL - "
39619 +                                           "SetPortFeature - USB_PORT_FEAT_RESET\n");
39620 +                               {
39621 +                                       pcgcctl_data_t pcgcctl = {.d32 = 0 };
39622 +                                       pcgcctl.b.enbl_sleep_gating = 1;
39623 +                                       pcgcctl.b.stoppclk = 1;
39624 +                                       DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
39625 +                                       DWC_WRITE_REG32(core_if->pcgcctl, 0);
39626 +                               }
39627 +#ifdef CONFIG_USB_DWC_OTG_LPM
39628 +                               {
39629 +                                       glpmcfg_data_t lpmcfg;
39630 +                                       lpmcfg.d32 =
39631 +                                               DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
39632 +                                       if (lpmcfg.b.prt_sleep_sts) {
39633 +                                               lpmcfg.b.en_utmi_sleep = 0;
39634 +                                               lpmcfg.b.hird_thres &= (~(1 << 4));
39635 +                                               DWC_WRITE_REG32
39636 +                                                   (&core_if->core_global_regs->glpmcfg,
39637 +                                                    lpmcfg.d32);
39638 +                                               dwc_mdelay(1);
39639 +                                       }
39640 +                               }
39641 +#endif
39642 +                               hprt0.d32 = dwc_otg_read_hprt0(core_if);
39643 +                               /* Clear suspend bit if resetting from suspended state. */
39644 +                               hprt0.b.prtsusp = 0;
39645 +                               /* When B-Host the Port reset bit is set in
39646 +                                * the Start HCD Callback function, so that
39647 +                                * the reset is started within 1ms of the HNP
39648 +                                * success interrupt. */
39649 +                               if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
39650 +                                       hprt0.b.prtpwr = 1;
39651 +                                       hprt0.b.prtrst = 1;
39652 +                                       DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
39653 +                                       DWC_WRITE_REG32(core_if->host_if->hprt0,
39654 +                                                       hprt0.d32);
39655 +                               }
39656 +                               /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
39657 +                               dwc_mdelay(60);
39658 +                               hprt0.b.prtrst = 0;
39659 +                               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39660 +                               core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
39661 +                       }
39662 +                       break;
39663 +#ifdef DWC_HS_ELECT_TST
39664 +               case UHF_PORT_TEST:
39665 +                       {
39666 +                               uint32_t t;
39667 +                               gintmsk_data_t gintmsk;
39668 +
39669 +                               t = (wIndex >> 8);      /* MSB wIndex USB */
39670 +                               DWC_DEBUGPL(DBG_HCD,
39671 +                                           "DWC OTG HCD HUB CONTROL - "
39672 +                                           "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
39673 +                                           t);
39674 +                               DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
39675 +                               if (t < 6) {
39676 +                                       hprt0.d32 = dwc_otg_read_hprt0(core_if);
39677 +                                       hprt0.b.prttstctl = t;
39678 +                                       DWC_WRITE_REG32(core_if->host_if->hprt0,
39679 +                                                       hprt0.d32);
39680 +                               } else {
39681 +                                       /* Setup global vars with reg addresses (quick and
39682 +                                        * dirty hack, should be cleaned up)
39683 +                                        */
39684 +                                       global_regs = core_if->core_global_regs;
39685 +                                       hc_global_regs =
39686 +                                           core_if->host_if->host_global_regs;
39687 +                                       hc_regs =
39688 +                                           (dwc_otg_hc_regs_t *) ((char *)
39689 +                                                                  global_regs +
39690 +                                                                  0x500);
39691 +                                       data_fifo =
39692 +                                           (uint32_t *) ((char *)global_regs +
39693 +                                                         0x1000);
39694 +
39695 +                                       if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
39696 +                                               /* Save current interrupt mask */
39697 +                                               gintmsk.d32 =
39698 +                                                   DWC_READ_REG32
39699 +                                                   (&global_regs->gintmsk);
39700 +
39701 +                                               /* Disable all interrupts while we muck with
39702 +                                                * the hardware directly
39703 +                                                */
39704 +                                               DWC_WRITE_REG32(&global_regs->gintmsk, 0);
39705 +
39706 +                                               /* 15 second delay per the test spec */
39707 +                                               dwc_mdelay(15000);
39708 +
39709 +                                               /* Drive suspend on the root port */
39710 +                                               hprt0.d32 =
39711 +                                                   dwc_otg_read_hprt0(core_if);
39712 +                                               hprt0.b.prtsusp = 1;
39713 +                                               hprt0.b.prtres = 0;
39714 +                                               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39715 +
39716 +                                               /* 15 second delay per the test spec */
39717 +                                               dwc_mdelay(15000);
39718 +
39719 +                                               /* Drive resume on the root port */
39720 +                                               hprt0.d32 =
39721 +                                                   dwc_otg_read_hprt0(core_if);
39722 +                                               hprt0.b.prtsusp = 0;
39723 +                                               hprt0.b.prtres = 1;
39724 +                                               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39725 +                                               dwc_mdelay(100);
39726 +
39727 +                                               /* Clear the resume bit */
39728 +                                               hprt0.b.prtres = 0;
39729 +                                               DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
39730 +
39731 +                                               /* Restore interrupts */
39732 +                                               DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
39733 +                                       } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
39734 +                                               /* Save current interrupt mask */
39735 +                                               gintmsk.d32 =
39736 +                                                   DWC_READ_REG32
39737 +                                                   (&global_regs->gintmsk);
39738 +
39739 +                                               /* Disable all interrupts while we muck with
39740 +                                                * the hardware directly
39741 +                                                */
39742 +                                               DWC_WRITE_REG32(&global_regs->gintmsk, 0);
39743 +
39744 +                                               /* 15 second delay per the test spec */
39745 +                                               dwc_mdelay(15000);
39746 +
39747 +                                               /* Send the Setup packet */
39748 +                                               do_setup();
39749 +
39750 +                                               /* 15 second delay so nothing else happens for awhile */
39751 +                                               dwc_mdelay(15000);
39752 +
39753 +                                               /* Restore interrupts */
39754 +                                               DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
39755 +                                       } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
39756 +                                               /* Save current interrupt mask */
39757 +                                               gintmsk.d32 =
39758 +                                                   DWC_READ_REG32
39759 +                                                   (&global_regs->gintmsk);
39760 +
39761 +                                               /* Disable all interrupts while we muck with
39762 +                                                * the hardware directly
39763 +                                                */
39764 +                                               DWC_WRITE_REG32(&global_regs->gintmsk, 0);
39765 +
39766 +                                               /* Send the Setup packet */
39767 +                                               do_setup();
39768 +
39769 +                                               /* 15 second delay so nothing else happens for awhile */
39770 +                                               dwc_mdelay(15000);
39771 +
39772 +                                               /* Send the In and Ack packets */
39773 +                                               do_in_ack();
39774 +
39775 +                                               /* 15 second delay so nothing else happens for awhile */
39776 +                                               dwc_mdelay(15000);
39777 +
39778 +                                               /* Restore interrupts */
39779 +                                               DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
39780 +                                       }
39781 +                               }
39782 +                               break;
39783 +                       }
39784 +#endif /* DWC_HS_ELECT_TST */
39785 +
39786 +               case UHF_PORT_INDICATOR:
39787 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
39788 +                                   "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
39789 +                       /* Not supported */
39790 +                       break;
39791 +               default:
39792 +                       retval = -DWC_E_INVALID;
39793 +                       DWC_ERROR("DWC OTG HCD - "
39794 +                                 "SetPortFeature request %xh "
39795 +                                 "unknown or unsupported\n", wValue);
39796 +                       break;
39797 +               }
39798 +               break;
39799 +#ifdef CONFIG_USB_DWC_OTG_LPM
39800 +       case UCR_SET_AND_TEST_PORT_FEATURE:
39801 +               if (wValue != UHF_PORT_L1) {
39802 +                       goto error;
39803 +               }
39804 +               {
39805 +                       int portnum, hird, devaddr, remwake;
39806 +                       glpmcfg_data_t lpmcfg;
39807 +                       uint32_t time_usecs;
39808 +                       gintsts_data_t gintsts;
39809 +                       gintmsk_data_t gintmsk;
39810 +
39811 +                       if (!dwc_otg_get_param_lpm_enable(core_if)) {
39812 +                               goto error;
39813 +                       }
39814 +                       if (wValue != UHF_PORT_L1 || wLength != 1) {
39815 +                               goto error;
39816 +                       }
39817 +                       /* Check if the port currently is in SLEEP state */
39818 +                       lpmcfg.d32 =
39819 +                           DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
39820 +                       if (lpmcfg.b.prt_sleep_sts) {
39821 +                               DWC_INFO("Port is already in sleep mode\n");
39822 +                               buf[0] = 0;     /* Return success */
39823 +                               break;
39824 +                       }
39825 +
39826 +                       portnum = wIndex & 0xf;
39827 +                       hird = (wIndex >> 4) & 0xf;
39828 +                       devaddr = (wIndex >> 8) & 0x7f;
39829 +                       remwake = (wIndex >> 15);
39830 +
39831 +                       if (portnum != 1) {
39832 +                               retval = -DWC_E_INVALID;
39833 +                               DWC_WARN
39834 +                                   ("Wrong port number(%d) in SetandTestPortFeature request\n",
39835 +                                    portnum);
39836 +                               break;
39837 +                       }
39838 +
39839 +                       DWC_PRINTF
39840 +                           ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
39841 +                            portnum, hird, devaddr, remwake);
39842 +                       /* Disable LPM interrupt */
39843 +                       gintmsk.d32 = 0;
39844 +                       gintmsk.b.lpmtranrcvd = 1;
39845 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
39846 +                                        gintmsk.d32, 0);
39847 +
39848 +                       if (dwc_otg_hcd_send_lpm
39849 +                           (dwc_otg_hcd, devaddr, hird, remwake)) {
39850 +                               retval = -DWC_E_INVALID;
39851 +                               break;
39852 +                       }
39853 +
39854 +                       time_usecs = 10 * (lpmcfg.b.retry_count + 1);
39855 +                       /* We will consider timeout if time_usecs microseconds pass,
39856 +                        * and we don't receive LPM transaction status.
39857 +                        * After receiving non-error responce(ACK/NYET/STALL) from device,
39858 +                        *  core will set lpmtranrcvd bit.
39859 +                        */
39860 +                       do {
39861 +                               gintsts.d32 =
39862 +                                   DWC_READ_REG32(&core_if->core_global_regs->gintsts);
39863 +                               if (gintsts.b.lpmtranrcvd) {
39864 +                                       break;
39865 +                               }
39866 +                               dwc_udelay(1);
39867 +                       } while (--time_usecs);
39868 +                       /* lpm_int bit will be cleared in LPM interrupt handler */
39869 +
39870 +                       /* Now fill status
39871 +                        * 0x00 - Success
39872 +                        * 0x10 - NYET
39873 +                        * 0x11 - Timeout
39874 +                        */
39875 +                       if (!gintsts.b.lpmtranrcvd) {
39876 +                               buf[0] = 0x3;   /* Completion code is Timeout */
39877 +                               dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
39878 +                       } else {
39879 +                               lpmcfg.d32 =
39880 +                                   DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
39881 +                               if (lpmcfg.b.lpm_resp == 0x3) {
39882 +                                       /* ACK responce from the device */
39883 +                                       buf[0] = 0x00;  /* Success */
39884 +                               } else if (lpmcfg.b.lpm_resp == 0x2) {
39885 +                                       /* NYET responce from the device */
39886 +                                       buf[0] = 0x2;
39887 +                               } else {
39888 +                                       /* Otherwise responce with Timeout */
39889 +                                       buf[0] = 0x3;
39890 +                               }
39891 +                       }
39892 +                       DWC_PRINTF("Device responce to LPM trans is %x\n",
39893 +                                  lpmcfg.b.lpm_resp);
39894 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
39895 +                                        gintmsk.d32);
39896 +
39897 +                       break;
39898 +               }
39899 +#endif /* CONFIG_USB_DWC_OTG_LPM */
39900 +       default:
39901 +error:
39902 +               retval = -DWC_E_INVALID;
39903 +               DWC_WARN("DWC OTG HCD - "
39904 +                        "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
39905 +                        typeReq, wIndex, wValue);
39906 +               break;
39907 +       }
39908 +
39909 +       return retval;
39910 +}
39911 +
39912 +#ifdef CONFIG_USB_DWC_OTG_LPM
39913 +/** Returns index of host channel to perform LPM transaction. */
39914 +int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
39915 +{
39916 +       dwc_otg_core_if_t *core_if = hcd->core_if;
39917 +       dwc_hc_t *hc;
39918 +       hcchar_data_t hcchar;
39919 +       gintmsk_data_t gintmsk = {.d32 = 0 };
39920 +
39921 +       if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
39922 +               DWC_PRINTF("No free channel to select for LPM transaction\n");
39923 +               return -1;
39924 +       }
39925 +
39926 +       hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
39927 +
39928 +       /* Mask host channel interrupts. */
39929 +       gintmsk.b.hcintr = 1;
39930 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
39931 +
39932 +       /* Fill fields that core needs for LPM transaction */
39933 +       hcchar.b.devaddr = devaddr;
39934 +       hcchar.b.epnum = 0;
39935 +       hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
39936 +       hcchar.b.mps = 64;
39937 +       hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
39938 +       hcchar.b.epdir = 0;     /* OUT */
39939 +       DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
39940 +                       hcchar.d32);
39941 +
39942 +       /* Remove the host channel from the free list. */
39943 +       DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
39944 +
39945 +       DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
39946 +
39947 +       return hc->hc_num;
39948 +}
39949 +
39950 +/** Release hc after performing LPM transaction */
39951 +void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
39952 +{
39953 +       dwc_hc_t *hc;
39954 +       glpmcfg_data_t lpmcfg;
39955 +       uint8_t hc_num;
39956 +
39957 +       lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
39958 +       hc_num = lpmcfg.b.lpm_chan_index;
39959 +
39960 +       hc = hcd->hc_ptr_array[hc_num];
39961 +
39962 +       DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
39963 +       /* Return host channel to free list */
39964 +       DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
39965 +}
39966 +
39967 +int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
39968 +                        uint8_t bRemoteWake)
39969 +{
39970 +       glpmcfg_data_t lpmcfg;
39971 +       pcgcctl_data_t pcgcctl = {.d32 = 0 };
39972 +       int channel;
39973 +
39974 +       channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
39975 +       if (channel < 0) {
39976 +               return channel;
39977 +       }
39978 +
39979 +       pcgcctl.b.enbl_sleep_gating = 1;
39980 +       DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
39981 +
39982 +       /* Read LPM config register */
39983 +       lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
39984 +
39985 +       /* Program LPM transaction fields */
39986 +       lpmcfg.b.rem_wkup_en = bRemoteWake;
39987 +       lpmcfg.b.hird = hird;
39988 +       lpmcfg.b.hird_thres = 0x1c;
39989 +       lpmcfg.b.lpm_chan_index = channel;
39990 +       lpmcfg.b.en_utmi_sleep = 1;
39991 +       /* Program LPM config register */
39992 +       DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
39993 +
39994 +       /* Send LPM transaction */
39995 +       lpmcfg.b.send_lpm = 1;
39996 +       DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
39997 +
39998 +       return 0;
39999 +}
40000 +
40001 +#endif /* CONFIG_USB_DWC_OTG_LPM */
40002 +
40003 +int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
40004 +{
40005 +       int retval;
40006 +
40007 +       if (port != 1) {
40008 +               return -DWC_E_INVALID;
40009 +       }
40010 +
40011 +       retval = (hcd->flags.b.port_connect_status_change ||
40012 +                 hcd->flags.b.port_reset_change ||
40013 +                 hcd->flags.b.port_enable_change ||
40014 +                 hcd->flags.b.port_suspend_change ||
40015 +                 hcd->flags.b.port_over_current_change);
40016 +#ifdef DEBUG
40017 +       if (retval) {
40018 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
40019 +                           " Root port status changed\n");
40020 +               DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
40021 +                           hcd->flags.b.port_connect_status_change);
40022 +               DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
40023 +                           hcd->flags.b.port_reset_change);
40024 +               DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
40025 +                           hcd->flags.b.port_enable_change);
40026 +               DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
40027 +                           hcd->flags.b.port_suspend_change);
40028 +               DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
40029 +                           hcd->flags.b.port_over_current_change);
40030 +       }
40031 +#endif
40032 +       return retval;
40033 +}
40034 +
40035 +int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
40036 +{
40037 +       hfnum_data_t hfnum;
40038 +       hfnum.d32 =
40039 +           DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
40040 +                          hfnum);
40041 +
40042 +#ifdef DEBUG_SOF
40043 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
40044 +                   hfnum.b.frnum);
40045 +#endif
40046 +       return hfnum.b.frnum;
40047 +}
40048 +
40049 +int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
40050 +                     struct dwc_otg_hcd_function_ops *fops)
40051 +{
40052 +       int retval = 0;
40053 +
40054 +       hcd->fops = fops;
40055 +       if (!dwc_otg_is_device_mode(hcd->core_if) &&
40056 +               (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
40057 +               dwc_otg_hcd_reinit(hcd);
40058 +       } else {
40059 +               retval = -DWC_E_NO_DEVICE;
40060 +       }
40061 +
40062 +       return retval;
40063 +}
40064 +
40065 +void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
40066 +{
40067 +       return hcd->priv;
40068 +}
40069 +
40070 +void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
40071 +{
40072 +       hcd->priv = priv_data;
40073 +}
40074 +
40075 +uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
40076 +{
40077 +       return hcd->otg_port;
40078 +}
40079 +
40080 +uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
40081 +{
40082 +       uint32_t is_b_host;
40083 +       if (hcd->core_if->op_state == B_HOST) {
40084 +               is_b_host = 1;
40085 +       } else {
40086 +               is_b_host = 0;
40087 +       }
40088 +
40089 +       return is_b_host;
40090 +}
40091 +
40092 +dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
40093 +                                        int iso_desc_count, int atomic_alloc)
40094 +{
40095 +       dwc_otg_hcd_urb_t *dwc_otg_urb;
40096 +       uint32_t size;
40097 +
40098 +       size =
40099 +           sizeof(*dwc_otg_urb) +
40100 +           iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
40101 +       if (atomic_alloc)
40102 +               dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
40103 +       else
40104 +               dwc_otg_urb = DWC_ALLOC(size);
40105 +
40106 +        if (dwc_otg_urb)
40107 +               dwc_otg_urb->packet_count = iso_desc_count;
40108 +        else {
40109 +               DWC_ERROR("**** DWC OTG HCD URB alloc - "
40110 +                       "%salloc of %db failed\n",
40111 +                       atomic_alloc?"atomic ":"", size);
40112 +       }
40113 +       return dwc_otg_urb;
40114 +}
40115 +
40116 +void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
40117 +                                 uint8_t dev_addr, uint8_t ep_num,
40118 +                                 uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
40119 +{
40120 +       dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
40121 +                             ep_type, ep_dir, mps);
40122 +#if 0
40123 +       DWC_PRINTF
40124 +           ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
40125 +            dev_addr, ep_num, ep_dir, ep_type, mps);
40126 +#endif
40127 +}
40128 +
40129 +void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
40130 +                               void *urb_handle, void *buf, dwc_dma_t dma,
40131 +                               uint32_t buflen, void *setup_packet,
40132 +                               dwc_dma_t setup_dma, uint32_t flags,
40133 +                               uint16_t interval)
40134 +{
40135 +       dwc_otg_urb->priv = urb_handle;
40136 +       dwc_otg_urb->buf = buf;
40137 +       dwc_otg_urb->dma = dma;
40138 +       dwc_otg_urb->length = buflen;
40139 +       dwc_otg_urb->setup_packet = setup_packet;
40140 +       dwc_otg_urb->setup_dma = setup_dma;
40141 +       dwc_otg_urb->flags = flags;
40142 +       dwc_otg_urb->interval = interval;
40143 +       dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
40144 +}
40145 +
40146 +uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
40147 +{
40148 +       return dwc_otg_urb->status;
40149 +}
40150 +
40151 +uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
40152 +{
40153 +       return dwc_otg_urb->actual_length;
40154 +}
40155 +
40156 +uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
40157 +{
40158 +       return dwc_otg_urb->error_count;
40159 +}
40160 +
40161 +void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
40162 +                                        int desc_num, uint32_t offset,
40163 +                                        uint32_t length)
40164 +{
40165 +       dwc_otg_urb->iso_descs[desc_num].offset = offset;
40166 +       dwc_otg_urb->iso_descs[desc_num].length = length;
40167 +}
40168 +
40169 +uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
40170 +                                            int desc_num)
40171 +{
40172 +       return dwc_otg_urb->iso_descs[desc_num].status;
40173 +}
40174 +
40175 +uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
40176 +                                                   dwc_otg_urb, int desc_num)
40177 +{
40178 +       return dwc_otg_urb->iso_descs[desc_num].actual_length;
40179 +}
40180 +
40181 +int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
40182 +{
40183 +       int allocated = 0;
40184 +       dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40185 +
40186 +       if (qh) {
40187 +               if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
40188 +                       allocated = 1;
40189 +               }
40190 +       }
40191 +       return allocated;
40192 +}
40193 +
40194 +int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
40195 +{
40196 +       dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40197 +       int freed = 0;
40198 +       DWC_ASSERT(qh, "qh is not allocated\n");
40199 +
40200 +       if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
40201 +               freed = 1;
40202 +       }
40203 +
40204 +       return freed;
40205 +}
40206 +
40207 +uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
40208 +{
40209 +       dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
40210 +       DWC_ASSERT(qh, "qh is not allocated\n");
40211 +       return qh->usecs;
40212 +}
40213 +
40214 +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
40215 +{
40216 +#ifdef DEBUG
40217 +       int num_channels;
40218 +       int i;
40219 +       gnptxsts_data_t np_tx_status;
40220 +       hptxsts_data_t p_tx_status;
40221 +
40222 +       num_channels = hcd->core_if->core_params->host_channels;
40223 +       DWC_PRINTF("\n");
40224 +       DWC_PRINTF
40225 +           ("************************************************************\n");
40226 +       DWC_PRINTF("HCD State:\n");
40227 +       DWC_PRINTF("  Num channels: %d\n", num_channels);
40228 +       for (i = 0; i < num_channels; i++) {
40229 +               dwc_hc_t *hc = hcd->hc_ptr_array[i];
40230 +               DWC_PRINTF("  Channel %d:\n", i);
40231 +               DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
40232 +                          hc->dev_addr, hc->ep_num, hc->ep_is_in);
40233 +               DWC_PRINTF("    speed: %d\n", hc->speed);
40234 +               DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
40235 +               DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
40236 +               DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
40237 +               DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
40238 +               DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
40239 +               DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
40240 +               DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
40241 +               DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
40242 +               DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
40243 +               DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
40244 +               DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
40245 +               DWC_PRINTF("    do_split: %d\n", hc->do_split);
40246 +               DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
40247 +               DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
40248 +               DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
40249 +               DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
40250 +               DWC_PRINTF("    requests: %d\n", hc->requests);
40251 +               DWC_PRINTF("    qh: %p\n", hc->qh);
40252 +               if (hc->xfer_started) {
40253 +                       hfnum_data_t hfnum;
40254 +                       hcchar_data_t hcchar;
40255 +                       hctsiz_data_t hctsiz;
40256 +                       hcint_data_t hcint;
40257 +                       hcintmsk_data_t hcintmsk;
40258 +                       hfnum.d32 =
40259 +                           DWC_READ_REG32(&hcd->core_if->
40260 +                                          host_if->host_global_regs->hfnum);
40261 +                       hcchar.d32 =
40262 +                           DWC_READ_REG32(&hcd->core_if->host_if->
40263 +                                          hc_regs[i]->hcchar);
40264 +                       hctsiz.d32 =
40265 +                           DWC_READ_REG32(&hcd->core_if->host_if->
40266 +                                          hc_regs[i]->hctsiz);
40267 +                       hcint.d32 =
40268 +                           DWC_READ_REG32(&hcd->core_if->host_if->
40269 +                                          hc_regs[i]->hcint);
40270 +                       hcintmsk.d32 =
40271 +                           DWC_READ_REG32(&hcd->core_if->host_if->
40272 +                                          hc_regs[i]->hcintmsk);
40273 +                       DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
40274 +                       DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
40275 +                       DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
40276 +                       DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
40277 +                       DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
40278 +               }
40279 +               if (hc->xfer_started && hc->qh) {
40280 +                       dwc_otg_qtd_t *qtd;
40281 +                       dwc_otg_hcd_urb_t *urb;
40282 +
40283 +                       DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
40284 +                               if (!qtd->in_process)
40285 +                                       break;
40286 +
40287 +                               urb = qtd->urb;
40288 +                       DWC_PRINTF("    URB Info:\n");
40289 +                       DWC_PRINTF("      qtd: %p, urb: %p\n", qtd, urb);
40290 +                       if (urb) {
40291 +                               DWC_PRINTF("      Dev: %d, EP: %d %s\n",
40292 +                                          dwc_otg_hcd_get_dev_addr(&urb->
40293 +                                                                   pipe_info),
40294 +                                          dwc_otg_hcd_get_ep_num(&urb->
40295 +                                                                 pipe_info),
40296 +                                          dwc_otg_hcd_is_pipe_in(&urb->
40297 +                                                                 pipe_info) ?
40298 +                                          "IN" : "OUT");
40299 +                               DWC_PRINTF("      Max packet size: %d\n",
40300 +                                          dwc_otg_hcd_get_mps(&urb->
40301 +                                                              pipe_info));
40302 +                               DWC_PRINTF("      transfer_buffer: %p\n",
40303 +                                          urb->buf);
40304 +                               DWC_PRINTF("      transfer_dma: %p\n",
40305 +                                          (void *)urb->dma);
40306 +                               DWC_PRINTF("      transfer_buffer_length: %d\n",
40307 +                                          urb->length);
40308 +                                       DWC_PRINTF("      actual_length: %d\n",
40309 +                                                  urb->actual_length);
40310 +                               }
40311 +                       }
40312 +               }
40313 +       }
40314 +       DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
40315 +       DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
40316 +       DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
40317 +       np_tx_status.d32 =
40318 +           DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
40319 +       DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
40320 +                  np_tx_status.b.nptxqspcavail);
40321 +       DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
40322 +                  np_tx_status.b.nptxfspcavail);
40323 +       p_tx_status.d32 =
40324 +           DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
40325 +       DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
40326 +                  p_tx_status.b.ptxqspcavail);
40327 +       DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
40328 +       dwc_otg_hcd_dump_frrem(hcd);
40329 +       dwc_otg_dump_global_registers(hcd->core_if);
40330 +       dwc_otg_dump_host_registers(hcd->core_if);
40331 +       DWC_PRINTF
40332 +           ("************************************************************\n");
40333 +       DWC_PRINTF("\n");
40334 +#endif
40335 +}
40336 +
40337 +#ifdef DEBUG
40338 +void dwc_print_setup_data(uint8_t * setup)
40339 +{
40340 +       int i;
40341 +       if (CHK_DEBUG_LEVEL(DBG_HCD)) {
40342 +               DWC_PRINTF("Setup Data = MSB ");
40343 +               for (i = 7; i >= 0; i--)
40344 +                       DWC_PRINTF("%02x ", setup[i]);
40345 +               DWC_PRINTF("\n");
40346 +               DWC_PRINTF("  bmRequestType Tranfer = %s\n",
40347 +                          (setup[0] & 0x80) ? "Device-to-Host" :
40348 +                          "Host-to-Device");
40349 +               DWC_PRINTF("  bmRequestType Type = ");
40350 +               switch ((setup[0] & 0x60) >> 5) {
40351 +               case 0:
40352 +                       DWC_PRINTF("Standard\n");
40353 +                       break;
40354 +               case 1:
40355 +                       DWC_PRINTF("Class\n");
40356 +                       break;
40357 +               case 2:
40358 +                       DWC_PRINTF("Vendor\n");
40359 +                       break;
40360 +               case 3:
40361 +                       DWC_PRINTF("Reserved\n");
40362 +                       break;
40363 +               }
40364 +               DWC_PRINTF("  bmRequestType Recipient = ");
40365 +               switch (setup[0] & 0x1f) {
40366 +               case 0:
40367 +                       DWC_PRINTF("Device\n");
40368 +                       break;
40369 +               case 1:
40370 +                       DWC_PRINTF("Interface\n");
40371 +                       break;
40372 +               case 2:
40373 +                       DWC_PRINTF("Endpoint\n");
40374 +                       break;
40375 +               case 3:
40376 +                       DWC_PRINTF("Other\n");
40377 +                       break;
40378 +               default:
40379 +                       DWC_PRINTF("Reserved\n");
40380 +                       break;
40381 +               }
40382 +               DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
40383 +               DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
40384 +               DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
40385 +               DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
40386 +       }
40387 +}
40388 +#endif
40389 +
40390 +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
40391 +{
40392 +#if 0
40393 +       DWC_PRINTF("Frame remaining at SOF:\n");
40394 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40395 +                  hcd->frrem_samples, hcd->frrem_accum,
40396 +                  (hcd->frrem_samples > 0) ?
40397 +                  hcd->frrem_accum / hcd->frrem_samples : 0);
40398 +
40399 +       DWC_PRINTF("\n");
40400 +       DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
40401 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40402 +                  hcd->core_if->hfnum_7_samples,
40403 +                  hcd->core_if->hfnum_7_frrem_accum,
40404 +                  (hcd->core_if->hfnum_7_samples >
40405 +                   0) ? hcd->core_if->hfnum_7_frrem_accum /
40406 +                  hcd->core_if->hfnum_7_samples : 0);
40407 +       DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
40408 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40409 +                  hcd->core_if->hfnum_0_samples,
40410 +                  hcd->core_if->hfnum_0_frrem_accum,
40411 +                  (hcd->core_if->hfnum_0_samples >
40412 +                   0) ? hcd->core_if->hfnum_0_frrem_accum /
40413 +                  hcd->core_if->hfnum_0_samples : 0);
40414 +       DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
40415 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40416 +                  hcd->core_if->hfnum_other_samples,
40417 +                  hcd->core_if->hfnum_other_frrem_accum,
40418 +                  (hcd->core_if->hfnum_other_samples >
40419 +                   0) ? hcd->core_if->hfnum_other_frrem_accum /
40420 +                  hcd->core_if->hfnum_other_samples : 0);
40421 +
40422 +       DWC_PRINTF("\n");
40423 +       DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
40424 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40425 +                  hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
40426 +                  (hcd->hfnum_7_samples_a > 0) ?
40427 +                  hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
40428 +       DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
40429 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40430 +                  hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
40431 +                  (hcd->hfnum_0_samples_a > 0) ?
40432 +                  hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
40433 +       DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
40434 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40435 +                  hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
40436 +                  (hcd->hfnum_other_samples_a > 0) ?
40437 +                  hcd->hfnum_other_frrem_accum_a /
40438 +                  hcd->hfnum_other_samples_a : 0);
40439 +
40440 +       DWC_PRINTF("\n");
40441 +       DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
40442 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40443 +                  hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
40444 +                  (hcd->hfnum_7_samples_b > 0) ?
40445 +                  hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
40446 +       DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
40447 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40448 +                  hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
40449 +                  (hcd->hfnum_0_samples_b > 0) ?
40450 +                  hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
40451 +       DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
40452 +       DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
40453 +                  hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
40454 +                  (hcd->hfnum_other_samples_b > 0) ?
40455 +                  hcd->hfnum_other_frrem_accum_b /
40456 +                  hcd->hfnum_other_samples_b : 0);
40457 +#endif
40458 +}
40459 +
40460 +#endif /* DWC_DEVICE_ONLY */
40461 --- /dev/null
40462 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.h
40463 @@ -0,0 +1,862 @@
40464 +/* ==========================================================================
40465 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
40466 + * $Revision: #58 $
40467 + * $Date: 2011/09/15 $
40468 + * $Change: 1846647 $
40469 + *
40470 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
40471 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
40472 + * otherwise expressly agreed to in writing between Synopsys and you.
40473 + *
40474 + * The Software IS NOT an item of Licensed Software or Licensed Product under
40475 + * any End User Software License Agreement or Agreement for Licensed Product
40476 + * with Synopsys or any supplement thereto. You are permitted to use and
40477 + * redistribute this Software in source and binary forms, with or without
40478 + * modification, provided that redistributions of source code must retain this
40479 + * notice. You may not view, use, disclose, copy or distribute this file or
40480 + * any information contained herein except pursuant to this license grant from
40481 + * Synopsys. If you do not agree with this notice, including the disclaimer
40482 + * below, then you are not authorized to use the Software.
40483 + *
40484 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
40485 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40486 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
40487 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
40488 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40489 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
40490 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
40491 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
40492 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40493 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
40494 + * DAMAGE.
40495 + * ========================================================================== */
40496 +#ifndef DWC_DEVICE_ONLY
40497 +#ifndef __DWC_HCD_H__
40498 +#define __DWC_HCD_H__
40499 +
40500 +#include "dwc_otg_os_dep.h"
40501 +#include "usb.h"
40502 +#include "dwc_otg_hcd_if.h"
40503 +#include "dwc_otg_core_if.h"
40504 +#include "dwc_list.h"
40505 +#include "dwc_otg_cil.h"
40506 +#include "dwc_otg_fiq_fsm.h"
40507 +
40508 +
40509 +/**
40510 + * @file
40511 + *
40512 + * This file contains the structures, constants, and interfaces for
40513 + * the Host Contoller Driver (HCD).
40514 + *
40515 + * The Host Controller Driver (HCD) is responsible for translating requests
40516 + * from the USB Driver into the appropriate actions on the DWC_otg controller.
40517 + * It isolates the USBD from the specifics of the controller by providing an
40518 + * API to the USBD.
40519 + */
40520 +
40521 +struct dwc_otg_hcd_pipe_info {
40522 +       uint8_t dev_addr;
40523 +       uint8_t ep_num;
40524 +       uint8_t pipe_type;
40525 +       uint8_t pipe_dir;
40526 +       uint16_t mps;
40527 +};
40528 +
40529 +struct dwc_otg_hcd_iso_packet_desc {
40530 +       uint32_t offset;
40531 +       uint32_t length;
40532 +       uint32_t actual_length;
40533 +       uint32_t status;
40534 +};
40535 +
40536 +struct dwc_otg_qtd;
40537 +
40538 +struct dwc_otg_hcd_urb {
40539 +       void *priv;
40540 +       struct dwc_otg_qtd *qtd;
40541 +       void *buf;
40542 +       dwc_dma_t dma;
40543 +       void *setup_packet;
40544 +       dwc_dma_t setup_dma;
40545 +       uint32_t length;
40546 +       uint32_t actual_length;
40547 +       uint32_t status;
40548 +       uint32_t error_count;
40549 +       uint32_t packet_count;
40550 +       uint32_t flags;
40551 +       uint16_t interval;
40552 +       struct dwc_otg_hcd_pipe_info pipe_info;
40553 +       struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
40554 +};
40555 +
40556 +static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
40557 +{
40558 +       return pipe->ep_num;
40559 +}
40560 +
40561 +static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
40562 +                                               *pipe)
40563 +{
40564 +       return pipe->pipe_type;
40565 +}
40566 +
40567 +static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
40568 +{
40569 +       return pipe->mps;
40570 +}
40571 +
40572 +static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
40573 +                                              *pipe)
40574 +{
40575 +       return pipe->dev_addr;
40576 +}
40577 +
40578 +static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
40579 +                                              *pipe)
40580 +{
40581 +       return (pipe->pipe_type == UE_ISOCHRONOUS);
40582 +}
40583 +
40584 +static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
40585 +                                             *pipe)
40586 +{
40587 +       return (pipe->pipe_type == UE_INTERRUPT);
40588 +}
40589 +
40590 +static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
40591 +                                              *pipe)
40592 +{
40593 +       return (pipe->pipe_type == UE_BULK);
40594 +}
40595 +
40596 +static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
40597 +                                                 *pipe)
40598 +{
40599 +       return (pipe->pipe_type == UE_CONTROL);
40600 +}
40601 +
40602 +static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
40603 +{
40604 +       return (pipe->pipe_dir == UE_DIR_IN);
40605 +}
40606 +
40607 +static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
40608 +                                             *pipe)
40609 +{
40610 +       return (!dwc_otg_hcd_is_pipe_in(pipe));
40611 +}
40612 +
40613 +static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
40614 +                                        uint8_t devaddr, uint8_t ep_num,
40615 +                                        uint8_t pipe_type, uint8_t pipe_dir,
40616 +                                        uint16_t mps)
40617 +{
40618 +       pipe->dev_addr = devaddr;
40619 +       pipe->ep_num = ep_num;
40620 +       pipe->pipe_type = pipe_type;
40621 +       pipe->pipe_dir = pipe_dir;
40622 +       pipe->mps = mps;
40623 +}
40624 +
40625 +/**
40626 + * Phases for control transfers.
40627 + */
40628 +typedef enum dwc_otg_control_phase {
40629 +       DWC_OTG_CONTROL_SETUP,
40630 +       DWC_OTG_CONTROL_DATA,
40631 +       DWC_OTG_CONTROL_STATUS
40632 +} dwc_otg_control_phase_e;
40633 +
40634 +/** Transaction types. */
40635 +typedef enum dwc_otg_transaction_type {
40636 +       DWC_OTG_TRANSACTION_NONE          = 0,
40637 +       DWC_OTG_TRANSACTION_PERIODIC      = 1,
40638 +       DWC_OTG_TRANSACTION_NON_PERIODIC  = 2,
40639 +       DWC_OTG_TRANSACTION_ALL           = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC
40640 +} dwc_otg_transaction_type_e;
40641 +
40642 +struct dwc_otg_qh;
40643 +
40644 +/**
40645 + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
40646 + * interrupt, or isochronous transfer. A single QTD is created for each URB
40647 + * (of one of these types) submitted to the HCD. The transfer associated with
40648 + * a QTD may require one or multiple transactions.
40649 + *
40650 + * A QTD is linked to a Queue Head, which is entered in either the
40651 + * non-periodic or periodic schedule for execution. When a QTD is chosen for
40652 + * execution, some or all of its transactions may be executed. After
40653 + * execution, the state of the QTD is updated. The QTD may be retired if all
40654 + * its transactions are complete or if an error occurred. Otherwise, it
40655 + * remains in the schedule so more transactions can be executed later.
40656 + */
40657 +typedef struct dwc_otg_qtd {
40658 +       /**
40659 +        * Determines the PID of the next data packet for the data phase of
40660 +        * control transfers. Ignored for other transfer types.<br>
40661 +        * One of the following values:
40662 +        *      - DWC_OTG_HC_PID_DATA0
40663 +        *      - DWC_OTG_HC_PID_DATA1
40664 +        */
40665 +       uint8_t data_toggle;
40666 +
40667 +       /** Current phase for control transfers (Setup, Data, or Status). */
40668 +       dwc_otg_control_phase_e control_phase;
40669 +
40670 +       /** Keep track of the current split type
40671 +        * for FS/LS endpoints on a HS Hub */
40672 +       uint8_t complete_split;
40673 +
40674 +       /** How many bytes transferred during SSPLIT OUT */
40675 +       uint32_t ssplit_out_xfer_count;
40676 +
40677 +       /**
40678 +        * Holds the number of bus errors that have occurred for a transaction
40679 +        * within this transfer.
40680 +        */
40681 +       uint8_t error_count;
40682 +
40683 +       /**
40684 +        * Index of the next frame descriptor for an isochronous transfer. A
40685 +        * frame descriptor describes the buffer position and length of the
40686 +        * data to be transferred in the next scheduled (micro)frame of an
40687 +        * isochronous transfer. It also holds status for that transaction.
40688 +        * The frame index starts at 0.
40689 +        */
40690 +       uint16_t isoc_frame_index;
40691 +
40692 +       /** Position of the ISOC split on full/low speed */
40693 +       uint8_t isoc_split_pos;
40694 +
40695 +       /** Position of the ISOC split in the buffer for the current frame */
40696 +       uint16_t isoc_split_offset;
40697 +
40698 +       /** URB for this transfer */
40699 +       struct dwc_otg_hcd_urb *urb;
40700 +
40701 +       struct dwc_otg_qh *qh;
40702 +
40703 +       /** This list of QTDs */
40704 +        DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
40705 +
40706 +       /** Indicates if this QTD is currently processed by HW. */
40707 +       uint8_t in_process;
40708 +
40709 +       /** Number of DMA descriptors for this QTD */
40710 +       uint8_t n_desc;
40711 +
40712 +       /**
40713 +        * Last activated frame(packet) index.
40714 +        * Used in Descriptor DMA mode only.
40715 +        */
40716 +       uint16_t isoc_frame_index_last;
40717 +
40718 +} dwc_otg_qtd_t;
40719 +
40720 +DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
40721 +
40722 +/**
40723 + * A Queue Head (QH) holds the static characteristics of an endpoint and
40724 + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
40725 + * be entered in either the non-periodic or periodic schedule.
40726 + */
40727 +typedef struct dwc_otg_qh {
40728 +       /**
40729 +        * Endpoint type.
40730 +        * One of the following values:
40731 +        *      - UE_CONTROL
40732 +        *      - UE_BULK
40733 +        *      - UE_INTERRUPT
40734 +        *      - UE_ISOCHRONOUS
40735 +        */
40736 +       uint8_t ep_type;
40737 +       uint8_t ep_is_in;
40738 +
40739 +       /** wMaxPacketSize Field of Endpoint Descriptor. */
40740 +       uint16_t maxp;
40741 +
40742 +       /**
40743 +        * Device speed.
40744 +        * One of the following values:
40745 +        *      - DWC_OTG_EP_SPEED_LOW
40746 +        *      - DWC_OTG_EP_SPEED_FULL
40747 +        *      - DWC_OTG_EP_SPEED_HIGH
40748 +        */
40749 +       uint8_t dev_speed;
40750 +
40751 +       /**
40752 +        * Determines the PID of the next data packet for non-control
40753 +        * transfers. Ignored for control transfers.<br>
40754 +        * One of the following values:
40755 +        *      - DWC_OTG_HC_PID_DATA0
40756 +        *      - DWC_OTG_HC_PID_DATA1
40757 +        */
40758 +       uint8_t data_toggle;
40759 +
40760 +       /** Ping state if 1. */
40761 +       uint8_t ping_state;
40762 +
40763 +       /**
40764 +        * List of QTDs for this QH.
40765 +        */
40766 +       struct dwc_otg_qtd_list qtd_list;
40767 +
40768 +       /** Host channel currently processing transfers for this QH. */
40769 +       struct dwc_hc *channel;
40770 +
40771 +       /** Full/low speed endpoint on high-speed hub requires split. */
40772 +       uint8_t do_split;
40773 +
40774 +       /** @name Periodic schedule information */
40775 +       /** @{ */
40776 +
40777 +       /** Bandwidth in microseconds per (micro)frame. */
40778 +       uint16_t usecs;
40779 +
40780 +       /** Interval between transfers in (micro)frames. */
40781 +       uint16_t interval;
40782 +
40783 +       /**
40784 +        * (micro)frame to initialize a periodic transfer. The transfer
40785 +        * executes in the following (micro)frame.
40786 +        */
40787 +       uint16_t sched_frame;
40788 +
40789 +       /*
40790 +       ** Frame a NAK was received on this queue head, used to minimise NAK retransmission
40791 +       */
40792 +       uint16_t nak_frame;
40793 +
40794 +       /** (micro)frame at which last start split was initialized. */
40795 +       uint16_t start_split_frame;
40796 +
40797 +       /** @} */
40798 +
40799 +       /**
40800 +        * Used instead of original buffer if
40801 +        * it(physical address) is not dword-aligned.
40802 +        */
40803 +       uint8_t *dw_align_buf;
40804 +       dwc_dma_t dw_align_buf_dma;
40805 +
40806 +       /** Entry for QH in either the periodic or non-periodic schedule. */
40807 +       dwc_list_link_t qh_list_entry;
40808 +
40809 +       /** @name Descriptor DMA support */
40810 +       /** @{ */
40811 +
40812 +       /** Descriptor List. */
40813 +       dwc_otg_host_dma_desc_t *desc_list;
40814 +
40815 +       /** Descriptor List physical address. */
40816 +       dwc_dma_t desc_list_dma;
40817 +
40818 +       /**
40819 +        * Xfer Bytes array.
40820 +        * Each element corresponds to a descriptor and indicates
40821 +        * original XferSize size value for the descriptor.
40822 +        */
40823 +       uint32_t *n_bytes;
40824 +
40825 +       /** Actual number of transfer descriptors in a list. */
40826 +       uint16_t ntd;
40827 +
40828 +       /** First activated isochronous transfer descriptor index. */
40829 +       uint8_t td_first;
40830 +       /** Last activated isochronous transfer descriptor index. */
40831 +       uint8_t td_last;
40832 +
40833 +       /** @} */
40834 +
40835 +
40836 +       uint16_t speed;
40837 +       uint16_t frame_usecs[8];
40838 +
40839 +       uint32_t skip_count;
40840 +} dwc_otg_qh_t;
40841 +
40842 +DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
40843 +
40844 +typedef struct urb_tq_entry {
40845 +       struct urb *urb;
40846 +       DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries;
40847 +} urb_tq_entry_t;
40848 +
40849 +DWC_TAILQ_HEAD(urb_list, urb_tq_entry);
40850 +
40851 +/**
40852 + * This structure holds the state of the HCD, including the non-periodic and
40853 + * periodic schedules.
40854 + */
40855 +struct dwc_otg_hcd {
40856 +       /** The DWC otg device pointer */
40857 +       struct dwc_otg_device *otg_dev;
40858 +       /** DWC OTG Core Interface Layer */
40859 +       dwc_otg_core_if_t *core_if;
40860 +
40861 +       /** Function HCD driver callbacks */
40862 +       struct dwc_otg_hcd_function_ops *fops;
40863 +
40864 +       /** Internal DWC HCD Flags */
40865 +       volatile union dwc_otg_hcd_internal_flags {
40866 +               uint32_t d32;
40867 +               struct {
40868 +                       unsigned port_connect_status_change:1;
40869 +                       unsigned port_connect_status:1;
40870 +                       unsigned port_reset_change:1;
40871 +                       unsigned port_enable_change:1;
40872 +                       unsigned port_suspend_change:1;
40873 +                       unsigned port_over_current_change:1;
40874 +                       unsigned port_l1_change:1;
40875 +                       unsigned reserved:26;
40876 +               } b;
40877 +       } flags;
40878 +
40879 +       /**
40880 +        * Inactive items in the non-periodic schedule. This is a list of
40881 +        * Queue Heads. Transfers associated with these Queue Heads are not
40882 +        * currently assigned to a host channel.
40883 +        */
40884 +       dwc_list_link_t non_periodic_sched_inactive;
40885 +
40886 +       /**
40887 +        * Active items in the non-periodic schedule. This is a list of
40888 +        * Queue Heads. Transfers associated with these Queue Heads are
40889 +        * currently assigned to a host channel.
40890 +        */
40891 +       dwc_list_link_t non_periodic_sched_active;
40892 +
40893 +       /**
40894 +        * Pointer to the next Queue Head to process in the active
40895 +        * non-periodic schedule.
40896 +        */
40897 +       dwc_list_link_t *non_periodic_qh_ptr;
40898 +
40899 +       /**
40900 +        * Inactive items in the periodic schedule. This is a list of QHs for
40901 +        * periodic transfers that are _not_ scheduled for the next frame.
40902 +        * Each QH in the list has an interval counter that determines when it
40903 +        * needs to be scheduled for execution. This scheduling mechanism
40904 +        * allows only a simple calculation for periodic bandwidth used (i.e.
40905 +        * must assume that all periodic transfers may need to execute in the
40906 +        * same frame). However, it greatly simplifies scheduling and should
40907 +        * be sufficient for the vast majority of OTG hosts, which need to
40908 +        * connect to a small number of peripherals at one time.
40909 +        *
40910 +        * Items move from this list to periodic_sched_ready when the QH
40911 +        * interval counter is 0 at SOF.
40912 +        */
40913 +       dwc_list_link_t periodic_sched_inactive;
40914 +
40915 +       /**
40916 +        * List of periodic QHs that are ready for execution in the next
40917 +        * frame, but have not yet been assigned to host channels.
40918 +        *
40919 +        * Items move from this list to periodic_sched_assigned as host
40920 +        * channels become available during the current frame.
40921 +        */
40922 +       dwc_list_link_t periodic_sched_ready;
40923 +
40924 +       /**
40925 +        * List of periodic QHs to be executed in the next frame that are
40926 +        * assigned to host channels.
40927 +        *
40928 +        * Items move from this list to periodic_sched_queued as the
40929 +        * transactions for the QH are queued to the DWC_otg controller.
40930 +        */
40931 +       dwc_list_link_t periodic_sched_assigned;
40932 +
40933 +       /**
40934 +        * List of periodic QHs that have been queued for execution.
40935 +        *
40936 +        * Items move from this list to either periodic_sched_inactive or
40937 +        * periodic_sched_ready when the channel associated with the transfer
40938 +        * is released. If the interval for the QH is 1, the item moves to
40939 +        * periodic_sched_ready because it must be rescheduled for the next
40940 +        * frame. Otherwise, the item moves to periodic_sched_inactive.
40941 +        */
40942 +       dwc_list_link_t periodic_sched_queued;
40943 +
40944 +       /**
40945 +        * Total bandwidth claimed so far for periodic transfers. This value
40946 +        * is in microseconds per (micro)frame. The assumption is that all
40947 +        * periodic transfers may occur in the same (micro)frame.
40948 +        */
40949 +       uint16_t periodic_usecs;
40950 +
40951 +       /**
40952 +        * Total bandwidth claimed so far for all periodic transfers
40953 +        * in a frame.
40954 +        * This will include a mixture of HS and FS transfers.
40955 +        * Units are microseconds per (micro)frame.
40956 +        * We have a budget per frame and have to schedule
40957 +        * transactions accordingly.
40958 +        * Watch out for the fact that things are actually scheduled for the
40959 +        * "next frame".
40960 +        */
40961 +       uint16_t                frame_usecs[8];
40962 +
40963 +
40964 +       /**
40965 +        * Frame number read from the core at SOF. The value ranges from 0 to
40966 +        * DWC_HFNUM_MAX_FRNUM.
40967 +        */
40968 +       uint16_t frame_number;
40969 +
40970 +       /**
40971 +        * Count of periodic QHs, if using several eps. For SOF enable/disable.
40972 +        */
40973 +       uint16_t periodic_qh_count;
40974 +
40975 +       /**
40976 +        * Free host channels in the controller. This is a list of
40977 +        * dwc_hc_t items.
40978 +        */
40979 +       struct hc_list free_hc_list;
40980 +       /**
40981 +        * Number of host channels assigned to periodic transfers. Currently
40982 +        * assuming that there is a dedicated host channel for each periodic
40983 +        * transaction and at least one host channel available for
40984 +        * non-periodic transactions.
40985 +        */
40986 +       int periodic_channels; /* microframe_schedule==0 */
40987 +
40988 +       /**
40989 +        * Number of host channels assigned to non-periodic transfers.
40990 +        */
40991 +       int non_periodic_channels; /* microframe_schedule==0 */
40992 +
40993 +       /**
40994 +        * Number of host channels assigned to non-periodic transfers.
40995 +        */
40996 +       int available_host_channels;
40997 +
40998 +       /**
40999 +        * Array of pointers to the host channel descriptors. Allows accessing
41000 +        * a host channel descriptor given the host channel number. This is
41001 +        * useful in interrupt handlers.
41002 +        */
41003 +       struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
41004 +
41005 +       /**
41006 +        * Buffer to use for any data received during the status phase of a
41007 +        * control transfer. Normally no data is transferred during the status
41008 +        * phase. This buffer is used as a bit bucket.
41009 +        */
41010 +       uint8_t *status_buf;
41011 +
41012 +       /**
41013 +        * DMA address for status_buf.
41014 +        */
41015 +       dma_addr_t status_buf_dma;
41016 +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
41017 +
41018 +       /**
41019 +        * Connection timer. An OTG host must display a message if the device
41020 +        * does not connect. Started when the VBus power is turned on via
41021 +        * sysfs attribute "buspower".
41022 +        */
41023 +       dwc_timer_t *conn_timer;
41024 +
41025 +       /* Tasket to do a reset */
41026 +       dwc_tasklet_t *reset_tasklet;
41027 +
41028 +       dwc_tasklet_t *completion_tasklet;
41029 +       struct urb_list completed_urb_list;
41030 +
41031 +       /*  */
41032 +       dwc_spinlock_t *lock;
41033 +       dwc_spinlock_t *channel_lock;
41034 +       /**
41035 +        * Private data that could be used by OS wrapper.
41036 +        */
41037 +       void *priv;
41038 +
41039 +       uint8_t otg_port;
41040 +
41041 +       /** Frame List */
41042 +       uint32_t *frame_list;
41043 +
41044 +       /** Hub - Port assignment */
41045 +       int hub_port[128];
41046 +#ifdef FIQ_DEBUG
41047 +       int hub_port_alloc[2048];
41048 +#endif
41049 +
41050 +       /** Frame List DMA address */
41051 +       dma_addr_t frame_list_dma;
41052 +
41053 +       struct fiq_stack *fiq_stack;
41054 +       struct fiq_state *fiq_state;
41055 +
41056 +       /** Virtual address for split transaction DMA bounce buffers */
41057 +       struct fiq_dma_blob *fiq_dmab;
41058 +
41059 +#ifdef DEBUG
41060 +       uint32_t frrem_samples;
41061 +       uint64_t frrem_accum;
41062 +
41063 +       uint32_t hfnum_7_samples_a;
41064 +       uint64_t hfnum_7_frrem_accum_a;
41065 +       uint32_t hfnum_0_samples_a;
41066 +       uint64_t hfnum_0_frrem_accum_a;
41067 +       uint32_t hfnum_other_samples_a;
41068 +       uint64_t hfnum_other_frrem_accum_a;
41069 +
41070 +       uint32_t hfnum_7_samples_b;
41071 +       uint64_t hfnum_7_frrem_accum_b;
41072 +       uint32_t hfnum_0_samples_b;
41073 +       uint64_t hfnum_0_frrem_accum_b;
41074 +       uint32_t hfnum_other_samples_b;
41075 +       uint64_t hfnum_other_frrem_accum_b;
41076 +#endif
41077 +};
41078 +
41079 +/** @name Transaction Execution Functions */
41080 +/** @{ */
41081 +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
41082 +                                                                 * hcd);
41083 +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
41084 +                                          dwc_otg_transaction_type_e tr_type);
41085 +
41086 +int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh);
41087 +void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh);
41088 +
41089 +extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh);
41090 +extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh);
41091 +extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num);
41092 +
41093 +/** @} */
41094 +
41095 +/** @name Interrupt Handler Functions */
41096 +/** @{ */
41097 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41098 +extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41099 +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
41100 +                                                        dwc_otg_hcd);
41101 +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
41102 +                                                       dwc_otg_hcd);
41103 +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
41104 +                                                          dwc_otg_hcd);
41105 +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
41106 +                                                          dwc_otg_hcd);
41107 +extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41108 +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
41109 +                                                            dwc_otg_hcd);
41110 +extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41111 +extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41112 +extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
41113 +                                           uint32_t num);
41114 +extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
41115 +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
41116 +                                                      dwc_otg_hcd);
41117 +/** @} */
41118 +
41119 +/** @name Schedule Queue Functions */
41120 +/** @{ */
41121 +
41122 +/* Implemented in dwc_otg_hcd_queue.c */
41123 +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
41124 +                                          dwc_otg_hcd_urb_t * urb, int atomic_alloc);
41125 +extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41126 +extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41127 +extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41128 +extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
41129 +                                     int sched_csplit);
41130 +
41131 +/** Remove and free a QH */
41132 +static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
41133 +                                                 dwc_otg_qh_t * qh)
41134 +{
41135 +       dwc_irqflags_t flags;
41136 +       DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
41137 +       dwc_otg_hcd_qh_remove(hcd, qh);
41138 +       DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
41139 +       dwc_otg_hcd_qh_free(hcd, qh);
41140 +}
41141 +
41142 +/** Allocates memory for a QH structure.
41143 + * @return Returns the memory allocate or NULL on error. */
41144 +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
41145 +{
41146 +       if (atomic_alloc)
41147 +               return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
41148 +       else
41149 +               return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
41150 +}
41151 +
41152 +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
41153 +                                            int atomic_alloc);
41154 +extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
41155 +extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
41156 +                              dwc_otg_qh_t ** qh, int atomic_alloc);
41157 +
41158 +/** Allocates memory for a QTD structure.
41159 + * @return Returns the memory allocate or NULL on error. */
41160 +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
41161 +{
41162 +       if (atomic_alloc)
41163 +               return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
41164 +       else
41165 +               return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
41166 +}
41167 +
41168 +/** Frees the memory for a QTD structure.  QTD should already be removed from
41169 + * list.
41170 + * @param qtd QTD to free.*/
41171 +static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
41172 +{
41173 +       DWC_FREE(qtd);
41174 +}
41175 +
41176 +/** Removes a QTD from list.
41177 + * @param hcd HCD instance.
41178 + * @param qtd QTD to remove from list.
41179 + * @param qh QTD belongs to.
41180 + */
41181 +static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
41182 +                                         dwc_otg_qtd_t * qtd,
41183 +                                         dwc_otg_qh_t * qh)
41184 +{
41185 +       DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
41186 +}
41187 +
41188 +/** Remove and free a QTD
41189 +  * Need to disable IRQ and hold hcd lock while calling this function out of
41190 +  * interrupt servicing chain */
41191 +static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
41192 +                                                  dwc_otg_qtd_t * qtd,
41193 +                                                  dwc_otg_qh_t * qh)
41194 +{
41195 +       dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
41196 +       dwc_otg_hcd_qtd_free(qtd);
41197 +}
41198 +
41199 +/** @} */
41200 +
41201 +/** @name Descriptor DMA Supporting Functions */
41202 +/** @{ */
41203 +
41204 +extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41205 +extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
41206 +                                          dwc_hc_t * hc,
41207 +                                          dwc_otg_hc_regs_t * hc_regs,
41208 +                                          dwc_otg_halt_status_e halt_status);
41209 +
41210 +extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41211 +extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
41212 +
41213 +/** @} */
41214 +
41215 +/** @name Internal Functions */
41216 +/** @{ */
41217 +dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
41218 +/** @} */
41219 +
41220 +#ifdef CONFIG_USB_DWC_OTG_LPM
41221 +extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
41222 +                                          uint8_t devaddr);
41223 +extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
41224 +#endif
41225 +
41226 +/** Gets the QH that contains the list_head */
41227 +#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
41228 +
41229 +/** Gets the QTD that contains the list_head */
41230 +#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
41231 +
41232 +/** Check if QH is non-periodic  */
41233 +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
41234 +                                    (_qh_ptr_->ep_type == UE_CONTROL))
41235 +
41236 +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
41237 +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
41238 +
41239 +/** Packet size for any kind of endpoint descriptor */
41240 +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
41241 +
41242 +/**
41243 + * Returns true if _frame1 is less than or equal to _frame2. The comparison is
41244 + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
41245 + * frame number when the max frame number is reached.
41246 + */
41247 +static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
41248 +{
41249 +       return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
41250 +           (DWC_HFNUM_MAX_FRNUM >> 1);
41251 +}
41252 +
41253 +/**
41254 + * Returns true if _frame1 is greater than _frame2. The comparison is done
41255 + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
41256 + * number when the max frame number is reached.
41257 + */
41258 +static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
41259 +{
41260 +       return (frame1 != frame2) &&
41261 +           (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
41262 +            (DWC_HFNUM_MAX_FRNUM >> 1));
41263 +}
41264 +
41265 +/**
41266 + * Increments _frame by the amount specified by _inc. The addition is done
41267 + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
41268 + */
41269 +static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
41270 +{
41271 +       return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
41272 +}
41273 +
41274 +static inline uint16_t dwc_full_frame_num(uint16_t frame)
41275 +{
41276 +       return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
41277 +}
41278 +
41279 +static inline uint16_t dwc_micro_frame_num(uint16_t frame)
41280 +{
41281 +       return frame & 0x7;
41282 +}
41283 +
41284 +void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
41285 +                                 dwc_otg_hc_regs_t * hc_regs,
41286 +                                 dwc_otg_qtd_t * qtd);
41287 +
41288 +#ifdef DEBUG
41289 +/**
41290 + * Macro to sample the remaining PHY clocks left in the current frame. This
41291 + * may be used during debugging to determine the average time it takes to
41292 + * execute sections of code. There are two possible sample points, "a" and
41293 + * "b", so the _letter argument must be one of these values.
41294 + *
41295 + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
41296 + * example, "cat /sys/devices/lm0/hcd_frrem".
41297 + */
41298 +#define dwc_sample_frrem(_hcd, _qh, _letter) \
41299 +{ \
41300 +       hfnum_data_t hfnum; \
41301 +       dwc_otg_qtd_t *qtd; \
41302 +       qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
41303 +       if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
41304 +               hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
41305 +               switch (hfnum.b.frnum & 0x7) { \
41306 +               case 7: \
41307 +                       _hcd->hfnum_7_samples_##_letter++; \
41308 +                       _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
41309 +                       break; \
41310 +               case 0: \
41311 +                       _hcd->hfnum_0_samples_##_letter++; \
41312 +                       _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
41313 +                       break; \
41314 +               default: \
41315 +                       _hcd->hfnum_other_samples_##_letter++; \
41316 +                       _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
41317 +                       break; \
41318 +               } \
41319 +       } \
41320 +}
41321 +#else
41322 +#define dwc_sample_frrem(_hcd, _qh, _letter)
41323 +#endif
41324 +#endif
41325 +#endif /* DWC_DEVICE_ONLY */
41326 --- /dev/null
41327 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c
41328 @@ -0,0 +1,1132 @@
41329 +/*==========================================================================
41330 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
41331 + * $Revision: #10 $
41332 + * $Date: 2011/10/20 $
41333 + * $Change: 1869464 $
41334 + *
41335 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
41336 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
41337 + * otherwise expressly agreed to in writing between Synopsys and you.
41338 + *
41339 + * The Software IS NOT an item of Licensed Software or Licensed Product under
41340 + * any End User Software License Agreement or Agreement for Licensed Product
41341 + * with Synopsys or any supplement thereto. You are permitted to use and
41342 + * redistribute this Software in source and binary forms, with or without
41343 + * modification, provided that redistributions of source code must retain this
41344 + * notice. You may not view, use, disclose, copy or distribute this file or
41345 + * any information contained herein except pursuant to this license grant from
41346 + * Synopsys. If you do not agree with this notice, including the disclaimer
41347 + * below, then you are not authorized to use the Software.
41348 + *
41349 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
41350 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41351 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41352 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
41353 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41354 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41355 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
41356 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41357 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
41358 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41359 + * DAMAGE.
41360 + * ========================================================================== */
41361 +#ifndef DWC_DEVICE_ONLY
41362 +
41363 +/** @file
41364 + * This file contains Descriptor DMA support implementation for host mode.
41365 + */
41366 +
41367 +#include "dwc_otg_hcd.h"
41368 +#include "dwc_otg_regs.h"
41369 +
41370 +extern bool microframe_schedule;
41371 +
41372 +static inline uint8_t frame_list_idx(uint16_t frame)
41373 +{
41374 +       return (frame & (MAX_FRLIST_EN_NUM - 1));
41375 +}
41376 +
41377 +static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
41378 +{
41379 +       return (idx + inc) &
41380 +           (((speed ==
41381 +              DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
41382 +             MAX_DMA_DESC_NUM_GENERIC) - 1);
41383 +}
41384 +
41385 +static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
41386 +{
41387 +       return (idx - inc) &
41388 +           (((speed ==
41389 +              DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
41390 +             MAX_DMA_DESC_NUM_GENERIC) - 1);
41391 +}
41392 +
41393 +static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
41394 +{
41395 +       return (((qh->ep_type == UE_ISOCHRONOUS)
41396 +                && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
41397 +               ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
41398 +}
41399 +static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
41400 +{
41401 +       return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
41402 +               ? ((qh->interval + 8 - 1) / 8)
41403 +               : qh->interval);
41404 +}
41405 +
41406 +static int desc_list_alloc(dwc_otg_qh_t * qh)
41407 +{
41408 +       int retval = 0;
41409 +
41410 +       qh->desc_list = (dwc_otg_host_dma_desc_t *)
41411 +           DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
41412 +                         &qh->desc_list_dma);
41413 +
41414 +       if (!qh->desc_list) {
41415 +               retval = -DWC_E_NO_MEMORY;
41416 +               DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
41417 +
41418 +       }
41419 +
41420 +       dwc_memset(qh->desc_list, 0x00,
41421 +                  sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
41422 +
41423 +       qh->n_bytes =
41424 +           (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
41425 +
41426 +       if (!qh->n_bytes) {
41427 +               retval = -DWC_E_NO_MEMORY;
41428 +               DWC_ERROR
41429 +                   ("%s: Failed to allocate array for descriptors' size actual values\n",
41430 +                    __func__);
41431 +
41432 +       }
41433 +       return retval;
41434 +
41435 +}
41436 +
41437 +static void desc_list_free(dwc_otg_qh_t * qh)
41438 +{
41439 +       if (qh->desc_list) {
41440 +               DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
41441 +                            qh->desc_list_dma);
41442 +               qh->desc_list = NULL;
41443 +       }
41444 +
41445 +       if (qh->n_bytes) {
41446 +               DWC_FREE(qh->n_bytes);
41447 +               qh->n_bytes = NULL;
41448 +       }
41449 +}
41450 +
41451 +static int frame_list_alloc(dwc_otg_hcd_t * hcd)
41452 +{
41453 +       int retval = 0;
41454 +       if (hcd->frame_list)
41455 +               return 0;
41456 +
41457 +       hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM,
41458 +                                       &hcd->frame_list_dma);
41459 +       if (!hcd->frame_list) {
41460 +               retval = -DWC_E_NO_MEMORY;
41461 +               DWC_ERROR("%s: Frame List allocation failed\n", __func__);
41462 +       }
41463 +
41464 +       dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
41465 +
41466 +       return retval;
41467 +}
41468 +
41469 +static void frame_list_free(dwc_otg_hcd_t * hcd)
41470 +{
41471 +       if (!hcd->frame_list)
41472 +               return;
41473 +
41474 +       DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
41475 +       hcd->frame_list = NULL;
41476 +}
41477 +
41478 +static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
41479 +{
41480 +
41481 +       hcfg_data_t hcfg;
41482 +
41483 +       hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
41484 +
41485 +       if (hcfg.b.perschedena) {
41486 +               /* already enabled */
41487 +               return;
41488 +       }
41489 +
41490 +       DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
41491 +                       hcd->frame_list_dma);
41492 +
41493 +       switch (fr_list_en) {
41494 +       case 64:
41495 +               hcfg.b.frlisten = 3;
41496 +               break;
41497 +       case 32:
41498 +               hcfg.b.frlisten = 2;
41499 +               break;
41500 +       case 16:
41501 +               hcfg.b.frlisten = 1;
41502 +               break;
41503 +       case 8:
41504 +               hcfg.b.frlisten = 0;
41505 +               break;
41506 +       default:
41507 +               break;
41508 +       }
41509 +
41510 +       hcfg.b.perschedena = 1;
41511 +
41512 +       DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
41513 +       DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
41514 +
41515 +}
41516 +
41517 +static void per_sched_disable(dwc_otg_hcd_t * hcd)
41518 +{
41519 +       hcfg_data_t hcfg;
41520 +
41521 +       hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
41522 +
41523 +       if (!hcfg.b.perschedena) {
41524 +               /* already disabled */
41525 +               return;
41526 +       }
41527 +       hcfg.b.perschedena = 0;
41528 +
41529 +       DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
41530 +       DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
41531 +}
41532 +
41533 +/*
41534 + * Activates/Deactivates FrameList entries for the channel
41535 + * based on endpoint servicing period.
41536 + */
41537 +void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
41538 +{
41539 +       uint16_t i, j, inc;
41540 +       dwc_hc_t *hc = NULL;
41541 +
41542 +       if (!qh->channel) {
41543 +               DWC_ERROR("qh->channel = %p", qh->channel);
41544 +               return;
41545 +       }
41546 +
41547 +       if (!hcd) {
41548 +               DWC_ERROR("------hcd = %p", hcd);
41549 +               return;
41550 +       }
41551 +
41552 +       if (!hcd->frame_list) {
41553 +               DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
41554 +               return;
41555 +       }
41556 +
41557 +       hc = qh->channel;
41558 +       inc = frame_incr_val(qh);
41559 +       if (qh->ep_type == UE_ISOCHRONOUS)
41560 +               i = frame_list_idx(qh->sched_frame);
41561 +       else
41562 +               i = 0;
41563 +
41564 +       j = i;
41565 +       do {
41566 +               if (enable)
41567 +                       hcd->frame_list[j] |= (1 << hc->hc_num);
41568 +               else
41569 +                       hcd->frame_list[j] &= ~(1 << hc->hc_num);
41570 +               j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
41571 +       }
41572 +       while (j != i);
41573 +       if (!enable)
41574 +               return;
41575 +       hc->schinfo = 0;
41576 +       if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
41577 +               j = 1;
41578 +               /* TODO - check this */
41579 +               inc = (8 + qh->interval - 1) / qh->interval;
41580 +               for (i = 0; i < inc; i++) {
41581 +                       hc->schinfo |= j;
41582 +                       j = j << qh->interval;
41583 +               }
41584 +       } else {
41585 +               hc->schinfo = 0xff;
41586 +       }
41587 +}
41588 +
41589 +#if 1
41590 +void dump_frame_list(dwc_otg_hcd_t * hcd)
41591 +{
41592 +       int i = 0;
41593 +       DWC_PRINTF("--FRAME LIST (hex) --\n");
41594 +       for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
41595 +               DWC_PRINTF("%x\t", hcd->frame_list[i]);
41596 +               if (!(i % 8) && i)
41597 +                       DWC_PRINTF("\n");
41598 +       }
41599 +       DWC_PRINTF("\n----\n");
41600 +
41601 +}
41602 +#endif
41603 +
41604 +static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41605 +{
41606 +       dwc_irqflags_t flags;
41607 +       dwc_spinlock_t *channel_lock = hcd->channel_lock;
41608 +
41609 +       dwc_hc_t *hc = qh->channel;
41610 +       if (dwc_qh_is_non_per(qh)) {
41611 +               DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
41612 +               if (!microframe_schedule)
41613 +                       hcd->non_periodic_channels--;
41614 +               else
41615 +                       hcd->available_host_channels++;
41616 +               DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
41617 +       } else
41618 +               update_frame_list(hcd, qh, 0);
41619 +
41620 +       /*
41621 +        * The condition is added to prevent double cleanup try in case of device
41622 +        * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
41623 +        */
41624 +       if (hc->qh) {
41625 +               dwc_otg_hc_cleanup(hcd->core_if, hc);
41626 +               DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
41627 +               hc->qh = NULL;
41628 +       }
41629 +
41630 +       qh->channel = NULL;
41631 +       qh->ntd = 0;
41632 +
41633 +       if (qh->desc_list) {
41634 +               dwc_memset(qh->desc_list, 0x00,
41635 +                          sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
41636 +       }
41637 +}
41638 +
41639 +/**
41640 + * Initializes a QH structure's Descriptor DMA related members.
41641 + * Allocates memory for descriptor list.
41642 + * On first periodic QH, allocates memory for FrameList
41643 + * and enables periodic scheduling.
41644 + *
41645 + * @param hcd The HCD state structure for the DWC OTG controller.
41646 + * @param qh The QH to init.
41647 + *
41648 + * @return 0 if successful, negative error code otherwise.
41649 + */
41650 +int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41651 +{
41652 +       int retval = 0;
41653 +
41654 +       if (qh->do_split) {
41655 +               DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
41656 +               return -1;
41657 +       }
41658 +
41659 +       retval = desc_list_alloc(qh);
41660 +
41661 +       if ((retval == 0)
41662 +           && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
41663 +               if (!hcd->frame_list) {
41664 +                       retval = frame_list_alloc(hcd);
41665 +                       /* Enable periodic schedule on first periodic QH */
41666 +                       if (retval == 0)
41667 +                               per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
41668 +               }
41669 +       }
41670 +
41671 +       qh->ntd = 0;
41672 +
41673 +       return retval;
41674 +}
41675 +
41676 +/**
41677 + * Frees descriptor list memory associated with the QH.
41678 + * If QH is periodic and the last, frees FrameList memory
41679 + * and disables periodic scheduling.
41680 + *
41681 + * @param hcd The HCD state structure for the DWC OTG controller.
41682 + * @param qh The QH to init.
41683 + */
41684 +void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41685 +{
41686 +       desc_list_free(qh);
41687 +
41688 +       /*
41689 +        * Channel still assigned due to some reasons.
41690 +        * Seen on Isoc URB dequeue. Channel halted but no subsequent
41691 +        * ChHalted interrupt to release the channel. Afterwards
41692 +        * when it comes here from endpoint disable routine
41693 +        * channel remains assigned.
41694 +        */
41695 +       if (qh->channel)
41696 +               release_channel_ddma(hcd, qh);
41697 +
41698 +       if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
41699 +           && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) {
41700 +
41701 +               per_sched_disable(hcd);
41702 +               frame_list_free(hcd);
41703 +       }
41704 +}
41705 +
41706 +static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
41707 +{
41708 +       if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
41709 +               /*
41710 +                * Descriptor set(8 descriptors) index
41711 +                * which is 8-aligned.
41712 +                */
41713 +               return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
41714 +       } else {
41715 +               return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
41716 +       }
41717 +}
41718 +
41719 +/*
41720 + * Determine starting frame for Isochronous transfer.
41721 + * Few frames skipped to prevent race condition with HC.
41722 + */
41723 +static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
41724 +                                  uint8_t * skip_frames)
41725 +{
41726 +       uint16_t frame = 0;
41727 +       hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
41728 +
41729 +       /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
41730 +
41731 +       /*
41732 +        * skip_frames is used to limit activated descriptors number
41733 +        * to avoid the situation when HC services the last activated
41734 +        * descriptor firstly.
41735 +        * Example for FS:
41736 +        * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
41737 +        * corresponding to curr_frame+1, the descriptor corresponding to frame 2
41738 +        * will be fetched. If the number of descriptors is max=64 (or greather) the
41739 +        * list will be fully programmed with Active descriptors and it is possible
41740 +        * case(rare) that the latest descriptor(considering rollback) corresponding
41741 +        * to frame 2 will be serviced first. HS case is more probable because, in fact,
41742 +        * up to 11 uframes(16 in the code) may be skipped.
41743 +        */
41744 +       if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
41745 +               /*
41746 +                * Consider uframe counter also, to start xfer asap.
41747 +                * If half of the frame elapsed skip 2 frames otherwise
41748 +                * just 1 frame.
41749 +                * Starting descriptor index must be 8-aligned, so
41750 +                * if the current frame is near to complete the next one
41751 +                * is skipped as well.
41752 +                */
41753 +
41754 +               if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
41755 +                       *skip_frames = 2 * 8;
41756 +                       frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
41757 +               } else {
41758 +                       *skip_frames = 1 * 8;
41759 +                       frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
41760 +               }
41761 +
41762 +               frame = dwc_full_frame_num(frame);
41763 +       } else {
41764 +               /*
41765 +                * Two frames are skipped for FS - the current and the next.
41766 +                * But for descriptor programming, 1 frame(descriptor) is enough,
41767 +                * see example above.
41768 +                */
41769 +               *skip_frames = 1;
41770 +               frame = dwc_frame_num_inc(hcd->frame_number, 2);
41771 +       }
41772 +
41773 +       return frame;
41774 +}
41775 +
41776 +/*
41777 + * Calculate initial descriptor index for isochronous transfer
41778 + * based on scheduled frame.
41779 + */
41780 +static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41781 +{
41782 +       uint16_t frame = 0, fr_idx, fr_idx_tmp;
41783 +       uint8_t skip_frames = 0;
41784 +       /*
41785 +        * With current ISOC processing algorithm the channel is being
41786 +        * released when no more QTDs in the list(qh->ntd == 0).
41787 +        * Thus this function is called only when qh->ntd == 0 and qh->channel == 0.
41788 +        *
41789 +        * So qh->channel != NULL branch is not used and just not removed from the
41790 +        * source file. It is required for another possible approach which is,
41791 +        * do not disable and release the channel when ISOC session completed,
41792 +        * just move QH to inactive schedule until new QTD arrives.
41793 +        * On new QTD, the QH moved back to 'ready' schedule,
41794 +        * starting frame and therefore starting desc_index are recalculated.
41795 +        * In this case channel is released only on ep_disable.
41796 +        */
41797 +
41798 +       /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
41799 +       if (qh->channel) {
41800 +               frame = calc_starting_frame(hcd, qh, &skip_frames);
41801 +               /*
41802 +                * Calculate initial descriptor index based on FrameList current bitmap
41803 +                * and servicing period.
41804 +                */
41805 +               fr_idx_tmp = frame_list_idx(frame);
41806 +               fr_idx =
41807 +                   (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
41808 +                    fr_idx_tmp)
41809 +                   % frame_incr_val(qh);
41810 +               fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
41811 +       } else {
41812 +               qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
41813 +               fr_idx = frame_list_idx(qh->sched_frame);
41814 +       }
41815 +
41816 +       qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
41817 +
41818 +       return skip_frames;
41819 +}
41820 +
41821 +#define        ISOC_URB_GIVEBACK_ASAP
41822 +
41823 +#define MAX_ISOC_XFER_SIZE_FS 1023
41824 +#define MAX_ISOC_XFER_SIZE_HS 3072
41825 +#define DESCNUM_THRESHOLD 4
41826 +
41827 +static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
41828 +                              uint8_t skip_frames)
41829 +{
41830 +       struct dwc_otg_hcd_iso_packet_desc *frame_desc;
41831 +       dwc_otg_qtd_t *qtd;
41832 +       dwc_otg_host_dma_desc_t *dma_desc;
41833 +       uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
41834 +
41835 +       idx = qh->td_last;
41836 +       inc = qh->interval;
41837 +       n_desc = 0;
41838 +
41839 +       ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
41840 +       if (skip_frames && !qh->channel)
41841 +               ntd_max = ntd_max - skip_frames / qh->interval;
41842 +
41843 +       max_xfer_size =
41844 +           (qh->dev_speed ==
41845 +            DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
41846 +           MAX_ISOC_XFER_SIZE_FS;
41847 +
41848 +       DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
41849 +               while ((qh->ntd < ntd_max)
41850 +                      && (qtd->isoc_frame_index_last <
41851 +                          qtd->urb->packet_count)) {
41852 +
41853 +                       dma_desc = &qh->desc_list[idx];
41854 +                       dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
41855 +
41856 +                       frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
41857 +
41858 +                       if (frame_desc->length > max_xfer_size)
41859 +                               qh->n_bytes[idx] = max_xfer_size;
41860 +                       else
41861 +                               qh->n_bytes[idx] = frame_desc->length;
41862 +                       dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
41863 +                       dma_desc->status.b_isoc.a = 1;
41864 +                       dma_desc->status.b_isoc.sts = 0;
41865 +
41866 +                       dma_desc->buf = qtd->urb->dma + frame_desc->offset;
41867 +
41868 +                       qh->ntd++;
41869 +
41870 +                       qtd->isoc_frame_index_last++;
41871 +
41872 +#ifdef ISOC_URB_GIVEBACK_ASAP
41873 +                       /*
41874 +                        * Set IOC for each descriptor corresponding to the
41875 +                        * last frame of the URB.
41876 +                        */
41877 +                       if (qtd->isoc_frame_index_last ==
41878 +                           qtd->urb->packet_count)
41879 +                               dma_desc->status.b_isoc.ioc = 1;
41880 +
41881 +#endif
41882 +                       idx = desclist_idx_inc(idx, inc, qh->dev_speed);
41883 +                       n_desc++;
41884 +
41885 +               }
41886 +               qtd->in_process = 1;
41887 +       }
41888 +
41889 +       qh->td_last = idx;
41890 +
41891 +#ifdef ISOC_URB_GIVEBACK_ASAP
41892 +       /* Set IOC for the last descriptor if descriptor list is full */
41893 +       if (qh->ntd == ntd_max) {
41894 +               idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
41895 +               qh->desc_list[idx].status.b_isoc.ioc = 1;
41896 +       }
41897 +#else
41898 +       /*
41899 +        * Set IOC bit only for one descriptor.
41900 +        * Always try to be ahead of HW processing,
41901 +        * i.e. on IOC generation driver activates next descriptors but
41902 +        * core continues to process descriptors followed the one with IOC set.
41903 +        */
41904 +
41905 +       if (n_desc > DESCNUM_THRESHOLD) {
41906 +               /*
41907 +                * Move IOC "up". Required even if there is only one QTD
41908 +                * in the list, cause QTDs migth continue to be queued,
41909 +                * but during the activation it was only one queued.
41910 +                * Actually more than one QTD might be in the list if this function called
41911 +                * from XferCompletion - QTDs was queued during HW processing of the previous
41912 +                * descriptor chunk.
41913 +                */
41914 +               idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
41915 +       } else {
41916 +               /*
41917 +                * Set the IOC for the latest descriptor
41918 +                * if either number of descriptor is not greather than threshold
41919 +                * or no more new descriptors activated.
41920 +                */
41921 +               idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
41922 +       }
41923 +
41924 +       qh->desc_list[idx].status.b_isoc.ioc = 1;
41925 +#endif
41926 +}
41927 +
41928 +static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
41929 +{
41930 +
41931 +       dwc_hc_t *hc;
41932 +       dwc_otg_host_dma_desc_t *dma_desc;
41933 +       dwc_otg_qtd_t *qtd;
41934 +       int num_packets, len, n_desc = 0;
41935 +
41936 +       hc = qh->channel;
41937 +
41938 +       /*
41939 +        * Start with hc->xfer_buff initialized in
41940 +        * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
41941 +        * this pointer re-assigned to the buffer of the currently processed QTD.
41942 +        * For non-SG request there is always one QTD active.
41943 +        */
41944 +
41945 +       DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
41946 +
41947 +               if (n_desc) {
41948 +                       /* SG request - more than 1 QTDs */
41949 +                       hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
41950 +                       hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
41951 +               }
41952 +
41953 +               qtd->n_desc = 0;
41954 +
41955 +               do {
41956 +                       dma_desc = &qh->desc_list[n_desc];
41957 +                       len = hc->xfer_len;
41958 +
41959 +                       if (len > MAX_DMA_DESC_SIZE)
41960 +                               len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
41961 +
41962 +                       if (hc->ep_is_in) {
41963 +                               if (len > 0) {
41964 +                                       num_packets = (len + hc->max_packet - 1) / hc->max_packet;
41965 +                               } else {
41966 +                                       /* Need 1 packet for transfer length of 0. */
41967 +                                       num_packets = 1;
41968 +                               }
41969 +                               /* Always program an integral # of max packets for IN transfers. */
41970 +                               len = num_packets * hc->max_packet;
41971 +                       }
41972 +
41973 +                       dma_desc->status.b.n_bytes = len;
41974 +
41975 +                       qh->n_bytes[n_desc] = len;
41976 +
41977 +                       if ((qh->ep_type == UE_CONTROL)
41978 +                           && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
41979 +                               dma_desc->status.b.sup = 1;     /* Setup Packet */
41980 +
41981 +                       dma_desc->status.b.a = 1;       /* Active descriptor */
41982 +                       dma_desc->status.b.sts = 0;
41983 +
41984 +                       dma_desc->buf =
41985 +                           ((unsigned long)hc->xfer_buff & 0xffffffff);
41986 +
41987 +                       /*
41988 +                        * Last descriptor(or single) of IN transfer
41989 +                        * with actual size less than MaxPacket.
41990 +                        */
41991 +                       if (len > hc->xfer_len) {
41992 +                               hc->xfer_len = 0;
41993 +                       } else {
41994 +                               hc->xfer_buff += len;
41995 +                               hc->xfer_len -= len;
41996 +                       }
41997 +
41998 +                       qtd->n_desc++;
41999 +                       n_desc++;
42000 +               }
42001 +               while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
42002 +
42003 +
42004 +               qtd->in_process = 1;
42005 +
42006 +               if (qh->ep_type == UE_CONTROL)
42007 +                       break;
42008 +
42009 +               if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
42010 +                       break;
42011 +       }
42012 +
42013 +       if (n_desc) {
42014 +               /* Request Transfer Complete interrupt for the last descriptor */
42015 +               qh->desc_list[n_desc - 1].status.b.ioc = 1;
42016 +               /* End of List indicator */
42017 +               qh->desc_list[n_desc - 1].status.b.eol = 1;
42018 +
42019 +               hc->ntd = n_desc;
42020 +       }
42021 +}
42022 +
42023 +/**
42024 + * For Control and Bulk endpoints initializes descriptor list
42025 + * and starts the transfer.
42026 + *
42027 + * For Interrupt and Isochronous endpoints initializes descriptor list
42028 + * then updates FrameList, marking appropriate entries as active.
42029 + * In case of Isochronous, the starting descriptor index is calculated based
42030 + * on the scheduled frame, but only on the first transfer descriptor within a session.
42031 + * Then starts the transfer via enabling the channel.
42032 + * For Isochronous endpoint the channel is not halted on XferComplete
42033 + * interrupt so remains assigned to the endpoint(QH) until session is done.
42034 + *
42035 + * @param hcd The HCD state structure for the DWC OTG controller.
42036 + * @param qh The QH to init.
42037 + *
42038 + * @return 0 if successful, negative error code otherwise.
42039 + */
42040 +void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
42041 +{
42042 +       /* Channel is already assigned */
42043 +       dwc_hc_t *hc = qh->channel;
42044 +       uint8_t skip_frames = 0;
42045 +
42046 +       switch (hc->ep_type) {
42047 +       case DWC_OTG_EP_TYPE_CONTROL:
42048 +       case DWC_OTG_EP_TYPE_BULK:
42049 +               init_non_isoc_dma_desc(hcd, qh);
42050 +
42051 +               dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42052 +               break;
42053 +       case DWC_OTG_EP_TYPE_INTR:
42054 +               init_non_isoc_dma_desc(hcd, qh);
42055 +
42056 +               update_frame_list(hcd, qh, 1);
42057 +
42058 +               dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42059 +               break;
42060 +       case DWC_OTG_EP_TYPE_ISOC:
42061 +
42062 +               if (!qh->ntd)
42063 +                       skip_frames = recalc_initial_desc_idx(hcd, qh);
42064 +
42065 +               init_isoc_dma_desc(hcd, qh, skip_frames);
42066 +
42067 +               if (!hc->xfer_started) {
42068 +
42069 +                       update_frame_list(hcd, qh, 1);
42070 +
42071 +                       /*
42072 +                        * Always set to max, instead of actual size.
42073 +                        * Otherwise ntd will be changed with
42074 +                        * channel being enabled. Not recommended.
42075 +                        *
42076 +                        */
42077 +                       hc->ntd = max_desc_num(qh);
42078 +                       /* Enable channel only once for ISOC */
42079 +                       dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
42080 +               }
42081 +
42082 +               break;
42083 +       default:
42084 +
42085 +               break;
42086 +       }
42087 +}
42088 +
42089 +static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
42090 +                                   dwc_hc_t * hc,
42091 +                                   dwc_otg_hc_regs_t * hc_regs,
42092 +                                   dwc_otg_halt_status_e halt_status)
42093 +{
42094 +       struct dwc_otg_hcd_iso_packet_desc *frame_desc;
42095 +       dwc_otg_qtd_t *qtd, *qtd_tmp;
42096 +       dwc_otg_qh_t *qh;
42097 +       dwc_otg_host_dma_desc_t *dma_desc;
42098 +       uint16_t idx, remain;
42099 +       uint8_t urb_compl;
42100 +
42101 +       qh = hc->qh;
42102 +       idx = qh->td_first;
42103 +
42104 +       if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42105 +               DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
42106 +                   qtd->in_process = 0;
42107 +               return;
42108 +       } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
42109 +                  (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
42110 +               /*
42111 +                * Channel is halted in these error cases.
42112 +                * Considered as serious issues.
42113 +                * Complete all URBs marking all frames as failed,
42114 +                * irrespective whether some of the descriptors(frames) succeeded or no.
42115 +                * Pass error code to completion routine as well, to
42116 +                * update urb->status, some of class drivers might use it to stop
42117 +                * queing transfer requests.
42118 +                */
42119 +               int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
42120 +                   ? (-DWC_E_IO)
42121 +                   : (-DWC_E_OVERFLOW);
42122 +
42123 +               DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42124 +                       for (idx = 0; idx < qtd->urb->packet_count; idx++) {
42125 +                               frame_desc = &qtd->urb->iso_descs[idx];
42126 +                               frame_desc->status = err;
42127 +                       }
42128 +                       hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
42129 +                       dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42130 +               }
42131 +               return;
42132 +       }
42133 +
42134 +       DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42135 +
42136 +               if (!qtd->in_process)
42137 +                       break;
42138 +
42139 +               urb_compl = 0;
42140 +
42141 +               do {
42142 +
42143 +                       dma_desc = &qh->desc_list[idx];
42144 +
42145 +                       frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
42146 +                       remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
42147 +
42148 +                       if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
42149 +                               /*
42150 +                                * XactError or, unable to complete all the transactions
42151 +                                * in the scheduled micro-frame/frame,
42152 +                                * both indicated by DMA_DESC_STS_PKTERR.
42153 +                                */
42154 +                               qtd->urb->error_count++;
42155 +                               frame_desc->actual_length = qh->n_bytes[idx] - remain;
42156 +                               frame_desc->status = -DWC_E_PROTOCOL;
42157 +                       } else {
42158 +                               /* Success */
42159 +
42160 +                               frame_desc->actual_length = qh->n_bytes[idx] - remain;
42161 +                               frame_desc->status = 0;
42162 +                       }
42163 +
42164 +                       if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
42165 +                               /*
42166 +                                * urb->status is not used for isoc transfers here.
42167 +                                * The individual frame_desc status are used instead.
42168 +                                */
42169 +
42170 +                               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
42171 +                               dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42172 +
42173 +                               /*
42174 +                                * This check is necessary because urb_dequeue can be called
42175 +                                * from urb complete callback(sound driver example).
42176 +                                * All pending URBs are dequeued there, so no need for
42177 +                                * further processing.
42178 +                                */
42179 +                               if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42180 +                                       return;
42181 +                               }
42182 +
42183 +                               urb_compl = 1;
42184 +
42185 +                       }
42186 +
42187 +                       qh->ntd--;
42188 +
42189 +                       /* Stop if IOC requested descriptor reached */
42190 +                       if (dma_desc->status.b_isoc.ioc) {
42191 +                               idx = desclist_idx_inc(idx, qh->interval, hc->speed);
42192 +                               goto stop_scan;
42193 +                       }
42194 +
42195 +                       idx = desclist_idx_inc(idx, qh->interval, hc->speed);
42196 +
42197 +                       if (urb_compl)
42198 +                               break;
42199 +               }
42200 +               while (idx != qh->td_first);
42201 +       }
42202 +stop_scan:
42203 +       qh->td_first = idx;
42204 +}
42205 +
42206 +uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
42207 +                                      dwc_hc_t * hc,
42208 +                                      dwc_otg_qtd_t * qtd,
42209 +                                      dwc_otg_host_dma_desc_t * dma_desc,
42210 +                                      dwc_otg_halt_status_e halt_status,
42211 +                                      uint32_t n_bytes, uint8_t * xfer_done)
42212 +{
42213 +
42214 +       uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
42215 +       dwc_otg_hcd_urb_t *urb = qtd->urb;
42216 +
42217 +       if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
42218 +               urb->status = -DWC_E_IO;
42219 +               return 1;
42220 +       }
42221 +       if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
42222 +               switch (halt_status) {
42223 +               case DWC_OTG_HC_XFER_STALL:
42224 +                       urb->status = -DWC_E_PIPE;
42225 +                       break;
42226 +               case DWC_OTG_HC_XFER_BABBLE_ERR:
42227 +                       urb->status = -DWC_E_OVERFLOW;
42228 +                       break;
42229 +               case DWC_OTG_HC_XFER_XACT_ERR:
42230 +                       urb->status = -DWC_E_PROTOCOL;
42231 +                       break;
42232 +               default:
42233 +                       DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
42234 +                                 halt_status);
42235 +                       break;
42236 +               }
42237 +               return 1;
42238 +       }
42239 +
42240 +       if (dma_desc->status.b.a == 1) {
42241 +               DWC_DEBUGPL(DBG_HCDV,
42242 +                           "Active descriptor encountered on channel %d\n",
42243 +                           hc->hc_num);
42244 +               return 0;
42245 +       }
42246 +
42247 +       if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
42248 +               if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
42249 +                       urb->actual_length += n_bytes - remain;
42250 +                       if (remain || urb->actual_length == urb->length) {
42251 +                               /*
42252 +                                * For Control Data stage do not set urb->status=0 to prevent
42253 +                                * URB callback. Set it when Status phase done. See below.
42254 +                                */
42255 +                               *xfer_done = 1;
42256 +                       }
42257 +
42258 +               } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
42259 +                       urb->status = 0;
42260 +                       *xfer_done = 1;
42261 +               }
42262 +               /* No handling for SETUP stage */
42263 +       } else {
42264 +               /* BULK and INTR */
42265 +               urb->actual_length += n_bytes - remain;
42266 +               if (remain || urb->actual_length == urb->length) {
42267 +                       urb->status = 0;
42268 +                       *xfer_done = 1;
42269 +               }
42270 +       }
42271 +
42272 +       return 0;
42273 +}
42274 +
42275 +static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
42276 +                                       dwc_hc_t * hc,
42277 +                                       dwc_otg_hc_regs_t * hc_regs,
42278 +                                       dwc_otg_halt_status_e halt_status)
42279 +{
42280 +       dwc_otg_hcd_urb_t *urb = NULL;
42281 +       dwc_otg_qtd_t *qtd, *qtd_tmp;
42282 +       dwc_otg_qh_t *qh;
42283 +       dwc_otg_host_dma_desc_t *dma_desc;
42284 +       uint32_t n_bytes, n_desc, i;
42285 +       uint8_t failed = 0, xfer_done;
42286 +
42287 +       n_desc = 0;
42288 +
42289 +       qh = hc->qh;
42290 +
42291 +       if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
42292 +               DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
42293 +                       qtd->in_process = 0;
42294 +               }
42295 +               return;
42296 +       }
42297 +
42298 +       DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
42299 +
42300 +               urb = qtd->urb;
42301 +
42302 +               n_bytes = 0;
42303 +               xfer_done = 0;
42304 +
42305 +               for (i = 0; i < qtd->n_desc; i++) {
42306 +                       dma_desc = &qh->desc_list[n_desc];
42307 +
42308 +                       n_bytes = qh->n_bytes[n_desc];
42309 +
42310 +                       failed =
42311 +                           update_non_isoc_urb_state_ddma(hcd, hc, qtd,
42312 +                                                          dma_desc,
42313 +                                                          halt_status, n_bytes,
42314 +                                                          &xfer_done);
42315 +
42316 +                       if (failed
42317 +                           || (xfer_done
42318 +                               && (urb->status != -DWC_E_IN_PROGRESS))) {
42319 +
42320 +                               hcd->fops->complete(hcd, urb->priv, urb,
42321 +                                                   urb->status);
42322 +                               dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
42323 +
42324 +                               if (failed)
42325 +                                       goto stop_scan;
42326 +                       } else if (qh->ep_type == UE_CONTROL) {
42327 +                               if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
42328 +                                       if (urb->length > 0) {
42329 +                                               qtd->control_phase = DWC_OTG_CONTROL_DATA;
42330 +                                       } else {
42331 +                                               qtd->control_phase = DWC_OTG_CONTROL_STATUS;
42332 +                                       }
42333 +                                       DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
42334 +                               } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
42335 +                                       if (xfer_done) {
42336 +                                               qtd->control_phase = DWC_OTG_CONTROL_STATUS;
42337 +                                               DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
42338 +                                       } else if (i + 1 == qtd->n_desc) {
42339 +                                               /*
42340 +                                                * Last descriptor for Control data stage which is
42341 +                                                * not completed yet.
42342 +                                                */
42343 +                                               dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
42344 +                                       }
42345 +                               }
42346 +                       }
42347 +
42348 +                       n_desc++;
42349 +               }
42350 +
42351 +       }
42352 +
42353 +stop_scan:
42354 +
42355 +       if (qh->ep_type != UE_CONTROL) {
42356 +               /*
42357 +                * Resetting the data toggle for bulk
42358 +                * and interrupt endpoints in case of stall. See handle_hc_stall_intr()
42359 +                */
42360 +               if (halt_status == DWC_OTG_HC_XFER_STALL)
42361 +                       qh->data_toggle = DWC_OTG_HC_PID_DATA0;
42362 +               else
42363 +                       dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
42364 +       }
42365 +
42366 +       if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
42367 +               hcint_data_t hcint;
42368 +               hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
42369 +               if (hcint.b.nyet) {
42370 +                       /*
42371 +                        * Got a NYET on the last transaction of the transfer. It
42372 +                        * means that the endpoint should be in the PING state at the
42373 +                        * beginning of the next transfer.
42374 +                        */
42375 +                       qh->ping_state = 1;
42376 +                       clear_hc_int(hc_regs, nyet);
42377 +               }
42378 +
42379 +       }
42380 +
42381 +}
42382 +
42383 +/**
42384 + * This function is called from interrupt handlers.
42385 + * Scans the descriptor list, updates URB's status and
42386 + * calls completion routine for the URB if it's done.
42387 + * Releases the channel to be used by other transfers.
42388 + * In case of Isochronous endpoint the channel is not halted until
42389 + * the end of the session, i.e. QTD list is empty.
42390 + * If periodic channel released the FrameList is updated accordingly.
42391 + *
42392 + * Calls transaction selection routines to activate pending transfers.
42393 + *
42394 + * @param hcd The HCD state structure for the DWC OTG controller.
42395 + * @param hc Host channel, the transfer is completed on.
42396 + * @param hc_regs Host channel registers.
42397 + * @param halt_status Reason the channel is being halted,
42398 + *                   or just XferComplete for isochronous transfer
42399 + */
42400 +void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
42401 +                                   dwc_hc_t * hc,
42402 +                                   dwc_otg_hc_regs_t * hc_regs,
42403 +                                   dwc_otg_halt_status_e halt_status)
42404 +{
42405 +       uint8_t continue_isoc_xfer = 0;
42406 +       dwc_otg_transaction_type_e tr_type;
42407 +       dwc_otg_qh_t *qh = hc->qh;
42408 +
42409 +       if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
42410 +
42411 +               complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
42412 +
42413 +               /* Release the channel if halted or session completed */
42414 +               if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
42415 +                   DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
42416 +
42417 +                       /* Halt the channel if session completed */
42418 +                       if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
42419 +                               dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
42420 +                       }
42421 +
42422 +                       release_channel_ddma(hcd, qh);
42423 +                       dwc_otg_hcd_qh_remove(hcd, qh);
42424 +               } else {
42425 +                       /* Keep in assigned schedule to continue transfer */
42426 +                       DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
42427 +                                          &qh->qh_list_entry);
42428 +                       continue_isoc_xfer = 1;
42429 +
42430 +               }
42431 +               /** @todo Consider the case when period exceeds FrameList size.
42432 +                *  Frame Rollover interrupt should be used.
42433 +                */
42434 +       } else {
42435 +               /* Scan descriptor list to complete the URB(s), then release the channel */
42436 +               complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
42437 +
42438 +               release_channel_ddma(hcd, qh);
42439 +               dwc_otg_hcd_qh_remove(hcd, qh);
42440 +
42441 +               if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
42442 +                       /* Add back to inactive non-periodic schedule on normal completion */
42443 +                       dwc_otg_hcd_qh_add(hcd, qh);
42444 +               }
42445 +
42446 +       }
42447 +       tr_type = dwc_otg_hcd_select_transactions(hcd);
42448 +       if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
42449 +               if (continue_isoc_xfer) {
42450 +                       if (tr_type == DWC_OTG_TRANSACTION_NONE) {
42451 +                               tr_type = DWC_OTG_TRANSACTION_PERIODIC;
42452 +                       } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
42453 +                               tr_type = DWC_OTG_TRANSACTION_ALL;
42454 +                       }
42455 +               }
42456 +               dwc_otg_hcd_queue_transactions(hcd, tr_type);
42457 +       }
42458 +}
42459 +
42460 +#endif /* DWC_DEVICE_ONLY */
42461 --- /dev/null
42462 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h
42463 @@ -0,0 +1,417 @@
42464 +/* ==========================================================================
42465 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
42466 + * $Revision: #12 $
42467 + * $Date: 2011/10/26 $
42468 + * $Change: 1873028 $
42469 + *
42470 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
42471 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
42472 + * otherwise expressly agreed to in writing between Synopsys and you.
42473 + *
42474 + * The Software IS NOT an item of Licensed Software or Licensed Product under
42475 + * any End User Software License Agreement or Agreement for Licensed Product
42476 + * with Synopsys or any supplement thereto. You are permitted to use and
42477 + * redistribute this Software in source and binary forms, with or without
42478 + * modification, provided that redistributions of source code must retain this
42479 + * notice. You may not view, use, disclose, copy or distribute this file or
42480 + * any information contained herein except pursuant to this license grant from
42481 + * Synopsys. If you do not agree with this notice, including the disclaimer
42482 + * below, then you are not authorized to use the Software.
42483 + *
42484 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
42485 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42486 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
42487 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
42488 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42489 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
42490 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
42491 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42492 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42493 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
42494 + * DAMAGE.
42495 + * ========================================================================== */
42496 +#ifndef DWC_DEVICE_ONLY
42497 +#ifndef __DWC_HCD_IF_H__
42498 +#define __DWC_HCD_IF_H__
42499 +
42500 +#include "dwc_otg_core_if.h"
42501 +
42502 +/** @file
42503 + * This file defines DWC_OTG HCD Core API.
42504 + */
42505 +
42506 +struct dwc_otg_hcd;
42507 +typedef struct dwc_otg_hcd dwc_otg_hcd_t;
42508 +
42509 +struct dwc_otg_hcd_urb;
42510 +typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
42511 +
42512 +/** @name HCD Function Driver Callbacks */
42513 +/** @{ */
42514 +
42515 +/** This function is called whenever core switches to host mode. */
42516 +typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
42517 +
42518 +/** This function is called when device has been disconnected */
42519 +typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
42520 +
42521 +/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
42522 +typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
42523 +                                                  void *urb_handle,
42524 +                                                  uint32_t * hub_addr,
42525 +                                                  uint32_t * port_addr);
42526 +/** Via this function HCD core gets device speed */
42527 +typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
42528 +                                               void *urb_handle);
42529 +
42530 +/** This function is called when urb is completed */
42531 +typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
42532 +                                             void *urb_handle,
42533 +                                             dwc_otg_hcd_urb_t * dwc_otg_urb,
42534 +                                             int32_t status);
42535 +
42536 +/** Via this function HCD core gets b_hnp_enable parameter */
42537 +typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
42538 +
42539 +struct dwc_otg_hcd_function_ops {
42540 +       dwc_otg_hcd_start_cb_t start;
42541 +       dwc_otg_hcd_disconnect_cb_t disconnect;
42542 +       dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
42543 +       dwc_otg_hcd_speed_from_urb_cb_t speed;
42544 +       dwc_otg_hcd_complete_urb_cb_t complete;
42545 +       dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
42546 +};
42547 +/** @} */
42548 +
42549 +/** @name HCD Core API */
42550 +/** @{ */
42551 +/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
42552 +extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
42553 +
42554 +/** This function should be called to initiate HCD Core.
42555 + *
42556 + * @param hcd The HCD
42557 + * @param core_if The DWC_OTG Core
42558 + *
42559 + * Returns -DWC_E_NO_MEMORY if no enough memory.
42560 + * Returns 0 on success
42561 + */
42562 +extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
42563 +
42564 +/** Frees HCD
42565 + *
42566 + * @param hcd The HCD
42567 + */
42568 +extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
42569 +
42570 +/** This function should be called on every hardware interrupt.
42571 + *
42572 + * @param dwc_otg_hcd The HCD
42573 + *
42574 + * Returns non zero if interrupt is handled
42575 + * Return 0 if interrupt is not handled
42576 + */
42577 +extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
42578 +
42579 +/** This function is used to handle the fast interrupt
42580 + *
42581 + */
42582 +extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void);
42583 +
42584 +/**
42585 + * Returns private data set by
42586 + * dwc_otg_hcd_set_priv_data function.
42587 + *
42588 + * @param hcd The HCD
42589 + */
42590 +extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
42591 +
42592 +/**
42593 + * Set private data.
42594 + *
42595 + * @param hcd The HCD
42596 + * @param priv_data pointer to be stored in private data
42597 + */
42598 +extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
42599 +
42600 +/**
42601 + * This function initializes the HCD Core.
42602 + *
42603 + * @param hcd The HCD
42604 + * @param fops The Function Driver Operations data structure containing pointers to all callbacks.
42605 + *
42606 + * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
42607 + * Returns 0 on success
42608 + */
42609 +extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
42610 +                            struct dwc_otg_hcd_function_ops *fops);
42611 +
42612 +/**
42613 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
42614 + * stopped.
42615 + *
42616 + * @param hcd The HCD
42617 + */
42618 +extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
42619 +
42620 +/**
42621 + * Handles hub class-specific requests.
42622 + *
42623 + * @param dwc_otg_hcd The HCD
42624 + * @param typeReq Request Type
42625 + * @param wValue wValue from control request
42626 + * @param wIndex wIndex from control request
42627 + * @param buf data buffer
42628 + * @param wLength data buffer length
42629 + *
42630 + * Returns -DWC_E_INVALID if invalid argument is passed
42631 + * Returns 0 on success
42632 + */
42633 +extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
42634 +                                  uint16_t typeReq, uint16_t wValue,
42635 +                                  uint16_t wIndex, uint8_t * buf,
42636 +                                  uint16_t wLength);
42637 +
42638 +/**
42639 + * Returns otg port number.
42640 + *
42641 + * @param hcd The HCD
42642 + */
42643 +extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
42644 +
42645 +/**
42646 + * Returns OTG version - either 1.3 or 2.0.
42647 + *
42648 + * @param core_if The core_if structure pointer
42649 + */
42650 +extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
42651 +
42652 +/**
42653 + * Returns 1 if currently core is acting as B host, and 0 otherwise.
42654 + *
42655 + * @param hcd The HCD
42656 + */
42657 +extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
42658 +
42659 +/**
42660 + * Returns current frame number.
42661 + *
42662 + * @param hcd The HCD
42663 + */
42664 +extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
42665 +
42666 +/**
42667 + * Dumps hcd state.
42668 + *
42669 + * @param hcd The HCD
42670 + */
42671 +extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
42672 +
42673 +/**
42674 + * Dump the average frame remaining at SOF. This can be used to
42675 + * determine average interrupt latency. Frame remaining is also shown for
42676 + * start transfer and two additional sample points.
42677 + * Currently this function is not implemented.
42678 + *
42679 + * @param hcd The HCD
42680 + */
42681 +extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
42682 +
42683 +/**
42684 + * Sends LPM transaction to the local device.
42685 + *
42686 + * @param hcd The HCD
42687 + * @param devaddr Device Address
42688 + * @param hird Host initiated resume duration
42689 + * @param bRemoteWake Value of bRemoteWake field in LPM transaction
42690 + *
42691 + * Returns negative value if sending LPM transaction was not succeeded.
42692 + * Returns 0 on success.
42693 + */
42694 +extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
42695 +                               uint8_t hird, uint8_t bRemoteWake);
42696 +
42697 +/* URB interface */
42698 +
42699 +/**
42700 + * Allocates memory for dwc_otg_hcd_urb structure.
42701 + * Allocated memory should be freed by call of DWC_FREE.
42702 + *
42703 + * @param hcd The HCD
42704 + * @param iso_desc_count Count of ISOC descriptors
42705 + * @param atomic_alloc Specefies whether to perform atomic allocation.
42706 + */
42707 +extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
42708 +                                               int iso_desc_count,
42709 +                                               int atomic_alloc);
42710 +
42711 +/**
42712 + * Set pipe information in URB.
42713 + *
42714 + * @param hcd_urb DWC_OTG URB
42715 + * @param devaddr Device Address
42716 + * @param ep_num Endpoint Number
42717 + * @param ep_type Endpoint Type
42718 + * @param ep_dir Endpoint Direction
42719 + * @param mps Max Packet Size
42720 + */
42721 +extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
42722 +                                        uint8_t devaddr, uint8_t ep_num,
42723 +                                        uint8_t ep_type, uint8_t ep_dir,
42724 +                                        uint16_t mps);
42725 +
42726 +/* Transfer flags */
42727 +#define URB_GIVEBACK_ASAP 0x1
42728 +#define URB_SEND_ZERO_PACKET 0x2
42729 +
42730 +/**
42731 + * Sets dwc_otg_hcd_urb parameters.
42732 + *
42733 + * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
42734 + * @param urb_handle Unique handle for request, this will be passed back
42735 + * to function driver in completion callback.
42736 + * @param buf The buffer for the data
42737 + * @param dma The DMA buffer for the data
42738 + * @param buflen Transfer length
42739 + * @param sp Buffer for setup data
42740 + * @param sp_dma DMA address of setup data buffer
42741 + * @param flags Transfer flags
42742 + * @param interval Polling interval for interrupt or isochronous transfers.
42743 + */
42744 +extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
42745 +                                      void *urb_handle, void *buf,
42746 +                                      dwc_dma_t dma, uint32_t buflen, void *sp,
42747 +                                      dwc_dma_t sp_dma, uint32_t flags,
42748 +                                      uint16_t interval);
42749 +
42750 +/** Gets status from dwc_otg_hcd_urb
42751 + *
42752 + * @param dwc_otg_urb DWC_OTG URB
42753 + */
42754 +extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
42755 +
42756 +/** Gets actual length from dwc_otg_hcd_urb
42757 + *
42758 + * @param dwc_otg_urb DWC_OTG URB
42759 + */
42760 +extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
42761 +                                                 dwc_otg_urb);
42762 +
42763 +/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
42764 + *
42765 + * @param dwc_otg_urb DWC_OTG URB
42766 + */
42767 +extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
42768 +                                               dwc_otg_urb);
42769 +
42770 +/** Set ISOC descriptor offset and length
42771 + *
42772 + * @param dwc_otg_urb DWC_OTG URB
42773 + * @param desc_num ISOC descriptor number
42774 + * @param offset Offset from beginig of buffer.
42775 + * @param length Transaction length
42776 + */
42777 +extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
42778 +                                               int desc_num, uint32_t offset,
42779 +                                               uint32_t length);
42780 +
42781 +/** Get status of ISOC descriptor, specified by desc_num
42782 + *
42783 + * @param dwc_otg_urb DWC_OTG URB
42784 + * @param desc_num ISOC descriptor number
42785 + */
42786 +extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
42787 +                                                   dwc_otg_urb, int desc_num);
42788 +
42789 +/** Get actual length of ISOC descriptor, specified by desc_num
42790 + *
42791 + * @param dwc_otg_urb DWC_OTG URB
42792 + * @param desc_num ISOC descriptor number
42793 + */
42794 +extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
42795 +                                                          dwc_otg_urb,
42796 +                                                          int desc_num);
42797 +
42798 +/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
42799 + *
42800 + * @param dwc_otg_hcd The HCD
42801 + * @param dwc_otg_urb DWC_OTG URB
42802 + * @param ep_handle Out parameter for returning endpoint handle
42803 + * @param atomic_alloc Flag to do atomic allocation if needed
42804 + *
42805 + * Returns -DWC_E_NO_DEVICE if no device is connected.
42806 + * Returns -DWC_E_NO_MEMORY if there is no enough memory.
42807 + * Returns 0 on success.
42808 + */
42809 +extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
42810 +                                  dwc_otg_hcd_urb_t * dwc_otg_urb,
42811 +                                  void **ep_handle, int atomic_alloc);
42812 +
42813 +/** De-queue the specified URB
42814 + *
42815 + * @param dwc_otg_hcd The HCD
42816 + * @param dwc_otg_urb DWC_OTG URB
42817 + */
42818 +extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
42819 +                                  dwc_otg_hcd_urb_t * dwc_otg_urb);
42820 +
42821 +/** Frees resources in the DWC_otg controller related to a given endpoint.
42822 + * Any URBs for the endpoint must already be dequeued.
42823 + *
42824 + * @param hcd The HCD
42825 + * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
42826 + * @param retry Number of retries if there are queued transfers.
42827 + *
42828 + * Returns -DWC_E_INVALID if invalid arguments are passed.
42829 + * Returns 0 on success
42830 + */
42831 +extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
42832 +                                       int retry);
42833 +
42834 +/* Resets the data toggle in qh structure. This function can be called from
42835 + * usb_clear_halt routine.
42836 + *
42837 + * @param hcd The HCD
42838 + * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
42839 + *
42840 + * Returns -DWC_E_INVALID if invalid arguments are passed.
42841 + * Returns 0 on success
42842 + */
42843 +extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
42844 +
42845 +/** Returns 1 if status of specified port is changed and 0 otherwise.
42846 + *
42847 + * @param hcd The HCD
42848 + * @param port Port number
42849 + */
42850 +extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
42851 +
42852 +/** Call this function to check if bandwidth was allocated for specified endpoint.
42853 + * Only for ISOC and INTERRUPT endpoints.
42854 + *
42855 + * @param hcd The HCD
42856 + * @param ep_handle Endpoint handle
42857 + */
42858 +extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
42859 +                                             void *ep_handle);
42860 +
42861 +/** Call this function to check if bandwidth was freed for specified endpoint.
42862 + *
42863 + * @param hcd The HCD
42864 + * @param ep_handle Endpoint handle
42865 + */
42866 +extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
42867 +
42868 +/** Returns bandwidth allocated for specified endpoint in microseconds.
42869 + * Only for ISOC and INTERRUPT endpoints.
42870 + *
42871 + * @param hcd The HCD
42872 + * @param ep_handle Endpoint handle
42873 + */
42874 +extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
42875 +                                           void *ep_handle);
42876 +
42877 +/** @} */
42878 +
42879 +#endif /* __DWC_HCD_IF_H__ */
42880 +#endif /* DWC_DEVICE_ONLY */
42881 --- /dev/null
42882 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
42883 @@ -0,0 +1,2714 @@
42884 +/* ==========================================================================
42885 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
42886 + * $Revision: #89 $
42887 + * $Date: 2011/10/20 $
42888 + * $Change: 1869487 $
42889 + *
42890 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
42891 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
42892 + * otherwise expressly agreed to in writing between Synopsys and you.
42893 + *
42894 + * The Software IS NOT an item of Licensed Software or Licensed Product under
42895 + * any End User Software License Agreement or Agreement for Licensed Product
42896 + * with Synopsys or any supplement thereto. You are permitted to use and
42897 + * redistribute this Software in source and binary forms, with or without
42898 + * modification, provided that redistributions of source code must retain this
42899 + * notice. You may not view, use, disclose, copy or distribute this file or
42900 + * any information contained herein except pursuant to this license grant from
42901 + * Synopsys. If you do not agree with this notice, including the disclaimer
42902 + * below, then you are not authorized to use the Software.
42903 + *
42904 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
42905 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42906 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
42907 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
42908 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
42909 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
42910 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
42911 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
42912 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42913 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
42914 + * DAMAGE.
42915 + * ========================================================================== */
42916 +#ifndef DWC_DEVICE_ONLY
42917 +
42918 +#include "dwc_otg_hcd.h"
42919 +#include "dwc_otg_regs.h"
42920 +
42921 +#include <linux/jiffies.h>
42922 +#include <asm/fiq.h>
42923 +
42924 +
42925 +extern bool microframe_schedule;
42926 +
42927 +/** @file
42928 + * This file contains the implementation of the HCD Interrupt handlers.
42929 + */
42930 +
42931 +int fiq_done, int_done;
42932 +
42933 +#ifdef FIQ_DEBUG
42934 +char buffer[1000*16];
42935 +int wptr;
42936 +void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...)
42937 +{
42938 +       FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB;
42939 +       va_list args;
42940 +       char text[17];
42941 +       hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) };
42942 +
42943 +       if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR)
42944 +       {
42945 +               local_fiq_disable();
42946 +               snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937);
42947 +               va_start(args, fmt);
42948 +               vsnprintf(text+8, 9, fmt, args);
42949 +               va_end(args);
42950 +
42951 +               memcpy(buffer + wptr, text, 16);
42952 +               wptr = (wptr + 16) % sizeof(buffer);
42953 +               local_fiq_enable();
42954 +       }
42955 +}
42956 +#endif
42957 +
42958 +/** This function handles interrupts for the HCD. */
42959 +int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
42960 +{
42961 +       int retval = 0;
42962 +       static int last_time;
42963 +       dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
42964 +       gintsts_data_t gintsts;
42965 +       gintmsk_data_t gintmsk;
42966 +       hfnum_data_t hfnum;
42967 +       haintmsk_data_t haintmsk;
42968 +
42969 +#ifdef DEBUG
42970 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
42971 +
42972 +#endif
42973 +
42974 +       gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
42975 +       gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
42976 +
42977 +       /* Exit from ISR if core is hibernated */
42978 +       if (core_if->hibernation_suspend == 1) {
42979 +               goto exit_handler_routine;
42980 +       }
42981 +       DWC_SPINLOCK(dwc_otg_hcd->lock);
42982 +       /* Check if HOST Mode */
42983 +       if (dwc_otg_is_host_mode(core_if)) {
42984 +               if (fiq_enable) {
42985 +                       local_fiq_disable();
42986 +                       fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
42987 +                       /* Pull in from the FIQ's disabled mask */
42988 +                       gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32);
42989 +                       dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0;
42990 +               }
42991 +
42992 +               if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) {
42993 +                       gintsts.b.hcintr = 1;
42994 +               }
42995 +
42996 +               /* Danger will robinson: fake a SOF if necessary */
42997 +               if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) {
42998 +                       gintsts.b.sofintr = 1;
42999 +               }
43000 +               gintsts.d32 &= gintmsk.d32;
43001 +
43002 +               if (fiq_enable) {
43003 +                       fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43004 +                       local_fiq_enable();
43005 +               }
43006 +
43007 +               if (!gintsts.d32) {
43008 +                       goto exit_handler_routine;
43009 +               }
43010 +
43011 +#ifdef DEBUG
43012 +               // We should be OK doing this because the common interrupts should already have been serviced
43013 +               /* Don't print debug message in the interrupt handler on SOF */
43014 +#ifndef DEBUG_SOF
43015 +               if (gintsts.d32 != DWC_SOF_INTR_MASK)
43016 +#endif
43017 +                       DWC_DEBUGPL(DBG_HCDI, "\n");
43018 +#endif
43019 +
43020 +#ifdef DEBUG
43021 +#ifndef DEBUG_SOF
43022 +               if (gintsts.d32 != DWC_SOF_INTR_MASK)
43023 +#endif
43024 +                       DWC_DEBUGPL(DBG_HCDI,
43025 +                                   "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n",
43026 +                                   gintsts.d32, core_if);
43027 +#endif
43028 +               hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum);
43029 +               if (gintsts.b.sofintr) {
43030 +                       retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
43031 +               }
43032 +
43033 +               if (gintsts.b.rxstsqlvl) {
43034 +                       retval |=
43035 +                           dwc_otg_hcd_handle_rx_status_q_level_intr
43036 +                           (dwc_otg_hcd);
43037 +               }
43038 +               if (gintsts.b.nptxfempty) {
43039 +                       retval |=
43040 +                           dwc_otg_hcd_handle_np_tx_fifo_empty_intr
43041 +                           (dwc_otg_hcd);
43042 +               }
43043 +               if (gintsts.b.i2cintr) {
43044 +                       /** @todo Implement i2cintr handler. */
43045 +               }
43046 +               if (gintsts.b.portintr) {
43047 +
43048 +                       gintmsk_data_t gintmsk = { .b.portintr = 1};
43049 +                       retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
43050 +                       if (fiq_enable) {
43051 +                               local_fiq_disable();
43052 +                               fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43053 +                               DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
43054 +                               fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43055 +                               local_fiq_enable();
43056 +                       } else {
43057 +                               DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
43058 +                       }
43059 +               }
43060 +               if (gintsts.b.hcintr) {
43061 +                       retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
43062 +               }
43063 +               if (gintsts.b.ptxfempty) {
43064 +                       retval |=
43065 +                           dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
43066 +                           (dwc_otg_hcd);
43067 +               }
43068 +#ifdef DEBUG
43069 +#ifndef DEBUG_SOF
43070 +               if (gintsts.d32 != DWC_SOF_INTR_MASK)
43071 +#endif
43072 +               {
43073 +                       DWC_DEBUGPL(DBG_HCDI,
43074 +                                   "DWC OTG HCD Finished Servicing Interrupts\n");
43075 +                       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
43076 +                                   DWC_READ_REG32(&global_regs->gintsts));
43077 +                       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
43078 +                                   DWC_READ_REG32(&global_regs->gintmsk));
43079 +               }
43080 +#endif
43081 +
43082 +#ifdef DEBUG
43083 +#ifndef DEBUG_SOF
43084 +               if (gintsts.d32 != DWC_SOF_INTR_MASK)
43085 +#endif
43086 +                       DWC_DEBUGPL(DBG_HCDI, "\n");
43087 +#endif
43088 +
43089 +       }
43090 +
43091 +exit_handler_routine:
43092 +       if (fiq_enable) {
43093 +               gintmsk_data_t gintmsk_new;
43094 +               haintmsk_data_t haintmsk_new;
43095 +               local_fiq_disable();
43096 +               fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43097 +               gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32;
43098 +               if(fiq_fsm_enable)
43099 +                       haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32;
43100 +               else
43101 +                       haintmsk_new.d32 = 0x0000FFFF;
43102 +
43103 +               /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */
43104 +               if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) {
43105 +                               DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16));
43106 +                               if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) {
43107 +                                       fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR");
43108 +                                       DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16)));
43109 +                                       while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17)))
43110 +                                               ;
43111 +                                       DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31));
43112 +                                       dwc_otg_hcd->fiq_state->mphi_int_count = 0;
43113 +                               }
43114 +                               int_done++;
43115 +               }
43116 +               haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
43117 +               /* Re-enable interrupts that the FIQ masked (first time round) */
43118 +               FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32);
43119 +               fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43120 +               local_fiq_enable();
43121 +
43122 +               if ((jiffies / HZ) > last_time) {
43123 +                       //dwc_otg_qh_t *qh;
43124 +                       //dwc_list_link_t *cur;
43125 +                       /* Once a second output the fiq and irq numbers, useful for debug */
43126 +                       last_time = jiffies / HZ;
43127 +               //       DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d",
43128 +               //      dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels,
43129 +               //      dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done);
43130 +                        //printk(KERN_WARNING "Periodic queues:\n");
43131 +               }
43132 +       }
43133 +
43134 +       DWC_SPINUNLOCK(dwc_otg_hcd->lock);
43135 +       return retval;
43136 +}
43137 +
43138 +#ifdef DWC_TRACK_MISSED_SOFS
43139 +
43140 +#warning Compiling code to track missed SOFs
43141 +#define FRAME_NUM_ARRAY_SIZE 1000
43142 +/**
43143 + * This function is for debug only.
43144 + */
43145 +static inline void track_missed_sofs(uint16_t curr_frame_number)
43146 +{
43147 +       static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
43148 +       static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
43149 +       static int frame_num_idx = 0;
43150 +       static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
43151 +       static int dumped_frame_num_array = 0;
43152 +
43153 +       if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
43154 +               if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
43155 +                   curr_frame_number) {
43156 +                       frame_num_array[frame_num_idx] = curr_frame_number;
43157 +                       last_frame_num_array[frame_num_idx++] = last_frame_num;
43158 +               }
43159 +       } else if (!dumped_frame_num_array) {
43160 +               int i;
43161 +               DWC_PRINTF("Frame     Last Frame\n");
43162 +               DWC_PRINTF("-----     ----------\n");
43163 +               for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
43164 +                       DWC_PRINTF("0x%04x    0x%04x\n",
43165 +                                  frame_num_array[i], last_frame_num_array[i]);
43166 +               }
43167 +               dumped_frame_num_array = 1;
43168 +       }
43169 +       last_frame_num = curr_frame_number;
43170 +}
43171 +#endif
43172 +
43173 +/**
43174 + * Handles the start-of-frame interrupt in host mode. Non-periodic
43175 + * transactions may be queued to the DWC_otg controller for the current
43176 + * (micro)frame. Periodic transactions may be queued to the controller for the
43177 + * next (micro)frame.
43178 + */
43179 +int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
43180 +{
43181 +       hfnum_data_t hfnum;
43182 +       gintsts_data_t gintsts = { .d32 = 0 };
43183 +       dwc_list_link_t *qh_entry;
43184 +       dwc_otg_qh_t *qh;
43185 +       dwc_otg_transaction_type_e tr_type;
43186 +       int did_something = 0;
43187 +       int32_t next_sched_frame = -1;
43188 +
43189 +       hfnum.d32 =
43190 +           DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
43191 +
43192 +#ifdef DEBUG_SOF
43193 +       DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
43194 +#endif
43195 +       hcd->frame_number = hfnum.b.frnum;
43196 +
43197 +#ifdef DEBUG
43198 +       hcd->frrem_accum += hfnum.b.frrem;
43199 +       hcd->frrem_samples++;
43200 +#endif
43201 +
43202 +#ifdef DWC_TRACK_MISSED_SOFS
43203 +       track_missed_sofs(hcd->frame_number);
43204 +#endif
43205 +       /* Determine whether any periodic QHs should be executed. */
43206 +       qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
43207 +       while (qh_entry != &hcd->periodic_sched_inactive) {
43208 +               qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
43209 +               qh_entry = qh_entry->next;
43210 +               if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
43211 +
43212 +                       /*
43213 +                        * Move QH to the ready list to be executed next
43214 +                        * (micro)frame.
43215 +                        */
43216 +                       DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
43217 +                                          &qh->qh_list_entry);
43218 +
43219 +                       did_something = 1;
43220 +               }
43221 +               else
43222 +               {
43223 +                       if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame))
43224 +                       {
43225 +                               next_sched_frame = qh->sched_frame;
43226 +                       }
43227 +               }
43228 +       }
43229 +       if (fiq_enable)
43230 +               hcd->fiq_state->next_sched_frame = next_sched_frame;
43231 +
43232 +       tr_type = dwc_otg_hcd_select_transactions(hcd);
43233 +       if (tr_type != DWC_OTG_TRANSACTION_NONE) {
43234 +               dwc_otg_hcd_queue_transactions(hcd, tr_type);
43235 +               did_something = 1;
43236 +       }
43237 +
43238 +       /* Clear interrupt - but do not trample on the FIQ sof */
43239 +       if (!fiq_fsm_enable) {
43240 +               gintsts.b.sofintr = 1;
43241 +               DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
43242 +       }
43243 +       return 1;
43244 +}
43245 +
43246 +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
43247 + * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
43248 + * memory if the DWC_otg controller is operating in Slave mode. */
43249 +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43250 +{
43251 +       host_grxsts_data_t grxsts;
43252 +       dwc_hc_t *hc = NULL;
43253 +
43254 +       DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
43255 +
43256 +       grxsts.d32 =
43257 +           DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
43258 +
43259 +       hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
43260 +       if (!hc) {
43261 +               DWC_ERROR("Unable to get corresponding channel\n");
43262 +               return 0;
43263 +       }
43264 +
43265 +       /* Packet Status */
43266 +       DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
43267 +       DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
43268 +       DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
43269 +                   hc->data_pid_start);
43270 +       DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
43271 +
43272 +       switch (grxsts.b.pktsts) {
43273 +       case DWC_GRXSTS_PKTSTS_IN:
43274 +               /* Read the data into the host buffer. */
43275 +               if (grxsts.b.bcnt > 0) {
43276 +                       dwc_otg_read_packet(dwc_otg_hcd->core_if,
43277 +                                           hc->xfer_buff, grxsts.b.bcnt);
43278 +
43279 +                       /* Update the HC fields for the next packet received. */
43280 +                       hc->xfer_count += grxsts.b.bcnt;
43281 +                       hc->xfer_buff += grxsts.b.bcnt;
43282 +               }
43283 +
43284 +       case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
43285 +       case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
43286 +       case DWC_GRXSTS_PKTSTS_CH_HALTED:
43287 +               /* Handled in interrupt, just ignore data */
43288 +               break;
43289 +       default:
43290 +               DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
43291 +                         grxsts.b.pktsts);
43292 +               break;
43293 +       }
43294 +
43295 +       return 1;
43296 +}
43297 +
43298 +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
43299 + * data packets may be written to the FIFO for OUT transfers. More requests
43300 + * may be written to the non-periodic request queue for IN transfers. This
43301 + * interrupt is enabled only in Slave mode. */
43302 +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43303 +{
43304 +       DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
43305 +       dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
43306 +                                      DWC_OTG_TRANSACTION_NON_PERIODIC);
43307 +       return 1;
43308 +}
43309 +
43310 +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
43311 + * packets may be written to the FIFO for OUT transfers. More requests may be
43312 + * written to the periodic request queue for IN transfers. This interrupt is
43313 + * enabled only in Slave mode. */
43314 +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43315 +{
43316 +       DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
43317 +       dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
43318 +                                      DWC_OTG_TRANSACTION_PERIODIC);
43319 +       return 1;
43320 +}
43321 +
43322 +/** There are multiple conditions that can cause a port interrupt. This function
43323 + * determines which interrupt conditions have occurred and handles them
43324 + * appropriately. */
43325 +int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43326 +{
43327 +       int retval = 0;
43328 +       hprt0_data_t hprt0;
43329 +       hprt0_data_t hprt0_modify;
43330 +
43331 +       hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43332 +       hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43333 +
43334 +       /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
43335 +        * GINTSTS */
43336 +
43337 +       hprt0_modify.b.prtena = 0;
43338 +       hprt0_modify.b.prtconndet = 0;
43339 +       hprt0_modify.b.prtenchng = 0;
43340 +       hprt0_modify.b.prtovrcurrchng = 0;
43341 +
43342 +       /* Port Connect Detected
43343 +        * Set flag and clear if detected */
43344 +       if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
43345 +               // Dont modify port status if we are in hibernation state
43346 +               hprt0_modify.b.prtconndet = 1;
43347 +               hprt0_modify.b.prtenchng = 1;
43348 +               DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
43349 +               hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
43350 +               return retval;
43351 +       }
43352 +
43353 +       if (hprt0.b.prtconndet) {
43354 +               /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */
43355 +               if (dwc_otg_hcd->core_if->adp_enable &&
43356 +                               dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
43357 +                       DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
43358 +                       DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
43359 +                       dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
43360 +                       /* TODO - check if this is required, as
43361 +                        * host initialization was already performed
43362 +                        * after initial ADP probing
43363 +                        */
43364 +                       /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
43365 +                       dwc_otg_core_init(dwc_otg_hcd->core_if);
43366 +                       dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
43367 +                       cil_hcd_start(dwc_otg_hcd->core_if);*/
43368 +               } else {
43369 +
43370 +                       DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
43371 +                                   "Port Connect Detected--\n", hprt0.d32);
43372 +                       dwc_otg_hcd->flags.b.port_connect_status_change = 1;
43373 +                       dwc_otg_hcd->flags.b.port_connect_status = 1;
43374 +                       hprt0_modify.b.prtconndet = 1;
43375 +
43376 +                       /* B-Device has connected, Delete the connection timer. */
43377 +                       DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
43378 +               }
43379 +               /* The Hub driver asserts a reset when it sees port connect
43380 +                * status change flag */
43381 +               retval |= 1;
43382 +       }
43383 +
43384 +       /* Port Enable Changed
43385 +        * Clear if detected - Set internal flag if disabled */
43386 +       if (hprt0.b.prtenchng) {
43387 +               DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
43388 +                           "Port Enable Changed--\n", hprt0.d32);
43389 +               hprt0_modify.b.prtenchng = 1;
43390 +               if (hprt0.b.prtena == 1) {
43391 +                       hfir_data_t hfir;
43392 +                       int do_reset = 0;
43393 +                       dwc_otg_core_params_t *params =
43394 +                           dwc_otg_hcd->core_if->core_params;
43395 +                       dwc_otg_core_global_regs_t *global_regs =
43396 +                           dwc_otg_hcd->core_if->core_global_regs;
43397 +                       dwc_otg_host_if_t *host_if =
43398 +                           dwc_otg_hcd->core_if->host_if;
43399 +
43400 +                       /* Every time when port enables calculate
43401 +                        * HFIR.FrInterval
43402 +                        */
43403 +                       hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
43404 +                       hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
43405 +                       DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
43406 +
43407 +                       /* Check if we need to adjust the PHY clock speed for
43408 +                        * low power and adjust it */
43409 +                       if (params->host_support_fs_ls_low_power) {
43410 +                               gusbcfg_data_t usbcfg;
43411 +
43412 +                               usbcfg.d32 =
43413 +                                   DWC_READ_REG32(&global_regs->gusbcfg);
43414 +
43415 +                               if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
43416 +                                   || hprt0.b.prtspd ==
43417 +                                   DWC_HPRT0_PRTSPD_FULL_SPEED) {
43418 +                                       /*
43419 +                                        * Low power
43420 +                                        */
43421 +                                       hcfg_data_t hcfg;
43422 +                                       if (usbcfg.b.phylpwrclksel == 0) {
43423 +                                               /* Set PHY low power clock select for FS/LS devices */
43424 +                                               usbcfg.b.phylpwrclksel = 1;
43425 +                                               DWC_WRITE_REG32
43426 +                                                   (&global_regs->gusbcfg,
43427 +                                                    usbcfg.d32);
43428 +                                               do_reset = 1;
43429 +                                       }
43430 +
43431 +                                       hcfg.d32 =
43432 +                                           DWC_READ_REG32
43433 +                                           (&host_if->host_global_regs->hcfg);
43434 +
43435 +                                       if (hprt0.b.prtspd ==
43436 +                                           DWC_HPRT0_PRTSPD_LOW_SPEED
43437 +                                           && params->host_ls_low_power_phy_clk
43438 +                                           ==
43439 +                                           DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
43440 +                                       {
43441 +                                               /* 6 MHZ */
43442 +                                               DWC_DEBUGPL(DBG_CIL,
43443 +                                                           "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
43444 +                                               if (hcfg.b.fslspclksel !=
43445 +                                                   DWC_HCFG_6_MHZ) {
43446 +                                                       hcfg.b.fslspclksel =
43447 +                                                           DWC_HCFG_6_MHZ;
43448 +                                                       DWC_WRITE_REG32
43449 +                                                           (&host_if->host_global_regs->hcfg,
43450 +                                                            hcfg.d32);
43451 +                                                       do_reset = 1;
43452 +                                               }
43453 +                                       } else {
43454 +                                               /* 48 MHZ */
43455 +                                               DWC_DEBUGPL(DBG_CIL,
43456 +                                                           "FS_PHY programming HCFG to 48 MHz ()\n");
43457 +                                               if (hcfg.b.fslspclksel !=
43458 +                                                   DWC_HCFG_48_MHZ) {
43459 +                                                       hcfg.b.fslspclksel =
43460 +                                                           DWC_HCFG_48_MHZ;
43461 +                                                       DWC_WRITE_REG32
43462 +                                                           (&host_if->host_global_regs->hcfg,
43463 +                                                            hcfg.d32);
43464 +                                                       do_reset = 1;
43465 +                                               }
43466 +                                       }
43467 +                               } else {
43468 +                                       /*
43469 +                                        * Not low power
43470 +                                        */
43471 +                                       if (usbcfg.b.phylpwrclksel == 1) {
43472 +                                               usbcfg.b.phylpwrclksel = 0;
43473 +                                               DWC_WRITE_REG32
43474 +                                                   (&global_regs->gusbcfg,
43475 +                                                    usbcfg.d32);
43476 +                                               do_reset = 1;
43477 +                                       }
43478 +                               }
43479 +
43480 +                               if (do_reset) {
43481 +                                       DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
43482 +                               }
43483 +                       }
43484 +
43485 +                       if (!do_reset) {
43486 +                               /* Port has been enabled set the reset change flag */
43487 +                               dwc_otg_hcd->flags.b.port_reset_change = 1;
43488 +                       }
43489 +               } else {
43490 +                       dwc_otg_hcd->flags.b.port_enable_change = 1;
43491 +               }
43492 +               retval |= 1;
43493 +       }
43494 +
43495 +       /** Overcurrent Change Interrupt */
43496 +       if (hprt0.b.prtovrcurrchng) {
43497 +               DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
43498 +                           "Port Overcurrent Changed--\n", hprt0.d32);
43499 +               dwc_otg_hcd->flags.b.port_over_current_change = 1;
43500 +               hprt0_modify.b.prtovrcurrchng = 1;
43501 +               retval |= 1;
43502 +       }
43503 +
43504 +       /* Clear Port Interrupts */
43505 +       DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
43506 +
43507 +       return retval;
43508 +}
43509 +
43510 +/** This interrupt indicates that one or more host channels has a pending
43511 + * interrupt. There are multiple conditions that can cause each host channel
43512 + * interrupt. This function determines which conditions have occurred for each
43513 + * host channel interrupt and handles them appropriately. */
43514 +int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
43515 +{
43516 +       int i;
43517 +       int retval = 0;
43518 +       haint_data_t haint = { .d32 = 0 } ;
43519 +
43520 +       /* Clear appropriate bits in HCINTn to clear the interrupt bit in
43521 +        * GINTSTS */
43522 +
43523 +       if (!fiq_fsm_enable)
43524 +               haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
43525 +
43526 +       // Overwrite with saved interrupts from fiq handler
43527 +       if(fiq_fsm_enable)
43528 +       {
43529 +               /* check the mask? */
43530 +               local_fiq_disable();
43531 +               fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
43532 +               haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint);
43533 +               dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0;
43534 +               fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
43535 +               local_fiq_enable();
43536 +       }
43537 +
43538 +       for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
43539 +               if (haint.b2.chint & (1 << i)) {
43540 +                       retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
43541 +               }
43542 +       }
43543 +
43544 +       return retval;
43545 +}
43546 +
43547 +/**
43548 + * Gets the actual length of a transfer after the transfer halts. _halt_status
43549 + * holds the reason for the halt.
43550 + *
43551 + * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
43552 + * *short_read is set to 1 upon return if less than the requested
43553 + * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
43554 + * return. short_read may also be NULL on entry, in which case it remains
43555 + * unchanged.
43556 + */
43557 +static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
43558 +                                      dwc_otg_hc_regs_t * hc_regs,
43559 +                                      dwc_otg_qtd_t * qtd,
43560 +                                      dwc_otg_halt_status_e halt_status,
43561 +                                      int *short_read)
43562 +{
43563 +       hctsiz_data_t hctsiz;
43564 +       uint32_t length;
43565 +
43566 +       if (short_read != NULL) {
43567 +               *short_read = 0;
43568 +       }
43569 +       hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
43570 +
43571 +       if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
43572 +               if (hc->ep_is_in) {
43573 +                       length = hc->xfer_len - hctsiz.b.xfersize;
43574 +                       if (short_read != NULL) {
43575 +                               *short_read = (hctsiz.b.xfersize != 0);
43576 +                       }
43577 +               } else if (hc->qh->do_split) {
43578 +                               //length = split_out_xfersize[hc->hc_num];
43579 +                               length = qtd->ssplit_out_xfer_count;
43580 +               } else {
43581 +                       length = hc->xfer_len;
43582 +               }
43583 +       } else {
43584 +               /*
43585 +                * Must use the hctsiz.pktcnt field to determine how much data
43586 +                * has been transferred. This field reflects the number of
43587 +                * packets that have been transferred via the USB. This is
43588 +                * always an integral number of packets if the transfer was
43589 +                * halted before its normal completion. (Can't use the
43590 +                * hctsiz.xfersize field because that reflects the number of
43591 +                * bytes transferred via the AHB, not the USB).
43592 +                */
43593 +               length =
43594 +                   (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
43595 +       }
43596 +
43597 +       return length;
43598 +}
43599 +
43600 +/**
43601 + * Updates the state of the URB after a Transfer Complete interrupt on the
43602 + * host channel. Updates the actual_length field of the URB based on the
43603 + * number of bytes transferred via the host channel. Sets the URB status
43604 + * if the data transfer is finished.
43605 + *
43606 + * @return 1 if the data transfer specified by the URB is completely finished,
43607 + * 0 otherwise.
43608 + */
43609 +static int update_urb_state_xfer_comp(dwc_hc_t * hc,
43610 +                                     dwc_otg_hc_regs_t * hc_regs,
43611 +                                     dwc_otg_hcd_urb_t * urb,
43612 +                                     dwc_otg_qtd_t * qtd)
43613 +{
43614 +       int xfer_done = 0;
43615 +       int short_read = 0;
43616 +
43617 +       int xfer_length;
43618 +
43619 +       xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
43620 +                                            DWC_OTG_HC_XFER_COMPLETE,
43621 +                                            &short_read);
43622 +
43623 +       /* non DWORD-aligned buffer case handling. */
43624 +       if (hc->align_buff && xfer_length && hc->ep_is_in) {
43625 +               dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
43626 +                          xfer_length);
43627 +       }
43628 +
43629 +       urb->actual_length += xfer_length;
43630 +
43631 +       if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
43632 +           (urb->flags & URB_SEND_ZERO_PACKET)
43633 +           && (urb->actual_length == urb->length)
43634 +           && !(urb->length % hc->max_packet)) {
43635 +               xfer_done = 0;
43636 +       } else if (short_read || urb->actual_length >= urb->length) {
43637 +               xfer_done = 1;
43638 +               urb->status = 0;
43639 +       }
43640 +
43641 +#ifdef DEBUG
43642 +       {
43643 +               hctsiz_data_t hctsiz;
43644 +               hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
43645 +               DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
43646 +                           __func__, (hc->ep_is_in ? "IN" : "OUT"),
43647 +                           hc->hc_num);
43648 +               DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
43649 +               DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
43650 +                           hctsiz.b.xfersize);
43651 +               DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
43652 +                           urb->length);
43653 +               DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
43654 +                           urb->actual_length);
43655 +               DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
43656 +                           short_read, xfer_done);
43657 +       }
43658 +#endif
43659 +
43660 +       return xfer_done;
43661 +}
43662 +
43663 +/*
43664 + * Save the starting data toggle for the next transfer. The data toggle is
43665 + * saved in the QH for non-control transfers and it's saved in the QTD for
43666 + * control transfers.
43667 + */
43668 +void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
43669 +                            dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
43670 +{
43671 +       hctsiz_data_t hctsiz;
43672 +       hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
43673 +
43674 +       if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
43675 +               dwc_otg_qh_t *qh = hc->qh;
43676 +               if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
43677 +                       qh->data_toggle = DWC_OTG_HC_PID_DATA0;
43678 +               } else {
43679 +                       qh->data_toggle = DWC_OTG_HC_PID_DATA1;
43680 +               }
43681 +       } else {
43682 +               if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
43683 +                       qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
43684 +               } else {
43685 +                       qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
43686 +               }
43687 +       }
43688 +}
43689 +
43690 +/**
43691 + * Updates the state of an Isochronous URB when the transfer is stopped for
43692 + * any reason. The fields of the current entry in the frame descriptor array
43693 + * are set based on the transfer state and the input _halt_status. Completes
43694 + * the Isochronous URB if all the URB frames have been completed.
43695 + *
43696 + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
43697 + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
43698 + */
43699 +static dwc_otg_halt_status_e
43700 +update_isoc_urb_state(dwc_otg_hcd_t * hcd,
43701 +                     dwc_hc_t * hc,
43702 +                     dwc_otg_hc_regs_t * hc_regs,
43703 +                     dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
43704 +{
43705 +       dwc_otg_hcd_urb_t *urb = qtd->urb;
43706 +       dwc_otg_halt_status_e ret_val = halt_status;
43707 +       struct dwc_otg_hcd_iso_packet_desc *frame_desc;
43708 +
43709 +       frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
43710 +       switch (halt_status) {
43711 +       case DWC_OTG_HC_XFER_COMPLETE:
43712 +               frame_desc->status = 0;
43713 +               frame_desc->actual_length =
43714 +                   get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
43715 +
43716 +               /* non DWORD-aligned buffer case handling. */
43717 +               if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
43718 +                       dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
43719 +                                  hc->qh->dw_align_buf, frame_desc->actual_length);
43720 +               }
43721 +
43722 +               break;
43723 +       case DWC_OTG_HC_XFER_FRAME_OVERRUN:
43724 +               urb->error_count++;
43725 +               if (hc->ep_is_in) {
43726 +                       frame_desc->status = -DWC_E_NO_STREAM_RES;
43727 +               } else {
43728 +                       frame_desc->status = -DWC_E_COMMUNICATION;
43729 +               }
43730 +               frame_desc->actual_length = 0;
43731 +               break;
43732 +       case DWC_OTG_HC_XFER_BABBLE_ERR:
43733 +               urb->error_count++;
43734 +               frame_desc->status = -DWC_E_OVERFLOW;
43735 +               /* Don't need to update actual_length in this case. */
43736 +               break;
43737 +       case DWC_OTG_HC_XFER_XACT_ERR:
43738 +               urb->error_count++;
43739 +               frame_desc->status = -DWC_E_PROTOCOL;
43740 +               frame_desc->actual_length =
43741 +                   get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
43742 +
43743 +               /* non DWORD-aligned buffer case handling. */
43744 +               if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
43745 +                       dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
43746 +                                  hc->qh->dw_align_buf, frame_desc->actual_length);
43747 +               }
43748 +               /* Skip whole frame */
43749 +               if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
43750 +                   hc->ep_is_in && hcd->core_if->dma_enable) {
43751 +                       qtd->complete_split = 0;
43752 +                       qtd->isoc_split_offset = 0;
43753 +               }
43754 +
43755 +               break;
43756 +       default:
43757 +               DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
43758 +               break;
43759 +       }
43760 +       if (++qtd->isoc_frame_index == urb->packet_count) {
43761 +               /*
43762 +                * urb->status is not used for isoc transfers.
43763 +                * The individual frame_desc statuses are used instead.
43764 +                */
43765 +               hcd->fops->complete(hcd, urb->priv, urb, 0);
43766 +               ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
43767 +       } else {
43768 +               ret_val = DWC_OTG_HC_XFER_COMPLETE;
43769 +       }
43770 +       return ret_val;
43771 +}
43772 +
43773 +/**
43774 + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
43775 + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
43776 + * still linked to the QH, the QH is added to the end of the inactive
43777 + * non-periodic schedule. For periodic QHs, removes the QH from the periodic
43778 + * schedule if no more QTDs are linked to the QH.
43779 + */
43780 +static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
43781 +{
43782 +       int continue_split = 0;
43783 +       dwc_otg_qtd_t *qtd;
43784 +
43785 +       DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
43786 +
43787 +       qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
43788 +
43789 +       if (qtd->complete_split) {
43790 +               continue_split = 1;
43791 +       } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
43792 +                  qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
43793 +               continue_split = 1;
43794 +       }
43795 +
43796 +       if (free_qtd) {
43797 +               dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
43798 +               continue_split = 0;
43799 +       }
43800 +
43801 +       qh->channel = NULL;
43802 +       dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
43803 +}
43804 +
43805 +/**
43806 + * Releases a host channel for use by other transfers. Attempts to select and
43807 + * queue more transactions since at least one host channel is available.
43808 + *
43809 + * @param hcd The HCD state structure.
43810 + * @param hc The host channel to release.
43811 + * @param qtd The QTD associated with the host channel. This QTD may be freed
43812 + * if the transfer is complete or an error has occurred.
43813 + * @param halt_status Reason the channel is being released. This status
43814 + * determines the actions taken by this function.
43815 + */
43816 +static void release_channel(dwc_otg_hcd_t * hcd,
43817 +                           dwc_hc_t * hc,
43818 +                           dwc_otg_qtd_t * qtd,
43819 +                           dwc_otg_halt_status_e halt_status)
43820 +{
43821 +       dwc_otg_transaction_type_e tr_type;
43822 +       int free_qtd;
43823 +       dwc_irqflags_t flags;
43824 +       dwc_spinlock_t *channel_lock = hcd->channel_lock;
43825 +
43826 +       int hog_port = 0;
43827 +
43828 +       DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d, xfer_len %d\n",
43829 +                   __func__, hc->hc_num, halt_status, hc->xfer_len);
43830 +
43831 +       if(fiq_fsm_enable && hc->do_split) {
43832 +               if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) {
43833 +                       if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID ||
43834 +                                       hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) {
43835 +                               hog_port = 0;
43836 +                       }
43837 +               }
43838 +       }
43839 +
43840 +       switch (halt_status) {
43841 +       case DWC_OTG_HC_XFER_URB_COMPLETE:
43842 +               free_qtd = 1;
43843 +               break;
43844 +       case DWC_OTG_HC_XFER_AHB_ERR:
43845 +       case DWC_OTG_HC_XFER_STALL:
43846 +       case DWC_OTG_HC_XFER_BABBLE_ERR:
43847 +               free_qtd = 1;
43848 +               break;
43849 +       case DWC_OTG_HC_XFER_XACT_ERR:
43850 +               if (qtd->error_count >= 3) {
43851 +                       DWC_DEBUGPL(DBG_HCDV,
43852 +                                   "  Complete URB with transaction error\n");
43853 +                       free_qtd = 1;
43854 +                       qtd->urb->status = -DWC_E_PROTOCOL;
43855 +                       hcd->fops->complete(hcd, qtd->urb->priv,
43856 +                                           qtd->urb, -DWC_E_PROTOCOL);
43857 +               } else {
43858 +                       free_qtd = 0;
43859 +               }
43860 +               break;
43861 +       case DWC_OTG_HC_XFER_URB_DEQUEUE:
43862 +               /*
43863 +                * The QTD has already been removed and the QH has been
43864 +                * deactivated. Don't want to do anything except release the
43865 +                * host channel and try to queue more transfers.
43866 +                */
43867 +               goto cleanup;
43868 +       case DWC_OTG_HC_XFER_NO_HALT_STATUS:
43869 +               free_qtd = 0;
43870 +               break;
43871 +       case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
43872 +               DWC_DEBUGPL(DBG_HCDV,
43873 +                       "  Complete URB with I/O error\n");
43874 +               free_qtd = 1;
43875 +               qtd->urb->status = -DWC_E_IO;
43876 +               hcd->fops->complete(hcd, qtd->urb->priv,
43877 +                       qtd->urb, -DWC_E_IO);
43878 +               break;
43879 +       default:
43880 +               free_qtd = 0;
43881 +               break;
43882 +       }
43883 +
43884 +       deactivate_qh(hcd, hc->qh, free_qtd);
43885 +
43886 +cleanup:
43887 +       /*
43888 +        * Release the host channel for use by other transfers. The cleanup
43889 +        * function clears the channel interrupt enables and conditions, so
43890 +        * there's no need to clear the Channel Halted interrupt separately.
43891 +        */
43892 +       if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH)
43893 +               dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num);
43894 +       dwc_otg_hc_cleanup(hcd->core_if, hc);
43895 +       DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
43896 +
43897 +       if (!microframe_schedule) {
43898 +               switch (hc->ep_type) {
43899 +               case DWC_OTG_EP_TYPE_CONTROL:
43900 +               case DWC_OTG_EP_TYPE_BULK:
43901 +                       hcd->non_periodic_channels--;
43902 +                       break;
43903 +
43904 +               default:
43905 +                       /*
43906 +                        * Don't release reservations for periodic channels here.
43907 +                        * That's done when a periodic transfer is descheduled (i.e.
43908 +                        * when the QH is removed from the periodic schedule).
43909 +                        */
43910 +                       break;
43911 +               }
43912 +       } else {
43913 +
43914 +               DWC_SPINLOCK_IRQSAVE(channel_lock, &flags);
43915 +               hcd->available_host_channels++;
43916 +               fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels);
43917 +               DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags);
43918 +       }
43919 +
43920 +       /* Try to queue more transfers now that there's a free channel. */
43921 +       tr_type = dwc_otg_hcd_select_transactions(hcd);
43922 +       if (tr_type != DWC_OTG_TRANSACTION_NONE) {
43923 +               dwc_otg_hcd_queue_transactions(hcd, tr_type);
43924 +       }
43925 +}
43926 +
43927 +/**
43928 + * Halts a host channel. If the channel cannot be halted immediately because
43929 + * the request queue is full, this function ensures that the FIFO empty
43930 + * interrupt for the appropriate queue is enabled so that the halt request can
43931 + * be queued when there is space in the request queue.
43932 + *
43933 + * This function may also be called in DMA mode. In that case, the channel is
43934 + * simply released since the core always halts the channel automatically in
43935 + * DMA mode.
43936 + */
43937 +static void halt_channel(dwc_otg_hcd_t * hcd,
43938 +                        dwc_hc_t * hc,
43939 +                        dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
43940 +{
43941 +       if (hcd->core_if->dma_enable) {
43942 +               release_channel(hcd, hc, qtd, halt_status);
43943 +               return;
43944 +       }
43945 +
43946 +       /* Slave mode processing... */
43947 +       dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
43948 +
43949 +       if (hc->halt_on_queue) {
43950 +               gintmsk_data_t gintmsk = {.d32 = 0 };
43951 +               dwc_otg_core_global_regs_t *global_regs;
43952 +               global_regs = hcd->core_if->core_global_regs;
43953 +
43954 +               if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
43955 +                   hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
43956 +                       /*
43957 +                        * Make sure the Non-periodic Tx FIFO empty interrupt
43958 +                        * is enabled so that the non-periodic schedule will
43959 +                        * be processed.
43960 +                        */
43961 +                       gintmsk.b.nptxfempty = 1;
43962 +                       if (fiq_enable) {
43963 +                               local_fiq_disable();
43964 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
43965 +                               DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
43966 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
43967 +                               local_fiq_enable();
43968 +                       } else {
43969 +                               DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
43970 +                       }
43971 +               } else {
43972 +                       /*
43973 +                        * Move the QH from the periodic queued schedule to
43974 +                        * the periodic assigned schedule. This allows the
43975 +                        * halt to be queued when the periodic schedule is
43976 +                        * processed.
43977 +                        */
43978 +                       DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
43979 +                                          &hc->qh->qh_list_entry);
43980 +
43981 +                       /*
43982 +                        * Make sure the Periodic Tx FIFO Empty interrupt is
43983 +                        * enabled so that the periodic schedule will be
43984 +                        * processed.
43985 +                        */
43986 +                       gintmsk.b.ptxfempty = 1;
43987 +                       if (fiq_enable) {
43988 +                               local_fiq_disable();
43989 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
43990 +                               DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
43991 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
43992 +                               local_fiq_enable();
43993 +                       } else {
43994 +                               DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
43995 +                       }
43996 +               }
43997 +       }
43998 +}
43999 +
44000 +/**
44001 + * Performs common cleanup for non-periodic transfers after a Transfer
44002 + * Complete interrupt. This function should be called after any endpoint type
44003 + * specific handling is finished to release the host channel.
44004 + */
44005 +static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
44006 +                                      dwc_hc_t * hc,
44007 +                                      dwc_otg_hc_regs_t * hc_regs,
44008 +                                      dwc_otg_qtd_t * qtd,
44009 +                                      dwc_otg_halt_status_e halt_status)
44010 +{
44011 +       hcint_data_t hcint;
44012 +
44013 +       qtd->error_count = 0;
44014 +
44015 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
44016 +       if (hcint.b.nyet) {
44017 +               /*
44018 +                * Got a NYET on the last transaction of the transfer. This
44019 +                * means that the endpoint should be in the PING state at the
44020 +                * beginning of the next transfer.
44021 +                */
44022 +               hc->qh->ping_state = 1;
44023 +               clear_hc_int(hc_regs, nyet);
44024 +       }
44025 +
44026 +       /*
44027 +        * Always halt and release the host channel to make it available for
44028 +        * more transfers. There may still be more phases for a control
44029 +        * transfer or more data packets for a bulk transfer at this point,
44030 +        * but the host channel is still halted. A channel will be reassigned
44031 +        * to the transfer when the non-periodic schedule is processed after
44032 +        * the channel is released. This allows transactions to be queued
44033 +        * properly via dwc_otg_hcd_queue_transactions, which also enables the
44034 +        * Tx FIFO Empty interrupt if necessary.
44035 +        */
44036 +       if (hc->ep_is_in) {
44037 +               /*
44038 +                * IN transfers in Slave mode require an explicit disable to
44039 +                * halt the channel. (In DMA mode, this call simply releases
44040 +                * the channel.)
44041 +                */
44042 +               halt_channel(hcd, hc, qtd, halt_status);
44043 +       } else {
44044 +               /*
44045 +                * The channel is automatically disabled by the core for OUT
44046 +                * transfers in Slave mode.
44047 +                */
44048 +               release_channel(hcd, hc, qtd, halt_status);
44049 +       }
44050 +}
44051 +
44052 +/**
44053 + * Performs common cleanup for periodic transfers after a Transfer Complete
44054 + * interrupt. This function should be called after any endpoint type specific
44055 + * handling is finished to release the host channel.
44056 + */
44057 +static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
44058 +                                  dwc_hc_t * hc,
44059 +                                  dwc_otg_hc_regs_t * hc_regs,
44060 +                                  dwc_otg_qtd_t * qtd,
44061 +                                  dwc_otg_halt_status_e halt_status)
44062 +{
44063 +       hctsiz_data_t hctsiz;
44064 +       qtd->error_count = 0;
44065 +
44066 +       hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44067 +       if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
44068 +               /* Core halts channel in these cases. */
44069 +               release_channel(hcd, hc, qtd, halt_status);
44070 +       } else {
44071 +               /* Flush any outstanding requests from the Tx queue. */
44072 +               halt_channel(hcd, hc, qtd, halt_status);
44073 +       }
44074 +}
44075 +
44076 +static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
44077 +                                            dwc_hc_t * hc,
44078 +                                            dwc_otg_hc_regs_t * hc_regs,
44079 +                                            dwc_otg_qtd_t * qtd)
44080 +{
44081 +       uint32_t len;
44082 +       struct dwc_otg_hcd_iso_packet_desc *frame_desc;
44083 +       frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
44084 +
44085 +       len = get_actual_xfer_length(hc, hc_regs, qtd,
44086 +                                    DWC_OTG_HC_XFER_COMPLETE, NULL);
44087 +
44088 +       if (!len) {
44089 +               qtd->complete_split = 0;
44090 +               qtd->isoc_split_offset = 0;
44091 +               return 0;
44092 +       }
44093 +       frame_desc->actual_length += len;
44094 +
44095 +       if (hc->align_buff && len)
44096 +               dwc_memcpy(qtd->urb->buf + frame_desc->offset +
44097 +                          qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
44098 +       qtd->isoc_split_offset += len;
44099 +
44100 +       if (frame_desc->length == frame_desc->actual_length) {
44101 +               frame_desc->status = 0;
44102 +               qtd->isoc_frame_index++;
44103 +               qtd->complete_split = 0;
44104 +               qtd->isoc_split_offset = 0;
44105 +       }
44106 +
44107 +       if (qtd->isoc_frame_index == qtd->urb->packet_count) {
44108 +               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
44109 +               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
44110 +       } else {
44111 +               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
44112 +       }
44113 +
44114 +       return 1;               /* Indicates that channel released */
44115 +}
44116 +
44117 +/**
44118 + * Handles a host channel Transfer Complete interrupt. This handler may be
44119 + * called in either DMA mode or Slave mode.
44120 + */
44121 +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
44122 +                                      dwc_hc_t * hc,
44123 +                                      dwc_otg_hc_regs_t * hc_regs,
44124 +                                      dwc_otg_qtd_t * qtd)
44125 +{
44126 +       int urb_xfer_done;
44127 +       dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
44128 +       dwc_otg_hcd_urb_t *urb = qtd->urb;
44129 +       int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
44130 +
44131 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44132 +                   "Transfer Complete--\n", hc->hc_num);
44133 +
44134 +       if (hcd->core_if->dma_desc_enable) {
44135 +               dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
44136 +               if (pipe_type == UE_ISOCHRONOUS) {
44137 +                       /* Do not disable the interrupt, just clear it */
44138 +                       clear_hc_int(hc_regs, xfercomp);
44139 +                       return 1;
44140 +               }
44141 +               goto handle_xfercomp_done;
44142 +       }
44143 +
44144 +       /*
44145 +        * Handle xfer complete on CSPLIT.
44146 +        */
44147 +
44148 +       if (hc->qh->do_split) {
44149 +               if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
44150 +                   && hcd->core_if->dma_enable) {
44151 +                       if (qtd->complete_split
44152 +                           && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
44153 +                                                            qtd))
44154 +                               goto handle_xfercomp_done;
44155 +               } else {
44156 +                       qtd->complete_split = 0;
44157 +               }
44158 +       }
44159 +
44160 +       /* Update the QTD and URB states. */
44161 +       switch (pipe_type) {
44162 +       case UE_CONTROL:
44163 +               switch (qtd->control_phase) {
44164 +               case DWC_OTG_CONTROL_SETUP:
44165 +                       if (urb->length > 0) {
44166 +                               qtd->control_phase = DWC_OTG_CONTROL_DATA;
44167 +                       } else {
44168 +                               qtd->control_phase = DWC_OTG_CONTROL_STATUS;
44169 +                       }
44170 +                       DWC_DEBUGPL(DBG_HCDV,
44171 +                                   "  Control setup transaction done\n");
44172 +                       halt_status = DWC_OTG_HC_XFER_COMPLETE;
44173 +                       break;
44174 +               case DWC_OTG_CONTROL_DATA:{
44175 +                               urb_xfer_done =
44176 +                                   update_urb_state_xfer_comp(hc, hc_regs, urb,
44177 +                                                              qtd);
44178 +                               if (urb_xfer_done) {
44179 +                                       qtd->control_phase =
44180 +                                           DWC_OTG_CONTROL_STATUS;
44181 +                                       DWC_DEBUGPL(DBG_HCDV,
44182 +                                                   "  Control data transfer done\n");
44183 +                               } else {
44184 +                                       dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44185 +                               }
44186 +                               halt_status = DWC_OTG_HC_XFER_COMPLETE;
44187 +                               break;
44188 +                       }
44189 +               case DWC_OTG_CONTROL_STATUS:
44190 +                       DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
44191 +                       if (urb->status == -DWC_E_IN_PROGRESS) {
44192 +                               urb->status = 0;
44193 +                       }
44194 +                       hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44195 +                       halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44196 +                       break;
44197 +               }
44198 +
44199 +               complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44200 +               break;
44201 +       case UE_BULK:
44202 +               DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
44203 +               urb_xfer_done =
44204 +                   update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
44205 +               if (urb_xfer_done) {
44206 +                       hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44207 +                       halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44208 +               } else {
44209 +                       halt_status = DWC_OTG_HC_XFER_COMPLETE;
44210 +               }
44211 +
44212 +               dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44213 +               complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44214 +               break;
44215 +       case UE_INTERRUPT:
44216 +               DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
44217 +               urb_xfer_done =
44218 +                       update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
44219 +
44220 +               /*
44221 +                * Interrupt URB is done on the first transfer complete
44222 +                * interrupt.
44223 +                */
44224 +               if (urb_xfer_done) {
44225 +                               hcd->fops->complete(hcd, urb->priv, urb, urb->status);
44226 +                               halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
44227 +               } else {
44228 +                               halt_status = DWC_OTG_HC_XFER_COMPLETE;
44229 +               }
44230 +
44231 +               dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44232 +               complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44233 +               break;
44234 +       case UE_ISOCHRONOUS:
44235 +               DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
44236 +               if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
44237 +                       halt_status =
44238 +                           update_isoc_urb_state(hcd, hc, hc_regs, qtd,
44239 +                                                 DWC_OTG_HC_XFER_COMPLETE);
44240 +               }
44241 +               complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
44242 +               break;
44243 +       }
44244 +
44245 +handle_xfercomp_done:
44246 +       disable_hc_int(hc_regs, xfercompl);
44247 +
44248 +       return 1;
44249 +}
44250 +
44251 +/**
44252 + * Handles a host channel STALL interrupt. This handler may be called in
44253 + * either DMA mode or Slave mode.
44254 + */
44255 +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
44256 +                                   dwc_hc_t * hc,
44257 +                                   dwc_otg_hc_regs_t * hc_regs,
44258 +                                   dwc_otg_qtd_t * qtd)
44259 +{
44260 +       dwc_otg_hcd_urb_t *urb = qtd->urb;
44261 +       int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
44262 +
44263 +       DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
44264 +                   "STALL Received--\n", hc->hc_num);
44265 +
44266 +       if (hcd->core_if->dma_desc_enable) {
44267 +               dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
44268 +               goto handle_stall_done;
44269 +       }
44270 +
44271 +       if (pipe_type == UE_CONTROL) {
44272 +               hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
44273 +       }
44274 +
44275 +       if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
44276 +               hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
44277 +               /*
44278 +                * USB protocol requires resetting the data toggle for bulk
44279 +                * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
44280 +                * setup command is issued to the endpoint. Anticipate the
44281 +                * CLEAR_FEATURE command since a STALL has occurred and reset
44282 +                * the data toggle now.
44283 +                */
44284 +               hc->qh->data_toggle = 0;
44285 +       }
44286 +
44287 +       halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
44288 +
44289 +handle_stall_done:
44290 +       disable_hc_int(hc_regs, stall);
44291 +
44292 +       return 1;
44293 +}
44294 +
44295 +/*
44296 + * Updates the state of the URB when a transfer has been stopped due to an
44297 + * abnormal condition before the transfer completes. Modifies the
44298 + * actual_length field of the URB to reflect the number of bytes that have
44299 + * actually been transferred via the host channel.
44300 + */
44301 +static void update_urb_state_xfer_intr(dwc_hc_t * hc,
44302 +                                      dwc_otg_hc_regs_t * hc_regs,
44303 +                                      dwc_otg_hcd_urb_t * urb,
44304 +                                      dwc_otg_qtd_t * qtd,
44305 +                                      dwc_otg_halt_status_e halt_status)
44306 +{
44307 +       uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
44308 +                                                           halt_status, NULL);
44309 +       /* non DWORD-aligned buffer case handling. */
44310 +       if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
44311 +               dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
44312 +                          bytes_transferred);
44313 +       }
44314 +
44315 +       urb->actual_length += bytes_transferred;
44316 +
44317 +#ifdef DEBUG
44318 +       {
44319 +               hctsiz_data_t hctsiz;
44320 +               hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44321 +               DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
44322 +                           __func__, (hc->ep_is_in ? "IN" : "OUT"),
44323 +                           hc->hc_num);
44324 +               DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
44325 +                           hc->start_pkt_count);
44326 +               DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
44327 +               DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
44328 +               DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
44329 +                           bytes_transferred);
44330 +               DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
44331 +                           urb->actual_length);
44332 +               DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
44333 +                           urb->length);
44334 +       }
44335 +#endif
44336 +}
44337 +
44338 +/**
44339 + * Handles a host channel NAK interrupt. This handler may be called in either
44340 + * DMA mode or Slave mode.
44341 + */
44342 +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
44343 +                                 dwc_hc_t * hc,
44344 +                                 dwc_otg_hc_regs_t * hc_regs,
44345 +                                 dwc_otg_qtd_t * qtd)
44346 +{
44347 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44348 +                   "NAK Received--\n", hc->hc_num);
44349 +
44350 +       /*
44351 +        * When we get bulk NAKs then remember this so we holdoff on this qh until
44352 +        * the beginning of the next frame
44353 +        */
44354 +       switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44355 +               case UE_BULK:
44356 +               case UE_CONTROL:
44357 +               if (nak_holdoff && qtd->qh->do_split)
44358 +                       hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd);
44359 +       }
44360 +
44361 +       /*
44362 +        * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
44363 +        * interrupt.  Re-start the SSPLIT transfer.
44364 +        */
44365 +       if (hc->do_split) {
44366 +               if (hc->complete_split) {
44367 +                       qtd->error_count = 0;
44368 +               }
44369 +               qtd->complete_split = 0;
44370 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44371 +               goto handle_nak_done;
44372 +       }
44373 +
44374 +       switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44375 +       case UE_CONTROL:
44376 +       case UE_BULK:
44377 +               if (hcd->core_if->dma_enable && hc->ep_is_in) {
44378 +                       /*
44379 +                        * NAK interrupts are enabled on bulk/control IN
44380 +                        * transfers in DMA mode for the sole purpose of
44381 +                        * resetting the error count after a transaction error
44382 +                        * occurs. The core will continue transferring data.
44383 +                        * Disable other interrupts unmasked for the same
44384 +                        * reason.
44385 +                        */
44386 +                       disable_hc_int(hc_regs, datatglerr);
44387 +                       disable_hc_int(hc_regs, ack);
44388 +                       qtd->error_count = 0;
44389 +                       goto handle_nak_done;
44390 +               }
44391 +
44392 +               /*
44393 +                * NAK interrupts normally occur during OUT transfers in DMA
44394 +                * or Slave mode. For IN transfers, more requests will be
44395 +                * queued as request queue space is available.
44396 +                */
44397 +               qtd->error_count = 0;
44398 +
44399 +               if (!hc->qh->ping_state) {
44400 +                       update_urb_state_xfer_intr(hc, hc_regs,
44401 +                                                  qtd->urb, qtd,
44402 +                                                  DWC_OTG_HC_XFER_NAK);
44403 +                       dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44404 +
44405 +                       if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
44406 +                               hc->qh->ping_state = 1;
44407 +               }
44408 +
44409 +               /*
44410 +                * Halt the channel so the transfer can be re-started from
44411 +                * the appropriate point or the PING protocol will
44412 +                * start/continue.
44413 +                */
44414 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44415 +               break;
44416 +       case UE_INTERRUPT:
44417 +               qtd->error_count = 0;
44418 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
44419 +               break;
44420 +       case UE_ISOCHRONOUS:
44421 +               /* Should never get called for isochronous transfers. */
44422 +               DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
44423 +               break;
44424 +       }
44425 +
44426 +handle_nak_done:
44427 +       disable_hc_int(hc_regs, nak);
44428 +
44429 +       return 1;
44430 +}
44431 +
44432 +/**
44433 + * Handles a host channel ACK interrupt. This interrupt is enabled when
44434 + * performing the PING protocol in Slave mode, when errors occur during
44435 + * either Slave mode or DMA mode, and during Start Split transactions.
44436 + */
44437 +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
44438 +                                 dwc_hc_t * hc,
44439 +                                 dwc_otg_hc_regs_t * hc_regs,
44440 +                                 dwc_otg_qtd_t * qtd)
44441 +{
44442 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44443 +                   "ACK Received--\n", hc->hc_num);
44444 +
44445 +       if (hc->do_split) {
44446 +               /*
44447 +                * Handle ACK on SSPLIT.
44448 +                * ACK should not occur in CSPLIT.
44449 +                */
44450 +               if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
44451 +                       qtd->ssplit_out_xfer_count = hc->xfer_len;
44452 +               }
44453 +               if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
44454 +                       /* Don't need complete for isochronous out transfers. */
44455 +                       qtd->complete_split = 1;
44456 +               }
44457 +
44458 +               /* ISOC OUT */
44459 +               if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
44460 +                       switch (hc->xact_pos) {
44461 +                       case DWC_HCSPLIT_XACTPOS_ALL:
44462 +                               break;
44463 +                       case DWC_HCSPLIT_XACTPOS_END:
44464 +                               qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
44465 +                               qtd->isoc_split_offset = 0;
44466 +                               break;
44467 +                       case DWC_HCSPLIT_XACTPOS_BEGIN:
44468 +                       case DWC_HCSPLIT_XACTPOS_MID:
44469 +                               /*
44470 +                                * For BEGIN or MID, calculate the length for
44471 +                                * the next microframe to determine the correct
44472 +                                * SSPLIT token, either MID or END.
44473 +                                */
44474 +                               {
44475 +                                       struct dwc_otg_hcd_iso_packet_desc
44476 +                                       *frame_desc;
44477 +
44478 +                                       frame_desc =
44479 +                                           &qtd->urb->
44480 +                                           iso_descs[qtd->isoc_frame_index];
44481 +                                       qtd->isoc_split_offset += 188;
44482 +
44483 +                                       if ((frame_desc->length -
44484 +                                            qtd->isoc_split_offset) <= 188) {
44485 +                                               qtd->isoc_split_pos =
44486 +                                                   DWC_HCSPLIT_XACTPOS_END;
44487 +                                       } else {
44488 +                                               qtd->isoc_split_pos =
44489 +                                                   DWC_HCSPLIT_XACTPOS_MID;
44490 +                                       }
44491 +
44492 +                               }
44493 +                               break;
44494 +                       }
44495 +               } else {
44496 +                       halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
44497 +               }
44498 +       } else {
44499 +               /*
44500 +                * An unmasked ACK on a non-split DMA transaction is
44501 +                * for the sole purpose of resetting error counts. Disable other
44502 +                * interrupts unmasked for the same reason.
44503 +                */
44504 +               if(hcd->core_if->dma_enable) {
44505 +                       disable_hc_int(hc_regs, datatglerr);
44506 +                       disable_hc_int(hc_regs, nak);
44507 +               }
44508 +               qtd->error_count = 0;
44509 +
44510 +               if (hc->qh->ping_state) {
44511 +                       hc->qh->ping_state = 0;
44512 +                       /*
44513 +                        * Halt the channel so the transfer can be re-started
44514 +                        * from the appropriate point. This only happens in
44515 +                        * Slave mode. In DMA mode, the ping_state is cleared
44516 +                        * when the transfer is started because the core
44517 +                        * automatically executes the PING, then the transfer.
44518 +                        */
44519 +                       halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
44520 +               }
44521 +       }
44522 +
44523 +       /*
44524 +        * If the ACK occurred when _not_ in the PING state, let the channel
44525 +        * continue transferring data after clearing the error count.
44526 +        */
44527 +
44528 +       disable_hc_int(hc_regs, ack);
44529 +
44530 +       return 1;
44531 +}
44532 +
44533 +/**
44534 + * Handles a host channel NYET interrupt. This interrupt should only occur on
44535 + * Bulk and Control OUT endpoints and for complete split transactions. If a
44536 + * NYET occurs at the same time as a Transfer Complete interrupt, it is
44537 + * handled in the xfercomp interrupt handler, not here. This handler may be
44538 + * called in either DMA mode or Slave mode.
44539 + */
44540 +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
44541 +                                  dwc_hc_t * hc,
44542 +                                  dwc_otg_hc_regs_t * hc_regs,
44543 +                                  dwc_otg_qtd_t * qtd)
44544 +{
44545 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44546 +                   "NYET Received--\n", hc->hc_num);
44547 +
44548 +       /*
44549 +        * NYET on CSPLIT
44550 +        * re-do the CSPLIT immediately on non-periodic
44551 +        */
44552 +       if (hc->do_split && hc->complete_split) {
44553 +               if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
44554 +                   && hcd->core_if->dma_enable) {
44555 +                       qtd->complete_split = 0;
44556 +                       qtd->isoc_split_offset = 0;
44557 +                       if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
44558 +                               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
44559 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
44560 +                       }
44561 +                       else
44562 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
44563 +                       goto handle_nyet_done;
44564 +               }
44565 +
44566 +               if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
44567 +                   hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
44568 +                       int frnum = dwc_otg_hcd_get_frame_number(hcd);
44569 +
44570 +                       // With the FIQ running we only ever see the failed NYET
44571 +                       if (dwc_full_frame_num(frnum) !=
44572 +                           dwc_full_frame_num(hc->qh->sched_frame) ||
44573 +                           fiq_fsm_enable) {
44574 +                               /*
44575 +                                * No longer in the same full speed frame.
44576 +                                * Treat this as a transaction error.
44577 +                                */
44578 +#if 0
44579 +                               /** @todo Fix system performance so this can
44580 +                                * be treated as an error. Right now complete
44581 +                                * splits cannot be scheduled precisely enough
44582 +                                * due to other system activity, so this error
44583 +                                * occurs regularly in Slave mode.
44584 +                                */
44585 +                               qtd->error_count++;
44586 +#endif
44587 +                               qtd->complete_split = 0;
44588 +                               halt_channel(hcd, hc, qtd,
44589 +                                            DWC_OTG_HC_XFER_XACT_ERR);
44590 +                               /** @todo add support for isoc release */
44591 +                               goto handle_nyet_done;
44592 +                       }
44593 +               }
44594 +
44595 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
44596 +               goto handle_nyet_done;
44597 +       }
44598 +
44599 +       hc->qh->ping_state = 1;
44600 +       qtd->error_count = 0;
44601 +
44602 +       update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
44603 +                                  DWC_OTG_HC_XFER_NYET);
44604 +       dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44605 +
44606 +       /*
44607 +        * Halt the channel and re-start the transfer so the PING
44608 +        * protocol will start.
44609 +        */
44610 +       halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
44611 +
44612 +handle_nyet_done:
44613 +       disable_hc_int(hc_regs, nyet);
44614 +       return 1;
44615 +}
44616 +
44617 +/**
44618 + * Handles a host channel babble interrupt. This handler may be called in
44619 + * either DMA mode or Slave mode.
44620 + */
44621 +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
44622 +                                    dwc_hc_t * hc,
44623 +                                    dwc_otg_hc_regs_t * hc_regs,
44624 +                                    dwc_otg_qtd_t * qtd)
44625 +{
44626 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44627 +                   "Babble Error--\n", hc->hc_num);
44628 +
44629 +       if (hcd->core_if->dma_desc_enable) {
44630 +               dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
44631 +                                              DWC_OTG_HC_XFER_BABBLE_ERR);
44632 +               goto handle_babble_done;
44633 +       }
44634 +
44635 +       if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
44636 +               hcd->fops->complete(hcd, qtd->urb->priv,
44637 +                                   qtd->urb, -DWC_E_OVERFLOW);
44638 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
44639 +       } else {
44640 +               dwc_otg_halt_status_e halt_status;
44641 +               halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
44642 +                                                   DWC_OTG_HC_XFER_BABBLE_ERR);
44643 +               halt_channel(hcd, hc, qtd, halt_status);
44644 +       }
44645 +
44646 +handle_babble_done:
44647 +       disable_hc_int(hc_regs, bblerr);
44648 +       return 1;
44649 +}
44650 +
44651 +/**
44652 + * Handles a host channel AHB error interrupt. This handler is only called in
44653 + * DMA mode.
44654 + */
44655 +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
44656 +                                    dwc_hc_t * hc,
44657 +                                    dwc_otg_hc_regs_t * hc_regs,
44658 +                                    dwc_otg_qtd_t * qtd)
44659 +{
44660 +       hcchar_data_t hcchar;
44661 +       hcsplt_data_t hcsplt;
44662 +       hctsiz_data_t hctsiz;
44663 +       uint32_t hcdma;
44664 +       char *pipetype, *speed;
44665 +
44666 +       dwc_otg_hcd_urb_t *urb = qtd->urb;
44667 +
44668 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44669 +                   "AHB Error--\n", hc->hc_num);
44670 +
44671 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
44672 +       hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
44673 +       hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44674 +       hcdma = DWC_READ_REG32(&hc_regs->hcdma);
44675 +
44676 +       DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
44677 +       DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
44678 +       DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
44679 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
44680 +       DWC_ERROR("  Device address: %d\n",
44681 +                 dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
44682 +       DWC_ERROR("  Endpoint: %d, %s\n",
44683 +                 dwc_otg_hcd_get_ep_num(&urb->pipe_info),
44684 +                 (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
44685 +
44686 +       switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
44687 +       case UE_CONTROL:
44688 +               pipetype = "CONTROL";
44689 +               break;
44690 +       case UE_BULK:
44691 +               pipetype = "BULK";
44692 +               break;
44693 +       case UE_INTERRUPT:
44694 +               pipetype = "INTERRUPT";
44695 +               break;
44696 +       case UE_ISOCHRONOUS:
44697 +               pipetype = "ISOCHRONOUS";
44698 +               break;
44699 +       default:
44700 +               pipetype = "UNKNOWN";
44701 +               break;
44702 +       }
44703 +
44704 +       DWC_ERROR("  Endpoint type: %s\n", pipetype);
44705 +
44706 +       switch (hc->speed) {
44707 +       case DWC_OTG_EP_SPEED_HIGH:
44708 +               speed = "HIGH";
44709 +               break;
44710 +       case DWC_OTG_EP_SPEED_FULL:
44711 +               speed = "FULL";
44712 +               break;
44713 +       case DWC_OTG_EP_SPEED_LOW:
44714 +               speed = "LOW";
44715 +               break;
44716 +       default:
44717 +               speed = "UNKNOWN";
44718 +               break;
44719 +       };
44720 +
44721 +       DWC_ERROR("  Speed: %s\n", speed);
44722 +
44723 +       DWC_ERROR("  Max packet size: %d\n",
44724 +                 dwc_otg_hcd_get_mps(&urb->pipe_info));
44725 +       DWC_ERROR("  Data buffer length: %d\n", urb->length);
44726 +       DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
44727 +                 urb->buf, (void *)urb->dma);
44728 +       DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
44729 +                 urb->setup_packet, (void *)urb->setup_dma);
44730 +       DWC_ERROR("  Interval: %d\n", urb->interval);
44731 +
44732 +       /* Core haltes the channel for Descriptor DMA mode */
44733 +       if (hcd->core_if->dma_desc_enable) {
44734 +               dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
44735 +                                              DWC_OTG_HC_XFER_AHB_ERR);
44736 +               goto handle_ahberr_done;
44737 +       }
44738 +
44739 +       hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
44740 +
44741 +       /*
44742 +        * Force a channel halt. Don't call halt_channel because that won't
44743 +        * write to the HCCHARn register in DMA mode to force the halt.
44744 +        */
44745 +       dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
44746 +handle_ahberr_done:
44747 +       disable_hc_int(hc_regs, ahberr);
44748 +       return 1;
44749 +}
44750 +
44751 +/**
44752 + * Handles a host channel transaction error interrupt. This handler may be
44753 + * called in either DMA mode or Slave mode.
44754 + */
44755 +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
44756 +                                     dwc_hc_t * hc,
44757 +                                     dwc_otg_hc_regs_t * hc_regs,
44758 +                                     dwc_otg_qtd_t * qtd)
44759 +{
44760 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44761 +                   "Transaction Error--\n", hc->hc_num);
44762 +
44763 +       if (hcd->core_if->dma_desc_enable) {
44764 +               dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
44765 +                                              DWC_OTG_HC_XFER_XACT_ERR);
44766 +               goto handle_xacterr_done;
44767 +       }
44768 +
44769 +       switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44770 +       case UE_CONTROL:
44771 +       case UE_BULK:
44772 +               qtd->error_count++;
44773 +               if (!hc->qh->ping_state) {
44774 +
44775 +                       update_urb_state_xfer_intr(hc, hc_regs,
44776 +                                                  qtd->urb, qtd,
44777 +                                                  DWC_OTG_HC_XFER_XACT_ERR);
44778 +                       dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44779 +                       if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
44780 +                               hc->qh->ping_state = 1;
44781 +                       }
44782 +               }
44783 +
44784 +               /*
44785 +                * Halt the channel so the transfer can be re-started from
44786 +                * the appropriate point or the PING protocol will start.
44787 +                */
44788 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
44789 +               break;
44790 +       case UE_INTERRUPT:
44791 +               qtd->error_count++;
44792 +               if (hc->do_split && hc->complete_split) {
44793 +                       qtd->complete_split = 0;
44794 +               }
44795 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
44796 +               break;
44797 +       case UE_ISOCHRONOUS:
44798 +               {
44799 +                       dwc_otg_halt_status_e halt_status;
44800 +                       halt_status =
44801 +                           update_isoc_urb_state(hcd, hc, hc_regs, qtd,
44802 +                                                 DWC_OTG_HC_XFER_XACT_ERR);
44803 +
44804 +                       halt_channel(hcd, hc, qtd, halt_status);
44805 +               }
44806 +               break;
44807 +       }
44808 +handle_xacterr_done:
44809 +       disable_hc_int(hc_regs, xacterr);
44810 +
44811 +       return 1;
44812 +}
44813 +
44814 +/**
44815 + * Handles a host channel frame overrun interrupt. This handler may be called
44816 + * in either DMA mode or Slave mode.
44817 + */
44818 +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
44819 +                                      dwc_hc_t * hc,
44820 +                                      dwc_otg_hc_regs_t * hc_regs,
44821 +                                      dwc_otg_qtd_t * qtd)
44822 +{
44823 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44824 +                   "Frame Overrun--\n", hc->hc_num);
44825 +
44826 +       switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
44827 +       case UE_CONTROL:
44828 +       case UE_BULK:
44829 +               break;
44830 +       case UE_INTERRUPT:
44831 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
44832 +               break;
44833 +       case UE_ISOCHRONOUS:
44834 +               {
44835 +                       dwc_otg_halt_status_e halt_status;
44836 +                       halt_status =
44837 +                           update_isoc_urb_state(hcd, hc, hc_regs, qtd,
44838 +                                                 DWC_OTG_HC_XFER_FRAME_OVERRUN);
44839 +
44840 +                       halt_channel(hcd, hc, qtd, halt_status);
44841 +               }
44842 +               break;
44843 +       }
44844 +
44845 +       disable_hc_int(hc_regs, frmovrun);
44846 +
44847 +       return 1;
44848 +}
44849 +
44850 +/**
44851 + * Handles a host channel data toggle error interrupt. This handler may be
44852 + * called in either DMA mode or Slave mode.
44853 + */
44854 +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
44855 +                                        dwc_hc_t * hc,
44856 +                                        dwc_otg_hc_regs_t * hc_regs,
44857 +                                        dwc_otg_qtd_t * qtd)
44858 +{
44859 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
44860 +               "Data Toggle Error on %s transfer--\n",
44861 +               hc->hc_num, (hc->ep_is_in ? "IN" : "OUT"));
44862 +
44863 +       /* Data toggles on split transactions cause the hc to halt.
44864 +        * restart transfer */
44865 +       if(hc->qh->do_split)
44866 +       {
44867 +               qtd->error_count++;
44868 +               dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
44869 +               update_urb_state_xfer_intr(hc, hc_regs,
44870 +                       qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
44871 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
44872 +       } else if (hc->ep_is_in) {
44873 +               /* An unmasked data toggle error on a non-split DMA transaction is
44874 +                * for the sole purpose of resetting error counts. Disable other
44875 +                * interrupts unmasked for the same reason.
44876 +                */
44877 +               if(hcd->core_if->dma_enable) {
44878 +                       disable_hc_int(hc_regs, ack);
44879 +                       disable_hc_int(hc_regs, nak);
44880 +               }
44881 +               qtd->error_count = 0;
44882 +       }
44883 +
44884 +       disable_hc_int(hc_regs, datatglerr);
44885 +
44886 +       return 1;
44887 +}
44888 +
44889 +#ifdef DEBUG
44890 +/**
44891 + * This function is for debug only. It checks that a valid halt status is set
44892 + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
44893 + * taken and a warning is issued.
44894 + * @return 1 if halt status is ok, 0 otherwise.
44895 + */
44896 +static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
44897 +                                dwc_hc_t * hc,
44898 +                                dwc_otg_hc_regs_t * hc_regs,
44899 +                                dwc_otg_qtd_t * qtd)
44900 +{
44901 +       hcchar_data_t hcchar;
44902 +       hctsiz_data_t hctsiz;
44903 +       hcint_data_t hcint;
44904 +       hcintmsk_data_t hcintmsk;
44905 +       hcsplt_data_t hcsplt;
44906 +
44907 +       if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
44908 +               /*
44909 +                * This code is here only as a check. This condition should
44910 +                * never happen. Ignore the halt if it does occur.
44911 +                */
44912 +               hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
44913 +               hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
44914 +               hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
44915 +               hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
44916 +               hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
44917 +               DWC_WARN
44918 +                   ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
44919 +                    "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
44920 +                    "hcint 0x%08x, hcintmsk 0x%08x, "
44921 +                    "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
44922 +                    hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
44923 +                    hcintmsk.d32, hcsplt.d32, qtd->complete_split);
44924 +
44925 +               DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
44926 +                        __func__, hc->hc_num);
44927 +               DWC_WARN("\n");
44928 +               clear_hc_int(hc_regs, chhltd);
44929 +               return 0;
44930 +       }
44931 +
44932 +       /*
44933 +        * This code is here only as a check. hcchar.chdis should
44934 +        * never be set when the halt interrupt occurs. Halt the
44935 +        * channel again if it does occur.
44936 +        */
44937 +       hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
44938 +       if (hcchar.b.chdis) {
44939 +               DWC_WARN("%s: hcchar.chdis set unexpectedly, "
44940 +                        "hcchar 0x%08x, trying to halt again\n",
44941 +                        __func__, hcchar.d32);
44942 +               clear_hc_int(hc_regs, chhltd);
44943 +               hc->halt_pending = 0;
44944 +               halt_channel(hcd, hc, qtd, hc->halt_status);
44945 +               return 0;
44946 +       }
44947 +
44948 +       return 1;
44949 +}
44950 +#endif
44951 +
44952 +/**
44953 + * Handles a host Channel Halted interrupt in DMA mode. This handler
44954 + * determines the reason the channel halted and proceeds accordingly.
44955 + */
44956 +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
44957 +                                     dwc_hc_t * hc,
44958 +                                     dwc_otg_hc_regs_t * hc_regs,
44959 +                                     dwc_otg_qtd_t * qtd)
44960 +{
44961 +       int out_nak_enh = 0;
44962 +       hcint_data_t hcint;
44963 +       hcintmsk_data_t hcintmsk;
44964 +       /* For core with OUT NAK enhancement, the flow for high-
44965 +        * speed CONTROL/BULK OUT is handled a little differently.
44966 +        */
44967 +       if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
44968 +               if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
44969 +                   (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
44970 +                    hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
44971 +                       out_nak_enh = 1;
44972 +               }
44973 +       }
44974 +
44975 +       if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
44976 +           (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
44977 +            && !hcd->core_if->dma_desc_enable)) {
44978 +               /*
44979 +                * Just release the channel. A dequeue can happen on a
44980 +                * transfer timeout. In the case of an AHB Error, the channel
44981 +                * was forced to halt because there's no way to gracefully
44982 +                * recover.
44983 +                */
44984 +               if (hcd->core_if->dma_desc_enable)
44985 +                       dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
44986 +                                                      hc->halt_status);
44987 +               else
44988 +                       release_channel(hcd, hc, qtd, hc->halt_status);
44989 +               return;
44990 +       }
44991 +
44992 +       /* Read the HCINTn register to determine the cause for the halt. */
44993 +
44994 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
44995 +       hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
44996 +
44997 +       if (hcint.b.xfercomp) {
44998 +               /** @todo This is here because of a possible hardware bug.  Spec
44999 +                * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
45000 +                * interrupt w/ACK bit set should occur, but I only see the
45001 +                * XFERCOMP bit, even with it masked out.  This is a workaround
45002 +                * for that behavior.  Should fix this when hardware is fixed.
45003 +                */
45004 +               if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
45005 +                       handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
45006 +               }
45007 +               handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
45008 +       } else if (hcint.b.stall) {
45009 +               handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
45010 +       } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
45011 +               if (out_nak_enh) {
45012 +                       if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
45013 +                               DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n");
45014 +                               qtd->error_count = 0;
45015 +                       } else {
45016 +                               DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n");
45017 +                       }
45018 +               }
45019 +
45020 +               /*
45021 +                * Must handle xacterr before nak or ack. Could get a xacterr
45022 +                * at the same time as either of these on a BULK/CONTROL OUT
45023 +                * that started with a PING. The xacterr takes precedence.
45024 +                */
45025 +               handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45026 +       } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
45027 +               handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45028 +       } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
45029 +               handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45030 +       } else if (hcint.b.bblerr) {
45031 +               handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
45032 +       } else if (hcint.b.frmovrun) {
45033 +               handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
45034 +       } else if (hcint.b.datatglerr) {
45035 +               handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
45036 +       } else if (!out_nak_enh) {
45037 +               if (hcint.b.nyet) {
45038 +                       /*
45039 +                        * Must handle nyet before nak or ack. Could get a nyet at the
45040 +                        * same time as either of those on a BULK/CONTROL OUT that
45041 +                        * started with a PING. The nyet takes precedence.
45042 +                        */
45043 +                       handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
45044 +               } else if (hcint.b.nak && !hcintmsk.b.nak) {
45045 +                       /*
45046 +                        * If nak is not masked, it's because a non-split IN transfer
45047 +                        * is in an error state. In that case, the nak is handled by
45048 +                        * the nak interrupt handler, not here. Handle nak here for
45049 +                        * BULK/CONTROL OUT transfers, which halt on a NAK to allow
45050 +                        * rewinding the buffer pointer.
45051 +                        */
45052 +                       handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45053 +               } else if (hcint.b.ack && !hcintmsk.b.ack) {
45054 +                       /*
45055 +                        * If ack is not masked, it's because a non-split IN transfer
45056 +                        * is in an error state. In that case, the ack is handled by
45057 +                        * the ack interrupt handler, not here. Handle ack here for
45058 +                        * split transfers. Start splits halt on ACK.
45059 +                        */
45060 +                       handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
45061 +               } else {
45062 +                       if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
45063 +                           hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
45064 +                               /*
45065 +                                * A periodic transfer halted with no other channel
45066 +                                * interrupts set. Assume it was halted by the core
45067 +                                * because it could not be completed in its scheduled
45068 +                                * (micro)frame.
45069 +                                */
45070 +#ifdef DEBUG
45071 +                               DWC_PRINTF
45072 +                                   ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
45073 +                                    __func__, hc->hc_num);
45074 +#endif
45075 +                               halt_channel(hcd, hc, qtd,
45076 +                                            DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
45077 +                       } else {
45078 +                               DWC_ERROR
45079 +                                   ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
45080 +                                    "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
45081 +                                    __func__, hc->hc_num, hcint.d32,
45082 +                                    DWC_READ_REG32(&hcd->
45083 +                                                   core_if->core_global_regs->
45084 +                                                   gintsts));
45085 +                               /* Failthrough: use 3-strikes rule */
45086 +                               qtd->error_count++;
45087 +                               dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45088 +                               update_urb_state_xfer_intr(hc, hc_regs,
45089 +                                          qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45090 +                               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45091 +                       }
45092 +
45093 +               }
45094 +       } else {
45095 +               DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
45096 +                          hcint.d32);
45097 +               /* Failthrough: use 3-strikes rule */
45098 +               qtd->error_count++;
45099 +               dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45100 +               update_urb_state_xfer_intr(hc, hc_regs,
45101 +                          qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45102 +               halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
45103 +       }
45104 +}
45105 +
45106 +/**
45107 + * Handles a host channel Channel Halted interrupt.
45108 + *
45109 + * In slave mode, this handler is called only when the driver specifically
45110 + * requests a halt. This occurs during handling other host channel interrupts
45111 + * (e.g. nak, xacterr, stall, nyet, etc.).
45112 + *
45113 + * In DMA mode, this is the interrupt that occurs when the core has finished
45114 + * processing a transfer on a channel. Other host channel interrupts (except
45115 + * ahberr) are disabled in DMA mode.
45116 + */
45117 +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
45118 +                                    dwc_hc_t * hc,
45119 +                                    dwc_otg_hc_regs_t * hc_regs,
45120 +                                    dwc_otg_qtd_t * qtd)
45121 +{
45122 +       DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: "
45123 +                   "Channel Halted--\n", hc->hc_num);
45124 +
45125 +       if (hcd->core_if->dma_enable) {
45126 +               handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
45127 +       } else {
45128 +#ifdef DEBUG
45129 +               if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
45130 +                       return 1;
45131 +               }
45132 +#endif
45133 +               release_channel(hcd, hc, qtd, hc->halt_status);
45134 +       }
45135 +
45136 +       return 1;
45137 +}
45138 +
45139 +
45140 +/**
45141 + * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on
45142 + * FIQ transfer completion
45143 + * @hcd:       Pointer to dwc_otg_hcd struct
45144 + * @num:       Host channel number
45145 + *
45146 + * 1. Un-mangle the status as recorded in each iso_frame_desc status
45147 + * 2. Copy it from the dwc_otg_urb into the real URB
45148 + */
45149 +void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
45150 +{
45151 +       struct dwc_otg_hcd_urb *dwc_urb = qtd->urb;
45152 +       int nr_frames = dwc_urb->packet_count;
45153 +       int i;
45154 +       hcint_data_t frame_hcint;
45155 +
45156 +       for (i = 0; i < nr_frames; i++) {
45157 +               frame_hcint.d32 = dwc_urb->iso_descs[i].status;
45158 +               if (frame_hcint.b.xfercomp) {
45159 +                       dwc_urb->iso_descs[i].status = 0;
45160 +                       dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length;
45161 +               } else if (frame_hcint.b.frmovrun) {
45162 +                       if (qh->ep_is_in)
45163 +                               dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES;
45164 +                       else
45165 +                               dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION;
45166 +                       dwc_urb->error_count++;
45167 +                       dwc_urb->iso_descs[i].actual_length = 0;
45168 +               } else if (frame_hcint.b.xacterr) {
45169 +                       dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL;
45170 +                       dwc_urb->error_count++;
45171 +                       dwc_urb->iso_descs[i].actual_length = 0;
45172 +               } else if (frame_hcint.b.bblerr) {
45173 +                       dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW;
45174 +                       dwc_urb->error_count++;
45175 +                       dwc_urb->iso_descs[i].actual_length = 0;
45176 +               } else {
45177 +                       /* Something went wrong */
45178 +                       dwc_urb->iso_descs[i].status = -1;
45179 +                       dwc_urb->iso_descs[i].actual_length = 0;
45180 +                       dwc_urb->error_count++;
45181 +               }
45182 +       }
45183 +       qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval * (nr_frames - 1));
45184 +
45185 +       //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n",
45186 +       //                      __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count);
45187 +}
45188 +
45189 +/**
45190 + * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions
45191 + * @hcd:       Pointer to dwc_otg_hcd struct
45192 + * @num:       Host channel number
45193 + *
45194 + * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state.
45195 + * Returns total length of data or -1 if the buffers were not used.
45196 + *
45197 + */
45198 +int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num)
45199 +{
45200 +       dwc_hc_t *hc = qh->channel;
45201 +       struct fiq_dma_blob *blob = hcd->fiq_dmab;
45202 +       struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
45203 +       uint8_t *ptr = NULL;
45204 +       int index = 0, len = 0;
45205 +       int i = 0;
45206 +       if (hc->ep_is_in) {
45207 +               /* Copy data out of the DMA bounce buffers to the URB's buffer.
45208 +                * The align_buf is ignored as this is ignored on FSM enqueue. */
45209 +               ptr = qtd->urb->buf;
45210 +               if (qh->ep_type == UE_ISOCHRONOUS) {
45211 +                       /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */
45212 +                       index = qtd->isoc_frame_index;
45213 +                       ptr += qtd->urb->iso_descs[index].offset;
45214 +               } else {
45215 +                       /* Need to increment by actual_length for interrupt IN */
45216 +                       ptr += qtd->urb->actual_length;
45217 +               }
45218 +
45219 +               for (i = 0; i < st->dma_info.index; i++) {
45220 +                       len += st->dma_info.slot_len[i];
45221 +                       dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]);
45222 +                       ptr += st->dma_info.slot_len[i];
45223 +               }
45224 +               return len;
45225 +       } else {
45226 +               /* OUT endpoints - nothing to do. */
45227 +               return -1;
45228 +       }
45229 +
45230 +}
45231 +/**
45232 + * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt
45233 + *                              from a channel handled in the FIQ
45234 + * @hcd:       Pointer to dwc_otg_hcd struct
45235 + * @num:       Host channel number
45236 + *
45237 + * If a host channel interrupt was received by the IRQ and this was a channel
45238 + * used by the FIQ, the execution flow for transfer completion is substantially
45239 + * different from the normal (messy) path. This function and its friends handles
45240 + * channel cleanup and transaction completion from a FIQ transaction.
45241 + */
45242 +void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num)
45243 +{
45244 +       struct fiq_channel_state *st = &hcd->fiq_state->channel[num];
45245 +       dwc_hc_t *hc = hcd->hc_ptr_array[num];
45246 +       dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
45247 +       dwc_otg_qh_t *qh = hc->qh;
45248 +       dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num];
45249 +       hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy;
45250 +       int hostchannels  = 0;
45251 +       fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm);
45252 +
45253 +       hostchannels = hcd->available_host_channels;
45254 +       switch (st->fsm) {
45255 +       case FIQ_TEST:
45256 +               break;
45257 +
45258 +       case FIQ_DEQUEUE_ISSUED:
45259 +               /* hc_halt was called. QTD no longer exists. */
45260 +               /* TODO: for a nonperiodic split transaction, need to issue a
45261 +                * CLEAR_TT_BUFFER hub command if we were in the start-split phase.
45262 +                */
45263 +               release_channel(hcd, hc, NULL, hc->halt_status);
45264 +               break;
45265 +
45266 +       case FIQ_NP_SPLIT_DONE:
45267 +               /* Nonperiodic transaction complete. */
45268 +               if (!hc->ep_is_in) {
45269 +                       qtd->ssplit_out_xfer_count = hc->xfer_len;
45270 +               }
45271 +               if (hcint.b.xfercomp) {
45272 +                       handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
45273 +               } else if (hcint.b.nak) {
45274 +                       handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45275 +               }
45276 +               break;
45277 +
45278 +       case FIQ_NP_SPLIT_HS_ABORTED:
45279 +               /* A HS abort is a 3-strikes on the HS bus at any point in the transaction.
45280 +                * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that
45281 +                * because there's no guarantee which order a non-periodic split happened in.
45282 +                * We could end up clearing a perfectly good transaction out of the buffer.
45283 +                */
45284 +               if (hcint.b.xacterr) {
45285 +                       qtd->error_count += st->nr_errors;
45286 +                       handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45287 +               } else if (hcint.b.ahberr) {
45288 +                       handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45289 +               } else {
45290 +                       local_fiq_disable();
45291 +                       BUG();
45292 +               }
45293 +               break;
45294 +
45295 +       case FIQ_NP_SPLIT_LS_ABORTED:
45296 +               /* A few cases can cause this - either an unknown state on a SSPLIT or
45297 +                * STALL/data toggle error response on a CSPLIT */
45298 +               if (hcint.b.stall) {
45299 +                       handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
45300 +               } else if (hcint.b.datatglerr) {
45301 +                       handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd);
45302 +               } else if (hcint.b.bblerr) {
45303 +                       handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
45304 +               } else if (hcint.b.ahberr) {
45305 +                       handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
45306 +               } else {
45307 +                       local_fiq_disable();
45308 +                       BUG();
45309 +               }
45310 +               break;
45311 +
45312 +       case FIQ_PER_SPLIT_DONE:
45313 +               /* Isoc IN or Interrupt IN/OUT */
45314 +
45315 +               /* Flow control here is different from the normal execution by the driver.
45316 +               * We need to completely ignore most of the driver's method of handling
45317 +               * split transactions and do it ourselves.
45318 +               */
45319 +               if (hc->ep_type == UE_INTERRUPT) {
45320 +                       if (hcint.b.nak) {
45321 +                                       handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
45322 +                       } else if (hc->ep_is_in) {
45323 +                               int len;
45324 +                               len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num);
45325 +                               //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length);
45326 +                               qtd->urb->actual_length += len;
45327 +                               if (qtd->urb->actual_length >= qtd->urb->length) {
45328 +                                       qtd->urb->status = 0;
45329 +                                       hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45330 +                                       release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45331 +                               } else {
45332 +                                       /* Interrupt transfer not complete yet - is it a short read? */
45333 +                                       if (len < hc->max_packet) {
45334 +                                               /* Interrupt transaction complete */
45335 +                                               qtd->urb->status = 0;
45336 +                                               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45337 +                                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45338 +                                       } else {
45339 +                                               /* Further transactions required */
45340 +                                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45341 +                                       }
45342 +                               }
45343 +                       } else {
45344 +                               /* Interrupt OUT complete. */
45345 +                               dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
45346 +                               qtd->urb->actual_length += hc->xfer_len;
45347 +                               if (qtd->urb->actual_length >= qtd->urb->length) {
45348 +                                       qtd->urb->status = 0;
45349 +                                       hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status);
45350 +                                       release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45351 +                               } else {
45352 +                                       release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45353 +                               }
45354 +                       }
45355 +               } else {
45356 +                       /* ISOC IN complete. */
45357 +                       struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45358 +                       int len = 0;
45359 +                       /* Record errors, update qtd. */
45360 +                       if (st->nr_errors) {
45361 +                               frame_desc->actual_length = 0;
45362 +                               frame_desc->status = -DWC_E_PROTOCOL;
45363 +                       } else {
45364 +                               frame_desc->status = 0;
45365 +                               /* Unswizzle dma */
45366 +                               len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num);
45367 +                               frame_desc->actual_length = len;
45368 +                       }
45369 +                       qtd->isoc_frame_index++;
45370 +                       if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45371 +                               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45372 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45373 +                       } else {
45374 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45375 +                       }
45376 +               }
45377 +               break;
45378 +
45379 +       case FIQ_PER_ISO_OUT_DONE: {
45380 +                       struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45381 +                       /* Record errors, update qtd. */
45382 +                       if (st->nr_errors) {
45383 +                               frame_desc->actual_length = 0;
45384 +                               frame_desc->status = -DWC_E_PROTOCOL;
45385 +                       } else {
45386 +                               frame_desc->status = 0;
45387 +                               frame_desc->actual_length = frame_desc->length;
45388 +                       }
45389 +                       qtd->isoc_frame_index++;
45390 +                       qtd->isoc_split_offset = 0;
45391 +                       if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45392 +                               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45393 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45394 +                       } else {
45395 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45396 +                       }
45397 +               }
45398 +               break;
45399 +
45400 +       case FIQ_PER_SPLIT_NYET_ABORTED:
45401 +               /* Doh. lost the data. */
45402 +               printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
45403 +                               "- FIQ reported NYET. Data may have been lost.\n",
45404 +                               hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
45405 +               if (hc->ep_type == UE_ISOCHRONOUS) {
45406 +                       struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45407 +                       /* Record errors, update qtd. */
45408 +                       frame_desc->actual_length = 0;
45409 +                       frame_desc->status = -DWC_E_PROTOCOL;
45410 +                       qtd->isoc_frame_index++;
45411 +                       qtd->isoc_split_offset = 0;
45412 +                       if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45413 +                               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45414 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45415 +                       } else {
45416 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45417 +                       }
45418 +               } else {
45419 +                       release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45420 +               }
45421 +               break;
45422 +
45423 +       case FIQ_HS_ISOC_DONE:
45424 +               /* The FIQ has performed a whole pile of isochronous transactions.
45425 +                * The status is recorded as the interrupt state should the transaction
45426 +                * fail.
45427 +                */
45428 +               dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num);
45429 +               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45430 +               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45431 +               break;
45432 +
45433 +       case FIQ_PER_SPLIT_LS_ABORTED:
45434 +               if (hcint.b.xacterr) {
45435 +                       /* Hub has responded with an ERR packet. Device
45436 +                        * has been unplugged or the port has been disabled.
45437 +                        * TODO: need to issue a reset to the hub port. */
45438 +                       qtd->error_count += 3;
45439 +                       handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45440 +               } else if (hcint.b.stall) {
45441 +                       handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
45442 +               } else if (hcint.b.bblerr) {
45443 +                       handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
45444 +               } else {
45445 +                       printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed "
45446 +                               "- FIQ reported FSM=%d. Data may have been lost.\n",
45447 +                               st->fsm, hc->dev_addr, hc->ep_num);
45448 +                       release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45449 +               }
45450 +               break;
45451 +
45452 +       case FIQ_PER_SPLIT_HS_ABORTED:
45453 +               /* Either the SSPLIT phase suffered transaction errors or something
45454 +                * unexpected happened.
45455 +                */
45456 +               qtd->error_count += 3;
45457 +               handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
45458 +               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45459 +               break;
45460 +
45461 +       case FIQ_PER_SPLIT_TIMEOUT:
45462 +               /* Couldn't complete in the nominated frame */
45463 +               printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed "
45464 +                               "- FIQ timed out. Data may have been lost.\n",
45465 +                               hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3);
45466 +               if (hc->ep_type == UE_ISOCHRONOUS) {
45467 +                       struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
45468 +                       /* Record errors, update qtd. */
45469 +                       frame_desc->actual_length = 0;
45470 +                       if (hc->ep_is_in) {
45471 +                               frame_desc->status = -DWC_E_NO_STREAM_RES;
45472 +                       } else {
45473 +                               frame_desc->status = -DWC_E_COMMUNICATION;
45474 +                       }
45475 +                       qtd->isoc_frame_index++;
45476 +                       if (qtd->isoc_frame_index == qtd->urb->packet_count) {
45477 +                               hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
45478 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
45479 +                       } else {
45480 +                               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE);
45481 +                       }
45482 +               } else {
45483 +                       release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45484 +               }
45485 +               break;
45486 +
45487 +       default:
45488 +               DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x",
45489 +                                       hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num);
45490 +               qtd->error_count++;
45491 +               release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
45492 +       }
45493 +       return;
45494 +}
45495 +
45496 +/** Handles interrupt for a specific Host Channel */
45497 +int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
45498 +{
45499 +       int retval = 0;
45500 +       hcint_data_t hcint;
45501 +       hcintmsk_data_t hcintmsk;
45502 +       dwc_hc_t *hc;
45503 +       dwc_otg_hc_regs_t *hc_regs;
45504 +       dwc_otg_qtd_t *qtd;
45505 +
45506 +       DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
45507 +
45508 +       hc = dwc_otg_hcd->hc_ptr_array[num];
45509 +       hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
45510 +       if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
45511 +               /* We are responding to a channel disable. Driver
45512 +                * state is cleared - our qtd has gone away.
45513 +                */
45514 +               release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status);
45515 +               return 1;
45516 +       }
45517 +       qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
45518 +
45519 +       /*
45520 +        * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ.
45521 +        * Execution path is fundamentally different for the channels after a FIQ has completed
45522 +        * a split transaction.
45523 +        */
45524 +       if (fiq_fsm_enable) {
45525 +               switch (dwc_otg_hcd->fiq_state->channel[num].fsm) {
45526 +                       case FIQ_PASSTHROUGH:
45527 +                               break;
45528 +                       case FIQ_PASSTHROUGH_ERRORSTATE:
45529 +                               /* Hook into the error count */
45530 +                               fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num);
45531 +                               if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) {
45532 +                                       qtd->error_count = 0;
45533 +                                       fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET   ");
45534 +                               }
45535 +                               break;
45536 +                       default:
45537 +                               dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num);
45538 +                               return 1;
45539 +               }
45540 +       }
45541 +
45542 +       hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
45543 +       hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
45544 +       hcint.d32 = hcint.d32 & hcintmsk.d32;
45545 +       if (!dwc_otg_hcd->core_if->dma_enable) {
45546 +               if (hcint.b.chhltd && hcint.d32 != 0x2) {
45547 +                       hcint.b.chhltd = 0;
45548 +               }
45549 +       }
45550 +
45551 +       if (hcint.b.xfercomp) {
45552 +               retval |=
45553 +                   handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45554 +               /*
45555 +                * If NYET occurred at same time as Xfer Complete, the NYET is
45556 +                * handled by the Xfer Complete interrupt handler. Don't want
45557 +                * to call the NYET interrupt handler in this case.
45558 +                */
45559 +               hcint.b.nyet = 0;
45560 +       }
45561 +       if (hcint.b.chhltd) {
45562 +               retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45563 +       }
45564 +       if (hcint.b.ahberr) {
45565 +               retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45566 +       }
45567 +       if (hcint.b.stall) {
45568 +               retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45569 +       }
45570 +       if (hcint.b.nak) {
45571 +               retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45572 +       }
45573 +       if (hcint.b.ack) {
45574 +               if(!hcint.b.chhltd)
45575 +                       retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45576 +       }
45577 +       if (hcint.b.nyet) {
45578 +               retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45579 +       }
45580 +       if (hcint.b.xacterr) {
45581 +               retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45582 +       }
45583 +       if (hcint.b.bblerr) {
45584 +               retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45585 +       }
45586 +       if (hcint.b.frmovrun) {
45587 +               retval |=
45588 +                   handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45589 +       }
45590 +       if (hcint.b.datatglerr) {
45591 +               retval |=
45592 +                   handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
45593 +       }
45594 +
45595 +       return retval;
45596 +}
45597 +#endif /* DWC_DEVICE_ONLY */
45598 --- /dev/null
45599 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
45600 @@ -0,0 +1,1005 @@
45601 +
45602 +/* ==========================================================================
45603 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
45604 + * $Revision: #20 $
45605 + * $Date: 2011/10/26 $
45606 + * $Change: 1872981 $
45607 + *
45608 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
45609 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
45610 + * otherwise expressly agreed to in writing between Synopsys and you.
45611 + *
45612 + * The Software IS NOT an item of Licensed Software or Licensed Product under
45613 + * any End User Software License Agreement or Agreement for Licensed Product
45614 + * with Synopsys or any supplement thereto. You are permitted to use and
45615 + * redistribute this Software in source and binary forms, with or without
45616 + * modification, provided that redistributions of source code must retain this
45617 + * notice. You may not view, use, disclose, copy or distribute this file or
45618 + * any information contained herein except pursuant to this license grant from
45619 + * Synopsys. If you do not agree with this notice, including the disclaimer
45620 + * below, then you are not authorized to use the Software.
45621 + *
45622 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
45623 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
45624 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45625 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
45626 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
45627 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
45628 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
45629 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
45630 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
45631 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
45632 + * DAMAGE.
45633 + * ========================================================================== */
45634 +#ifndef DWC_DEVICE_ONLY
45635 +
45636 +/**
45637 + * @file
45638 + *
45639 + * This file contains the implementation of the HCD. In Linux, the HCD
45640 + * implements the hc_driver API.
45641 + */
45642 +#include <linux/kernel.h>
45643 +#include <linux/module.h>
45644 +#include <linux/moduleparam.h>
45645 +#include <linux/init.h>
45646 +#include <linux/device.h>
45647 +#include <linux/errno.h>
45648 +#include <linux/list.h>
45649 +#include <linux/interrupt.h>
45650 +#include <linux/string.h>
45651 +#include <linux/dma-mapping.h>
45652 +#include <linux/version.h>
45653 +#include <asm/io.h>
45654 +#include <asm/fiq.h>
45655 +#include <linux/usb.h>
45656 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
45657 +#include <../drivers/usb/core/hcd.h>
45658 +#else
45659 +#include <linux/usb/hcd.h>
45660 +#endif
45661 +#include <asm/bug.h>
45662 +
45663 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
45664 +#define USB_URB_EP_LINKING 1
45665 +#else
45666 +#define USB_URB_EP_LINKING 0
45667 +#endif
45668 +
45669 +#include "dwc_otg_hcd_if.h"
45670 +#include "dwc_otg_dbg.h"
45671 +#include "dwc_otg_driver.h"
45672 +#include "dwc_otg_hcd.h"
45673 +
45674 +extern unsigned char  _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end;
45675 +
45676 +/**
45677 + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is
45678 + * qualified with its direction (possible 32 endpoints per device).
45679 + */
45680 +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
45681 +                                                    ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
45682 +
45683 +static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
45684 +
45685 +extern bool fiq_enable;
45686 +
45687 +/** @name Linux HC Driver API Functions */
45688 +/** @{ */
45689 +/* manage i/o requests, device state */
45690 +static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
45691 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
45692 +                      struct usb_host_endpoint *ep,
45693 +#endif
45694 +                      struct urb *urb, gfp_t mem_flags);
45695 +
45696 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
45697 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
45698 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
45699 +#endif
45700 +#else /* kernels at or post 2.6.30 */
45701 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd,
45702 +                               struct urb *urb, int status);
45703 +#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */
45704 +
45705 +static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
45706 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
45707 +static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
45708 +#endif
45709 +static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
45710 +extern int hcd_start(struct usb_hcd *hcd);
45711 +extern void hcd_stop(struct usb_hcd *hcd);
45712 +static int get_frame_number(struct usb_hcd *hcd);
45713 +extern int hub_status_data(struct usb_hcd *hcd, char *buf);
45714 +extern int hub_control(struct usb_hcd *hcd,
45715 +                      u16 typeReq,
45716 +                      u16 wValue, u16 wIndex, char *buf, u16 wLength);
45717 +
45718 +struct wrapper_priv_data {
45719 +       dwc_otg_hcd_t *dwc_otg_hcd;
45720 +};
45721 +
45722 +/** @} */
45723 +
45724 +static struct hc_driver dwc_otg_hc_driver = {
45725 +
45726 +       .description = dwc_otg_hcd_name,
45727 +       .product_desc = "DWC OTG Controller",
45728 +       .hcd_priv_size = sizeof(struct wrapper_priv_data),
45729 +
45730 +       .irq = dwc_otg_hcd_irq,
45731 +
45732 +       .flags = HCD_MEMORY | HCD_USB2,
45733 +
45734 +       //.reset =
45735 +       .start = hcd_start,
45736 +       //.suspend =
45737 +       //.resume =
45738 +       .stop = hcd_stop,
45739 +
45740 +       .urb_enqueue = dwc_otg_urb_enqueue,
45741 +       .urb_dequeue = dwc_otg_urb_dequeue,
45742 +       .endpoint_disable = endpoint_disable,
45743 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
45744 +       .endpoint_reset = endpoint_reset,
45745 +#endif
45746 +       .get_frame_number = get_frame_number,
45747 +
45748 +       .hub_status_data = hub_status_data,
45749 +       .hub_control = hub_control,
45750 +       //.bus_suspend =
45751 +       //.bus_resume =
45752 +};
45753 +
45754 +/** Gets the dwc_otg_hcd from a struct usb_hcd */
45755 +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
45756 +{
45757 +       struct wrapper_priv_data *p;
45758 +       p = (struct wrapper_priv_data *)(hcd->hcd_priv);
45759 +       return p->dwc_otg_hcd;
45760 +}
45761 +
45762 +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */
45763 +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
45764 +{
45765 +       return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
45766 +}
45767 +
45768 +/** Gets the usb_host_endpoint associated with an URB. */
45769 +inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
45770 +{
45771 +       struct usb_device *dev = urb->dev;
45772 +       int ep_num = usb_pipeendpoint(urb->pipe);
45773 +
45774 +       if (usb_pipein(urb->pipe))
45775 +               return dev->ep_in[ep_num];
45776 +       else
45777 +               return dev->ep_out[ep_num];
45778 +}
45779 +
45780 +static int _disconnect(dwc_otg_hcd_t * hcd)
45781 +{
45782 +       struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
45783 +
45784 +       usb_hcd->self.is_b_host = 0;
45785 +       return 0;
45786 +}
45787 +
45788 +static int _start(dwc_otg_hcd_t * hcd)
45789 +{
45790 +       struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
45791 +
45792 +       usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
45793 +       hcd_start(usb_hcd);
45794 +
45795 +       return 0;
45796 +}
45797 +
45798 +static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
45799 +                    uint32_t * port_addr)
45800 +{
45801 +   struct urb *urb = (struct urb *)urb_handle;
45802 +   struct usb_bus *bus;
45803 +#if 1 //GRAYG - temporary
45804 +   if (NULL == urb_handle)
45805 +      DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG
45806 +   if (NULL == urb->dev)
45807 +      DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG
45808 +   if (NULL == port_addr)
45809 +      DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG
45810 +#endif
45811 +   if (urb->dev->tt) {
45812 +        if (NULL == urb->dev->tt->hub) {
45813 +                DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n",
45814 +                           __func__); //GRAYG
45815 +                //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG
45816 +                *hub_addr = 0; //GRAYG
45817 +                // we probably shouldn't have a transaction translator if
45818 +                // there's no associated hub?
45819 +        } else {
45820 +               bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd));
45821 +               if (urb->dev->tt->hub == bus->root_hub)
45822 +                       *hub_addr = 0;
45823 +               else
45824 +                       *hub_addr = urb->dev->tt->hub->devnum;
45825 +       }
45826 +       *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1;
45827 +   } else {
45828 +        *hub_addr = 0;
45829 +       *port_addr = urb->dev->ttport;
45830 +   }
45831 +   return 0;
45832 +}
45833 +
45834 +static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
45835 +{
45836 +       struct urb *urb = (struct urb *)urb_handle;
45837 +       return urb->dev->speed;
45838 +}
45839 +
45840 +static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
45841 +{
45842 +       struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
45843 +       return usb_hcd->self.b_hnp_enable;
45844 +}
45845 +
45846 +static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
45847 +                                  struct urb *urb)
45848 +{
45849 +       hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
45850 +       if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
45851 +               hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
45852 +       } else {
45853 +               hcd_to_bus(hcd)->bandwidth_int_reqs++;
45854 +       }
45855 +}
45856 +
45857 +static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
45858 +                              struct urb *urb)
45859 +{
45860 +       hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
45861 +       if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
45862 +               hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
45863 +       } else {
45864 +               hcd_to_bus(hcd)->bandwidth_int_reqs--;
45865 +       }
45866 +}
45867 +
45868 +/**
45869 + * Sets the final status of an URB and returns it to the device driver. Any
45870 + * required cleanup of the URB is performed.  The HCD lock should be held on
45871 + * entry.
45872 + */
45873 +static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
45874 +                    dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
45875 +{
45876 +       struct urb *urb = (struct urb *)urb_handle;
45877 +       urb_tq_entry_t *new_entry;
45878 +       int rc = 0;
45879 +       if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
45880 +               DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
45881 +                          __func__, urb, usb_pipedevice(urb->pipe),
45882 +                          usb_pipeendpoint(urb->pipe),
45883 +                          usb_pipein(urb->pipe) ? "IN" : "OUT", status);
45884 +               if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
45885 +                       int i;
45886 +                       for (i = 0; i < urb->number_of_packets; i++) {
45887 +                               DWC_PRINTF("  ISO Desc %d status: %d\n",
45888 +                                          i, urb->iso_frame_desc[i].status);
45889 +                       }
45890 +               }
45891 +       }
45892 +       new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t));
45893 +       urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
45894 +       /* Convert status value. */
45895 +       switch (status) {
45896 +       case -DWC_E_PROTOCOL:
45897 +               status = -EPROTO;
45898 +               break;
45899 +       case -DWC_E_IN_PROGRESS:
45900 +               status = -EINPROGRESS;
45901 +               break;
45902 +       case -DWC_E_PIPE:
45903 +               status = -EPIPE;
45904 +               break;
45905 +       case -DWC_E_IO:
45906 +               status = -EIO;
45907 +               break;
45908 +       case -DWC_E_TIMEOUT:
45909 +               status = -ETIMEDOUT;
45910 +               break;
45911 +       case -DWC_E_OVERFLOW:
45912 +               status = -EOVERFLOW;
45913 +               break;
45914 +       case -DWC_E_SHUTDOWN:
45915 +               status = -ESHUTDOWN;
45916 +               break;
45917 +       default:
45918 +               if (status) {
45919 +                       DWC_PRINTF("Uknown urb status %d\n", status);
45920 +
45921 +               }
45922 +       }
45923 +
45924 +       if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
45925 +               int i;
45926 +
45927 +               urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
45928 +               for (i = 0; i < urb->number_of_packets; ++i) {
45929 +                       urb->iso_frame_desc[i].actual_length =
45930 +                           dwc_otg_hcd_urb_get_iso_desc_actual_length
45931 +                           (dwc_otg_urb, i);
45932 +                       urb->iso_frame_desc[i].status =
45933 +                           dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
45934 +               }
45935 +       }
45936 +
45937 +       urb->status = status;
45938 +       urb->hcpriv = NULL;
45939 +       if (!status) {
45940 +               if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
45941 +                   (urb->actual_length < urb->transfer_buffer_length)) {
45942 +                       urb->status = -EREMOTEIO;
45943 +               }
45944 +       }
45945 +
45946 +       if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
45947 +           (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
45948 +               struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
45949 +               if (ep) {
45950 +                       free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
45951 +                                          dwc_otg_hcd_get_ep_bandwidth(hcd,
45952 +                                                                       ep->hcpriv),
45953 +                                          urb);
45954 +               }
45955 +       }
45956 +       DWC_FREE(dwc_otg_urb);
45957 +       if (!new_entry) {
45958 +               DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n");
45959 +               urb->status = -EPROTO;
45960 +               /* don't schedule the tasklet -
45961 +                * directly return the packet here with error. */
45962 +#if USB_URB_EP_LINKING
45963 +               usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
45964 +#endif
45965 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
45966 +               usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
45967 +#else
45968 +               usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
45969 +#endif
45970 +       } else {
45971 +               new_entry->urb = urb;
45972 +#if USB_URB_EP_LINKING
45973 +               rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status);
45974 +               if(0 == rc) {
45975 +                       usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb);
45976 +               }
45977 +#endif
45978 +               if(0 == rc) {
45979 +                       DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry,
45980 +                                               urb_tq_entries);
45981 +                       DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet);
45982 +               }
45983 +       }
45984 +       return 0;
45985 +}
45986 +
45987 +static struct dwc_otg_hcd_function_ops hcd_fops = {
45988 +       .start = _start,
45989 +       .disconnect = _disconnect,
45990 +       .hub_info = _hub_info,
45991 +       .speed = _speed,
45992 +       .complete = _complete,
45993 +       .get_b_hnp_enable = _get_b_hnp_enable,
45994 +};
45995 +
45996 +static struct fiq_handler fh = {
45997 +  .name = "usb_fiq",
45998 +};
45999 +
46000 +static void hcd_init_fiq(void *cookie)
46001 +{
46002 +       dwc_otg_device_t *otg_dev = cookie;
46003 +       dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
46004 +       struct pt_regs regs;
46005 +       int irq;
46006 +
46007 +       if (claim_fiq(&fh)) {
46008 +               DWC_ERROR("Can't claim FIQ");
46009 +               BUG();
46010 +       }
46011 +       DWC_WARN("FIQ on core %d at 0x%08x",
46012 +                               smp_processor_id(),
46013 +                               (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
46014 +       DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
46015 +               set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
46016 +       memset(&regs,0,sizeof(regs));
46017 +
46018 +       regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state;
46019 +       if (fiq_fsm_enable) {
46020 +               regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels;
46021 +               //regs.ARM_r10 = dwc_otg_hcd->dma;
46022 +               regs.ARM_fp = (long) dwc_otg_fiq_fsm;
46023 +       } else {
46024 +               regs.ARM_fp = (long) dwc_otg_fiq_nop;
46025 +       }
46026 +
46027 +       regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4);
46028 +
46029 +//             __show_regs(&regs);
46030 +       set_fiq_regs(&regs);
46031 +
46032 +       //Set the mphi periph to  the required registers
46033 +       dwc_otg_hcd->fiq_state->mphi_regs.base    = otg_dev->os_dep.mphi_base;
46034 +       dwc_otg_hcd->fiq_state->mphi_regs.ctrl    = otg_dev->os_dep.mphi_base + 0x4c;
46035 +       dwc_otg_hcd->fiq_state->mphi_regs.outdda  = otg_dev->os_dep.mphi_base + 0x28;
46036 +       dwc_otg_hcd->fiq_state->mphi_regs.outddb  = otg_dev->os_dep.mphi_base + 0x2c;
46037 +       dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50;
46038 +       dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base;
46039 +       DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base);
46040 +       //Enable mphi peripheral
46041 +       writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl);
46042 +#ifdef DEBUG
46043 +       if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000)
46044 +               DWC_WARN("MPHI periph has been enabled");
46045 +       else
46046 +               DWC_WARN("MPHI periph has NOT been enabled");
46047 +#endif
46048 +       // Enable FIQ interrupt from USB peripheral
46049 +#ifdef CONFIG_MULTI_IRQ_HANDLER
46050 +       irq = platform_get_irq(otg_dev->os_dep.platformdev, 1);
46051 +#else
46052 +       irq = INTERRUPT_VC_USB;
46053 +#endif
46054 +       if (irq < 0) {
46055 +               DWC_ERROR("Can't get FIQ irq");
46056 +               return;
46057 +       }
46058 +       enable_fiq(irq);
46059 +       local_fiq_enable();
46060 +}
46061 +
46062 +/**
46063 + * Initializes the HCD. This function allocates memory for and initializes the
46064 + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
46065 + * USB bus with the core and calls the hc_driver->start() function. It returns
46066 + * a negative error on failure.
46067 + */
46068 +int hcd_init(dwc_bus_dev_t *_dev)
46069 +{
46070 +       struct usb_hcd *hcd = NULL;
46071 +       dwc_otg_hcd_t *dwc_otg_hcd = NULL;
46072 +       dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
46073 +       int retval = 0;
46074 +        u64 dmamask;
46075 +
46076 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev);
46077 +
46078 +       /* Set device flags indicating whether the HCD supports DMA. */
46079 +       if (dwc_otg_is_dma_enable(otg_dev->core_if))
46080 +                dmamask = DMA_BIT_MASK(32);
46081 +        else
46082 +                dmamask = 0;
46083 +
46084 +#if    defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE)
46085 +        dma_set_mask(&_dev->dev, dmamask);
46086 +        dma_set_coherent_mask(&_dev->dev, dmamask);
46087 +#elif  defined(PCI_INTERFACE)
46088 +        pci_set_dma_mask(_dev, dmamask);
46089 +        pci_set_consistent_dma_mask(_dev, dmamask);
46090 +#endif
46091 +
46092 +       /*
46093 +        * Allocate memory for the base HCD plus the DWC OTG HCD.
46094 +        * Initialize the base HCD.
46095 +        */
46096 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
46097 +       hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
46098 +#else
46099 +       hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
46100 +       hcd->has_tt = 1;
46101 +//      hcd->uses_new_polling = 1;
46102 +//      hcd->poll_rh = 0;
46103 +#endif
46104 +       if (!hcd) {
46105 +               retval = -ENOMEM;
46106 +               goto error1;
46107 +       }
46108 +
46109 +       hcd->regs = otg_dev->os_dep.base;
46110 +
46111 +
46112 +       /* Initialize the DWC OTG HCD. */
46113 +       dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
46114 +       if (!dwc_otg_hcd) {
46115 +               goto error2;
46116 +       }
46117 +       ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
46118 +           dwc_otg_hcd;
46119 +       otg_dev->hcd = dwc_otg_hcd;
46120 +
46121 +       if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
46122 +               goto error2;
46123 +       }
46124 +
46125 +       if (fiq_enable) {
46126 +               if (num_online_cpus() > 1) {
46127 +                       /* bcm2709: can run the FIQ on a separate core to IRQs */
46128 +                       smp_call_function_single(1, hcd_init_fiq, otg_dev, 1);
46129 +               } else {
46130 +                       smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
46131 +               }
46132 +       }
46133 +
46134 +       otg_dev->hcd->otg_dev = otg_dev;
46135 +       hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
46136 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
46137 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later
46138 +       hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
46139 +#endif
46140 +       /* Don't support SG list at this point */
46141 +       hcd->self.sg_tablesize = 0;
46142 +#endif
46143 +       /*
46144 +        * Finish generic HCD initialization and start the HCD. This function
46145 +        * allocates the DMA buffer pool, registers the USB bus, requests the
46146 +        * IRQ line, and calls hcd_start method.
46147 +        */
46148 +#ifdef PLATFORM_INTERFACE
46149 +       retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED);
46150 +#else
46151 +       retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED);
46152 +#endif
46153 +       if (retval < 0) {
46154 +               goto error2;
46155 +       }
46156 +
46157 +       dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
46158 +       return 0;
46159 +
46160 +error2:
46161 +       usb_put_hcd(hcd);
46162 +error1:
46163 +       return retval;
46164 +}
46165 +
46166 +/**
46167 + * Removes the HCD.
46168 + * Frees memory and resources associated with the HCD and deregisters the bus.
46169 + */
46170 +void hcd_remove(dwc_bus_dev_t *_dev)
46171 +{
46172 +       dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
46173 +       dwc_otg_hcd_t *dwc_otg_hcd;
46174 +       struct usb_hcd *hcd;
46175 +
46176 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev);
46177 +
46178 +       if (!otg_dev) {
46179 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
46180 +               return;
46181 +       }
46182 +
46183 +       dwc_otg_hcd = otg_dev->hcd;
46184 +
46185 +       if (!dwc_otg_hcd) {
46186 +               DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
46187 +               return;
46188 +       }
46189 +
46190 +       hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
46191 +
46192 +       if (!hcd) {
46193 +               DWC_DEBUGPL(DBG_ANY,
46194 +                           "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
46195 +                           __func__);
46196 +               return;
46197 +       }
46198 +       usb_remove_hcd(hcd);
46199 +       dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
46200 +       dwc_otg_hcd_remove(dwc_otg_hcd);
46201 +       usb_put_hcd(hcd);
46202 +}
46203 +
46204 +/* =========================================================================
46205 + *  Linux HC Driver Functions
46206 + * ========================================================================= */
46207 +
46208 +/** Initializes the DWC_otg controller and its root hub and prepares it for host
46209 + * mode operation. Activates the root port. Returns 0 on success and a negative
46210 + * error code on failure. */
46211 +int hcd_start(struct usb_hcd *hcd)
46212 +{
46213 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46214 +       struct usb_bus *bus;
46215 +
46216 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
46217 +       bus = hcd_to_bus(hcd);
46218 +
46219 +       hcd->state = HC_STATE_RUNNING;
46220 +       if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
46221 +               return 0;
46222 +       }
46223 +
46224 +       /* Initialize and connect root hub if one is not already attached */
46225 +       if (bus->root_hub) {
46226 +               DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
46227 +               /* Inform the HUB driver to resume. */
46228 +               usb_hcd_resume_root_hub(hcd);
46229 +       }
46230 +
46231 +       return 0;
46232 +}
46233 +
46234 +/**
46235 + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
46236 + * stopped.
46237 + */
46238 +void hcd_stop(struct usb_hcd *hcd)
46239 +{
46240 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46241 +
46242 +       dwc_otg_hcd_stop(dwc_otg_hcd);
46243 +}
46244 +
46245 +/** Returns the current frame number. */
46246 +static int get_frame_number(struct usb_hcd *hcd)
46247 +{
46248 +       hprt0_data_t hprt0;
46249 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46250 +       hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
46251 +       if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
46252 +               return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3;
46253 +       else
46254 +               return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
46255 +}
46256 +
46257 +#ifdef DEBUG
46258 +static void dump_urb_info(struct urb *urb, char *fn_name)
46259 +{
46260 +       DWC_PRINTF("%s, urb %p\n", fn_name, urb);
46261 +       DWC_PRINTF("  Device address: %d\n", usb_pipedevice(urb->pipe));
46262 +       DWC_PRINTF("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
46263 +                  (usb_pipein(urb->pipe) ? "IN" : "OUT"));
46264 +       DWC_PRINTF("  Endpoint type: %s\n", ( {
46265 +                                            char *pipetype;
46266 +                                            switch (usb_pipetype(urb->pipe)) {
46267 +case PIPE_CONTROL:
46268 +pipetype = "CONTROL"; break; case PIPE_BULK:
46269 +pipetype = "BULK"; break; case PIPE_INTERRUPT:
46270 +pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
46271 +pipetype = "ISOCHRONOUS"; break; default:
46272 +                                            pipetype = "UNKNOWN"; break;};
46273 +                                            pipetype;}
46274 +                  )) ;
46275 +       DWC_PRINTF("  Speed: %s\n", ( {
46276 +                                    char *speed; switch (urb->dev->speed) {
46277 +case USB_SPEED_HIGH:
46278 +speed = "HIGH"; break; case USB_SPEED_FULL:
46279 +speed = "FULL"; break; case USB_SPEED_LOW:
46280 +speed = "LOW"; break; default:
46281 +                                    speed = "UNKNOWN"; break;};
46282 +                                    speed;}
46283 +                  )) ;
46284 +       DWC_PRINTF("  Max packet size: %d\n",
46285 +                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
46286 +       DWC_PRINTF("  Data buffer length: %d\n", urb->transfer_buffer_length);
46287 +       DWC_PRINTF("  Transfer buffer: %p, Transfer DMA: %p\n",
46288 +                  urb->transfer_buffer, (void *)urb->transfer_dma);
46289 +       DWC_PRINTF("  Setup buffer: %p, Setup DMA: %p\n",
46290 +                  urb->setup_packet, (void *)urb->setup_dma);
46291 +       DWC_PRINTF("  Interval: %d\n", urb->interval);
46292 +       if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
46293 +               int i;
46294 +               for (i = 0; i < urb->number_of_packets; i++) {
46295 +                       DWC_PRINTF("  ISO Desc %d:\n", i);
46296 +                       DWC_PRINTF("    offset: %d, length %d\n",
46297 +                                  urb->iso_frame_desc[i].offset,
46298 +                                  urb->iso_frame_desc[i].length);
46299 +               }
46300 +       }
46301 +}
46302 +#endif
46303 +
46304 +/** Starts processing a USB transfer request specified by a USB Request Block
46305 + * (URB). mem_flags indicates the type of memory allocation to use while
46306 + * processing this URB. */
46307 +static int dwc_otg_urb_enqueue(struct usb_hcd *hcd,
46308 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
46309 +                      struct usb_host_endpoint *ep,
46310 +#endif
46311 +                      struct urb *urb, gfp_t mem_flags)
46312 +{
46313 +       int retval = 0;
46314 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
46315 +       struct usb_host_endpoint *ep = urb->ep;
46316 +#endif
46317 +       dwc_irqflags_t irqflags;
46318 +        void **ref_ep_hcpriv = &ep->hcpriv;
46319 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46320 +       dwc_otg_hcd_urb_t *dwc_otg_urb;
46321 +       int i;
46322 +       int alloc_bandwidth = 0;
46323 +       uint8_t ep_type = 0;
46324 +       uint32_t flags = 0;
46325 +       void *buf;
46326 +
46327 +#ifdef DEBUG
46328 +       if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46329 +               dump_urb_info(urb, "dwc_otg_urb_enqueue");
46330 +       }
46331 +#endif
46332 +
46333 +       if (!urb->transfer_buffer && urb->transfer_buffer_length)
46334 +               return -EINVAL;
46335 +
46336 +       if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
46337 +           || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
46338 +               if (!dwc_otg_hcd_is_bandwidth_allocated
46339 +                   (dwc_otg_hcd, ref_ep_hcpriv)) {
46340 +                       alloc_bandwidth = 1;
46341 +               }
46342 +       }
46343 +
46344 +       switch (usb_pipetype(urb->pipe)) {
46345 +       case PIPE_CONTROL:
46346 +               ep_type = USB_ENDPOINT_XFER_CONTROL;
46347 +               break;
46348 +       case PIPE_ISOCHRONOUS:
46349 +               ep_type = USB_ENDPOINT_XFER_ISOC;
46350 +               break;
46351 +       case PIPE_BULK:
46352 +               ep_type = USB_ENDPOINT_XFER_BULK;
46353 +               break;
46354 +       case PIPE_INTERRUPT:
46355 +               ep_type = USB_ENDPOINT_XFER_INT;
46356 +               break;
46357 +       default:
46358 +                DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe));
46359 +       }
46360 +
46361 +        /* # of packets is often 0 - do we really need to call this then? */
46362 +       dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
46363 +                                           urb->number_of_packets,
46364 +                                           mem_flags == GFP_ATOMIC ? 1 : 0);
46365 +
46366 +       if(dwc_otg_urb == NULL)
46367 +               return -ENOMEM;
46368 +
46369 +       if (!dwc_otg_urb && urb->number_of_packets)
46370 +               return -ENOMEM;
46371 +
46372 +       dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
46373 +                                    usb_pipeendpoint(urb->pipe), ep_type,
46374 +                                    usb_pipein(urb->pipe),
46375 +                                    usb_maxpacket(urb->dev, urb->pipe,
46376 +                                                  !(usb_pipein(urb->pipe))));
46377 +
46378 +       buf = urb->transfer_buffer;
46379 +       if (hcd->self.uses_dma && !buf && urb->transfer_buffer_length) {
46380 +               /*
46381 +                * Calculate virtual address from physical address,
46382 +                * because some class driver may not fill transfer_buffer.
46383 +                * In Buffer DMA mode virual address is used,
46384 +                * when handling non DWORD aligned buffers.
46385 +                */
46386 +               buf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma);
46387 +               dev_warn_once(&urb->dev->dev,
46388 +                             "USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\n",
46389 +                             &urb->transfer_dma, buf);
46390 +       }
46391 +
46392 +       if (!(urb->transfer_flags & URB_NO_INTERRUPT))
46393 +               flags |= URB_GIVEBACK_ASAP;
46394 +       if (urb->transfer_flags & URB_ZERO_PACKET)
46395 +               flags |= URB_SEND_ZERO_PACKET;
46396 +
46397 +       dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
46398 +                                  urb->transfer_dma,
46399 +                                  urb->transfer_buffer_length,
46400 +                                  urb->setup_packet,
46401 +                                  urb->setup_dma, flags, urb->interval);
46402 +
46403 +       for (i = 0; i < urb->number_of_packets; ++i) {
46404 +               dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
46405 +                                                   urb->
46406 +                                                   iso_frame_desc[i].offset,
46407 +                                                   urb->
46408 +                                                   iso_frame_desc[i].length);
46409 +       }
46410 +
46411 +       DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags);
46412 +       urb->hcpriv = dwc_otg_urb;
46413 +#if USB_URB_EP_LINKING
46414 +       retval = usb_hcd_link_urb_to_ep(hcd, urb);
46415 +       if (0 == retval)
46416 +#endif
46417 +       {
46418 +               retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb,
46419 +                                               /*(dwc_otg_qh_t **)*/
46420 +                                               ref_ep_hcpriv, 1);
46421 +               if (0 == retval) {
46422 +                       if (alloc_bandwidth) {
46423 +                               allocate_bus_bandwidth(hcd,
46424 +                                               dwc_otg_hcd_get_ep_bandwidth(
46425 +                                                       dwc_otg_hcd, *ref_ep_hcpriv),
46426 +                                               urb);
46427 +                       }
46428 +               } else {
46429 +                       DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval);
46430 +#if USB_URB_EP_LINKING
46431 +                       usb_hcd_unlink_urb_from_ep(hcd, urb);
46432 +#endif
46433 +                       DWC_FREE(dwc_otg_urb);
46434 +                       urb->hcpriv = NULL;
46435 +                       if (retval == -DWC_E_NO_DEVICE)
46436 +                               retval = -ENODEV;
46437 +               }
46438 +       }
46439 +#if USB_URB_EP_LINKING
46440 +       else
46441 +       {
46442 +               DWC_FREE(dwc_otg_urb);
46443 +               urb->hcpriv = NULL;
46444 +       }
46445 +#endif
46446 +       DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags);
46447 +       return retval;
46448 +}
46449 +
46450 +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate
46451 + * success.  */
46452 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
46453 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
46454 +#else
46455 +static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
46456 +#endif
46457 +{
46458 +       dwc_irqflags_t flags;
46459 +       dwc_otg_hcd_t *dwc_otg_hcd;
46460 +        int rc;
46461 +
46462 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
46463 +
46464 +       dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46465 +
46466 +#ifdef DEBUG
46467 +       if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46468 +               dump_urb_info(urb, "dwc_otg_urb_dequeue");
46469 +       }
46470 +#endif
46471 +
46472 +       DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
46473 +       rc = usb_hcd_check_unlink_urb(hcd, urb, status);
46474 +       if (0 == rc) {
46475 +               if(urb->hcpriv != NULL) {
46476 +                       dwc_otg_hcd_urb_dequeue(dwc_otg_hcd,
46477 +                                           (dwc_otg_hcd_urb_t *)urb->hcpriv);
46478 +
46479 +                       DWC_FREE(urb->hcpriv);
46480 +                       urb->hcpriv = NULL;
46481 +               }
46482 +        }
46483 +
46484 +        if (0 == rc) {
46485 +               /* Higher layer software sets URB status. */
46486 +#if USB_URB_EP_LINKING
46487 +                usb_hcd_unlink_urb_from_ep(hcd, urb);
46488 +#endif
46489 +               DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
46490 +
46491 +
46492 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
46493 +                usb_hcd_giveback_urb(hcd, urb);
46494 +#else
46495 +                usb_hcd_giveback_urb(hcd, urb, status);
46496 +#endif
46497 +                if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
46498 +                        DWC_PRINTF("Called usb_hcd_giveback_urb() \n");
46499 +                        DWC_PRINTF("  1urb->status = %d\n", urb->status);
46500 +                }
46501 +                DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n");
46502 +        } else {
46503 +               DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
46504 +                DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n",
46505 +                            rc);
46506 +        }
46507 +
46508 +       return rc;
46509 +}
46510 +
46511 +/* Frees resources in the DWC_otg controller related to a given endpoint. Also
46512 + * clears state in the HCD related to the endpoint. Any URBs for the endpoint
46513 + * must already be dequeued. */
46514 +static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
46515 +{
46516 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46517 +
46518 +       DWC_DEBUGPL(DBG_HCD,
46519 +                   "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
46520 +                   "endpoint=%d\n", ep->desc.bEndpointAddress,
46521 +                   dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
46522 +       dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
46523 +       ep->hcpriv = NULL;
46524 +}
46525 +
46526 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
46527 +/* Resets endpoint specific parameter values, in current version used to reset
46528 + * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
46529 +static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
46530 +{
46531 +       dwc_irqflags_t flags;
46532 +       struct usb_device *udev = NULL;
46533 +       int epnum = usb_endpoint_num(&ep->desc);
46534 +       int is_out = usb_endpoint_dir_out(&ep->desc);
46535 +       int is_control = usb_endpoint_xfer_control(&ep->desc);
46536 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46537 +        struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep);
46538 +
46539 +       if (dev)
46540 +               udev = to_usb_device(dev);
46541 +       else
46542 +               return;
46543 +
46544 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
46545 +
46546 +       DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
46547 +       usb_settoggle(udev, epnum, is_out, 0);
46548 +       if (is_control)
46549 +               usb_settoggle(udev, epnum, !is_out, 0);
46550 +
46551 +       if (ep->hcpriv) {
46552 +               dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
46553 +       }
46554 +       DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
46555 +}
46556 +#endif
46557 +
46558 +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
46559 + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
46560 + * interrupt.
46561 + *
46562 + * This function is called by the USB core when an interrupt occurs */
46563 +static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
46564 +{
46565 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46566 +       int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
46567 +       if (retval != 0) {
46568 +               S3C2410X_CLEAR_EINTPEND();
46569 +       }
46570 +       return IRQ_RETVAL(retval);
46571 +}
46572 +
46573 +/** Creates Status Change bitmap for the root hub and root port. The bitmap is
46574 + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
46575 + * is the status change indicator for the single root port. Returns 1 if either
46576 + * change indicator is 1, otherwise returns 0. */
46577 +int hub_status_data(struct usb_hcd *hcd, char *buf)
46578 +{
46579 +       dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
46580 +
46581 +       buf[0] = 0;
46582 +       buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
46583 +
46584 +       return (buf[0] != 0);
46585 +}
46586 +
46587 +/** Handles hub class-specific requests. */
46588 +int hub_control(struct usb_hcd *hcd,
46589 +               u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
46590 +{
46591 +       int retval;
46592 +
46593 +       retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
46594 +                                        typeReq, wValue, wIndex, buf, wLength);
46595 +
46596 +       switch (retval) {
46597 +       case -DWC_E_INVALID:
46598 +               retval = -EINVAL;
46599 +               break;
46600 +       }
46601 +
46602 +       return retval;
46603 +}
46604 +
46605 +#endif /* DWC_DEVICE_ONLY */
46606 --- /dev/null
46607 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
46608 @@ -0,0 +1,957 @@
46609 +/* ==========================================================================
46610 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
46611 + * $Revision: #44 $
46612 + * $Date: 2011/10/26 $
46613 + * $Change: 1873028 $
46614 + *
46615 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
46616 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
46617 + * otherwise expressly agreed to in writing between Synopsys and you.
46618 + *
46619 + * The Software IS NOT an item of Licensed Software or Licensed Product under
46620 + * any End User Software License Agreement or Agreement for Licensed Product
46621 + * with Synopsys or any supplement thereto. You are permitted to use and
46622 + * redistribute this Software in source and binary forms, with or without
46623 + * modification, provided that redistributions of source code must retain this
46624 + * notice. You may not view, use, disclose, copy or distribute this file or
46625 + * any information contained herein except pursuant to this license grant from
46626 + * Synopsys. If you do not agree with this notice, including the disclaimer
46627 + * below, then you are not authorized to use the Software.
46628 + *
46629 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
46630 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46631 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
46632 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
46633 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46634 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
46635 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46636 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
46637 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
46638 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
46639 + * DAMAGE.
46640 + * ========================================================================== */
46641 +#ifndef DWC_DEVICE_ONLY
46642 +
46643 +/**
46644 + * @file
46645 + *
46646 + * This file contains the functions to manage Queue Heads and Queue
46647 + * Transfer Descriptors.
46648 + */
46649 +
46650 +#include "dwc_otg_hcd.h"
46651 +#include "dwc_otg_regs.h"
46652 +
46653 +extern bool microframe_schedule;
46654 +
46655 +/**
46656 + * Free each QTD in the QH's QTD-list then free the QH.  QH should already be
46657 + * removed from a list.  QTD list should already be empty if called from URB
46658 + * Dequeue.
46659 + *
46660 + * @param hcd HCD instance.
46661 + * @param qh The QH to free.
46662 + */
46663 +void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
46664 +{
46665 +       dwc_otg_qtd_t *qtd, *qtd_tmp;
46666 +       dwc_irqflags_t flags;
46667 +
46668 +       /* Free each QTD in the QTD list */
46669 +       DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
46670 +       DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
46671 +               DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
46672 +               dwc_otg_hcd_qtd_free(qtd);
46673 +       }
46674 +
46675 +       if (hcd->core_if->dma_desc_enable) {
46676 +               dwc_otg_hcd_qh_free_ddma(hcd, qh);
46677 +       } else if (qh->dw_align_buf) {
46678 +               uint32_t buf_size;
46679 +               if (qh->ep_type == UE_ISOCHRONOUS) {
46680 +                       buf_size = 4096;
46681 +               } else {
46682 +                       buf_size = hcd->core_if->core_params->max_transfer_size;
46683 +               }
46684 +               DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
46685 +       }
46686 +
46687 +       DWC_FREE(qh);
46688 +       DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
46689 +       return;
46690 +}
46691 +
46692 +#define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)
46693 +#define HS_HOST_DELAY          5       /* nanoseconds */
46694 +#define FS_LS_HOST_DELAY       1000    /* nanoseconds */
46695 +#define HUB_LS_SETUP           333     /* nanoseconds */
46696 +#define NS_TO_US(ns)           ((ns + 500) / 1000)
46697 +                               /* convert & round nanoseconds to microseconds */
46698 +
46699 +static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
46700 +{
46701 +       unsigned long retval;
46702 +
46703 +       switch (speed) {
46704 +       case USB_SPEED_HIGH:
46705 +               if (is_isoc) {
46706 +                       retval =
46707 +                           ((38 * 8 * 2083) +
46708 +                            (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
46709 +                           HS_HOST_DELAY;
46710 +               } else {
46711 +                       retval =
46712 +                           ((55 * 8 * 2083) +
46713 +                            (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
46714 +                           HS_HOST_DELAY;
46715 +               }
46716 +               break;
46717 +       case USB_SPEED_FULL:
46718 +               if (is_isoc) {
46719 +                       retval =
46720 +                           (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
46721 +                       if (is_in) {
46722 +                               retval = 7268 + FS_LS_HOST_DELAY + retval;
46723 +                       } else {
46724 +                               retval = 6265 + FS_LS_HOST_DELAY + retval;
46725 +                       }
46726 +               } else {
46727 +                       retval =
46728 +                           (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
46729 +                       retval = 9107 + FS_LS_HOST_DELAY + retval;
46730 +               }
46731 +               break;
46732 +       case USB_SPEED_LOW:
46733 +               if (is_in) {
46734 +                       retval =
46735 +                           (67667 * (31 + 10 * BitStuffTime(bytecount))) /
46736 +                           1000;
46737 +                       retval =
46738 +                           64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
46739 +                           retval;
46740 +               } else {
46741 +                       retval =
46742 +                           (66700 * (31 + 10 * BitStuffTime(bytecount))) /
46743 +                           1000;
46744 +                       retval =
46745 +                           64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
46746 +                           retval;
46747 +               }
46748 +               break;
46749 +       default:
46750 +               DWC_WARN("Unknown device speed\n");
46751 +               retval = -1;
46752 +       }
46753 +
46754 +       return NS_TO_US(retval);
46755 +}
46756 +
46757 +/**
46758 + * Initializes a QH structure.
46759 + *
46760 + * @param hcd The HCD state structure for the DWC OTG controller.
46761 + * @param qh  The QH to init.
46762 + * @param urb Holds the information about the device/endpoint that we need
46763 + *           to initialize the QH.
46764 + */
46765 +#define SCHEDULE_SLOP 10
46766 +void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
46767 +{
46768 +       char *speed, *type;
46769 +       int dev_speed;
46770 +       uint32_t hub_addr, hub_port;
46771 +
46772 +       dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
46773 +
46774 +       /* Initialize QH */
46775 +       qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
46776 +       qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
46777 +
46778 +       qh->data_toggle = DWC_OTG_HC_PID_DATA0;
46779 +       qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
46780 +       DWC_CIRCLEQ_INIT(&qh->qtd_list);
46781 +       DWC_LIST_INIT(&qh->qh_list_entry);
46782 +       qh->channel = NULL;
46783 +
46784 +       /* FS/LS Enpoint on HS Hub
46785 +        * NOT virtual root hub */
46786 +       dev_speed = hcd->fops->speed(hcd, urb->priv);
46787 +
46788 +       hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
46789 +       qh->do_split = 0;
46790 +       if (microframe_schedule)
46791 +               qh->speed = dev_speed;
46792 +
46793 +       qh->nak_frame = 0xffff;
46794 +
46795 +       if (((dev_speed == USB_SPEED_LOW) ||
46796 +            (dev_speed == USB_SPEED_FULL)) &&
46797 +           (hub_addr != 0 && hub_addr != 1)) {
46798 +               DWC_DEBUGPL(DBG_HCD,
46799 +                           "QH init: EP %d: TT found at hub addr %d, for port %d\n",
46800 +                           dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
46801 +                           hub_port);
46802 +               qh->do_split = 1;
46803 +               qh->skip_count = 0;
46804 +       }
46805 +
46806 +       if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
46807 +               /* Compute scheduling parameters once and save them. */
46808 +               hprt0_data_t hprt;
46809 +
46810 +               /** @todo Account for split transfers in the bus time. */
46811 +               int bytecount =
46812 +                   dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
46813 +
46814 +               qh->usecs =
46815 +                   calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
46816 +                                 qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
46817 +                                 bytecount);
46818 +               /* Start in a slightly future (micro)frame. */
46819 +               qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
46820 +                                                   SCHEDULE_SLOP);
46821 +               qh->interval = urb->interval;
46822 +
46823 +#if 0
46824 +               /* Increase interrupt polling rate for debugging. */
46825 +               if (qh->ep_type == UE_INTERRUPT) {
46826 +                       qh->interval = 8;
46827 +               }
46828 +#endif
46829 +               hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
46830 +               if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
46831 +                   ((dev_speed == USB_SPEED_LOW) ||
46832 +                    (dev_speed == USB_SPEED_FULL))) {
46833 +                       qh->interval *= 8;
46834 +                       qh->sched_frame |= 0x7;
46835 +                       qh->start_split_frame = qh->sched_frame;
46836 +               }
46837 +
46838 +       }
46839 +
46840 +       DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
46841 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
46842 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
46843 +                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
46844 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
46845 +                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
46846 +                   dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
46847 +       switch (dev_speed) {
46848 +       case USB_SPEED_LOW:
46849 +               qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
46850 +               speed = "low";
46851 +               break;
46852 +       case USB_SPEED_FULL:
46853 +               qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
46854 +               speed = "full";
46855 +               break;
46856 +       case USB_SPEED_HIGH:
46857 +               qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
46858 +               speed = "high";
46859 +               break;
46860 +       default:
46861 +               speed = "?";
46862 +               break;
46863 +       }
46864 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
46865 +
46866 +       switch (qh->ep_type) {
46867 +       case UE_ISOCHRONOUS:
46868 +               type = "isochronous";
46869 +               break;
46870 +       case UE_INTERRUPT:
46871 +               type = "interrupt";
46872 +               break;
46873 +       case UE_CONTROL:
46874 +               type = "control";
46875 +               break;
46876 +       case UE_BULK:
46877 +               type = "bulk";
46878 +               break;
46879 +       default:
46880 +               type = "?";
46881 +               break;
46882 +       }
46883 +
46884 +       DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n", type);
46885 +
46886 +#ifdef DEBUG
46887 +       if (qh->ep_type == UE_INTERRUPT) {
46888 +               DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
46889 +                           qh->usecs);
46890 +               DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
46891 +                           qh->interval);
46892 +       }
46893 +#endif
46894 +
46895 +}
46896 +
46897 +/**
46898 + * This function allocates and initializes a QH.
46899 + *
46900 + * @param hcd The HCD state structure for the DWC OTG controller.
46901 + * @param urb Holds the information about the device/endpoint that we need
46902 + *           to initialize the QH.
46903 + * @param atomic_alloc Flag to do atomic allocation if needed
46904 + *
46905 + * @return Returns pointer to the newly allocated QH, or NULL on error. */
46906 +dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
46907 +                                   dwc_otg_hcd_urb_t * urb, int atomic_alloc)
46908 +{
46909 +       dwc_otg_qh_t *qh;
46910 +
46911 +       /* Allocate memory */
46912 +       /** @todo add memflags argument */
46913 +       qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
46914 +       if (qh == NULL) {
46915 +               DWC_ERROR("qh allocation failed");
46916 +               return NULL;
46917 +       }
46918 +
46919 +       qh_init(hcd, qh, urb);
46920 +
46921 +       if (hcd->core_if->dma_desc_enable
46922 +           && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
46923 +               dwc_otg_hcd_qh_free(hcd, qh);
46924 +               return NULL;
46925 +       }
46926 +
46927 +       return qh;
46928 +}
46929 +
46930 +/* microframe_schedule=0 start */
46931 +
46932 +/**
46933 + * Checks that a channel is available for a periodic transfer.
46934 + *
46935 + * @return 0 if successful, negative error code otherise.
46936 + */
46937 +static int periodic_channel_available(dwc_otg_hcd_t * hcd)
46938 +{
46939 +       /*
46940 +        * Currently assuming that there is a dedicated host channnel for each
46941 +        * periodic transaction plus at least one host channel for
46942 +        * non-periodic transactions.
46943 +        */
46944 +       int status;
46945 +       int num_channels;
46946 +
46947 +       num_channels = hcd->core_if->core_params->host_channels;
46948 +       if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
46949 +           && (hcd->periodic_channels < num_channels - 1)) {
46950 +               status = 0;
46951 +       } else {
46952 +               DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
46953 +                       __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels);    //NOTICE
46954 +               status = -DWC_E_NO_SPACE;
46955 +       }
46956 +
46957 +       return status;
46958 +}
46959 +
46960 +/**
46961 + * Checks that there is sufficient bandwidth for the specified QH in the
46962 + * periodic schedule. For simplicity, this calculation assumes that all the
46963 + * transfers in the periodic schedule may occur in the same (micro)frame.
46964 + *
46965 + * @param hcd The HCD state structure for the DWC OTG controller.
46966 + * @param qh QH containing periodic bandwidth required.
46967 + *
46968 + * @return 0 if successful, negative error code otherwise.
46969 + */
46970 +static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
46971 +{
46972 +       int status;
46973 +       int16_t max_claimed_usecs;
46974 +
46975 +       status = 0;
46976 +
46977 +       if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
46978 +               /*
46979 +                * High speed mode.
46980 +                * Max periodic usecs is 80% x 125 usec = 100 usec.
46981 +                */
46982 +
46983 +               max_claimed_usecs = 100 - qh->usecs;
46984 +       } else {
46985 +               /*
46986 +                * Full speed mode.
46987 +                * Max periodic usecs is 90% x 1000 usec = 900 usec.
46988 +                */
46989 +               max_claimed_usecs = 900 - qh->usecs;
46990 +       }
46991 +
46992 +       if (hcd->periodic_usecs > max_claimed_usecs) {
46993 +               DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs);        //NOTICE
46994 +               status = -DWC_E_NO_SPACE;
46995 +       }
46996 +
46997 +       return status;
46998 +}
46999 +
47000 +/* microframe_schedule=0 end */
47001 +
47002 +/**
47003 + * Microframe scheduler
47004 + * track the total use in hcd->frame_usecs
47005 + * keep each qh use in qh->frame_usecs
47006 + * when surrendering the qh then donate the time back
47007 + */
47008 +const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 };
47009 +
47010 +/*
47011 + * called from dwc_otg_hcd.c:dwc_otg_hcd_init
47012 + */
47013 +int init_hcd_usecs(dwc_otg_hcd_t *_hcd)
47014 +{
47015 +       int i;
47016 +       for (i=0; i<8; i++) {
47017 +               _hcd->frame_usecs[i] = max_uframe_usecs[i];
47018 +       }
47019 +       return 0;
47020 +}
47021 +
47022 +static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47023 +{
47024 +       int i;
47025 +       unsigned short utime;
47026 +       int t_left;
47027 +       int ret;
47028 +       int done;
47029 +
47030 +       ret = -1;
47031 +       utime = _qh->usecs;
47032 +       t_left = utime;
47033 +       i = 0;
47034 +       done = 0;
47035 +       while (done == 0) {
47036 +               /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */
47037 +               if (utime <= _hcd->frame_usecs[i]) {
47038 +                       _hcd->frame_usecs[i] -= utime;
47039 +                       _qh->frame_usecs[i] += utime;
47040 +                       t_left -= utime;
47041 +                       ret = i;
47042 +                       done = 1;
47043 +                       return ret;
47044 +               } else {
47045 +                       i++;
47046 +                       if (i == 8) {
47047 +                               done = 1;
47048 +                               ret = -1;
47049 +                       }
47050 +               }
47051 +       }
47052 +       return ret;
47053 + }
47054 +
47055 +/*
47056 + * use this for FS apps that can span multiple uframes
47057 +  */
47058 +static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47059 +{
47060 +       int i;
47061 +       int j;
47062 +       unsigned short utime;
47063 +       int t_left;
47064 +       int ret;
47065 +       int done;
47066 +       unsigned short xtime;
47067 +
47068 +       ret = -1;
47069 +       utime = _qh->usecs;
47070 +       t_left = utime;
47071 +       i = 0;
47072 +       done = 0;
47073 +loop:
47074 +       while (done == 0) {
47075 +               if(_hcd->frame_usecs[i] <= 0) {
47076 +                       i++;
47077 +                       if (i == 8) {
47078 +                               done = 1;
47079 +                               ret = -1;
47080 +                       }
47081 +                       goto loop;
47082 +               }
47083 +
47084 +               /*
47085 +                * we need n consecutive slots
47086 +                * so use j as a start slot j plus j+1 must be enough time (for now)
47087 +                */
47088 +               xtime= _hcd->frame_usecs[i];
47089 +               for (j = i+1 ; j < 8 ; j++ ) {
47090 +                       /*
47091 +                        * if we add this frame remaining time to xtime we may
47092 +                        * be OK, if not we need to test j for a complete frame
47093 +                        */
47094 +                       if ((xtime+_hcd->frame_usecs[j]) < utime) {
47095 +                               if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) {
47096 +                                       j = 8;
47097 +                                       ret = -1;
47098 +                                       continue;
47099 +                               }
47100 +                       }
47101 +                       if (xtime >= utime) {
47102 +                               ret = i;
47103 +                               j = 8;  /* stop loop with a good value ret */
47104 +                               continue;
47105 +                       }
47106 +                       /* add the frame time to x time */
47107 +                       xtime += _hcd->frame_usecs[j];
47108 +                      /* we must have a fully available next frame or break */
47109 +                      if ((xtime < utime)
47110 +                                      && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) {
47111 +                              ret = -1;
47112 +                              j = 8;  /* stop loop with a bad value ret */
47113 +                              continue;
47114 +                      }
47115 +               }
47116 +               if (ret >= 0) {
47117 +                       t_left = utime;
47118 +                       for (j = i; (t_left>0) && (j < 8); j++ ) {
47119 +                               t_left -= _hcd->frame_usecs[j];
47120 +                               if ( t_left <= 0 ) {
47121 +                                       _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left;
47122 +                                       _hcd->frame_usecs[j]= -t_left;
47123 +                                       ret = i;
47124 +                                       done = 1;
47125 +                               } else {
47126 +                                       _qh->frame_usecs[j] += _hcd->frame_usecs[j];
47127 +                                       _hcd->frame_usecs[j] = 0;
47128 +                               }
47129 +                       }
47130 +               } else {
47131 +                       i++;
47132 +                       if (i == 8) {
47133 +                               done = 1;
47134 +                               ret = -1;
47135 +                       }
47136 +               }
47137 +       }
47138 +       return ret;
47139 +}
47140 +
47141 +static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh)
47142 +{
47143 +       int ret;
47144 +       ret = -1;
47145 +
47146 +       if (_qh->speed == USB_SPEED_HIGH) {
47147 +               /* if this is a hs transaction we need a full frame */
47148 +               ret = find_single_uframe(_hcd, _qh);
47149 +       } else {
47150 +               /* if this is a fs transaction we may need a sequence of frames */
47151 +               ret = find_multi_uframe(_hcd, _qh);
47152 +       }
47153 +       return ret;
47154 +}
47155 +
47156 +/**
47157 + * Checks that the max transfer size allowed in a host channel is large enough
47158 + * to handle the maximum data transfer in a single (micro)frame for a periodic
47159 + * transfer.
47160 + *
47161 + * @param hcd The HCD state structure for the DWC OTG controller.
47162 + * @param qh QH for a periodic endpoint.
47163 + *
47164 + * @return 0 if successful, negative error code otherwise.
47165 + */
47166 +static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47167 +{
47168 +       int status;
47169 +       uint32_t max_xfer_size;
47170 +       uint32_t max_channel_xfer_size;
47171 +
47172 +       status = 0;
47173 +
47174 +       max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
47175 +       max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
47176 +
47177 +       if (max_xfer_size > max_channel_xfer_size) {
47178 +               DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
47179 +                               __func__, max_xfer_size, max_channel_xfer_size);        //NOTICE
47180 +               status = -DWC_E_NO_SPACE;
47181 +       }
47182 +
47183 +       return status;
47184 +}
47185 +
47186 +
47187 +
47188 +/**
47189 + * Schedules an interrupt or isochronous transfer in the periodic schedule.
47190 + *
47191 + * @param hcd The HCD state structure for the DWC OTG controller.
47192 + * @param qh QH for the periodic transfer. The QH should already contain the
47193 + * scheduling information.
47194 + *
47195 + * @return 0 if successful, negative error code otherwise.
47196 + */
47197 +static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47198 +{
47199 +       int status = 0;
47200 +
47201 +       if (microframe_schedule) {
47202 +               int frame;
47203 +               status = find_uframe(hcd, qh);
47204 +               frame = -1;
47205 +               if (status == 0) {
47206 +                       frame = 7;
47207 +               } else {
47208 +                       if (status > 0 )
47209 +                               frame = status-1;
47210 +               }
47211 +
47212 +               /* Set the new frame up */
47213 +               if (frame > -1) {
47214 +                       qh->sched_frame &= ~0x7;
47215 +                       qh->sched_frame |= (frame & 7);
47216 +               }
47217 +
47218 +               if (status != -1)
47219 +                       status = 0;
47220 +       } else {
47221 +               status = periodic_channel_available(hcd);
47222 +               if (status) {
47223 +                       DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__);        //NOTICE
47224 +                       return status;
47225 +               }
47226 +
47227 +               status = check_periodic_bandwidth(hcd, qh);
47228 +       }
47229 +       if (status) {
47230 +               DWC_INFO("%s: Insufficient periodic bandwidth for "
47231 +                           "periodic transfer.\n", __func__);
47232 +               return status;
47233 +       }
47234 +       status = check_max_xfer_size(hcd, qh);
47235 +       if (status) {
47236 +               DWC_INFO("%s: Channel max transfer size too small "
47237 +                           "for periodic transfer.\n", __func__);
47238 +               return status;
47239 +       }
47240 +
47241 +       if (hcd->core_if->dma_desc_enable) {
47242 +               /* Don't rely on SOF and start in ready schedule */
47243 +               DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
47244 +       }
47245 +       else {
47246 +               if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame)))
47247 +               {
47248 +                       hcd->fiq_state->next_sched_frame = qh->sched_frame;
47249 +
47250 +               }
47251 +               /* Always start in the inactive schedule. */
47252 +               DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
47253 +       }
47254 +
47255 +       if (!microframe_schedule) {
47256 +               /* Reserve the periodic channel. */
47257 +               hcd->periodic_channels++;
47258 +       }
47259 +
47260 +       /* Update claimed usecs per (micro)frame. */
47261 +       hcd->periodic_usecs += qh->usecs;
47262 +
47263 +       return status;
47264 +}
47265 +
47266 +
47267 +/**
47268 + * This function adds a QH to either the non periodic or periodic schedule if
47269 + * it is not already in the schedule. If the QH is already in the schedule, no
47270 + * action is taken.
47271 + *
47272 + * @return 0 if successful, negative error code otherwise.
47273 + */
47274 +int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47275 +{
47276 +       int status = 0;
47277 +       gintmsk_data_t intr_mask = {.d32 = 0 };
47278 +
47279 +       if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
47280 +               /* QH already in a schedule. */
47281 +               return status;
47282 +       }
47283 +
47284 +       /* Add the new QH to the appropriate schedule */
47285 +       if (dwc_qh_is_non_per(qh)) {
47286 +               /* Always start in the inactive schedule. */
47287 +               DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
47288 +                                    &qh->qh_list_entry);
47289 +               //hcd->fiq_state->kick_np_queues = 1;
47290 +       } else {
47291 +               status = schedule_periodic(hcd, qh);
47292 +               if ( !hcd->periodic_qh_count ) {
47293 +                       intr_mask.b.sofintr = 1;
47294 +                       if (fiq_enable) {
47295 +                               local_fiq_disable();
47296 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
47297 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
47298 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
47299 +                               local_fiq_enable();
47300 +                       } else {
47301 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
47302 +                       }
47303 +               }
47304 +               hcd->periodic_qh_count++;
47305 +       }
47306 +
47307 +       return status;
47308 +}
47309 +
47310 +/**
47311 + * Removes an interrupt or isochronous transfer from the periodic schedule.
47312 + *
47313 + * @param hcd The HCD state structure for the DWC OTG controller.
47314 + * @param qh QH for the periodic transfer.
47315 + */
47316 +static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47317 +{
47318 +       int i;
47319 +       DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
47320 +
47321 +       /* Update claimed usecs per (micro)frame. */
47322 +       hcd->periodic_usecs -= qh->usecs;
47323 +
47324 +       if (!microframe_schedule) {
47325 +               /* Release the periodic channel reservation. */
47326 +               hcd->periodic_channels--;
47327 +       } else {
47328 +               for (i = 0; i < 8; i++) {
47329 +                       hcd->frame_usecs[i] += qh->frame_usecs[i];
47330 +                       qh->frame_usecs[i] = 0;
47331 +               }
47332 +       }
47333 +}
47334 +
47335 +/**
47336 + * Removes a QH from either the non-periodic or periodic schedule.  Memory is
47337 + * not freed.
47338 + *
47339 + * @param hcd The HCD state structure.
47340 + * @param qh QH to remove from schedule. */
47341 +void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
47342 +{
47343 +       gintmsk_data_t intr_mask = {.d32 = 0 };
47344 +
47345 +       if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
47346 +               /* QH is not in a schedule. */
47347 +               return;
47348 +       }
47349 +
47350 +       if (dwc_qh_is_non_per(qh)) {
47351 +               if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
47352 +                       hcd->non_periodic_qh_ptr =
47353 +                           hcd->non_periodic_qh_ptr->next;
47354 +               }
47355 +               DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
47356 +               //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive))
47357 +               //      hcd->fiq_state->kick_np_queues = 1;
47358 +       } else {
47359 +               deschedule_periodic(hcd, qh);
47360 +               hcd->periodic_qh_count--;
47361 +               if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
47362 +                       intr_mask.b.sofintr = 1;
47363 +                       if (fiq_enable) {
47364 +                               local_fiq_disable();
47365 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
47366 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
47367 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
47368 +                               local_fiq_enable();
47369 +                       } else {
47370 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
47371 +                       }
47372 +               }
47373 +       }
47374 +}
47375 +
47376 +/**
47377 + * Deactivates a QH. For non-periodic QHs, removes the QH from the active
47378 + * non-periodic schedule. The QH is added to the inactive non-periodic
47379 + * schedule if any QTDs are still attached to the QH.
47380 + *
47381 + * For periodic QHs, the QH is removed from the periodic queued schedule. If
47382 + * there are any QTDs still attached to the QH, the QH is added to either the
47383 + * periodic inactive schedule or the periodic ready schedule and its next
47384 + * scheduled frame is calculated. The QH is placed in the ready schedule if
47385 + * the scheduled frame has been reached already. Otherwise it's placed in the
47386 + * inactive schedule. If there are no QTDs attached to the QH, the QH is
47387 + * completely removed from the periodic schedule.
47388 + */
47389 +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
47390 +                              int sched_next_periodic_split)
47391 +{
47392 +       if (dwc_qh_is_non_per(qh)) {
47393 +               dwc_otg_hcd_qh_remove(hcd, qh);
47394 +               if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
47395 +                       /* Add back to inactive non-periodic schedule. */
47396 +                       dwc_otg_hcd_qh_add(hcd, qh);
47397 +                       //hcd->fiq_state->kick_np_queues = 1;
47398 +               }
47399 +       } else {
47400 +               uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
47401 +
47402 +               if (qh->do_split) {
47403 +                       /* Schedule the next continuing periodic split transfer */
47404 +                       if (sched_next_periodic_split) {
47405 +
47406 +                               qh->sched_frame = frame_number;
47407 +
47408 +                               if (dwc_frame_num_le(frame_number,
47409 +                                                    dwc_frame_num_inc
47410 +                                                    (qh->start_split_frame,
47411 +                                                     1))) {
47412 +                                       /*
47413 +                                        * Allow one frame to elapse after start
47414 +                                        * split microframe before scheduling
47415 +                                        * complete split, but DONT if we are
47416 +                                        * doing the next start split in the
47417 +                                        * same frame for an ISOC out.
47418 +                                        */
47419 +                                       if ((qh->ep_type != UE_ISOCHRONOUS) ||
47420 +                                           (qh->ep_is_in != 0)) {
47421 +                                               qh->sched_frame =
47422 +                                                   dwc_frame_num_inc(qh->sched_frame, 1);
47423 +                                       }
47424 +                               }
47425 +                       } else {
47426 +                               qh->sched_frame =
47427 +                                   dwc_frame_num_inc(qh->start_split_frame,
47428 +                                                     qh->interval);
47429 +                               if (dwc_frame_num_le
47430 +                                   (qh->sched_frame, frame_number)) {
47431 +                                       qh->sched_frame = frame_number;
47432 +                               }
47433 +                               qh->sched_frame |= 0x7;
47434 +                               qh->start_split_frame = qh->sched_frame;
47435 +                       }
47436 +               } else {
47437 +                       qh->sched_frame =
47438 +                           dwc_frame_num_inc(qh->sched_frame, qh->interval);
47439 +                       if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
47440 +                               qh->sched_frame = frame_number;
47441 +                       }
47442 +               }
47443 +
47444 +               if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
47445 +                       dwc_otg_hcd_qh_remove(hcd, qh);
47446 +               } else {
47447 +                       /*
47448 +                        * Remove from periodic_sched_queued and move to
47449 +                        * appropriate queue.
47450 +                        */
47451 +                       if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) ||
47452 +                       (!microframe_schedule && qh->sched_frame == frame_number)) {
47453 +                               DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
47454 +                                                  &qh->qh_list_entry);
47455 +                       } else {
47456 +                               if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame))
47457 +                               {
47458 +                                       hcd->fiq_state->next_sched_frame = qh->sched_frame;
47459 +                               }
47460 +
47461 +                               DWC_LIST_MOVE_HEAD
47462 +                                   (&hcd->periodic_sched_inactive,
47463 +                                    &qh->qh_list_entry);
47464 +                       }
47465 +               }
47466 +       }
47467 +}
47468 +
47469 +/**
47470 + * This function allocates and initializes a QTD.
47471 + *
47472 + * @param urb The URB to create a QTD from.  Each URB-QTD pair will end up
47473 + *           pointing to each other so each pair should have a unique correlation.
47474 + * @param atomic_alloc Flag to do atomic alloc if needed
47475 + *
47476 + * @return Returns pointer to the newly allocated QTD, or NULL on error. */
47477 +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
47478 +{
47479 +       dwc_otg_qtd_t *qtd;
47480 +
47481 +       qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
47482 +       if (qtd == NULL) {
47483 +               return NULL;
47484 +       }
47485 +
47486 +       dwc_otg_hcd_qtd_init(qtd, urb);
47487 +       return qtd;
47488 +}
47489 +
47490 +/**
47491 + * Initializes a QTD structure.
47492 + *
47493 + * @param qtd The QTD to initialize.
47494 + * @param urb The URB to use for initialization.  */
47495 +void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
47496 +{
47497 +       dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
47498 +       qtd->urb = urb;
47499 +       if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
47500 +               /*
47501 +                * The only time the QTD data toggle is used is on the data
47502 +                * phase of control transfers. This phase always starts with
47503 +                * DATA1.
47504 +                */
47505 +               qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
47506 +               qtd->control_phase = DWC_OTG_CONTROL_SETUP;
47507 +       }
47508 +
47509 +       /* start split */
47510 +       qtd->complete_split = 0;
47511 +       qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
47512 +       qtd->isoc_split_offset = 0;
47513 +       qtd->in_process = 0;
47514 +
47515 +       /* Store the qtd ptr in the urb to reference what QTD. */
47516 +       urb->qtd = qtd;
47517 +       return;
47518 +}
47519 +
47520 +/**
47521 + * This function adds a QTD to the QTD-list of a QH.  It will find the correct
47522 + * QH to place the QTD into.  If it does not find a QH, then it will create a
47523 + * new QH. If the QH to which the QTD is added is not currently scheduled, it
47524 + * is placed into the proper schedule based on its EP type.
47525 + * HCD lock must be held and interrupts must be disabled on entry
47526 + *
47527 + * @param[in] qtd The QTD to add
47528 + * @param[in] hcd The DWC HCD structure
47529 + * @param[out] qh out parameter to return queue head
47530 + * @param atomic_alloc Flag to do atomic alloc if needed
47531 + *
47532 + * @return 0 if successful, negative error code otherwise.
47533 + */
47534 +int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
47535 +                       dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
47536 +{
47537 +       int retval = 0;
47538 +       dwc_otg_hcd_urb_t *urb = qtd->urb;
47539 +
47540 +       /*
47541 +        * Get the QH which holds the QTD-list to insert to. Create QH if it
47542 +        * doesn't exist.
47543 +        */
47544 +       if (*qh == NULL) {
47545 +               *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
47546 +               if (*qh == NULL) {
47547 +                       retval = -DWC_E_NO_MEMORY;
47548 +                       goto done;
47549 +               } else {
47550 +                       if (fiq_enable)
47551 +                               hcd->fiq_state->kick_np_queues = 1;
47552 +               }
47553 +       }
47554 +       retval = dwc_otg_hcd_qh_add(hcd, *qh);
47555 +       if (retval == 0) {
47556 +               DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
47557 +                                       qtd_list_entry);
47558 +               qtd->qh = *qh;
47559 +       }
47560 +done:
47561 +
47562 +       return retval;
47563 +}
47564 +
47565 +#endif /* DWC_DEVICE_ONLY */
47566 --- /dev/null
47567 +++ b/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h
47568 @@ -0,0 +1,188 @@
47569 +#ifndef _DWC_OS_DEP_H_
47570 +#define _DWC_OS_DEP_H_
47571 +
47572 +/**
47573 + * @file
47574 + *
47575 + * This file contains OS dependent structures.
47576 + *
47577 + */
47578 +
47579 +#include <linux/kernel.h>
47580 +#include <linux/module.h>
47581 +#include <linux/moduleparam.h>
47582 +#include <linux/init.h>
47583 +#include <linux/device.h>
47584 +#include <linux/errno.h>
47585 +#include <linux/types.h>
47586 +#include <linux/slab.h>
47587 +#include <linux/list.h>
47588 +#include <linux/interrupt.h>
47589 +#include <linux/ctype.h>
47590 +#include <linux/string.h>
47591 +#include <linux/dma-mapping.h>
47592 +#include <linux/jiffies.h>
47593 +#include <linux/delay.h>
47594 +#include <linux/timer.h>
47595 +#include <linux/workqueue.h>
47596 +#include <linux/stat.h>
47597 +#include <linux/pci.h>
47598 +
47599 +#include <linux/version.h>
47600 +
47601 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
47602 +# include <linux/irq.h>
47603 +#endif
47604 +
47605 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
47606 +# include <linux/usb/ch9.h>
47607 +#else
47608 +# include <linux/usb_ch9.h>
47609 +#endif
47610 +
47611 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
47612 +# include <linux/usb/gadget.h>
47613 +#else
47614 +# include <linux/usb_gadget.h>
47615 +#endif
47616 +
47617 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
47618 +# include <asm/irq.h>
47619 +#endif
47620 +
47621 +#ifdef PCI_INTERFACE
47622 +# include <asm/io.h>
47623 +#endif
47624 +
47625 +#ifdef LM_INTERFACE
47626 +# include <asm/unaligned.h>
47627 +# include <asm/sizes.h>
47628 +# include <asm/param.h>
47629 +# include <asm/io.h>
47630 +# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
47631 +#  include <asm/arch/hardware.h>
47632 +#  include <asm/arch/lm.h>
47633 +#  include <asm/arch/irqs.h>
47634 +#  include <asm/arch/regs-irq.h>
47635 +# else
47636 +/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure -
47637 +   here we assume that the machine architecture provides definitions
47638 +   in its own header
47639 +*/
47640 +#  include <mach/lm.h>
47641 +#  include <mach/hardware.h>
47642 +# endif
47643 +#endif
47644 +
47645 +#ifdef PLATFORM_INTERFACE
47646 +#include <linux/platform_device.h>
47647 +#include <asm/mach/map.h>
47648 +#endif
47649 +
47650 +/** The OS page size */
47651 +#define DWC_OS_PAGE_SIZE       PAGE_SIZE
47652 +
47653 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
47654 +typedef int gfp_t;
47655 +#endif
47656 +
47657 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
47658 +# define IRQF_SHARED SA_SHIRQ
47659 +#endif
47660 +
47661 +typedef struct os_dependent {
47662 +       /** Base address returned from ioremap() */
47663 +       void *base;
47664 +
47665 +       /** Register offset for Diagnostic API */
47666 +       uint32_t reg_offset;
47667 +
47668 +       /** Base address for MPHI peripheral */
47669 +       void *mphi_base;
47670 +
47671 +#ifdef LM_INTERFACE
47672 +       struct lm_device *lmdev;
47673 +#elif  defined(PCI_INTERFACE)
47674 +       struct pci_dev *pcidev;
47675 +
47676 +       /** Start address of a PCI region */
47677 +       resource_size_t rsrc_start;
47678 +
47679 +       /** Length address of a PCI region */
47680 +       resource_size_t rsrc_len;
47681 +#elif  defined(PLATFORM_INTERFACE)
47682 +       struct platform_device *platformdev;
47683 +#endif
47684 +
47685 +} os_dependent_t;
47686 +
47687 +#ifdef __cplusplus
47688 +}
47689 +#endif
47690 +
47691 +
47692 +
47693 +/* Type for the our device on the chosen bus */
47694 +#if   defined(LM_INTERFACE)
47695 +typedef struct lm_device       dwc_bus_dev_t;
47696 +#elif defined(PCI_INTERFACE)
47697 +typedef struct pci_dev         dwc_bus_dev_t;
47698 +#elif defined(PLATFORM_INTERFACE)
47699 +typedef struct platform_device dwc_bus_dev_t;
47700 +#endif
47701 +
47702 +/* Helper macro to retrieve drvdata from the device on the chosen bus */
47703 +#if    defined(LM_INTERFACE)
47704 +#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev)
47705 +#elif  defined(PCI_INTERFACE)
47706 +#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev)
47707 +#elif  defined(PLATFORM_INTERFACE)
47708 +#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev)
47709 +#endif
47710 +
47711 +/**
47712 + * Helper macro returning the otg_device structure of a given struct device
47713 + *
47714 + * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev)
47715 + */
47716 +#ifdef LM_INTERFACE
47717 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
47718 +                struct lm_device *lm_dev = \
47719 +                        container_of(_dev, struct lm_device, dev); \
47720 +                _var = lm_get_drvdata(lm_dev); \
47721 +        } while (0)
47722 +
47723 +#elif defined(PCI_INTERFACE)
47724 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
47725 +                _var = dev_get_drvdata(_dev); \
47726 +        } while (0)
47727 +
47728 +#elif defined(PLATFORM_INTERFACE)
47729 +#define DWC_OTG_GETDRVDEV(_var, _dev) do { \
47730 +                struct platform_device *platform_dev = \
47731 +                        container_of(_dev, struct platform_device, dev); \
47732 +                _var = platform_get_drvdata(platform_dev); \
47733 +        } while (0)
47734 +#endif
47735 +
47736 +
47737 +/**
47738 + * Helper macro returning the struct dev of the given struct os_dependent
47739 + *
47740 + * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep)
47741 + */
47742 +#ifdef LM_INTERFACE
47743 +#define DWC_OTG_OS_GETDEV(_osdep) \
47744 +        ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev)
47745 +#elif defined(PCI_INTERFACE)
47746 +#define DWC_OTG_OS_GETDEV(_osdep) \
47747 +        ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev)
47748 +#elif defined(PLATFORM_INTERFACE)
47749 +#define DWC_OTG_OS_GETDEV(_osdep) \
47750 +        ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev)
47751 +#endif
47752 +
47753 +
47754 +
47755 +
47756 +#endif /* _DWC_OS_DEP_H_ */
47757 --- /dev/null
47758 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c
47759 @@ -0,0 +1,2712 @@
47760 +/* ==========================================================================
47761 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
47762 + * $Revision: #101 $
47763 + * $Date: 2012/08/10 $
47764 + * $Change: 2047372 $
47765 + *
47766 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
47767 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
47768 + * otherwise expressly agreed to in writing between Synopsys and you.
47769 + *
47770 + * The Software IS NOT an item of Licensed Software or Licensed Product under
47771 + * any End User Software License Agreement or Agreement for Licensed Product
47772 + * with Synopsys or any supplement thereto. You are permitted to use and
47773 + * redistribute this Software in source and binary forms, with or without
47774 + * modification, provided that redistributions of source code must retain this
47775 + * notice. You may not view, use, disclose, copy or distribute this file or
47776 + * any information contained herein except pursuant to this license grant from
47777 + * Synopsys. If you do not agree with this notice, including the disclaimer
47778 + * below, then you are not authorized to use the Software.
47779 + *
47780 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
47781 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47782 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47783 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
47784 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47785 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47786 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
47787 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
47788 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
47789 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
47790 + * DAMAGE.
47791 + * ========================================================================== */
47792 +#ifndef DWC_HOST_ONLY
47793 +
47794 +/** @file
47795 + * This file implements PCD Core. All code in this file is portable and doesn't
47796 + * use any OS specific functions.
47797 + * PCD Core provides Interface, defined in <code><dwc_otg_pcd_if.h></code>
47798 + * header file, which can be used to implement OS specific PCD interface.
47799 + *
47800 + * An important function of the PCD is managing interrupts generated
47801 + * by the DWC_otg controller. The implementation of the DWC_otg device
47802 + * mode interrupt service routines is in dwc_otg_pcd_intr.c.
47803 + *
47804 + * @todo Add Device Mode test modes (Test J mode, Test K mode, etc).
47805 + * @todo Does it work when the request size is greater than DEPTSIZ
47806 + * transfer size
47807 + *
47808 + */
47809 +
47810 +#include "dwc_otg_pcd.h"
47811 +
47812 +#ifdef DWC_UTE_CFI
47813 +#include "dwc_otg_cfi.h"
47814 +
47815 +extern int init_cfi(cfiobject_t * cfiobj);
47816 +#endif
47817 +
47818 +/**
47819 + * Choose endpoint from ep arrays using usb_ep structure.
47820 + */
47821 +static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
47822 +{
47823 +       int i;
47824 +       if (pcd->ep0.priv == handle) {
47825 +               return &pcd->ep0;
47826 +       }
47827 +       for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
47828 +               if (pcd->in_ep[i].priv == handle)
47829 +                       return &pcd->in_ep[i];
47830 +               if (pcd->out_ep[i].priv == handle)
47831 +                       return &pcd->out_ep[i];
47832 +       }
47833 +
47834 +       return NULL;
47835 +}
47836 +
47837 +/**
47838 + * This function completes a request.  It call's the request call back.
47839 + */
47840 +void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
47841 +                         int32_t status)
47842 +{
47843 +       unsigned stopped = ep->stopped;
47844 +
47845 +       DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
47846 +       DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
47847 +
47848 +       /* don't modify queue heads during completion callback */
47849 +       ep->stopped = 1;
47850 +       /* spin_unlock/spin_lock now done in fops->complete() */
47851 +       ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
47852 +                               req->actual);
47853 +
47854 +       if (ep->pcd->request_pending > 0) {
47855 +               --ep->pcd->request_pending;
47856 +       }
47857 +
47858 +       ep->stopped = stopped;
47859 +       DWC_FREE(req);
47860 +}
47861 +
47862 +/**
47863 + * This function terminates all the requsts in the EP request queue.
47864 + */
47865 +void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
47866 +{
47867 +       dwc_otg_pcd_request_t *req;
47868 +
47869 +       ep->stopped = 1;
47870 +
47871 +       /* called with irqs blocked?? */
47872 +       while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
47873 +               req = DWC_CIRCLEQ_FIRST(&ep->queue);
47874 +               dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
47875 +       }
47876 +}
47877 +
47878 +void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
47879 +                      const struct dwc_otg_pcd_function_ops *fops)
47880 +{
47881 +       pcd->fops = fops;
47882 +}
47883 +
47884 +/**
47885 + * PCD Callback function for initializing the PCD when switching to
47886 + * device mode.
47887 + *
47888 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
47889 + */
47890 +static int32_t dwc_otg_pcd_start_cb(void *p)
47891 +{
47892 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
47893 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
47894 +
47895 +       /*
47896 +        * Initialized the Core for Device mode.
47897 +        */
47898 +       if (dwc_otg_is_device_mode(core_if)) {
47899 +               dwc_otg_core_dev_init(core_if);
47900 +               /* Set core_if's lock pointer to the pcd->lock */
47901 +               core_if->lock = pcd->lock;
47902 +       }
47903 +       return 1;
47904 +}
47905 +
47906 +/** CFI-specific buffer allocation function for EP */
47907 +#ifdef DWC_UTE_CFI
47908 +uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
47909 +                             size_t buflen, int flags)
47910 +{
47911 +       dwc_otg_pcd_ep_t *ep;
47912 +       ep = get_ep_from_handle(pcd, pep);
47913 +       if (!ep) {
47914 +               DWC_WARN("bad ep\n");
47915 +               return -DWC_E_INVALID;
47916 +       }
47917 +
47918 +       return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
47919 +                                         flags);
47920 +}
47921 +#else
47922 +uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
47923 +                             size_t buflen, int flags);
47924 +#endif
47925 +
47926 +/**
47927 + * PCD Callback function for notifying the PCD when resuming from
47928 + * suspend.
47929 + *
47930 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
47931 + */
47932 +static int32_t dwc_otg_pcd_resume_cb(void *p)
47933 +{
47934 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
47935 +
47936 +       if (pcd->fops->resume) {
47937 +               pcd->fops->resume(pcd);
47938 +       }
47939 +
47940 +       /* Stop the SRP timeout timer. */
47941 +       if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
47942 +           || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
47943 +               if (GET_CORE_IF(pcd)->srp_timer_started) {
47944 +                       GET_CORE_IF(pcd)->srp_timer_started = 0;
47945 +                       DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
47946 +               }
47947 +       }
47948 +       return 1;
47949 +}
47950 +
47951 +/**
47952 + * PCD Callback function for notifying the PCD device is suspended.
47953 + *
47954 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
47955 + */
47956 +static int32_t dwc_otg_pcd_suspend_cb(void *p)
47957 +{
47958 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
47959 +
47960 +       if (pcd->fops->suspend) {
47961 +               DWC_SPINUNLOCK(pcd->lock);
47962 +               pcd->fops->suspend(pcd);
47963 +               DWC_SPINLOCK(pcd->lock);
47964 +       }
47965 +
47966 +       return 1;
47967 +}
47968 +
47969 +/**
47970 + * PCD Callback function for stopping the PCD when switching to Host
47971 + * mode.
47972 + *
47973 + * @param p void pointer to the <code>dwc_otg_pcd_t</code>
47974 + */
47975 +static int32_t dwc_otg_pcd_stop_cb(void *p)
47976 +{
47977 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
47978 +       extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
47979 +
47980 +       dwc_otg_pcd_stop(pcd);
47981 +       return 1;
47982 +}
47983 +
47984 +/**
47985 + * PCD Callback structure for handling mode switching.
47986 + */
47987 +static dwc_otg_cil_callbacks_t pcd_callbacks = {
47988 +       .start = dwc_otg_pcd_start_cb,
47989 +       .stop = dwc_otg_pcd_stop_cb,
47990 +       .suspend = dwc_otg_pcd_suspend_cb,
47991 +       .resume_wakeup = dwc_otg_pcd_resume_cb,
47992 +       .p = 0,                 /* Set at registration */
47993 +};
47994 +
47995 +/**
47996 + * This function allocates a DMA Descriptor chain for the Endpoint
47997 + * buffer to be used for a transfer to/from the specified endpoint.
47998 + */
47999 +dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
48000 +                                                   uint32_t count)
48001 +{
48002 +       return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t),
48003 +                                                       dma_desc_addr);
48004 +}
48005 +
48006 +/**
48007 + * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
48008 + */
48009 +void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
48010 +                               uint32_t dma_desc_addr, uint32_t count)
48011 +{
48012 +       DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
48013 +                    dma_desc_addr);
48014 +}
48015 +
48016 +#ifdef DWC_EN_ISOC
48017 +
48018 +/**
48019 + * This function initializes a descriptor chain for Isochronous transfer
48020 + *
48021 + * @param core_if Programming view of DWC_otg controller.
48022 + * @param dwc_ep The EP to start the transfer on.
48023 + *
48024 + */
48025 +void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
48026 +                                       dwc_ep_t * dwc_ep)
48027 +{
48028 +
48029 +       dsts_data_t dsts = {.d32 = 0 };
48030 +       depctl_data_t depctl = {.d32 = 0 };
48031 +       volatile uint32_t *addr;
48032 +       int i, j;
48033 +       uint32_t len;
48034 +
48035 +       if (dwc_ep->is_in)
48036 +               dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
48037 +       else
48038 +               dwc_ep->desc_cnt =
48039 +                   dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
48040 +                   dwc_ep->bInterval;
48041 +
48042 +       /** Allocate descriptors for double buffering */
48043 +       dwc_ep->iso_desc_addr =
48044 +           dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
48045 +                                       dwc_ep->desc_cnt * 2);
48046 +       if (dwc_ep->desc_addr) {
48047 +               DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
48048 +               return;
48049 +       }
48050 +
48051 +       dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48052 +
48053 +       /** ISO OUT EP */
48054 +       if (dwc_ep->is_in == 0) {
48055 +               dev_dma_desc_sts_t sts = {.d32 = 0 };
48056 +               dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
48057 +               dma_addr_t dma_ad;
48058 +               uint32_t data_per_desc;
48059 +               dwc_otg_dev_out_ep_regs_t *out_regs =
48060 +                   core_if->dev_if->out_ep_regs[dwc_ep->num];
48061 +               int offset;
48062 +
48063 +               addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
48064 +               dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
48065 +
48066 +               /** Buffer 0 descriptors setup */
48067 +               dma_ad = dwc_ep->dma_addr0;
48068 +
48069 +               sts.b_iso_out.bs = BS_HOST_READY;
48070 +               sts.b_iso_out.rxsts = 0;
48071 +               sts.b_iso_out.l = 0;
48072 +               sts.b_iso_out.sp = 0;
48073 +               sts.b_iso_out.ioc = 0;
48074 +               sts.b_iso_out.pid = 0;
48075 +               sts.b_iso_out.framenum = 0;
48076 +
48077 +               offset = 0;
48078 +               for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48079 +                    i += dwc_ep->pkt_per_frm) {
48080 +
48081 +                       for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
48082 +                               uint32_t len = (j + 1) * dwc_ep->maxpacket;
48083 +                               if (len > dwc_ep->data_per_frame)
48084 +                                       data_per_desc =
48085 +                                           dwc_ep->data_per_frame -
48086 +                                           j * dwc_ep->maxpacket;
48087 +                               else
48088 +                                       data_per_desc = dwc_ep->maxpacket;
48089 +                               len = data_per_desc % 4;
48090 +                               if (len)
48091 +                                       data_per_desc += 4 - len;
48092 +
48093 +                               sts.b_iso_out.rxbytes = data_per_desc;
48094 +                               dma_desc->buf = dma_ad;
48095 +                               dma_desc->status.d32 = sts.d32;
48096 +
48097 +                               offset += data_per_desc;
48098 +                               dma_desc++;
48099 +                               dma_ad += data_per_desc;
48100 +                       }
48101 +               }
48102 +
48103 +               for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
48104 +                       uint32_t len = (j + 1) * dwc_ep->maxpacket;
48105 +                       if (len > dwc_ep->data_per_frame)
48106 +                               data_per_desc =
48107 +                                   dwc_ep->data_per_frame -
48108 +                                   j * dwc_ep->maxpacket;
48109 +                       else
48110 +                               data_per_desc = dwc_ep->maxpacket;
48111 +                       len = data_per_desc % 4;
48112 +                       if (len)
48113 +                               data_per_desc += 4 - len;
48114 +                       sts.b_iso_out.rxbytes = data_per_desc;
48115 +                       dma_desc->buf = dma_ad;
48116 +                       dma_desc->status.d32 = sts.d32;
48117 +
48118 +                       offset += data_per_desc;
48119 +                       dma_desc++;
48120 +                       dma_ad += data_per_desc;
48121 +               }
48122 +
48123 +               sts.b_iso_out.ioc = 1;
48124 +               len = (j + 1) * dwc_ep->maxpacket;
48125 +               if (len > dwc_ep->data_per_frame)
48126 +                       data_per_desc =
48127 +                           dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
48128 +               else
48129 +                       data_per_desc = dwc_ep->maxpacket;
48130 +               len = data_per_desc % 4;
48131 +               if (len)
48132 +                       data_per_desc += 4 - len;
48133 +               sts.b_iso_out.rxbytes = data_per_desc;
48134 +
48135 +               dma_desc->buf = dma_ad;
48136 +               dma_desc->status.d32 = sts.d32;
48137 +               dma_desc++;
48138 +
48139 +               /** Buffer 1 descriptors setup */
48140 +               sts.b_iso_out.ioc = 0;
48141 +               dma_ad = dwc_ep->dma_addr1;
48142 +
48143 +               offset = 0;
48144 +               for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48145 +                    i += dwc_ep->pkt_per_frm) {
48146 +                       for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
48147 +                               uint32_t len = (j + 1) * dwc_ep->maxpacket;
48148 +                               if (len > dwc_ep->data_per_frame)
48149 +                                       data_per_desc =
48150 +                                           dwc_ep->data_per_frame -
48151 +                                           j * dwc_ep->maxpacket;
48152 +                               else
48153 +                                       data_per_desc = dwc_ep->maxpacket;
48154 +                               len = data_per_desc % 4;
48155 +                               if (len)
48156 +                                       data_per_desc += 4 - len;
48157 +
48158 +                               data_per_desc =
48159 +                                   sts.b_iso_out.rxbytes = data_per_desc;
48160 +                               dma_desc->buf = dma_ad;
48161 +                               dma_desc->status.d32 = sts.d32;
48162 +
48163 +                               offset += data_per_desc;
48164 +                               dma_desc++;
48165 +                               dma_ad += data_per_desc;
48166 +                       }
48167 +               }
48168 +               for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
48169 +                       data_per_desc =
48170 +                           ((j + 1) * dwc_ep->maxpacket >
48171 +                            dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
48172 +                           j * dwc_ep->maxpacket : dwc_ep->maxpacket;
48173 +                       data_per_desc +=
48174 +                           (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
48175 +                       sts.b_iso_out.rxbytes = data_per_desc;
48176 +                       dma_desc->buf = dma_ad;
48177 +                       dma_desc->status.d32 = sts.d32;
48178 +
48179 +                       offset += data_per_desc;
48180 +                       dma_desc++;
48181 +                       dma_ad += data_per_desc;
48182 +               }
48183 +
48184 +               sts.b_iso_out.ioc = 1;
48185 +               sts.b_iso_out.l = 1;
48186 +               data_per_desc =
48187 +                   ((j + 1) * dwc_ep->maxpacket >
48188 +                    dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
48189 +                   j * dwc_ep->maxpacket : dwc_ep->maxpacket;
48190 +               data_per_desc +=
48191 +                   (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
48192 +               sts.b_iso_out.rxbytes = data_per_desc;
48193 +
48194 +               dma_desc->buf = dma_ad;
48195 +               dma_desc->status.d32 = sts.d32;
48196 +
48197 +               dwc_ep->next_frame = 0;
48198 +
48199 +               /** Write dma_ad into DOEPDMA register */
48200 +               DWC_WRITE_REG32(&(out_regs->doepdma),
48201 +                               (uint32_t) dwc_ep->iso_dma_desc_addr);
48202 +
48203 +       }
48204 +       /** ISO IN EP */
48205 +       else {
48206 +               dev_dma_desc_sts_t sts = {.d32 = 0 };
48207 +               dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
48208 +               dma_addr_t dma_ad;
48209 +               dwc_otg_dev_in_ep_regs_t *in_regs =
48210 +                   core_if->dev_if->in_ep_regs[dwc_ep->num];
48211 +               unsigned int frmnumber;
48212 +               fifosize_data_t txfifosize, rxfifosize;
48213 +
48214 +               txfifosize.d32 =
48215 +                   DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
48216 +                                  dtxfsts);
48217 +               rxfifosize.d32 =
48218 +                   DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
48219 +
48220 +               addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
48221 +
48222 +               dma_ad = dwc_ep->dma_addr0;
48223 +
48224 +               dsts.d32 =
48225 +                   DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48226 +
48227 +               sts.b_iso_in.bs = BS_HOST_READY;
48228 +               sts.b_iso_in.txsts = 0;
48229 +               sts.b_iso_in.sp =
48230 +                   (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
48231 +               sts.b_iso_in.ioc = 0;
48232 +               sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
48233 +
48234 +               frmnumber = dwc_ep->next_frame;
48235 +
48236 +               sts.b_iso_in.framenum = frmnumber;
48237 +               sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
48238 +               sts.b_iso_in.l = 0;
48239 +
48240 +               /** Buffer 0 descriptors setup */
48241 +               for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
48242 +                       dma_desc->buf = dma_ad;
48243 +                       dma_desc->status.d32 = sts.d32;
48244 +                       dma_desc++;
48245 +
48246 +                       dma_ad += dwc_ep->data_per_frame;
48247 +                       sts.b_iso_in.framenum += dwc_ep->bInterval;
48248 +               }
48249 +
48250 +               sts.b_iso_in.ioc = 1;
48251 +               dma_desc->buf = dma_ad;
48252 +               dma_desc->status.d32 = sts.d32;
48253 +               ++dma_desc;
48254 +
48255 +               /** Buffer 1 descriptors setup */
48256 +               sts.b_iso_in.ioc = 0;
48257 +               dma_ad = dwc_ep->dma_addr1;
48258 +
48259 +               for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
48260 +                    i += dwc_ep->pkt_per_frm) {
48261 +                       dma_desc->buf = dma_ad;
48262 +                       dma_desc->status.d32 = sts.d32;
48263 +                       dma_desc++;
48264 +
48265 +                       dma_ad += dwc_ep->data_per_frame;
48266 +                       sts.b_iso_in.framenum += dwc_ep->bInterval;
48267 +
48268 +                       sts.b_iso_in.ioc = 0;
48269 +               }
48270 +               sts.b_iso_in.ioc = 1;
48271 +               sts.b_iso_in.l = 1;
48272 +
48273 +               dma_desc->buf = dma_ad;
48274 +               dma_desc->status.d32 = sts.d32;
48275 +
48276 +               dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
48277 +
48278 +               /** Write dma_ad into diepdma register */
48279 +               DWC_WRITE_REG32(&(in_regs->diepdma),
48280 +                               (uint32_t) dwc_ep->iso_dma_desc_addr);
48281 +       }
48282 +       /** Enable endpoint, clear nak  */
48283 +       depctl.d32 = 0;
48284 +       depctl.b.epena = 1;
48285 +       depctl.b.usbactep = 1;
48286 +       depctl.b.cnak = 1;
48287 +
48288 +       DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
48289 +       depctl.d32 = DWC_READ_REG32(addr);
48290 +}
48291 +
48292 +/**
48293 + * This function initializes a descriptor chain for Isochronous transfer
48294 + *
48295 + * @param core_if Programming view of DWC_otg controller.
48296 + * @param ep The EP to start the transfer on.
48297 + *
48298 + */
48299 +void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
48300 +                                      dwc_ep_t * ep)
48301 +{
48302 +       depctl_data_t depctl = {.d32 = 0 };
48303 +       volatile uint32_t *addr;
48304 +
48305 +       if (ep->is_in) {
48306 +               addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
48307 +       } else {
48308 +               addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
48309 +       }
48310 +
48311 +       if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
48312 +               return;
48313 +       } else {
48314 +               deptsiz_data_t deptsiz = {.d32 = 0 };
48315 +
48316 +               ep->xfer_len =
48317 +                   ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
48318 +               ep->pkt_cnt =
48319 +                   (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
48320 +               ep->xfer_count = 0;
48321 +               ep->xfer_buff =
48322 +                   (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
48323 +               ep->dma_addr =
48324 +                   (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
48325 +
48326 +               if (ep->is_in) {
48327 +                       /* Program the transfer size and packet count
48328 +                        *      as follows: xfersize = N * maxpacket +
48329 +                        *      short_packet pktcnt = N + (short_packet
48330 +                        *      exist ? 1 : 0)
48331 +                        */
48332 +                       deptsiz.b.mc = ep->pkt_per_frm;
48333 +                       deptsiz.b.xfersize = ep->xfer_len;
48334 +                       deptsiz.b.pktcnt =
48335 +                           (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
48336 +                       DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
48337 +                                       dieptsiz, deptsiz.d32);
48338 +
48339 +                       /* Write the DMA register */
48340 +                       DWC_WRITE_REG32(&
48341 +                                       (core_if->dev_if->in_ep_regs[ep->num]->
48342 +                                        diepdma), (uint32_t) ep->dma_addr);
48343 +
48344 +               } else {
48345 +                       deptsiz.b.pktcnt =
48346 +                           (ep->xfer_len + (ep->maxpacket - 1)) /
48347 +                           ep->maxpacket;
48348 +                       deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
48349 +
48350 +                       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
48351 +                                       doeptsiz, deptsiz.d32);
48352 +
48353 +                       /* Write the DMA register */
48354 +                       DWC_WRITE_REG32(&
48355 +                                       (core_if->dev_if->out_ep_regs[ep->num]->
48356 +                                        doepdma), (uint32_t) ep->dma_addr);
48357 +
48358 +               }
48359 +               /** Enable endpoint, clear nak  */
48360 +               depctl.d32 = 0;
48361 +               depctl.b.epena = 1;
48362 +               depctl.b.cnak = 1;
48363 +
48364 +               DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
48365 +       }
48366 +}
48367 +
48368 +/**
48369 + * This function does the setup for a data transfer for an EP and
48370 + * starts the transfer. For an IN transfer, the packets will be
48371 + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
48372 + * the packets are unloaded from the Rx FIFO in the ISR.
48373 + *
48374 + * @param core_if Programming view of DWC_otg controller.
48375 + * @param ep The EP to start the transfer on.
48376 + */
48377 +
48378 +static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
48379 +                                         dwc_ep_t * ep)
48380 +{
48381 +       if (core_if->dma_enable) {
48382 +               if (core_if->dma_desc_enable) {
48383 +                       if (ep->is_in) {
48384 +                               ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
48385 +                       } else {
48386 +                               ep->desc_cnt = ep->pkt_cnt;
48387 +                       }
48388 +                       dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
48389 +               } else {
48390 +                       if (core_if->pti_enh_enable) {
48391 +                               dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
48392 +                       } else {
48393 +                               ep->cur_pkt_addr =
48394 +                                   (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
48395 +                                   xfer_buff0;
48396 +                               ep->cur_pkt_dma_addr =
48397 +                                   (ep->proc_buf_num) ? ep->dma_addr1 : ep->
48398 +                                   dma_addr0;
48399 +                               dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
48400 +                       }
48401 +               }
48402 +       } else {
48403 +               ep->cur_pkt_addr =
48404 +                   (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
48405 +               ep->cur_pkt_dma_addr =
48406 +                   (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
48407 +               dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
48408 +       }
48409 +}
48410 +
48411 +/**
48412 + * This function stops transfer for an EP and
48413 + * resets the ep's variables.
48414 + *
48415 + * @param core_if Programming view of DWC_otg controller.
48416 + * @param ep The EP to start the transfer on.
48417 + */
48418 +
48419 +void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
48420 +{
48421 +       depctl_data_t depctl = {.d32 = 0 };
48422 +       volatile uint32_t *addr;
48423 +
48424 +       if (ep->is_in == 1) {
48425 +               addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
48426 +       } else {
48427 +               addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
48428 +       }
48429 +
48430 +       /* disable the ep */
48431 +       depctl.d32 = DWC_READ_REG32(addr);
48432 +
48433 +       depctl.b.epdis = 1;
48434 +       depctl.b.snak = 1;
48435 +
48436 +       DWC_WRITE_REG32(addr, depctl.d32);
48437 +
48438 +       if (core_if->dma_desc_enable &&
48439 +           ep->iso_desc_addr && ep->iso_dma_desc_addr) {
48440 +               dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
48441 +                                          ep->iso_dma_desc_addr,
48442 +                                          ep->desc_cnt * 2);
48443 +       }
48444 +
48445 +       /* reset varibales */
48446 +       ep->dma_addr0 = 0;
48447 +       ep->dma_addr1 = 0;
48448 +       ep->xfer_buff0 = 0;
48449 +       ep->xfer_buff1 = 0;
48450 +       ep->data_per_frame = 0;
48451 +       ep->data_pattern_frame = 0;
48452 +       ep->sync_frame = 0;
48453 +       ep->buf_proc_intrvl = 0;
48454 +       ep->bInterval = 0;
48455 +       ep->proc_buf_num = 0;
48456 +       ep->pkt_per_frm = 0;
48457 +       ep->pkt_per_frm = 0;
48458 +       ep->desc_cnt = 0;
48459 +       ep->iso_desc_addr = 0;
48460 +       ep->iso_dma_desc_addr = 0;
48461 +}
48462 +
48463 +int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
48464 +                            uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
48465 +                            dwc_dma_t dma1, int sync_frame, int dp_frame,
48466 +                            int data_per_frame, int start_frame,
48467 +                            int buf_proc_intrvl, void *req_handle,
48468 +                            int atomic_alloc)
48469 +{
48470 +       dwc_otg_pcd_ep_t *ep;
48471 +       dwc_irqflags_t flags = 0;
48472 +       dwc_ep_t *dwc_ep;
48473 +       int32_t frm_data;
48474 +       dsts_data_t dsts;
48475 +       dwc_otg_core_if_t *core_if;
48476 +
48477 +       ep = get_ep_from_handle(pcd, ep_handle);
48478 +
48479 +       if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
48480 +               DWC_WARN("bad ep\n");
48481 +               return -DWC_E_INVALID;
48482 +       }
48483 +
48484 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
48485 +       core_if = GET_CORE_IF(pcd);
48486 +       dwc_ep = &ep->dwc_ep;
48487 +
48488 +       if (ep->iso_req_handle) {
48489 +               DWC_WARN("ISO request in progress\n");
48490 +       }
48491 +
48492 +       dwc_ep->dma_addr0 = dma0;
48493 +       dwc_ep->dma_addr1 = dma1;
48494 +
48495 +       dwc_ep->xfer_buff0 = buf0;
48496 +       dwc_ep->xfer_buff1 = buf1;
48497 +
48498 +       dwc_ep->data_per_frame = data_per_frame;
48499 +
48500 +       /** @todo - pattern data support is to be implemented in the future */
48501 +       dwc_ep->data_pattern_frame = dp_frame;
48502 +       dwc_ep->sync_frame = sync_frame;
48503 +
48504 +       dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
48505 +
48506 +       dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
48507 +
48508 +       dwc_ep->proc_buf_num = 0;
48509 +
48510 +       dwc_ep->pkt_per_frm = 0;
48511 +       frm_data = ep->dwc_ep.data_per_frame;
48512 +       while (frm_data > 0) {
48513 +               dwc_ep->pkt_per_frm++;
48514 +               frm_data -= ep->dwc_ep.maxpacket;
48515 +       }
48516 +
48517 +       dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
48518 +
48519 +       if (start_frame == -1) {
48520 +               dwc_ep->next_frame = dsts.b.soffn + 1;
48521 +               if (dwc_ep->bInterval != 1) {
48522 +                       dwc_ep->next_frame =
48523 +                           dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
48524 +                                                 dwc_ep->next_frame %
48525 +                                                 dwc_ep->bInterval);
48526 +               }
48527 +       } else {
48528 +               dwc_ep->next_frame = start_frame;
48529 +       }
48530 +
48531 +       if (!core_if->pti_enh_enable) {
48532 +               dwc_ep->pkt_cnt =
48533 +                   dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
48534 +                   dwc_ep->bInterval;
48535 +       } else {
48536 +               dwc_ep->pkt_cnt =
48537 +                   (dwc_ep->data_per_frame *
48538 +                    (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
48539 +                    - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
48540 +       }
48541 +
48542 +       if (core_if->dma_desc_enable) {
48543 +               dwc_ep->desc_cnt =
48544 +                   dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
48545 +                   dwc_ep->bInterval;
48546 +       }
48547 +
48548 +       if (atomic_alloc) {
48549 +               dwc_ep->pkt_info =
48550 +                   DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
48551 +       } else {
48552 +               dwc_ep->pkt_info =
48553 +                   DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
48554 +       }
48555 +       if (!dwc_ep->pkt_info) {
48556 +               DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
48557 +               return -DWC_E_NO_MEMORY;
48558 +       }
48559 +       if (core_if->pti_enh_enable) {
48560 +               dwc_memset(dwc_ep->pkt_info, 0,
48561 +                          sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
48562 +       }
48563 +
48564 +       dwc_ep->cur_pkt = 0;
48565 +       ep->iso_req_handle = req_handle;
48566 +
48567 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
48568 +       dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
48569 +       return 0;
48570 +}
48571 +
48572 +int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
48573 +                           void *req_handle)
48574 +{
48575 +       dwc_irqflags_t flags = 0;
48576 +       dwc_otg_pcd_ep_t *ep;
48577 +       dwc_ep_t *dwc_ep;
48578 +
48579 +       ep = get_ep_from_handle(pcd, ep_handle);
48580 +       if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
48581 +               DWC_WARN("bad ep\n");
48582 +               return -DWC_E_INVALID;
48583 +       }
48584 +       dwc_ep = &ep->dwc_ep;
48585 +
48586 +       dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
48587 +
48588 +       DWC_FREE(dwc_ep->pkt_info);
48589 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
48590 +       if (ep->iso_req_handle != req_handle) {
48591 +               DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
48592 +               return -DWC_E_INVALID;
48593 +       }
48594 +
48595 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
48596 +
48597 +       ep->iso_req_handle = 0;
48598 +       return 0;
48599 +}
48600 +
48601 +/**
48602 + * This function is used for perodical data exchnage between PCD and gadget drivers.
48603 + * for Isochronous EPs
48604 + *
48605 + *     - Every time a sync period completes this function is called to
48606 + *       perform data exchange between PCD and gadget
48607 + */
48608 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
48609 +                            void *req_handle)
48610 +{
48611 +       int i;
48612 +       dwc_ep_t *dwc_ep;
48613 +
48614 +       dwc_ep = &ep->dwc_ep;
48615 +
48616 +       DWC_SPINUNLOCK(ep->pcd->lock);
48617 +       pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
48618 +                                dwc_ep->proc_buf_num ^ 0x1);
48619 +       DWC_SPINLOCK(ep->pcd->lock);
48620 +
48621 +       for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
48622 +               dwc_ep->pkt_info[i].status = 0;
48623 +               dwc_ep->pkt_info[i].offset = 0;
48624 +               dwc_ep->pkt_info[i].length = 0;
48625 +       }
48626 +}
48627 +
48628 +int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
48629 +                                    void *iso_req_handle)
48630 +{
48631 +       dwc_otg_pcd_ep_t *ep;
48632 +       dwc_ep_t *dwc_ep;
48633 +
48634 +       ep = get_ep_from_handle(pcd, ep_handle);
48635 +       if (!ep->desc || ep->dwc_ep.num == 0) {
48636 +               DWC_WARN("bad ep\n");
48637 +               return -DWC_E_INVALID;
48638 +       }
48639 +       dwc_ep = &ep->dwc_ep;
48640 +
48641 +       return dwc_ep->pkt_cnt;
48642 +}
48643 +
48644 +void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
48645 +                                      void *iso_req_handle, int packet,
48646 +                                      int *status, int *actual, int *offset)
48647 +{
48648 +       dwc_otg_pcd_ep_t *ep;
48649 +       dwc_ep_t *dwc_ep;
48650 +
48651 +       ep = get_ep_from_handle(pcd, ep_handle);
48652 +       if (!ep)
48653 +               DWC_WARN("bad ep\n");
48654 +
48655 +       dwc_ep = &ep->dwc_ep;
48656 +
48657 +       *status = dwc_ep->pkt_info[packet].status;
48658 +       *actual = dwc_ep->pkt_info[packet].length;
48659 +       *offset = dwc_ep->pkt_info[packet].offset;
48660 +}
48661 +
48662 +#endif /* DWC_EN_ISOC */
48663 +
48664 +static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
48665 +                               uint32_t is_in, uint32_t ep_num)
48666 +{
48667 +       /* Init EP structure */
48668 +       pcd_ep->desc = 0;
48669 +       pcd_ep->pcd = pcd;
48670 +       pcd_ep->stopped = 1;
48671 +       pcd_ep->queue_sof = 0;
48672 +
48673 +       /* Init DWC ep structure */
48674 +       pcd_ep->dwc_ep.is_in = is_in;
48675 +       pcd_ep->dwc_ep.num = ep_num;
48676 +       pcd_ep->dwc_ep.active = 0;
48677 +       pcd_ep->dwc_ep.tx_fifo_num = 0;
48678 +       /* Control until ep is actvated */
48679 +       pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
48680 +       pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
48681 +       pcd_ep->dwc_ep.dma_addr = 0;
48682 +       pcd_ep->dwc_ep.start_xfer_buff = 0;
48683 +       pcd_ep->dwc_ep.xfer_buff = 0;
48684 +       pcd_ep->dwc_ep.xfer_len = 0;
48685 +       pcd_ep->dwc_ep.xfer_count = 0;
48686 +       pcd_ep->dwc_ep.sent_zlp = 0;
48687 +       pcd_ep->dwc_ep.total_len = 0;
48688 +       pcd_ep->dwc_ep.desc_addr = 0;
48689 +       pcd_ep->dwc_ep.dma_desc_addr = 0;
48690 +       DWC_CIRCLEQ_INIT(&pcd_ep->queue);
48691 +}
48692 +
48693 +/**
48694 + * Initialize ep's
48695 + */
48696 +static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
48697 +{
48698 +       int i;
48699 +       uint32_t hwcfg1;
48700 +       dwc_otg_pcd_ep_t *ep;
48701 +       int in_ep_cntr, out_ep_cntr;
48702 +       uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
48703 +       uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
48704 +
48705 +       /**
48706 +        * Initialize the EP0 structure.
48707 +        */
48708 +       ep = &pcd->ep0;
48709 +       dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
48710 +
48711 +       in_ep_cntr = 0;
48712 +       hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
48713 +       for (i = 1; in_ep_cntr < num_in_eps; i++) {
48714 +               if ((hwcfg1 & 0x1) == 0) {
48715 +                       dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
48716 +                       in_ep_cntr++;
48717 +                       /**
48718 +                        * @todo NGS: Add direction to EP, based on contents
48719 +                        * of HWCFG1.  Need a copy of HWCFG1 in pcd structure?
48720 +                        * sprintf(";r
48721 +                        */
48722 +                       dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
48723 +
48724 +                       DWC_CIRCLEQ_INIT(&ep->queue);
48725 +               }
48726 +               hwcfg1 >>= 2;
48727 +       }
48728 +
48729 +       out_ep_cntr = 0;
48730 +       hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
48731 +       for (i = 1; out_ep_cntr < num_out_eps; i++) {
48732 +               if ((hwcfg1 & 0x1) == 0) {
48733 +                       dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
48734 +                       out_ep_cntr++;
48735 +                       /**
48736 +                        * @todo NGS: Add direction to EP, based on contents
48737 +                        * of HWCFG1.  Need a copy of HWCFG1 in pcd structure?
48738 +                        * sprintf(";r
48739 +                        */
48740 +                       dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
48741 +                       DWC_CIRCLEQ_INIT(&ep->queue);
48742 +               }
48743 +               hwcfg1 >>= 2;
48744 +       }
48745 +
48746 +       pcd->ep0state = EP0_DISCONNECT;
48747 +       pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
48748 +       pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
48749 +}
48750 +
48751 +/**
48752 + * This function is called when the SRP timer expires. The SRP should
48753 + * complete within 6 seconds.
48754 + */
48755 +static void srp_timeout(void *ptr)
48756 +{
48757 +       gotgctl_data_t gotgctl;
48758 +       dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
48759 +       volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
48760 +
48761 +       gotgctl.d32 = DWC_READ_REG32(addr);
48762 +
48763 +       core_if->srp_timer_started = 0;
48764 +
48765 +       if (core_if->adp_enable) {
48766 +               if (gotgctl.b.bsesvld == 0) {
48767 +                       gpwrdn_data_t gpwrdn = {.d32 = 0 };
48768 +                       DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
48769 +                       /* Power off the core */
48770 +                       if (core_if->power_down == 2) {
48771 +                               gpwrdn.b.pwrdnswtch = 1;
48772 +                               DWC_MODIFY_REG32(&core_if->
48773 +                                                core_global_regs->gpwrdn,
48774 +                                                gpwrdn.d32, 0);
48775 +                       }
48776 +
48777 +                       gpwrdn.d32 = 0;
48778 +                       gpwrdn.b.pmuintsel = 1;
48779 +                       gpwrdn.b.pmuactv = 1;
48780 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
48781 +                                        gpwrdn.d32);
48782 +                       dwc_otg_adp_probe_start(core_if);
48783 +               } else {
48784 +                       DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
48785 +                       core_if->op_state = B_PERIPHERAL;
48786 +                       dwc_otg_core_init(core_if);
48787 +                       dwc_otg_enable_global_interrupts(core_if);
48788 +                       cil_pcd_start(core_if);
48789 +               }
48790 +       }
48791 +
48792 +       if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
48793 +           (core_if->core_params->i2c_enable)) {
48794 +               DWC_PRINTF("SRP Timeout\n");
48795 +
48796 +               if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
48797 +                       if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
48798 +                               core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
48799 +                       }
48800 +
48801 +                       /* Clear Session Request */
48802 +                       gotgctl.d32 = 0;
48803 +                       gotgctl.b.sesreq = 1;
48804 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
48805 +                                        gotgctl.d32, 0);
48806 +
48807 +                       core_if->srp_success = 0;
48808 +               } else {
48809 +                       __DWC_ERROR("Device not connected/responding\n");
48810 +                       gotgctl.b.sesreq = 0;
48811 +                       DWC_WRITE_REG32(addr, gotgctl.d32);
48812 +               }
48813 +       } else if (gotgctl.b.sesreq) {
48814 +               DWC_PRINTF("SRP Timeout\n");
48815 +
48816 +               __DWC_ERROR("Device not connected/responding\n");
48817 +               gotgctl.b.sesreq = 0;
48818 +               DWC_WRITE_REG32(addr, gotgctl.d32);
48819 +       } else {
48820 +               DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
48821 +       }
48822 +}
48823 +
48824 +/**
48825 + * Tasklet
48826 + *
48827 + */
48828 +extern void start_next_request(dwc_otg_pcd_ep_t * ep);
48829 +
48830 +static void start_xfer_tasklet_func(void *data)
48831 +{
48832 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
48833 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
48834 +
48835 +       int i;
48836 +       depctl_data_t diepctl;
48837 +
48838 +       DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
48839 +
48840 +       diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
48841 +
48842 +       if (pcd->ep0.queue_sof) {
48843 +               pcd->ep0.queue_sof = 0;
48844 +               start_next_request(&pcd->ep0);
48845 +               // break;
48846 +       }
48847 +
48848 +       for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
48849 +               depctl_data_t diepctl;
48850 +               diepctl.d32 =
48851 +                   DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
48852 +
48853 +               if (pcd->in_ep[i].queue_sof) {
48854 +                       pcd->in_ep[i].queue_sof = 0;
48855 +                       start_next_request(&pcd->in_ep[i]);
48856 +                       // break;
48857 +               }
48858 +       }
48859 +
48860 +       return;
48861 +}
48862 +
48863 +/**
48864 + * This function initialized the PCD portion of the driver.
48865 + *
48866 + */
48867 +dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
48868 +{
48869 +       dwc_otg_pcd_t *pcd = NULL;
48870 +       dwc_otg_dev_if_t *dev_if;
48871 +       int i;
48872 +
48873 +       /*
48874 +        * Allocate PCD structure
48875 +        */
48876 +       pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
48877 +
48878 +       if (pcd == NULL) {
48879 +               return NULL;
48880 +       }
48881 +
48882 +#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK))
48883 +       DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock);
48884 +#else
48885 +       pcd->lock = DWC_SPINLOCK_ALLOC();
48886 +#endif
48887 +        DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n",
48888 +                    pcd, core_if);//GRAYG
48889 +       if (!pcd->lock) {
48890 +               DWC_ERROR("Could not allocate lock for pcd");
48891 +               DWC_FREE(pcd);
48892 +               return NULL;
48893 +       }
48894 +       /* Set core_if's lock pointer to hcd->lock */
48895 +       core_if->lock = pcd->lock;
48896 +       pcd->core_if = core_if;
48897 +
48898 +       dev_if = core_if->dev_if;
48899 +       dev_if->isoc_ep = NULL;
48900 +
48901 +       if (core_if->hwcfg4.b.ded_fifo_en) {
48902 +               DWC_PRINTF("Dedicated Tx FIFOs mode\n");
48903 +       } else {
48904 +               DWC_PRINTF("Shared Tx FIFO mode\n");
48905 +       }
48906 +
48907 +       /*
48908 +        * Initialized the Core for Device mode here if there is nod ADP support.
48909 +        * Otherwise it will be done later in dwc_otg_adp_start routine.
48910 +        */
48911 +       if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
48912 +               dwc_otg_core_dev_init(core_if);
48913 +       }
48914 +
48915 +       /*
48916 +        * Register the PCD Callbacks.
48917 +        */
48918 +       dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
48919 +
48920 +       /*
48921 +        * Initialize the DMA buffer for SETUP packets
48922 +        */
48923 +       if (GET_CORE_IF(pcd)->dma_enable) {
48924 +               pcd->setup_pkt =
48925 +                   DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5,
48926 +                                 &pcd->setup_pkt_dma_handle);
48927 +               if (pcd->setup_pkt == NULL) {
48928 +                       DWC_FREE(pcd);
48929 +                       return NULL;
48930 +               }
48931 +
48932 +               pcd->status_buf =
48933 +                   DWC_DMA_ALLOC(sizeof(uint16_t),
48934 +                                 &pcd->status_buf_dma_handle);
48935 +               if (pcd->status_buf == NULL) {
48936 +                       DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
48937 +                                    pcd->setup_pkt, pcd->setup_pkt_dma_handle);
48938 +                       DWC_FREE(pcd);
48939 +                       return NULL;
48940 +               }
48941 +
48942 +               if (GET_CORE_IF(pcd)->dma_desc_enable) {
48943 +                       dev_if->setup_desc_addr[0] =
48944 +                           dwc_otg_ep_alloc_desc_chain
48945 +                           (&dev_if->dma_setup_desc_addr[0], 1);
48946 +                       dev_if->setup_desc_addr[1] =
48947 +                           dwc_otg_ep_alloc_desc_chain
48948 +                           (&dev_if->dma_setup_desc_addr[1], 1);
48949 +                       dev_if->in_desc_addr =
48950 +                           dwc_otg_ep_alloc_desc_chain
48951 +                           (&dev_if->dma_in_desc_addr, 1);
48952 +                       dev_if->out_desc_addr =
48953 +                           dwc_otg_ep_alloc_desc_chain
48954 +                           (&dev_if->dma_out_desc_addr, 1);
48955 +                       pcd->data_terminated = 0;
48956 +
48957 +                       if (dev_if->setup_desc_addr[0] == 0
48958 +                           || dev_if->setup_desc_addr[1] == 0
48959 +                           || dev_if->in_desc_addr == 0
48960 +                           || dev_if->out_desc_addr == 0) {
48961 +
48962 +                               if (dev_if->out_desc_addr)
48963 +                                       dwc_otg_ep_free_desc_chain
48964 +                                           (dev_if->out_desc_addr,
48965 +                                            dev_if->dma_out_desc_addr, 1);
48966 +                               if (dev_if->in_desc_addr)
48967 +                                       dwc_otg_ep_free_desc_chain
48968 +                                           (dev_if->in_desc_addr,
48969 +                                            dev_if->dma_in_desc_addr, 1);
48970 +                               if (dev_if->setup_desc_addr[1])
48971 +                                       dwc_otg_ep_free_desc_chain
48972 +                                           (dev_if->setup_desc_addr[1],
48973 +                                            dev_if->dma_setup_desc_addr[1], 1);
48974 +                               if (dev_if->setup_desc_addr[0])
48975 +                                       dwc_otg_ep_free_desc_chain
48976 +                                           (dev_if->setup_desc_addr[0],
48977 +                                            dev_if->dma_setup_desc_addr[0], 1);
48978 +
48979 +                               DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
48980 +                                            pcd->setup_pkt,
48981 +                                            pcd->setup_pkt_dma_handle);
48982 +                               DWC_DMA_FREE(sizeof(*pcd->status_buf),
48983 +                                            pcd->status_buf,
48984 +                                            pcd->status_buf_dma_handle);
48985 +
48986 +                               DWC_FREE(pcd);
48987 +
48988 +                               return NULL;
48989 +                       }
48990 +               }
48991 +       } else {
48992 +               pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
48993 +               if (pcd->setup_pkt == NULL) {
48994 +                       DWC_FREE(pcd);
48995 +                       return NULL;
48996 +               }
48997 +
48998 +               pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
48999 +               if (pcd->status_buf == NULL) {
49000 +                       DWC_FREE(pcd->setup_pkt);
49001 +                       DWC_FREE(pcd);
49002 +                       return NULL;
49003 +               }
49004 +       }
49005 +
49006 +       dwc_otg_pcd_reinit(pcd);
49007 +
49008 +       /* Allocate the cfi object for the PCD */
49009 +#ifdef DWC_UTE_CFI
49010 +       pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
49011 +       if (NULL == pcd->cfi)
49012 +               goto fail;
49013 +       if (init_cfi(pcd->cfi)) {
49014 +               CFI_INFO("%s: Failed to init the CFI object\n", __func__);
49015 +               goto fail;
49016 +       }
49017 +#endif
49018 +
49019 +       /* Initialize tasklets */
49020 +       pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
49021 +                                                start_xfer_tasklet_func, pcd);
49022 +       pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
49023 +                                               do_test_mode, pcd);
49024 +
49025 +       /* Initialize SRP timer */
49026 +       core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
49027 +
49028 +       if (core_if->core_params->dev_out_nak) {
49029 +               /**
49030 +               * Initialize xfer timeout timer. Implemented for
49031 +               * 2.93a feature "Device DDMA OUT NAK Enhancement"
49032 +               */
49033 +               for(i = 0; i < MAX_EPS_CHANNELS; i++) {
49034 +                       pcd->core_if->ep_xfer_timer[i] =
49035 +                               DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
49036 +                               &pcd->core_if->ep_xfer_info[i]);
49037 +               }
49038 +       }
49039 +
49040 +       return pcd;
49041 +#ifdef DWC_UTE_CFI
49042 +fail:
49043 +#endif
49044 +       if (pcd->setup_pkt)
49045 +               DWC_FREE(pcd->setup_pkt);
49046 +       if (pcd->status_buf)
49047 +               DWC_FREE(pcd->status_buf);
49048 +#ifdef DWC_UTE_CFI
49049 +       if (pcd->cfi)
49050 +               DWC_FREE(pcd->cfi);
49051 +#endif
49052 +       if (pcd)
49053 +               DWC_FREE(pcd);
49054 +       return NULL;
49055 +
49056 +}
49057 +
49058 +/**
49059 + * Remove PCD specific data
49060 + */
49061 +void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
49062 +{
49063 +       dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
49064 +       int i;
49065 +       if (pcd->core_if->core_params->dev_out_nak) {
49066 +               for (i = 0; i < MAX_EPS_CHANNELS; i++) {
49067 +                       DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
49068 +                       pcd->core_if->ep_xfer_info[i].state = 0;
49069 +               }
49070 +       }
49071 +
49072 +       if (GET_CORE_IF(pcd)->dma_enable) {
49073 +               DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
49074 +                            pcd->setup_pkt_dma_handle);
49075 +               DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf,
49076 +                            pcd->status_buf_dma_handle);
49077 +               if (GET_CORE_IF(pcd)->dma_desc_enable) {
49078 +                       dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
49079 +                                                  dev_if->dma_setup_desc_addr
49080 +                                                  [0], 1);
49081 +                       dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
49082 +                                                  dev_if->dma_setup_desc_addr
49083 +                                                  [1], 1);
49084 +                       dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
49085 +                                                  dev_if->dma_in_desc_addr, 1);
49086 +                       dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
49087 +                                                  dev_if->dma_out_desc_addr,
49088 +                                                  1);
49089 +               }
49090 +       } else {
49091 +               DWC_FREE(pcd->setup_pkt);
49092 +               DWC_FREE(pcd->status_buf);
49093 +       }
49094 +       DWC_SPINLOCK_FREE(pcd->lock);
49095 +       /* Set core_if's lock pointer to NULL */
49096 +       pcd->core_if->lock = NULL;
49097 +
49098 +       DWC_TASK_FREE(pcd->start_xfer_tasklet);
49099 +       DWC_TASK_FREE(pcd->test_mode_tasklet);
49100 +       if (pcd->core_if->core_params->dev_out_nak) {
49101 +               for (i = 0; i < MAX_EPS_CHANNELS; i++) {
49102 +                       if (pcd->core_if->ep_xfer_timer[i]) {
49103 +                                       DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
49104 +                       }
49105 +               }
49106 +       }
49107 +
49108 +/* Release the CFI object's dynamic memory */
49109 +#ifdef DWC_UTE_CFI
49110 +       if (pcd->cfi->ops.release) {
49111 +               pcd->cfi->ops.release(pcd->cfi);
49112 +       }
49113 +#endif
49114 +
49115 +       DWC_FREE(pcd);
49116 +}
49117 +
49118 +/**
49119 + * Returns whether registered pcd is dual speed or not
49120 + */
49121 +uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
49122 +{
49123 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
49124 +
49125 +       if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
49126 +           ((core_if->hwcfg2.b.hs_phy_type == 2) &&
49127 +            (core_if->hwcfg2.b.fs_phy_type == 1) &&
49128 +            (core_if->core_params->ulpi_fs_ls))) {
49129 +               return 0;
49130 +       }
49131 +
49132 +       return 1;
49133 +}
49134 +
49135 +/**
49136 + * Returns whether registered pcd is OTG capable or not
49137 + */
49138 +uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
49139 +{
49140 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
49141 +       gusbcfg_data_t usbcfg = {.d32 = 0 };
49142 +
49143 +       usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
49144 +       if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
49145 +               return 0;
49146 +       }
49147 +
49148 +       return 1;
49149 +}
49150 +
49151 +/**
49152 + * This function assigns periodic Tx FIFO to an periodic EP
49153 + * in shared Tx FIFO mode
49154 + */
49155 +static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
49156 +{
49157 +       uint32_t TxMsk = 1;
49158 +       int i;
49159 +
49160 +       for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
49161 +               if ((TxMsk & core_if->tx_msk) == 0) {
49162 +                       core_if->tx_msk |= TxMsk;
49163 +                       return i + 1;
49164 +               }
49165 +               TxMsk <<= 1;
49166 +       }
49167 +       return 0;
49168 +}
49169 +
49170 +/**
49171 + * This function assigns periodic Tx FIFO to an periodic EP
49172 + * in shared Tx FIFO mode
49173 + */
49174 +static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
49175 +{
49176 +       uint32_t PerTxMsk = 1;
49177 +       int i;
49178 +       for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
49179 +               if ((PerTxMsk & core_if->p_tx_msk) == 0) {
49180 +                       core_if->p_tx_msk |= PerTxMsk;
49181 +                       return i + 1;
49182 +               }
49183 +               PerTxMsk <<= 1;
49184 +       }
49185 +       return 0;
49186 +}
49187 +
49188 +/**
49189 + * This function releases periodic Tx FIFO
49190 + * in shared Tx FIFO mode
49191 + */
49192 +static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
49193 +                                 uint32_t fifo_num)
49194 +{
49195 +       core_if->p_tx_msk =
49196 +           (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
49197 +}
49198 +
49199 +/**
49200 + * This function releases periodic Tx FIFO
49201 + * in shared Tx FIFO mode
49202 + */
49203 +static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
49204 +{
49205 +       core_if->tx_msk =
49206 +           (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
49207 +}
49208 +
49209 +/**
49210 + * This function is being called from gadget
49211 + * to enable PCD endpoint.
49212 + */
49213 +int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
49214 +                         const uint8_t * ep_desc, void *usb_ep)
49215 +{
49216 +       int num, dir;
49217 +       dwc_otg_pcd_ep_t *ep = NULL;
49218 +       const usb_endpoint_descriptor_t *desc;
49219 +       dwc_irqflags_t flags;
49220 +       fifosize_data_t dptxfsiz = {.d32 = 0 };
49221 +       gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
49222 +       gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
49223 +       int retval = 0;
49224 +       int i, epcount;
49225 +
49226 +       desc = (const usb_endpoint_descriptor_t *)ep_desc;
49227 +
49228 +       if (!desc) {
49229 +               pcd->ep0.priv = usb_ep;
49230 +               ep = &pcd->ep0;
49231 +               retval = -DWC_E_INVALID;
49232 +               goto out;
49233 +       }
49234 +
49235 +       num = UE_GET_ADDR(desc->bEndpointAddress);
49236 +       dir = UE_GET_DIR(desc->bEndpointAddress);
49237 +
49238 +       if (!desc->wMaxPacketSize) {
49239 +               DWC_WARN("bad maxpacketsize\n");
49240 +               retval = -DWC_E_INVALID;
49241 +               goto out;
49242 +       }
49243 +
49244 +       if (dir == UE_DIR_IN) {
49245 +               epcount = pcd->core_if->dev_if->num_in_eps;
49246 +               for (i = 0; i < epcount; i++) {
49247 +                       if (num == pcd->in_ep[i].dwc_ep.num) {
49248 +                               ep = &pcd->in_ep[i];
49249 +                               break;
49250 +                       }
49251 +               }
49252 +       } else {
49253 +               epcount = pcd->core_if->dev_if->num_out_eps;
49254 +               for (i = 0; i < epcount; i++) {
49255 +                       if (num == pcd->out_ep[i].dwc_ep.num) {
49256 +                               ep = &pcd->out_ep[i];
49257 +                               break;
49258 +                       }
49259 +               }
49260 +       }
49261 +
49262 +       if (!ep) {
49263 +               DWC_WARN("bad address\n");
49264 +               retval = -DWC_E_INVALID;
49265 +               goto out;
49266 +       }
49267 +
49268 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49269 +
49270 +       ep->desc = desc;
49271 +       ep->priv = usb_ep;
49272 +
49273 +       /*
49274 +        * Activate the EP
49275 +        */
49276 +       ep->stopped = 0;
49277 +
49278 +       ep->dwc_ep.is_in = (dir == UE_DIR_IN);
49279 +       ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
49280 +
49281 +       ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
49282 +
49283 +       if (ep->dwc_ep.is_in) {
49284 +               if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49285 +                       ep->dwc_ep.tx_fifo_num = 0;
49286 +
49287 +                       if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
49288 +                               /*
49289 +                                * if ISOC EP then assign a Periodic Tx FIFO.
49290 +                                */
49291 +                               ep->dwc_ep.tx_fifo_num =
49292 +                                   assign_perio_tx_fifo(GET_CORE_IF(pcd));
49293 +                       }
49294 +               } else {
49295 +                       /*
49296 +                        * if Dedicated FIFOs mode is on then assign a Tx FIFO.
49297 +                        */
49298 +                       ep->dwc_ep.tx_fifo_num =
49299 +                           assign_tx_fifo(GET_CORE_IF(pcd));
49300 +               }
49301 +
49302 +               /* Calculating EP info controller base address */
49303 +               if (ep->dwc_ep.tx_fifo_num
49304 +                   && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49305 +                       gdfifocfg.d32 =
49306 +                           DWC_READ_REG32(&GET_CORE_IF(pcd)->
49307 +                                          core_global_regs->gdfifocfg);
49308 +                       gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
49309 +                       dptxfsiz.d32 =
49310 +                           (DWC_READ_REG32
49311 +                            (&GET_CORE_IF(pcd)->core_global_regs->
49312 +                             dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16);
49313 +                       gdfifocfg.b.epinfobase =
49314 +                           gdfifocfgbase.d32 + dptxfsiz.d32;
49315 +                       if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
49316 +                               DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
49317 +                                               core_global_regs->gdfifocfg,
49318 +                                               gdfifocfg.d32);
49319 +                       }
49320 +               }
49321 +       }
49322 +       /* Set initial data PID. */
49323 +       if (ep->dwc_ep.type == UE_BULK) {
49324 +               ep->dwc_ep.data_pid_start = 0;
49325 +       }
49326 +
49327 +       /* Alloc DMA Descriptors */
49328 +       if (GET_CORE_IF(pcd)->dma_desc_enable) {
49329 +#ifndef DWC_UTE_PER_IO
49330 +               if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
49331 +#endif
49332 +                       ep->dwc_ep.desc_addr =
49333 +                           dwc_otg_ep_alloc_desc_chain(&ep->
49334 +                                                       dwc_ep.dma_desc_addr,
49335 +                                                       MAX_DMA_DESC_CNT);
49336 +                       if (!ep->dwc_ep.desc_addr) {
49337 +                               DWC_WARN("%s, can't allocate DMA descriptor\n",
49338 +                                        __func__);
49339 +                               retval = -DWC_E_SHUTDOWN;
49340 +                               DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49341 +                               goto out;
49342 +                       }
49343 +#ifndef DWC_UTE_PER_IO
49344 +               }
49345 +#endif
49346 +       }
49347 +
49348 +       DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
49349 +                   (ep->dwc_ep.is_in ? "IN" : "OUT"),
49350 +                   ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
49351 +#ifdef DWC_UTE_PER_IO
49352 +       ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
49353 +#endif
49354 +       if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
49355 +               ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
49356 +               ep->dwc_ep.frame_num = 0xFFFFFFFF;
49357 +       }
49358 +
49359 +       dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
49360 +
49361 +#ifdef DWC_UTE_CFI
49362 +       if (pcd->cfi->ops.ep_enable) {
49363 +               pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
49364 +       }
49365 +#endif
49366 +
49367 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49368 +
49369 +out:
49370 +       return retval;
49371 +}
49372 +
49373 +/**
49374 + * This function is being called from gadget
49375 + * to disable PCD endpoint.
49376 + */
49377 +int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
49378 +{
49379 +       dwc_otg_pcd_ep_t *ep;
49380 +       dwc_irqflags_t flags;
49381 +       dwc_otg_dev_dma_desc_t *desc_addr;
49382 +       dwc_dma_t dma_desc_addr;
49383 +       gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
49384 +       gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
49385 +       fifosize_data_t dptxfsiz = {.d32 = 0 };
49386 +
49387 +       ep = get_ep_from_handle(pcd, ep_handle);
49388 +
49389 +       if (!ep || !ep->desc) {
49390 +               DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
49391 +               return -DWC_E_INVALID;
49392 +       }
49393 +
49394 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49395 +
49396 +       dwc_otg_request_nuke(ep);
49397 +
49398 +       dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
49399 +       if (pcd->core_if->core_params->dev_out_nak) {
49400 +               DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
49401 +               pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
49402 +       }
49403 +       ep->desc = NULL;
49404 +       ep->stopped = 1;
49405 +
49406 +       gdfifocfg.d32 =
49407 +           DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
49408 +       gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
49409 +
49410 +       if (ep->dwc_ep.is_in) {
49411 +               if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49412 +                       /* Flush the Tx FIFO */
49413 +                       dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd),
49414 +                                             ep->dwc_ep.tx_fifo_num);
49415 +               }
49416 +               release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
49417 +               release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
49418 +               if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
49419 +                       /* Decreasing EPinfo Base Addr */
49420 +                       dptxfsiz.d32 =
49421 +                           (DWC_READ_REG32
49422 +                            (&GET_CORE_IF(pcd)->
49423 +                               core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
49424 +                       gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
49425 +                       if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) {
49426 +                               DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
49427 +                                       gdfifocfg.d32);
49428 +                       }
49429 +               }
49430 +       }
49431 +
49432 +       /* Free DMA Descriptors */
49433 +       if (GET_CORE_IF(pcd)->dma_desc_enable) {
49434 +               if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
49435 +                       desc_addr = ep->dwc_ep.desc_addr;
49436 +                       dma_desc_addr = ep->dwc_ep.dma_desc_addr;
49437 +
49438 +                       /* Cannot call dma_free_coherent() with IRQs disabled */
49439 +                       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49440 +                       dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
49441 +                                                  MAX_DMA_DESC_CNT);
49442 +
49443 +                       goto out_unlocked;
49444 +               }
49445 +       }
49446 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49447 +
49448 +out_unlocked:
49449 +       DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
49450 +                   ep->dwc_ep.is_in ? "IN" : "OUT");
49451 +       return 0;
49452 +
49453 +}
49454 +
49455 +/******************************************************************************/
49456 +#ifdef DWC_UTE_PER_IO
49457 +
49458 +/**
49459 + * Free the request and its extended parts
49460 + *
49461 + */
49462 +void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
49463 +{
49464 +       DWC_FREE(req->ext_req.per_io_frame_descs);
49465 +       DWC_FREE(req);
49466 +}
49467 +
49468 +/**
49469 + * Start the next request in the endpoint's queue.
49470 + *
49471 + */
49472 +int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
49473 +                                       dwc_otg_pcd_ep_t * ep)
49474 +{
49475 +       int i;
49476 +       dwc_otg_pcd_request_t *req = NULL;
49477 +       dwc_ep_t *dwcep = NULL;
49478 +       struct dwc_iso_xreq_port *ereq = NULL;
49479 +       struct dwc_iso_pkt_desc_port *ddesc_iso;
49480 +       uint16_t nat;
49481 +       depctl_data_t diepctl;
49482 +
49483 +       dwcep = &ep->dwc_ep;
49484 +
49485 +       if (dwcep->xiso_active_xfers > 0) {
49486 +#if 0  //Disable this to decrease s/w overhead that is crucial for Isoc transfers
49487 +               DWC_WARN("There are currently active transfers for EP%d \
49488 +                               (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers,
49489 +                               dwcep->xiso_queued_xfers);
49490 +#endif
49491 +               return 0;
49492 +       }
49493 +
49494 +       nat = UGETW(ep->desc->wMaxPacketSize);
49495 +       nat = (nat >> 11) & 0x03;
49496 +
49497 +       if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
49498 +               req = DWC_CIRCLEQ_FIRST(&ep->queue);
49499 +               ereq = &req->ext_req;
49500 +               ep->stopped = 0;
49501 +
49502 +               /* Get the frame number */
49503 +               dwcep->xiso_frame_num =
49504 +                   dwc_otg_get_frame_number(GET_CORE_IF(pcd));
49505 +               DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
49506 +
49507 +               ddesc_iso = ereq->per_io_frame_descs;
49508 +
49509 +               if (dwcep->is_in) {
49510 +                       /* Setup DMA Descriptor chain for IN Isoc request */
49511 +                       for (i = 0; i < ereq->pio_pkt_count; i++) {
49512 +                               //if ((i % (nat + 1)) == 0)
49513 +                               if ( i > 0 )
49514 +                                       dwcep->xiso_frame_num =
49515 +                                           (dwcep->xiso_bInterval +
49516 +                                                                               dwcep->xiso_frame_num) & 0x3FFF;
49517 +                               dwcep->desc_addr[i].buf =
49518 +                                   req->dma + ddesc_iso[i].offset;
49519 +                               dwcep->desc_addr[i].status.b_iso_in.txbytes =
49520 +                                   ddesc_iso[i].length;
49521 +                               dwcep->desc_addr[i].status.b_iso_in.framenum =
49522 +                                   dwcep->xiso_frame_num;
49523 +                               dwcep->desc_addr[i].status.b_iso_in.bs =
49524 +                                   BS_HOST_READY;
49525 +                               dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
49526 +                               dwcep->desc_addr[i].status.b_iso_in.sp =
49527 +                                   (ddesc_iso[i].length %
49528 +                                    dwcep->maxpacket) ? 1 : 0;
49529 +                               dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
49530 +                               dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
49531 +                               dwcep->desc_addr[i].status.b_iso_in.l = 0;
49532 +
49533 +                               /* Process the last descriptor */
49534 +                               if (i == ereq->pio_pkt_count - 1) {
49535 +                                       dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
49536 +                                       dwcep->desc_addr[i].status.b_iso_in.l = 1;
49537 +                               }
49538 +                       }
49539 +
49540 +                       /* Setup and start the transfer for this endpoint */
49541 +                       dwcep->xiso_active_xfers++;
49542 +                       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
49543 +                                       in_ep_regs[dwcep->num]->diepdma,
49544 +                                       dwcep->dma_desc_addr);
49545 +                       diepctl.d32 = 0;
49546 +                       diepctl.b.epena = 1;
49547 +                       diepctl.b.cnak = 1;
49548 +                       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
49549 +                                        in_ep_regs[dwcep->num]->diepctl, 0,
49550 +                                        diepctl.d32);
49551 +               } else {
49552 +                       /* Setup DMA Descriptor chain for OUT Isoc request */
49553 +                       for (i = 0; i < ereq->pio_pkt_count; i++) {
49554 +                               //if ((i % (nat + 1)) == 0)
49555 +                               dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
49556 +                                                                               dwcep->xiso_frame_num) & 0x3FFF;
49557 +                               dwcep->desc_addr[i].buf =
49558 +                                   req->dma + ddesc_iso[i].offset;
49559 +                               dwcep->desc_addr[i].status.b_iso_out.rxbytes =
49560 +                                   ddesc_iso[i].length;
49561 +                               dwcep->desc_addr[i].status.b_iso_out.framenum =
49562 +                                   dwcep->xiso_frame_num;
49563 +                               dwcep->desc_addr[i].status.b_iso_out.bs =
49564 +                                   BS_HOST_READY;
49565 +                               dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
49566 +                               dwcep->desc_addr[i].status.b_iso_out.sp =
49567 +                                   (ddesc_iso[i].length %
49568 +                                    dwcep->maxpacket) ? 1 : 0;
49569 +                               dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
49570 +                               dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
49571 +                               dwcep->desc_addr[i].status.b_iso_out.l = 0;
49572 +
49573 +                               /* Process the last descriptor */
49574 +                               if (i == ereq->pio_pkt_count - 1) {
49575 +                                       dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
49576 +                                       dwcep->desc_addr[i].status.b_iso_out.l = 1;
49577 +                               }
49578 +                       }
49579 +
49580 +                       /* Setup and start the transfer for this endpoint */
49581 +                       dwcep->xiso_active_xfers++;
49582 +                       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->
49583 +                                       dev_if->out_ep_regs[dwcep->num]->
49584 +                                       doepdma, dwcep->dma_desc_addr);
49585 +                       diepctl.d32 = 0;
49586 +                       diepctl.b.epena = 1;
49587 +                       diepctl.b.cnak = 1;
49588 +                       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
49589 +                                        dev_if->out_ep_regs[dwcep->num]->
49590 +                                        doepctl, 0, diepctl.d32);
49591 +               }
49592 +
49593 +       } else {
49594 +               ep->stopped = 1;
49595 +       }
49596 +
49597 +       return 0;
49598 +}
49599 +
49600 +/**
49601 + *     - Remove the request from the queue
49602 + */
49603 +void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
49604 +{
49605 +       dwc_otg_pcd_request_t *req = NULL;
49606 +       struct dwc_iso_xreq_port *ereq = NULL;
49607 +       struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
49608 +       dwc_ep_t *dwcep = NULL;
49609 +       int i;
49610 +
49611 +       //DWC_DEBUG();
49612 +       dwcep = &ep->dwc_ep;
49613 +
49614 +       /* Get the first pending request from the queue */
49615 +       if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
49616 +               req = DWC_CIRCLEQ_FIRST(&ep->queue);
49617 +               if (!req) {
49618 +                       DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
49619 +                       return;
49620 +               }
49621 +               dwcep->xiso_active_xfers--;
49622 +               dwcep->xiso_queued_xfers--;
49623 +               /* Remove this request from the queue */
49624 +               DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
49625 +       } else {
49626 +               DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
49627 +               return;
49628 +       }
49629 +
49630 +       ep->stopped = 1;
49631 +       ereq = &req->ext_req;
49632 +       ddesc_iso = ereq->per_io_frame_descs;
49633 +
49634 +       if (dwcep->xiso_active_xfers < 0) {
49635 +               DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
49636 +                        dwcep->xiso_active_xfers);
49637 +       }
49638 +
49639 +       /* Fill the Isoc descs of portable extended req from dma descriptors */
49640 +       for (i = 0; i < ereq->pio_pkt_count; i++) {
49641 +               if (dwcep->is_in) {     /* IN endpoints */
49642 +                       ddesc_iso[i].actual_length = ddesc_iso[i].length -
49643 +                           dwcep->desc_addr[i].status.b_iso_in.txbytes;
49644 +                       ddesc_iso[i].status =
49645 +                           dwcep->desc_addr[i].status.b_iso_in.txsts;
49646 +               } else {        /* OUT endpoints */
49647 +                       ddesc_iso[i].actual_length = ddesc_iso[i].length -
49648 +                           dwcep->desc_addr[i].status.b_iso_out.rxbytes;
49649 +                       ddesc_iso[i].status =
49650 +                           dwcep->desc_addr[i].status.b_iso_out.rxsts;
49651 +               }
49652 +       }
49653 +
49654 +       DWC_SPINUNLOCK(ep->pcd->lock);
49655 +
49656 +       /* Call the completion function in the non-portable logic */
49657 +       ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
49658 +                                     &req->ext_req);
49659 +
49660 +       DWC_SPINLOCK(ep->pcd->lock);
49661 +
49662 +       /* Free the request - specific freeing needed for extended request object */
49663 +       dwc_pcd_xiso_ereq_free(ep, req);
49664 +
49665 +       /* Start the next request */
49666 +       dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
49667 +
49668 +       return;
49669 +}
49670 +
49671 +/**
49672 + * Create and initialize the Isoc pkt descriptors of the extended request.
49673 + *
49674 + */
49675 +static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
49676 +                                            void *ereq_nonport,
49677 +                                            int atomic_alloc)
49678 +{
49679 +       struct dwc_iso_xreq_port *ereq = NULL;
49680 +       struct dwc_iso_xreq_port *req_mapped = NULL;
49681 +       struct dwc_iso_pkt_desc_port *ipds = NULL;      /* To be created in this function */
49682 +       uint32_t pkt_count;
49683 +       int i;
49684 +
49685 +       ereq = &req->ext_req;
49686 +       req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
49687 +       pkt_count = req_mapped->pio_pkt_count;
49688 +
49689 +       /* Create the isoc descs */
49690 +       if (atomic_alloc) {
49691 +               ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
49692 +       } else {
49693 +               ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
49694 +       }
49695 +
49696 +       if (!ipds) {
49697 +               DWC_ERROR("Failed to allocate isoc descriptors");
49698 +               return -DWC_E_NO_MEMORY;
49699 +       }
49700 +
49701 +       /* Initialize the extended request fields */
49702 +       ereq->per_io_frame_descs = ipds;
49703 +       ereq->error_count = 0;
49704 +       ereq->pio_alloc_pkt_count = pkt_count;
49705 +       ereq->pio_pkt_count = pkt_count;
49706 +       ereq->tr_sub_flags = req_mapped->tr_sub_flags;
49707 +
49708 +       /* Init the Isoc descriptors */
49709 +       for (i = 0; i < pkt_count; i++) {
49710 +               ipds[i].length = req_mapped->per_io_frame_descs[i].length;
49711 +               ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
49712 +               ipds[i].status = req_mapped->per_io_frame_descs[i].status;      /* 0 */
49713 +               ipds[i].actual_length =
49714 +                   req_mapped->per_io_frame_descs[i].actual_length;
49715 +       }
49716 +
49717 +       return 0;
49718 +}
49719 +
49720 +static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
49721 +{
49722 +       struct dwc_iso_pkt_desc_port *xfd = NULL;
49723 +       int i;
49724 +
49725 +       DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
49726 +       DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
49727 +       DWC_DEBUG("error_count=%d", ereq->error_count);
49728 +       DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
49729 +       DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
49730 +       DWC_DEBUG("res=%d", ereq->res);
49731 +
49732 +       for (i = 0; i < ereq->pio_pkt_count; i++) {
49733 +               xfd = &ereq->per_io_frame_descs[0];
49734 +               DWC_DEBUG("FD #%d", i);
49735 +
49736 +               DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
49737 +               DWC_DEBUG("xfd->length=%d", xfd->length);
49738 +               DWC_DEBUG("xfd->offset=%d", xfd->offset);
49739 +               DWC_DEBUG("xfd->status=%d", xfd->status);
49740 +       }
49741 +}
49742 +
49743 +/**
49744 + *
49745 + */
49746 +int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
49747 +                             uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
49748 +                             int zero, void *req_handle, int atomic_alloc,
49749 +                             void *ereq_nonport)
49750 +{
49751 +       dwc_otg_pcd_request_t *req = NULL;
49752 +       dwc_otg_pcd_ep_t *ep;
49753 +       dwc_irqflags_t flags;
49754 +       int res;
49755 +
49756 +       ep = get_ep_from_handle(pcd, ep_handle);
49757 +       if (!ep) {
49758 +               DWC_WARN("bad ep\n");
49759 +               return -DWC_E_INVALID;
49760 +       }
49761 +
49762 +       /* We support this extension only for DDMA mode */
49763 +       if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
49764 +               if (!GET_CORE_IF(pcd)->dma_desc_enable)
49765 +                       return -DWC_E_INVALID;
49766 +
49767 +       /* Create a dwc_otg_pcd_request_t object */
49768 +       if (atomic_alloc) {
49769 +               req = DWC_ALLOC_ATOMIC(sizeof(*req));
49770 +       } else {
49771 +               req = DWC_ALLOC(sizeof(*req));
49772 +       }
49773 +
49774 +       if (!req) {
49775 +               return -DWC_E_NO_MEMORY;
49776 +       }
49777 +
49778 +       /* Create the Isoc descs for this request which shall be the exact match
49779 +        * of the structure sent to us from the non-portable logic */
49780 +       res =
49781 +           dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
49782 +       if (res) {
49783 +               DWC_WARN("Failed to init the Isoc descriptors");
49784 +               DWC_FREE(req);
49785 +               return res;
49786 +       }
49787 +
49788 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49789 +
49790 +       DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
49791 +       req->buf = buf;
49792 +       req->dma = dma_buf;
49793 +       req->length = buflen;
49794 +       req->sent_zlp = zero;
49795 +       req->priv = req_handle;
49796 +
49797 +       //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49798 +       ep->dwc_ep.dma_addr = dma_buf;
49799 +       ep->dwc_ep.start_xfer_buff = buf;
49800 +       ep->dwc_ep.xfer_buff = buf;
49801 +       ep->dwc_ep.xfer_len = 0;
49802 +       ep->dwc_ep.xfer_count = 0;
49803 +       ep->dwc_ep.sent_zlp = 0;
49804 +       ep->dwc_ep.total_len = buflen;
49805 +
49806 +       /* Add this request to the tail */
49807 +       DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
49808 +       ep->dwc_ep.xiso_queued_xfers++;
49809 +
49810 +//DWC_DEBUG("CP_0");
49811 +//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
49812 +//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
49813 +//prn_ext_request(&req->ext_req);
49814 +
49815 +       //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49816 +
49817 +       /* If the req->status == ASAP  then check if there is any active transfer
49818 +        * for this endpoint. If no active transfers, then get the first entry
49819 +        * from the queue and start that transfer
49820 +        */
49821 +       if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
49822 +               res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
49823 +               if (res) {
49824 +                       DWC_WARN("Failed to start the next Isoc transfer");
49825 +                       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49826 +                       DWC_FREE(req);
49827 +                       return res;
49828 +               }
49829 +       }
49830 +
49831 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49832 +       return 0;
49833 +}
49834 +
49835 +#endif
49836 +/* END ifdef DWC_UTE_PER_IO ***************************************************/
49837 +int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
49838 +                        uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
49839 +                        int zero, void *req_handle, int atomic_alloc)
49840 +{
49841 +       dwc_irqflags_t flags;
49842 +       dwc_otg_pcd_request_t *req;
49843 +       dwc_otg_pcd_ep_t *ep;
49844 +       uint32_t max_transfer;
49845 +
49846 +       ep = get_ep_from_handle(pcd, ep_handle);
49847 +       if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
49848 +               DWC_WARN("bad ep\n");
49849 +               return -DWC_E_INVALID;
49850 +       }
49851 +
49852 +       if (atomic_alloc) {
49853 +               req = DWC_ALLOC_ATOMIC(sizeof(*req));
49854 +       } else {
49855 +               req = DWC_ALLOC(sizeof(*req));
49856 +       }
49857 +
49858 +       if (!req) {
49859 +               return -DWC_E_NO_MEMORY;
49860 +       }
49861 +       DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
49862 +       if (!GET_CORE_IF(pcd)->core_params->opt) {
49863 +               if (ep->dwc_ep.num != 0) {
49864 +                       DWC_ERROR("queue req %p, len %d buf %p\n",
49865 +                                 req_handle, buflen, buf);
49866 +               }
49867 +       }
49868 +
49869 +       req->buf = buf;
49870 +       req->dma = dma_buf;
49871 +       req->length = buflen;
49872 +       req->sent_zlp = zero;
49873 +       req->priv = req_handle;
49874 +       req->dw_align_buf = NULL;
49875 +       if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
49876 +                       && !GET_CORE_IF(pcd)->dma_desc_enable)
49877 +               req->dw_align_buf = DWC_DMA_ALLOC(buflen,
49878 +                                &req->dw_align_buf_dma);
49879 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
49880 +
49881 +       /*
49882 +        * After adding request to the queue for IN ISOC wait for In Token Received
49883 +        * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token
49884 +        * Received when EP is disabled interrupt to obtain starting microframe
49885 +        * (odd/even) start transfer
49886 +        */
49887 +       if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
49888 +               if (req != 0) {
49889 +                       depctl_data_t depctl = {.d32 =
49890 +                                   DWC_READ_REG32(&pcd->core_if->dev_if->
49891 +                                                  in_ep_regs[ep->dwc_ep.num]->
49892 +                                                  diepctl) };
49893 +                       ++pcd->request_pending;
49894 +
49895 +                       DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
49896 +                       if (ep->dwc_ep.is_in) {
49897 +                               depctl.b.cnak = 1;
49898 +                               DWC_WRITE_REG32(&pcd->core_if->dev_if->
49899 +                                               in_ep_regs[ep->dwc_ep.num]->
49900 +                                               diepctl, depctl.d32);
49901 +                       }
49902 +
49903 +                       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49904 +               }
49905 +               return 0;
49906 +       }
49907 +
49908 +       /*
49909 +        * For EP0 IN without premature status, zlp is required?
49910 +        */
49911 +       if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
49912 +               DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
49913 +               //_req->zero = 1;
49914 +       }
49915 +
49916 +       /* Start the transfer */
49917 +       if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
49918 +               /* EP0 Transfer? */
49919 +               if (ep->dwc_ep.num == 0) {
49920 +                       switch (pcd->ep0state) {
49921 +                       case EP0_IN_DATA_PHASE:
49922 +                               DWC_DEBUGPL(DBG_PCD,
49923 +                                           "%s ep0: EP0_IN_DATA_PHASE\n",
49924 +                                           __func__);
49925 +                               break;
49926 +
49927 +                       case EP0_OUT_DATA_PHASE:
49928 +                               DWC_DEBUGPL(DBG_PCD,
49929 +                                           "%s ep0: EP0_OUT_DATA_PHASE\n",
49930 +                                           __func__);
49931 +                               if (pcd->request_config) {
49932 +                                       /* Complete STATUS PHASE */
49933 +                                       ep->dwc_ep.is_in = 1;
49934 +                                       pcd->ep0state = EP0_IN_STATUS_PHASE;
49935 +                               }
49936 +                               break;
49937 +
49938 +                       case EP0_IN_STATUS_PHASE:
49939 +                               DWC_DEBUGPL(DBG_PCD,
49940 +                                           "%s ep0: EP0_IN_STATUS_PHASE\n",
49941 +                                           __func__);
49942 +                               break;
49943 +
49944 +                       default:
49945 +                               DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
49946 +                                           pcd->ep0state);
49947 +                               DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
49948 +                               return -DWC_E_SHUTDOWN;
49949 +                       }
49950 +
49951 +                       ep->dwc_ep.dma_addr = dma_buf;
49952 +                       ep->dwc_ep.start_xfer_buff = buf;
49953 +                       ep->dwc_ep.xfer_buff = buf;
49954 +                       ep->dwc_ep.xfer_len = buflen;
49955 +                       ep->dwc_ep.xfer_count = 0;
49956 +                       ep->dwc_ep.sent_zlp = 0;
49957 +                       ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
49958 +
49959 +                       if (zero) {
49960 +                               if ((ep->dwc_ep.xfer_len %
49961 +                                    ep->dwc_ep.maxpacket == 0)
49962 +                                   && (ep->dwc_ep.xfer_len != 0)) {
49963 +                                       ep->dwc_ep.sent_zlp = 1;
49964 +                               }
49965 +
49966 +                       }
49967 +
49968 +                       dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
49969 +                                                  &ep->dwc_ep);
49970 +               }               // non-ep0 endpoints
49971 +               else {
49972 +#ifdef DWC_UTE_CFI
49973 +                       if (ep->dwc_ep.buff_mode != BM_STANDARD) {
49974 +                               /* store the request length */
49975 +                               ep->dwc_ep.cfi_req_len = buflen;
49976 +                               pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
49977 +                                                               ep, req);
49978 +                       } else {
49979 +#endif
49980 +                               max_transfer =
49981 +                                   GET_CORE_IF(ep->pcd)->core_params->
49982 +                                   max_transfer_size;
49983 +
49984 +                               /* Setup and start the Transfer */
49985 +                               if (req->dw_align_buf){
49986 +                                       if (ep->dwc_ep.is_in)
49987 +                                               dwc_memcpy(req->dw_align_buf,
49988 +                                                          buf, buflen);
49989 +                                       ep->dwc_ep.dma_addr =
49990 +                                           req->dw_align_buf_dma;
49991 +                                       ep->dwc_ep.start_xfer_buff =
49992 +                                           req->dw_align_buf;
49993 +                                       ep->dwc_ep.xfer_buff =
49994 +                                           req->dw_align_buf;
49995 +                               } else {
49996 +                                       ep->dwc_ep.dma_addr = dma_buf;
49997 +                                       ep->dwc_ep.start_xfer_buff = buf;
49998 +                                        ep->dwc_ep.xfer_buff = buf;
49999 +                               }
50000 +                               ep->dwc_ep.xfer_len = 0;
50001 +                               ep->dwc_ep.xfer_count = 0;
50002 +                               ep->dwc_ep.sent_zlp = 0;
50003 +                               ep->dwc_ep.total_len = buflen;
50004 +
50005 +                               ep->dwc_ep.maxxfer = max_transfer;
50006 +                               if (GET_CORE_IF(pcd)->dma_desc_enable) {
50007 +                                       uint32_t out_max_xfer =
50008 +                                           DDMA_MAX_TRANSFER_SIZE -
50009 +                                           (DDMA_MAX_TRANSFER_SIZE % 4);
50010 +                                       if (ep->dwc_ep.is_in) {
50011 +                                               if (ep->dwc_ep.maxxfer >
50012 +                                                   DDMA_MAX_TRANSFER_SIZE) {
50013 +                                                       ep->dwc_ep.maxxfer =
50014 +                                                           DDMA_MAX_TRANSFER_SIZE;
50015 +                                               }
50016 +                                       } else {
50017 +                                               if (ep->dwc_ep.maxxfer >
50018 +                                                   out_max_xfer) {
50019 +                                                       ep->dwc_ep.maxxfer =
50020 +                                                           out_max_xfer;
50021 +                                               }
50022 +                                       }
50023 +                               }
50024 +                               if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
50025 +                                       ep->dwc_ep.maxxfer -=
50026 +                                           (ep->dwc_ep.maxxfer %
50027 +                                            ep->dwc_ep.maxpacket);
50028 +                               }
50029 +
50030 +                               if (zero) {
50031 +                                       if ((ep->dwc_ep.total_len %
50032 +                                            ep->dwc_ep.maxpacket == 0)
50033 +                                           && (ep->dwc_ep.total_len != 0)) {
50034 +                                               ep->dwc_ep.sent_zlp = 1;
50035 +                                       }
50036 +                               }
50037 +#ifdef DWC_UTE_CFI
50038 +                       }
50039 +#endif
50040 +                       dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
50041 +                                                 &ep->dwc_ep);
50042 +               }
50043 +       }
50044 +
50045 +       if (req != 0) {
50046 +               ++pcd->request_pending;
50047 +               DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
50048 +               if (ep->dwc_ep.is_in && ep->stopped
50049 +                   && !(GET_CORE_IF(pcd)->dma_enable)) {
50050 +                       /** @todo NGS Create a function for this. */
50051 +                       diepmsk_data_t diepmsk = {.d32 = 0 };
50052 +                       diepmsk.b.intktxfemp = 1;
50053 +                       if (GET_CORE_IF(pcd)->multiproc_int_enable) {
50054 +                               DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
50055 +                                                dev_if->dev_global_regs->diepeachintmsk
50056 +                                                [ep->dwc_ep.num], 0,
50057 +                                                diepmsk.d32);
50058 +                       } else {
50059 +                               DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->
50060 +                                                dev_if->dev_global_regs->
50061 +                                                diepmsk, 0, diepmsk.d32);
50062 +                       }
50063 +
50064 +               }
50065 +       }
50066 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50067 +
50068 +       return 0;
50069 +}
50070 +
50071 +int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
50072 +                          void *req_handle)
50073 +{
50074 +       dwc_irqflags_t flags;
50075 +       dwc_otg_pcd_request_t *req;
50076 +       dwc_otg_pcd_ep_t *ep;
50077 +
50078 +       ep = get_ep_from_handle(pcd, ep_handle);
50079 +       if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
50080 +               DWC_WARN("bad argument\n");
50081 +               return -DWC_E_INVALID;
50082 +       }
50083 +
50084 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50085 +
50086 +       /* make sure it's actually queued on this endpoint */
50087 +       DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
50088 +               if (req->priv == (void *)req_handle) {
50089 +                       break;
50090 +               }
50091 +       }
50092 +
50093 +       if (req->priv != (void *)req_handle) {
50094 +               DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50095 +               return -DWC_E_INVALID;
50096 +       }
50097 +
50098 +       if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
50099 +               dwc_otg_request_done(ep, req, -DWC_E_RESTART);
50100 +       } else {
50101 +               req = NULL;
50102 +       }
50103 +
50104 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50105 +
50106 +       return req ? 0 : -DWC_E_SHUTDOWN;
50107 +
50108 +}
50109 +
50110 +/**
50111 + * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests
50112 + *
50113 + * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
50114 + * requests. If the gadget driver clears the halt status, it will
50115 + * automatically unwedge the endpoint.
50116 + *
50117 + * Returns zero on success, else negative DWC error code.
50118 + */
50119 +int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle)
50120 +{
50121 +       dwc_otg_pcd_ep_t *ep;
50122 +       dwc_irqflags_t flags;
50123 +       int retval = 0;
50124 +
50125 +       ep = get_ep_from_handle(pcd, ep_handle);
50126 +
50127 +       if ((!ep->desc && ep != &pcd->ep0) ||
50128 +           (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
50129 +               DWC_WARN("%s, bad ep\n", __func__);
50130 +               return -DWC_E_INVALID;
50131 +       }
50132 +
50133 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50134 +       if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
50135 +               DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
50136 +                        ep->dwc_ep.is_in ? "IN" : "OUT");
50137 +               retval = -DWC_E_AGAIN;
50138 +       } else {
50139 +                /* This code needs to be reviewed */
50140 +               if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
50141 +                       dtxfsts_data_t txstatus;
50142 +                       fifosize_data_t txfifosize;
50143 +
50144 +                       txfifosize.d32 =
50145 +                           DWC_READ_REG32(&GET_CORE_IF(pcd)->
50146 +                                          core_global_regs->dtxfsiz[ep->dwc_ep.
50147 +                                                                    tx_fifo_num]);
50148 +                       txstatus.d32 =
50149 +                           DWC_READ_REG32(&GET_CORE_IF(pcd)->
50150 +                                          dev_if->in_ep_regs[ep->dwc_ep.num]->
50151 +                                          dtxfsts);
50152 +
50153 +                       if (txstatus.b.txfspcavail < txfifosize.b.depth) {
50154 +                               DWC_WARN("%s() Data In Tx Fifo\n", __func__);
50155 +                               retval = -DWC_E_AGAIN;
50156 +                       } else {
50157 +                               if (ep->dwc_ep.num == 0) {
50158 +                                       pcd->ep0state = EP0_STALL;
50159 +                               }
50160 +
50161 +                               ep->stopped = 1;
50162 +                               dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
50163 +                                                    &ep->dwc_ep);
50164 +                       }
50165 +               } else {
50166 +                       if (ep->dwc_ep.num == 0) {
50167 +                               pcd->ep0state = EP0_STALL;
50168 +                       }
50169 +
50170 +                       ep->stopped = 1;
50171 +                       dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50172 +               }
50173 +       }
50174 +
50175 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50176 +
50177 +       return retval;
50178 +}
50179 +
50180 +int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
50181 +{
50182 +       dwc_otg_pcd_ep_t *ep;
50183 +       dwc_irqflags_t flags;
50184 +       int retval = 0;
50185 +
50186 +       ep = get_ep_from_handle(pcd, ep_handle);
50187 +
50188 +       if (!ep || (!ep->desc && ep != &pcd->ep0) ||
50189 +           (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
50190 +               DWC_WARN("%s, bad ep\n", __func__);
50191 +               return -DWC_E_INVALID;
50192 +       }
50193 +
50194 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50195 +       if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
50196 +               DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
50197 +                        ep->dwc_ep.is_in ? "IN" : "OUT");
50198 +               retval = -DWC_E_AGAIN;
50199 +       } else if (value == 0) {
50200 +               dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50201 +       } else if (value == 1) {
50202 +               if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
50203 +                       dtxfsts_data_t txstatus;
50204 +                       fifosize_data_t txfifosize;
50205 +
50206 +                       txfifosize.d32 =
50207 +                           DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
50208 +                                          dtxfsiz[ep->dwc_ep.tx_fifo_num]);
50209 +                       txstatus.d32 =
50210 +                           DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
50211 +                                          in_ep_regs[ep->dwc_ep.num]->dtxfsts);
50212 +
50213 +                       if (txstatus.b.txfspcavail < txfifosize.b.depth) {
50214 +                               DWC_WARN("%s() Data In Tx Fifo\n", __func__);
50215 +                               retval = -DWC_E_AGAIN;
50216 +                       } else {
50217 +                               if (ep->dwc_ep.num == 0) {
50218 +                                       pcd->ep0state = EP0_STALL;
50219 +                               }
50220 +
50221 +                               ep->stopped = 1;
50222 +                               dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
50223 +                                                    &ep->dwc_ep);
50224 +                       }
50225 +               } else {
50226 +                       if (ep->dwc_ep.num == 0) {
50227 +                               pcd->ep0state = EP0_STALL;
50228 +                       }
50229 +
50230 +                       ep->stopped = 1;
50231 +                       dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
50232 +               }
50233 +       } else if (value == 2) {
50234 +               ep->dwc_ep.stall_clear_flag = 0;
50235 +       } else if (value == 3) {
50236 +               ep->dwc_ep.stall_clear_flag = 1;
50237 +       }
50238 +
50239 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50240 +
50241 +       return retval;
50242 +}
50243 +
50244 +/**
50245 + * This function initiates remote wakeup of the host from suspend state.
50246 + */
50247 +void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
50248 +{
50249 +       dctl_data_t dctl = { 0 };
50250 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50251 +       dsts_data_t dsts;
50252 +
50253 +       dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
50254 +       if (!dsts.b.suspsts) {
50255 +               DWC_WARN("Remote wakeup while is not in suspend state\n");
50256 +       }
50257 +       /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
50258 +       if (pcd->remote_wakeup_enable) {
50259 +               if (set) {
50260 +
50261 +                       if (core_if->adp_enable) {
50262 +                               gpwrdn_data_t gpwrdn;
50263 +
50264 +                               dwc_otg_adp_probe_stop(core_if);
50265 +
50266 +                               /* Mask SRP detected interrupt from Power Down Logic */
50267 +                               gpwrdn.d32 = 0;
50268 +                               gpwrdn.b.srp_det_msk = 1;
50269 +                               DWC_MODIFY_REG32(&core_if->
50270 +                                                core_global_regs->gpwrdn,
50271 +                                                gpwrdn.d32, 0);
50272 +
50273 +                               /* Disable Power Down Logic */
50274 +                               gpwrdn.d32 = 0;
50275 +                               gpwrdn.b.pmuactv = 1;
50276 +                               DWC_MODIFY_REG32(&core_if->
50277 +                                                core_global_regs->gpwrdn,
50278 +                                                gpwrdn.d32, 0);
50279 +
50280 +                               /*
50281 +                                * Initialize the Core for Device mode.
50282 +                                */
50283 +                               core_if->op_state = B_PERIPHERAL;
50284 +                               dwc_otg_core_init(core_if);
50285 +                               dwc_otg_enable_global_interrupts(core_if);
50286 +                               cil_pcd_start(core_if);
50287 +
50288 +                               dwc_otg_initiate_srp(core_if);
50289 +                       }
50290 +
50291 +                       dctl.b.rmtwkupsig = 1;
50292 +                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50293 +                                        dctl, 0, dctl.d32);
50294 +                       DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
50295 +
50296 +                       dwc_mdelay(2);
50297 +                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
50298 +                                        dctl, dctl.d32, 0);
50299 +                       DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
50300 +               }
50301 +       } else {
50302 +               DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
50303 +       }
50304 +}
50305 +
50306 +#ifdef CONFIG_USB_DWC_OTG_LPM
50307 +/**
50308 + * This function initiates remote wakeup of the host from L1 sleep state.
50309 + */
50310 +void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
50311 +{
50312 +       glpmcfg_data_t lpmcfg;
50313 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50314 +
50315 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
50316 +
50317 +       /* Check if we are in L1 state */
50318 +       if (!lpmcfg.b.prt_sleep_sts) {
50319 +               DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
50320 +               return;
50321 +       }
50322 +
50323 +       /* Check if host allows remote wakeup */
50324 +       if (!lpmcfg.b.rem_wkup_en) {
50325 +               DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
50326 +               return;
50327 +       }
50328 +
50329 +       /* Check if Resume OK */
50330 +       if (!lpmcfg.b.sleep_state_resumeok) {
50331 +               DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
50332 +               return;
50333 +       }
50334 +
50335 +       lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
50336 +       lpmcfg.b.en_utmi_sleep = 0;
50337 +       lpmcfg.b.hird_thres &= (~(1 << 4));
50338 +       DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
50339 +
50340 +       if (set) {
50341 +               dctl_data_t dctl = {.d32 = 0 };
50342 +               dctl.b.rmtwkupsig = 1;
50343 +               /* Set RmtWkUpSig bit to start remote wakup signaling.
50344 +                * Hardware will automatically clear this bit.
50345 +                */
50346 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
50347 +                                0, dctl.d32);
50348 +               DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
50349 +       }
50350 +
50351 +}
50352 +#endif
50353 +
50354 +/**
50355 + * Performs remote wakeup.
50356 + */
50357 +void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
50358 +{
50359 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50360 +       dwc_irqflags_t flags;
50361 +       if (dwc_otg_is_device_mode(core_if)) {
50362 +               DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50363 +#ifdef CONFIG_USB_DWC_OTG_LPM
50364 +               if (core_if->lx_state == DWC_OTG_L1) {
50365 +                       dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
50366 +               } else {
50367 +#endif
50368 +                       dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
50369 +#ifdef CONFIG_USB_DWC_OTG_LPM
50370 +               }
50371 +#endif
50372 +               DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50373 +       }
50374 +       return;
50375 +}
50376 +
50377 +void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
50378 +{
50379 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
50380 +       dctl_data_t dctl = { 0 };
50381 +
50382 +       if (dwc_otg_is_device_mode(core_if)) {
50383 +               dctl.b.sftdiscon = 1;
50384 +               DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
50385 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
50386 +               dwc_udelay(no_of_usecs);
50387 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
50388 +
50389 +       } else{
50390 +               DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
50391 +       }
50392 +       return;
50393 +
50394 +}
50395 +
50396 +int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
50397 +{
50398 +       dsts_data_t dsts;
50399 +       gotgctl_data_t gotgctl;
50400 +
50401 +       /*
50402 +        * This function starts the Protocol if no session is in progress. If
50403 +        * a session is already in progress, but the device is suspended,
50404 +        * remote wakeup signaling is started.
50405 +        */
50406 +
50407 +       /* Check if valid session */
50408 +       gotgctl.d32 =
50409 +           DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
50410 +       if (gotgctl.b.bsesvld) {
50411 +               /* Check if suspend state */
50412 +               dsts.d32 =
50413 +                   DWC_READ_REG32(&
50414 +                                  (GET_CORE_IF(pcd)->dev_if->
50415 +                                   dev_global_regs->dsts));
50416 +               if (dsts.b.suspsts) {
50417 +                       dwc_otg_pcd_remote_wakeup(pcd, 1);
50418 +               }
50419 +       } else {
50420 +               dwc_otg_pcd_initiate_srp(pcd);
50421 +       }
50422 +
50423 +       return 0;
50424 +
50425 +}
50426 +
50427 +/**
50428 + * Start the SRP timer to detect when the SRP does not complete within
50429 + * 6 seconds.
50430 + *
50431 + * @param pcd the pcd structure.
50432 + */
50433 +void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
50434 +{
50435 +       dwc_irqflags_t flags;
50436 +       DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
50437 +       dwc_otg_initiate_srp(GET_CORE_IF(pcd));
50438 +       DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
50439 +}
50440 +
50441 +int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
50442 +{
50443 +       return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
50444 +}
50445 +
50446 +int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
50447 +{
50448 +       return GET_CORE_IF(pcd)->core_params->lpm_enable;
50449 +}
50450 +
50451 +uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
50452 +{
50453 +       return pcd->b_hnp_enable;
50454 +}
50455 +
50456 +uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
50457 +{
50458 +       return pcd->a_hnp_support;
50459 +}
50460 +
50461 +uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
50462 +{
50463 +       return pcd->a_alt_hnp_support;
50464 +}
50465 +
50466 +int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
50467 +{
50468 +       return pcd->remote_wakeup_enable;
50469 +}
50470 +
50471 +#endif /* DWC_HOST_ONLY */
50472 --- /dev/null
50473 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.h
50474 @@ -0,0 +1,266 @@
50475 +/* ==========================================================================
50476 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
50477 + * $Revision: #48 $
50478 + * $Date: 2012/08/10 $
50479 + * $Change: 2047372 $
50480 + *
50481 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
50482 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
50483 + * otherwise expressly agreed to in writing between Synopsys and you.
50484 + *
50485 + * The Software IS NOT an item of Licensed Software or Licensed Product under
50486 + * any End User Software License Agreement or Agreement for Licensed Product
50487 + * with Synopsys or any supplement thereto. You are permitted to use and
50488 + * redistribute this Software in source and binary forms, with or without
50489 + * modification, provided that redistributions of source code must retain this
50490 + * notice. You may not view, use, disclose, copy or distribute this file or
50491 + * any information contained herein except pursuant to this license grant from
50492 + * Synopsys. If you do not agree with this notice, including the disclaimer
50493 + * below, then you are not authorized to use the Software.
50494 + *
50495 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
50496 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50497 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50498 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
50499 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50500 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
50501 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
50502 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50503 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50504 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
50505 + * DAMAGE.
50506 + * ========================================================================== */
50507 +#ifndef DWC_HOST_ONLY
50508 +#if !defined(__DWC_PCD_H__)
50509 +#define __DWC_PCD_H__
50510 +
50511 +#include "dwc_otg_os_dep.h"
50512 +#include "usb.h"
50513 +#include "dwc_otg_cil.h"
50514 +#include "dwc_otg_pcd_if.h"
50515 +struct cfiobject;
50516 +
50517 +/**
50518 + * @file
50519 + *
50520 + * This file contains the structures, constants, and interfaces for
50521 + * the Perpherial Contoller Driver (PCD).
50522 + *
50523 + * The Peripheral Controller Driver (PCD) for Linux will implement the
50524 + * Gadget API, so that the existing Gadget drivers can be used. For
50525 + * the Mass Storage Function driver the File-backed USB Storage Gadget
50526 + * (FBS) driver will be used.  The FBS driver supports the
50527 + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
50528 + * transports.
50529 + *
50530 + */
50531 +
50532 +/** Invalid DMA Address */
50533 +#define DWC_DMA_ADDR_INVALID   (~(dwc_dma_t)0)
50534 +
50535 +/** Max Transfer size for any EP */
50536 +#define DDMA_MAX_TRANSFER_SIZE 65535
50537 +
50538 +/**
50539 + * Get the pointer to the core_if from the pcd pointer.
50540 + */
50541 +#define GET_CORE_IF( _pcd ) (_pcd->core_if)
50542 +
50543 +/**
50544 + * States of EP0.
50545 + */
50546 +typedef enum ep0_state {
50547 +       EP0_DISCONNECT,         /* no host */
50548 +       EP0_IDLE,
50549 +       EP0_IN_DATA_PHASE,
50550 +       EP0_OUT_DATA_PHASE,
50551 +       EP0_IN_STATUS_PHASE,
50552 +       EP0_OUT_STATUS_PHASE,
50553 +       EP0_STALL,
50554 +} ep0state_e;
50555 +
50556 +/** Fordward declaration.*/
50557 +struct dwc_otg_pcd;
50558 +
50559 +/** DWC_otg iso request structure.
50560 + *
50561 + */
50562 +typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
50563 +
50564 +#ifdef DWC_UTE_PER_IO
50565 +
50566 +/**
50567 + * This shall be the exact analogy of the same type structure defined in the
50568 + * usb_gadget.h. Each descriptor contains
50569 + */
50570 +struct dwc_iso_pkt_desc_port {
50571 +       uint32_t offset;
50572 +       uint32_t length;        /* expected length */
50573 +       uint32_t actual_length;
50574 +       uint32_t status;
50575 +};
50576 +
50577 +struct dwc_iso_xreq_port {
50578 +       /** transfer/submission flag */
50579 +       uint32_t tr_sub_flags;
50580 +       /** Start the request ASAP */
50581 +#define DWC_EREQ_TF_ASAP               0x00000002
50582 +       /** Just enqueue the request w/o initiating a transfer */
50583 +#define DWC_EREQ_TF_ENQUEUE            0x00000004
50584 +
50585 +       /**
50586 +       * count of ISO packets attached to this request - shall
50587 +       * not exceed the pio_alloc_pkt_count
50588 +       */
50589 +       uint32_t pio_pkt_count;
50590 +       /** count of ISO packets allocated for this request */
50591 +       uint32_t pio_alloc_pkt_count;
50592 +       /** number of ISO packet errors */
50593 +       uint32_t error_count;
50594 +       /** reserved for future extension */
50595 +       uint32_t res;
50596 +       /** Will be allocated and freed in the UTE gadget and based on the CFC value */
50597 +       struct dwc_iso_pkt_desc_port *per_io_frame_descs;
50598 +};
50599 +#endif
50600 +/** DWC_otg request structure.
50601 + * This structure is a list of requests.
50602 + */
50603 +typedef struct dwc_otg_pcd_request {
50604 +       void *priv;
50605 +       void *buf;
50606 +       dwc_dma_t dma;
50607 +       uint32_t length;
50608 +       uint32_t actual;
50609 +       unsigned sent_zlp:1;
50610 +    /**
50611 +     * Used instead of original buffer if
50612 +     * it(physical address) is not dword-aligned.
50613 +     **/
50614 +     uint8_t *dw_align_buf;
50615 +     dwc_dma_t dw_align_buf_dma;
50616 +
50617 +        DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
50618 +#ifdef DWC_UTE_PER_IO
50619 +       struct dwc_iso_xreq_port ext_req;
50620 +       //void *priv_ereq_nport; /*  */
50621 +#endif
50622 +} dwc_otg_pcd_request_t;
50623 +
50624 +DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
50625 +
50626 +/**      PCD EP structure.
50627 + * This structure describes an EP, there is an array of EPs in the PCD
50628 + * structure.
50629 + */
50630 +typedef struct dwc_otg_pcd_ep {
50631 +       /** USB EP Descriptor */
50632 +       const usb_endpoint_descriptor_t *desc;
50633 +
50634 +       /** queue of dwc_otg_pcd_requests. */
50635 +       struct req_list queue;
50636 +       unsigned stopped:1;
50637 +       unsigned disabling:1;
50638 +       unsigned dma:1;
50639 +       unsigned queue_sof:1;
50640 +
50641 +#ifdef DWC_EN_ISOC
50642 +       /** ISOC req handle passed */
50643 +       void *iso_req_handle;
50644 +#endif                         //_EN_ISOC_
50645 +
50646 +       /** DWC_otg ep data. */
50647 +       dwc_ep_t dwc_ep;
50648 +
50649 +       /** Pointer to PCD */
50650 +       struct dwc_otg_pcd *pcd;
50651 +
50652 +       void *priv;
50653 +} dwc_otg_pcd_ep_t;
50654 +
50655 +/** DWC_otg PCD Structure.
50656 + * This structure encapsulates the data for the dwc_otg PCD.
50657 + */
50658 +struct dwc_otg_pcd {
50659 +       const struct dwc_otg_pcd_function_ops *fops;
50660 +       /** The DWC otg device pointer */
50661 +       struct dwc_otg_device *otg_dev;
50662 +       /** Core Interface */
50663 +       dwc_otg_core_if_t *core_if;
50664 +       /** State of EP0 */
50665 +       ep0state_e ep0state;
50666 +       /** EP0 Request is pending */
50667 +       unsigned ep0_pending:1;
50668 +       /** Indicates when SET CONFIGURATION Request is in process */
50669 +       unsigned request_config:1;
50670 +       /** The state of the Remote Wakeup Enable. */
50671 +       unsigned remote_wakeup_enable:1;
50672 +       /** The state of the B-Device HNP Enable. */
50673 +       unsigned b_hnp_enable:1;
50674 +       /** The state of A-Device HNP Support. */
50675 +       unsigned a_hnp_support:1;
50676 +       /** The state of the A-Device Alt HNP support. */
50677 +       unsigned a_alt_hnp_support:1;
50678 +       /** Count of pending Requests */
50679 +       unsigned request_pending;
50680 +
50681 +       /** SETUP packet for EP0
50682 +        * This structure is allocated as a DMA buffer on PCD initialization
50683 +        * with enough space for up to 3 setup packets.
50684 +        */
50685 +       union {
50686 +               usb_device_request_t req;
50687 +               uint32_t d32[2];
50688 +       } *setup_pkt;
50689 +
50690 +       dwc_dma_t setup_pkt_dma_handle;
50691 +
50692 +       /* Additional buffer and flag for CTRL_WR premature case */
50693 +       uint8_t *backup_buf;
50694 +       unsigned data_terminated;
50695 +
50696 +       /** 2-byte dma buffer used to return status from GET_STATUS */
50697 +       uint16_t *status_buf;
50698 +       dwc_dma_t status_buf_dma_handle;
50699 +
50700 +       /** EP0 */
50701 +       dwc_otg_pcd_ep_t ep0;
50702 +
50703 +       /** Array of IN EPs. */
50704 +       dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
50705 +       /** Array of OUT EPs. */
50706 +       dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
50707 +       /** number of valid EPs in the above array. */
50708 +//        unsigned      num_eps : 4;
50709 +       dwc_spinlock_t *lock;
50710 +
50711 +       /** Tasklet to defer starting of TEST mode transmissions until
50712 +        *      Status Phase has been completed.
50713 +        */
50714 +       dwc_tasklet_t *test_mode_tasklet;
50715 +
50716 +       /** Tasklet to delay starting of xfer in DMA mode */
50717 +       dwc_tasklet_t *start_xfer_tasklet;
50718 +
50719 +       /** The test mode to enter when the tasklet is executed. */
50720 +       unsigned test_mode;
50721 +       /** The cfi_api structure that implements most of the CFI API
50722 +        * and OTG specific core configuration functionality
50723 +        */
50724 +#ifdef DWC_UTE_CFI
50725 +       struct cfiobject *cfi;
50726 +#endif
50727 +
50728 +};
50729 +
50730 +//FIXME this functions should be static, and this prototypes should be removed
50731 +extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
50732 +extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
50733 +                                dwc_otg_pcd_request_t * req, int32_t status);
50734 +
50735 +void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
50736 +                            void *req_handle);
50737 +
50738 +extern void do_test_mode(void *data);
50739 +#endif
50740 +#endif /* DWC_HOST_ONLY */
50741 --- /dev/null
50742 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h
50743 @@ -0,0 +1,360 @@
50744 +/* ==========================================================================
50745 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
50746 + * $Revision: #11 $
50747 + * $Date: 2011/10/26 $
50748 + * $Change: 1873028 $
50749 + *
50750 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
50751 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
50752 + * otherwise expressly agreed to in writing between Synopsys and you.
50753 + *
50754 + * The Software IS NOT an item of Licensed Software or Licensed Product under
50755 + * any End User Software License Agreement or Agreement for Licensed Product
50756 + * with Synopsys or any supplement thereto. You are permitted to use and
50757 + * redistribute this Software in source and binary forms, with or without
50758 + * modification, provided that redistributions of source code must retain this
50759 + * notice. You may not view, use, disclose, copy or distribute this file or
50760 + * any information contained herein except pursuant to this license grant from
50761 + * Synopsys. If you do not agree with this notice, including the disclaimer
50762 + * below, then you are not authorized to use the Software.
50763 + *
50764 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
50765 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50766 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50767 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
50768 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
50769 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
50770 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
50771 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50772 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50773 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
50774 + * DAMAGE.
50775 + * ========================================================================== */
50776 +#ifndef DWC_HOST_ONLY
50777 +
50778 +#if !defined(__DWC_PCD_IF_H__)
50779 +#define __DWC_PCD_IF_H__
50780 +
50781 +//#include "dwc_os.h"
50782 +#include "dwc_otg_core_if.h"
50783 +
50784 +/** @file
50785 + * This file defines DWC_OTG PCD Core API.
50786 + */
50787 +
50788 +struct dwc_otg_pcd;
50789 +typedef struct dwc_otg_pcd dwc_otg_pcd_t;
50790 +
50791 +/** Maxpacket size for EP0 */
50792 +#define MAX_EP0_SIZE   64
50793 +/** Maxpacket size for any EP */
50794 +#define MAX_PACKET_SIZE 1024
50795 +
50796 +/** @name Function Driver Callbacks */
50797 +/** @{ */
50798 +
50799 +/** This function will be called whenever a previously queued request has
50800 + * completed.  The status value will be set to -DWC_E_SHUTDOWN to indicated a
50801 + * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
50802 + * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
50803 + * parameters. */
50804 +typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
50805 +                                   void *req_handle, int32_t status,
50806 +                                   uint32_t actual);
50807 +/**
50808 + * This function will be called whenever a previousle queued ISOC request has
50809 + * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
50810 + * function.
50811 + * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
50812 + * functions.
50813 + */
50814 +typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
50815 +                                        void *req_handle, int proc_buf_num);
50816 +/** This function should handle any SETUP request that cannot be handled by the
50817 + * PCD Core.  This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
50818 + * class-specific requests, etc.  The function must non-blocking.
50819 + *
50820 + * Returns 0 on success.
50821 + * Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
50822 + * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
50823 + * Returns -DWC_E_SHUTDOWN on any other error. */
50824 +typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
50825 +/** This is called whenever the device has been disconnected.  The function
50826 + * driver should take appropriate action to clean up all pending requests in the
50827 + * PCD Core, remove all endpoints (except ep0), and initialize back to reset
50828 + * state. */
50829 +typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
50830 +/** This function is called when device has been connected. */
50831 +typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
50832 +/** This function is called when device has been suspended */
50833 +typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
50834 +/** This function is called when device has received LPM tokens, i.e.
50835 + * device has been sent to sleep state. */
50836 +typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
50837 +/** This function is called when device has been resumed
50838 + * from suspend(L2) or L1 sleep state. */
50839 +typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
50840 +/** This function is called whenever hnp params has been changed.
50841 + * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
50842 + * to get hnp parameters. */
50843 +typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
50844 +/** This function is called whenever USB RESET is detected. */
50845 +typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
50846 +
50847 +typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
50848 +
50849 +/**
50850 + *
50851 + * @param ep_handle    Void pointer to the usb_ep structure
50852 + * @param ereq_port Pointer to the extended request structure created in the
50853 + *                                     portable part.
50854 + */
50855 +typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
50856 +                                    void *req_handle, int32_t status,
50857 +                                    void *ereq_port);
50858 +/** Function Driver Ops Data Structure */
50859 +struct dwc_otg_pcd_function_ops {
50860 +       dwc_connect_cb_t connect;
50861 +       dwc_disconnect_cb_t disconnect;
50862 +       dwc_setup_cb_t setup;
50863 +       dwc_completion_cb_t complete;
50864 +       dwc_isoc_completion_cb_t isoc_complete;
50865 +       dwc_suspend_cb_t suspend;
50866 +       dwc_sleep_cb_t sleep;
50867 +       dwc_resume_cb_t resume;
50868 +       dwc_reset_cb_t reset;
50869 +       dwc_hnp_params_changed_cb_t hnp_changed;
50870 +       cfi_setup_cb_t cfi_setup;
50871 +#ifdef DWC_UTE_PER_IO
50872 +       xiso_completion_cb_t xisoc_complete;
50873 +#endif
50874 +};
50875 +/** @} */
50876 +
50877 +/** @name Function Driver Functions */
50878 +/** @{ */
50879 +
50880 +/** Call this function to get pointer on dwc_otg_pcd_t,
50881 + * this pointer will be used for all PCD API functions.
50882 + *
50883 + * @param core_if The DWC_OTG Core
50884 + */
50885 +extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
50886 +
50887 +/** Frees PCD allocated by dwc_otg_pcd_init
50888 + *
50889 + * @param pcd The PCD
50890 + */
50891 +extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
50892 +
50893 +/** Call this to bind the function driver to the PCD Core.
50894 + *
50895 + * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
50896 + * @param fops The Function Driver Ops data structure containing pointers to all callbacks.
50897 + */
50898 +extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
50899 +                             const struct dwc_otg_pcd_function_ops *fops);
50900 +
50901 +/** Enables an endpoint for use.  This function enables an endpoint in
50902 + * the PCD.  The endpoint is described by the ep_desc which has the
50903 + * same format as a USB ep descriptor.  The ep_handle parameter is used to refer
50904 + * to the endpoint from other API functions and in callbacks.  Normally this
50905 + * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
50906 + * core for that interface.
50907 + *
50908 + * Returns -DWC_E_INVALID if invalid parameters were passed.
50909 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
50910 + * Returns 0 on success.
50911 + *
50912 + * @param pcd The PCD
50913 + * @param ep_desc Endpoint descriptor
50914 + * @param usb_ep Handle on endpoint, that will be used to identify endpoint.
50915 + */
50916 +extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
50917 +                                const uint8_t * ep_desc, void *usb_ep);
50918 +
50919 +/** Disable the endpoint referenced by ep_handle.
50920 + *
50921 + * Returns -DWC_E_INVALID if invalid parameters were passed.
50922 + * Returns -DWC_E_SHUTDOWN if any other error occurred.
50923 + * Returns 0 on success. */
50924 +extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
50925 +
50926 +/** Queue a data transfer request on the endpoint referenced by ep_handle.
50927 + * After the transfer is completes, the complete callback will be called with
50928 + * the request status.
50929 + *
50930 + * @param pcd The PCD
50931 + * @param ep_handle The handle of the endpoint
50932 + * @param buf The buffer for the data
50933 + * @param dma_buf The DMA buffer for the data
50934 + * @param buflen The length of the data transfer
50935 + * @param zero Specifies whether to send zero length last packet.
50936 + * @param req_handle Set this handle to any value to use to reference this
50937 + * request in the ep_dequeue function or from the complete callback
50938 + * @param atomic_alloc If driver need to perform atomic allocations
50939 + * for internal data structures.
50940 + *
50941 + * Returns -DWC_E_INVALID if invalid parameters were passed.
50942 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
50943 + * Returns 0 on success. */
50944 +extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
50945 +                               uint8_t * buf, dwc_dma_t dma_buf,
50946 +                               uint32_t buflen, int zero, void *req_handle,
50947 +                               int atomic_alloc);
50948 +#ifdef DWC_UTE_PER_IO
50949 +/**
50950 + *
50951 + * @param ereq_nonport Pointer to the extended request part of the
50952 + *                                             usb_request structure defined in usb_gadget.h file.
50953 + */
50954 +extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
50955 +                                    uint8_t * buf, dwc_dma_t dma_buf,
50956 +                                    uint32_t buflen, int zero,
50957 +                                    void *req_handle, int atomic_alloc,
50958 +                                    void *ereq_nonport);
50959 +
50960 +#endif
50961 +
50962 +/** De-queue the specified data transfer that has not yet completed.
50963 + *
50964 + * Returns -DWC_E_INVALID if invalid parameters were passed.
50965 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
50966 + * Returns 0 on success. */
50967 +extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
50968 +                                 void *req_handle);
50969 +
50970 +/** Halt (STALL) an endpoint or clear it.
50971 + *
50972 + * Returns -DWC_E_INVALID if invalid parameters were passed.
50973 + * Returns -DWC_E_SHUTDOWN if any other error ocurred.
50974 + * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
50975 + * Returns 0 on success. */
50976 +extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
50977 +
50978 +/** This function */
50979 +extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle);
50980 +
50981 +/** This function should be called on every hardware interrupt */
50982 +extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
50983 +
50984 +/** This function returns current frame number */
50985 +extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
50986 +
50987 +/**
50988 + * Start isochronous transfers on the endpoint referenced by ep_handle.
50989 + * For isochronous transfers duble buffering is used.
50990 + * After processing each of buffers comlete callback will be called with
50991 + * status for each transaction.
50992 + *
50993 + * @param pcd The PCD
50994 + * @param ep_handle The handle of the endpoint
50995 + * @param buf0 The virtual address of first data buffer
50996 + * @param buf1 The virtual address of second data buffer
50997 + * @param dma0 The DMA address of first data buffer
50998 + * @param dma1 The DMA address of second data buffer
50999 + * @param sync_frame Data pattern frame number
51000 + * @param dp_frame Data size for pattern frame
51001 + * @param data_per_frame Data size for regular frame
51002 + * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
51003 + * @param buf_proc_intrvl Interval of ISOC Buffer processing
51004 + * @param req_handle Handle of ISOC request
51005 + * @param atomic_alloc Specefies whether to perform atomic allocation for
51006 + *                     internal data structures.
51007 + *
51008 + * Returns -DWC_E_NO_MEMORY if there is no enough memory.
51009 + * Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
51010 + * Returns -DW_E_SHUTDOWN for any other error.
51011 + * Returns 0 on success
51012 + */
51013 +extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
51014 +                                   uint8_t * buf0, uint8_t * buf1,
51015 +                                   dwc_dma_t dma0, dwc_dma_t dma1,
51016 +                                   int sync_frame, int dp_frame,
51017 +                                   int data_per_frame, int start_frame,
51018 +                                   int buf_proc_intrvl, void *req_handle,
51019 +                                   int atomic_alloc);
51020 +
51021 +/** Stop ISOC transfers on endpoint referenced by ep_handle.
51022 + *
51023 + * @param pcd The PCD
51024 + * @param ep_handle The handle of the endpoint
51025 + * @param req_handle Handle of ISOC request
51026 + *
51027 + * Returns -DWC_E_INVALID if incorrect arguments are passed to the function
51028 + * Returns 0 on success
51029 + */
51030 +int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
51031 +                           void *req_handle);
51032 +
51033 +/** Get ISOC packet status.
51034 + *
51035 + * @param pcd The PCD
51036 + * @param ep_handle The handle of the endpoint
51037 + * @param iso_req_handle Isochronoush request handle
51038 + * @param packet Number of packet
51039 + * @param status Out parameter for returning status
51040 + * @param actual Out parameter for returning actual length
51041 + * @param offset Out parameter for returning offset
51042 + *
51043 + */
51044 +extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
51045 +                                             void *ep_handle,
51046 +                                             void *iso_req_handle, int packet,
51047 +                                             int *status, int *actual,
51048 +                                             int *offset);
51049 +
51050 +/** Get ISOC packet count.
51051 + *
51052 + * @param pcd The PCD
51053 + * @param ep_handle The handle of the endpoint
51054 + * @param iso_req_handle
51055 + */
51056 +extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
51057 +                                           void *ep_handle,
51058 +                                           void *iso_req_handle);
51059 +
51060 +/** This function starts the SRP Protocol if no session is in progress. If
51061 + * a session is already in progress, but the device is suspended,
51062 + * remote wakeup signaling is started.
51063 + */
51064 +extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
51065 +
51066 +/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
51067 +extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
51068 +
51069 +/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
51070 +extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
51071 +
51072 +/** Initiate SRP */
51073 +extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
51074 +
51075 +/** Starts remote wakeup signaling. */
51076 +extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
51077 +
51078 +/** Starts micorsecond soft disconnect. */
51079 +extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
51080 +/** This function returns whether device is dualspeed.*/
51081 +extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
51082 +
51083 +/** This function returns whether device is otg. */
51084 +extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
51085 +
51086 +/** These functions allow to get hnp parameters */
51087 +extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
51088 +extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
51089 +extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
51090 +
51091 +/** CFI specific Interface functions */
51092 +/** Allocate a cfi buffer */
51093 +extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
51094 +                                    dwc_dma_t * addr, size_t buflen,
51095 +                                    int flags);
51096 +
51097 +/******************************************************************************/
51098 +
51099 +/** @} */
51100 +
51101 +#endif                         /* __DWC_PCD_IF_H__ */
51102 +
51103 +#endif                         /* DWC_HOST_ONLY */
51104 --- /dev/null
51105 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
51106 @@ -0,0 +1,5147 @@
51107 +/* ==========================================================================
51108 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
51109 + * $Revision: #116 $
51110 + * $Date: 2012/08/10 $
51111 + * $Change: 2047372 $
51112 + *
51113 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
51114 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
51115 + * otherwise expressly agreed to in writing between Synopsys and you.
51116 + *
51117 + * The Software IS NOT an item of Licensed Software or Licensed Product under
51118 + * any End User Software License Agreement or Agreement for Licensed Product
51119 + * with Synopsys or any supplement thereto. You are permitted to use and
51120 + * redistribute this Software in source and binary forms, with or without
51121 + * modification, provided that redistributions of source code must retain this
51122 + * notice. You may not view, use, disclose, copy or distribute this file or
51123 + * any information contained herein except pursuant to this license grant from
51124 + * Synopsys. If you do not agree with this notice, including the disclaimer
51125 + * below, then you are not authorized to use the Software.
51126 + *
51127 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
51128 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
51129 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51130 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
51131 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
51132 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
51133 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
51134 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
51135 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51136 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
51137 + * DAMAGE.
51138 + * ========================================================================== */
51139 +#ifndef DWC_HOST_ONLY
51140 +
51141 +#include "dwc_otg_pcd.h"
51142 +
51143 +#ifdef DWC_UTE_CFI
51144 +#include "dwc_otg_cfi.h"
51145 +#endif
51146 +
51147 +#ifdef DWC_UTE_PER_IO
51148 +extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
51149 +#endif
51150 +//#define PRINT_CFI_DMA_DESCS
51151 +
51152 +#define DEBUG_EP0
51153 +
51154 +/**
51155 + * This function updates OTG.
51156 + */
51157 +static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
51158 +{
51159 +
51160 +       if (reset) {
51161 +               pcd->b_hnp_enable = 0;
51162 +               pcd->a_hnp_support = 0;
51163 +               pcd->a_alt_hnp_support = 0;
51164 +       }
51165 +
51166 +       if (pcd->fops->hnp_changed) {
51167 +               pcd->fops->hnp_changed(pcd);
51168 +       }
51169 +}
51170 +
51171 +/** @file
51172 + * This file contains the implementation of the PCD Interrupt handlers.
51173 + *
51174 + * The PCD handles the device interrupts.  Many conditions can cause a
51175 + * device interrupt. When an interrupt occurs, the device interrupt
51176 + * service routine determines the cause of the interrupt and
51177 + * dispatches handling to the appropriate function. These interrupt
51178 + * handling functions are described below.
51179 + * All interrupt registers are processed from LSB to MSB.
51180 + */
51181 +
51182 +/**
51183 + * This function prints the ep0 state for debug purposes.
51184 + */
51185 +static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
51186 +{
51187 +#ifdef DEBUG
51188 +       char str[40];
51189 +
51190 +       switch (pcd->ep0state) {
51191 +       case EP0_DISCONNECT:
51192 +               dwc_strcpy(str, "EP0_DISCONNECT");
51193 +               break;
51194 +       case EP0_IDLE:
51195 +               dwc_strcpy(str, "EP0_IDLE");
51196 +               break;
51197 +       case EP0_IN_DATA_PHASE:
51198 +               dwc_strcpy(str, "EP0_IN_DATA_PHASE");
51199 +               break;
51200 +       case EP0_OUT_DATA_PHASE:
51201 +               dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
51202 +               break;
51203 +       case EP0_IN_STATUS_PHASE:
51204 +               dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
51205 +               break;
51206 +       case EP0_OUT_STATUS_PHASE:
51207 +               dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
51208 +               break;
51209 +       case EP0_STALL:
51210 +               dwc_strcpy(str, "EP0_STALL");
51211 +               break;
51212 +       default:
51213 +               dwc_strcpy(str, "EP0_INVALID");
51214 +       }
51215 +
51216 +       DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
51217 +#endif
51218 +}
51219 +
51220 +/**
51221 + * This function calculate the size of the payload in the memory
51222 + * for out endpoints and prints size for debug purposes(used in
51223 + * 2.93a DevOutNak feature).
51224 + */
51225 +static inline void print_memory_payload(dwc_otg_pcd_t * pcd,  dwc_ep_t * ep)
51226 +{
51227 +#ifdef DEBUG
51228 +       deptsiz_data_t deptsiz_init = {.d32 = 0 };
51229 +       deptsiz_data_t deptsiz_updt = {.d32 = 0 };
51230 +       int pack_num;
51231 +       unsigned payload;
51232 +
51233 +       deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
51234 +       deptsiz_updt.d32 =
51235 +               DWC_READ_REG32(&pcd->core_if->dev_if->
51236 +                                               out_ep_regs[ep->num]->doeptsiz);
51237 +       /* Payload will be */
51238 +       payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
51239 +       /* Packet count is decremented every time a packet
51240 +        * is written to the RxFIFO not in to the external memory
51241 +        * So, if payload == 0, then it means no packet was sent to ext memory*/
51242 +       pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
51243 +       DWC_DEBUGPL(DBG_PCDV,
51244 +               "Payload for EP%d-%s\n",
51245 +               ep->num, (ep->is_in ? "IN" : "OUT"));
51246 +       DWC_DEBUGPL(DBG_PCDV,
51247 +               "Number of transfered bytes = 0x%08x\n", payload);
51248 +       DWC_DEBUGPL(DBG_PCDV,
51249 +               "Number of transfered packets = %d\n", pack_num);
51250 +#endif
51251 +}
51252 +
51253 +
51254 +#ifdef DWC_UTE_CFI
51255 +static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
51256 +                             const uint8_t * epname, int descnum)
51257 +{
51258 +       CFI_INFO
51259 +           ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
51260 +            epname, descnum, ddesc->buf, ddesc->status.b.bytes,
51261 +            ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
51262 +            ddesc->status.b.bs);
51263 +}
51264 +#endif
51265 +
51266 +/**
51267 + * This function returns pointer to in ep struct with number ep_num
51268 + */
51269 +static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
51270 +{
51271 +       int i;
51272 +       int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
51273 +       if (ep_num == 0) {
51274 +               return &pcd->ep0;
51275 +       } else {
51276 +               for (i = 0; i < num_in_eps; ++i) {
51277 +                       if (pcd->in_ep[i].dwc_ep.num == ep_num)
51278 +                               return &pcd->in_ep[i];
51279 +               }
51280 +               return 0;
51281 +       }
51282 +}
51283 +
51284 +/**
51285 + * This function returns pointer to out ep struct with number ep_num
51286 + */
51287 +static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
51288 +{
51289 +       int i;
51290 +       int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
51291 +       if (ep_num == 0) {
51292 +               return &pcd->ep0;
51293 +       } else {
51294 +               for (i = 0; i < num_out_eps; ++i) {
51295 +                       if (pcd->out_ep[i].dwc_ep.num == ep_num)
51296 +                               return &pcd->out_ep[i];
51297 +               }
51298 +               return 0;
51299 +       }
51300 +}
51301 +
51302 +/**
51303 + * This functions gets a pointer to an EP from the wIndex address
51304 + * value of the control request.
51305 + */
51306 +dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
51307 +{
51308 +       dwc_otg_pcd_ep_t *ep;
51309 +       uint32_t ep_num = UE_GET_ADDR(wIndex);
51310 +
51311 +       if (ep_num == 0) {
51312 +               ep = &pcd->ep0;
51313 +       } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {   /* in ep */
51314 +               ep = &pcd->in_ep[ep_num - 1];
51315 +       } else {
51316 +               ep = &pcd->out_ep[ep_num - 1];
51317 +       }
51318 +
51319 +       return ep;
51320 +}
51321 +
51322 +/**
51323 + * This function checks the EP request queue, if the queue is not
51324 + * empty the next request is started.
51325 + */
51326 +void start_next_request(dwc_otg_pcd_ep_t * ep)
51327 +{
51328 +       dwc_otg_pcd_request_t *req = 0;
51329 +       uint32_t max_transfer =
51330 +           GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
51331 +
51332 +#ifdef DWC_UTE_CFI
51333 +       struct dwc_otg_pcd *pcd;
51334 +       pcd = ep->pcd;
51335 +#endif
51336 +
51337 +       if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
51338 +               req = DWC_CIRCLEQ_FIRST(&ep->queue);
51339 +
51340 +#ifdef DWC_UTE_CFI
51341 +               if (ep->dwc_ep.buff_mode != BM_STANDARD) {
51342 +                       ep->dwc_ep.cfi_req_len = req->length;
51343 +                       pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
51344 +               } else {
51345 +#endif
51346 +                       /* Setup and start the Transfer */
51347 +                       if (req->dw_align_buf) {
51348 +                               ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
51349 +                               ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
51350 +                               ep->dwc_ep.xfer_buff = req->dw_align_buf;
51351 +                       } else {
51352 +                               ep->dwc_ep.dma_addr = req->dma;
51353 +                               ep->dwc_ep.start_xfer_buff = req->buf;
51354 +                               ep->dwc_ep.xfer_buff = req->buf;
51355 +                       }
51356 +                       ep->dwc_ep.sent_zlp = 0;
51357 +                       ep->dwc_ep.total_len = req->length;
51358 +                       ep->dwc_ep.xfer_len = 0;
51359 +                       ep->dwc_ep.xfer_count = 0;
51360 +
51361 +                       ep->dwc_ep.maxxfer = max_transfer;
51362 +                       if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
51363 +                               uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
51364 +                                   - (DDMA_MAX_TRANSFER_SIZE % 4);
51365 +                               if (ep->dwc_ep.is_in) {
51366 +                                       if (ep->dwc_ep.maxxfer >
51367 +                                           DDMA_MAX_TRANSFER_SIZE) {
51368 +                                               ep->dwc_ep.maxxfer =
51369 +                                                   DDMA_MAX_TRANSFER_SIZE;
51370 +                                       }
51371 +                               } else {
51372 +                                       if (ep->dwc_ep.maxxfer > out_max_xfer) {
51373 +                                               ep->dwc_ep.maxxfer =
51374 +                                                   out_max_xfer;
51375 +                                       }
51376 +                               }
51377 +                       }
51378 +                       if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
51379 +                               ep->dwc_ep.maxxfer -=
51380 +                                   (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
51381 +                       }
51382 +                       if (req->sent_zlp) {
51383 +                               if ((ep->dwc_ep.total_len %
51384 +                                    ep->dwc_ep.maxpacket == 0)
51385 +                                   && (ep->dwc_ep.total_len != 0)) {
51386 +                                       ep->dwc_ep.sent_zlp = 1;
51387 +                               }
51388 +
51389 +                       }
51390 +#ifdef DWC_UTE_CFI
51391 +               }
51392 +#endif
51393 +               dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
51394 +       } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
51395 +               DWC_PRINTF("There are no more ISOC requests \n");
51396 +               ep->dwc_ep.frame_num = 0xFFFFFFFF;
51397 +       }
51398 +}
51399 +
51400 +/**
51401 + * This function handles the SOF Interrupts. At this time the SOF
51402 + * Interrupt is disabled.
51403 + */
51404 +int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
51405 +{
51406 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51407 +
51408 +       gintsts_data_t gintsts;
51409 +
51410 +       DWC_DEBUGPL(DBG_PCD, "SOF\n");
51411 +
51412 +       /* Clear interrupt */
51413 +       gintsts.d32 = 0;
51414 +       gintsts.b.sofintr = 1;
51415 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
51416 +
51417 +       return 1;
51418 +}
51419 +
51420 +/**
51421 + * This function handles the Rx Status Queue Level Interrupt, which
51422 + * indicates that there is a least one packet in the Rx FIFO.  The
51423 + * packets are moved from the FIFO to memory, where they will be
51424 + * processed when the Endpoint Interrupt Register indicates Transfer
51425 + * Complete or SETUP Phase Done.
51426 + *
51427 + * Repeat the following until the Rx Status Queue is empty:
51428 + *      -# Read the Receive Status Pop Register (GRXSTSP) to get Packet
51429 + *             info
51430 + *      -# If Receive FIFO is empty then skip to step Clear the interrupt
51431 + *             and exit
51432 + *      -# If SETUP Packet call dwc_otg_read_setup_packet to copy the
51433 + *             SETUP data to the buffer
51434 + *      -# If OUT Data Packet call dwc_otg_read_packet to copy the data
51435 + *             to the destination buffer
51436 + */
51437 +int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
51438 +{
51439 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51440 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
51441 +       gintmsk_data_t gintmask = {.d32 = 0 };
51442 +       device_grxsts_data_t status;
51443 +       dwc_otg_pcd_ep_t *ep;
51444 +       gintsts_data_t gintsts;
51445 +#ifdef DEBUG
51446 +       static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
51447 +#endif
51448 +
51449 +       //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
51450 +       /* Disable the Rx Status Queue Level interrupt */
51451 +       gintmask.b.rxstsqlvl = 1;
51452 +       DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
51453 +
51454 +       /* Get the Status from the top of the FIFO */
51455 +       status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
51456 +
51457 +       DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
51458 +                   "pktsts:%x Frame:%d(0x%0x)\n",
51459 +                   status.b.epnum, status.b.bcnt,
51460 +                   dpid_str[status.b.dpid],
51461 +                   status.b.pktsts, status.b.fn, status.b.fn);
51462 +       /* Get pointer to EP structure */
51463 +       ep = get_out_ep(pcd, status.b.epnum);
51464 +
51465 +       switch (status.b.pktsts) {
51466 +       case DWC_DSTS_GOUT_NAK:
51467 +               DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
51468 +               break;
51469 +       case DWC_STS_DATA_UPDT:
51470 +               DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
51471 +               if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
51472 +                       /** @todo NGS Check for buffer overflow? */
51473 +                       dwc_otg_read_packet(core_if,
51474 +                                           ep->dwc_ep.xfer_buff,
51475 +                                           status.b.bcnt);
51476 +                       ep->dwc_ep.xfer_count += status.b.bcnt;
51477 +                       ep->dwc_ep.xfer_buff += status.b.bcnt;
51478 +               }
51479 +               break;
51480 +       case DWC_STS_XFER_COMP:
51481 +               DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
51482 +               break;
51483 +       case DWC_DSTS_SETUP_COMP:
51484 +#ifdef DEBUG_EP0
51485 +               DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
51486 +#endif
51487 +               break;
51488 +       case DWC_DSTS_SETUP_UPDT:
51489 +               dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
51490 +#ifdef DEBUG_EP0
51491 +               DWC_DEBUGPL(DBG_PCD,
51492 +                           "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
51493 +                           pcd->setup_pkt->req.bmRequestType,
51494 +                           pcd->setup_pkt->req.bRequest,
51495 +                           UGETW(pcd->setup_pkt->req.wValue),
51496 +                           UGETW(pcd->setup_pkt->req.wIndex),
51497 +                           UGETW(pcd->setup_pkt->req.wLength));
51498 +#endif
51499 +               ep->dwc_ep.xfer_count += status.b.bcnt;
51500 +               break;
51501 +       default:
51502 +               DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
51503 +                           status.b.pktsts);
51504 +               break;
51505 +       }
51506 +
51507 +       /* Enable the Rx Status Queue Level interrupt */
51508 +       DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
51509 +       /* Clear interrupt */
51510 +       gintsts.d32 = 0;
51511 +       gintsts.b.rxstsqlvl = 1;
51512 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
51513 +
51514 +       //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
51515 +       return 1;
51516 +}
51517 +
51518 +/**
51519 + * This function examines the Device IN Token Learning Queue to
51520 + * determine the EP number of the last IN token received.  This
51521 + * implementation is for the Mass Storage device where there are only
51522 + * 2 IN EPs (Control-IN and BULK-IN).
51523 + *
51524 + * The EP numbers for the first six IN Tokens are in DTKNQR1 and there
51525 + * are 8 EP Numbers in each of the other possible DTKNQ Registers.
51526 + *
51527 + * @param core_if Programming view of DWC_otg controller.
51528 + *
51529 + */
51530 +static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
51531 +{
51532 +       dwc_otg_device_global_regs_t *dev_global_regs =
51533 +           core_if->dev_if->dev_global_regs;
51534 +       const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
51535 +       /* Number of Token Queue Registers */
51536 +       const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
51537 +       dtknq1_data_t dtknqr1;
51538 +       uint32_t in_tkn_epnums[4];
51539 +       int ndx = 0;
51540 +       int i = 0;
51541 +       volatile uint32_t *addr = &dev_global_regs->dtknqr1;
51542 +       int epnum = 0;
51543 +
51544 +       //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
51545 +
51546 +       /* Read the DTKNQ Registers */
51547 +       for (i = 0; i < DTKNQ_REG_CNT; i++) {
51548 +               in_tkn_epnums[i] = DWC_READ_REG32(addr);
51549 +               DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
51550 +                           in_tkn_epnums[i]);
51551 +               if (addr == &dev_global_regs->dvbusdis) {
51552 +                       addr = &dev_global_regs->dtknqr3_dthrctl;
51553 +               } else {
51554 +                       ++addr;
51555 +               }
51556 +
51557 +       }
51558 +
51559 +       /* Copy the DTKNQR1 data to the bit field. */
51560 +       dtknqr1.d32 = in_tkn_epnums[0];
51561 +       /* Get the EP numbers */
51562 +       in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
51563 +       ndx = dtknqr1.b.intknwptr - 1;
51564 +
51565 +       //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
51566 +       if (ndx == -1) {
51567 +               /** @todo Find a simpler way to calculate the max
51568 +                * queue position.*/
51569 +               int cnt = TOKEN_Q_DEPTH;
51570 +               if (TOKEN_Q_DEPTH <= 6) {
51571 +                       cnt = TOKEN_Q_DEPTH - 1;
51572 +               } else if (TOKEN_Q_DEPTH <= 14) {
51573 +                       cnt = TOKEN_Q_DEPTH - 7;
51574 +               } else if (TOKEN_Q_DEPTH <= 22) {
51575 +                       cnt = TOKEN_Q_DEPTH - 15;
51576 +               } else {
51577 +                       cnt = TOKEN_Q_DEPTH - 23;
51578 +               }
51579 +               epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
51580 +       } else {
51581 +               if (ndx <= 5) {
51582 +                       epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
51583 +               } else if (ndx <= 13) {
51584 +                       ndx -= 6;
51585 +                       epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
51586 +               } else if (ndx <= 21) {
51587 +                       ndx -= 14;
51588 +                       epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
51589 +               } else if (ndx <= 29) {
51590 +                       ndx -= 22;
51591 +                       epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
51592 +               }
51593 +       }
51594 +       //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
51595 +       return epnum;
51596 +}
51597 +
51598 +/**
51599 + * This interrupt occurs when the non-periodic Tx FIFO is half-empty.
51600 + * The active request is checked for the next packet to be loaded into
51601 + * the non-periodic Tx FIFO.
51602 + */
51603 +int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
51604 +{
51605 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51606 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
51607 +       dwc_otg_dev_in_ep_regs_t *ep_regs;
51608 +       gnptxsts_data_t txstatus = {.d32 = 0 };
51609 +       gintsts_data_t gintsts;
51610 +
51611 +       int epnum = 0;
51612 +       dwc_otg_pcd_ep_t *ep = 0;
51613 +       uint32_t len = 0;
51614 +       int dwords;
51615 +
51616 +       /* Get the epnum from the IN Token Learning Queue. */
51617 +       epnum = get_ep_of_last_in_token(core_if);
51618 +       ep = get_in_ep(pcd, epnum);
51619 +
51620 +       DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
51621 +
51622 +       ep_regs = core_if->dev_if->in_ep_regs[epnum];
51623 +
51624 +       len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
51625 +       if (len > ep->dwc_ep.maxpacket) {
51626 +               len = ep->dwc_ep.maxpacket;
51627 +       }
51628 +       dwords = (len + 3) / 4;
51629 +
51630 +       /* While there is space in the queue and space in the FIFO and
51631 +        * More data to tranfer, Write packets to the Tx FIFO */
51632 +       txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
51633 +       DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
51634 +
51635 +       while (txstatus.b.nptxqspcavail > 0 &&
51636 +              txstatus.b.nptxfspcavail > dwords &&
51637 +              ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
51638 +               /* Write the FIFO */
51639 +               dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
51640 +               len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
51641 +
51642 +               if (len > ep->dwc_ep.maxpacket) {
51643 +                       len = ep->dwc_ep.maxpacket;
51644 +               }
51645 +
51646 +               dwords = (len + 3) / 4;
51647 +               txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
51648 +               DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
51649 +       }
51650 +
51651 +       DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
51652 +                   DWC_READ_REG32(&global_regs->gnptxsts));
51653 +
51654 +       /* Clear interrupt */
51655 +       gintsts.d32 = 0;
51656 +       gintsts.b.nptxfempty = 1;
51657 +       DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
51658 +
51659 +       return 1;
51660 +}
51661 +
51662 +/**
51663 + * This function is called when dedicated Tx FIFO Empty interrupt occurs.
51664 + * The active request is checked for the next packet to be loaded into
51665 + * apropriate Tx FIFO.
51666 + */
51667 +static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
51668 +{
51669 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51670 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
51671 +       dwc_otg_dev_in_ep_regs_t *ep_regs;
51672 +       dtxfsts_data_t txstatus = {.d32 = 0 };
51673 +       dwc_otg_pcd_ep_t *ep = 0;
51674 +       uint32_t len = 0;
51675 +       int dwords;
51676 +
51677 +       ep = get_in_ep(pcd, epnum);
51678 +
51679 +       DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
51680 +
51681 +       ep_regs = core_if->dev_if->in_ep_regs[epnum];
51682 +
51683 +       len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
51684 +
51685 +       if (len > ep->dwc_ep.maxpacket) {
51686 +               len = ep->dwc_ep.maxpacket;
51687 +       }
51688 +
51689 +       dwords = (len + 3) / 4;
51690 +
51691 +       /* While there is space in the queue and space in the FIFO and
51692 +        * More data to tranfer, Write packets to the Tx FIFO */
51693 +       txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
51694 +       DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
51695 +
51696 +       while (txstatus.b.txfspcavail > dwords &&
51697 +              ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
51698 +              ep->dwc_ep.xfer_len != 0) {
51699 +               /* Write the FIFO */
51700 +               dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
51701 +
51702 +               len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
51703 +               if (len > ep->dwc_ep.maxpacket) {
51704 +                       len = ep->dwc_ep.maxpacket;
51705 +               }
51706 +
51707 +               dwords = (len + 3) / 4;
51708 +               txstatus.d32 =
51709 +                   DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
51710 +               DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
51711 +                           txstatus.d32);
51712 +       }
51713 +
51714 +       DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
51715 +                   DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
51716 +
51717 +       return 1;
51718 +}
51719 +
51720 +/**
51721 + * This function is called when the Device is disconnected. It stops
51722 + * any active requests and informs the Gadget driver of the
51723 + * disconnect.
51724 + */
51725 +void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
51726 +{
51727 +       int i, num_in_eps, num_out_eps;
51728 +       dwc_otg_pcd_ep_t *ep;
51729 +
51730 +       gintmsk_data_t intr_mask = {.d32 = 0 };
51731 +
51732 +       DWC_SPINLOCK(pcd->lock);
51733 +
51734 +       num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
51735 +       num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
51736 +
51737 +       DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
51738 +       /* don't disconnect drivers more than once */
51739 +       if (pcd->ep0state == EP0_DISCONNECT) {
51740 +               DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
51741 +               DWC_SPINUNLOCK(pcd->lock);
51742 +               return;
51743 +       }
51744 +       pcd->ep0state = EP0_DISCONNECT;
51745 +
51746 +       /* Reset the OTG state. */
51747 +       dwc_otg_pcd_update_otg(pcd, 1);
51748 +
51749 +       /* Disable the NP Tx Fifo Empty Interrupt. */
51750 +       intr_mask.b.nptxfempty = 1;
51751 +       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
51752 +                        intr_mask.d32, 0);
51753 +
51754 +       /* Flush the FIFOs */
51755 +       /**@todo NGS Flush Periodic FIFOs */
51756 +       dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
51757 +       dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
51758 +
51759 +       /* prevent new request submissions, kill any outstanding requests  */
51760 +       ep = &pcd->ep0;
51761 +       dwc_otg_request_nuke(ep);
51762 +       /* prevent new request submissions, kill any outstanding requests  */
51763 +       for (i = 0; i < num_in_eps; i++) {
51764 +               dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
51765 +               dwc_otg_request_nuke(ep);
51766 +       }
51767 +       /* prevent new request submissions, kill any outstanding requests  */
51768 +       for (i = 0; i < num_out_eps; i++) {
51769 +               dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
51770 +               dwc_otg_request_nuke(ep);
51771 +       }
51772 +
51773 +       /* report disconnect; the driver is already quiesced */
51774 +       if (pcd->fops->disconnect) {
51775 +               DWC_SPINUNLOCK(pcd->lock);
51776 +               pcd->fops->disconnect(pcd);
51777 +               DWC_SPINLOCK(pcd->lock);
51778 +       }
51779 +       DWC_SPINUNLOCK(pcd->lock);
51780 +}
51781 +
51782 +/**
51783 + * This interrupt indicates that ...
51784 + */
51785 +int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
51786 +{
51787 +       gintmsk_data_t intr_mask = {.d32 = 0 };
51788 +       gintsts_data_t gintsts;
51789 +
51790 +       DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
51791 +       intr_mask.b.i2cintr = 1;
51792 +       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
51793 +                        intr_mask.d32, 0);
51794 +
51795 +       /* Clear interrupt */
51796 +       gintsts.d32 = 0;
51797 +       gintsts.b.i2cintr = 1;
51798 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
51799 +                       gintsts.d32);
51800 +       return 1;
51801 +}
51802 +
51803 +/**
51804 + * This interrupt indicates that ...
51805 + */
51806 +int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
51807 +{
51808 +       gintsts_data_t gintsts;
51809 +#if defined(VERBOSE)
51810 +       DWC_PRINTF("Early Suspend Detected\n");
51811 +#endif
51812 +
51813 +       /* Clear interrupt */
51814 +       gintsts.d32 = 0;
51815 +       gintsts.b.erlysuspend = 1;
51816 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
51817 +                       gintsts.d32);
51818 +       return 1;
51819 +}
51820 +
51821 +/**
51822 + * This function configures EPO to receive SETUP packets.
51823 + *
51824 + * @todo NGS: Update the comments from the HW FS.
51825 + *
51826 + *     -# Program the following fields in the endpoint specific registers
51827 + *     for Control OUT EP 0, in order to receive a setup packet
51828 + *     - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
51829 + *       setup packets)
51830 + *     - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
51831 + *       to back setup packets)
51832 + *             - In DMA mode, DOEPDMA0 Register with a memory address to
51833 + *               store any setup packets received
51834 + *
51835 + * @param core_if Programming view of DWC_otg controller.
51836 + * @param pcd    Programming view of the PCD.
51837 + */
51838 +static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
51839 +                                dwc_otg_pcd_t * pcd)
51840 +{
51841 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
51842 +       deptsiz0_data_t doeptsize0 = {.d32 = 0 };
51843 +       dwc_otg_dev_dma_desc_t *dma_desc;
51844 +       depctl_data_t doepctl = {.d32 = 0 };
51845 +
51846 +#ifdef VERBOSE
51847 +       DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
51848 +                   DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
51849 +#endif
51850 +       if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
51851 +               doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
51852 +               if (doepctl.b.epena) {
51853 +                       return;
51854 +               }
51855 +       }
51856 +
51857 +       doeptsize0.b.supcnt = 3;
51858 +       doeptsize0.b.pktcnt = 1;
51859 +       doeptsize0.b.xfersize = 8 * 3;
51860 +
51861 +       if (core_if->dma_enable) {
51862 +               if (!core_if->dma_desc_enable) {
51863 +                       /** put here as for Hermes mode deptisz register should not be written */
51864 +                       DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
51865 +                                       doeptsize0.d32);
51866 +
51867 +                       /** @todo dma needs to handle multiple setup packets (up to 3) */
51868 +                       DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
51869 +                                       pcd->setup_pkt_dma_handle);
51870 +               } else {
51871 +                       dev_if->setup_desc_index =
51872 +                           (dev_if->setup_desc_index + 1) & 1;
51873 +                       dma_desc =
51874 +                           dev_if->setup_desc_addr[dev_if->setup_desc_index];
51875 +
51876 +                       /** DMA Descriptor Setup */
51877 +                       dma_desc->status.b.bs = BS_HOST_BUSY;
51878 +                       if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
51879 +                               dma_desc->status.b.sr = 0;
51880 +                               dma_desc->status.b.mtrf = 0;
51881 +                       }
51882 +                       dma_desc->status.b.l = 1;
51883 +                       dma_desc->status.b.ioc = 1;
51884 +                       dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
51885 +                       dma_desc->buf = pcd->setup_pkt_dma_handle;
51886 +                       dma_desc->status.b.sts = 0;
51887 +                       dma_desc->status.b.bs = BS_HOST_READY;
51888 +
51889 +                       /** DOEPDMA0 Register write */
51890 +                       DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
51891 +                                       dev_if->dma_setup_desc_addr
51892 +                                       [dev_if->setup_desc_index]);
51893 +               }
51894 +
51895 +       } else {
51896 +               /** put here as for Hermes mode deptisz register should not be written */
51897 +               DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
51898 +                               doeptsize0.d32);
51899 +       }
51900 +
51901 +       /** DOEPCTL0 Register write cnak will be set after setup interrupt */
51902 +       doepctl.d32 = 0;
51903 +       doepctl.b.epena = 1;
51904 +       if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
51905 +       doepctl.b.cnak = 1;
51906 +       DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
51907 +       } else {
51908 +               DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32);
51909 +       }
51910 +
51911 +#ifdef VERBOSE
51912 +       DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
51913 +                   DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
51914 +       DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
51915 +                   DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
51916 +#endif
51917 +}
51918 +
51919 +/**
51920 + * This interrupt occurs when a USB Reset is detected. When the USB
51921 + * Reset Interrupt occurs the device state is set to DEFAULT and the
51922 + * EP0 state is set to IDLE.
51923 + *     -#      Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
51924 + *     -#      Unmask the following interrupt bits
51925 + *             - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
51926 + *     - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
51927 + *     - DOEPMSK.SETUP = 1
51928 + *     - DOEPMSK.XferCompl = 1
51929 + *     - DIEPMSK.XferCompl = 1
51930 + *     - DIEPMSK.TimeOut = 1
51931 + *     -# Program the following fields in the endpoint specific registers
51932 + *     for Control OUT EP 0, in order to receive a setup packet
51933 + *     - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back
51934 + *       setup packets)
51935 + *     - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back
51936 + *       to back setup packets)
51937 + *             - In DMA mode, DOEPDMA0 Register with a memory address to
51938 + *               store any setup packets received
51939 + * At this point, all the required initialization, except for enabling
51940 + * the control 0 OUT endpoint is done, for receiving SETUP packets.
51941 + */
51942 +int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
51943 +{
51944 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
51945 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
51946 +       depctl_data_t doepctl = {.d32 = 0 };
51947 +       depctl_data_t diepctl = {.d32 = 0 };
51948 +       daint_data_t daintmsk = {.d32 = 0 };
51949 +       doepmsk_data_t doepmsk = {.d32 = 0 };
51950 +       diepmsk_data_t diepmsk = {.d32 = 0 };
51951 +       dcfg_data_t dcfg = {.d32 = 0 };
51952 +       grstctl_t resetctl = {.d32 = 0 };
51953 +       dctl_data_t dctl = {.d32 = 0 };
51954 +       int i = 0;
51955 +       gintsts_data_t gintsts;
51956 +       pcgcctl_data_t power = {.d32 = 0 };
51957 +
51958 +       power.d32 = DWC_READ_REG32(core_if->pcgcctl);
51959 +       if (power.b.stoppclk) {
51960 +               power.d32 = 0;
51961 +               power.b.stoppclk = 1;
51962 +               DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
51963 +
51964 +               power.b.pwrclmp = 1;
51965 +               DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
51966 +
51967 +               power.b.rstpdwnmodule = 1;
51968 +               DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
51969 +       }
51970 +
51971 +       core_if->lx_state = DWC_OTG_L0;
51972 +
51973 +       DWC_PRINTF("USB RESET\n");
51974 +#ifdef DWC_EN_ISOC
51975 +       for (i = 1; i < 16; ++i) {
51976 +               dwc_otg_pcd_ep_t *ep;
51977 +               dwc_ep_t *dwc_ep;
51978 +               ep = get_in_ep(pcd, i);
51979 +               if (ep != 0) {
51980 +                       dwc_ep = &ep->dwc_ep;
51981 +                       dwc_ep->next_frame = 0xffffffff;
51982 +               }
51983 +       }
51984 +#endif /* DWC_EN_ISOC */
51985 +
51986 +       /* reset the HNP settings */
51987 +       dwc_otg_pcd_update_otg(pcd, 1);
51988 +
51989 +       /* Clear the Remote Wakeup Signalling */
51990 +       dctl.b.rmtwkupsig = 1;
51991 +       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
51992 +
51993 +       /* Set NAK for all OUT EPs */
51994 +       doepctl.b.snak = 1;
51995 +       for (i = 0; i <= dev_if->num_out_eps; i++) {
51996 +               DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
51997 +       }
51998 +
51999 +       /* Flush the NP Tx FIFO */
52000 +       dwc_otg_flush_tx_fifo(core_if, 0x10);
52001 +       /* Flush the Learning Queue */
52002 +       resetctl.b.intknqflsh = 1;
52003 +       DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
52004 +
52005 +       if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
52006 +               core_if->start_predict = 0;
52007 +               for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
52008 +                       core_if->nextep_seq[i] = 0xff;  // 0xff - EP not active
52009 +               }
52010 +               core_if->nextep_seq[0] = 0;
52011 +               core_if->first_in_nextep_seq = 0;
52012 +               diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
52013 +               diepctl.b.nextep = 0;
52014 +               DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
52015 +
52016 +               /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
52017 +               dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
52018 +               dcfg.b.epmscnt = 2;
52019 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
52020 +
52021 +               DWC_DEBUGPL(DBG_PCDV,
52022 +                           "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
52023 +                       __func__, core_if->first_in_nextep_seq);
52024 +               for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
52025 +                       DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
52026 +               }
52027 +       }
52028 +
52029 +       if (core_if->multiproc_int_enable) {
52030 +               daintmsk.b.inep0 = 1;
52031 +               daintmsk.b.outep0 = 1;
52032 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
52033 +                               daintmsk.d32);
52034 +
52035 +               doepmsk.b.setup = 1;
52036 +               doepmsk.b.xfercompl = 1;
52037 +               doepmsk.b.ahberr = 1;
52038 +               doepmsk.b.epdisabled = 1;
52039 +
52040 +               if ((core_if->dma_desc_enable) ||
52041 +                   (core_if->dma_enable
52042 +                    && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
52043 +                       doepmsk.b.stsphsercvd = 1;
52044 +               }
52045 +               if (core_if->dma_desc_enable)
52046 +                       doepmsk.b.bna = 1;
52047 +/*
52048 +               doepmsk.b.babble = 1;
52049 +               doepmsk.b.nyet = 1;
52050 +
52051 +               if (core_if->dma_enable) {
52052 +                       doepmsk.b.nak = 1;
52053 +               }
52054 +*/
52055 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
52056 +                               doepmsk.d32);
52057 +
52058 +               diepmsk.b.xfercompl = 1;
52059 +               diepmsk.b.timeout = 1;
52060 +               diepmsk.b.epdisabled = 1;
52061 +               diepmsk.b.ahberr = 1;
52062 +               diepmsk.b.intknepmis = 1;
52063 +               if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
52064 +                       diepmsk.b.intknepmis = 0;
52065 +
52066 +/*             if (core_if->dma_desc_enable) {
52067 +                       diepmsk.b.bna = 1;
52068 +               }
52069 +*/
52070 +/*
52071 +               if (core_if->dma_enable) {
52072 +                       diepmsk.b.nak = 1;
52073 +               }
52074 +*/
52075 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
52076 +                               diepmsk.d32);
52077 +       } else {
52078 +               daintmsk.b.inep0 = 1;
52079 +               daintmsk.b.outep0 = 1;
52080 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
52081 +                               daintmsk.d32);
52082 +
52083 +               doepmsk.b.setup = 1;
52084 +               doepmsk.b.xfercompl = 1;
52085 +               doepmsk.b.ahberr = 1;
52086 +               doepmsk.b.epdisabled = 1;
52087 +
52088 +               if ((core_if->dma_desc_enable) ||
52089 +                   (core_if->dma_enable
52090 +                    && core_if->snpsid >= OTG_CORE_REV_3_00a)) {
52091 +                       doepmsk.b.stsphsercvd = 1;
52092 +               }
52093 +               if (core_if->dma_desc_enable)
52094 +                       doepmsk.b.bna = 1;
52095 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
52096 +
52097 +               diepmsk.b.xfercompl = 1;
52098 +               diepmsk.b.timeout = 1;
52099 +               diepmsk.b.epdisabled = 1;
52100 +               diepmsk.b.ahberr = 1;
52101 +               if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
52102 +                       diepmsk.b.intknepmis = 0;
52103 +/*
52104 +               if (core_if->dma_desc_enable) {
52105 +                       diepmsk.b.bna = 1;
52106 +               }
52107 +*/
52108 +
52109 +               DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
52110 +       }
52111 +
52112 +       /* Reset Device Address */
52113 +       dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
52114 +       dcfg.b.devaddr = 0;
52115 +       DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
52116 +
52117 +       /* setup EP0 to receive SETUP packets */
52118 +       if (core_if->snpsid <= OTG_CORE_REV_2_94a)
52119 +               ep0_out_start(core_if, pcd);
52120 +
52121 +       /* Clear interrupt */
52122 +       gintsts.d32 = 0;
52123 +       gintsts.b.usbreset = 1;
52124 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52125 +
52126 +       return 1;
52127 +}
52128 +
52129 +/**
52130 + * Get the device speed from the device status register and convert it
52131 + * to USB speed constant.
52132 + *
52133 + * @param core_if Programming view of DWC_otg controller.
52134 + */
52135 +static int get_device_speed(dwc_otg_core_if_t * core_if)
52136 +{
52137 +       dsts_data_t dsts;
52138 +       int speed = 0;
52139 +       dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
52140 +
52141 +       switch (dsts.b.enumspd) {
52142 +       case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
52143 +               speed = USB_SPEED_HIGH;
52144 +               break;
52145 +       case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
52146 +       case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
52147 +               speed = USB_SPEED_FULL;
52148 +               break;
52149 +
52150 +       case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
52151 +               speed = USB_SPEED_LOW;
52152 +               break;
52153 +       }
52154 +
52155 +       return speed;
52156 +}
52157 +
52158 +/**
52159 + * Read the device status register and set the device speed in the
52160 + * data structure.
52161 + * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate.
52162 + */
52163 +int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
52164 +{
52165 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52166 +       gintsts_data_t gintsts;
52167 +       gusbcfg_data_t gusbcfg;
52168 +       dwc_otg_core_global_regs_t *global_regs =
52169 +           GET_CORE_IF(pcd)->core_global_regs;
52170 +       uint8_t utmi16b, utmi8b;
52171 +       int speed;
52172 +       DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
52173 +
52174 +       if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
52175 +               utmi16b = 6;    //vahrama old value was 6;
52176 +               utmi8b = 9;
52177 +       } else {
52178 +               utmi16b = 4;
52179 +               utmi8b = 8;
52180 +       }
52181 +       dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
52182 +       if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) {
52183 +               ep0_out_start(GET_CORE_IF(pcd), pcd);
52184 +       }
52185 +
52186 +#ifdef DEBUG_EP0
52187 +       print_ep0_state(pcd);
52188 +#endif
52189 +
52190 +       if (pcd->ep0state == EP0_DISCONNECT) {
52191 +               pcd->ep0state = EP0_IDLE;
52192 +       } else if (pcd->ep0state == EP0_STALL) {
52193 +               pcd->ep0state = EP0_IDLE;
52194 +       }
52195 +
52196 +       pcd->ep0state = EP0_IDLE;
52197 +
52198 +       ep0->stopped = 0;
52199 +
52200 +       speed = get_device_speed(GET_CORE_IF(pcd));
52201 +       pcd->fops->connect(pcd, speed);
52202 +
52203 +       /* Set USB turnaround time based on device speed and PHY interface. */
52204 +       gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
52205 +       if (speed == USB_SPEED_HIGH) {
52206 +               if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52207 +                   DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
52208 +                       /* ULPI interface */
52209 +                       gusbcfg.b.usbtrdtim = 9;
52210 +               }
52211 +               if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52212 +                   DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
52213 +                       /* UTMI+ interface */
52214 +                       if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
52215 +                               gusbcfg.b.usbtrdtim = utmi8b;
52216 +                       } else if (GET_CORE_IF(pcd)->hwcfg4.
52217 +                                  b.utmi_phy_data_width == 1) {
52218 +                               gusbcfg.b.usbtrdtim = utmi16b;
52219 +                       } else if (GET_CORE_IF(pcd)->
52220 +                                  core_params->phy_utmi_width == 8) {
52221 +                               gusbcfg.b.usbtrdtim = utmi8b;
52222 +                       } else {
52223 +                               gusbcfg.b.usbtrdtim = utmi16b;
52224 +                       }
52225 +               }
52226 +               if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
52227 +                   DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
52228 +                       /* UTMI+  OR  ULPI interface */
52229 +                       if (gusbcfg.b.ulpi_utmi_sel == 1) {
52230 +                               /* ULPI interface */
52231 +                               gusbcfg.b.usbtrdtim = 9;
52232 +                       } else {
52233 +                               /* UTMI+ interface */
52234 +                               if (GET_CORE_IF(pcd)->
52235 +                                   core_params->phy_utmi_width == 16) {
52236 +                                       gusbcfg.b.usbtrdtim = utmi16b;
52237 +                               } else {
52238 +                                       gusbcfg.b.usbtrdtim = utmi8b;
52239 +                               }
52240 +                       }
52241 +               }
52242 +       } else {
52243 +               /* Full or low speed */
52244 +               gusbcfg.b.usbtrdtim = 9;
52245 +       }
52246 +       DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
52247 +
52248 +       /* Clear interrupt */
52249 +       gintsts.d32 = 0;
52250 +       gintsts.b.enumdone = 1;
52251 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52252 +                       gintsts.d32);
52253 +       return 1;
52254 +}
52255 +
52256 +/**
52257 + * This interrupt indicates that the ISO OUT Packet was dropped due to
52258 + * Rx FIFO full or Rx Status Queue Full.  If this interrupt occurs
52259 + * read all the data from the Rx FIFO.
52260 + */
52261 +int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
52262 +{
52263 +       gintmsk_data_t intr_mask = {.d32 = 0 };
52264 +       gintsts_data_t gintsts;
52265 +
52266 +       DWC_WARN("INTERRUPT Handler not implemented for %s\n",
52267 +                "ISOC Out Dropped");
52268 +
52269 +       intr_mask.b.isooutdrop = 1;
52270 +       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52271 +                        intr_mask.d32, 0);
52272 +
52273 +       /* Clear interrupt */
52274 +       gintsts.d32 = 0;
52275 +       gintsts.b.isooutdrop = 1;
52276 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52277 +                       gintsts.d32);
52278 +
52279 +       return 1;
52280 +}
52281 +
52282 +/**
52283 + * This interrupt indicates the end of the portion of the micro-frame
52284 + * for periodic transactions.  If there is a periodic transaction for
52285 + * the next frame, load the packets into the EP periodic Tx FIFO.
52286 + */
52287 +int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
52288 +{
52289 +       gintmsk_data_t intr_mask = {.d32 = 0 };
52290 +       gintsts_data_t gintsts;
52291 +       DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
52292 +
52293 +       intr_mask.b.eopframe = 1;
52294 +       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
52295 +                        intr_mask.d32, 0);
52296 +
52297 +       /* Clear interrupt */
52298 +       gintsts.d32 = 0;
52299 +       gintsts.b.eopframe = 1;
52300 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
52301 +                       gintsts.d32);
52302 +
52303 +       return 1;
52304 +}
52305 +
52306 +/**
52307 + * This interrupt indicates that EP of the packet on the top of the
52308 + * non-periodic Tx FIFO does not match EP of the IN Token received.
52309 + *
52310 + * The "Device IN Token Queue" Registers are read to determine the
52311 + * order the IN Tokens have been received. The non-periodic Tx FIFO
52312 + * is flushed, so it can be reloaded in the order seen in the IN Token
52313 + * Queue.
52314 + */
52315 +int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
52316 +{
52317 +       gintsts_data_t gintsts;
52318 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52319 +       dctl_data_t dctl;
52320 +       gintmsk_data_t intr_mask = {.d32 = 0 };
52321 +
52322 +       if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
52323 +               core_if->start_predict = 1;
52324 +
52325 +               DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
52326 +
52327 +               gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
52328 +               if (!gintsts.b.ginnakeff) {
52329 +                       /* Disable EP Mismatch interrupt */
52330 +                       intr_mask.d32 = 0;
52331 +                       intr_mask.b.epmismatch = 1;
52332 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
52333 +                       /* Enable the Global IN NAK Effective Interrupt */
52334 +                       intr_mask.d32 = 0;
52335 +                       intr_mask.b.ginnakeff = 1;
52336 +                       DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
52337 +                       /* Set the global non-periodic IN NAK handshake */
52338 +                       dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
52339 +                       dctl.b.sgnpinnak = 1;
52340 +                       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
52341 +               } else {
52342 +                       DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
52343 +               }
52344 +               /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
52345 +                * handler after Global IN NAK Effective interrupt will be asserted */
52346 +       }
52347 +       /* Clear interrupt */
52348 +       gintsts.d32 = 0;
52349 +       gintsts.b.epmismatch = 1;
52350 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52351 +
52352 +       return 1;
52353 +}
52354 +
52355 +/**
52356 + * This interrupt is valid only in DMA mode. This interrupt indicates that the
52357 + * core has stopped fetching data for IN endpoints due to the unavailability of
52358 + * TxFIFO space or Request Queue space. This interrupt is used by the
52359 + * application for an endpoint mismatch algorithm.
52360 + *
52361 + * @param pcd The PCD
52362 + */
52363 +int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
52364 +{
52365 +       gintsts_data_t gintsts;
52366 +       gintmsk_data_t gintmsk_data;
52367 +       dctl_data_t dctl;
52368 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52369 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
52370 +
52371 +       /* Clear the global non-periodic IN NAK handshake */
52372 +       dctl.d32 = 0;
52373 +       dctl.b.cgnpinnak = 1;
52374 +       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
52375 +
52376 +       /* Mask GINTSTS.FETSUSP interrupt */
52377 +       gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
52378 +       gintmsk_data.b.fetsusp = 0;
52379 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
52380 +
52381 +       /* Clear interrupt */
52382 +       gintsts.d32 = 0;
52383 +       gintsts.b.fetsusp = 1;
52384 +       DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
52385 +
52386 +       return 1;
52387 +}
52388 +/**
52389 + * This funcion stalls EP0.
52390 + */
52391 +static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
52392 +{
52393 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52394 +       usb_device_request_t *ctrl = &pcd->setup_pkt->req;
52395 +       DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
52396 +                ctrl->bmRequestType, ctrl->bRequest, err_val);
52397 +
52398 +       ep0->dwc_ep.is_in = 1;
52399 +       dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
52400 +       pcd->ep0.stopped = 1;
52401 +       pcd->ep0state = EP0_IDLE;
52402 +       ep0_out_start(GET_CORE_IF(pcd), pcd);
52403 +}
52404 +
52405 +/**
52406 + * This functions delegates the setup command to the gadget driver.
52407 + */
52408 +static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
52409 +                                  usb_device_request_t * ctrl)
52410 +{
52411 +       int ret = 0;
52412 +       DWC_SPINUNLOCK(pcd->lock);
52413 +       ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
52414 +       DWC_SPINLOCK(pcd->lock);
52415 +       if (ret < 0) {
52416 +               ep0_do_stall(pcd, ret);
52417 +       }
52418 +
52419 +       /** @todo This is a g_file_storage gadget driver specific
52420 +        * workaround: a DELAYED_STATUS result from the fsg_setup
52421 +        * routine will result in the gadget queueing a EP0 IN status
52422 +        * phase for a two-stage control transfer. Exactly the same as
52423 +        * a SET_CONFIGURATION/SET_INTERFACE except that this is a class
52424 +        * specific request.  Need a generic way to know when the gadget
52425 +        * driver will queue the status phase. Can we assume when we
52426 +        * call the gadget driver setup() function that it will always
52427 +        * queue and require the following flag? Need to look into
52428 +        * this.
52429 +        */
52430 +
52431 +       if (ret == 256 + 999) {
52432 +               pcd->request_config = 1;
52433 +       }
52434 +}
52435 +
52436 +#ifdef DWC_UTE_CFI
52437 +/**
52438 + * This functions delegates the CFI setup commands to the gadget driver.
52439 + * This function will return a negative value to indicate a failure.
52440 + */
52441 +static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
52442 +                                  struct cfi_usb_ctrlrequest *ctrl_req)
52443 +{
52444 +       int ret = 0;
52445 +
52446 +       if (pcd->fops && pcd->fops->cfi_setup) {
52447 +               DWC_SPINUNLOCK(pcd->lock);
52448 +               ret = pcd->fops->cfi_setup(pcd, ctrl_req);
52449 +               DWC_SPINLOCK(pcd->lock);
52450 +               if (ret < 0) {
52451 +                       ep0_do_stall(pcd, ret);
52452 +                       return ret;
52453 +               }
52454 +       }
52455 +
52456 +       return ret;
52457 +}
52458 +#endif
52459 +
52460 +/**
52461 + * This function starts the Zero-Length Packet for the IN status phase
52462 + * of a 2 stage control transfer.
52463 + */
52464 +static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
52465 +{
52466 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52467 +       if (pcd->ep0state == EP0_STALL) {
52468 +               return;
52469 +       }
52470 +
52471 +       pcd->ep0state = EP0_IN_STATUS_PHASE;
52472 +
52473 +       /* Prepare for more SETUP Packets */
52474 +       DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
52475 +       if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a)
52476 +           && (pcd->core_if->dma_desc_enable)
52477 +           && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) {
52478 +               DWC_DEBUGPL(DBG_PCDV,
52479 +                           "Data terminated wait next packet in out_desc_addr\n");
52480 +               pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr);
52481 +               pcd->data_terminated = 1;
52482 +       }
52483 +       ep0->dwc_ep.xfer_len = 0;
52484 +       ep0->dwc_ep.xfer_count = 0;
52485 +       ep0->dwc_ep.is_in = 1;
52486 +       ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
52487 +       dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
52488 +
52489 +       /* Prepare for more SETUP Packets */
52490 +       //ep0_out_start(GET_CORE_IF(pcd), pcd);
52491 +}
52492 +
52493 +/**
52494 + * This function starts the Zero-Length Packet for the OUT status phase
52495 + * of a 2 stage control transfer.
52496 + */
52497 +static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
52498 +{
52499 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52500 +       if (pcd->ep0state == EP0_STALL) {
52501 +               DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
52502 +               return;
52503 +       }
52504 +       pcd->ep0state = EP0_OUT_STATUS_PHASE;
52505 +
52506 +       DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
52507 +       ep0->dwc_ep.xfer_len = 0;
52508 +       ep0->dwc_ep.xfer_count = 0;
52509 +       ep0->dwc_ep.is_in = 0;
52510 +       ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
52511 +       dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
52512 +
52513 +       /* Prepare for more SETUP Packets */
52514 +       if (GET_CORE_IF(pcd)->dma_enable == 0) {
52515 +               ep0_out_start(GET_CORE_IF(pcd), pcd);
52516 +       }
52517 +}
52518 +
52519 +/**
52520 + * Clear the EP halt (STALL) and if pending requests start the
52521 + * transfer.
52522 + */
52523 +static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
52524 +{
52525 +       if (ep->dwc_ep.stall_clear_flag == 0)
52526 +               dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
52527 +
52528 +       /* Reactive the EP */
52529 +       dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
52530 +       if (ep->stopped) {
52531 +               ep->stopped = 0;
52532 +               /* If there is a request in the EP queue start it */
52533 +
52534 +               /** @todo FIXME: this causes an EP mismatch in DMA mode.
52535 +                * epmismatch not yet implemented. */
52536 +
52537 +               /*
52538 +                * Above fixme is solved by implmenting a tasklet to call the
52539 +                * start_next_request(), outside of interrupt context at some
52540 +                * time after the current time, after a clear-halt setup packet.
52541 +                * Still need to implement ep mismatch in the future if a gadget
52542 +                * ever uses more than one endpoint at once
52543 +                */
52544 +               ep->queue_sof = 1;
52545 +               DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
52546 +       }
52547 +       /* Start Control Status Phase */
52548 +       do_setup_in_status_phase(pcd);
52549 +}
52550 +
52551 +/**
52552 + * This function is called when the SET_FEATURE TEST_MODE Setup packet
52553 + * is sent from the host.  The Device Control register is written with
52554 + * the Test Mode bits set to the specified Test Mode.  This is done as
52555 + * a tasklet so that the "Status" phase of the control transfer
52556 + * completes before transmitting the TEST packets.
52557 + *
52558 + * @todo This has not been tested since the tasklet struct was put
52559 + * into the PCD struct!
52560 + *
52561 + */
52562 +void do_test_mode(void *data)
52563 +{
52564 +       dctl_data_t dctl;
52565 +       dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
52566 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52567 +       int test_mode = pcd->test_mode;
52568 +
52569 +//        DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
52570 +
52571 +       dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
52572 +       switch (test_mode) {
52573 +       case 1:         // TEST_J
52574 +               dctl.b.tstctl = 1;
52575 +               break;
52576 +
52577 +       case 2:         // TEST_K
52578 +               dctl.b.tstctl = 2;
52579 +               break;
52580 +
52581 +       case 3:         // TEST_SE0_NAK
52582 +               dctl.b.tstctl = 3;
52583 +               break;
52584 +
52585 +       case 4:         // TEST_PACKET
52586 +               dctl.b.tstctl = 4;
52587 +               break;
52588 +
52589 +       case 5:         // TEST_FORCE_ENABLE
52590 +               dctl.b.tstctl = 5;
52591 +               break;
52592 +       }
52593 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
52594 +}
52595 +
52596 +/**
52597 + * This function process the GET_STATUS Setup Commands.
52598 + */
52599 +static inline void do_get_status(dwc_otg_pcd_t * pcd)
52600 +{
52601 +       usb_device_request_t ctrl = pcd->setup_pkt->req;
52602 +       dwc_otg_pcd_ep_t *ep;
52603 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52604 +       uint16_t *status = pcd->status_buf;
52605 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52606 +
52607 +#ifdef DEBUG_EP0
52608 +       DWC_DEBUGPL(DBG_PCD,
52609 +                   "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
52610 +                   ctrl.bmRequestType, ctrl.bRequest,
52611 +                   UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
52612 +                   UGETW(ctrl.wLength));
52613 +#endif
52614 +
52615 +       switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
52616 +       case UT_DEVICE:
52617 +               if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
52618 +                       DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
52619 +                       DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
52620 +                       DWC_PRINTF("OTG CAP - %d, %d\n",
52621 +                                  core_if->core_params->otg_cap,
52622 +                                               DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
52623 +                       if (core_if->otg_ver == 1
52624 +                           && core_if->core_params->otg_cap ==
52625 +                           DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
52626 +                               uint8_t *otgsts = (uint8_t*)pcd->status_buf;
52627 +                               *otgsts = (core_if->otg_sts & 0x1);
52628 +                               pcd->ep0_pending = 1;
52629 +                               ep0->dwc_ep.start_xfer_buff =
52630 +                                   (uint8_t *) otgsts;
52631 +                               ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
52632 +                               ep0->dwc_ep.dma_addr =
52633 +                                   pcd->status_buf_dma_handle;
52634 +                               ep0->dwc_ep.xfer_len = 1;
52635 +                               ep0->dwc_ep.xfer_count = 0;
52636 +                               ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
52637 +                               dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
52638 +                                                          &ep0->dwc_ep);
52639 +                               return;
52640 +                       } else {
52641 +                               ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52642 +                               return;
52643 +                       }
52644 +                       break;
52645 +               } else {
52646 +                       *status = 0x1;  /* Self powered */
52647 +                       *status |= pcd->remote_wakeup_enable << 1;
52648 +                       break;
52649 +               }
52650 +       case UT_INTERFACE:
52651 +               *status = 0;
52652 +               break;
52653 +
52654 +       case UT_ENDPOINT:
52655 +               ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
52656 +               if (ep == 0 || UGETW(ctrl.wLength) > 2) {
52657 +                       ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52658 +                       return;
52659 +               }
52660 +               /** @todo check for EP stall */
52661 +               *status = ep->stopped;
52662 +               break;
52663 +       }
52664 +       pcd->ep0_pending = 1;
52665 +       ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
52666 +       ep0->dwc_ep.xfer_buff = (uint8_t *) status;
52667 +       ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
52668 +       ep0->dwc_ep.xfer_len = 2;
52669 +       ep0->dwc_ep.xfer_count = 0;
52670 +       ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
52671 +       dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
52672 +}
52673 +
52674 +/**
52675 + * This function process the SET_FEATURE Setup Commands.
52676 + */
52677 +static inline void do_set_feature(dwc_otg_pcd_t * pcd)
52678 +{
52679 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52680 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
52681 +       usb_device_request_t ctrl = pcd->setup_pkt->req;
52682 +       dwc_otg_pcd_ep_t *ep = 0;
52683 +       int32_t otg_cap_param = core_if->core_params->otg_cap;
52684 +       gotgctl_data_t gotgctl = {.d32 = 0 };
52685 +
52686 +       DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
52687 +                   ctrl.bmRequestType, ctrl.bRequest,
52688 +                   UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
52689 +                   UGETW(ctrl.wLength));
52690 +       DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
52691 +
52692 +       switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
52693 +       case UT_DEVICE:
52694 +               switch (UGETW(ctrl.wValue)) {
52695 +               case UF_DEVICE_REMOTE_WAKEUP:
52696 +                       pcd->remote_wakeup_enable = 1;
52697 +                       break;
52698 +
52699 +               case UF_TEST_MODE:
52700 +                       /* Setup the Test Mode tasklet to do the Test
52701 +                        * Packet generation after the SETUP Status
52702 +                        * phase has completed. */
52703 +
52704 +                       /** @todo This has not been tested since the
52705 +                        * tasklet struct was put into the PCD
52706 +                        * struct! */
52707 +                       pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
52708 +                       DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
52709 +                       break;
52710 +
52711 +               case UF_DEVICE_B_HNP_ENABLE:
52712 +                       DWC_DEBUGPL(DBG_PCDV,
52713 +                                   "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
52714 +
52715 +                       /* dev may initiate HNP */
52716 +                       if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
52717 +                               pcd->b_hnp_enable = 1;
52718 +                               dwc_otg_pcd_update_otg(pcd, 0);
52719 +                               DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
52720 +                               /**@todo Is the gotgctl.devhnpen cleared
52721 +                                * by a USB Reset? */
52722 +                               gotgctl.b.devhnpen = 1;
52723 +                               gotgctl.b.hnpreq = 1;
52724 +                               DWC_WRITE_REG32(&global_regs->gotgctl,
52725 +                                               gotgctl.d32);
52726 +                       } else {
52727 +                               ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52728 +                               return;
52729 +                       }
52730 +                       break;
52731 +
52732 +               case UF_DEVICE_A_HNP_SUPPORT:
52733 +                       /* RH port supports HNP */
52734 +                       DWC_DEBUGPL(DBG_PCDV,
52735 +                                   "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
52736 +                       if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
52737 +                               pcd->a_hnp_support = 1;
52738 +                               dwc_otg_pcd_update_otg(pcd, 0);
52739 +                       } else {
52740 +                               ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52741 +                               return;
52742 +                       }
52743 +                       break;
52744 +
52745 +               case UF_DEVICE_A_ALT_HNP_SUPPORT:
52746 +                       /* other RH port does */
52747 +                       DWC_DEBUGPL(DBG_PCDV,
52748 +                                   "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
52749 +                       if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
52750 +                               pcd->a_alt_hnp_support = 1;
52751 +                               dwc_otg_pcd_update_otg(pcd, 0);
52752 +                       } else {
52753 +                               ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52754 +                               return;
52755 +                       }
52756 +                       break;
52757 +
52758 +               default:
52759 +                       ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52760 +                       return;
52761 +
52762 +               }
52763 +               do_setup_in_status_phase(pcd);
52764 +               break;
52765 +
52766 +       case UT_INTERFACE:
52767 +               do_gadget_setup(pcd, &ctrl);
52768 +               break;
52769 +
52770 +       case UT_ENDPOINT:
52771 +               if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
52772 +                       ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
52773 +                       if (ep == 0) {
52774 +                               ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52775 +                               return;
52776 +                       }
52777 +                       ep->stopped = 1;
52778 +                       dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
52779 +               }
52780 +               do_setup_in_status_phase(pcd);
52781 +               break;
52782 +       }
52783 +}
52784 +
52785 +/**
52786 + * This function process the CLEAR_FEATURE Setup Commands.
52787 + */
52788 +static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
52789 +{
52790 +       usb_device_request_t ctrl = pcd->setup_pkt->req;
52791 +       dwc_otg_pcd_ep_t *ep = 0;
52792 +
52793 +       DWC_DEBUGPL(DBG_PCD,
52794 +                   "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
52795 +                   ctrl.bmRequestType, ctrl.bRequest,
52796 +                   UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
52797 +                   UGETW(ctrl.wLength));
52798 +
52799 +       switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
52800 +       case UT_DEVICE:
52801 +               switch (UGETW(ctrl.wValue)) {
52802 +               case UF_DEVICE_REMOTE_WAKEUP:
52803 +                       pcd->remote_wakeup_enable = 0;
52804 +                       break;
52805 +
52806 +               case UF_TEST_MODE:
52807 +                       /** @todo Add CLEAR_FEATURE for TEST modes. */
52808 +                       break;
52809 +
52810 +               default:
52811 +                       ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52812 +                       return;
52813 +               }
52814 +               do_setup_in_status_phase(pcd);
52815 +               break;
52816 +
52817 +       case UT_ENDPOINT:
52818 +               ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
52819 +               if (ep == 0) {
52820 +                       ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
52821 +                       return;
52822 +               }
52823 +
52824 +               pcd_clear_halt(pcd, ep);
52825 +
52826 +               break;
52827 +       }
52828 +}
52829 +
52830 +/**
52831 + * This function process the SET_ADDRESS Setup Commands.
52832 + */
52833 +static inline void do_set_address(dwc_otg_pcd_t * pcd)
52834 +{
52835 +       dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
52836 +       usb_device_request_t ctrl = pcd->setup_pkt->req;
52837 +
52838 +       if (ctrl.bmRequestType == UT_DEVICE) {
52839 +               dcfg_data_t dcfg = {.d32 = 0 };
52840 +
52841 +#ifdef DEBUG_EP0
52842 +//                      DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
52843 +#endif
52844 +               dcfg.b.devaddr = UGETW(ctrl.wValue);
52845 +               DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
52846 +               do_setup_in_status_phase(pcd);
52847 +       }
52848 +}
52849 +
52850 +/**
52851 + *     This function processes SETUP commands. In Linux, the USB Command
52852 + *     processing is done in two places - the first being the PCD and the
52853 + *     second in the Gadget Driver (for example, the File-Backed Storage
52854 + *     Gadget Driver).
52855 + *
52856 + * <table>
52857 + * <tr><td>Command     </td><td>Driver </td><td>Description</td></tr>
52858 + *
52859 + * <tr><td>GET_STATUS </td><td>PCD </td><td>Command is processed as
52860 + * defined in chapter 9 of the USB 2.0 Specification chapter 9
52861 + * </td></tr>
52862 + *
52863 + * <tr><td>CLEAR_FEATURE </td><td>PCD </td><td>The Device and Endpoint
52864 + * requests are the ENDPOINT_HALT feature is procesed, all others the
52865 + * interface requests are ignored.</td></tr>
52866 + *
52867 + * <tr><td>SET_FEATURE </td><td>PCD </td><td>The Device and Endpoint
52868 + * requests are processed by the PCD.  Interface requests are passed
52869 + * to the Gadget Driver.</td></tr>
52870 + *
52871 + * <tr><td>SET_ADDRESS </td><td>PCD </td><td>Program the DCFG reg,
52872 + * with device address received </td></tr>
52873 + *
52874 + * <tr><td>GET_DESCRIPTOR </td><td>Gadget Driver </td><td>Return the
52875 + * requested descriptor</td></tr>
52876 + *
52877 + * <tr><td>SET_DESCRIPTOR </td><td>Gadget Driver </td><td>Optional -
52878 + * not implemented by any of the existing Gadget Drivers.</td></tr>
52879 + *
52880 + * <tr><td>SET_CONFIGURATION </td><td>Gadget Driver </td><td>Disable
52881 + * all EPs and enable EPs for new configuration.</td></tr>
52882 + *
52883 + * <tr><td>GET_CONFIGURATION </td><td>Gadget Driver </td><td>Return
52884 + * the current configuration</td></tr>
52885 + *
52886 + * <tr><td>SET_INTERFACE </td><td>Gadget Driver </td><td>Disable all
52887 + * EPs and enable EPs for new configuration.</td></tr>
52888 + *
52889 + * <tr><td>GET_INTERFACE </td><td>Gadget Driver </td><td>Return the
52890 + * current interface.</td></tr>
52891 + *
52892 + * <tr><td>SYNC_FRAME </td><td>PCD </td><td>Display debug
52893 + * message.</td></tr>
52894 + * </table>
52895 + *
52896 + * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are
52897 + * processed by pcd_setup. Calling the Function Driver's setup function from
52898 + * pcd_setup processes the gadget SETUP commands.
52899 + */
52900 +static inline void pcd_setup(dwc_otg_pcd_t * pcd)
52901 +{
52902 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
52903 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
52904 +       usb_device_request_t ctrl = pcd->setup_pkt->req;
52905 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
52906 +
52907 +       deptsiz0_data_t doeptsize0 = {.d32 = 0 };
52908 +
52909 +#ifdef DWC_UTE_CFI
52910 +       int retval = 0;
52911 +       struct cfi_usb_ctrlrequest cfi_req;
52912 +#endif
52913 +
52914 +       doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
52915 +
52916 +       /** In BDMA more then 1 setup packet is not supported till 3.00a */
52917 +       if (core_if->dma_enable && core_if->dma_desc_enable == 0
52918 +           && (doeptsize0.b.supcnt < 2)
52919 +           && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
52920 +               DWC_ERROR
52921 +                   ("\n\n-----------    CANNOT handle > 1 setup packet in DMA mode\n\n");
52922 +       }
52923 +       if ((core_if->snpsid >= OTG_CORE_REV_3_00a)
52924 +           && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) {
52925 +               ctrl =
52926 +                   (pcd->setup_pkt +
52927 +                    (3 - doeptsize0.b.supcnt - 1 +
52928 +                     ep0->dwc_ep.stp_rollover))->req;
52929 +       }
52930 +#ifdef DEBUG_EP0
52931 +       DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
52932 +                   ctrl.bmRequestType, ctrl.bRequest,
52933 +                   UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
52934 +                   UGETW(ctrl.wLength));
52935 +#endif
52936 +
52937 +       /* Clean up the request queue */
52938 +       dwc_otg_request_nuke(ep0);
52939 +       ep0->stopped = 0;
52940 +
52941 +       if (ctrl.bmRequestType & UE_DIR_IN) {
52942 +               ep0->dwc_ep.is_in = 1;
52943 +               pcd->ep0state = EP0_IN_DATA_PHASE;
52944 +       } else {
52945 +               ep0->dwc_ep.is_in = 0;
52946 +               pcd->ep0state = EP0_OUT_DATA_PHASE;
52947 +       }
52948 +
52949 +       if (UGETW(ctrl.wLength) == 0) {
52950 +               ep0->dwc_ep.is_in = 1;
52951 +               pcd->ep0state = EP0_IN_STATUS_PHASE;
52952 +       }
52953 +
52954 +       if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
52955 +
52956 +#ifdef DWC_UTE_CFI
52957 +               DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
52958 +
52959 +               //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n",
52960 +                               ctrl.bRequestType, ctrl.bRequest);
52961 +               if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
52962 +                       if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
52963 +                               retval = cfi_setup(pcd, &cfi_req);
52964 +                               if (retval < 0) {
52965 +                                       ep0_do_stall(pcd, retval);
52966 +                                       pcd->ep0_pending = 0;
52967 +                                       return;
52968 +                               }
52969 +
52970 +                               /* if need gadget setup then call it and check the retval */
52971 +                               if (pcd->cfi->need_gadget_att) {
52972 +                                       retval =
52973 +                                           cfi_gadget_setup(pcd,
52974 +                                                            &pcd->
52975 +                                                            cfi->ctrl_req);
52976 +                                       if (retval < 0) {
52977 +                                               pcd->ep0_pending = 0;
52978 +                                               return;
52979 +                                       }
52980 +                               }
52981 +
52982 +                               if (pcd->cfi->need_status_in_complete) {
52983 +                                       do_setup_in_status_phase(pcd);
52984 +                               }
52985 +                               return;
52986 +                       }
52987 +               }
52988 +#endif
52989 +
52990 +               /* handle non-standard (class/vendor) requests in the gadget driver */
52991 +               do_gadget_setup(pcd, &ctrl);
52992 +               return;
52993 +       }
52994 +
52995 +       /** @todo NGS: Handle bad setup packet? */
52996 +
52997 +///////////////////////////////////////////
52998 +//// --- Standard Request handling --- ////
52999 +
53000 +       switch (ctrl.bRequest) {
53001 +       case UR_GET_STATUS:
53002 +               do_get_status(pcd);
53003 +               break;
53004 +
53005 +       case UR_CLEAR_FEATURE:
53006 +               do_clear_feature(pcd);
53007 +               break;
53008 +
53009 +       case UR_SET_FEATURE:
53010 +               do_set_feature(pcd);
53011 +               break;
53012 +
53013 +       case UR_SET_ADDRESS:
53014 +               do_set_address(pcd);
53015 +               break;
53016 +
53017 +       case UR_SET_INTERFACE:
53018 +       case UR_SET_CONFIG:
53019 +//              _pcd->request_config = 1;       /* Configuration changed */
53020 +               do_gadget_setup(pcd, &ctrl);
53021 +               break;
53022 +
53023 +       case UR_SYNCH_FRAME:
53024 +               do_gadget_setup(pcd, &ctrl);
53025 +               break;
53026 +
53027 +       default:
53028 +               /* Call the Gadget Driver's setup functions */
53029 +               do_gadget_setup(pcd, &ctrl);
53030 +               break;
53031 +       }
53032 +}
53033 +
53034 +/**
53035 + * This function completes the ep0 control transfer.
53036 + */
53037 +static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
53038 +{
53039 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
53040 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
53041 +       dwc_otg_dev_in_ep_regs_t *in_ep_regs =
53042 +           dev_if->in_ep_regs[ep->dwc_ep.num];
53043 +#ifdef DEBUG_EP0
53044 +       dwc_otg_dev_out_ep_regs_t *out_ep_regs =
53045 +           dev_if->out_ep_regs[ep->dwc_ep.num];
53046 +#endif
53047 +       deptsiz0_data_t deptsiz;
53048 +       dev_dma_desc_sts_t desc_sts;
53049 +       dwc_otg_pcd_request_t *req;
53050 +       int is_last = 0;
53051 +       dwc_otg_pcd_t *pcd = ep->pcd;
53052 +
53053 +#ifdef DWC_UTE_CFI
53054 +       struct cfi_usb_ctrlrequest *ctrlreq;
53055 +       int retval = -DWC_E_NOT_SUPPORTED;
53056 +#endif
53057 +
53058 +        desc_sts.b.bytes = 0;
53059 +
53060 +       if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53061 +               if (ep->dwc_ep.is_in) {
53062 +#ifdef DEBUG_EP0
53063 +                       DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
53064 +#endif
53065 +                       do_setup_out_status_phase(pcd);
53066 +               } else {
53067 +#ifdef DEBUG_EP0
53068 +                       DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
53069 +#endif
53070 +
53071 +#ifdef DWC_UTE_CFI
53072 +                       ctrlreq = &pcd->cfi->ctrl_req;
53073 +
53074 +                       if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
53075 +                               if (ctrlreq->bRequest > 0xB0
53076 +                                   && ctrlreq->bRequest < 0xBF) {
53077 +
53078 +                                       /* Return if the PCD failed to handle the request */
53079 +                                       if ((retval =
53080 +                                            pcd->cfi->ops.
53081 +                                            ctrl_write_complete(pcd->cfi,
53082 +                                                                pcd)) < 0) {
53083 +                                               CFI_INFO
53084 +                                                   ("ERROR setting a new value in the PCD(%d)\n",
53085 +                                                    retval);
53086 +                                               ep0_do_stall(pcd, retval);
53087 +                                               pcd->ep0_pending = 0;
53088 +                                               return 0;
53089 +                                       }
53090 +
53091 +                                       /* If the gadget needs to be notified on the request */
53092 +                                       if (pcd->cfi->need_gadget_att == 1) {
53093 +                                               //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
53094 +                                               retval =
53095 +                                                   cfi_gadget_setup(pcd,
53096 +                                                                    &pcd->cfi->
53097 +                                                                    ctrl_req);
53098 +
53099 +                                               /* Return from the function if the gadget failed to process
53100 +                                                * the request properly - this should never happen !!!
53101 +                                                */
53102 +                                               if (retval < 0) {
53103 +                                                       CFI_INFO
53104 +                                                           ("ERROR setting a new value in the gadget(%d)\n",
53105 +                                                            retval);
53106 +                                                       pcd->ep0_pending = 0;
53107 +                                                       return 0;
53108 +                                               }
53109 +                                       }
53110 +
53111 +                                       CFI_INFO("%s: RETVAL=%d\n", __func__,
53112 +                                                retval);
53113 +                                       /* If we hit here then the PCD and the gadget has properly
53114 +                                        * handled the request - so send the ZLP IN to the host.
53115 +                                        */
53116 +                                       /* @todo: MAS - decide whether we need to start the setup
53117 +                                        * stage based on the need_setup value of the cfi object
53118 +                                        */
53119 +                                       do_setup_in_status_phase(pcd);
53120 +                                       pcd->ep0_pending = 0;
53121 +                                       return 1;
53122 +                               }
53123 +                       }
53124 +#endif
53125 +
53126 +                       do_setup_in_status_phase(pcd);
53127 +               }
53128 +               pcd->ep0_pending = 0;
53129 +               return 1;
53130 +       }
53131 +
53132 +       if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53133 +               return 0;
53134 +       }
53135 +       req = DWC_CIRCLEQ_FIRST(&ep->queue);
53136 +
53137 +       if (pcd->ep0state == EP0_OUT_STATUS_PHASE
53138 +           || pcd->ep0state == EP0_IN_STATUS_PHASE) {
53139 +               is_last = 1;
53140 +       } else if (ep->dwc_ep.is_in) {
53141 +               deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
53142 +               if (core_if->dma_desc_enable != 0)
53143 +                       desc_sts = dev_if->in_desc_addr->status;
53144 +#ifdef DEBUG_EP0
53145 +               DWC_DEBUGPL(DBG_PCDV, "%d len=%d  xfersize=%d pktcnt=%d\n",
53146 +                           ep->dwc_ep.num, ep->dwc_ep.xfer_len,
53147 +                           deptsiz.b.xfersize, deptsiz.b.pktcnt);
53148 +#endif
53149 +
53150 +               if (((core_if->dma_desc_enable == 0)
53151 +                    && (deptsiz.b.xfersize == 0))
53152 +                   || ((core_if->dma_desc_enable != 0)
53153 +                       && (desc_sts.b.bytes == 0))) {
53154 +                       req->actual = ep->dwc_ep.xfer_count;
53155 +                       /* Is a Zero Len Packet needed? */
53156 +                       if (req->sent_zlp) {
53157 +#ifdef DEBUG_EP0
53158 +                               DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
53159 +#endif
53160 +                               req->sent_zlp = 0;
53161 +                       }
53162 +                       do_setup_out_status_phase(pcd);
53163 +               }
53164 +       } else {
53165 +               /* ep0-OUT */
53166 +#ifdef DEBUG_EP0
53167 +               deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
53168 +               DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
53169 +                           ep->dwc_ep.num, ep->dwc_ep.xfer_len,
53170 +                           deptsiz.b.xfersize, deptsiz.b.pktcnt);
53171 +#endif
53172 +               req->actual = ep->dwc_ep.xfer_count;
53173 +
53174 +               /* Is a Zero Len Packet needed? */
53175 +               if (req->sent_zlp) {
53176 +#ifdef DEBUG_EP0
53177 +                       DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
53178 +#endif
53179 +                       req->sent_zlp = 0;
53180 +               }
53181 +               /* For older cores do setup in status phase in Slave/BDMA modes,
53182 +                * starting from 3.00 do that only in slave, and for DMA modes
53183 +                * just re-enable ep 0 OUT here*/
53184 +               if (core_if->dma_enable == 0
53185 +                   || (core_if->dma_desc_enable == 0
53186 +                       && core_if->snpsid <= OTG_CORE_REV_2_94a)) {
53187 +                       do_setup_in_status_phase(pcd);
53188 +               } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
53189 +                       DWC_DEBUGPL(DBG_PCDV,
53190 +                                   "Enable out ep before in status phase\n");
53191 +                       ep0_out_start(core_if, pcd);
53192 +               }
53193 +       }
53194 +
53195 +       /* Complete the request */
53196 +       if (is_last) {
53197 +               dwc_otg_request_done(ep, req, 0);
53198 +               ep->dwc_ep.start_xfer_buff = 0;
53199 +               ep->dwc_ep.xfer_buff = 0;
53200 +               ep->dwc_ep.xfer_len = 0;
53201 +               return 1;
53202 +       }
53203 +       return 0;
53204 +}
53205 +
53206 +#ifdef DWC_UTE_CFI
53207 +/**
53208 + * This function calculates traverses all the CFI DMA descriptors and
53209 + * and accumulates the bytes that are left to be transfered.
53210 + *
53211 + * @return The total bytes left to transfered, or a negative value as failure
53212 + */
53213 +static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
53214 +{
53215 +       int32_t ret = 0;
53216 +       int i;
53217 +       struct dwc_otg_dma_desc *ddesc = NULL;
53218 +       struct cfi_ep *cfiep;
53219 +
53220 +       /* See if the pcd_ep has its respective cfi_ep mapped */
53221 +       cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
53222 +       if (!cfiep) {
53223 +               CFI_INFO("%s: Failed to find ep\n", __func__);
53224 +               return -1;
53225 +       }
53226 +
53227 +       ddesc = ep->dwc_ep.descs;
53228 +
53229 +       for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
53230 +
53231 +#if defined(PRINT_CFI_DMA_DESCS)
53232 +               print_desc(ddesc, ep->ep.name, i);
53233 +#endif
53234 +               ret += ddesc->status.b.bytes;
53235 +               ddesc++;
53236 +       }
53237 +
53238 +       if (ret)
53239 +               CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
53240 +                        ret);
53241 +
53242 +       return ret;
53243 +}
53244 +#endif
53245 +
53246 +/**
53247 + * This function completes the request for the EP. If there are
53248 + * additional requests for the EP in the queue they will be started.
53249 + */
53250 +static void complete_ep(dwc_otg_pcd_ep_t * ep)
53251 +{
53252 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
53253 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
53254 +       dwc_otg_dev_in_ep_regs_t *in_ep_regs =
53255 +           dev_if->in_ep_regs[ep->dwc_ep.num];
53256 +       deptsiz_data_t deptsiz;
53257 +       dev_dma_desc_sts_t desc_sts;
53258 +       dwc_otg_pcd_request_t *req = 0;
53259 +       dwc_otg_dev_dma_desc_t *dma_desc;
53260 +       uint32_t byte_count = 0;
53261 +       int is_last = 0;
53262 +       int i;
53263 +
53264 +       DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
53265 +                   (ep->dwc_ep.is_in ? "IN" : "OUT"));
53266 +
53267 +       /* Get any pending requests */
53268 +       if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
53269 +               req = DWC_CIRCLEQ_FIRST(&ep->queue);
53270 +               if (!req) {
53271 +                       DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
53272 +                       return;
53273 +               }
53274 +       } else {
53275 +               DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
53276 +               return;
53277 +       }
53278 +
53279 +       DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
53280 +
53281 +       if (ep->dwc_ep.is_in) {
53282 +               deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
53283 +
53284 +               if (core_if->dma_enable) {
53285 +                       if (core_if->dma_desc_enable == 0) {
53286 +                               if (deptsiz.b.xfersize == 0
53287 +                                   && deptsiz.b.pktcnt == 0) {
53288 +                                       byte_count =
53289 +                                           ep->dwc_ep.xfer_len -
53290 +                                           ep->dwc_ep.xfer_count;
53291 +
53292 +                                       ep->dwc_ep.xfer_buff += byte_count;
53293 +                                       ep->dwc_ep.dma_addr += byte_count;
53294 +                                       ep->dwc_ep.xfer_count += byte_count;
53295 +
53296 +                                       DWC_DEBUGPL(DBG_PCDV,
53297 +                                                   "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
53298 +                                                   ep->dwc_ep.num,
53299 +                                                   (ep->dwc_ep.
53300 +                                                    is_in ? "IN" : "OUT"),
53301 +                                                   ep->dwc_ep.xfer_len,
53302 +                                                   deptsiz.b.xfersize,
53303 +                                                   deptsiz.b.pktcnt);
53304 +
53305 +                                       if (ep->dwc_ep.xfer_len <
53306 +                                           ep->dwc_ep.total_len) {
53307 +                                               dwc_otg_ep_start_transfer
53308 +                                                   (core_if, &ep->dwc_ep);
53309 +                                       } else if (ep->dwc_ep.sent_zlp) {
53310 +                                               /*
53311 +                                                * This fragment of code should initiate 0
53312 +                                                * length transfer in case if it is queued
53313 +                                                * a transfer with size divisible to EPs max
53314 +                                                * packet size and with usb_request zero field
53315 +                                                * is set, which means that after data is transfered,
53316 +                                                * it is also should be transfered
53317 +                                                * a 0 length packet at the end. For Slave and
53318 +                                                * Buffer DMA modes in this case SW has
53319 +                                                * to initiate 2 transfers one with transfer size,
53320 +                                                * and the second with 0 size. For Descriptor
53321 +                                                * DMA mode SW is able to initiate a transfer,
53322 +                                                * which will handle all the packets including
53323 +                                                * the last  0 length.
53324 +                                                */
53325 +                                               ep->dwc_ep.sent_zlp = 0;
53326 +                                               dwc_otg_ep_start_zl_transfer
53327 +                                                   (core_if, &ep->dwc_ep);
53328 +                                       } else {
53329 +                                               is_last = 1;
53330 +                                       }
53331 +                               } else {
53332 +                                       if (ep->dwc_ep.type ==
53333 +                                           DWC_OTG_EP_TYPE_ISOC) {
53334 +                                               req->actual = 0;
53335 +                                               dwc_otg_request_done(ep, req, 0);
53336 +
53337 +                                               ep->dwc_ep.start_xfer_buff = 0;
53338 +                                               ep->dwc_ep.xfer_buff = 0;
53339 +                                               ep->dwc_ep.xfer_len = 0;
53340 +
53341 +                                               /* If there is a request in the queue start it. */
53342 +                                               start_next_request(ep);
53343 +                                       } else
53344 +                                               DWC_WARN
53345 +                                               ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
53346 +                                               ep->dwc_ep.num,
53347 +                                               (ep->dwc_ep.is_in ? "IN" : "OUT"),
53348 +                                               deptsiz.b.xfersize,
53349 +                                               deptsiz.b.pktcnt);
53350 +                               }
53351 +                       } else {
53352 +                               dma_desc = ep->dwc_ep.desc_addr;
53353 +                               byte_count = 0;
53354 +                               ep->dwc_ep.sent_zlp = 0;
53355 +
53356 +#ifdef DWC_UTE_CFI
53357 +                               CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
53358 +                                        ep->dwc_ep.buff_mode);
53359 +                               if (ep->dwc_ep.buff_mode != BM_STANDARD) {
53360 +                                       int residue;
53361 +
53362 +                                       residue = cfi_calc_desc_residue(ep);
53363 +                                       if (residue < 0)
53364 +                                               return;
53365 +
53366 +                                       byte_count = residue;
53367 +                               } else {
53368 +#endif
53369 +                                       for (i = 0; i < ep->dwc_ep.desc_cnt;
53370 +                                            ++i) {
53371 +                                       desc_sts = dma_desc->status;
53372 +                                       byte_count += desc_sts.b.bytes;
53373 +                                       dma_desc++;
53374 +                               }
53375 +#ifdef DWC_UTE_CFI
53376 +                               }
53377 +#endif
53378 +                               if (byte_count == 0) {
53379 +                                       ep->dwc_ep.xfer_count =
53380 +                                           ep->dwc_ep.total_len;
53381 +                                       is_last = 1;
53382 +                               } else {
53383 +                                       DWC_WARN("Incomplete transfer\n");
53384 +                               }
53385 +                       }
53386 +               } else {
53387 +                       if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
53388 +                               DWC_DEBUGPL(DBG_PCDV,
53389 +                                           "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
53390 +                                           ep->dwc_ep.num,
53391 +                                           ep->dwc_ep.is_in ? "IN" : "OUT",
53392 +                                           ep->dwc_ep.xfer_len,
53393 +                                           deptsiz.b.xfersize,
53394 +                                           deptsiz.b.pktcnt);
53395 +
53396 +                               /*      Check if the whole transfer was completed,
53397 +                                *      if no, setup transfer for next portion of data
53398 +                                */
53399 +                               if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
53400 +                                       dwc_otg_ep_start_transfer(core_if,
53401 +                                                                 &ep->dwc_ep);
53402 +                               } else if (ep->dwc_ep.sent_zlp) {
53403 +                                       /*
53404 +                                        * This fragment of code should initiate 0
53405 +                                        * length trasfer in case if it is queued
53406 +                                        * a trasfer with size divisible to EPs max
53407 +                                        * packet size and with usb_request zero field
53408 +                                        * is set, which means that after data is transfered,
53409 +                                        * it is also should be transfered
53410 +                                        * a 0 length packet at the end. For Slave and
53411 +                                        * Buffer DMA modes in this case SW has
53412 +                                        * to initiate 2 transfers one with transfer size,
53413 +                                        * and the second with 0 size. For Desriptor
53414 +                                        * DMA mode SW is able to initiate a transfer,
53415 +                                        * which will handle all the packets including
53416 +                                        * the last  0 legth.
53417 +                                        */
53418 +                                       ep->dwc_ep.sent_zlp = 0;
53419 +                                       dwc_otg_ep_start_zl_transfer(core_if,
53420 +                                                                    &ep->dwc_ep);
53421 +                               } else {
53422 +                                       is_last = 1;
53423 +                               }
53424 +                       } else {
53425 +                               DWC_WARN
53426 +                                   ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
53427 +                                    ep->dwc_ep.num,
53428 +                                    (ep->dwc_ep.is_in ? "IN" : "OUT"),
53429 +                                    deptsiz.b.xfersize, deptsiz.b.pktcnt);
53430 +                       }
53431 +               }
53432 +       } else {
53433 +               dwc_otg_dev_out_ep_regs_t *out_ep_regs =
53434 +                   dev_if->out_ep_regs[ep->dwc_ep.num];
53435 +               desc_sts.d32 = 0;
53436 +               if (core_if->dma_enable) {
53437 +                       if (core_if->dma_desc_enable) {
53438 +                               dma_desc = ep->dwc_ep.desc_addr;
53439 +                               byte_count = 0;
53440 +                               ep->dwc_ep.sent_zlp = 0;
53441 +
53442 +#ifdef DWC_UTE_CFI
53443 +                               CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
53444 +                                        ep->dwc_ep.buff_mode);
53445 +                               if (ep->dwc_ep.buff_mode != BM_STANDARD) {
53446 +                                       int residue;
53447 +                                       residue = cfi_calc_desc_residue(ep);
53448 +                                       if (residue < 0)
53449 +                                               return;
53450 +                                       byte_count = residue;
53451 +                               } else {
53452 +#endif
53453 +
53454 +                                       for (i = 0; i < ep->dwc_ep.desc_cnt;
53455 +                                            ++i) {
53456 +                                               desc_sts = dma_desc->status;
53457 +                                               byte_count += desc_sts.b.bytes;
53458 +                                               dma_desc++;
53459 +                                       }
53460 +
53461 +#ifdef DWC_UTE_CFI
53462 +                               }
53463 +#endif
53464 +                               /* Checking for interrupt Out transfers with not
53465 +                                * dword aligned mps sizes
53466 +                                */
53467 +                               if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
53468 +                                                       (ep->dwc_ep.maxpacket%4)) {
53469 +                                       ep->dwc_ep.xfer_count =
53470 +                                           ep->dwc_ep.total_len - byte_count;
53471 +                                       if ((ep->dwc_ep.xfer_len %
53472 +                                            ep->dwc_ep.maxpacket)
53473 +                                           && (ep->dwc_ep.xfer_len /
53474 +                                               ep->dwc_ep.maxpacket <
53475 +                                               MAX_DMA_DESC_CNT))
53476 +                                               ep->dwc_ep.xfer_len -=
53477 +                                                   (ep->dwc_ep.desc_cnt -
53478 +                                                    1) * ep->dwc_ep.maxpacket +
53479 +                                                   ep->dwc_ep.xfer_len %
53480 +                                                   ep->dwc_ep.maxpacket;
53481 +                                       else
53482 +                                               ep->dwc_ep.xfer_len -=
53483 +                                                   ep->dwc_ep.desc_cnt *
53484 +                                                   ep->dwc_ep.maxpacket;
53485 +                                       if (ep->dwc_ep.xfer_len > 0) {
53486 +                                               dwc_otg_ep_start_transfer
53487 +                                                   (core_if, &ep->dwc_ep);
53488 +                                       } else {
53489 +                                               is_last = 1;
53490 +                                       }
53491 +                               } else {
53492 +                                       ep->dwc_ep.xfer_count =
53493 +                                           ep->dwc_ep.total_len - byte_count +
53494 +                                           ((4 -
53495 +                                             (ep->dwc_ep.
53496 +                                              total_len & 0x3)) & 0x3);
53497 +                                       is_last = 1;
53498 +                               }
53499 +                       } else {
53500 +                               deptsiz.d32 = 0;
53501 +                               deptsiz.d32 =
53502 +                                   DWC_READ_REG32(&out_ep_regs->doeptsiz);
53503 +
53504 +                               byte_count = (ep->dwc_ep.xfer_len -
53505 +                                             ep->dwc_ep.xfer_count -
53506 +                                             deptsiz.b.xfersize);
53507 +                               ep->dwc_ep.xfer_buff += byte_count;
53508 +                               ep->dwc_ep.dma_addr += byte_count;
53509 +                               ep->dwc_ep.xfer_count += byte_count;
53510 +
53511 +                               /*      Check if the whole transfer was completed,
53512 +                                *      if no, setup transfer for next portion of data
53513 +                                */
53514 +                               if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
53515 +                                       dwc_otg_ep_start_transfer(core_if,
53516 +                                                                 &ep->dwc_ep);
53517 +                               } else if (ep->dwc_ep.sent_zlp) {
53518 +                                       /*
53519 +                                        * This fragment of code should initiate 0
53520 +                                        * length trasfer in case if it is queued
53521 +                                        * a trasfer with size divisible to EPs max
53522 +                                        * packet size and with usb_request zero field
53523 +                                        * is set, which means that after data is transfered,
53524 +                                        * it is also should be transfered
53525 +                                        * a 0 length packet at the end. For Slave and
53526 +                                        * Buffer DMA modes in this case SW has
53527 +                                        * to initiate 2 transfers one with transfer size,
53528 +                                        * and the second with 0 size. For Desriptor
53529 +                                        * DMA mode SW is able to initiate a transfer,
53530 +                                        * which will handle all the packets including
53531 +                                        * the last  0 legth.
53532 +                                        */
53533 +                                       ep->dwc_ep.sent_zlp = 0;
53534 +                                       dwc_otg_ep_start_zl_transfer(core_if,
53535 +                                                                    &ep->dwc_ep);
53536 +                               } else {
53537 +                                       is_last = 1;
53538 +                               }
53539 +                       }
53540 +               } else {
53541 +                       /*      Check if the whole transfer was completed,
53542 +                        *      if no, setup transfer for next portion of data
53543 +                        */
53544 +                       if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
53545 +                               dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
53546 +                       } else if (ep->dwc_ep.sent_zlp) {
53547 +                               /*
53548 +                                * This fragment of code should initiate 0
53549 +                                * length transfer in case if it is queued
53550 +                                * a transfer with size divisible to EPs max
53551 +                                * packet size and with usb_request zero field
53552 +                                * is set, which means that after data is transfered,
53553 +                                * it is also should be transfered
53554 +                                * a 0 length packet at the end. For Slave and
53555 +                                * Buffer DMA modes in this case SW has
53556 +                                * to initiate 2 transfers one with transfer size,
53557 +                                * and the second with 0 size. For Descriptor
53558 +                                * DMA mode SW is able to initiate a transfer,
53559 +                                * which will handle all the packets including
53560 +                                * the last  0 length.
53561 +                                */
53562 +                               ep->dwc_ep.sent_zlp = 0;
53563 +                               dwc_otg_ep_start_zl_transfer(core_if,
53564 +                                                            &ep->dwc_ep);
53565 +                       } else {
53566 +                               is_last = 1;
53567 +                       }
53568 +               }
53569 +
53570 +               DWC_DEBUGPL(DBG_PCDV,
53571 +                           "addr %p,    %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
53572 +                           &out_ep_regs->doeptsiz, ep->dwc_ep.num,
53573 +                           ep->dwc_ep.is_in ? "IN" : "OUT",
53574 +                           ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
53575 +                           deptsiz.b.xfersize, deptsiz.b.pktcnt);
53576 +       }
53577 +
53578 +       /* Complete the request */
53579 +       if (is_last) {
53580 +#ifdef DWC_UTE_CFI
53581 +               if (ep->dwc_ep.buff_mode != BM_STANDARD) {
53582 +                       req->actual = ep->dwc_ep.cfi_req_len - byte_count;
53583 +               } else {
53584 +#endif
53585 +                       req->actual = ep->dwc_ep.xfer_count;
53586 +#ifdef DWC_UTE_CFI
53587 +               }
53588 +#endif
53589 +               if (req->dw_align_buf) {
53590 +                       if (!ep->dwc_ep.is_in) {
53591 +                               dwc_memcpy(req->buf, req->dw_align_buf, req->length);
53592 +                       }
53593 +                       DWC_DMA_FREE(req->length, req->dw_align_buf,
53594 +                                    req->dw_align_buf_dma);
53595 +               }
53596 +
53597 +               dwc_otg_request_done(ep, req, 0);
53598 +
53599 +               ep->dwc_ep.start_xfer_buff = 0;
53600 +               ep->dwc_ep.xfer_buff = 0;
53601 +               ep->dwc_ep.xfer_len = 0;
53602 +
53603 +               /* If there is a request in the queue start it. */
53604 +               start_next_request(ep);
53605 +       }
53606 +}
53607 +
53608 +#ifdef DWC_EN_ISOC
53609 +
53610 +/**
53611 + * This function BNA interrupt for Isochronous EPs
53612 + *
53613 + */
53614 +static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
53615 +{
53616 +       dwc_ep_t *dwc_ep = &ep->dwc_ep;
53617 +       volatile uint32_t *addr;
53618 +       depctl_data_t depctl = {.d32 = 0 };
53619 +       dwc_otg_pcd_t *pcd = ep->pcd;
53620 +       dwc_otg_dev_dma_desc_t *dma_desc;
53621 +       int i;
53622 +
53623 +       dma_desc =
53624 +           dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
53625 +
53626 +       if (dwc_ep->is_in) {
53627 +               dev_dma_desc_sts_t sts = {.d32 = 0 };
53628 +               for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
53629 +                       sts.d32 = dma_desc->status.d32;
53630 +                       sts.b_iso_in.bs = BS_HOST_READY;
53631 +                       dma_desc->status.d32 = sts.d32;
53632 +               }
53633 +       } else {
53634 +               dev_dma_desc_sts_t sts = {.d32 = 0 };
53635 +               for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
53636 +                       sts.d32 = dma_desc->status.d32;
53637 +                       sts.b_iso_out.bs = BS_HOST_READY;
53638 +                       dma_desc->status.d32 = sts.d32;
53639 +               }
53640 +       }
53641 +
53642 +       if (dwc_ep->is_in == 0) {
53643 +               addr =
53644 +                   &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
53645 +                                                          num]->doepctl;
53646 +       } else {
53647 +               addr =
53648 +                   &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
53649 +       }
53650 +       depctl.b.epena = 1;
53651 +       DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
53652 +}
53653 +
53654 +/**
53655 + * This function sets latest iso packet information(non-PTI mode)
53656 + *
53657 + * @param core_if Programming view of DWC_otg controller.
53658 + * @param ep The EP to start the transfer on.
53659 + *
53660 + */
53661 +void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
53662 +{
53663 +       deptsiz_data_t deptsiz = {.d32 = 0 };
53664 +       dma_addr_t dma_addr;
53665 +       uint32_t offset;
53666 +
53667 +       if (ep->proc_buf_num)
53668 +               dma_addr = ep->dma_addr1;
53669 +       else
53670 +               dma_addr = ep->dma_addr0;
53671 +
53672 +       if (ep->is_in) {
53673 +               deptsiz.d32 =
53674 +                   DWC_READ_REG32(&core_if->dev_if->
53675 +                                  in_ep_regs[ep->num]->dieptsiz);
53676 +               offset = ep->data_per_frame;
53677 +       } else {
53678 +               deptsiz.d32 =
53679 +                   DWC_READ_REG32(&core_if->dev_if->
53680 +                                  out_ep_regs[ep->num]->doeptsiz);
53681 +               offset =
53682 +                   ep->data_per_frame +
53683 +                   (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
53684 +       }
53685 +
53686 +       if (!deptsiz.b.xfersize) {
53687 +               ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
53688 +               ep->pkt_info[ep->cur_pkt].offset =
53689 +                   ep->cur_pkt_dma_addr - dma_addr;
53690 +               ep->pkt_info[ep->cur_pkt].status = 0;
53691 +       } else {
53692 +               ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
53693 +               ep->pkt_info[ep->cur_pkt].offset =
53694 +                   ep->cur_pkt_dma_addr - dma_addr;
53695 +               ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
53696 +       }
53697 +       ep->cur_pkt_addr += offset;
53698 +       ep->cur_pkt_dma_addr += offset;
53699 +       ep->cur_pkt++;
53700 +}
53701 +
53702 +/**
53703 + * This function sets latest iso packet information(DDMA mode)
53704 + *
53705 + * @param core_if Programming view of DWC_otg controller.
53706 + * @param dwc_ep The EP to start the transfer on.
53707 + *
53708 + */
53709 +static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
53710 +                                  dwc_ep_t * dwc_ep)
53711 +{
53712 +       dwc_otg_dev_dma_desc_t *dma_desc;
53713 +       dev_dma_desc_sts_t sts = {.d32 = 0 };
53714 +       iso_pkt_info_t *iso_packet;
53715 +       uint32_t data_per_desc;
53716 +       uint32_t offset;
53717 +       int i, j;
53718 +
53719 +       iso_packet = dwc_ep->pkt_info;
53720 +
53721 +       /** Reinit closed DMA Descriptors*/
53722 +       /** ISO OUT EP */
53723 +       if (dwc_ep->is_in == 0) {
53724 +               dma_desc =
53725 +                   dwc_ep->iso_desc_addr +
53726 +                   dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
53727 +               offset = 0;
53728 +
53729 +               for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
53730 +                    i += dwc_ep->pkt_per_frm) {
53731 +                       for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
53732 +                               data_per_desc =
53733 +                                   ((j + 1) * dwc_ep->maxpacket >
53734 +                                    dwc_ep->
53735 +                                    data_per_frame) ? dwc_ep->data_per_frame -
53736 +                                   j * dwc_ep->maxpacket : dwc_ep->maxpacket;
53737 +                               data_per_desc +=
53738 +                                   (data_per_desc % 4) ? (4 -
53739 +                                                          data_per_desc %
53740 +                                                          4) : 0;
53741 +
53742 +                               sts.d32 = dma_desc->status.d32;
53743 +
53744 +                               /* Write status in iso_packet_decsriptor  */
53745 +                               iso_packet->status =
53746 +                                   sts.b_iso_out.rxsts +
53747 +                                   (sts.b_iso_out.bs ^ BS_DMA_DONE);
53748 +                               if (iso_packet->status) {
53749 +                                       iso_packet->status = -DWC_E_NO_DATA;
53750 +                               }
53751 +
53752 +                               /* Received data length */
53753 +                               if (!sts.b_iso_out.rxbytes) {
53754 +                                       iso_packet->length =
53755 +                                           data_per_desc -
53756 +                                           sts.b_iso_out.rxbytes;
53757 +                               } else {
53758 +                                       iso_packet->length =
53759 +                                           data_per_desc -
53760 +                                           sts.b_iso_out.rxbytes + (4 -
53761 +                                                                    dwc_ep->data_per_frame
53762 +                                                                    % 4);
53763 +                               }
53764 +
53765 +                               iso_packet->offset = offset;
53766 +
53767 +                               offset += data_per_desc;
53768 +                               dma_desc++;
53769 +                               iso_packet++;
53770 +                       }
53771 +               }
53772 +
53773 +               for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
53774 +                       data_per_desc =
53775 +                           ((j + 1) * dwc_ep->maxpacket >
53776 +                            dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
53777 +                           j * dwc_ep->maxpacket : dwc_ep->maxpacket;
53778 +                       data_per_desc +=
53779 +                           (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
53780 +
53781 +                       sts.d32 = dma_desc->status.d32;
53782 +
53783 +                       /* Write status in iso_packet_decsriptor  */
53784 +                       iso_packet->status =
53785 +                           sts.b_iso_out.rxsts +
53786 +                           (sts.b_iso_out.bs ^ BS_DMA_DONE);
53787 +                       if (iso_packet->status) {
53788 +                               iso_packet->status = -DWC_E_NO_DATA;
53789 +                       }
53790 +
53791 +                       /* Received data length */
53792 +                       iso_packet->length =
53793 +                           dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
53794 +
53795 +                       iso_packet->offset = offset;
53796 +
53797 +                       offset += data_per_desc;
53798 +                       iso_packet++;
53799 +                       dma_desc++;
53800 +               }
53801 +
53802 +               sts.d32 = dma_desc->status.d32;
53803 +
53804 +               /* Write status in iso_packet_decsriptor  */
53805 +               iso_packet->status =
53806 +                   sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
53807 +               if (iso_packet->status) {
53808 +                       iso_packet->status = -DWC_E_NO_DATA;
53809 +               }
53810 +               /* Received data length */
53811 +               if (!sts.b_iso_out.rxbytes) {
53812 +                       iso_packet->length =
53813 +                           dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
53814 +               } else {
53815 +                       iso_packet->length =
53816 +                           dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
53817 +                           (4 - dwc_ep->data_per_frame % 4);
53818 +               }
53819 +
53820 +               iso_packet->offset = offset;
53821 +       } else {
53822 +/** ISO IN EP */
53823 +
53824 +               dma_desc =
53825 +                   dwc_ep->iso_desc_addr +
53826 +                   dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
53827 +
53828 +               for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
53829 +                       sts.d32 = dma_desc->status.d32;
53830 +
53831 +                       /* Write status in iso packet descriptor */
53832 +                       iso_packet->status =
53833 +                           sts.b_iso_in.txsts +
53834 +                           (sts.b_iso_in.bs ^ BS_DMA_DONE);
53835 +                       if (iso_packet->status != 0) {
53836 +                               iso_packet->status = -DWC_E_NO_DATA;
53837 +
53838 +                       }
53839 +                       /* Bytes has been transfered */
53840 +                       iso_packet->length =
53841 +                           dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
53842 +
53843 +                       dma_desc++;
53844 +                       iso_packet++;
53845 +               }
53846 +
53847 +               sts.d32 = dma_desc->status.d32;
53848 +               while (sts.b_iso_in.bs == BS_DMA_BUSY) {
53849 +                       sts.d32 = dma_desc->status.d32;
53850 +               }
53851 +
53852 +               /* Write status in iso packet descriptor ??? do be done with ERROR codes */
53853 +               iso_packet->status =
53854 +                   sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
53855 +               if (iso_packet->status != 0) {
53856 +                       iso_packet->status = -DWC_E_NO_DATA;
53857 +               }
53858 +
53859 +               /* Bytes has been transfered */
53860 +               iso_packet->length =
53861 +                   dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
53862 +       }
53863 +}
53864 +
53865 +/**
53866 + * This function reinitialize DMA Descriptors for Isochronous transfer
53867 + *
53868 + * @param core_if Programming view of DWC_otg controller.
53869 + * @param dwc_ep The EP to start the transfer on.
53870 + *
53871 + */
53872 +static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
53873 +{
53874 +       int i, j;
53875 +       dwc_otg_dev_dma_desc_t *dma_desc;
53876 +       dma_addr_t dma_ad;
53877 +       volatile uint32_t *addr;
53878 +       dev_dma_desc_sts_t sts = {.d32 = 0 };
53879 +       uint32_t data_per_desc;
53880 +
53881 +       if (dwc_ep->is_in == 0) {
53882 +               addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
53883 +       } else {
53884 +               addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
53885 +       }
53886 +
53887 +       if (dwc_ep->proc_buf_num == 0) {
53888 +               /** Buffer 0 descriptors setup */
53889 +               dma_ad = dwc_ep->dma_addr0;
53890 +       } else {
53891 +               /** Buffer 1 descriptors setup */
53892 +               dma_ad = dwc_ep->dma_addr1;
53893 +       }
53894 +
53895 +       /** Reinit closed DMA Descriptors*/
53896 +       /** ISO OUT EP */
53897 +       if (dwc_ep->is_in == 0) {
53898 +               dma_desc =
53899 +                   dwc_ep->iso_desc_addr +
53900 +                   dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
53901 +
53902 +               sts.b_iso_out.bs = BS_HOST_READY;
53903 +               sts.b_iso_out.rxsts = 0;
53904 +               sts.b_iso_out.l = 0;
53905 +               sts.b_iso_out.sp = 0;
53906 +               sts.b_iso_out.ioc = 0;
53907 +               sts.b_iso_out.pid = 0;
53908 +               sts.b_iso_out.framenum = 0;
53909 +
53910 +               for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
53911 +                    i += dwc_ep->pkt_per_frm) {
53912 +                       for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
53913 +                               data_per_desc =
53914 +                                   ((j + 1) * dwc_ep->maxpacket >
53915 +                                    dwc_ep->
53916 +                                    data_per_frame) ? dwc_ep->data_per_frame -
53917 +                                   j * dwc_ep->maxpacket : dwc_ep->maxpacket;
53918 +                               data_per_desc +=
53919 +                                   (data_per_desc % 4) ? (4 -
53920 +                                                          data_per_desc %
53921 +                                                          4) : 0;
53922 +                               sts.b_iso_out.rxbytes = data_per_desc;
53923 +                               dma_desc->buf = dma_ad;
53924 +                               dma_desc->status.d32 = sts.d32;
53925 +
53926 +                               dma_ad += data_per_desc;
53927 +                               dma_desc++;
53928 +                       }
53929 +               }
53930 +
53931 +               for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
53932 +
53933 +                       data_per_desc =
53934 +                           ((j + 1) * dwc_ep->maxpacket >
53935 +                            dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
53936 +                           j * dwc_ep->maxpacket : dwc_ep->maxpacket;
53937 +                       data_per_desc +=
53938 +                           (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
53939 +                       sts.b_iso_out.rxbytes = data_per_desc;
53940 +
53941 +                       dma_desc->buf = dma_ad;
53942 +                       dma_desc->status.d32 = sts.d32;
53943 +
53944 +                       dma_desc++;
53945 +                       dma_ad += data_per_desc;
53946 +               }
53947 +
53948 +               sts.b_iso_out.ioc = 1;
53949 +               sts.b_iso_out.l = dwc_ep->proc_buf_num;
53950 +
53951 +               data_per_desc =
53952 +                   ((j + 1) * dwc_ep->maxpacket >
53953 +                    dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
53954 +                   j * dwc_ep->maxpacket : dwc_ep->maxpacket;
53955 +               data_per_desc +=
53956 +                   (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
53957 +               sts.b_iso_out.rxbytes = data_per_desc;
53958 +
53959 +               dma_desc->buf = dma_ad;
53960 +               dma_desc->status.d32 = sts.d32;
53961 +       } else {
53962 +/** ISO IN EP */
53963 +
53964 +               dma_desc =
53965 +                   dwc_ep->iso_desc_addr +
53966 +                   dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
53967 +
53968 +               sts.b_iso_in.bs = BS_HOST_READY;
53969 +               sts.b_iso_in.txsts = 0;
53970 +               sts.b_iso_in.sp = 0;
53971 +               sts.b_iso_in.ioc = 0;
53972 +               sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
53973 +               sts.b_iso_in.framenum = dwc_ep->next_frame;
53974 +               sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
53975 +               sts.b_iso_in.l = 0;
53976 +
53977 +               for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
53978 +                       dma_desc->buf = dma_ad;
53979 +                       dma_desc->status.d32 = sts.d32;
53980 +
53981 +                       sts.b_iso_in.framenum += dwc_ep->bInterval;
53982 +                       dma_ad += dwc_ep->data_per_frame;
53983 +                       dma_desc++;
53984 +               }
53985 +
53986 +               sts.b_iso_in.ioc = 1;
53987 +               sts.b_iso_in.l = dwc_ep->proc_buf_num;
53988 +
53989 +               dma_desc->buf = dma_ad;
53990 +               dma_desc->status.d32 = sts.d32;
53991 +
53992 +               dwc_ep->next_frame =
53993 +                   sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
53994 +       }
53995 +       dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
53996 +}
53997 +
53998 +/**
53999 + * This function is to handle Iso EP transfer complete interrupt
54000 + * in case Iso out packet was dropped
54001 + *
54002 + * @param core_if Programming view of DWC_otg controller.
54003 + * @param dwc_ep The EP for wihich transfer complete was asserted
54004 + *
54005 + */
54006 +static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
54007 +                                          dwc_ep_t * dwc_ep)
54008 +{
54009 +       uint32_t dma_addr;
54010 +       uint32_t drp_pkt;
54011 +       uint32_t drp_pkt_cnt;
54012 +       deptsiz_data_t deptsiz = {.d32 = 0 };
54013 +       depctl_data_t depctl = {.d32 = 0 };
54014 +       int i;
54015 +
54016 +       deptsiz.d32 =
54017 +           DWC_READ_REG32(&core_if->dev_if->
54018 +                          out_ep_regs[dwc_ep->num]->doeptsiz);
54019 +
54020 +       drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
54021 +       drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
54022 +
54023 +       /* Setting dropped packets status */
54024 +       for (i = 0; i < drp_pkt_cnt; ++i) {
54025 +               dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
54026 +               drp_pkt++;
54027 +               deptsiz.b.pktcnt--;
54028 +       }
54029 +
54030 +       if (deptsiz.b.pktcnt > 0) {
54031 +               deptsiz.b.xfersize =
54032 +                   dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
54033 +                                       deptsiz.b.pktcnt) * dwc_ep->maxpacket;
54034 +       } else {
54035 +               deptsiz.b.xfersize = 0;
54036 +               deptsiz.b.pktcnt = 0;
54037 +       }
54038 +
54039 +       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
54040 +                       deptsiz.d32);
54041 +
54042 +       if (deptsiz.b.pktcnt > 0) {
54043 +               if (dwc_ep->proc_buf_num) {
54044 +                       dma_addr =
54045 +                           dwc_ep->dma_addr1 + dwc_ep->xfer_len -
54046 +                           deptsiz.b.xfersize;
54047 +               } else {
54048 +                       dma_addr =
54049 +                           dwc_ep->dma_addr0 + dwc_ep->xfer_len -
54050 +                           deptsiz.b.xfersize;;
54051 +               }
54052 +
54053 +               DWC_WRITE_REG32(&core_if->dev_if->
54054 +                               out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
54055 +
54056 +               /** Re-enable endpoint, clear nak  */
54057 +               depctl.d32 = 0;
54058 +               depctl.b.epena = 1;
54059 +               depctl.b.cnak = 1;
54060 +
54061 +               DWC_MODIFY_REG32(&core_if->dev_if->
54062 +                                out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
54063 +                                depctl.d32);
54064 +               return 0;
54065 +       } else {
54066 +               return 1;
54067 +       }
54068 +}
54069 +
54070 +/**
54071 + * This function sets iso packets information(PTI mode)
54072 + *
54073 + * @param core_if Programming view of DWC_otg controller.
54074 + * @param ep The EP to start the transfer on.
54075 + *
54076 + */
54077 +static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
54078 +{
54079 +       int i, j;
54080 +       dma_addr_t dma_ad;
54081 +       iso_pkt_info_t *packet_info = ep->pkt_info;
54082 +       uint32_t offset;
54083 +       uint32_t frame_data;
54084 +       deptsiz_data_t deptsiz;
54085 +
54086 +       if (ep->proc_buf_num == 0) {
54087 +               /** Buffer 0 descriptors setup */
54088 +               dma_ad = ep->dma_addr0;
54089 +       } else {
54090 +               /** Buffer 1 descriptors setup */
54091 +               dma_ad = ep->dma_addr1;
54092 +       }
54093 +
54094 +       if (ep->is_in) {
54095 +               deptsiz.d32 =
54096 +                   DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
54097 +                                  dieptsiz);
54098 +       } else {
54099 +               deptsiz.d32 =
54100 +                   DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
54101 +                                  doeptsiz);
54102 +       }
54103 +
54104 +       if (!deptsiz.b.xfersize) {
54105 +               offset = 0;
54106 +               for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
54107 +                       frame_data = ep->data_per_frame;
54108 +                       for (j = 0; j < ep->pkt_per_frm; ++j) {
54109 +
54110 +                               /* Packet status - is not set as initially
54111 +                                * it is set to 0 and if packet was sent
54112 +                                successfully, status field will remain 0*/
54113 +
54114 +                               /* Bytes has been transfered */
54115 +                               packet_info->length =
54116 +                                   (ep->maxpacket <
54117 +                                    frame_data) ? ep->maxpacket : frame_data;
54118 +
54119 +                               /* Received packet offset */
54120 +                               packet_info->offset = offset;
54121 +                               offset += packet_info->length;
54122 +                               frame_data -= packet_info->length;
54123 +
54124 +                               packet_info++;
54125 +                       }
54126 +               }
54127 +               return 1;
54128 +       } else {
54129 +               /* This is a workaround for in case of Transfer Complete with
54130 +                * PktDrpSts interrupts merging - in this case Transfer complete
54131 +                * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
54132 +                * set and with DOEPTSIZ register non zero. Investigations showed,
54133 +                * that this happens when Out packet is dropped, but because of
54134 +                * interrupts merging during first interrupt handling PktDrpSts
54135 +                * bit is cleared and for next merged interrupts it is not reset.
54136 +                * In this case SW hadles the interrupt as if PktDrpSts bit is set.
54137 +                */
54138 +               if (ep->is_in) {
54139 +                       return 1;
54140 +               } else {
54141 +                       return handle_iso_out_pkt_dropped(core_if, ep);
54142 +               }
54143 +       }
54144 +}
54145 +
54146 +/**
54147 + * This function is to handle Iso EP transfer complete interrupt
54148 + *
54149 + * @param pcd The PCD
54150 + * @param ep The EP for which transfer complete was asserted
54151 + *
54152 + */
54153 +static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
54154 +{
54155 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
54156 +       dwc_ep_t *dwc_ep = &ep->dwc_ep;
54157 +       uint8_t is_last = 0;
54158 +
54159 +       if (ep->dwc_ep.next_frame == 0xffffffff) {
54160 +               DWC_WARN("Next frame is not set!\n");
54161 +               return;
54162 +       }
54163 +
54164 +       if (core_if->dma_enable) {
54165 +               if (core_if->dma_desc_enable) {
54166 +                       set_ddma_iso_pkts_info(core_if, dwc_ep);
54167 +                       reinit_ddma_iso_xfer(core_if, dwc_ep);
54168 +                       is_last = 1;
54169 +               } else {
54170 +                       if (core_if->pti_enh_enable) {
54171 +                               if (set_iso_pkts_info(core_if, dwc_ep)) {
54172 +                                       dwc_ep->proc_buf_num =
54173 +                                           (dwc_ep->proc_buf_num ^ 1) & 0x1;
54174 +                                       dwc_otg_iso_ep_start_buf_transfer
54175 +                                           (core_if, dwc_ep);
54176 +                                       is_last = 1;
54177 +                               }
54178 +                       } else {
54179 +                               set_current_pkt_info(core_if, dwc_ep);
54180 +                               if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
54181 +                                       is_last = 1;
54182 +                                       dwc_ep->cur_pkt = 0;
54183 +                                       dwc_ep->proc_buf_num =
54184 +                                           (dwc_ep->proc_buf_num ^ 1) & 0x1;
54185 +                                       if (dwc_ep->proc_buf_num) {
54186 +                                               dwc_ep->cur_pkt_addr =
54187 +                                                   dwc_ep->xfer_buff1;
54188 +                                               dwc_ep->cur_pkt_dma_addr =
54189 +                                                   dwc_ep->dma_addr1;
54190 +                                       } else {
54191 +                                               dwc_ep->cur_pkt_addr =
54192 +                                                   dwc_ep->xfer_buff0;
54193 +                                               dwc_ep->cur_pkt_dma_addr =
54194 +                                                   dwc_ep->dma_addr0;
54195 +                                       }
54196 +
54197 +                               }
54198 +                               dwc_otg_iso_ep_start_frm_transfer(core_if,
54199 +                                                                 dwc_ep);
54200 +                       }
54201 +               }
54202 +       } else {
54203 +               set_current_pkt_info(core_if, dwc_ep);
54204 +               if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
54205 +                       is_last = 1;
54206 +                       dwc_ep->cur_pkt = 0;
54207 +                       dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
54208 +                       if (dwc_ep->proc_buf_num) {
54209 +                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
54210 +                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
54211 +                       } else {
54212 +                               dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
54213 +                               dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
54214 +                       }
54215 +
54216 +               }
54217 +               dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
54218 +       }
54219 +       if (is_last)
54220 +               dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
54221 +}
54222 +#endif /* DWC_EN_ISOC */
54223 +
54224 +/**
54225 + * This function handle BNA interrupt for Non Isochronous EPs
54226 + *
54227 + */
54228 +static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
54229 +{
54230 +       dwc_ep_t *dwc_ep = &ep->dwc_ep;
54231 +       volatile uint32_t *addr;
54232 +       depctl_data_t depctl = {.d32 = 0 };
54233 +       dwc_otg_pcd_t *pcd = ep->pcd;
54234 +       dwc_otg_dev_dma_desc_t *dma_desc;
54235 +       dev_dma_desc_sts_t sts = {.d32 = 0 };
54236 +       dwc_otg_core_if_t *core_if = ep->pcd->core_if;
54237 +       int i, start;
54238 +
54239 +       if (!dwc_ep->desc_cnt)
54240 +               DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num,
54241 +                        (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt);
54242 +
54243 +       if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
54244 +                                                       && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
54245 +               uint32_t doepdma;
54246 +               dwc_otg_dev_out_ep_regs_t *out_regs =
54247 +                       core_if->dev_if->out_ep_regs[dwc_ep->num];
54248 +               doepdma = DWC_READ_REG32(&(out_regs->doepdma));
54249 +               start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
54250 +               dma_desc = &(dwc_ep->desc_addr[start]);
54251 +       } else {
54252 +               start = 0;
54253 +               dma_desc = dwc_ep->desc_addr;
54254 +       }
54255 +
54256 +
54257 +       for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
54258 +               sts.d32 = dma_desc->status.d32;
54259 +               sts.b.bs = BS_HOST_READY;
54260 +               dma_desc->status.d32 = sts.d32;
54261 +       }
54262 +
54263 +       if (dwc_ep->is_in == 0) {
54264 +               addr =
54265 +                   &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
54266 +                   doepctl;
54267 +       } else {
54268 +               addr =
54269 +                   &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
54270 +       }
54271 +       depctl.b.epena = 1;
54272 +       depctl.b.cnak = 1;
54273 +       DWC_MODIFY_REG32(addr, 0, depctl.d32);
54274 +}
54275 +
54276 +/**
54277 + * This function handles EP0 Control transfers.
54278 + *
54279 + * The state of the control transfers are tracked in
54280 + * <code>ep0state</code>.
54281 + */
54282 +static void handle_ep0(dwc_otg_pcd_t * pcd)
54283 +{
54284 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
54285 +       dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
54286 +       dev_dma_desc_sts_t desc_sts;
54287 +       deptsiz0_data_t deptsiz;
54288 +       uint32_t byte_count;
54289 +
54290 +#ifdef DEBUG_EP0
54291 +       DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
54292 +       print_ep0_state(pcd);
54293 +#endif
54294 +
54295 +//      DWC_PRINTF("HANDLE EP0\n");
54296 +
54297 +       switch (pcd->ep0state) {
54298 +       case EP0_DISCONNECT:
54299 +               break;
54300 +
54301 +       case EP0_IDLE:
54302 +               pcd->request_config = 0;
54303 +
54304 +               pcd_setup(pcd);
54305 +               break;
54306 +
54307 +       case EP0_IN_DATA_PHASE:
54308 +#ifdef DEBUG_EP0
54309 +               DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
54310 +                           ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
54311 +                           ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
54312 +#endif
54313 +
54314 +               if (core_if->dma_enable != 0) {
54315 +                       /*
54316 +                        * For EP0 we can only program 1 packet at a time so we
54317 +                        * need to do the make calculations after each complete.
54318 +                        * Call write_packet to make the calculations, as in
54319 +                        * slave mode, and use those values to determine if we
54320 +                        * can complete.
54321 +                        */
54322 +                       if (core_if->dma_desc_enable == 0) {
54323 +                               deptsiz.d32 =
54324 +                                   DWC_READ_REG32(&core_if->
54325 +                                                  dev_if->in_ep_regs[0]->
54326 +                                                  dieptsiz);
54327 +                               byte_count =
54328 +                                   ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
54329 +                       } else {
54330 +                               desc_sts =
54331 +                                   core_if->dev_if->in_desc_addr->status;
54332 +                               byte_count =
54333 +                                   ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
54334 +                       }
54335 +                       ep0->dwc_ep.xfer_count += byte_count;
54336 +                       ep0->dwc_ep.xfer_buff += byte_count;
54337 +                       ep0->dwc_ep.dma_addr += byte_count;
54338 +               }
54339 +               if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
54340 +                       dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54341 +                                                     &ep0->dwc_ep);
54342 +                       DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
54343 +               } else if (ep0->dwc_ep.sent_zlp) {
54344 +                       dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54345 +                                                     &ep0->dwc_ep);
54346 +                       ep0->dwc_ep.sent_zlp = 0;
54347 +                       DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
54348 +               } else {
54349 +                       ep0_complete_request(ep0);
54350 +                       DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
54351 +               }
54352 +               break;
54353 +       case EP0_OUT_DATA_PHASE:
54354 +#ifdef DEBUG_EP0
54355 +               DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
54356 +                           ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
54357 +                           ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
54358 +#endif
54359 +               if (core_if->dma_enable != 0) {
54360 +                       if (core_if->dma_desc_enable == 0) {
54361 +                               deptsiz.d32 =
54362 +                                   DWC_READ_REG32(&core_if->
54363 +                                                  dev_if->out_ep_regs[0]->
54364 +                                                  doeptsiz);
54365 +                               byte_count =
54366 +                                   ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
54367 +                       } else {
54368 +                               desc_sts =
54369 +                                   core_if->dev_if->out_desc_addr->status;
54370 +                               byte_count =
54371 +                                   ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
54372 +                       }
54373 +                       ep0->dwc_ep.xfer_count += byte_count;
54374 +                       ep0->dwc_ep.xfer_buff += byte_count;
54375 +                       ep0->dwc_ep.dma_addr += byte_count;
54376 +               }
54377 +               if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
54378 +                       dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54379 +                                                     &ep0->dwc_ep);
54380 +                       DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
54381 +               } else if (ep0->dwc_ep.sent_zlp) {
54382 +                       dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
54383 +                                                     &ep0->dwc_ep);
54384 +                       ep0->dwc_ep.sent_zlp = 0;
54385 +                       DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n");
54386 +               } else {
54387 +                       ep0_complete_request(ep0);
54388 +                       DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
54389 +               }
54390 +               break;
54391 +
54392 +       case EP0_IN_STATUS_PHASE:
54393 +       case EP0_OUT_STATUS_PHASE:
54394 +               DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
54395 +               ep0_complete_request(ep0);
54396 +               pcd->ep0state = EP0_IDLE;
54397 +               ep0->stopped = 1;
54398 +               ep0->dwc_ep.is_in = 0;  /* OUT for next SETUP */
54399 +
54400 +               /* Prepare for more SETUP Packets */
54401 +               if (core_if->dma_enable) {
54402 +                       ep0_out_start(core_if, pcd);
54403 +               }
54404 +               break;
54405 +
54406 +       case EP0_STALL:
54407 +               DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
54408 +               break;
54409 +       }
54410 +#ifdef DEBUG_EP0
54411 +       print_ep0_state(pcd);
54412 +#endif
54413 +}
54414 +
54415 +/**
54416 + * Restart transfer
54417 + */
54418 +static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
54419 +{
54420 +       dwc_otg_core_if_t *core_if;
54421 +       dwc_otg_dev_if_t *dev_if;
54422 +       deptsiz_data_t dieptsiz = {.d32 = 0 };
54423 +       dwc_otg_pcd_ep_t *ep;
54424 +
54425 +       ep = get_in_ep(pcd, epnum);
54426 +
54427 +#ifdef DWC_EN_ISOC
54428 +       if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
54429 +               return;
54430 +       }
54431 +#endif /* DWC_EN_ISOC  */
54432 +
54433 +       core_if = GET_CORE_IF(pcd);
54434 +       dev_if = core_if->dev_if;
54435 +
54436 +       dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
54437 +
54438 +       DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
54439 +                   " stopped=%d\n", ep->dwc_ep.xfer_buff,
54440 +                   ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
54441 +       /*
54442 +        * If xfersize is 0 and pktcnt in not 0, resend the last packet.
54443 +        */
54444 +       if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
54445 +           ep->dwc_ep.start_xfer_buff != 0) {
54446 +               if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
54447 +                       ep->dwc_ep.xfer_count = 0;
54448 +                       ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
54449 +                       ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
54450 +               } else {
54451 +                       ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
54452 +                       /* convert packet size to dwords. */
54453 +                       ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
54454 +                       ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
54455 +               }
54456 +               ep->stopped = 0;
54457 +               DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
54458 +                           "xfer_len=%0x stopped=%d\n",
54459 +                           ep->dwc_ep.xfer_buff,
54460 +                           ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
54461 +                           ep->stopped);
54462 +               if (epnum == 0) {
54463 +                       dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
54464 +               } else {
54465 +                       dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
54466 +               }
54467 +       }
54468 +}
54469 +
54470 +/*
54471 + * This function create new nextep sequnce based on Learn Queue.
54472 + *
54473 + * @param core_if Programming view of DWC_otg controller
54474 + */
54475 +void predict_nextep_seq( dwc_otg_core_if_t * core_if)
54476 +{
54477 +       dwc_otg_device_global_regs_t *dev_global_regs =
54478 +           core_if->dev_if->dev_global_regs;
54479 +       const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
54480 +       /* Number of Token Queue Registers */
54481 +       const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
54482 +       dtknq1_data_t dtknqr1;
54483 +       uint32_t in_tkn_epnums[4];
54484 +       uint8_t seqnum[MAX_EPS_CHANNELS];
54485 +       uint8_t intkn_seq[TOKEN_Q_DEPTH];
54486 +       grstctl_t resetctl = {.d32 = 0 };
54487 +       uint8_t temp;
54488 +       int ndx = 0;
54489 +       int start = 0;
54490 +       int end = 0;
54491 +       int sort_done = 0;
54492 +       int i = 0;
54493 +       volatile uint32_t *addr = &dev_global_regs->dtknqr1;
54494 +
54495 +
54496 +       DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
54497 +
54498 +       /* Read the DTKNQ Registers */
54499 +       for (i = 0; i < DTKNQ_REG_CNT; i++) {
54500 +               in_tkn_epnums[i] = DWC_READ_REG32(addr);
54501 +               DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
54502 +                           in_tkn_epnums[i]);
54503 +               if (addr == &dev_global_regs->dvbusdis) {
54504 +                       addr = &dev_global_regs->dtknqr3_dthrctl;
54505 +               } else {
54506 +                       ++addr;
54507 +               }
54508 +
54509 +       }
54510 +
54511 +       /* Copy the DTKNQR1 data to the bit field. */
54512 +       dtknqr1.d32 = in_tkn_epnums[0];
54513 +       if (dtknqr1.b.wrap_bit) {
54514 +               ndx = dtknqr1.b.intknwptr;
54515 +               end = ndx -1;
54516 +               if (end < 0)
54517 +                       end = TOKEN_Q_DEPTH -1;
54518 +       } else {
54519 +               ndx = 0;
54520 +               end = dtknqr1.b.intknwptr -1;
54521 +               if (end < 0)
54522 +                       end = 0;
54523 +       }
54524 +       start = ndx;
54525 +
54526 +       /* Fill seqnum[] by initial values: EP number + 31 */
54527 +       for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
54528 +               seqnum[i] = i +31;
54529 +       }
54530 +
54531 +       /* Fill intkn_seq[] from in_tkn_epnums[0] */
54532 +       for (i=0; i < 6; i++)
54533 +               intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
54534 +
54535 +       if (TOKEN_Q_DEPTH > 6) {
54536 +               /* Fill intkn_seq[] from in_tkn_epnums[1] */
54537 +               for (i=6; i < 14; i++)
54538 +                       intkn_seq[i] =
54539 +                           (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf;
54540 +       }
54541 +
54542 +       if (TOKEN_Q_DEPTH > 14) {
54543 +               /* Fill intkn_seq[] from in_tkn_epnums[1] */
54544 +               for (i=14; i < 22; i++)
54545 +                       intkn_seq[i] =
54546 +                           (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf;
54547 +       }
54548 +
54549 +       if (TOKEN_Q_DEPTH > 22) {
54550 +               /* Fill intkn_seq[] from in_tkn_epnums[1] */
54551 +               for (i=22; i < 30; i++)
54552 +                       intkn_seq[i] =
54553 +                           (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf;
54554 +       }
54555 +
54556 +       DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__,
54557 +                   start, end);
54558 +       for (i=0; i<TOKEN_Q_DEPTH; i++)
54559 +               DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
54560 +
54561 +       /* Update seqnum based on intkn_seq[] */
54562 +       i = 0;
54563 +       do {
54564 +               seqnum[intkn_seq[ndx]] = i;
54565 +               ndx++;
54566 +               i++;
54567 +               if (ndx == TOKEN_Q_DEPTH)
54568 +                       ndx = 0;
54569 +       } while ( i < TOKEN_Q_DEPTH );
54570 +
54571 +       /* Mark non active EP's in seqnum[] by 0xff */
54572 +       for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
54573 +               if (core_if->nextep_seq[i] == 0xff )
54574 +                       seqnum[i] = 0xff;
54575 +       }
54576 +
54577 +       /* Sort seqnum[] */
54578 +       sort_done = 0;
54579 +       while (!sort_done) {
54580 +               sort_done = 1;
54581 +               for (i=0; i<core_if->dev_if->num_in_eps; i++) {
54582 +                       if (seqnum[i] > seqnum[i+1]) {
54583 +                               temp = seqnum[i];
54584 +                               seqnum[i] = seqnum[i+1];
54585 +                               seqnum[i+1] = temp;
54586 +                               sort_done = 0;
54587 +                       }
54588 +               }
54589 +       }
54590 +
54591 +       ndx = start + seqnum[0];
54592 +       if (ndx >= TOKEN_Q_DEPTH)
54593 +               ndx = ndx % TOKEN_Q_DEPTH;
54594 +       core_if->first_in_nextep_seq = intkn_seq[ndx];
54595 +
54596 +       /* Update seqnum[] by EP numbers  */
54597 +       for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
54598 +               ndx = start + i;
54599 +               if (seqnum[i] < 31) {
54600 +                       ndx = start + seqnum[i];
54601 +                       if (ndx >= TOKEN_Q_DEPTH)
54602 +                               ndx = ndx % TOKEN_Q_DEPTH;
54603 +                       seqnum[i] = intkn_seq[ndx];
54604 +               } else {
54605 +                       if (seqnum[i] < 0xff) {
54606 +                               seqnum[i] = seqnum[i] - 31;
54607 +                       } else {
54608 +                               break;
54609 +                       }
54610 +               }
54611 +       }
54612 +
54613 +       /* Update nextep_seq[] based on seqnum[] */
54614 +       for (i=0; i<core_if->dev_if->num_in_eps; i++) {
54615 +               if (seqnum[i] != 0xff) {
54616 +                       if (seqnum[i+1] != 0xff) {
54617 +                               core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
54618 +                       } else {
54619 +                               core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
54620 +                               break;
54621 +                       }
54622 +               } else {
54623 +                       break;
54624 +               }
54625 +       }
54626 +
54627 +       DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
54628 +               __func__, core_if->first_in_nextep_seq);
54629 +       for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
54630 +               DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
54631 +       }
54632 +
54633 +       /* Flush the Learning Queue */
54634 +       resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
54635 +       resetctl.b.intknqflsh = 1;
54636 +       DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
54637 +
54638 +
54639 +}
54640 +
54641 +/**
54642 + * handle the IN EP disable interrupt.
54643 + */
54644 +static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
54645 +                                            const uint32_t epnum)
54646 +{
54647 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
54648 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
54649 +       deptsiz_data_t dieptsiz = {.d32 = 0 };
54650 +       dctl_data_t dctl = {.d32 = 0 };
54651 +       dwc_otg_pcd_ep_t *ep;
54652 +       dwc_ep_t *dwc_ep;
54653 +       gintmsk_data_t gintmsk_data;
54654 +       depctl_data_t depctl;
54655 +       uint32_t diepdma;
54656 +       uint32_t remain_to_transfer = 0;
54657 +       uint8_t i;
54658 +       uint32_t xfer_size;
54659 +
54660 +       ep = get_in_ep(pcd, epnum);
54661 +       dwc_ep = &ep->dwc_ep;
54662 +
54663 +       if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
54664 +               dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
54665 +               complete_ep(ep);
54666 +               return;
54667 +       }
54668 +
54669 +       DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
54670 +                   DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
54671 +       dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
54672 +       depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
54673 +
54674 +       DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
54675 +                   dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
54676 +
54677 +       if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) {
54678 +               if (ep->stopped) {
54679 +                       if (core_if->en_multiple_tx_fifo)
54680 +                               /* Flush the Tx FIFO */
54681 +                               dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
54682 +                       /* Clear the Global IN NP NAK */
54683 +                       dctl.d32 = 0;
54684 +                       dctl.b.cgnpinnak = 1;
54685 +                       DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
54686 +                       /* Restart the transaction */
54687 +                       if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
54688 +                               restart_transfer(pcd, epnum);
54689 +                       }
54690 +               } else {
54691 +                       /* Restart the transaction */
54692 +                       if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
54693 +                               restart_transfer(pcd, epnum);
54694 +                       }
54695 +                       DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
54696 +               }
54697 +               return;
54698 +       }
54699 +
54700 +       if (core_if->start_predict > 2) {       // NP IN EP
54701 +               core_if->start_predict--;
54702 +               return;
54703 +       }
54704 +
54705 +       core_if->start_predict--;
54706 +
54707 +       if (core_if->start_predict == 1) {      // All NP IN Ep's disabled now
54708 +
54709 +               predict_nextep_seq(core_if);
54710 +
54711 +               /* Update all active IN EP's NextEP field based of nextep_seq[] */
54712 +               for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
54713 +                       depctl.d32 =
54714 +                           DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
54715 +                       if (core_if->nextep_seq[i] != 0xff) {   // Active NP IN EP
54716 +                               depctl.b.nextep = core_if->nextep_seq[i];
54717 +                               DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
54718 +                       }
54719 +               }
54720 +               /* Flush Shared NP TxFIFO */
54721 +               dwc_otg_flush_tx_fifo(core_if, 0);
54722 +               /* Rewind buffers */
54723 +               if (!core_if->dma_desc_enable) {
54724 +                       i = core_if->first_in_nextep_seq;
54725 +                       do {
54726 +                               ep = get_in_ep(pcd, i);
54727 +                               dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
54728 +                               xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
54729 +                               if (xfer_size > ep->dwc_ep.maxxfer)
54730 +                                       xfer_size = ep->dwc_ep.maxxfer;
54731 +                               depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
54732 +                               if (dieptsiz.b.pktcnt != 0) {
54733 +                                       if (xfer_size == 0) {
54734 +                                               remain_to_transfer = 0;
54735 +                                       } else {
54736 +                                               if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
54737 +                                                       remain_to_transfer =
54738 +                                                               dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
54739 +                                               } else {
54740 +                                                       remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket)
54741 +                                                               + (xfer_size % ep->dwc_ep.maxpacket);
54742 +                                               }
54743 +                                       }
54744 +                                       diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
54745 +                                       dieptsiz.b.xfersize = remain_to_transfer;
54746 +                                       DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
54747 +                                       diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
54748 +                                       DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
54749 +                               }
54750 +                               i = core_if->nextep_seq[i];
54751 +                       } while (i != core_if->first_in_nextep_seq);
54752 +               } else { // dma_desc_enable
54753 +                               DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
54754 +               }
54755 +
54756 +               /* Restart transfers in predicted sequences */
54757 +               i = core_if->first_in_nextep_seq;
54758 +               do {
54759 +                       dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
54760 +                       depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
54761 +                       if (dieptsiz.b.pktcnt != 0) {
54762 +                               depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
54763 +                               depctl.b.epena = 1;
54764 +                               depctl.b.cnak = 1;
54765 +                               DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
54766 +                       }
54767 +                       i = core_if->nextep_seq[i];
54768 +               } while (i != core_if->first_in_nextep_seq);
54769 +
54770 +               /* Clear the global non-periodic IN NAK handshake */
54771 +               dctl.d32 = 0;
54772 +               dctl.b.cgnpinnak = 1;
54773 +               DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
54774 +
54775 +               /* Unmask EP Mismatch interrupt */
54776 +               gintmsk_data.d32 = 0;
54777 +               gintmsk_data.b.epmismatch = 1;
54778 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
54779 +
54780 +               core_if->start_predict = 0;
54781 +
54782 +       }
54783 +}
54784 +
54785 +/**
54786 + * Handler for the IN EP timeout handshake interrupt.
54787 + */
54788 +static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
54789 +                                            const uint32_t epnum)
54790 +{
54791 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
54792 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
54793 +
54794 +#ifdef DEBUG
54795 +       deptsiz_data_t dieptsiz = {.d32 = 0 };
54796 +       uint32_t num = 0;
54797 +#endif
54798 +       dctl_data_t dctl = {.d32 = 0 };
54799 +       dwc_otg_pcd_ep_t *ep;
54800 +
54801 +       gintmsk_data_t intr_mask = {.d32 = 0 };
54802 +
54803 +       ep = get_in_ep(pcd, epnum);
54804 +
54805 +       /* Disable the NP Tx Fifo Empty Interrrupt */
54806 +       if (!core_if->dma_enable) {
54807 +               intr_mask.b.nptxfempty = 1;
54808 +               DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
54809 +                                intr_mask.d32, 0);
54810 +       }
54811 +       /** @todo NGS Check EP type.
54812 +        * Implement for Periodic EPs */
54813 +       /*
54814 +        * Non-periodic EP
54815 +        */
54816 +       /* Enable the Global IN NAK Effective Interrupt */
54817 +       intr_mask.b.ginnakeff = 1;
54818 +       DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
54819 +
54820 +       /* Set Global IN NAK */
54821 +       dctl.b.sgnpinnak = 1;
54822 +       DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
54823 +
54824 +       ep->stopped = 1;
54825 +
54826 +#ifdef DEBUG
54827 +       dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
54828 +       DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
54829 +                   dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
54830 +#endif
54831 +
54832 +#ifdef DISABLE_PERIODIC_EP
54833 +       /*
54834 +        * Set the NAK bit for this EP to
54835 +        * start the disable process.
54836 +        */
54837 +       diepctl.d32 = 0;
54838 +       diepctl.b.snak = 1;
54839 +       DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
54840 +                        diepctl.d32);
54841 +       ep->disabling = 1;
54842 +       ep->stopped = 1;
54843 +#endif
54844 +}
54845 +
54846 +/**
54847 + * Handler for the IN EP NAK interrupt.
54848 + */
54849 +static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
54850 +                                           const uint32_t epnum)
54851 +{
54852 +       /** @todo implement ISR */
54853 +       dwc_otg_core_if_t *core_if;
54854 +       diepmsk_data_t intr_mask = {.d32 = 0 };
54855 +
54856 +       DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
54857 +       core_if = GET_CORE_IF(pcd);
54858 +       intr_mask.b.nak = 1;
54859 +
54860 +       if (core_if->multiproc_int_enable) {
54861 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
54862 +                                diepeachintmsk[epnum], intr_mask.d32, 0);
54863 +       } else {
54864 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
54865 +                                intr_mask.d32, 0);
54866 +       }
54867 +
54868 +       return 1;
54869 +}
54870 +
54871 +/**
54872 + * Handler for the OUT EP Babble interrupt.
54873 + */
54874 +static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
54875 +                                               const uint32_t epnum)
54876 +{
54877 +       /** @todo implement ISR */
54878 +       dwc_otg_core_if_t *core_if;
54879 +       doepmsk_data_t intr_mask = {.d32 = 0 };
54880 +
54881 +       DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
54882 +                  "OUT EP Babble");
54883 +       core_if = GET_CORE_IF(pcd);
54884 +       intr_mask.b.babble = 1;
54885 +
54886 +       if (core_if->multiproc_int_enable) {
54887 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
54888 +                                doepeachintmsk[epnum], intr_mask.d32, 0);
54889 +       } else {
54890 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
54891 +                                intr_mask.d32, 0);
54892 +       }
54893 +
54894 +       return 1;
54895 +}
54896 +
54897 +/**
54898 + * Handler for the OUT EP NAK interrupt.
54899 + */
54900 +static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
54901 +                                            const uint32_t epnum)
54902 +{
54903 +       /** @todo implement ISR */
54904 +       dwc_otg_core_if_t *core_if;
54905 +       doepmsk_data_t intr_mask = {.d32 = 0 };
54906 +
54907 +       DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
54908 +       core_if = GET_CORE_IF(pcd);
54909 +       intr_mask.b.nak = 1;
54910 +
54911 +       if (core_if->multiproc_int_enable) {
54912 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
54913 +                                doepeachintmsk[epnum], intr_mask.d32, 0);
54914 +       } else {
54915 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
54916 +                                intr_mask.d32, 0);
54917 +       }
54918 +
54919 +       return 1;
54920 +}
54921 +
54922 +/**
54923 + * Handler for the OUT EP NYET interrupt.
54924 + */
54925 +static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
54926 +                                             const uint32_t epnum)
54927 +{
54928 +       /** @todo implement ISR */
54929 +       dwc_otg_core_if_t *core_if;
54930 +       doepmsk_data_t intr_mask = {.d32 = 0 };
54931 +
54932 +       DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
54933 +       core_if = GET_CORE_IF(pcd);
54934 +       intr_mask.b.nyet = 1;
54935 +
54936 +       if (core_if->multiproc_int_enable) {
54937 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
54938 +                                doepeachintmsk[epnum], intr_mask.d32, 0);
54939 +       } else {
54940 +               DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
54941 +                                intr_mask.d32, 0);
54942 +       }
54943 +
54944 +       return 1;
54945 +}
54946 +
54947 +/**
54948 + * This interrupt indicates that an IN EP has a pending Interrupt.
54949 + * The sequence for handling the IN EP interrupt is shown below:
54950 + * -#  Read the Device All Endpoint Interrupt register
54951 + * -#  Repeat the following for each IN EP interrupt bit set (from
54952 + *             LSB to MSB).
54953 + * -#  Read the Device Endpoint Interrupt (DIEPINTn) register
54954 + * -#  If "Transfer Complete" call the request complete function
54955 + * -#  If "Endpoint Disabled" complete the EP disable procedure.
54956 + * -#  If "AHB Error Interrupt" log error
54957 + * -#  If "Time-out Handshake" log error
54958 + * -#  If "IN Token Received when TxFIFO Empty" write packet to Tx
54959 + *             FIFO.
54960 + * -#  If "IN Token EP Mismatch" (disable, this is handled by EP
54961 + *             Mismatch Interrupt)
54962 + */
54963 +static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
54964 +{
54965 +#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
54966 +do { \
54967 +               diepint_data_t diepint = {.d32=0}; \
54968 +               diepint.b.__intr = 1; \
54969 +               DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
54970 +               diepint.d32); \
54971 +} while (0)
54972 +
54973 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
54974 +       dwc_otg_dev_if_t *dev_if = core_if->dev_if;
54975 +       diepint_data_t diepint = {.d32 = 0 };
54976 +       depctl_data_t depctl = {.d32 = 0 };
54977 +       uint32_t ep_intr;
54978 +       uint32_t epnum = 0;
54979 +       dwc_otg_pcd_ep_t *ep;
54980 +       dwc_ep_t *dwc_ep;
54981 +       gintmsk_data_t intr_mask = {.d32 = 0 };
54982 +
54983 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
54984 +
54985 +       /* Read in the device interrupt bits */
54986 +       ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
54987 +
54988 +       /* Service the Device IN interrupts for each endpoint */
54989 +       while (ep_intr) {
54990 +               if (ep_intr & 0x1) {
54991 +                       uint32_t empty_msk;
54992 +                       /* Get EP pointer */
54993 +                       ep = get_in_ep(pcd, epnum);
54994 +                       dwc_ep = &ep->dwc_ep;
54995 +
54996 +                       depctl.d32 =
54997 +                           DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
54998 +                       empty_msk =
54999 +                           DWC_READ_REG32(&dev_if->
55000 +                                          dev_global_regs->dtknqr4_fifoemptymsk);
55001 +
55002 +                       DWC_DEBUGPL(DBG_PCDV,
55003 +                                   "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
55004 +                                   epnum, empty_msk, depctl.d32);
55005 +
55006 +                       DWC_DEBUGPL(DBG_PCD,
55007 +                                   "EP%d-%s: type=%d, mps=%d\n",
55008 +                                   dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
55009 +                                   dwc_ep->type, dwc_ep->maxpacket);
55010 +
55011 +                       diepint.d32 =
55012 +                           dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
55013 +
55014 +                       DWC_DEBUGPL(DBG_PCDV,
55015 +                                   "EP %d Interrupt Register - 0x%x\n", epnum,
55016 +                                   diepint.d32);
55017 +                       /* Transfer complete */
55018 +                       if (diepint.b.xfercompl) {
55019 +                               /* Disable the NP Tx FIFO Empty
55020 +                                * Interrupt */
55021 +                               if (core_if->en_multiple_tx_fifo == 0) {
55022 +                                       intr_mask.b.nptxfempty = 1;
55023 +                                       DWC_MODIFY_REG32
55024 +                                           (&core_if->core_global_regs->gintmsk,
55025 +                                            intr_mask.d32, 0);
55026 +                               } else {
55027 +                                       /* Disable the Tx FIFO Empty Interrupt for this EP */
55028 +                                       uint32_t fifoemptymsk =
55029 +                                           0x1 << dwc_ep->num;
55030 +                                       DWC_MODIFY_REG32(&core_if->
55031 +                                                        dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
55032 +                                                        fifoemptymsk, 0);
55033 +                               }
55034 +                               /* Clear the bit in DIEPINTn for this interrupt */
55035 +                               CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
55036 +
55037 +                               /* Complete the transfer */
55038 +                               if (epnum == 0) {
55039 +                                       handle_ep0(pcd);
55040 +                               }
55041 +#ifdef DWC_EN_ISOC
55042 +                               else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55043 +                                       if (!ep->stopped)
55044 +                                               complete_iso_ep(pcd, ep);
55045 +                               }
55046 +#endif /* DWC_EN_ISOC */
55047 +#ifdef DWC_UTE_PER_IO
55048 +                               else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55049 +                                       if (!ep->stopped)
55050 +                                               complete_xiso_ep(ep);
55051 +                               }
55052 +#endif /* DWC_UTE_PER_IO */
55053 +                               else {
55054 +                                       if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC &&
55055 +                                                       dwc_ep->bInterval > 1) {
55056 +                                               dwc_ep->frame_num += dwc_ep->bInterval;
55057 +                                               if (dwc_ep->frame_num > 0x3FFF)
55058 +                                               {
55059 +                                                       dwc_ep->frm_overrun = 1;
55060 +                                                       dwc_ep->frame_num &= 0x3FFF;
55061 +                                               } else
55062 +                                                       dwc_ep->frm_overrun = 0;
55063 +                                       }
55064 +                                       complete_ep(ep);
55065 +                                       if(diepint.b.nak)
55066 +                                               CLEAR_IN_EP_INTR(core_if, epnum, nak);
55067 +                               }
55068 +                       }
55069 +                       /* Endpoint disable      */
55070 +                       if (diepint.b.epdisabled) {
55071 +                               DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
55072 +                                           epnum);
55073 +                               handle_in_ep_disable_intr(pcd, epnum);
55074 +
55075 +                               /* Clear the bit in DIEPINTn for this interrupt */
55076 +                               CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
55077 +                       }
55078 +                       /* AHB Error */
55079 +                       if (diepint.b.ahberr) {
55080 +                               DWC_ERROR("EP%d IN AHB Error\n", epnum);
55081 +                               /* Clear the bit in DIEPINTn for this interrupt */
55082 +                               CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
55083 +                       }
55084 +                       /* TimeOUT Handshake (non-ISOC IN EPs) */
55085 +                       if (diepint.b.timeout) {
55086 +                               DWC_ERROR("EP%d IN Time-out\n", epnum);
55087 +                               handle_in_ep_timeout_intr(pcd, epnum);
55088 +
55089 +                               CLEAR_IN_EP_INTR(core_if, epnum, timeout);
55090 +                       }
55091 +                       /** IN Token received with TxF Empty */
55092 +                       if (diepint.b.intktxfemp) {
55093 +                               DWC_DEBUGPL(DBG_ANY,
55094 +                                           "EP%d IN TKN TxFifo Empty\n",
55095 +                                           epnum);
55096 +                               if (!ep->stopped && epnum != 0) {
55097 +
55098 +                                       diepmsk_data_t diepmsk = {.d32 = 0 };
55099 +                                       diepmsk.b.intktxfemp = 1;
55100 +
55101 +                                       if (core_if->multiproc_int_enable) {
55102 +                                               DWC_MODIFY_REG32
55103 +                                                   (&dev_if->dev_global_regs->diepeachintmsk
55104 +                                                    [epnum], diepmsk.d32, 0);
55105 +                                       } else {
55106 +                                               DWC_MODIFY_REG32
55107 +                                                   (&dev_if->dev_global_regs->diepmsk,
55108 +                                                    diepmsk.d32, 0);
55109 +                                       }
55110 +                               } else if (core_if->dma_desc_enable
55111 +                                          && epnum == 0
55112 +                                          && pcd->ep0state ==
55113 +                                          EP0_OUT_STATUS_PHASE) {
55114 +                                       // EP0 IN set STALL
55115 +                                       depctl.d32 =
55116 +                                           DWC_READ_REG32(&dev_if->in_ep_regs
55117 +                                                          [epnum]->diepctl);
55118 +
55119 +                                       /* set the disable and stall bits */
55120 +                                       if (depctl.b.epena) {
55121 +                                               depctl.b.epdis = 1;
55122 +                                       }
55123 +                                       depctl.b.stall = 1;
55124 +                                       DWC_WRITE_REG32(&dev_if->in_ep_regs
55125 +                                                       [epnum]->diepctl,
55126 +                                                       depctl.d32);
55127 +                               }
55128 +                               CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
55129 +                       }
55130 +                       /** IN Token Received with EP mismatch */
55131 +                       if (diepint.b.intknepmis) {
55132 +                               DWC_DEBUGPL(DBG_ANY,
55133 +                                           "EP%d IN TKN EP Mismatch\n", epnum);
55134 +                               CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
55135 +                       }
55136 +                       /** IN Endpoint NAK Effective */
55137 +                       if (diepint.b.inepnakeff) {
55138 +                               DWC_DEBUGPL(DBG_ANY,
55139 +                                           "EP%d IN EP NAK Effective\n",
55140 +                                           epnum);
55141 +                               /* Periodic EP */
55142 +                               if (ep->disabling) {
55143 +                                       depctl.d32 = 0;
55144 +                                       depctl.b.snak = 1;
55145 +                                       depctl.b.epdis = 1;
55146 +                                       DWC_MODIFY_REG32(&dev_if->in_ep_regs
55147 +                                                        [epnum]->diepctl,
55148 +                                                        depctl.d32,
55149 +                                                        depctl.d32);
55150 +                               }
55151 +                               CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
55152 +
55153 +                       }
55154 +
55155 +                       /** IN EP Tx FIFO Empty Intr */
55156 +                       if (diepint.b.emptyintr) {
55157 +                               DWC_DEBUGPL(DBG_ANY,
55158 +                                           "EP%d Tx FIFO Empty Intr \n",
55159 +                                           epnum);
55160 +                               write_empty_tx_fifo(pcd, epnum);
55161 +
55162 +                               CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
55163 +
55164 +                       }
55165 +
55166 +                       /** IN EP BNA Intr */
55167 +                       if (diepint.b.bna) {
55168 +                               CLEAR_IN_EP_INTR(core_if, epnum, bna);
55169 +                               if (core_if->dma_desc_enable) {
55170 +#ifdef DWC_EN_ISOC
55171 +                                       if (dwc_ep->type ==
55172 +                                           DWC_OTG_EP_TYPE_ISOC) {
55173 +                                               /*
55174 +                                                * This checking is performed to prevent first "false" BNA
55175 +                                                * handling occuring right after reconnect
55176 +                                                */
55177 +                                               if (dwc_ep->next_frame !=
55178 +                                                   0xffffffff)
55179 +                                                       dwc_otg_pcd_handle_iso_bna(ep);
55180 +                                       } else
55181 +#endif                         /* DWC_EN_ISOC */
55182 +                                       {
55183 +                                               dwc_otg_pcd_handle_noniso_bna(ep);
55184 +                                       }
55185 +                               }
55186 +                       }
55187 +                       /* NAK Interrutp */
55188 +                       if (diepint.b.nak) {
55189 +                               DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
55190 +                                           epnum);
55191 +                               if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
55192 +                                       depctl_data_t depctl;
55193 +                                       if (ep->dwc_ep.frame_num == 0xFFFFFFFF) {
55194 +                                               ep->dwc_ep.frame_num = core_if->frame_num;
55195 +                                               if (ep->dwc_ep.bInterval > 1) {
55196 +                                                       depctl.d32 = 0;
55197 +                                                       depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
55198 +                                                       if (ep->dwc_ep.frame_num & 0x1) {
55199 +                                                               depctl.b.setd1pid = 1;
55200 +                                                               depctl.b.setd0pid = 0;
55201 +                                                       } else {
55202 +                                                               depctl.b.setd0pid = 1;
55203 +                                                               depctl.b.setd1pid = 0;
55204 +                                                       }
55205 +                                                       DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
55206 +                                               }
55207 +                                               start_next_request(ep);
55208 +                                       }
55209 +                                       ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
55210 +                                       if (dwc_ep->frame_num > 0x3FFF) {
55211 +                                               dwc_ep->frm_overrun = 1;
55212 +                                               dwc_ep->frame_num &= 0x3FFF;
55213 +                                       } else
55214 +                                               dwc_ep->frm_overrun = 0;
55215 +                               }
55216 +
55217 +                               CLEAR_IN_EP_INTR(core_if, epnum, nak);
55218 +                       }
55219 +               }
55220 +               epnum++;
55221 +               ep_intr >>= 1;
55222 +       }
55223 +
55224 +       return 1;
55225 +#undef CLEAR_IN_EP_INTR
55226 +}
55227 +
55228 +/**
55229 + * This interrupt indicates that an OUT EP has a pending Interrupt.
55230 + * The sequence for handling the OUT EP interrupt is shown below:
55231 + * -#  Read the Device All Endpoint Interrupt register
55232 + * -#  Repeat the following for each OUT EP interrupt bit set (from
55233 + *             LSB to MSB).
55234 + * -#  Read the Device Endpoint Interrupt (DOEPINTn) register
55235 + * -#  If "Transfer Complete" call the request complete function
55236 + * -#  If "Endpoint Disabled" complete the EP disable procedure.
55237 + * -#  If "AHB Error Interrupt" log error
55238 + * -#  If "Setup Phase Done" process Setup Packet (See Standard USB
55239 + *             Command Processing)
55240 + */
55241 +static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
55242 +{
55243 +#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
55244 +do { \
55245 +               doepint_data_t doepint = {.d32=0}; \
55246 +               doepint.b.__intr = 1; \
55247 +               DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
55248 +               doepint.d32); \
55249 +} while (0)
55250 +
55251 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
55252 +       uint32_t ep_intr;
55253 +       doepint_data_t doepint = {.d32 = 0 };
55254 +       uint32_t epnum = 0;
55255 +       dwc_otg_pcd_ep_t *ep;
55256 +       dwc_ep_t *dwc_ep;
55257 +       dctl_data_t dctl = {.d32 = 0 };
55258 +       gintmsk_data_t gintmsk = {.d32 = 0 };
55259 +
55260 +
55261 +       DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
55262 +
55263 +       /* Read in the device interrupt bits */
55264 +       ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
55265 +
55266 +       while (ep_intr) {
55267 +               if (ep_intr & 0x1) {
55268 +                       /* Get EP pointer */
55269 +                       ep = get_out_ep(pcd, epnum);
55270 +                       dwc_ep = &ep->dwc_ep;
55271 +
55272 +#ifdef VERBOSE
55273 +                       DWC_DEBUGPL(DBG_PCDV,
55274 +                                   "EP%d-%s: type=%d, mps=%d\n",
55275 +                                   dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
55276 +                                   dwc_ep->type, dwc_ep->maxpacket);
55277 +#endif
55278 +                       doepint.d32 =
55279 +                           dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
55280 +                       /* Moved this interrupt upper due to core deffect of asserting
55281 +                        * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */
55282 +                       if (doepint.b.stsphsercvd) {
55283 +                               deptsiz0_data_t deptsiz;
55284 +                               CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
55285 +                               deptsiz.d32 =
55286 +                                   DWC_READ_REG32(&core_if->dev_if->
55287 +                                                  out_ep_regs[0]->doeptsiz);
55288 +                               if (core_if->snpsid >= OTG_CORE_REV_3_00a
55289 +                                   && core_if->dma_enable
55290 +                                   && core_if->dma_desc_enable == 0
55291 +                                   && doepint.b.xfercompl
55292 +                                   && deptsiz.b.xfersize == 24) {
55293 +                                       CLEAR_OUT_EP_INTR(core_if, epnum,
55294 +                                                         xfercompl);
55295 +                                       doepint.b.xfercompl = 0;
55296 +                                       ep0_out_start(core_if, pcd);
55297 +                               }
55298 +                               if ((core_if->dma_desc_enable) ||
55299 +                                   (core_if->dma_enable
55300 +                                    && core_if->snpsid >=
55301 +                                    OTG_CORE_REV_3_00a)) {
55302 +                                       do_setup_in_status_phase(pcd);
55303 +                               }
55304 +                       }
55305 +                       /* Transfer complete */
55306 +                       if (doepint.b.xfercompl) {
55307 +
55308 +                               if (epnum == 0) {
55309 +                                       /* Clear the bit in DOEPINTn for this interrupt */
55310 +                                       CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
55311 +                                       if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
55312 +                                               DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
55313 +                                                       DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint),
55314 +                                                       doepint.d32);
55315 +                                               DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n",
55316 +                                                       DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl));
55317 +
55318 +                                               if (core_if->snpsid >= OTG_CORE_REV_3_00a
55319 +                                                       && core_if->dma_enable == 0) {
55320 +                                                       doepint_data_t doepint;
55321 +                                                       doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55322 +                                                                                                               out_ep_regs[0]->doepint);
55323 +                                                       if (pcd->ep0state == EP0_IDLE && doepint.b.sr) {
55324 +                                                               CLEAR_OUT_EP_INTR(core_if, epnum, sr);
55325 +                                                               goto exit_xfercompl;
55326 +                                                       }
55327 +                                               }
55328 +                                               /* In case of DDMA  look at SR bit to go to the Data Stage */
55329 +                                               if (core_if->dma_desc_enable) {
55330 +                                                       dev_dma_desc_sts_t status = {.d32 = 0};
55331 +                                                       if (pcd->ep0state == EP0_IDLE) {
55332 +                                                               status.d32 = core_if->dev_if->setup_desc_addr[core_if->
55333 +                                                                                       dev_if->setup_desc_index]->status.d32;
55334 +                                                               if(pcd->data_terminated) {
55335 +                                                                        pcd->data_terminated = 0;
55336 +                                                                        status.d32 = core_if->dev_if->out_desc_addr->status.d32;
55337 +                                                                        dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8);
55338 +                                                               }
55339 +                                                               if (status.b.sr) {
55340 +                                                                       if (doepint.b.setup) {
55341 +                                                                               DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n");
55342 +                                                                               /* Already started data stage, clear setup */
55343 +                                                                               CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55344 +                                                                               doepint.b.setup = 0;
55345 +                                                                               handle_ep0(pcd);
55346 +                                                                               /* Prepare for more setup packets */
55347 +                                                                               if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
55348 +                                                                                       pcd->ep0state == EP0_IN_DATA_PHASE) {
55349 +                                                                                       ep0_out_start(core_if, pcd);
55350 +                                                                               }
55351 +
55352 +                                                                               goto exit_xfercompl;
55353 +                                                                       } else {
55354 +                                                                               /* Prepare for more setup packets */
55355 +                                                                               DWC_DEBUGPL(DBG_PCDV,
55356 +                                                                                       "EP0_IDLE SR=1 setup=0 new setup comes\n");
55357 +                                                                               ep0_out_start(core_if, pcd);
55358 +                                                                       }
55359 +                                                               }
55360 +                                                       } else {
55361 +                                                               dwc_otg_pcd_request_t *req;
55362 +                                                               dev_dma_desc_sts_t status = {.d32 = 0};
55363 +                                                               diepint_data_t diepint0;
55364 +                                                               diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
55365 +                                                                                                                       in_ep_regs[0]->diepint);
55366 +
55367 +                                                               if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) {
55368 +                                                                       DWC_ERROR("EP0 is stalled/disconnected\n");
55369 +                                                               }
55370 +
55371 +                                                               /* Clear IN xfercompl if set */
55372 +                                                               if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE
55373 +                                                                       || pcd->ep0state == EP0_IN_DATA_PHASE)) {
55374 +                                                                       DWC_WRITE_REG32(&core_if->dev_if->
55375 +                                                                               in_ep_regs[0]->diepint, diepint0.d32);
55376 +                                                               }
55377 +
55378 +                                                               status.d32 = core_if->dev_if->setup_desc_addr[core_if->
55379 +                                                                       dev_if->setup_desc_index]->status.d32;
55380 +
55381 +                                                               if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len
55382 +                                                                       && (pcd->ep0state == EP0_OUT_DATA_PHASE))
55383 +                                                                       status.d32 = core_if->dev_if->out_desc_addr->status.d32;
55384 +                                                               if (pcd->ep0state == EP0_OUT_STATUS_PHASE)
55385 +                                                                       status.d32 = core_if->dev_if->
55386 +                                                                       out_desc_addr->status.d32;
55387 +
55388 +                                                               if (status.b.sr) {
55389 +                                                                       if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
55390 +                                                                               DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
55391 +                                                                       } else {
55392 +                                                                               DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
55393 +                                                                               req = DWC_CIRCLEQ_FIRST(&ep->queue);
55394 +                                                                               if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
55395 +                                                                                       pcd->ep0state == EP0_OUT_DATA_PHASE) {
55396 +                                                                                               /* Read arrived setup packet from req->buf */
55397 +                                                                                               dwc_memcpy(&pcd->setup_pkt->req,
55398 +                                                                                                       req->buf + ep->dwc_ep.xfer_count, 8);
55399 +                                                                               }
55400 +                                                                               req->actual = ep->dwc_ep.xfer_count;
55401 +                                                                               dwc_otg_request_done(ep, req, -ECONNRESET);
55402 +                                                                               ep->dwc_ep.start_xfer_buff = 0;
55403 +                                                                               ep->dwc_ep.xfer_buff = 0;
55404 +                                                                               ep->dwc_ep.xfer_len = 0;
55405 +                                                                       }
55406 +                                                                       pcd->ep0state = EP0_IDLE;
55407 +                                                                       if (doepint.b.setup) {
55408 +                                                                               DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
55409 +                                                                               /* Data stage started, clear setup */
55410 +                                                                               CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55411 +                                                                               doepint.b.setup = 0;
55412 +                                                                               handle_ep0(pcd);
55413 +                                                                               /* Prepare for setup packets if ep0in was enabled*/
55414 +                                                                               if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
55415 +                                                                                       ep0_out_start(core_if, pcd);
55416 +                                                                               }
55417 +
55418 +                                                                               goto exit_xfercompl;
55419 +                                                                       } else {
55420 +                                                                               /* Prepare for more setup packets */
55421 +                                                                               DWC_DEBUGPL(DBG_PCDV,
55422 +                                                                                       "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
55423 +                                                                               ep0_out_start(core_if, pcd);
55424 +                                                                       }
55425 +                                                               }
55426 +                                                       }
55427 +                                               }
55428 +                                               if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable
55429 +                                                       && core_if->dma_desc_enable == 0) {
55430 +                                                       doepint_data_t doepint_temp = {.d32 = 0};
55431 +                                                       deptsiz0_data_t doeptsize0 = {.d32 = 0 };
55432 +                                                       doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
55433 +                                                                                                                       out_ep_regs[ep->dwc_ep.num]->doepint);
55434 +                                                       doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if->
55435 +                                                                                                                       out_ep_regs[ep->dwc_ep.num]->doeptsiz);
55436 +                                                       if (pcd->ep0state == EP0_IDLE) {
55437 +                                                               if (doepint_temp.b.sr) {
55438 +                                                                       CLEAR_OUT_EP_INTR(core_if, epnum, sr);
55439 +                                                               }
55440 +                                                                       doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55441 +                                                                                                                                       out_ep_regs[0]->doepint);
55442 +                                                                       if (doeptsize0.b.supcnt == 3) {
55443 +                                                                               DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n");
55444 +                                                                               ep->dwc_ep.stp_rollover = 1;
55445 +                                                                       }
55446 +                                                                       if (doepint.b.setup) {
55447 +retry:
55448 +                                                                               /* Already started data stage, clear setup */
55449 +                                                                               CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55450 +                                                                               doepint.b.setup = 0;
55451 +                                                                               handle_ep0(pcd);
55452 +                                                                               ep->dwc_ep.stp_rollover = 0;
55453 +                                                                               /* Prepare for more setup packets */
55454 +                                                                               if (pcd->ep0state == EP0_IN_STATUS_PHASE ||
55455 +                                                                                       pcd->ep0state == EP0_IN_DATA_PHASE) {
55456 +                                                                                       ep0_out_start(core_if, pcd);
55457 +                                                                               }
55458 +                                                                               goto exit_xfercompl;
55459 +                                                                       } else {
55460 +                                                                               /* Prepare for more setup packets */
55461 +                                                                               DWC_DEBUGPL(DBG_ANY,
55462 +                                                                                       "EP0_IDLE SR=1 setup=0 new setup comes\n");
55463 +                                                                               doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55464 +                                                                                                                                       out_ep_regs[0]->doepint);
55465 +                                                                               if(doepint.b.setup)
55466 +                                                                                       goto retry;
55467 +                                                                               ep0_out_start(core_if, pcd);
55468 +                                                                       }
55469 +                                                       } else {
55470 +                                                               dwc_otg_pcd_request_t *req;
55471 +                                                               diepint_data_t diepint0 = {.d32 = 0};
55472 +                                                               doepint_data_t doepint_temp = {.d32 = 0};
55473 +                                                               depctl_data_t diepctl0;
55474 +                                                               diepint0.d32 = DWC_READ_REG32(&core_if->dev_if->
55475 +                                                                                                                               in_ep_regs[0]->diepint);
55476 +                                                               diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if->
55477 +                                                                                                                               in_ep_regs[0]->diepctl);
55478 +
55479 +                                                               if (pcd->ep0state == EP0_IN_DATA_PHASE
55480 +                                                                       || pcd->ep0state == EP0_IN_STATUS_PHASE) {
55481 +                                                                       if (diepint0.b.xfercompl) {
55482 +                                                                               DWC_WRITE_REG32(&core_if->dev_if->
55483 +                                                                                       in_ep_regs[0]->diepint, diepint0.d32);
55484 +                                                                       }
55485 +                                                                       if (diepctl0.b.epena) {
55486 +                                                                               diepint_data_t diepint = {.d32 = 0};
55487 +                                                                               diepctl0.b.snak = 1;
55488 +                                                                               DWC_WRITE_REG32(&core_if->dev_if->
55489 +                                                                                                               in_ep_regs[0]->diepctl, diepctl0.d32);
55490 +                                                                               do {
55491 +                                                                                       dwc_udelay(10);
55492 +                                                                                       diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55493 +                                                                                               in_ep_regs[0]->diepint);
55494 +                                                                               } while (!diepint.b.inepnakeff);
55495 +                                                                               diepint.b.inepnakeff = 1;
55496 +                                                                               DWC_WRITE_REG32(&core_if->dev_if->
55497 +                                                                                       in_ep_regs[0]->diepint, diepint.d32);
55498 +                                                                               diepctl0.d32 = 0;
55499 +                                                                               diepctl0.b.epdis = 1;
55500 +                                                                               DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl,
55501 +                                                                                                               diepctl0.d32);
55502 +                                                                               do {
55503 +                                                                                       dwc_udelay(10);
55504 +                                                                                       diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
55505 +                                                                                               in_ep_regs[0]->diepint);
55506 +                                                                               } while (!diepint.b.epdisabled);
55507 +                                                                               diepint.b.epdisabled = 1;
55508 +                                                                               DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint,
55509 +                                                                                                                       diepint.d32);
55510 +                                                                       }
55511 +                                                               }
55512 +                                                               doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if->
55513 +                                                                                                                               out_ep_regs[ep->dwc_ep.num]->doepint);
55514 +                                                               if (doepint_temp.b.sr) {
55515 +                                                                       CLEAR_OUT_EP_INTR(core_if, epnum, sr);
55516 +                                                                       if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
55517 +                                                                               DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n");
55518 +                                                                       } else {
55519 +                                                                               DWC_DEBUGPL(DBG_PCDV, "complete req!!\n");
55520 +                                                                               req = DWC_CIRCLEQ_FIRST(&ep->queue);
55521 +                                                                               if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len &&
55522 +                                                                                       pcd->ep0state == EP0_OUT_DATA_PHASE) {
55523 +                                                                                               /* Read arrived setup packet from req->buf */
55524 +                                                                                               dwc_memcpy(&pcd->setup_pkt->req,
55525 +                                                                                                       req->buf + ep->dwc_ep.xfer_count, 8);
55526 +                                                                               }
55527 +                                                                               req->actual = ep->dwc_ep.xfer_count;
55528 +                                                                               dwc_otg_request_done(ep, req, -ECONNRESET);
55529 +                                                                               ep->dwc_ep.start_xfer_buff = 0;
55530 +                                                                               ep->dwc_ep.xfer_buff = 0;
55531 +                                                                               ep->dwc_ep.xfer_len = 0;
55532 +                                                                       }
55533 +                                                                       pcd->ep0state = EP0_IDLE;
55534 +                                                                       if (doepint.b.setup) {
55535 +                                                                               DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n");
55536 +                                                                               /* Data stage started, clear setup */
55537 +                                                                               CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55538 +                                                                               doepint.b.setup = 0;
55539 +                                                                               handle_ep0(pcd);
55540 +                                                                               /* Prepare for setup packets if ep0in was enabled*/
55541 +                                                                               if (pcd->ep0state == EP0_IN_STATUS_PHASE) {
55542 +                                                                                       ep0_out_start(core_if, pcd);
55543 +                                                                               }
55544 +                                                                               goto exit_xfercompl;
55545 +                                                                       } else {
55546 +                                                                               /* Prepare for more setup packets */
55547 +                                                                               DWC_DEBUGPL(DBG_PCDV,
55548 +                                                                                       "EP0_IDLE SR=1 setup=0 new setup comes 2\n");
55549 +                                                                               ep0_out_start(core_if, pcd);
55550 +                                                                       }
55551 +                                                               }
55552 +                                                       }
55553 +                                               }
55554 +                                               if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE)
55555 +                                                       handle_ep0(pcd);
55556 +exit_xfercompl:
55557 +                                               DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n",
55558 +                                                       dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32);
55559 +                                       } else {
55560 +                                       if (core_if->dma_desc_enable == 0
55561 +                                           || pcd->ep0state != EP0_IDLE)
55562 +                                               handle_ep0(pcd);
55563 +                                       }
55564 +#ifdef DWC_EN_ISOC
55565 +                               } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55566 +                                       if (doepint.b.pktdrpsts == 0) {
55567 +                                               /* Clear the bit in DOEPINTn for this interrupt */
55568 +                                               CLEAR_OUT_EP_INTR(core_if,
55569 +                                                                 epnum,
55570 +                                                                 xfercompl);
55571 +                                               complete_iso_ep(pcd, ep);
55572 +                                       } else {
55573 +
55574 +                                               doepint_data_t doepint = {.d32 = 0 };
55575 +                                               doepint.b.xfercompl = 1;
55576 +                                               doepint.b.pktdrpsts = 1;
55577 +                                               DWC_WRITE_REG32
55578 +                                                   (&core_if->dev_if->out_ep_regs
55579 +                                                    [epnum]->doepint,
55580 +                                                    doepint.d32);
55581 +                                               if (handle_iso_out_pkt_dropped
55582 +                                                   (core_if, dwc_ep)) {
55583 +                                                       complete_iso_ep(pcd,
55584 +                                                                       ep);
55585 +                                               }
55586 +                                       }
55587 +#endif /* DWC_EN_ISOC */
55588 +#ifdef DWC_UTE_PER_IO
55589 +                               } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55590 +                                       CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
55591 +                                       if (!ep->stopped)
55592 +                                               complete_xiso_ep(ep);
55593 +#endif /* DWC_UTE_PER_IO */
55594 +                               } else {
55595 +                                       /* Clear the bit in DOEPINTn for this interrupt */
55596 +                                       CLEAR_OUT_EP_INTR(core_if, epnum,
55597 +                                                         xfercompl);
55598 +
55599 +                                       if (core_if->core_params->dev_out_nak) {
55600 +                                               DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
55601 +                                               pcd->core_if->ep_xfer_info[epnum].state = 0;
55602 +#ifdef DEBUG
55603 +                                               print_memory_payload(pcd, dwc_ep);
55604 +#endif
55605 +                                       }
55606 +                                       complete_ep(ep);
55607 +                               }
55608 +
55609 +                       }
55610 +
55611 +                       /* Endpoint disable      */
55612 +                       if (doepint.b.epdisabled) {
55613 +
55614 +                               /* Clear the bit in DOEPINTn for this interrupt */
55615 +                               CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
55616 +                               if (core_if->core_params->dev_out_nak) {
55617 +#ifdef DEBUG
55618 +                                       print_memory_payload(pcd, dwc_ep);
55619 +#endif
55620 +                                       /* In case of timeout condition */
55621 +                                       if (core_if->ep_xfer_info[epnum].state == 2) {
55622 +                                               dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
55623 +                                                                               dev_global_regs->dctl);
55624 +                                               dctl.b.cgoutnak = 1;
55625 +                                               DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
55626 +                                                                                                                               dctl.d32);
55627 +                                               /* Unmask goutnakeff interrupt which was masked
55628 +                                                * during handle nak out interrupt */
55629 +                                               gintmsk.b.goutnakeff = 1;
55630 +                                               DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
55631 +                                                                                                                               0, gintmsk.d32);
55632 +
55633 +                                               complete_ep(ep);
55634 +                                       }
55635 +                               }
55636 +                               if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
55637 +                               {
55638 +                                       dctl_data_t dctl;
55639 +                                       gintmsk_data_t intr_mask = {.d32 = 0};
55640 +                                       dwc_otg_pcd_request_t *req = 0;
55641 +
55642 +                                       dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
55643 +                                               dev_global_regs->dctl);
55644 +                                       dctl.b.cgoutnak = 1;
55645 +                                       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
55646 +                                               dctl.d32);
55647 +
55648 +                                       intr_mask.d32 = 0;
55649 +                                       intr_mask.b.incomplisoout = 1;
55650 +
55651 +                                       /* Get any pending requests */
55652 +                                       if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
55653 +                                               req = DWC_CIRCLEQ_FIRST(&ep->queue);
55654 +                                               if (!req) {
55655 +                                                       DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
55656 +                                               } else {
55657 +                                                       dwc_otg_request_done(ep, req, 0);
55658 +                                                       start_next_request(ep);
55659 +                                               }
55660 +                                       } else {
55661 +                                               DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
55662 +                                       }
55663 +                               }
55664 +                       }
55665 +                       /* AHB Error */
55666 +                       if (doepint.b.ahberr) {
55667 +                               DWC_ERROR("EP%d OUT AHB Error\n", epnum);
55668 +                               DWC_ERROR("EP%d DEPDMA=0x%08x \n",
55669 +                                         epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
55670 +                               CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
55671 +                       }
55672 +                       /* Setup Phase Done (contorl EPs) */
55673 +                       if (doepint.b.setup) {
55674 +#ifdef DEBUG_EP0
55675 +                               DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum);
55676 +#endif
55677 +                               CLEAR_OUT_EP_INTR(core_if, epnum, setup);
55678 +
55679 +                               handle_ep0(pcd);
55680 +                       }
55681 +
55682 +                       /** OUT EP BNA Intr */
55683 +                       if (doepint.b.bna) {
55684 +                               CLEAR_OUT_EP_INTR(core_if, epnum, bna);
55685 +                               if (core_if->dma_desc_enable) {
55686 +#ifdef DWC_EN_ISOC
55687 +                                       if (dwc_ep->type ==
55688 +                                           DWC_OTG_EP_TYPE_ISOC) {
55689 +                                               /*
55690 +                                                * This checking is performed to prevent first "false" BNA
55691 +                                                * handling occuring right after reconnect
55692 +                                                */
55693 +                                               if (dwc_ep->next_frame !=
55694 +                                                   0xffffffff)
55695 +                                                       dwc_otg_pcd_handle_iso_bna(ep);
55696 +                                       } else
55697 +#endif                         /* DWC_EN_ISOC */
55698 +                                       {
55699 +                                               dwc_otg_pcd_handle_noniso_bna(ep);
55700 +                                       }
55701 +                               }
55702 +                       }
55703 +                       /* Babble Interrupt */
55704 +                       if (doepint.b.babble) {
55705 +                               DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
55706 +                                           epnum);
55707 +                               handle_out_ep_babble_intr(pcd, epnum);
55708 +
55709 +                               CLEAR_OUT_EP_INTR(core_if, epnum, babble);
55710 +                       }
55711 +                       if (doepint.b.outtknepdis) {
55712 +                               DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
55713 +                                       disabled\n",epnum);
55714 +                               if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
55715 +                                       doepmsk_data_t doepmsk = {.d32 = 0};
55716 +                                       ep->dwc_ep.frame_num = core_if->frame_num;
55717 +                                       if (ep->dwc_ep.bInterval > 1) {
55718 +                                               depctl_data_t depctl;
55719 +                                               depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
55720 +                                                                                                       out_ep_regs[epnum]->doepctl);
55721 +                                               if (ep->dwc_ep.frame_num & 0x1) {
55722 +                                                       depctl.b.setd1pid = 1;
55723 +                                                       depctl.b.setd0pid = 0;
55724 +                                               } else {
55725 +                                                       depctl.b.setd0pid = 1;
55726 +                                                       depctl.b.setd1pid = 0;
55727 +                                               }
55728 +                                               DWC_WRITE_REG32(&core_if->dev_if->
55729 +                                                                               out_ep_regs[epnum]->doepctl, depctl.d32);
55730 +                                       }
55731 +                                       start_next_request(ep);
55732 +                                       doepmsk.b.outtknepdis = 1;
55733 +                                       DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
55734 +                                                                doepmsk.d32, 0);
55735 +                               }
55736 +                               CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
55737 +                       }
55738 +
55739 +                       /* NAK Interrutp */
55740 +                       if (doepint.b.nak) {
55741 +                               DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
55742 +                               handle_out_ep_nak_intr(pcd, epnum);
55743 +
55744 +                               CLEAR_OUT_EP_INTR(core_if, epnum, nak);
55745 +                       }
55746 +                       /* NYET Interrutp */
55747 +                       if (doepint.b.nyet) {
55748 +                               DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
55749 +                               handle_out_ep_nyet_intr(pcd, epnum);
55750 +
55751 +                               CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
55752 +                       }
55753 +               }
55754 +
55755 +               epnum++;
55756 +               ep_intr >>= 1;
55757 +       }
55758 +
55759 +       return 1;
55760 +
55761 +#undef CLEAR_OUT_EP_INTR
55762 +}
55763 +static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
55764 +{
55765 +       int retval = 0;
55766 +       if(!frm_overrun && curr_fr >= trgt_fr)
55767 +               retval = 1;
55768 +       else if (frm_overrun
55769 +                && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2)))
55770 +               retval = 1;
55771 +       return retval;
55772 +}
55773 +/**
55774 + * Incomplete ISO IN Transfer Interrupt.
55775 + * This interrupt indicates one of the following conditions occurred
55776 + * while transmitting an ISOC transaction.
55777 + * - Corrupted IN Token for ISOC EP.
55778 + * - Packet not complete in FIFO.
55779 + * The follow actions will be taken:
55780 + *     -#      Determine the EP
55781 + *     -#      Set incomplete flag in dwc_ep structure
55782 + *     -#      Disable EP; when "Endpoint Disabled" interrupt is received
55783 + *             Flush FIFO
55784 + */
55785 +int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
55786 +{
55787 +       gintsts_data_t gintsts;
55788 +
55789 +#ifdef DWC_EN_ISOC
55790 +       dwc_otg_dev_if_t *dev_if;
55791 +       deptsiz_data_t deptsiz = {.d32 = 0 };
55792 +       depctl_data_t depctl = {.d32 = 0 };
55793 +       dsts_data_t dsts = {.d32 = 0 };
55794 +       dwc_ep_t *dwc_ep;
55795 +       int i;
55796 +
55797 +       dev_if = GET_CORE_IF(pcd)->dev_if;
55798 +
55799 +       for (i = 1; i <= dev_if->num_in_eps; ++i) {
55800 +               dwc_ep = &pcd->in_ep[i].dwc_ep;
55801 +               if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55802 +                       deptsiz.d32 =
55803 +                           DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
55804 +                       depctl.d32 =
55805 +                           DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
55806 +
55807 +                       if (depctl.b.epdis && deptsiz.d32) {
55808 +                               set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
55809 +                               if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
55810 +                                       dwc_ep->cur_pkt = 0;
55811 +                                       dwc_ep->proc_buf_num =
55812 +                                           (dwc_ep->proc_buf_num ^ 1) & 0x1;
55813 +
55814 +                                       if (dwc_ep->proc_buf_num) {
55815 +                                               dwc_ep->cur_pkt_addr =
55816 +                                                   dwc_ep->xfer_buff1;
55817 +                                               dwc_ep->cur_pkt_dma_addr =
55818 +                                                   dwc_ep->dma_addr1;
55819 +                                       } else {
55820 +                                               dwc_ep->cur_pkt_addr =
55821 +                                                   dwc_ep->xfer_buff0;
55822 +                                               dwc_ep->cur_pkt_dma_addr =
55823 +                                                   dwc_ep->dma_addr0;
55824 +                                       }
55825 +
55826 +                               }
55827 +
55828 +                               dsts.d32 =
55829 +                                   DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
55830 +                                                  dev_global_regs->dsts);
55831 +                               dwc_ep->next_frame = dsts.b.soffn;
55832 +
55833 +                               dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
55834 +                                                                 (pcd),
55835 +                                                                 dwc_ep);
55836 +                       }
55837 +               }
55838 +       }
55839 +
55840 +#else
55841 +       depctl_data_t depctl = {.d32 = 0 };
55842 +       dwc_ep_t *dwc_ep;
55843 +       dwc_otg_dev_if_t *dev_if;
55844 +       int i;
55845 +       dev_if = GET_CORE_IF(pcd)->dev_if;
55846 +
55847 +       DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
55848 +
55849 +       for (i = 1; i <= dev_if->num_in_eps; ++i) {
55850 +               dwc_ep = &pcd->in_ep[i-1].dwc_ep;
55851 +               depctl.d32 =
55852 +                       DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
55853 +               if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
55854 +                       if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num,
55855 +                                                       dwc_ep->frm_overrun))
55856 +                       {
55857 +                               depctl.d32 =
55858 +                                       DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
55859 +                               depctl.b.snak = 1;
55860 +                               depctl.b.epdis = 1;
55861 +                               DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
55862 +                       }
55863 +               }
55864 +       }
55865 +
55866 +       /*intr_mask.b.incomplisoin = 1;
55867 +       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
55868 +                        intr_mask.d32, 0);      */
55869 +#endif                         //DWC_EN_ISOC
55870 +
55871 +       /* Clear interrupt */
55872 +       gintsts.d32 = 0;
55873 +       gintsts.b.incomplisoin = 1;
55874 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
55875 +                       gintsts.d32);
55876 +
55877 +       return 1;
55878 +}
55879 +
55880 +/**
55881 + * Incomplete ISO OUT Transfer Interrupt.
55882 + *
55883 + * This interrupt indicates that the core has dropped an ISO OUT
55884 + * packet. The following conditions can be the cause:
55885 + * - FIFO Full, the entire packet would not fit in the FIFO.
55886 + * - CRC Error
55887 + * - Corrupted Token
55888 + * The follow actions will be taken:
55889 + *     -#      Determine the EP
55890 + *     -#      Set incomplete flag in dwc_ep structure
55891 + *     -#      Read any data from the FIFO
55892 + *     -#      Disable EP. When "Endpoint Disabled" interrupt is received
55893 + *             re-enable EP.
55894 + */
55895 +int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
55896 +{
55897 +
55898 +       gintsts_data_t gintsts;
55899 +
55900 +#ifdef DWC_EN_ISOC
55901 +       dwc_otg_dev_if_t *dev_if;
55902 +       deptsiz_data_t deptsiz = {.d32 = 0 };
55903 +       depctl_data_t depctl = {.d32 = 0 };
55904 +       dsts_data_t dsts = {.d32 = 0 };
55905 +       dwc_ep_t *dwc_ep;
55906 +       int i;
55907 +
55908 +       dev_if = GET_CORE_IF(pcd)->dev_if;
55909 +
55910 +       for (i = 1; i <= dev_if->num_out_eps; ++i) {
55911 +               dwc_ep = &pcd->in_ep[i].dwc_ep;
55912 +               if (pcd->out_ep[i].dwc_ep.active &&
55913 +                   pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
55914 +                       deptsiz.d32 =
55915 +                           DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
55916 +                       depctl.d32 =
55917 +                           DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
55918 +
55919 +                       if (depctl.b.epdis && deptsiz.d32) {
55920 +                               set_current_pkt_info(GET_CORE_IF(pcd),
55921 +                                                    &pcd->out_ep[i].dwc_ep);
55922 +                               if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
55923 +                                       dwc_ep->cur_pkt = 0;
55924 +                                       dwc_ep->proc_buf_num =
55925 +                                           (dwc_ep->proc_buf_num ^ 1) & 0x1;
55926 +
55927 +                                       if (dwc_ep->proc_buf_num) {
55928 +                                               dwc_ep->cur_pkt_addr =
55929 +                                                   dwc_ep->xfer_buff1;
55930 +                                               dwc_ep->cur_pkt_dma_addr =
55931 +                                                   dwc_ep->dma_addr1;
55932 +                                       } else {
55933 +                                               dwc_ep->cur_pkt_addr =
55934 +                                                   dwc_ep->xfer_buff0;
55935 +                                               dwc_ep->cur_pkt_dma_addr =
55936 +                                                   dwc_ep->dma_addr0;
55937 +                                       }
55938 +
55939 +                               }
55940 +
55941 +                               dsts.d32 =
55942 +                                   DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
55943 +                                                  dev_global_regs->dsts);
55944 +                               dwc_ep->next_frame = dsts.b.soffn;
55945 +
55946 +                               dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
55947 +                                                                 (pcd),
55948 +                                                                 dwc_ep);
55949 +                       }
55950 +               }
55951 +       }
55952 +#else
55953 +       /** @todo implement ISR */
55954 +       gintmsk_data_t intr_mask = {.d32 = 0 };
55955 +       dwc_otg_core_if_t *core_if;
55956 +       deptsiz_data_t deptsiz = {.d32 = 0 };
55957 +       depctl_data_t depctl = {.d32 = 0 };
55958 +       dctl_data_t dctl = {.d32 = 0 };
55959 +       dwc_ep_t *dwc_ep = NULL;
55960 +       int i;
55961 +       core_if = GET_CORE_IF(pcd);
55962 +
55963 +       for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
55964 +               dwc_ep = &pcd->out_ep[i].dwc_ep;
55965 +               depctl.d32 =
55966 +                       DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
55967 +               if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
55968 +                       core_if->dev_if->isoc_ep = dwc_ep;
55969 +                       deptsiz.d32 =
55970 +                                       DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
55971 +                               break;
55972 +               }
55973 +       }
55974 +       dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
55975 +       gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
55976 +       intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
55977 +
55978 +       if (!intr_mask.b.goutnakeff) {
55979 +               /* Unmask it */
55980 +               intr_mask.b.goutnakeff = 1;
55981 +               DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
55982 +       }
55983 +       if (!gintsts.b.goutnakeff) {
55984 +               dctl.b.sgoutnak = 1;
55985 +       }
55986 +       DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
55987 +
55988 +       depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
55989 +       if (depctl.b.epena) {
55990 +               depctl.b.epdis = 1;
55991 +               depctl.b.snak = 1;
55992 +       }
55993 +       DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
55994 +
55995 +       intr_mask.d32 = 0;
55996 +       intr_mask.b.incomplisoout = 1;
55997 +
55998 +#endif /* DWC_EN_ISOC */
55999 +
56000 +       /* Clear interrupt */
56001 +       gintsts.d32 = 0;
56002 +       gintsts.b.incomplisoout = 1;
56003 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56004 +                       gintsts.d32);
56005 +
56006 +       return 1;
56007 +}
56008 +
56009 +/**
56010 + * This function handles the Global IN NAK Effective interrupt.
56011 + *
56012 + */
56013 +int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
56014 +{
56015 +       dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
56016 +       depctl_data_t diepctl = {.d32 = 0 };
56017 +       gintmsk_data_t intr_mask = {.d32 = 0 };
56018 +       gintsts_data_t gintsts;
56019 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
56020 +       int i;
56021 +
56022 +       DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
56023 +
56024 +       /* Disable all active IN EPs */
56025 +       for (i = 0; i <= dev_if->num_in_eps; i++) {
56026 +               diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
56027 +               if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
56028 +                       if (core_if->start_predict > 0)
56029 +                               core_if->start_predict++;
56030 +                       diepctl.b.epdis = 1;
56031 +                       diepctl.b.snak = 1;
56032 +                       DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
56033 +               }
56034 +       }
56035 +
56036 +
56037 +       /* Disable the Global IN NAK Effective Interrupt */
56038 +       intr_mask.b.ginnakeff = 1;
56039 +       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
56040 +                        intr_mask.d32, 0);
56041 +
56042 +       /* Clear interrupt */
56043 +       gintsts.d32 = 0;
56044 +       gintsts.b.ginnakeff = 1;
56045 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56046 +                       gintsts.d32);
56047 +
56048 +       return 1;
56049 +}
56050 +
56051 +/**
56052 + * OUT NAK Effective.
56053 + *
56054 + */
56055 +int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
56056 +{
56057 +       dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
56058 +       gintmsk_data_t intr_mask = {.d32 = 0 };
56059 +       gintsts_data_t gintsts;
56060 +       depctl_data_t doepctl;
56061 +       int i;
56062 +
56063 +       /* Disable the Global OUT NAK Effective Interrupt */
56064 +       intr_mask.b.goutnakeff = 1;
56065 +       DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
56066 +               intr_mask.d32, 0);
56067 +
56068 +       /* If DEV OUT NAK enabled*/
56069 +       if (pcd->core_if->core_params->dev_out_nak) {
56070 +               /* Run over all out endpoints to determine the ep number on
56071 +                * which the timeout has happened
56072 +                */
56073 +               for (i = 0; i <= dev_if->num_out_eps; i++) {
56074 +                       if ( pcd->core_if->ep_xfer_info[i].state == 2 )
56075 +                               break;
56076 +               }
56077 +               if (i > dev_if->num_out_eps) {
56078 +                       dctl_data_t dctl;
56079 +                       dctl.d32 =
56080 +                           DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
56081 +                       dctl.b.cgoutnak = 1;
56082 +                       DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
56083 +                               dctl.d32);
56084 +                       goto out;
56085 +               }
56086 +
56087 +               /* Disable the endpoint */
56088 +               doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
56089 +               if (doepctl.b.epena) {
56090 +                       doepctl.b.epdis = 1;
56091 +                       doepctl.b.snak = 1;
56092 +               }
56093 +               DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
56094 +               return 1;
56095 +       }
56096 +       /* We come here from Incomplete ISO OUT handler */
56097 +       if (dev_if->isoc_ep) {
56098 +               dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
56099 +               uint32_t epnum = dwc_ep->num;
56100 +               doepint_data_t doepint;
56101 +               doepint.d32 =
56102 +                   DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
56103 +               dev_if->isoc_ep = NULL;
56104 +               doepctl.d32 =
56105 +                   DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
56106 +               DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
56107 +               if (doepctl.b.epena) {
56108 +                       doepctl.b.epdis = 1;
56109 +                       doepctl.b.snak = 1;
56110 +               }
56111 +               DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl,
56112 +                               doepctl.d32);
56113 +               return 1;
56114 +       } else
56115 +               DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
56116 +                          "Global OUT NAK Effective\n");
56117 +
56118 +out:
56119 +       /* Clear interrupt */
56120 +       gintsts.d32 = 0;
56121 +       gintsts.b.goutnakeff = 1;
56122 +       DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
56123 +                       gintsts.d32);
56124 +
56125 +       return 1;
56126 +}
56127 +
56128 +/**
56129 + * PCD interrupt handler.
56130 + *
56131 + * The PCD handles the device interrupts.  Many conditions can cause a
56132 + * device interrupt. When an interrupt occurs, the device interrupt
56133 + * service routine determines the cause of the interrupt and
56134 + * dispatches handling to the appropriate function. These interrupt
56135 + * handling functions are described below.
56136 + *
56137 + * All interrupt registers are processed from LSB to MSB.
56138 + *
56139 + */
56140 +int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
56141 +{
56142 +       dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
56143 +#ifdef VERBOSE
56144 +       dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
56145 +#endif
56146 +       gintsts_data_t gintr_status;
56147 +       int32_t retval = 0;
56148 +
56149 +       /* Exit from ISR if core is hibernated */
56150 +       if (core_if->hibernation_suspend == 1) {
56151 +               return retval;
56152 +       }
56153 +#ifdef VERBOSE
56154 +       DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x  gintmsk=%08x\n",
56155 +                   __func__,
56156 +                   DWC_READ_REG32(&global_regs->gintsts),
56157 +                   DWC_READ_REG32(&global_regs->gintmsk));
56158 +#endif
56159 +
56160 +       if (dwc_otg_is_device_mode(core_if)) {
56161 +               DWC_SPINLOCK(pcd->lock);
56162 +#ifdef VERBOSE
56163 +               DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
56164 +                           __func__,
56165 +                           DWC_READ_REG32(&global_regs->gintsts),
56166 +                           DWC_READ_REG32(&global_regs->gintmsk));
56167 +#endif
56168 +
56169 +               gintr_status.d32 = dwc_otg_read_core_intr(core_if);
56170 +
56171 +               DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
56172 +                           __func__, gintr_status.d32);
56173 +
56174 +               if (gintr_status.b.sofintr) {
56175 +                       retval |= dwc_otg_pcd_handle_sof_intr(pcd);
56176 +               }
56177 +               if (gintr_status.b.rxstsqlvl) {
56178 +                       retval |=
56179 +                           dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
56180 +               }
56181 +               if (gintr_status.b.nptxfempty) {
56182 +                       retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
56183 +               }
56184 +               if (gintr_status.b.goutnakeff) {
56185 +                       retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
56186 +               }
56187 +               if (gintr_status.b.i2cintr) {
56188 +                       retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
56189 +               }
56190 +               if (gintr_status.b.erlysuspend) {
56191 +                       retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
56192 +               }
56193 +               if (gintr_status.b.usbreset) {
56194 +                       retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
56195 +               }
56196 +               if (gintr_status.b.enumdone) {
56197 +                       retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
56198 +               }
56199 +               if (gintr_status.b.isooutdrop) {
56200 +                       retval |=
56201 +                           dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
56202 +                           (pcd);
56203 +               }
56204 +               if (gintr_status.b.eopframe) {
56205 +                       retval |=
56206 +                           dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
56207 +               }
56208 +               if (gintr_status.b.inepint) {
56209 +                       if (!core_if->multiproc_int_enable) {
56210 +                               retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
56211 +                       }
56212 +               }
56213 +               if (gintr_status.b.outepintr) {
56214 +                       if (!core_if->multiproc_int_enable) {
56215 +                               retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
56216 +                       }
56217 +               }
56218 +               if (gintr_status.b.epmismatch) {
56219 +                       retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
56220 +               }
56221 +               if (gintr_status.b.fetsusp) {
56222 +                       retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
56223 +               }
56224 +               if (gintr_status.b.ginnakeff) {
56225 +                       retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
56226 +               }
56227 +               if (gintr_status.b.incomplisoin) {
56228 +                       retval |=
56229 +                           dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
56230 +               }
56231 +               if (gintr_status.b.incomplisoout) {
56232 +                       retval |=
56233 +                           dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
56234 +               }
56235 +
56236 +               /* In MPI mode Device Endpoints interrupts are asserted
56237 +                * without setting outepintr and inepint bits set, so these
56238 +                * Interrupt handlers are called without checking these bit-fields
56239 +                */
56240 +               if (core_if->multiproc_int_enable) {
56241 +                       retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
56242 +                       retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
56243 +               }
56244 +#ifdef VERBOSE
56245 +               DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
56246 +                           DWC_READ_REG32(&global_regs->gintsts));
56247 +#endif
56248 +               DWC_SPINUNLOCK(pcd->lock);
56249 +       }
56250 +       return retval;
56251 +}
56252 +
56253 +#endif /* DWC_HOST_ONLY */
56254 --- /dev/null
56255 +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c
56256 @@ -0,0 +1,1280 @@
56257 + /* ==========================================================================
56258 +  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
56259 +  * $Revision: #21 $
56260 +  * $Date: 2012/08/10 $
56261 +  * $Change: 2047372 $
56262 +  *
56263 +  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
56264 +  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
56265 +  * otherwise expressly agreed to in writing between Synopsys and you.
56266 +  *
56267 +  * The Software IS NOT an item of Licensed Software or Licensed Product under
56268 +  * any End User Software License Agreement or Agreement for Licensed Product
56269 +  * with Synopsys or any supplement thereto. You are permitted to use and
56270 +  * redistribute this Software in source and binary forms, with or without
56271 +  * modification, provided that redistributions of source code must retain this
56272 +  * notice. You may not view, use, disclose, copy or distribute this file or
56273 +  * any information contained herein except pursuant to this license grant from
56274 +  * Synopsys. If you do not agree with this notice, including the disclaimer
56275 +  * below, then you are not authorized to use the Software.
56276 +  *
56277 +  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
56278 +  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
56279 +  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
56280 +  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
56281 +  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
56282 +  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
56283 +  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
56284 +  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56285 +  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56286 +  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56287 +  * DAMAGE.
56288 +  * ========================================================================== */
56289 +#ifndef DWC_HOST_ONLY
56290 +
56291 +/** @file
56292 + * This file implements the Peripheral Controller Driver.
56293 + *
56294 + * The Peripheral Controller Driver (PCD) is responsible for
56295 + * translating requests from the Function Driver into the appropriate
56296 + * actions on the DWC_otg controller. It isolates the Function Driver
56297 + * from the specifics of the controller by providing an API to the
56298 + * Function Driver.
56299 + *
56300 + * The Peripheral Controller Driver for Linux will implement the
56301 + * Gadget API, so that the existing Gadget drivers can be used.
56302 + * (Gadget Driver is the Linux terminology for a Function Driver.)
56303 + *
56304 + * The Linux Gadget API is defined in the header file
56305 + * <code><linux/usb_gadget.h></code>.  The USB EP operations API is
56306 + * defined in the structure <code>usb_ep_ops</code> and the USB
56307 + * Controller API is defined in the structure
56308 + * <code>usb_gadget_ops</code>.
56309 + *
56310 + */
56311 +
56312 +#include "dwc_otg_os_dep.h"
56313 +#include "dwc_otg_pcd_if.h"
56314 +#include "dwc_otg_pcd.h"
56315 +#include "dwc_otg_driver.h"
56316 +#include "dwc_otg_dbg.h"
56317 +
56318 +extern bool fiq_enable;
56319 +
56320 +static struct gadget_wrapper {
56321 +       dwc_otg_pcd_t *pcd;
56322 +
56323 +       struct usb_gadget gadget;
56324 +       struct usb_gadget_driver *driver;
56325 +
56326 +       struct usb_ep ep0;
56327 +       struct usb_ep in_ep[16];
56328 +       struct usb_ep out_ep[16];
56329 +
56330 +} *gadget_wrapper;
56331 +
56332 +/* Display the contents of the buffer */
56333 +extern void dump_msg(const u8 * buf, unsigned int length);
56334 +/**
56335 + * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case
56336 + * if the endpoint is not found
56337 + */
56338 +static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
56339 +{
56340 +       int i;
56341 +       if (pcd->ep0.priv == handle) {
56342 +               return &pcd->ep0;
56343 +       }
56344 +
56345 +       for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
56346 +               if (pcd->in_ep[i].priv == handle)
56347 +                       return &pcd->in_ep[i];
56348 +               if (pcd->out_ep[i].priv == handle)
56349 +                       return &pcd->out_ep[i];
56350 +       }
56351 +
56352 +       return NULL;
56353 +}
56354 +
56355 +/* USB Endpoint Operations */
56356 +/*
56357 + * The following sections briefly describe the behavior of the Gadget
56358 + * API endpoint operations implemented in the DWC_otg driver
56359 + * software. Detailed descriptions of the generic behavior of each of
56360 + * these functions can be found in the Linux header file
56361 + * include/linux/usb_gadget.h.
56362 + *
56363 + * The Gadget API provides wrapper functions for each of the function
56364 + * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
56365 + * function, which then calls the underlying PCD function. The
56366 + * following sections are named according to the wrapper
56367 + * functions. Within each section, the corresponding DWC_otg PCD
56368 + * function name is specified.
56369 + *
56370 + */
56371 +
56372 +/**
56373 + * This function is called by the Gadget Driver for each EP to be
56374 + * configured for the current configuration (SET_CONFIGURATION).
56375 + *
56376 + * This function initializes the dwc_otg_ep_t data structure, and then
56377 + * calls dwc_otg_ep_activate.
56378 + */
56379 +static int ep_enable(struct usb_ep *usb_ep,
56380 +                    const struct usb_endpoint_descriptor *ep_desc)
56381 +{
56382 +       int retval;
56383 +
56384 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
56385 +
56386 +       if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
56387 +               DWC_WARN("%s, bad ep or descriptor\n", __func__);
56388 +               return -EINVAL;
56389 +       }
56390 +       if (usb_ep == &gadget_wrapper->ep0) {
56391 +               DWC_WARN("%s, bad ep(0)\n", __func__);
56392 +               return -EINVAL;
56393 +       }
56394 +
56395 +       /* Check FIFO size? */
56396 +       if (!ep_desc->wMaxPacketSize) {
56397 +               DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
56398 +               return -ERANGE;
56399 +       }
56400 +
56401 +       if (!gadget_wrapper->driver ||
56402 +           gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
56403 +               DWC_WARN("%s, bogus device state\n", __func__);
56404 +               return -ESHUTDOWN;
56405 +       }
56406 +
56407 +       /* Delete after check - MAS */
56408 +#if 0
56409 +       nat = (uint32_t) ep_desc->wMaxPacketSize;
56410 +       printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
56411 +       nat = (nat >> 11) & 0x03;
56412 +       printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
56413 +#endif
56414 +       retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
56415 +                                      (const uint8_t *)ep_desc,
56416 +                                      (void *)usb_ep);
56417 +       if (retval) {
56418 +               DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
56419 +               return -EINVAL;
56420 +       }
56421 +
56422 +       usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
56423 +
56424 +       return 0;
56425 +}
56426 +
56427 +/**
56428 + * This function is called when an EP is disabled due to disconnect or
56429 + * change in configuration. Any pending requests will terminate with a
56430 + * status of -ESHUTDOWN.
56431 + *
56432 + * This function modifies the dwc_otg_ep_t data structure for this EP,
56433 + * and then calls dwc_otg_ep_deactivate.
56434 + */
56435 +static int ep_disable(struct usb_ep *usb_ep)
56436 +{
56437 +       int retval;
56438 +
56439 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
56440 +       if (!usb_ep) {
56441 +               DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
56442 +                           usb_ep ? usb_ep->name : NULL);
56443 +               return -EINVAL;
56444 +       }
56445 +
56446 +       retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
56447 +       if (retval) {
56448 +               retval = -EINVAL;
56449 +       }
56450 +
56451 +       return retval;
56452 +}
56453 +
56454 +/**
56455 + * This function allocates a request object to use with the specified
56456 + * endpoint.
56457 + *
56458 + * @param ep The endpoint to be used with with the request
56459 + * @param gfp_flags the GFP_* flags to use.
56460 + */
56461 +static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
56462 +                                                    gfp_t gfp_flags)
56463 +{
56464 +       struct usb_request *usb_req;
56465 +
56466 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
56467 +       if (0 == ep) {
56468 +               DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
56469 +               return 0;
56470 +       }
56471 +       usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
56472 +       if (0 == usb_req) {
56473 +               DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
56474 +               return 0;
56475 +       }
56476 +       memset(usb_req, 0, sizeof(*usb_req));
56477 +       usb_req->dma = DWC_DMA_ADDR_INVALID;
56478 +
56479 +       return usb_req;
56480 +}
56481 +
56482 +/**
56483 + * This function frees a request object.
56484 + *
56485 + * @param ep The endpoint associated with the request
56486 + * @param req The request being freed
56487 + */
56488 +static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
56489 +{
56490 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
56491 +
56492 +       if (0 == ep || 0 == req) {
56493 +               DWC_WARN("%s() %s\n", __func__,
56494 +                        "Invalid ep or req argument!\n");
56495 +               return;
56496 +       }
56497 +
56498 +       kfree(req);
56499 +}
56500 +
56501 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
56502 +/**
56503 + * This function allocates an I/O buffer to be used for a transfer
56504 + * to/from the specified endpoint.
56505 + *
56506 + * @param usb_ep The endpoint to be used with with the request
56507 + * @param bytes The desired number of bytes for the buffer
56508 + * @param dma Pointer to the buffer's DMA address; must be valid
56509 + * @param gfp_flags the GFP_* flags to use.
56510 + * @return address of a new buffer or null is buffer could not be allocated.
56511 + */
56512 +static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
56513 +                                     dma_addr_t * dma, gfp_t gfp_flags)
56514 +{
56515 +       void *buf;
56516 +       dwc_otg_pcd_t *pcd = 0;
56517 +
56518 +       pcd = gadget_wrapper->pcd;
56519 +
56520 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
56521 +                   dma, gfp_flags);
56522 +
56523 +       /* Check dword alignment */
56524 +       if ((bytes & 0x3UL) != 0) {
56525 +               DWC_WARN("%s() Buffer size is not a multiple of"
56526 +                        "DWORD size (%d)", __func__, bytes);
56527 +       }
56528 +
56529 +       buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
56530 +
56531 +       /* Check dword alignment */
56532 +       if (((int)buf & 0x3UL) != 0) {
56533 +               DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
56534 +                        __func__, buf);
56535 +       }
56536 +
56537 +       return buf;
56538 +}
56539 +
56540 +/**
56541 + * This function frees an I/O buffer that was allocated by alloc_buffer.
56542 + *
56543 + * @param usb_ep the endpoint associated with the buffer
56544 + * @param buf address of the buffer
56545 + * @param dma The buffer's DMA address
56546 + * @param bytes The number of bytes of the buffer
56547 + */
56548 +static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
56549 +                                   dma_addr_t dma, unsigned bytes)
56550 +{
56551 +       dwc_otg_pcd_t *pcd = 0;
56552 +
56553 +       pcd = gadget_wrapper->pcd;
56554 +
56555 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
56556 +
56557 +       dma_free_coherent(NULL, bytes, buf, dma);
56558 +}
56559 +#endif
56560 +
56561 +/**
56562 + * This function is used to submit an I/O Request to an EP.
56563 + *
56564 + *     - When the request completes the request's completion callback
56565 + *       is called to return the request to the driver.
56566 + *     - An EP, except control EPs, may have multiple requests
56567 + *       pending.
56568 + *     - Once submitted the request cannot be examined or modified.
56569 + *     - Each request is turned into one or more packets.
56570 + *     - A BULK EP can queue any amount of data; the transfer is
56571 + *       packetized.
56572 + *     - Zero length Packets are specified with the request 'zero'
56573 + *       flag.
56574 + */
56575 +static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
56576 +                   gfp_t gfp_flags)
56577 +{
56578 +       dwc_otg_pcd_t *pcd;
56579 +       struct dwc_otg_pcd_ep *ep = NULL;
56580 +       int retval = 0, is_isoc_ep = 0;
56581 +       dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
56582 +
56583 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
56584 +                   __func__, usb_ep, usb_req, gfp_flags);
56585 +
56586 +       if (!usb_req || !usb_req->complete || !usb_req->buf) {
56587 +               DWC_WARN("bad params\n");
56588 +               return -EINVAL;
56589 +       }
56590 +
56591 +       if (!usb_ep) {
56592 +               DWC_WARN("bad ep\n");
56593 +               return -EINVAL;
56594 +       }
56595 +
56596 +       pcd = gadget_wrapper->pcd;
56597 +       if (!gadget_wrapper->driver ||
56598 +           gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
56599 +               DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
56600 +                           gadget_wrapper->gadget.speed);
56601 +               DWC_WARN("bogus device state\n");
56602 +               return -ESHUTDOWN;
56603 +       }
56604 +
56605 +       DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
56606 +                   usb_ep->name, usb_req, usb_req->length, usb_req->buf);
56607 +
56608 +       usb_req->status = -EINPROGRESS;
56609 +       usb_req->actual = 0;
56610 +
56611 +       ep = ep_from_handle(pcd, usb_ep);
56612 +       if (ep == NULL)
56613 +               is_isoc_ep = 0;
56614 +       else
56615 +               is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
56616 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
56617 +       dma_addr = usb_req->dma;
56618 +#else
56619 +       if (GET_CORE_IF(pcd)->dma_enable) {
56620 +                dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
56621 +                struct device *dev = NULL;
56622 +
56623 +                if (otg_dev != NULL)
56624 +                        dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
56625 +
56626 +               if (usb_req->length != 0 &&
56627 +                    usb_req->dma == DWC_DMA_ADDR_INVALID) {
56628 +                        dma_addr = dma_map_single(dev, usb_req->buf,
56629 +                                                  usb_req->length,
56630 +                                                  ep->dwc_ep.is_in ?
56631 +                                                        DMA_TO_DEVICE:
56632 +                                                        DMA_FROM_DEVICE);
56633 +               }
56634 +       }
56635 +#endif
56636 +
56637 +#ifdef DWC_UTE_PER_IO
56638 +       if (is_isoc_ep == 1) {
56639 +               retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
56640 +                       usb_req->length, usb_req->zero, usb_req,
56641 +                       gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
56642 +               if (retval)
56643 +                       return -EINVAL;
56644 +
56645 +               return 0;
56646 +       }
56647 +#endif
56648 +       retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
56649 +                                     usb_req->length, usb_req->zero, usb_req,
56650 +                                     gfp_flags == GFP_ATOMIC ? 1 : 0);
56651 +       if (retval) {
56652 +               return -EINVAL;
56653 +       }
56654 +
56655 +       return 0;
56656 +}
56657 +
56658 +/**
56659 + * This function cancels an I/O request from an EP.
56660 + */
56661 +static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
56662 +{
56663 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
56664 +
56665 +       if (!usb_ep || !usb_req) {
56666 +               DWC_WARN("bad argument\n");
56667 +               return -EINVAL;
56668 +       }
56669 +       if (!gadget_wrapper->driver ||
56670 +           gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
56671 +               DWC_WARN("bogus device state\n");
56672 +               return -ESHUTDOWN;
56673 +       }
56674 +       if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
56675 +               return -EINVAL;
56676 +       }
56677 +
56678 +       return 0;
56679 +}
56680 +
56681 +/**
56682 + * usb_ep_set_halt stalls an endpoint.
56683 + *
56684 + * usb_ep_clear_halt clears an endpoint halt and resets its data
56685 + * toggle.
56686 + *
56687 + * Both of these functions are implemented with the same underlying
56688 + * function. The behavior depends on the value argument.
56689 + *
56690 + * @param[in] usb_ep the Endpoint to halt or clear halt.
56691 + * @param[in] value
56692 + *     - 0 means clear_halt.
56693 + *     - 1 means set_halt,
56694 + *     - 2 means clear stall lock flag.
56695 + *     - 3 means set  stall lock flag.
56696 + */
56697 +static int ep_halt(struct usb_ep *usb_ep, int value)
56698 +{
56699 +       int retval = 0;
56700 +
56701 +       DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
56702 +
56703 +       if (!usb_ep) {
56704 +               DWC_WARN("bad ep\n");
56705 +               return -EINVAL;
56706 +       }
56707 +
56708 +       retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
56709 +       if (retval == -DWC_E_AGAIN) {
56710 +               return -EAGAIN;
56711 +       } else if (retval) {
56712 +               retval = -EINVAL;
56713 +       }
56714 +
56715 +       return retval;
56716 +}
56717 +
56718 +//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
56719 +#if 0
56720 +/**
56721 + * ep_wedge: sets the halt feature and ignores clear requests
56722 + *
56723 + * @usb_ep: the endpoint being wedged
56724 + *
56725 + * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT)
56726 + * requests. If the gadget driver clears the halt status, it will
56727 + * automatically unwedge the endpoint.
56728 + *
56729 + * Returns zero on success, else negative errno. *
56730 + * Check usb_ep_set_wedge() at "usb_gadget.h" for details
56731 + */
56732 +static int ep_wedge(struct usb_ep *usb_ep)
56733 +{
56734 +       int retval = 0;
56735 +
56736 +       DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name);
56737 +
56738 +       if (!usb_ep) {
56739 +               DWC_WARN("bad ep\n");
56740 +               return -EINVAL;
56741 +       }
56742 +
56743 +       retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep);
56744 +       if (retval == -DWC_E_AGAIN) {
56745 +               retval = -EAGAIN;
56746 +       } else if (retval) {
56747 +               retval = -EINVAL;
56748 +       }
56749 +
56750 +       return retval;
56751 +}
56752 +#endif
56753 +
56754 +#ifdef DWC_EN_ISOC
56755 +/**
56756 + * This function is used to submit an ISOC Transfer Request to an EP.
56757 + *
56758 + *     - Every time a sync period completes the request's completion callback
56759 + *       is called to provide data to the gadget driver.
56760 + *     - Once submitted the request cannot be modified.
56761 + *     - Each request is turned into periodic data packets untill ISO
56762 + *       Transfer is stopped..
56763 + */
56764 +static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
56765 +                       gfp_t gfp_flags)
56766 +{
56767 +       int retval = 0;
56768 +
56769 +       if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
56770 +               DWC_WARN("bad params\n");
56771 +               return -EINVAL;
56772 +       }
56773 +
56774 +       if (!usb_ep) {
56775 +               DWC_PRINTF("bad params\n");
56776 +               return -EINVAL;
56777 +       }
56778 +
56779 +       req->status = -EINPROGRESS;
56780 +
56781 +       retval =
56782 +           dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
56783 +                                    req->buf1, req->dma0, req->dma1,
56784 +                                    req->sync_frame, req->data_pattern_frame,
56785 +                                    req->data_per_frame,
56786 +                                    req->
56787 +                                    flags & USB_REQ_ISO_ASAP ? -1 :
56788 +                                    req->start_frame, req->buf_proc_intrvl,
56789 +                                    req, gfp_flags == GFP_ATOMIC ? 1 : 0);
56790 +
56791 +       if (retval) {
56792 +               return -EINVAL;
56793 +       }
56794 +
56795 +       return retval;
56796 +}
56797 +
56798 +/**
56799 + * This function stops ISO EP Periodic Data Transfer.
56800 + */
56801 +static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
56802 +{
56803 +       int retval = 0;
56804 +       if (!usb_ep) {
56805 +               DWC_WARN("bad ep\n");
56806 +       }
56807 +
56808 +       if (!gadget_wrapper->driver ||
56809 +           gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
56810 +               DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
56811 +                           gadget_wrapper->gadget.speed);
56812 +               DWC_WARN("bogus device state\n");
56813 +       }
56814 +
56815 +       dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
56816 +       if (retval) {
56817 +               retval = -EINVAL;
56818 +       }
56819 +
56820 +       return retval;
56821 +}
56822 +
56823 +static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
56824 +                                                int packets, gfp_t gfp_flags)
56825 +{
56826 +       struct usb_iso_request *pReq = NULL;
56827 +       uint32_t req_size;
56828 +
56829 +       req_size = sizeof(struct usb_iso_request);
56830 +       req_size +=
56831 +           (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
56832 +
56833 +       pReq = kmalloc(req_size, gfp_flags);
56834 +       if (!pReq) {
56835 +               DWC_WARN("Can't allocate Iso Request\n");
56836 +               return 0;
56837 +       }
56838 +       pReq->iso_packet_desc0 = (void *)(pReq + 1);
56839 +
56840 +       pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
56841 +
56842 +       return pReq;
56843 +}
56844 +
56845 +static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
56846 +{
56847 +       kfree(req);
56848 +}
56849 +
56850 +static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
56851 +       .ep_ops = {
56852 +                  .enable = ep_enable,
56853 +                  .disable = ep_disable,
56854 +
56855 +                  .alloc_request = dwc_otg_pcd_alloc_request,
56856 +                  .free_request = dwc_otg_pcd_free_request,
56857 +
56858 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
56859 +                  .alloc_buffer = dwc_otg_pcd_alloc_buffer,
56860 +                  .free_buffer = dwc_otg_pcd_free_buffer,
56861 +#endif
56862 +
56863 +                  .queue = ep_queue,
56864 +                  .dequeue = ep_dequeue,
56865 +
56866 +                  .set_halt = ep_halt,
56867 +                  .fifo_status = 0,
56868 +                  .fifo_flush = 0,
56869 +                  },
56870 +       .iso_ep_start = iso_ep_start,
56871 +       .iso_ep_stop = iso_ep_stop,
56872 +       .alloc_iso_request = alloc_iso_request,
56873 +       .free_iso_request = free_iso_request,
56874 +};
56875 +
56876 +#else
56877 +
56878 +       int (*enable) (struct usb_ep *ep,
56879 +               const struct usb_endpoint_descriptor *desc);
56880 +       int (*disable) (struct usb_ep *ep);
56881 +
56882 +       struct usb_request *(*alloc_request) (struct usb_ep *ep,
56883 +               gfp_t gfp_flags);
56884 +       void (*free_request) (struct usb_ep *ep, struct usb_request *req);
56885 +
56886 +       int (*queue) (struct usb_ep *ep, struct usb_request *req,
56887 +               gfp_t gfp_flags);
56888 +       int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
56889 +
56890 +       int (*set_halt) (struct usb_ep *ep, int value);
56891 +       int (*set_wedge) (struct usb_ep *ep);
56892 +
56893 +       int (*fifo_status) (struct usb_ep *ep);
56894 +       void (*fifo_flush) (struct usb_ep *ep);
56895 +static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
56896 +       .enable = ep_enable,
56897 +       .disable = ep_disable,
56898 +
56899 +       .alloc_request = dwc_otg_pcd_alloc_request,
56900 +       .free_request = dwc_otg_pcd_free_request,
56901 +
56902 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
56903 +       .alloc_buffer = dwc_otg_pcd_alloc_buffer,
56904 +       .free_buffer = dwc_otg_pcd_free_buffer,
56905 +#else
56906 +       /* .set_wedge = ep_wedge, */
56907 +        .set_wedge = NULL, /* uses set_halt instead */
56908 +#endif
56909 +
56910 +       .queue = ep_queue,
56911 +       .dequeue = ep_dequeue,
56912 +
56913 +       .set_halt = ep_halt,
56914 +       .fifo_status = 0,
56915 +       .fifo_flush = 0,
56916 +
56917 +};
56918 +
56919 +#endif /* _EN_ISOC_ */
56920 +/*     Gadget Operations */
56921 +/**
56922 + * The following gadget operations will be implemented in the DWC_otg
56923 + * PCD. Functions in the API that are not described below are not
56924 + * implemented.
56925 + *
56926 + * The Gadget API provides wrapper functions for each of the function
56927 + * pointers defined in usb_gadget_ops. The Gadget Driver calls the
56928 + * wrapper function, which then calls the underlying PCD function. The
56929 + * following sections are named according to the wrapper functions
56930 + * (except for ioctl, which doesn't have a wrapper function). Within
56931 + * each section, the corresponding DWC_otg PCD function name is
56932 + * specified.
56933 + *
56934 + */
56935 +
56936 +/**
56937 + *Gets the USB Frame number of the last SOF.
56938 + */
56939 +static int get_frame_number(struct usb_gadget *gadget)
56940 +{
56941 +       struct gadget_wrapper *d;
56942 +
56943 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
56944 +
56945 +       if (gadget == 0) {
56946 +               return -ENODEV;
56947 +       }
56948 +
56949 +       d = container_of(gadget, struct gadget_wrapper, gadget);
56950 +       return dwc_otg_pcd_get_frame_number(d->pcd);
56951 +}
56952 +
56953 +#ifdef CONFIG_USB_DWC_OTG_LPM
56954 +static int test_lpm_enabled(struct usb_gadget *gadget)
56955 +{
56956 +       struct gadget_wrapper *d;
56957 +
56958 +       d = container_of(gadget, struct gadget_wrapper, gadget);
56959 +
56960 +       return dwc_otg_pcd_is_lpm_enabled(d->pcd);
56961 +}
56962 +#endif
56963 +
56964 +/**
56965 + * Initiates Session Request Protocol (SRP) to wakeup the host if no
56966 + * session is in progress. If a session is already in progress, but
56967 + * the device is suspended, remote wakeup signaling is started.
56968 + *
56969 + */
56970 +static int wakeup(struct usb_gadget *gadget)
56971 +{
56972 +       struct gadget_wrapper *d;
56973 +
56974 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
56975 +
56976 +       if (gadget == 0) {
56977 +               return -ENODEV;
56978 +       } else {
56979 +               d = container_of(gadget, struct gadget_wrapper, gadget);
56980 +       }
56981 +       dwc_otg_pcd_wakeup(d->pcd);
56982 +       return 0;
56983 +}
56984 +
56985 +static const struct usb_gadget_ops dwc_otg_pcd_ops = {
56986 +       .get_frame = get_frame_number,
56987 +       .wakeup = wakeup,
56988 +#ifdef CONFIG_USB_DWC_OTG_LPM
56989 +       .lpm_support = test_lpm_enabled,
56990 +#endif
56991 +       // current versions must always be self-powered
56992 +};
56993 +
56994 +static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
56995 +{
56996 +       int retval = -DWC_E_NOT_SUPPORTED;
56997 +       if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
56998 +               retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
56999 +                                                      (struct usb_ctrlrequest
57000 +                                                       *)bytes);
57001 +       }
57002 +
57003 +       if (retval == -ENOTSUPP) {
57004 +               retval = -DWC_E_NOT_SUPPORTED;
57005 +       } else if (retval < 0) {
57006 +               retval = -DWC_E_INVALID;
57007 +       }
57008 +
57009 +       return retval;
57010 +}
57011 +
57012 +#ifdef DWC_EN_ISOC
57013 +static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57014 +                         void *req_handle, int proc_buf_num)
57015 +{
57016 +       int i, packet_count;
57017 +       struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
57018 +       struct usb_iso_request *iso_req = req_handle;
57019 +
57020 +       if (proc_buf_num) {
57021 +               iso_packet = iso_req->iso_packet_desc1;
57022 +       } else {
57023 +               iso_packet = iso_req->iso_packet_desc0;
57024 +       }
57025 +       packet_count =
57026 +           dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
57027 +       for (i = 0; i < packet_count; ++i) {
57028 +               int status;
57029 +               int actual;
57030 +               int offset;
57031 +               dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
57032 +                                                 i, &status, &actual, &offset);
57033 +               switch (status) {
57034 +               case -DWC_E_NO_DATA:
57035 +                       status = -ENODATA;
57036 +                       break;
57037 +               default:
57038 +                       if (status) {
57039 +                               DWC_PRINTF("unknown status in isoc packet\n");
57040 +                       }
57041 +
57042 +               }
57043 +               iso_packet[i].status = status;
57044 +               iso_packet[i].offset = offset;
57045 +               iso_packet[i].actual_length = actual;
57046 +       }
57047 +
57048 +       iso_req->status = 0;
57049 +       iso_req->process_buffer(ep_handle, iso_req);
57050 +
57051 +       return 0;
57052 +}
57053 +#endif /* DWC_EN_ISOC */
57054 +
57055 +#ifdef DWC_UTE_PER_IO
57056 +/**
57057 + * Copy the contents of the extended request to the Linux usb_request's
57058 + * extended part and call the gadget's completion.
57059 + *
57060 + * @param pcd                  Pointer to the pcd structure
57061 + * @param ep_handle            Void pointer to the usb_ep structure
57062 + * @param req_handle   Void pointer to the usb_request structure
57063 + * @param status               Request status returned from the portable logic
57064 + * @param ereq_port            Void pointer to the extended request structure
57065 + *                                             created in the the portable part that contains the
57066 + *                                             results of the processed iso packets.
57067 + */
57068 +static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57069 +                          void *req_handle, int32_t status, void *ereq_port)
57070 +{
57071 +       struct dwc_ute_iso_req_ext *ereqorg = NULL;
57072 +       struct dwc_iso_xreq_port *ereqport = NULL;
57073 +       struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
57074 +       int i;
57075 +       struct usb_request *req;
57076 +       //struct dwc_ute_iso_packet_descriptor *
57077 +       //int status = 0;
57078 +
57079 +       req = (struct usb_request *)req_handle;
57080 +       ereqorg = &req->ext_req;
57081 +       ereqport = (struct dwc_iso_xreq_port *)ereq_port;
57082 +       desc_org = ereqorg->per_io_frame_descs;
57083 +
57084 +       if (req && req->complete) {
57085 +               /* Copy the request data from the portable logic to our request */
57086 +               for (i = 0; i < ereqport->pio_pkt_count; i++) {
57087 +                       desc_org[i].actual_length =
57088 +                           ereqport->per_io_frame_descs[i].actual_length;
57089 +                       desc_org[i].status =
57090 +                           ereqport->per_io_frame_descs[i].status;
57091 +               }
57092 +
57093 +               switch (status) {
57094 +               case -DWC_E_SHUTDOWN:
57095 +                       req->status = -ESHUTDOWN;
57096 +                       break;
57097 +               case -DWC_E_RESTART:
57098 +                       req->status = -ECONNRESET;
57099 +                       break;
57100 +               case -DWC_E_INVALID:
57101 +                       req->status = -EINVAL;
57102 +                       break;
57103 +               case -DWC_E_TIMEOUT:
57104 +                       req->status = -ETIMEDOUT;
57105 +                       break;
57106 +               default:
57107 +                       req->status = status;
57108 +               }
57109 +
57110 +               /* And call the gadget's completion */
57111 +               req->complete(ep_handle, req);
57112 +       }
57113 +
57114 +       return 0;
57115 +}
57116 +#endif /* DWC_UTE_PER_IO */
57117 +
57118 +static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
57119 +                    void *req_handle, int32_t status, uint32_t actual)
57120 +{
57121 +       struct usb_request *req = (struct usb_request *)req_handle;
57122 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
57123 +       struct dwc_otg_pcd_ep *ep = NULL;
57124 +#endif
57125 +
57126 +       if (req && req->complete) {
57127 +               switch (status) {
57128 +               case -DWC_E_SHUTDOWN:
57129 +                       req->status = -ESHUTDOWN;
57130 +                       break;
57131 +               case -DWC_E_RESTART:
57132 +                       req->status = -ECONNRESET;
57133 +                       break;
57134 +               case -DWC_E_INVALID:
57135 +                       req->status = -EINVAL;
57136 +                       break;
57137 +               case -DWC_E_TIMEOUT:
57138 +                       req->status = -ETIMEDOUT;
57139 +                       break;
57140 +               default:
57141 +                       req->status = status;
57142 +
57143 +               }
57144 +
57145 +               req->actual = actual;
57146 +               DWC_SPINUNLOCK(pcd->lock);
57147 +               req->complete(ep_handle, req);
57148 +               DWC_SPINLOCK(pcd->lock);
57149 +       }
57150 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
57151 +       ep = ep_from_handle(pcd, ep_handle);
57152 +       if (GET_CORE_IF(pcd)->dma_enable) {
57153 +                if (req->length != 0) {
57154 +                        dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev;
57155 +                        struct device *dev = NULL;
57156 +
57157 +                        if (otg_dev != NULL)
57158 +                                  dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep);
57159 +
57160 +                       dma_unmap_single(dev, req->dma, req->length,
57161 +                                         ep->dwc_ep.is_in ?
57162 +                                                DMA_TO_DEVICE: DMA_FROM_DEVICE);
57163 +                }
57164 +       }
57165 +#endif
57166 +
57167 +       return 0;
57168 +}
57169 +
57170 +static int _connect(dwc_otg_pcd_t * pcd, int speed)
57171 +{
57172 +       gadget_wrapper->gadget.speed = speed;
57173 +       return 0;
57174 +}
57175 +
57176 +static int _disconnect(dwc_otg_pcd_t * pcd)
57177 +{
57178 +       if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
57179 +               gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
57180 +       }
57181 +       return 0;
57182 +}
57183 +
57184 +static int _resume(dwc_otg_pcd_t * pcd)
57185 +{
57186 +       if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
57187 +               gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
57188 +       }
57189 +
57190 +       return 0;
57191 +}
57192 +
57193 +static int _suspend(dwc_otg_pcd_t * pcd)
57194 +{
57195 +       if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
57196 +               gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
57197 +       }
57198 +       return 0;
57199 +}
57200 +
57201 +/**
57202 + * This function updates the otg values in the gadget structure.
57203 + */
57204 +static int _hnp_changed(dwc_otg_pcd_t * pcd)
57205 +{
57206 +
57207 +       if (!gadget_wrapper->gadget.is_otg)
57208 +               return 0;
57209 +
57210 +       gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
57211 +       gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
57212 +       gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
57213 +       return 0;
57214 +}
57215 +
57216 +static int _reset(dwc_otg_pcd_t * pcd)
57217 +{
57218 +       return 0;
57219 +}
57220 +
57221 +#ifdef DWC_UTE_CFI
57222 +static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
57223 +{
57224 +       int retval = -DWC_E_INVALID;
57225 +       if (gadget_wrapper->driver->cfi_feature_setup) {
57226 +               retval =
57227 +                   gadget_wrapper->driver->
57228 +                   cfi_feature_setup(&gadget_wrapper->gadget,
57229 +                                     (struct cfi_usb_ctrlrequest *)cfi_req);
57230 +       }
57231 +
57232 +       return retval;
57233 +}
57234 +#endif
57235 +
57236 +static const struct dwc_otg_pcd_function_ops fops = {
57237 +       .complete = _complete,
57238 +#ifdef DWC_EN_ISOC
57239 +       .isoc_complete = _isoc_complete,
57240 +#endif
57241 +       .setup = _setup,
57242 +       .disconnect = _disconnect,
57243 +       .connect = _connect,
57244 +       .resume = _resume,
57245 +       .suspend = _suspend,
57246 +       .hnp_changed = _hnp_changed,
57247 +       .reset = _reset,
57248 +#ifdef DWC_UTE_CFI
57249 +       .cfi_setup = _cfi_setup,
57250 +#endif
57251 +#ifdef DWC_UTE_PER_IO
57252 +       .xisoc_complete = _xisoc_complete,
57253 +#endif
57254 +};
57255 +
57256 +/**
57257 + * This function is the top level PCD interrupt handler.
57258 + */
57259 +static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
57260 +{
57261 +       dwc_otg_pcd_t *pcd = dev;
57262 +       int32_t retval = IRQ_NONE;
57263 +
57264 +       retval = dwc_otg_pcd_handle_intr(pcd);
57265 +       if (retval != 0) {
57266 +               S3C2410X_CLEAR_EINTPEND();
57267 +       }
57268 +       return IRQ_RETVAL(retval);
57269 +}
57270 +
57271 +/**
57272 + * This function initialized the usb_ep structures to there default
57273 + * state.
57274 + *
57275 + * @param d Pointer on gadget_wrapper.
57276 + */
57277 +void gadget_add_eps(struct gadget_wrapper *d)
57278 +{
57279 +       static const char *names[] = {
57280 +
57281 +               "ep0",
57282 +               "ep1in",
57283 +               "ep2in",
57284 +               "ep3in",
57285 +               "ep4in",
57286 +               "ep5in",
57287 +               "ep6in",
57288 +               "ep7in",
57289 +               "ep8in",
57290 +               "ep9in",
57291 +               "ep10in",
57292 +               "ep11in",
57293 +               "ep12in",
57294 +               "ep13in",
57295 +               "ep14in",
57296 +               "ep15in",
57297 +               "ep1out",
57298 +               "ep2out",
57299 +               "ep3out",
57300 +               "ep4out",
57301 +               "ep5out",
57302 +               "ep6out",
57303 +               "ep7out",
57304 +               "ep8out",
57305 +               "ep9out",
57306 +               "ep10out",
57307 +               "ep11out",
57308 +               "ep12out",
57309 +               "ep13out",
57310 +               "ep14out",
57311 +               "ep15out"
57312 +       };
57313 +
57314 +       int i;
57315 +       struct usb_ep *ep;
57316 +       int8_t dev_endpoints;
57317 +
57318 +       DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
57319 +
57320 +       INIT_LIST_HEAD(&d->gadget.ep_list);
57321 +       d->gadget.ep0 = &d->ep0;
57322 +       d->gadget.speed = USB_SPEED_UNKNOWN;
57323 +
57324 +       INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
57325 +
57326 +       /**
57327 +        * Initialize the EP0 structure.
57328 +        */
57329 +       ep = &d->ep0;
57330 +
57331 +       /* Init the usb_ep structure. */
57332 +       ep->name = names[0];
57333 +       ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57334 +
57335 +       /**
57336 +        * @todo NGS: What should the max packet size be set to
57337 +        * here?  Before EP type is set?
57338 +        */
57339 +       ep->maxpacket = MAX_PACKET_SIZE;
57340 +       dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
57341 +
57342 +       list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57343 +
57344 +       /**
57345 +        * Initialize the EP structures.
57346 +        */
57347 +       dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
57348 +
57349 +       for (i = 0; i < dev_endpoints; i++) {
57350 +               ep = &d->in_ep[i];
57351 +
57352 +               /* Init the usb_ep structure. */
57353 +               ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
57354 +               ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57355 +
57356 +               /**
57357 +                * @todo NGS: What should the max packet size be set to
57358 +                * here?  Before EP type is set?
57359 +                */
57360 +               ep->maxpacket = MAX_PACKET_SIZE;
57361 +               list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57362 +       }
57363 +
57364 +       dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
57365 +
57366 +       for (i = 0; i < dev_endpoints; i++) {
57367 +               ep = &d->out_ep[i];
57368 +
57369 +               /* Init the usb_ep structure. */
57370 +               ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
57371 +               ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
57372 +
57373 +               /**
57374 +                * @todo NGS: What should the max packet size be set to
57375 +                * here?  Before EP type is set?
57376 +                */
57377 +               ep->maxpacket = MAX_PACKET_SIZE;
57378 +
57379 +               list_add_tail(&ep->ep_list, &d->gadget.ep_list);
57380 +       }
57381 +
57382 +       /* remove ep0 from the list.  There is a ep0 pointer. */
57383 +       list_del_init(&d->ep0.ep_list);
57384 +
57385 +       d->ep0.maxpacket = MAX_EP0_SIZE;
57386 +}
57387 +
57388 +/**
57389 + * This function releases the Gadget device.
57390 + * required by device_unregister().
57391 + *
57392 + * @todo Should this do something?     Should it free the PCD?
57393 + */
57394 +static void dwc_otg_pcd_gadget_release(struct device *dev)
57395 +{
57396 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
57397 +}
57398 +
57399 +static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev)
57400 +{
57401 +       static char pcd_name[] = "dwc_otg_pcd";
57402 +       dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
57403 +       struct gadget_wrapper *d;
57404 +       int retval;
57405 +
57406 +       d = DWC_ALLOC(sizeof(*d));
57407 +       if (d == NULL) {
57408 +               return NULL;
57409 +       }
57410 +
57411 +       memset(d, 0, sizeof(*d));
57412 +
57413 +       d->gadget.name = pcd_name;
57414 +       d->pcd = otg_dev->pcd;
57415 +
57416 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
57417 +       strcpy(d->gadget.dev.bus_id, "gadget");
57418 +#else
57419 +       dev_set_name(&d->gadget.dev, "%s", "gadget");
57420 +#endif
57421 +
57422 +       d->gadget.dev.parent = &_dev->dev;
57423 +       d->gadget.dev.release = dwc_otg_pcd_gadget_release;
57424 +       d->gadget.ops = &dwc_otg_pcd_ops;
57425 +       d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL;
57426 +       d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
57427 +
57428 +       d->driver = 0;
57429 +       /* Register the gadget device */
57430 +       retval = device_register(&d->gadget.dev);
57431 +       if (retval != 0) {
57432 +               DWC_ERROR("device_register failed\n");
57433 +               DWC_FREE(d);
57434 +               return NULL;
57435 +       }
57436 +
57437 +       return d;
57438 +}
57439 +
57440 +static void free_wrapper(struct gadget_wrapper *d)
57441 +{
57442 +       if (d->driver) {
57443 +               /* should have been done already by driver model core */
57444 +               DWC_WARN("driver '%s' is still registered\n",
57445 +                        d->driver->driver.name);
57446 +#ifdef CONFIG_USB_GADGET
57447 +               usb_gadget_unregister_driver(d->driver);
57448 +#endif
57449 +       }
57450 +
57451 +       device_unregister(&d->gadget.dev);
57452 +       DWC_FREE(d);
57453 +}
57454 +
57455 +/**
57456 + * This function initialized the PCD portion of the driver.
57457 + *
57458 + */
57459 +int pcd_init(dwc_bus_dev_t *_dev)
57460 +{
57461 +       dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
57462 +       int retval = 0;
57463 +
57464 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev);
57465 +
57466 +       otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
57467 +
57468 +       if (!otg_dev->pcd) {
57469 +               DWC_ERROR("dwc_otg_pcd_init failed\n");
57470 +               return -ENOMEM;
57471 +       }
57472 +
57473 +       otg_dev->pcd->otg_dev = otg_dev;
57474 +       gadget_wrapper = alloc_wrapper(_dev);
57475 +
57476 +       /*
57477 +        * Initialize EP structures
57478 +        */
57479 +       gadget_add_eps(gadget_wrapper);
57480 +       /*
57481 +        * Setup interupt handler
57482 +        */
57483 +#ifdef PLATFORM_INTERFACE
57484 +       DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
57485 +                    platform_get_irq(_dev, fiq_enable ? 0 : 1));
57486 +       retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq,
57487 +                            IRQF_SHARED, gadget_wrapper->gadget.name,
57488 +                            otg_dev->pcd);
57489 +       if (retval != 0) {
57490 +               DWC_ERROR("request of irq%d failed\n",
57491 +                          platform_get_irq(_dev, fiq_enable ? 0 : 1));
57492 +               free_wrapper(gadget_wrapper);
57493 +               return -EBUSY;
57494 +       }
57495 +#else
57496 +       DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n",
57497 +                    _dev->irq);
57498 +       retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
57499 +                            IRQF_SHARED | IRQF_DISABLED,
57500 +                            gadget_wrapper->gadget.name, otg_dev->pcd);
57501 +       if (retval != 0) {
57502 +               DWC_ERROR("request of irq%d failed\n", _dev->irq);
57503 +               free_wrapper(gadget_wrapper);
57504 +               return -EBUSY;
57505 +       }
57506 +#endif
57507 +
57508 +       dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
57509 +
57510 +       return retval;
57511 +}
57512 +
57513 +/**
57514 + * Cleanup the PCD.
57515 + */
57516 +void pcd_remove(dwc_bus_dev_t *_dev)
57517 +{
57518 +       dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev);
57519 +       dwc_otg_pcd_t *pcd = otg_dev->pcd;
57520 +
57521 +       DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev);
57522 +
57523 +       /*
57524 +        * Free the IRQ
57525 +        */
57526 +#ifdef PLATFORM_INTERFACE
57527 +       free_irq(platform_get_irq(_dev, 0), pcd);
57528 +#else
57529 +       free_irq(_dev->irq, pcd);
57530 +#endif
57531 +       dwc_otg_pcd_remove(otg_dev->pcd);
57532 +       free_wrapper(gadget_wrapper);
57533 +       otg_dev->pcd = 0;
57534 +}
57535 +
57536 +#endif /* DWC_HOST_ONLY */
57537 --- /dev/null
57538 +++ b/drivers/usb/host/dwc_otg/dwc_otg_regs.h
57539 @@ -0,0 +1,2550 @@
57540 +/* ==========================================================================
57541 + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
57542 + * $Revision: #98 $
57543 + * $Date: 2012/08/10 $
57544 + * $Change: 2047372 $
57545 + *
57546 + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
57547 + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
57548 + * otherwise expressly agreed to in writing between Synopsys and you.
57549 + *
57550 + * The Software IS NOT an item of Licensed Software or Licensed Product under
57551 + * any End User Software License Agreement or Agreement for Licensed Product
57552 + * with Synopsys or any supplement thereto. You are permitted to use and
57553 + * redistribute this Software in source and binary forms, with or without
57554 + * modification, provided that redistributions of source code must retain this
57555 + * notice. You may not view, use, disclose, copy or distribute this file or
57556 + * any information contained herein except pursuant to this license grant from
57557 + * Synopsys. If you do not agree with this notice, including the disclaimer
57558 + * below, then you are not authorized to use the Software.
57559 + *
57560 + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
57561 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57562 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
57563 + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
57564 + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
57565 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
57566 + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
57567 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
57568 + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57569 + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
57570 + * DAMAGE.
57571 + * ========================================================================== */
57572 +
57573 +#ifndef __DWC_OTG_REGS_H__
57574 +#define __DWC_OTG_REGS_H__
57575 +
57576 +#include "dwc_otg_core_if.h"
57577 +
57578 +/**
57579 + * @file
57580 + *
57581 + * This file contains the data structures for accessing the DWC_otg core registers.
57582 + *
57583 + * The application interfaces with the HS OTG core by reading from and
57584 + * writing to the Control and Status Register (CSR) space through the
57585 + * AHB Slave interface. These registers are 32 bits wide, and the
57586 + * addresses are 32-bit-block aligned.
57587 + * CSRs are classified as follows:
57588 + * - Core Global Registers
57589 + * - Device Mode Registers
57590 + * - Device Global Registers
57591 + * - Device Endpoint Specific Registers
57592 + * - Host Mode Registers
57593 + * - Host Global Registers
57594 + * - Host Port CSRs
57595 + * - Host Channel Specific Registers
57596 + *
57597 + * Only the Core Global registers can be accessed in both Device and
57598 + * Host modes. When the HS OTG core is operating in one mode, either
57599 + * Device or Host, the application must not access registers from the
57600 + * other mode. When the core switches from one mode to another, the
57601 + * registers in the new mode of operation must be reprogrammed as they
57602 + * would be after a power-on reset.
57603 + */
57604 +
57605 +/****************************************************************************/
57606 +/** DWC_otg Core registers .
57607 + * The dwc_otg_core_global_regs structure defines the size
57608 + * and relative field offsets for the Core Global registers.
57609 + */
57610 +typedef struct dwc_otg_core_global_regs {
57611 +       /** OTG Control and Status Register.  <i>Offset: 000h</i> */
57612 +       volatile uint32_t gotgctl;
57613 +       /** OTG Interrupt Register.      <i>Offset: 004h</i> */
57614 +       volatile uint32_t gotgint;
57615 +       /**Core AHB Configuration Register.      <i>Offset: 008h</i> */
57616 +       volatile uint32_t gahbcfg;
57617 +
57618 +#define DWC_GLBINTRMASK                0x0001
57619 +#define DWC_DMAENABLE          0x0020
57620 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080
57621 +#define DWC_NPTXEMPTYLVL_HALFEMPTY     0x0000
57622 +#define DWC_PTXEMPTYLVL_EMPTY  0x0100
57623 +#define DWC_PTXEMPTYLVL_HALFEMPTY      0x0000
57624 +
57625 +       /**Core USB Configuration Register.      <i>Offset: 00Ch</i> */
57626 +       volatile uint32_t gusbcfg;
57627 +       /**Core Reset Register.  <i>Offset: 010h</i> */
57628 +       volatile uint32_t grstctl;
57629 +       /**Core Interrupt Register.      <i>Offset: 014h</i> */
57630 +       volatile uint32_t gintsts;
57631 +       /**Core Interrupt Mask Register.  <i>Offset: 018h</i> */
57632 +       volatile uint32_t gintmsk;
57633 +       /**Receive Status Queue Read Register (Read Only).      <i>Offset: 01Ch</i> */
57634 +       volatile uint32_t grxstsr;
57635 +       /**Receive Status Queue Read & POP Register (Read Only).  <i>Offset: 020h</i>*/
57636 +       volatile uint32_t grxstsp;
57637 +       /**Receive FIFO Size Register.  <i>Offset: 024h</i> */
57638 +       volatile uint32_t grxfsiz;
57639 +       /**Non Periodic Transmit FIFO Size Register.  <i>Offset: 028h</i> */
57640 +       volatile uint32_t gnptxfsiz;
57641 +       /**Non Periodic Transmit FIFO/Queue Status Register (Read
57642 +        * Only). <i>Offset: 02Ch</i> */
57643 +       volatile uint32_t gnptxsts;
57644 +       /**I2C Access Register.  <i>Offset: 030h</i> */
57645 +       volatile uint32_t gi2cctl;
57646 +       /**PHY Vendor Control Register.  <i>Offset: 034h</i> */
57647 +       volatile uint32_t gpvndctl;
57648 +       /**General Purpose Input/Output Register.  <i>Offset: 038h</i> */
57649 +       volatile uint32_t ggpio;
57650 +       /**User ID Register.  <i>Offset: 03Ch</i> */
57651 +       volatile uint32_t guid;
57652 +       /**Synopsys ID Register (Read Only).  <i>Offset: 040h</i> */
57653 +       volatile uint32_t gsnpsid;
57654 +       /**User HW Config1 Register (Read Only).  <i>Offset: 044h</i> */
57655 +       volatile uint32_t ghwcfg1;
57656 +       /**User HW Config2 Register (Read Only).  <i>Offset: 048h</i> */
57657 +       volatile uint32_t ghwcfg2;
57658 +#define DWC_SLAVE_ONLY_ARCH 0
57659 +#define DWC_EXT_DMA_ARCH 1
57660 +#define DWC_INT_DMA_ARCH 2
57661 +
57662 +#define DWC_MODE_HNP_SRP_CAPABLE       0
57663 +#define DWC_MODE_SRP_ONLY_CAPABLE      1
57664 +#define DWC_MODE_NO_HNP_SRP_CAPABLE            2
57665 +#define DWC_MODE_SRP_CAPABLE_DEVICE            3
57666 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4
57667 +#define DWC_MODE_SRP_CAPABLE_HOST      5
57668 +#define DWC_MODE_NO_SRP_CAPABLE_HOST   6
57669 +
57670 +       /**User HW Config3 Register (Read Only).  <i>Offset: 04Ch</i> */
57671 +       volatile uint32_t ghwcfg3;
57672 +       /**User HW Config4 Register (Read Only).  <i>Offset: 050h</i>*/
57673 +       volatile uint32_t ghwcfg4;
57674 +       /** Core LPM Configuration register <i>Offset: 054h</i>*/
57675 +       volatile uint32_t glpmcfg;
57676 +       /** Global PowerDn Register <i>Offset: 058h</i> */
57677 +       volatile uint32_t gpwrdn;
57678 +       /** Global DFIFO SW Config Register  <i>Offset: 05Ch</i> */
57679 +       volatile uint32_t gdfifocfg;
57680 +       /** ADP Control Register  <i>Offset: 060h</i> */
57681 +       volatile uint32_t adpctl;
57682 +       /** Reserved  <i>Offset: 064h-0FFh</i> */
57683 +       volatile uint32_t reserved39[39];
57684 +       /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */
57685 +       volatile uint32_t hptxfsiz;
57686 +       /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled,
57687 +               otherwise Device Transmit FIFO#n Register.
57688 +        * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */
57689 +       volatile uint32_t dtxfsiz[15];
57690 +} dwc_otg_core_global_regs_t;
57691 +
57692 +/**
57693 + * This union represents the bit fields of the Core OTG Control
57694 + * and Status Register (GOTGCTL).  Set the bits using the bit
57695 + * fields then write the <i>d32</i> value to the register.
57696 + */
57697 +typedef union gotgctl_data {
57698 +       /** raw register data */
57699 +       uint32_t d32;
57700 +       /** register bits */
57701 +       struct {
57702 +               unsigned sesreqscs:1;
57703 +               unsigned sesreq:1;
57704 +               unsigned vbvalidoven:1;
57705 +               unsigned vbvalidovval:1;
57706 +               unsigned avalidoven:1;
57707 +               unsigned avalidovval:1;
57708 +               unsigned bvalidoven:1;
57709 +               unsigned bvalidovval:1;
57710 +               unsigned hstnegscs:1;
57711 +               unsigned hnpreq:1;
57712 +               unsigned hstsethnpen:1;
57713 +               unsigned devhnpen:1;
57714 +               unsigned reserved12_15:4;
57715 +               unsigned conidsts:1;
57716 +               unsigned dbnctime:1;
57717 +               unsigned asesvld:1;
57718 +               unsigned bsesvld:1;
57719 +               unsigned otgver:1;
57720 +               unsigned reserved1:1;
57721 +               unsigned multvalidbc:5;
57722 +               unsigned chirpen:1;
57723 +               unsigned reserved28_31:4;
57724 +       } b;
57725 +} gotgctl_data_t;
57726 +
57727 +/**
57728 + * This union represents the bit fields of the Core OTG Interrupt Register
57729 + * (GOTGINT).  Set/clear the bits using the bit fields then write the <i>d32</i>
57730 + * value to the register.
57731 + */
57732 +typedef union gotgint_data {
57733 +       /** raw register data */
57734 +       uint32_t d32;
57735 +       /** register bits */
57736 +       struct {
57737 +               /** Current Mode */
57738 +               unsigned reserved0_1:2;
57739 +
57740 +               /** Session End Detected */
57741 +               unsigned sesenddet:1;
57742 +
57743 +               unsigned reserved3_7:5;
57744 +
57745 +               /** Session Request Success Status Change */
57746 +               unsigned sesreqsucstschng:1;
57747 +               /** Host Negotiation Success Status Change */
57748 +               unsigned hstnegsucstschng:1;
57749 +
57750 +               unsigned reserved10_16:7;
57751 +
57752 +               /** Host Negotiation Detected */
57753 +               unsigned hstnegdet:1;
57754 +               /** A-Device Timeout Change */
57755 +               unsigned adevtoutchng:1;
57756 +               /** Debounce Done */
57757 +               unsigned debdone:1;
57758 +               /** Multi-Valued input changed */
57759 +               unsigned mvic:1;
57760 +
57761 +               unsigned reserved31_21:11;
57762 +
57763 +       } b;
57764 +} gotgint_data_t;
57765 +
57766 +/**
57767 + * This union represents the bit fields of the Core AHB Configuration
57768 + * Register (GAHBCFG). Set/clear the bits using the bit fields then
57769 + * write the <i>d32</i> value to the register.
57770 + */
57771 +typedef union gahbcfg_data {
57772 +       /** raw register data */
57773 +       uint32_t d32;
57774 +       /** register bits */
57775 +       struct {
57776 +               unsigned glblintrmsk:1;
57777 +#define DWC_GAHBCFG_GLBINT_ENABLE              1
57778 +
57779 +               unsigned hburstlen:4;
57780 +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE       0
57781 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR         1
57782 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4                3
57783 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8                5
57784 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16       7
57785 +
57786 +               unsigned dmaenable:1;
57787 +#define DWC_GAHBCFG_DMAENABLE                  1
57788 +               unsigned reserved:1;
57789 +               unsigned nptxfemplvl_txfemplvl:1;
57790 +               unsigned ptxfemplvl:1;
57791 +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY          1
57792 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY      0
57793 +               unsigned reserved9_20:12;
57794 +               unsigned remmemsupp:1;
57795 +               unsigned notialldmawrit:1;
57796 +               unsigned ahbsingle:1;
57797 +               unsigned reserved24_31:8;
57798 +       } b;
57799 +} gahbcfg_data_t;
57800 +
57801 +/**
57802 + * This union represents the bit fields of the Core USB Configuration
57803 + * Register (GUSBCFG). Set the bits using the bit fields then write
57804 + * the <i>d32</i> value to the register.
57805 + */
57806 +typedef union gusbcfg_data {
57807 +       /** raw register data */
57808 +       uint32_t d32;
57809 +       /** register bits */
57810 +       struct {
57811 +               unsigned toutcal:3;
57812 +               unsigned phyif:1;
57813 +               unsigned ulpi_utmi_sel:1;
57814 +               unsigned fsintf:1;
57815 +               unsigned physel:1;
57816 +               unsigned ddrsel:1;
57817 +               unsigned srpcap:1;
57818 +               unsigned hnpcap:1;
57819 +               unsigned usbtrdtim:4;
57820 +               unsigned reserved1:1;
57821 +               unsigned phylpwrclksel:1;
57822 +               unsigned otgutmifssel:1;
57823 +               unsigned ulpi_fsls:1;
57824 +               unsigned ulpi_auto_res:1;
57825 +               unsigned ulpi_clk_sus_m:1;
57826 +               unsigned ulpi_ext_vbus_drv:1;
57827 +               unsigned ulpi_int_vbus_indicator:1;
57828 +               unsigned term_sel_dl_pulse:1;
57829 +               unsigned indicator_complement:1;
57830 +               unsigned indicator_pass_through:1;
57831 +               unsigned ulpi_int_prot_dis:1;
57832 +               unsigned ic_usb_cap:1;
57833 +               unsigned ic_traffic_pull_remove:1;
57834 +               unsigned tx_end_delay:1;
57835 +               unsigned force_host_mode:1;
57836 +               unsigned force_dev_mode:1;
57837 +               unsigned reserved31:1;
57838 +       } b;
57839 +} gusbcfg_data_t;
57840 +
57841 +/**
57842 + * This union represents the bit fields of the Core Reset Register
57843 + * (GRSTCTL).  Set/clear the bits using the bit fields then write the
57844 + * <i>d32</i> value to the register.
57845 + */
57846 +typedef union grstctl_data {
57847 +       /** raw register data */
57848 +       uint32_t d32;
57849 +       /** register bits */
57850 +       struct {
57851 +               /** Core Soft Reset (CSftRst) (Device and Host)
57852 +                *
57853 +                * The application can flush the control logic in the
57854 +                * entire core using this bit. This bit resets the
57855 +                * pipelines in the AHB Clock domain as well as the
57856 +                * PHY Clock domain.
57857 +                *
57858 +                * The state machines are reset to an IDLE state, the
57859 +                * control bits in the CSRs are cleared, all the
57860 +                * transmit FIFOs and the receive FIFO are flushed.
57861 +                *
57862 +                * The status mask bits that control the generation of
57863 +                * the interrupt, are cleared, to clear the
57864 +                * interrupt. The interrupt status bits are not
57865 +                * cleared, so the application can get the status of
57866 +                * any events that occurred in the core after it has
57867 +                * set this bit.
57868 +                *
57869 +                * Any transactions on the AHB are terminated as soon
57870 +                * as possible following the protocol. Any
57871 +                * transactions on the USB are terminated immediately.
57872 +                *
57873 +                * The configuration settings in the CSRs are
57874 +                * unchanged, so the software doesn't have to
57875 +                * reprogram these registers (Device
57876 +                * Configuration/Host Configuration/Core System
57877 +                * Configuration/Core PHY Configuration).
57878 +                *
57879 +                * The application can write to this bit, any time it
57880 +                * wants to reset the core. This is a self clearing
57881 +                * bit and the core clears this bit after all the
57882 +                * necessary logic is reset in the core, which may
57883 +                * take several clocks, depending on the current state
57884 +                * of the core.
57885 +                */
57886 +               unsigned csftrst:1;
57887 +               /** Hclk Soft Reset
57888 +                *
57889 +                * The application uses this bit to reset the control logic in
57890 +                * the AHB clock domain. Only AHB clock domain pipelines are
57891 +                * reset.
57892 +                */
57893 +               unsigned hsftrst:1;
57894 +               /** Host Frame Counter Reset (Host Only)<br>
57895 +                *
57896 +                * The application can reset the (micro)frame number
57897 +                * counter inside the core, using this bit. When the
57898 +                * (micro)frame counter is reset, the subsequent SOF
57899 +                * sent out by the core, will have a (micro)frame
57900 +                * number of 0.
57901 +                */
57902 +               unsigned hstfrm:1;
57903 +               /** In Token Sequence Learning Queue Flush
57904 +                * (INTknQFlsh) (Device Only)
57905 +                */
57906 +               unsigned intknqflsh:1;
57907 +               /** RxFIFO Flush (RxFFlsh) (Device and Host)
57908 +                *
57909 +                * The application can flush the entire Receive FIFO
57910 +                * using this bit. The application must first
57911 +                * ensure that the core is not in the middle of a
57912 +                * transaction. The application should write into
57913 +                * this bit, only after making sure that neither the
57914 +                * DMA engine is reading from the RxFIFO nor the MAC
57915 +                * is writing the data in to the FIFO. The
57916 +                * application should wait until the bit is cleared
57917 +                * before performing any other operations. This bit
57918 +                * will takes 8 clocks (slowest of PHY or AHB clock)
57919 +                * to clear.
57920 +                */
57921 +               unsigned rxfflsh:1;
57922 +               /** TxFIFO Flush (TxFFlsh) (Device and Host).
57923 +                *
57924 +                * This bit is used to selectively flush a single or
57925 +                * all transmit FIFOs. The application must first
57926 +                * ensure that the core is not in the middle of a
57927 +                * transaction. The application should write into
57928 +                * this bit, only after making sure that neither the
57929 +                * DMA engine is writing into the TxFIFO nor the MAC
57930 +                * is reading the data out of the FIFO. The
57931 +                * application should wait until the core clears this
57932 +                * bit, before performing any operations. This bit
57933 +                * will takes 8 clocks (slowest of PHY or AHB clock)
57934 +                * to clear.
57935 +                */
57936 +               unsigned txfflsh:1;
57937 +
57938 +               /** TxFIFO Number (TxFNum) (Device and Host).
57939 +                *
57940 +                * This is the FIFO number which needs to be flushed,
57941 +                * using the TxFIFO Flush bit. This field should not
57942 +                * be changed until the TxFIFO Flush bit is cleared by
57943 +                * the core.
57944 +                *       - 0x0 : Non Periodic TxFIFO Flush
57945 +                *       - 0x1 : Periodic TxFIFO #1 Flush in device mode
57946 +                *         or Periodic TxFIFO in host mode
57947 +                *       - 0x2 : Periodic TxFIFO #2 Flush in device mode.
57948 +                *       - ...
57949 +                *       - 0xF : Periodic TxFIFO #15 Flush in device mode
57950 +                *       - 0x10: Flush all the Transmit NonPeriodic and
57951 +                *         Transmit Periodic FIFOs in the core
57952 +                */
57953 +               unsigned txfnum:5;
57954 +               /** Reserved */
57955 +               unsigned reserved11_29:19;
57956 +               /** DMA Request Signal.  Indicated DMA request is in
57957 +                * probress. Used for debug purpose. */
57958 +               unsigned dmareq:1;
57959 +               /** AHB Master Idle.  Indicates the AHB Master State
57960 +                * Machine is in IDLE condition. */
57961 +               unsigned ahbidle:1;
57962 +       } b;
57963 +} grstctl_t;
57964 +
57965 +/**
57966 + * This union represents the bit fields of the Core Interrupt Mask
57967 + * Register (GINTMSK). Set/clear the bits using the bit fields then
57968 + * write the <i>d32</i> value to the register.
57969 + */
57970 +typedef union gintmsk_data {
57971 +       /** raw register data */
57972 +       uint32_t d32;
57973 +       /** register bits */
57974 +       struct {
57975 +               unsigned reserved0:1;
57976 +               unsigned modemismatch:1;
57977 +               unsigned otgintr:1;
57978 +               unsigned sofintr:1;
57979 +               unsigned rxstsqlvl:1;
57980 +               unsigned nptxfempty:1;
57981 +               unsigned ginnakeff:1;
57982 +               unsigned goutnakeff:1;
57983 +               unsigned ulpickint:1;
57984 +               unsigned i2cintr:1;
57985 +               unsigned erlysuspend:1;
57986 +               unsigned usbsuspend:1;
57987 +               unsigned usbreset:1;
57988 +               unsigned enumdone:1;
57989 +               unsigned isooutdrop:1;
57990 +               unsigned eopframe:1;
57991 +               unsigned restoredone:1;
57992 +               unsigned epmismatch:1;
57993 +               unsigned inepintr:1;
57994 +               unsigned outepintr:1;
57995 +               unsigned incomplisoin:1;
57996 +               unsigned incomplisoout:1;
57997 +               unsigned fetsusp:1;
57998 +               unsigned resetdet:1;
57999 +               unsigned portintr:1;
58000 +               unsigned hcintr:1;
58001 +               unsigned ptxfempty:1;
58002 +               unsigned lpmtranrcvd:1;
58003 +               unsigned conidstschng:1;
58004 +               unsigned disconnect:1;
58005 +               unsigned sessreqintr:1;
58006 +               unsigned wkupintr:1;
58007 +       } b;
58008 +} gintmsk_data_t;
58009 +/**
58010 + * This union represents the bit fields of the Core Interrupt Register
58011 + * (GINTSTS).  Set/clear the bits using the bit fields then write the
58012 + * <i>d32</i> value to the register.
58013 + */
58014 +typedef union gintsts_data {
58015 +       /** raw register data */
58016 +       uint32_t d32;
58017 +#define DWC_SOF_INTR_MASK 0x0008
58018 +       /** register bits */
58019 +       struct {
58020 +#define DWC_HOST_MODE 1
58021 +               unsigned curmode:1;
58022 +               unsigned modemismatch:1;
58023 +               unsigned otgintr:1;
58024 +               unsigned sofintr:1;
58025 +               unsigned rxstsqlvl:1;
58026 +               unsigned nptxfempty:1;
58027 +               unsigned ginnakeff:1;
58028 +               unsigned goutnakeff:1;
58029 +               unsigned ulpickint:1;
58030 +               unsigned i2cintr:1;
58031 +               unsigned erlysuspend:1;
58032 +               unsigned usbsuspend:1;
58033 +               unsigned usbreset:1;
58034 +               unsigned enumdone:1;
58035 +               unsigned isooutdrop:1;
58036 +               unsigned eopframe:1;
58037 +               unsigned restoredone:1;
58038 +               unsigned epmismatch:1;
58039 +               unsigned inepint:1;
58040 +               unsigned outepintr:1;
58041 +               unsigned incomplisoin:1;
58042 +               unsigned incomplisoout:1;
58043 +               unsigned fetsusp:1;
58044 +               unsigned resetdet:1;
58045 +               unsigned portintr:1;
58046 +               unsigned hcintr:1;
58047 +               unsigned ptxfempty:1;
58048 +               unsigned lpmtranrcvd:1;
58049 +               unsigned conidstschng:1;
58050 +               unsigned disconnect:1;
58051 +               unsigned sessreqintr:1;
58052 +               unsigned wkupintr:1;
58053 +       } b;
58054 +} gintsts_data_t;
58055 +
58056 +/**
58057 + * This union represents the bit fields in the Device Receive Status Read and
58058 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
58059 + * element then read out the bits using the <i>b</i>it elements.
58060 + */
58061 +typedef union device_grxsts_data {
58062 +       /** raw register data */
58063 +       uint32_t d32;
58064 +       /** register bits */
58065 +       struct {
58066 +               unsigned epnum:4;
58067 +               unsigned bcnt:11;
58068 +               unsigned dpid:2;
58069 +
58070 +#define DWC_STS_DATA_UPDT              0x2     // OUT Data Packet
58071 +#define DWC_STS_XFER_COMP              0x3     // OUT Data Transfer Complete
58072 +
58073 +#define DWC_DSTS_GOUT_NAK              0x1     // Global OUT NAK
58074 +#define DWC_DSTS_SETUP_COMP            0x4     // Setup Phase Complete
58075 +#define DWC_DSTS_SETUP_UPDT 0x6        // SETUP Packet
58076 +               unsigned pktsts:4;
58077 +               unsigned fn:4;
58078 +               unsigned reserved25_31:7;
58079 +       } b;
58080 +} device_grxsts_data_t;
58081 +
58082 +/**
58083 + * This union represents the bit fields in the Host Receive Status Read and
58084 + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i>
58085 + * element then read out the bits using the <i>b</i>it elements.
58086 + */
58087 +typedef union host_grxsts_data {
58088 +       /** raw register data */
58089 +       uint32_t d32;
58090 +       /** register bits */
58091 +       struct {
58092 +               unsigned chnum:4;
58093 +               unsigned bcnt:11;
58094 +               unsigned dpid:2;
58095 +
58096 +               unsigned pktsts:4;
58097 +#define DWC_GRXSTS_PKTSTS_IN                     0x2
58098 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP   0x3
58099 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
58100 +#define DWC_GRXSTS_PKTSTS_CH_HALTED              0x7
58101 +
58102 +               unsigned reserved21_31:11;
58103 +       } b;
58104 +} host_grxsts_data_t;
58105 +
58106 +/**
58107 + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ,
58108 + * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element
58109 + * then read out the bits using the <i>b</i>it elements.
58110 + */
58111 +typedef union fifosize_data {
58112 +       /** raw register data */
58113 +       uint32_t d32;
58114 +       /** register bits */
58115 +       struct {
58116 +               unsigned startaddr:16;
58117 +               unsigned depth:16;
58118 +       } b;
58119 +} fifosize_data_t;
58120 +
58121 +/**
58122 + * This union represents the bit fields in the Non-Periodic Transmit
58123 + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the
58124 + * <i>d32</i> element then read out the bits using the <i>b</i>it
58125 + * elements.
58126 + */
58127 +typedef union gnptxsts_data {
58128 +       /** raw register data */
58129 +       uint32_t d32;
58130 +       /** register bits */
58131 +       struct {
58132 +               unsigned nptxfspcavail:16;
58133 +               unsigned nptxqspcavail:8;
58134 +               /** Top of the Non-Periodic Transmit Request Queue
58135 +                *      - bit 24 - Terminate (Last entry for the selected
58136 +                *        channel/EP)
58137 +                *      - bits 26:25 - Token Type
58138 +                *        - 2'b00 - IN/OUT
58139 +                *        - 2'b01 - Zero Length OUT
58140 +                *        - 2'b10 - PING/Complete Split
58141 +                *        - 2'b11 - Channel Halt
58142 +                *      - bits 30:27 - Channel/EP Number
58143 +                */
58144 +               unsigned nptxqtop_terminate:1;
58145 +               unsigned nptxqtop_token:2;
58146 +               unsigned nptxqtop_chnep:4;
58147 +               unsigned reserved:1;
58148 +       } b;
58149 +} gnptxsts_data_t;
58150 +
58151 +/**
58152 + * This union represents the bit fields in the Transmit
58153 + * FIFO Status Register (DTXFSTS). Read the register into the
58154 + * <i>d32</i> element then read out the bits using the <i>b</i>it
58155 + * elements.
58156 + */
58157 +typedef union dtxfsts_data {
58158 +       /** raw register data */
58159 +       uint32_t d32;
58160 +       /** register bits */
58161 +       struct {
58162 +               unsigned txfspcavail:16;
58163 +               unsigned reserved:16;
58164 +       } b;
58165 +} dtxfsts_data_t;
58166 +
58167 +/**
58168 + * This union represents the bit fields in the I2C Control Register
58169 + * (I2CCTL). Read the register into the <i>d32</i> element then read out the
58170 + * bits using the <i>b</i>it elements.
58171 + */
58172 +typedef union gi2cctl_data {
58173 +       /** raw register data */
58174 +       uint32_t d32;
58175 +       /** register bits */
58176 +       struct {
58177 +               unsigned rwdata:8;
58178 +               unsigned regaddr:8;
58179 +               unsigned addr:7;
58180 +               unsigned i2cen:1;
58181 +               unsigned ack:1;
58182 +               unsigned i2csuspctl:1;
58183 +               unsigned i2cdevaddr:2;
58184 +               unsigned i2cdatse0:1;
58185 +               unsigned reserved:1;
58186 +               unsigned rw:1;
58187 +               unsigned bsydne:1;
58188 +       } b;
58189 +} gi2cctl_data_t;
58190 +
58191 +/**
58192 + * This union represents the bit fields in the PHY Vendor Control Register
58193 + * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the
58194 + * bits using the <i>b</i>it elements.
58195 + */
58196 +typedef union gpvndctl_data {
58197 +       /** raw register data */
58198 +       uint32_t d32;
58199 +       /** register bits */
58200 +       struct {
58201 +               unsigned regdata:8;
58202 +               unsigned vctrl:8;
58203 +               unsigned regaddr16_21:6;
58204 +               unsigned regwr:1;
58205 +               unsigned reserved23_24:2;
58206 +               unsigned newregreq:1;
58207 +               unsigned vstsbsy:1;
58208 +               unsigned vstsdone:1;
58209 +               unsigned reserved28_30:3;
58210 +               unsigned disulpidrvr:1;
58211 +       } b;
58212 +} gpvndctl_data_t;
58213 +
58214 +/**
58215 + * This union represents the bit fields in the General Purpose
58216 + * Input/Output Register (GGPIO).
58217 + * Read the register into the <i>d32</i> element then read out the
58218 + * bits using the <i>b</i>it elements.
58219 + */
58220 +typedef union ggpio_data {
58221 +       /** raw register data */
58222 +       uint32_t d32;
58223 +       /** register bits */
58224 +       struct {
58225 +               unsigned gpi:16;
58226 +               unsigned gpo:16;
58227 +       } b;
58228 +} ggpio_data_t;
58229 +
58230 +/**
58231 + * This union represents the bit fields in the User ID Register
58232 + * (GUID). Read the register into the <i>d32</i> element then read out the
58233 + * bits using the <i>b</i>it elements.
58234 + */
58235 +typedef union guid_data {
58236 +       /** raw register data */
58237 +       uint32_t d32;
58238 +       /** register bits */
58239 +       struct {
58240 +               unsigned rwdata:32;
58241 +       } b;
58242 +} guid_data_t;
58243 +
58244 +/**
58245 + * This union represents the bit fields in the Synopsys ID Register
58246 + * (GSNPSID). Read the register into the <i>d32</i> element then read out the
58247 + * bits using the <i>b</i>it elements.
58248 + */
58249 +typedef union gsnpsid_data {
58250 +       /** raw register data */
58251 +       uint32_t d32;
58252 +       /** register bits */
58253 +       struct {
58254 +               unsigned rwdata:32;
58255 +       } b;
58256 +} gsnpsid_data_t;
58257 +
58258 +/**
58259 + * This union represents the bit fields in the User HW Config1
58260 + * Register.  Read the register into the <i>d32</i> element then read
58261 + * out the bits using the <i>b</i>it elements.
58262 + */
58263 +typedef union hwcfg1_data {
58264 +       /** raw register data */
58265 +       uint32_t d32;
58266 +       /** register bits */
58267 +       struct {
58268 +               unsigned ep_dir0:2;
58269 +               unsigned ep_dir1:2;
58270 +               unsigned ep_dir2:2;
58271 +               unsigned ep_dir3:2;
58272 +               unsigned ep_dir4:2;
58273 +               unsigned ep_dir5:2;
58274 +               unsigned ep_dir6:2;
58275 +               unsigned ep_dir7:2;
58276 +               unsigned ep_dir8:2;
58277 +               unsigned ep_dir9:2;
58278 +               unsigned ep_dir10:2;
58279 +               unsigned ep_dir11:2;
58280 +               unsigned ep_dir12:2;
58281 +               unsigned ep_dir13:2;
58282 +               unsigned ep_dir14:2;
58283 +               unsigned ep_dir15:2;
58284 +       } b;
58285 +} hwcfg1_data_t;
58286 +
58287 +/**
58288 + * This union represents the bit fields in the User HW Config2
58289 + * Register.  Read the register into the <i>d32</i> element then read
58290 + * out the bits using the <i>b</i>it elements.
58291 + */
58292 +typedef union hwcfg2_data {
58293 +       /** raw register data */
58294 +       uint32_t d32;
58295 +       /** register bits */
58296 +       struct {
58297 +               /* GHWCFG2 */
58298 +               unsigned op_mode:3;
58299 +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
58300 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
58301 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
58302 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
58303 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
58304 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
58305 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
58306 +
58307 +               unsigned architecture:2;
58308 +               unsigned point2point:1;
58309 +               unsigned hs_phy_type:2;
58310 +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
58311 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
58312 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
58313 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
58314 +
58315 +               unsigned fs_phy_type:2;
58316 +               unsigned num_dev_ep:4;
58317 +               unsigned num_host_chan:4;
58318 +               unsigned perio_ep_supported:1;
58319 +               unsigned dynamic_fifo:1;
58320 +               unsigned multi_proc_int:1;
58321 +               unsigned reserved21:1;
58322 +               unsigned nonperio_tx_q_depth:2;
58323 +               unsigned host_perio_tx_q_depth:2;
58324 +               unsigned dev_token_q_depth:5;
58325 +               unsigned otg_enable_ic_usb:1;
58326 +       } b;
58327 +} hwcfg2_data_t;
58328 +
58329 +/**
58330 + * This union represents the bit fields in the User HW Config3
58331 + * Register.  Read the register into the <i>d32</i> element then read
58332 + * out the bits using the <i>b</i>it elements.
58333 + */
58334 +typedef union hwcfg3_data {
58335 +       /** raw register data */
58336 +       uint32_t d32;
58337 +       /** register bits */
58338 +       struct {
58339 +               /* GHWCFG3 */
58340 +               unsigned xfer_size_cntr_width:4;
58341 +               unsigned packet_size_cntr_width:3;
58342 +               unsigned otg_func:1;
58343 +               unsigned i2c:1;
58344 +               unsigned vendor_ctrl_if:1;
58345 +               unsigned optional_features:1;
58346 +               unsigned synch_reset_type:1;
58347 +               unsigned adp_supp:1;
58348 +               unsigned otg_enable_hsic:1;
58349 +               unsigned bc_support:1;
58350 +               unsigned otg_lpm_en:1;
58351 +               unsigned dfifo_depth:16;
58352 +       } b;
58353 +} hwcfg3_data_t;
58354 +
58355 +/**
58356 + * This union represents the bit fields in the User HW Config4
58357 + * Register.  Read the register into the <i>d32</i> element then read
58358 + * out the bits using the <i>b</i>it elements.
58359 + */
58360 +typedef union hwcfg4_data {
58361 +       /** raw register data */
58362 +       uint32_t d32;
58363 +       /** register bits */
58364 +       struct {
58365 +               unsigned num_dev_perio_in_ep:4;
58366 +               unsigned power_optimiz:1;
58367 +               unsigned min_ahb_freq:1;
58368 +               unsigned hiber:1;
58369 +               unsigned xhiber:1;
58370 +               unsigned reserved:6;
58371 +               unsigned utmi_phy_data_width:2;
58372 +               unsigned num_dev_mode_ctrl_ep:4;
58373 +               unsigned iddig_filt_en:1;
58374 +               unsigned vbus_valid_filt_en:1;
58375 +               unsigned a_valid_filt_en:1;
58376 +               unsigned b_valid_filt_en:1;
58377 +               unsigned session_end_filt_en:1;
58378 +               unsigned ded_fifo_en:1;
58379 +               unsigned num_in_eps:4;
58380 +               unsigned desc_dma:1;
58381 +               unsigned desc_dma_dyn:1;
58382 +       } b;
58383 +} hwcfg4_data_t;
58384 +
58385 +/**
58386 + * This union represents the bit fields of the Core LPM Configuration
58387 + * Register (GLPMCFG). Set the bits using bit fields then write
58388 + * the <i>d32</i> value to the register.
58389 + */
58390 +typedef union glpmctl_data {
58391 +       /** raw register data */
58392 +       uint32_t d32;
58393 +       /** register bits */
58394 +       struct {
58395 +               /** LPM-Capable (LPMCap) (Device and Host)
58396 +                * The application uses this bit to control
58397 +                * the DWC_otg core LPM capabilities.
58398 +                */
58399 +               unsigned lpm_cap_en:1;
58400 +               /** LPM response programmed by application (AppL1Res) (Device)
58401 +                * Handshake response to LPM token pre-programmed
58402 +                * by device application software.
58403 +                */
58404 +               unsigned appl_resp:1;
58405 +               /** Host Initiated Resume Duration (HIRD) (Device and Host)
58406 +                * In Host mode this field indicates the value of HIRD
58407 +                * to be sent in an LPM transaction.
58408 +                * In Device mode this field is updated with the
58409 +                * Received LPM Token HIRD bmAttribute
58410 +                * when an ACK/NYET/STALL response is sent
58411 +                * to an LPM transaction.
58412 +                */
58413 +               unsigned hird:4;
58414 +               /** RemoteWakeEnable (bRemoteWake) (Device and Host)
58415 +                * In Host mode this bit indicates the value of remote
58416 +                * wake up to be sent in wIndex field of LPM transaction.
58417 +                * In Device mode this field is updated with the
58418 +                * Received LPM Token bRemoteWake bmAttribute
58419 +                * when an ACK/NYET/STALL response is sent
58420 +                * to an LPM transaction.
58421 +                */
58422 +               unsigned rem_wkup_en:1;
58423 +               /** Enable utmi_sleep_n (EnblSlpM) (Device and Host)
58424 +                * The application uses this bit to control
58425 +                * the utmi_sleep_n assertion to the PHY when in L1 state.
58426 +                */
58427 +               unsigned en_utmi_sleep:1;
58428 +               /** HIRD Threshold (HIRD_Thres) (Device and Host)
58429 +                */
58430 +               unsigned hird_thres:5;
58431 +               /** LPM Response (CoreL1Res) (Device and Host)
58432 +                * In Host mode this bit contains handsake response to
58433 +                * LPM transaction.
58434 +                * In Device mode the response of the core to
58435 +                * LPM transaction received is reflected in these two bits.
58436 +                       - 0x0 : ERROR (No handshake response)
58437 +                       - 0x1 : STALL
58438 +                       - 0x2 : NYET
58439 +                       - 0x3 : ACK
58440 +                */
58441 +               unsigned lpm_resp:2;
58442 +               /** Port Sleep Status (SlpSts) (Device and Host)
58443 +                * This bit is set as long as a Sleep condition
58444 +                * is present on the USB bus.
58445 +                */
58446 +               unsigned prt_sleep_sts:1;
58447 +               /** Sleep State Resume OK (L1ResumeOK) (Device and Host)
58448 +                * Indicates that the application or host
58449 +                * can start resume from Sleep state.
58450 +                */
58451 +               unsigned sleep_state_resumeok:1;
58452 +               /** LPM channel Index (LPM_Chnl_Indx) (Host)
58453 +                * The channel number on which the LPM transaction
58454 +                * has to be applied while sending
58455 +                * an LPM transaction to the local device.
58456 +                */
58457 +               unsigned lpm_chan_index:4;
58458 +               /** LPM Retry Count (LPM_Retry_Cnt) (Host)
58459 +                * Number host retries that would be performed
58460 +                * if the device response was not valid response.
58461 +                */
58462 +               unsigned retry_count:3;
58463 +               /** Send LPM Transaction (SndLPM) (Host)
58464 +                * When set by application software,
58465 +                * an LPM transaction containing two tokens
58466 +                * is sent.
58467 +                */
58468 +               unsigned send_lpm:1;
58469 +               /** LPM Retry status (LPM_RetryCnt_Sts) (Host)
58470 +                * Number of LPM Host Retries still remaining
58471 +                * to be transmitted for the current LPM sequence
58472 +                */
58473 +               unsigned retry_count_sts:3;
58474 +               unsigned reserved28_29:2;
58475 +               /** In host mode once this bit is set, the host
58476 +                * configures to drive the HSIC Idle state on the bus.
58477 +                * It then waits for the  device to initiate the Connect sequence.
58478 +                * In device mode once this bit is set, the device waits for
58479 +                * the HSIC Idle line state on the bus. Upon receving the Idle
58480 +                * line state, it initiates the HSIC Connect sequence.
58481 +                */
58482 +               unsigned hsic_connect:1;
58483 +               /** This bit overrides and functionally inverts
58484 +                * the if_select_hsic input port signal.
58485 +                */
58486 +               unsigned inv_sel_hsic:1;
58487 +       } b;
58488 +} glpmcfg_data_t;
58489 +
58490 +/**
58491 + * This union represents the bit fields of the Core ADP Timer, Control and
58492 + * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write
58493 + * the <i>d32</i> value to the register.
58494 + */
58495 +typedef union adpctl_data {
58496 +       /** raw register data */
58497 +       uint32_t d32;
58498 +       /** register bits */
58499 +       struct {
58500 +               /** Probe Discharge (PRB_DSCHG)
58501 +                *  These bits set the times for TADP_DSCHG.
58502 +                *  These bits are defined as follows:
58503 +                *  2'b00 - 4 msec
58504 +                *  2'b01 - 8 msec
58505 +                *  2'b10 - 16 msec
58506 +                *  2'b11 - 32 msec
58507 +                */
58508 +               unsigned prb_dschg:2;
58509 +               /** Probe Delta (PRB_DELTA)
58510 +                *  These bits set the resolution for RTIM   value.
58511 +                *  The bits are defined in units of 32 kHz clock cycles as follows:
58512 +                *  2'b00  -  1 cycles
58513 +                *  2'b01  -  2 cycles
58514 +                *  2'b10 -  3 cycles
58515 +                *  2'b11 - 4 cycles
58516 +                *  For example if this value is chosen to 2'b01, it means that RTIM
58517 +                *  increments for every 3(three) 32Khz clock cycles.
58518 +                */
58519 +               unsigned prb_delta:2;
58520 +               /** Probe Period (PRB_PER)
58521 +                *  These bits sets the TADP_PRD as shown in Figure 4 as follows:
58522 +                *  2'b00  -  0.625 to 0.925 sec (typical 0.775 sec)
58523 +                *  2'b01  -  1.25 to 1.85 sec (typical 1.55 sec)
58524 +                *  2'b10  -  1.9 to 2.6 sec (typical 2.275 sec)
58525 +                *  2'b11  -  Reserved
58526 +                */
58527 +               unsigned prb_per:2;
58528 +               /** These bits capture the latest time it took for VBUS to ramp from
58529 +                *  VADP_SINK to VADP_PRB.
58530 +                *  0x000  -  1 cycles
58531 +                *  0x001  -  2 cycles
58532 +                *  0x002  -  3 cycles
58533 +                *  etc
58534 +                *  0x7FF  -  2048 cycles
58535 +                *  A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec.
58536 +               */
58537 +               unsigned rtim:11;
58538 +               /** Enable Probe (EnaPrb)
58539 +                *  When programmed to 1'b1, the core performs a probe operation.
58540 +                *  This bit is valid only if OTG_Ver = 1'b1.
58541 +                */
58542 +               unsigned enaprb:1;
58543 +               /** Enable Sense (EnaSns)
58544 +                *  When programmed to 1'b1, the core performs a Sense operation.
58545 +                *  This bit is valid only if OTG_Ver = 1'b1.
58546 +                */
58547 +               unsigned enasns:1;
58548 +               /** ADP Reset (ADPRes)
58549 +                *  When set, ADP controller is reset.
58550 +                *  This bit is valid only if OTG_Ver = 1'b1.
58551 +                */
58552 +               unsigned adpres:1;
58553 +               /** ADP Enable (ADPEn)
58554 +                *  When set, the core performs either ADP probing or sensing
58555 +                *  based on EnaPrb or EnaSns.
58556 +                *  This bit is valid only if OTG_Ver = 1'b1.
58557 +                */
58558 +               unsigned adpen:1;
58559 +               /** ADP Probe Interrupt (ADP_PRB_INT)
58560 +                *  When this bit is set, it means that the VBUS
58561 +                *  voltage is greater than VADP_PRB or VADP_PRB is reached.
58562 +                *  This bit is valid only if OTG_Ver = 1'b1.
58563 +                */
58564 +               unsigned adp_prb_int:1;
58565 +               /**
58566 +                *  ADP Sense Interrupt (ADP_SNS_INT)
58567 +                *  When this bit is set, it means that the VBUS voltage is greater than
58568 +                *  VADP_SNS value or VADP_SNS is reached.
58569 +                *  This bit is valid only if OTG_Ver = 1'b1.
58570 +                */
58571 +               unsigned adp_sns_int:1;
58572 +               /** ADP Tomeout Interrupt (ADP_TMOUT_INT)
58573 +                *  This bit is relevant only for an ADP probe.
58574 +                *  When this bit is set, it means that the ramp time has
58575 +                *  completed ie ADPCTL.RTIM has reached its terminal value
58576 +                *  of 0x7FF.  This is a debug feature that allows software
58577 +                *  to read the ramp time after each cycle.
58578 +                *  This bit is valid only if OTG_Ver = 1'b1.
58579 +                */
58580 +               unsigned adp_tmout_int:1;
58581 +               /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK)
58582 +                *  When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
58583 +                *  This bit is valid only if OTG_Ver = 1'b1.
58584 +                */
58585 +               unsigned adp_prb_int_msk:1;
58586 +               /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK)
58587 +                *  When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
58588 +                *  This bit is valid only if OTG_Ver = 1'b1.
58589 +                */
58590 +               unsigned adp_sns_int_msk:1;
58591 +               /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK)
58592 +                *  When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
58593 +                *  This bit is valid only if OTG_Ver = 1'b1.
58594 +                */
58595 +               unsigned adp_tmout_int_msk:1;
58596 +               /** Access Request
58597 +                * 2'b00 - Read/Write Valid (updated by the core)
58598 +                * 2'b01 - Read
58599 +                * 2'b00 - Write
58600 +                * 2'b00 - Reserved
58601 +                */
58602 +               unsigned ar:2;
58603 +                /** Reserved */
58604 +               unsigned reserved29_31:3;
58605 +       } b;
58606 +} adpctl_data_t;
58607 +
58608 +////////////////////////////////////////////
58609 +// Device Registers
58610 +/**
58611 + * Device Global Registers. <i>Offsets 800h-BFFh</i>
58612 + *
58613 + * The following structures define the size and relative field offsets
58614 + * for the Device Mode Registers.
58615 + *
58616 + * <i>These registers are visible only in Device mode and must not be
58617 + * accessed in Host mode, as the results are unknown.</i>
58618 + */
58619 +typedef struct dwc_otg_dev_global_regs {
58620 +       /** Device Configuration Register. <i>Offset 800h</i> */
58621 +       volatile uint32_t dcfg;
58622 +       /** Device Control Register. <i>Offset: 804h</i> */
58623 +       volatile uint32_t dctl;
58624 +       /** Device Status Register (Read Only). <i>Offset: 808h</i> */
58625 +       volatile uint32_t dsts;
58626 +       /** Reserved. <i>Offset: 80Ch</i> */
58627 +       uint32_t unused;
58628 +       /** Device IN Endpoint Common Interrupt Mask
58629 +        * Register. <i>Offset: 810h</i> */
58630 +       volatile uint32_t diepmsk;
58631 +       /** Device OUT Endpoint Common Interrupt Mask
58632 +        * Register. <i>Offset: 814h</i> */
58633 +       volatile uint32_t doepmsk;
58634 +       /** Device All Endpoints Interrupt Register.  <i>Offset: 818h</i> */
58635 +       volatile uint32_t daint;
58636 +       /** Device All Endpoints Interrupt Mask Register.  <i>Offset:
58637 +        * 81Ch</i> */
58638 +       volatile uint32_t daintmsk;
58639 +       /** Device IN Token Queue Read Register-1 (Read Only).
58640 +        * <i>Offset: 820h</i> */
58641 +       volatile uint32_t dtknqr1;
58642 +       /** Device IN Token Queue Read Register-2 (Read Only).
58643 +        * <i>Offset: 824h</i> */
58644 +       volatile uint32_t dtknqr2;
58645 +       /** Device VBUS  discharge Register.  <i>Offset: 828h</i> */
58646 +       volatile uint32_t dvbusdis;
58647 +       /** Device VBUS Pulse Register.  <i>Offset: 82Ch</i> */
58648 +       volatile uint32_t dvbuspulse;
58649 +       /** Device IN Token Queue Read Register-3 (Read Only). /
58650 +        *      Device Thresholding control register (Read/Write)
58651 +        * <i>Offset: 830h</i> */
58652 +       volatile uint32_t dtknqr3_dthrctl;
58653 +       /** Device IN Token Queue Read Register-4 (Read Only). /
58654 +        *      Device IN EPs empty Inr. Mask Register (Read/Write)
58655 +        * <i>Offset: 834h</i> */
58656 +       volatile uint32_t dtknqr4_fifoemptymsk;
58657 +       /** Device Each Endpoint Interrupt Register (Read Only). /
58658 +        * <i>Offset: 838h</i> */
58659 +       volatile uint32_t deachint;
58660 +       /** Device Each Endpoint Interrupt mask Register (Read/Write). /
58661 +        * <i>Offset: 83Ch</i> */
58662 +       volatile uint32_t deachintmsk;
58663 +       /** Device Each In Endpoint Interrupt mask Register (Read/Write). /
58664 +        * <i>Offset: 840h</i> */
58665 +       volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
58666 +       /** Device Each Out Endpoint Interrupt mask Register (Read/Write). /
58667 +        * <i>Offset: 880h</i> */
58668 +       volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
58669 +} dwc_otg_device_global_regs_t;
58670 +
58671 +/**
58672 + * This union represents the bit fields in the Device Configuration
58673 + * Register.  Read the register into the <i>d32</i> member then
58674 + * set/clear the bits using the <i>b</i>it elements.  Write the
58675 + * <i>d32</i> member to the dcfg register.
58676 + */
58677 +typedef union dcfg_data {
58678 +       /** raw register data */
58679 +       uint32_t d32;
58680 +       /** register bits */
58681 +       struct {
58682 +               /** Device Speed */
58683 +               unsigned devspd:2;
58684 +               /** Non Zero Length Status OUT Handshake */
58685 +               unsigned nzstsouthshk:1;
58686 +#define DWC_DCFG_SEND_STALL 1
58687 +
58688 +               unsigned ena32khzs:1;
58689 +               /** Device Addresses */
58690 +               unsigned devaddr:7;
58691 +               /** Periodic Frame Interval */
58692 +               unsigned perfrint:2;
58693 +#define DWC_DCFG_FRAME_INTERVAL_80 0
58694 +#define DWC_DCFG_FRAME_INTERVAL_85 1
58695 +#define DWC_DCFG_FRAME_INTERVAL_90 2
58696 +#define DWC_DCFG_FRAME_INTERVAL_95 3
58697 +
58698 +               /** Enable Device OUT NAK for bulk in DDMA mode */
58699 +               unsigned endevoutnak:1;
58700 +
58701 +               unsigned reserved14_17:4;
58702 +               /** In Endpoint Mis-match count */
58703 +               unsigned epmscnt:5;
58704 +               /** Enable Descriptor DMA in Device mode */
58705 +               unsigned descdma:1;
58706 +               unsigned perschintvl:2;
58707 +               unsigned resvalid:6;
58708 +       } b;
58709 +} dcfg_data_t;
58710 +
58711 +/**
58712 + * This union represents the bit fields in the Device Control
58713 + * Register.  Read the register into the <i>d32</i> member then
58714 + * set/clear the bits using the <i>b</i>it elements.
58715 + */
58716 +typedef union dctl_data {
58717 +       /** raw register data */
58718 +       uint32_t d32;
58719 +       /** register bits */
58720 +       struct {
58721 +               /** Remote Wakeup */
58722 +               unsigned rmtwkupsig:1;
58723 +               /** Soft Disconnect */
58724 +               unsigned sftdiscon:1;
58725 +               /** Global Non-Periodic IN NAK Status */
58726 +               unsigned gnpinnaksts:1;
58727 +               /** Global OUT NAK Status */
58728 +               unsigned goutnaksts:1;
58729 +               /** Test Control */
58730 +               unsigned tstctl:3;
58731 +               /** Set Global Non-Periodic IN NAK */
58732 +               unsigned sgnpinnak:1;
58733 +               /** Clear Global Non-Periodic IN NAK */
58734 +               unsigned cgnpinnak:1;
58735 +               /** Set Global OUT NAK */
58736 +               unsigned sgoutnak:1;
58737 +               /** Clear Global OUT NAK */
58738 +               unsigned cgoutnak:1;
58739 +               /** Power-On Programming Done */
58740 +               unsigned pwronprgdone:1;
58741 +               /** Reserved */
58742 +               unsigned reserved:1;
58743 +               /** Global Multi Count */
58744 +               unsigned gmc:2;
58745 +               /** Ignore Frame Number for ISOC EPs */
58746 +               unsigned ifrmnum:1;
58747 +               /** NAK on Babble */
58748 +               unsigned nakonbble:1;
58749 +               /** Enable Continue on BNA */
58750 +               unsigned encontonbna:1;
58751 +
58752 +               unsigned reserved18_31:14;
58753 +       } b;
58754 +} dctl_data_t;
58755 +
58756 +/**
58757 + * This union represents the bit fields in the Device Status
58758 + * Register.  Read the register into the <i>d32</i> member then
58759 + * set/clear the bits using the <i>b</i>it elements.
58760 + */
58761 +typedef union dsts_data {
58762 +       /** raw register data */
58763 +       uint32_t d32;
58764 +       /** register bits */
58765 +       struct {
58766 +               /** Suspend Status */
58767 +               unsigned suspsts:1;
58768 +               /** Enumerated Speed */
58769 +               unsigned enumspd:2;
58770 +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
58771 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
58772 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ              2
58773 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ             3
58774 +               /** Erratic Error */
58775 +               unsigned errticerr:1;
58776 +               unsigned reserved4_7:4;
58777 +               /** Frame or Microframe Number of the received SOF */
58778 +               unsigned soffn:14;
58779 +               unsigned reserved22_31:10;
58780 +       } b;
58781 +} dsts_data_t;
58782 +
58783 +/**
58784 + * This union represents the bit fields in the Device IN EP Interrupt
58785 + * Register and the Device IN EP Common Mask Register.
58786 + *
58787 + * - Read the register into the <i>d32</i> member then set/clear the
58788 + *      bits using the <i>b</i>it elements.
58789 + */
58790 +typedef union diepint_data {
58791 +       /** raw register data */
58792 +       uint32_t d32;
58793 +       /** register bits */
58794 +       struct {
58795 +               /** Transfer complete mask */
58796 +               unsigned xfercompl:1;
58797 +               /** Endpoint disable mask */
58798 +               unsigned epdisabled:1;
58799 +               /** AHB Error mask */
58800 +               unsigned ahberr:1;
58801 +               /** TimeOUT Handshake mask (non-ISOC EPs) */
58802 +               unsigned timeout:1;
58803 +               /** IN Token received with TxF Empty mask */
58804 +               unsigned intktxfemp:1;
58805 +               /** IN Token Received with EP mismatch mask */
58806 +               unsigned intknepmis:1;
58807 +               /** IN Endpoint NAK Effective mask */
58808 +               unsigned inepnakeff:1;
58809 +               /** Reserved */
58810 +               unsigned emptyintr:1;
58811 +
58812 +               unsigned txfifoundrn:1;
58813 +
58814 +               /** BNA Interrupt mask */
58815 +               unsigned bna:1;
58816 +
58817 +               unsigned reserved10_12:3;
58818 +               /** BNA Interrupt mask */
58819 +               unsigned nak:1;
58820 +
58821 +               unsigned reserved14_31:18;
58822 +       } b;
58823 +} diepint_data_t;
58824 +
58825 +/**
58826 + * This union represents the bit fields in the Device IN EP
58827 + * Common/Dedicated Interrupt Mask Register.
58828 + */
58829 +typedef union diepint_data diepmsk_data_t;
58830 +
58831 +/**
58832 + * This union represents the bit fields in the Device OUT EP Interrupt
58833 + * Registerand Device OUT EP Common Interrupt Mask Register.
58834 + *
58835 + * - Read the register into the <i>d32</i> member then set/clear the
58836 + *      bits using the <i>b</i>it elements.
58837 + */
58838 +typedef union doepint_data {
58839 +       /** raw register data */
58840 +       uint32_t d32;
58841 +       /** register bits */
58842 +       struct {
58843 +               /** Transfer complete */
58844 +               unsigned xfercompl:1;
58845 +               /** Endpoint disable  */
58846 +               unsigned epdisabled:1;
58847 +               /** AHB Error */
58848 +               unsigned ahberr:1;
58849 +               /** Setup Phase Done (contorl EPs) */
58850 +               unsigned setup:1;
58851 +               /** OUT Token Received when Endpoint Disabled */
58852 +               unsigned outtknepdis:1;
58853 +
58854 +               unsigned stsphsercvd:1;
58855 +               /** Back-to-Back SETUP Packets Received */
58856 +               unsigned back2backsetup:1;
58857 +
58858 +               unsigned reserved7:1;
58859 +               /** OUT packet Error */
58860 +               unsigned outpkterr:1;
58861 +               /** BNA Interrupt */
58862 +               unsigned bna:1;
58863 +
58864 +               unsigned reserved10:1;
58865 +               /** Packet Drop Status */
58866 +               unsigned pktdrpsts:1;
58867 +               /** Babble Interrupt */
58868 +               unsigned babble:1;
58869 +               /** NAK Interrupt */
58870 +               unsigned nak:1;
58871 +               /** NYET Interrupt */
58872 +               unsigned nyet:1;
58873 +               /** Bit indicating setup packet received */
58874 +               unsigned sr:1;
58875 +
58876 +               unsigned reserved16_31:16;
58877 +       } b;
58878 +} doepint_data_t;
58879 +
58880 +/**
58881 + * This union represents the bit fields in the Device OUT EP
58882 + * Common/Dedicated Interrupt Mask Register.
58883 + */
58884 +typedef union doepint_data doepmsk_data_t;
58885 +
58886 +/**
58887 + * This union represents the bit fields in the Device All EP Interrupt
58888 + * and Mask Registers.
58889 + * - Read the register into the <i>d32</i> member then set/clear the
58890 + *      bits using the <i>b</i>it elements.
58891 + */
58892 +typedef union daint_data {
58893 +       /** raw register data */
58894 +       uint32_t d32;
58895 +       /** register bits */
58896 +       struct {
58897 +               /** IN Endpoint bits */
58898 +               unsigned in:16;
58899 +               /** OUT Endpoint bits */
58900 +               unsigned out:16;
58901 +       } ep;
58902 +       struct {
58903 +               /** IN Endpoint bits */
58904 +               unsigned inep0:1;
58905 +               unsigned inep1:1;
58906 +               unsigned inep2:1;
58907 +               unsigned inep3:1;
58908 +               unsigned inep4:1;
58909 +               unsigned inep5:1;
58910 +               unsigned inep6:1;
58911 +               unsigned inep7:1;
58912 +               unsigned inep8:1;
58913 +               unsigned inep9:1;
58914 +               unsigned inep10:1;
58915 +               unsigned inep11:1;
58916 +               unsigned inep12:1;
58917 +               unsigned inep13:1;
58918 +               unsigned inep14:1;
58919 +               unsigned inep15:1;
58920 +               /** OUT Endpoint bits */
58921 +               unsigned outep0:1;
58922 +               unsigned outep1:1;
58923 +               unsigned outep2:1;
58924 +               unsigned outep3:1;
58925 +               unsigned outep4:1;
58926 +               unsigned outep5:1;
58927 +               unsigned outep6:1;
58928 +               unsigned outep7:1;
58929 +               unsigned outep8:1;
58930 +               unsigned outep9:1;
58931 +               unsigned outep10:1;
58932 +               unsigned outep11:1;
58933 +               unsigned outep12:1;
58934 +               unsigned outep13:1;
58935 +               unsigned outep14:1;
58936 +               unsigned outep15:1;
58937 +       } b;
58938 +} daint_data_t;
58939 +
58940 +/**
58941 + * This union represents the bit fields in the Device IN Token Queue
58942 + * Read Registers.
58943 + * - Read the register into the <i>d32</i> member.
58944 + * - READ-ONLY Register
58945 + */
58946 +typedef union dtknq1_data {
58947 +       /** raw register data */
58948 +       uint32_t d32;
58949 +       /** register bits */
58950 +       struct {
58951 +               /** In Token Queue Write Pointer */
58952 +               unsigned intknwptr:5;
58953 +               /** Reserved */
58954 +               unsigned reserved05_06:2;
58955 +               /** write pointer has wrapped. */
58956 +               unsigned wrap_bit:1;
58957 +               /** EP Numbers of IN Tokens 0 ... 4 */
58958 +               unsigned epnums0_5:24;
58959 +       } b;
58960 +} dtknq1_data_t;
58961 +
58962 +/**
58963 + * This union represents Threshold control Register
58964 + * - Read and write the register into the <i>d32</i> member.
58965 + * - READ-WRITABLE Register
58966 + */
58967 +typedef union dthrctl_data {
58968 +       /** raw register data */
58969 +       uint32_t d32;
58970 +       /** register bits */
58971 +       struct {
58972 +               /** non ISO Tx Thr. Enable */
58973 +               unsigned non_iso_thr_en:1;
58974 +               /** ISO Tx Thr. Enable */
58975 +               unsigned iso_thr_en:1;
58976 +               /** Tx Thr. Length */
58977 +               unsigned tx_thr_len:9;
58978 +               /** AHB Threshold ratio */
58979 +               unsigned ahb_thr_ratio:2;
58980 +               /** Reserved */
58981 +               unsigned reserved13_15:3;
58982 +               /** Rx Thr. Enable */
58983 +               unsigned rx_thr_en:1;
58984 +               /** Rx Thr. Length */
58985 +               unsigned rx_thr_len:9;
58986 +               unsigned reserved26:1;
58987 +               /** Arbiter Parking Enable*/
58988 +               unsigned arbprken:1;
58989 +               /** Reserved */
58990 +               unsigned reserved28_31:4;
58991 +       } b;
58992 +} dthrctl_data_t;
58993 +
58994 +/**
58995 + * Device Logical IN Endpoint-Specific Registers. <i>Offsets
58996 + * 900h-AFCh</i>
58997 + *
58998 + * There will be one set of endpoint registers per logical endpoint
58999 + * implemented.
59000 + *
59001 + * <i>These registers are visible only in Device mode and must not be
59002 + * accessed in Host mode, as the results are unknown.</i>
59003 + */
59004 +typedef struct dwc_otg_dev_in_ep_regs {
59005 +       /** Device IN Endpoint Control Register. <i>Offset:900h +
59006 +        * (ep_num * 20h) + 00h</i> */
59007 +       volatile uint32_t diepctl;
59008 +       /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */
59009 +       uint32_t reserved04;
59010 +       /** Device IN Endpoint Interrupt Register. <i>Offset:900h +
59011 +        * (ep_num * 20h) + 08h</i> */
59012 +       volatile uint32_t diepint;
59013 +       /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */
59014 +       uint32_t reserved0C;
59015 +       /** Device IN Endpoint Transfer Size
59016 +        * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */
59017 +       volatile uint32_t dieptsiz;
59018 +       /** Device IN Endpoint DMA Address Register. <i>Offset:900h +
59019 +        * (ep_num * 20h) + 14h</i> */
59020 +       volatile uint32_t diepdma;
59021 +       /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h +
59022 +        * (ep_num * 20h) + 18h</i> */
59023 +       volatile uint32_t dtxfsts;
59024 +       /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h +
59025 +        * (ep_num * 20h) + 1Ch</i> */
59026 +       volatile uint32_t diepdmab;
59027 +} dwc_otg_dev_in_ep_regs_t;
59028 +
59029 +/**
59030 + * Device Logical OUT Endpoint-Specific Registers. <i>Offsets:
59031 + * B00h-CFCh</i>
59032 + *
59033 + * There will be one set of endpoint registers per logical endpoint
59034 + * implemented.
59035 + *
59036 + * <i>These registers are visible only in Device mode and must not be
59037 + * accessed in Host mode, as the results are unknown.</i>
59038 + */
59039 +typedef struct dwc_otg_dev_out_ep_regs {
59040 +       /** Device OUT Endpoint Control Register. <i>Offset:B00h +
59041 +        * (ep_num * 20h) + 00h</i> */
59042 +       volatile uint32_t doepctl;
59043 +       /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */
59044 +       uint32_t reserved04;
59045 +       /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h +
59046 +        * (ep_num * 20h) + 08h</i> */
59047 +       volatile uint32_t doepint;
59048 +       /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */
59049 +       uint32_t reserved0C;
59050 +       /** Device OUT Endpoint Transfer Size Register. <i>Offset:
59051 +        * B00h + (ep_num * 20h) + 10h</i> */
59052 +       volatile uint32_t doeptsiz;
59053 +       /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h
59054 +        * + (ep_num * 20h) + 14h</i> */
59055 +       volatile uint32_t doepdma;
59056 +       /** Reserved. <i>Offset:B00h +   * (ep_num * 20h) + 18h</i> */
59057 +       uint32_t unused;
59058 +       /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h
59059 +        * + (ep_num * 20h) + 1Ch</i> */
59060 +       uint32_t doepdmab;
59061 +} dwc_otg_dev_out_ep_regs_t;
59062 +
59063 +/**
59064 + * This union represents the bit fields in the Device EP Control
59065 + * Register.  Read the register into the <i>d32</i> member then
59066 + * set/clear the bits using the <i>b</i>it elements.
59067 + */
59068 +typedef union depctl_data {
59069 +       /** raw register data */
59070 +       uint32_t d32;
59071 +       /** register bits */
59072 +       struct {
59073 +               /** Maximum Packet Size
59074 +                * IN/OUT EPn
59075 +                * IN/OUT EP0 - 2 bits
59076 +                *       2'b00: 64 Bytes
59077 +                *       2'b01: 32
59078 +                *       2'b10: 16
59079 +                *       2'b11: 8 */
59080 +               unsigned mps:11;
59081 +#define DWC_DEP0CTL_MPS_64      0
59082 +#define DWC_DEP0CTL_MPS_32      1
59083 +#define DWC_DEP0CTL_MPS_16      2
59084 +#define DWC_DEP0CTL_MPS_8       3
59085 +
59086 +               /** Next Endpoint
59087 +                * IN EPn/IN EP0
59088 +                * OUT EPn/OUT EP0 - reserved */
59089 +               unsigned nextep:4;
59090 +
59091 +               /** USB Active Endpoint */
59092 +               unsigned usbactep:1;
59093 +
59094 +               /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
59095 +                * This field contains the PID of the packet going to
59096 +                * be received or transmitted on this endpoint. The
59097 +                * application should program the PID of the first
59098 +                * packet going to be received or transmitted on this
59099 +                * endpoint , after the endpoint is
59100 +                * activated. Application use the SetD1PID and
59101 +                * SetD0PID fields of this register to program either
59102 +                * D0 or D1 PID.
59103 +                *
59104 +                * The encoding for this field is
59105 +                *       - 0: D0
59106 +                *       - 1: D1
59107 +                */
59108 +               unsigned dpid:1;
59109 +
59110 +               /** NAK Status */
59111 +               unsigned naksts:1;
59112 +
59113 +               /** Endpoint Type
59114 +                *      2'b00: Control
59115 +                *      2'b01: Isochronous
59116 +                *      2'b10: Bulk
59117 +                *      2'b11: Interrupt */
59118 +               unsigned eptype:2;
59119 +
59120 +               /** Snoop Mode
59121 +                * OUT EPn/OUT EP0
59122 +                * IN EPn/IN EP0 - reserved */
59123 +               unsigned snp:1;
59124 +
59125 +               /** Stall Handshake */
59126 +               unsigned stall:1;
59127 +
59128 +               /** Tx Fifo Number
59129 +                * IN EPn/IN EP0
59130 +                * OUT EPn/OUT EP0 - reserved */
59131 +               unsigned txfnum:4;
59132 +
59133 +               /** Clear NAK */
59134 +               unsigned cnak:1;
59135 +               /** Set NAK */
59136 +               unsigned snak:1;
59137 +               /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
59138 +                * Writing to this field sets the Endpoint DPID (DPID)
59139 +                * field in this register to DATA0. Set Even
59140 +                * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
59141 +                * Writing to this field sets the Even/Odd
59142 +                * (micro)frame (EO_FrNum) field to even (micro)
59143 +                * frame.
59144 +                */
59145 +               unsigned setd0pid:1;
59146 +               /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
59147 +                * Writing to this field sets the Endpoint DPID (DPID)
59148 +                * field in this register to DATA1 Set Odd
59149 +                * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
59150 +                * Writing to this field sets the Even/Odd
59151 +                * (micro)frame (EO_FrNum) field to odd (micro) frame.
59152 +                */
59153 +               unsigned setd1pid:1;
59154 +
59155 +               /** Endpoint Disable */
59156 +               unsigned epdis:1;
59157 +               /** Endpoint Enable */
59158 +               unsigned epena:1;
59159 +       } b;
59160 +} depctl_data_t;
59161 +
59162 +/**
59163 + * This union represents the bit fields in the Device EP Transfer
59164 + * Size Register.  Read the register into the <i>d32</i> member then
59165 + * set/clear the bits using the <i>b</i>it elements.
59166 + */
59167 +typedef union deptsiz_data {
59168 +               /** raw register data */
59169 +       uint32_t d32;
59170 +               /** register bits */
59171 +       struct {
59172 +               /** Transfer size */
59173 +               unsigned xfersize:19;
59174 +/** Max packet count for EP (pow(2,10)-1) */
59175 +#define MAX_PKT_CNT 1023
59176 +               /** Packet Count */
59177 +               unsigned pktcnt:10;
59178 +               /** Multi Count - Periodic IN endpoints */
59179 +               unsigned mc:2;
59180 +               unsigned reserved:1;
59181 +       } b;
59182 +} deptsiz_data_t;
59183 +
59184 +/**
59185 + * This union represents the bit fields in the Device EP 0 Transfer
59186 + * Size Register.  Read the register into the <i>d32</i> member then
59187 + * set/clear the bits using the <i>b</i>it elements.
59188 + */
59189 +typedef union deptsiz0_data {
59190 +               /** raw register data */
59191 +       uint32_t d32;
59192 +               /** register bits */
59193 +       struct {
59194 +               /** Transfer size */
59195 +               unsigned xfersize:7;
59196 +                               /** Reserved */
59197 +               unsigned reserved7_18:12;
59198 +               /** Packet Count */
59199 +               unsigned pktcnt:2;
59200 +                               /** Reserved */
59201 +               unsigned reserved21_28:8;
59202 +                               /**Setup Packet Count (DOEPTSIZ0 Only) */
59203 +               unsigned supcnt:2;
59204 +               unsigned reserved31;
59205 +       } b;
59206 +} deptsiz0_data_t;
59207 +
59208 +/////////////////////////////////////////////////
59209 +// DMA Descriptor Specific Structures
59210 +//
59211 +
59212 +/** Buffer status definitions */
59213 +
59214 +#define BS_HOST_READY  0x0
59215 +#define BS_DMA_BUSY            0x1
59216 +#define BS_DMA_DONE            0x2
59217 +#define BS_HOST_BUSY   0x3
59218 +
59219 +/** Receive/Transmit status definitions */
59220 +
59221 +#define RTS_SUCCESS            0x0
59222 +#define RTS_BUFFLUSH   0x1
59223 +#define RTS_RESERVED   0x2
59224 +#define RTS_BUFERR             0x3
59225 +
59226 +/**
59227 + * This union represents the bit fields in the DMA Descriptor
59228 + * status quadlet. Read the quadlet into the <i>d32</i> member then
59229 + * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and
59230 + * <i>b_iso_in</i> elements.
59231 + */
59232 +typedef union dev_dma_desc_sts {
59233 +               /** raw register data */
59234 +       uint32_t d32;
59235 +               /** quadlet bits */
59236 +       struct {
59237 +               /** Received number of bytes */
59238 +               unsigned bytes:16;
59239 +               /** NAK bit - only for OUT EPs */
59240 +               unsigned nak:1;
59241 +               unsigned reserved17_22:6;
59242 +               /** Multiple Transfer - only for OUT EPs */
59243 +               unsigned mtrf:1;
59244 +               /** Setup Packet received - only for OUT EPs */
59245 +               unsigned sr:1;
59246 +               /** Interrupt On Complete */
59247 +               unsigned ioc:1;
59248 +               /** Short Packet */
59249 +               unsigned sp:1;
59250 +               /** Last */
59251 +               unsigned l:1;
59252 +               /** Receive Status */
59253 +               unsigned sts:2;
59254 +               /** Buffer Status */
59255 +               unsigned bs:2;
59256 +       } b;
59257 +
59258 +//#ifdef DWC_EN_ISOC
59259 +               /** iso out quadlet bits */
59260 +       struct {
59261 +               /** Received number of bytes */
59262 +               unsigned rxbytes:11;
59263 +
59264 +               unsigned reserved11:1;
59265 +               /** Frame Number */
59266 +               unsigned framenum:11;
59267 +               /** Received ISO Data PID */
59268 +               unsigned pid:2;
59269 +               /** Interrupt On Complete */
59270 +               unsigned ioc:1;
59271 +               /** Short Packet */
59272 +               unsigned sp:1;
59273 +               /** Last */
59274 +               unsigned l:1;
59275 +               /** Receive Status */
59276 +               unsigned rxsts:2;
59277 +               /** Buffer Status */
59278 +               unsigned bs:2;
59279 +       } b_iso_out;
59280 +
59281 +               /** iso in quadlet bits */
59282 +       struct {
59283 +               /** Transmited number of bytes */
59284 +               unsigned txbytes:12;
59285 +               /** Frame Number */
59286 +               unsigned framenum:11;
59287 +               /** Transmited ISO Data PID */
59288 +               unsigned pid:2;
59289 +               /** Interrupt On Complete */
59290 +               unsigned ioc:1;
59291 +               /** Short Packet */
59292 +               unsigned sp:1;
59293 +               /** Last */
59294 +               unsigned l:1;
59295 +               /** Transmit Status */
59296 +               unsigned txsts:2;
59297 +               /** Buffer Status */
59298 +               unsigned bs:2;
59299 +       } b_iso_in;
59300 +//#endif                                /* DWC_EN_ISOC */
59301 +} dev_dma_desc_sts_t;
59302 +
59303 +/**
59304 + * DMA Descriptor structure
59305 + *
59306 + * DMA Descriptor structure contains two quadlets:
59307 + * Status quadlet and Data buffer pointer.
59308 + */
59309 +typedef struct dwc_otg_dev_dma_desc {
59310 +       /** DMA Descriptor status quadlet */
59311 +       dev_dma_desc_sts_t status;
59312 +       /** DMA Descriptor data buffer pointer */
59313 +       uint32_t buf;
59314 +} dwc_otg_dev_dma_desc_t;
59315 +
59316 +/**
59317 + * The dwc_otg_dev_if structure contains information needed to manage
59318 + * the DWC_otg controller acting in device mode. It represents the
59319 + * programming view of the device-specific aspects of the controller.
59320 + */
59321 +typedef struct dwc_otg_dev_if {
59322 +       /** Pointer to device Global registers.
59323 +        * Device Global Registers starting at offset 800h
59324 +        */
59325 +       dwc_otg_device_global_regs_t *dev_global_regs;
59326 +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800
59327 +
59328 +       /**
59329 +        * Device Logical IN Endpoint-Specific Registers 900h-AFCh
59330 +        */
59331 +       dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
59332 +#define DWC_DEV_IN_EP_REG_OFFSET 0x900
59333 +#define DWC_EP_REG_OFFSET 0x20
59334 +
59335 +       /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */
59336 +       dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
59337 +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
59338 +
59339 +       /* Device configuration information */
59340 +       uint8_t speed;                           /**< Device Speed      0: Unknown, 1: LS, 2:FS, 3: HS */
59341 +       uint8_t num_in_eps;              /**< Number # of Tx EP range: 0-15 exept ep0 */
59342 +       uint8_t num_out_eps;             /**< Number # of Rx EP range: 0-15 exept ep 0*/
59343 +
59344 +       /** Size of periodic FIFOs (Bytes) */
59345 +       uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
59346 +
59347 +       /** Size of Tx FIFOs (Bytes) */
59348 +       uint16_t tx_fifo_size[MAX_TX_FIFOS];
59349 +
59350 +       /** Thresholding enable flags and length varaiables **/
59351 +       uint16_t rx_thr_en;
59352 +       uint16_t iso_tx_thr_en;
59353 +       uint16_t non_iso_tx_thr_en;
59354 +
59355 +       uint16_t rx_thr_length;
59356 +       uint16_t tx_thr_length;
59357 +
59358 +       /**
59359 +        * Pointers to the DMA Descriptors for EP0 Control
59360 +        * transfers (virtual and physical)
59361 +        */
59362 +
59363 +       /** 2 descriptors for SETUP packets */
59364 +       dwc_dma_t dma_setup_desc_addr[2];
59365 +       dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
59366 +
59367 +       /** Pointer to Descriptor with latest SETUP packet */
59368 +       dwc_otg_dev_dma_desc_t *psetup;
59369 +
59370 +       /** Index of current SETUP handler descriptor */
59371 +       uint32_t setup_desc_index;
59372 +
59373 +       /** Descriptor for Data In or Status In phases */
59374 +       dwc_dma_t dma_in_desc_addr;
59375 +       dwc_otg_dev_dma_desc_t *in_desc_addr;
59376 +
59377 +       /** Descriptor for Data Out or Status Out phases */
59378 +       dwc_dma_t dma_out_desc_addr;
59379 +       dwc_otg_dev_dma_desc_t *out_desc_addr;
59380 +
59381 +       /** Setup Packet Detected - if set clear NAK when queueing */
59382 +       uint32_t spd;
59383 +       /** Isoc ep pointer on which incomplete happens */
59384 +       void *isoc_ep;
59385 +
59386 +} dwc_otg_dev_if_t;
59387 +
59388 +/////////////////////////////////////////////////
59389 +// Host Mode Register Structures
59390 +//
59391 +/**
59392 + * The Host Global Registers structure defines the size and relative
59393 + * field offsets for the Host Mode Global Registers.  Host Global
59394 + * Registers offsets 400h-7FFh.
59395 +*/
59396 +typedef struct dwc_otg_host_global_regs {
59397 +       /** Host Configuration Register.   <i>Offset: 400h</i> */
59398 +       volatile uint32_t hcfg;
59399 +       /** Host Frame Interval Register.       <i>Offset: 404h</i> */
59400 +       volatile uint32_t hfir;
59401 +       /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */
59402 +       volatile uint32_t hfnum;
59403 +       /** Reserved.   <i>Offset: 40Ch</i> */
59404 +       uint32_t reserved40C;
59405 +       /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */
59406 +       volatile uint32_t hptxsts;
59407 +       /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */
59408 +       volatile uint32_t haint;
59409 +       /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */
59410 +       volatile uint32_t haintmsk;
59411 +       /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */
59412 +       volatile uint32_t hflbaddr;
59413 +} dwc_otg_host_global_regs_t;
59414 +
59415 +/**
59416 + * This union represents the bit fields in the Host Configuration Register.
59417 + * Read the register into the <i>d32</i> member then set/clear the bits using
59418 + * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register.
59419 + */
59420 +typedef union hcfg_data {
59421 +       /** raw register data */
59422 +       uint32_t d32;
59423 +
59424 +       /** register bits */
59425 +       struct {
59426 +               /** FS/LS Phy Clock Select */
59427 +               unsigned fslspclksel:2;
59428 +#define DWC_HCFG_30_60_MHZ 0
59429 +#define DWC_HCFG_48_MHZ           1
59430 +#define DWC_HCFG_6_MHZ    2
59431 +
59432 +               /** FS/LS Only Support */
59433 +               unsigned fslssupp:1;
59434 +               unsigned reserved3_6:4;
59435 +               /** Enable 32-KHz Suspend Mode */
59436 +               unsigned ena32khzs:1;
59437 +               /** Resume Validation Periiod */
59438 +               unsigned resvalid:8;
59439 +               unsigned reserved16_22:7;
59440 +               /** Enable Scatter/gather DMA in Host mode */
59441 +               unsigned descdma:1;
59442 +               /** Frame List Entries */
59443 +               unsigned frlisten:2;
59444 +               /** Enable Periodic Scheduling */
59445 +               unsigned perschedena:1;
59446 +               unsigned reserved27_30:4;
59447 +               unsigned modechtimen:1;
59448 +       } b;
59449 +} hcfg_data_t;
59450 +
59451 +/**
59452 + * This union represents the bit fields in the Host Frame Remaing/Number
59453 + * Register.
59454 + */
59455 +typedef union hfir_data {
59456 +       /** raw register data */
59457 +       uint32_t d32;
59458 +
59459 +       /** register bits */
59460 +       struct {
59461 +               unsigned frint:16;
59462 +               unsigned hfirrldctrl:1;
59463 +               unsigned reserved:15;
59464 +       } b;
59465 +} hfir_data_t;
59466 +
59467 +/**
59468 + * This union represents the bit fields in the Host Frame Remaing/Number
59469 + * Register.
59470 + */
59471 +typedef union hfnum_data {
59472 +       /** raw register data */
59473 +       uint32_t d32;
59474 +
59475 +       /** register bits */
59476 +       struct {
59477 +               unsigned frnum:16;
59478 +#define DWC_HFNUM_MAX_FRNUM 0x3FFF
59479 +               unsigned frrem:16;
59480 +       } b;
59481 +} hfnum_data_t;
59482 +
59483 +typedef union hptxsts_data {
59484 +       /** raw register data */
59485 +       uint32_t d32;
59486 +
59487 +       /** register bits */
59488 +       struct {
59489 +               unsigned ptxfspcavail:16;
59490 +               unsigned ptxqspcavail:8;
59491 +               /** Top of the Periodic Transmit Request Queue
59492 +                *      - bit 24 - Terminate (last entry for the selected channel)
59493 +                *      - bits 26:25 - Token Type
59494 +                *        - 2'b00 - Zero length
59495 +                *        - 2'b01 - Ping
59496 +                *        - 2'b10 - Disable
59497 +                *      - bits 30:27 - Channel Number
59498 +                *      - bit 31 - Odd/even microframe
59499 +                */
59500 +               unsigned ptxqtop_terminate:1;
59501 +               unsigned ptxqtop_token:2;
59502 +               unsigned ptxqtop_chnum:4;
59503 +               unsigned ptxqtop_odd:1;
59504 +       } b;
59505 +} hptxsts_data_t;
59506 +
59507 +/**
59508 + * This union represents the bit fields in the Host Port Control and Status
59509 + * Register. Read the register into the <i>d32</i> member then set/clear the
59510 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
59511 + * hprt0 register.
59512 + */
59513 +typedef union hprt0_data {
59514 +       /** raw register data */
59515 +       uint32_t d32;
59516 +       /** register bits */
59517 +       struct {
59518 +               unsigned prtconnsts:1;
59519 +               unsigned prtconndet:1;
59520 +               unsigned prtena:1;
59521 +               unsigned prtenchng:1;
59522 +               unsigned prtovrcurract:1;
59523 +               unsigned prtovrcurrchng:1;
59524 +               unsigned prtres:1;
59525 +               unsigned prtsusp:1;
59526 +               unsigned prtrst:1;
59527 +               unsigned reserved9:1;
59528 +               unsigned prtlnsts:2;
59529 +               unsigned prtpwr:1;
59530 +               unsigned prttstctl:4;
59531 +               unsigned prtspd:2;
59532 +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
59533 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1
59534 +#define DWC_HPRT0_PRTSPD_LOW_SPEED     2
59535 +               unsigned reserved19_31:13;
59536 +       } b;
59537 +} hprt0_data_t;
59538 +
59539 +/**
59540 + * This union represents the bit fields in the Host All Interrupt
59541 + * Register.
59542 + */
59543 +typedef union haint_data {
59544 +       /** raw register data */
59545 +       uint32_t d32;
59546 +       /** register bits */
59547 +       struct {
59548 +               unsigned ch0:1;
59549 +               unsigned ch1:1;
59550 +               unsigned ch2:1;
59551 +               unsigned ch3:1;
59552 +               unsigned ch4:1;
59553 +               unsigned ch5:1;
59554 +               unsigned ch6:1;
59555 +               unsigned ch7:1;
59556 +               unsigned ch8:1;
59557 +               unsigned ch9:1;
59558 +               unsigned ch10:1;
59559 +               unsigned ch11:1;
59560 +               unsigned ch12:1;
59561 +               unsigned ch13:1;
59562 +               unsigned ch14:1;
59563 +               unsigned ch15:1;
59564 +               unsigned reserved:16;
59565 +       } b;
59566 +
59567 +       struct {
59568 +               unsigned chint:16;
59569 +               unsigned reserved:16;
59570 +       } b2;
59571 +} haint_data_t;
59572 +
59573 +/**
59574 + * This union represents the bit fields in the Host All Interrupt
59575 + * Register.
59576 + */
59577 +typedef union haintmsk_data {
59578 +       /** raw register data */
59579 +       uint32_t d32;
59580 +       /** register bits */
59581 +       struct {
59582 +               unsigned ch0:1;
59583 +               unsigned ch1:1;
59584 +               unsigned ch2:1;
59585 +               unsigned ch3:1;
59586 +               unsigned ch4:1;
59587 +               unsigned ch5:1;
59588 +               unsigned ch6:1;
59589 +               unsigned ch7:1;
59590 +               unsigned ch8:1;
59591 +               unsigned ch9:1;
59592 +               unsigned ch10:1;
59593 +               unsigned ch11:1;
59594 +               unsigned ch12:1;
59595 +               unsigned ch13:1;
59596 +               unsigned ch14:1;
59597 +               unsigned ch15:1;
59598 +               unsigned reserved:16;
59599 +       } b;
59600 +
59601 +       struct {
59602 +               unsigned chint:16;
59603 +               unsigned reserved:16;
59604 +       } b2;
59605 +} haintmsk_data_t;
59606 +
59607 +/**
59608 + * Host Channel Specific Registers. <i>500h-5FCh</i>
59609 + */
59610 +typedef struct dwc_otg_hc_regs {
59611 +       /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */
59612 +       volatile uint32_t hcchar;
59613 +       /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */
59614 +       volatile uint32_t hcsplt;
59615 +       /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */
59616 +       volatile uint32_t hcint;
59617 +       /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */
59618 +       volatile uint32_t hcintmsk;
59619 +       /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */
59620 +       volatile uint32_t hctsiz;
59621 +       /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */
59622 +       volatile uint32_t hcdma;
59623 +       volatile uint32_t reserved;
59624 +       /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */
59625 +       volatile uint32_t hcdmab;
59626 +} dwc_otg_hc_regs_t;
59627 +
59628 +/**
59629 + * This union represents the bit fields in the Host Channel Characteristics
59630 + * Register. Read the register into the <i>d32</i> member then set/clear the
59631 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
59632 + * hcchar register.
59633 + */
59634 +typedef union hcchar_data {
59635 +       /** raw register data */
59636 +       uint32_t d32;
59637 +
59638 +       /** register bits */
59639 +       struct {
59640 +               /** Maximum packet size in bytes */
59641 +               unsigned mps:11;
59642 +
59643 +               /** Endpoint number */
59644 +               unsigned epnum:4;
59645 +
59646 +               /** 0: OUT, 1: IN */
59647 +               unsigned epdir:1;
59648 +
59649 +               unsigned reserved:1;
59650 +
59651 +               /** 0: Full/high speed device, 1: Low speed device */
59652 +               unsigned lspddev:1;
59653 +
59654 +               /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
59655 +               unsigned eptype:2;
59656 +
59657 +               /** Packets per frame for periodic transfers. 0 is reserved. */
59658 +               unsigned multicnt:2;
59659 +
59660 +               /** Device address */
59661 +               unsigned devaddr:7;
59662 +
59663 +               /**
59664 +                * Frame to transmit periodic transaction.
59665 +                * 0: even, 1: odd
59666 +                */
59667 +               unsigned oddfrm:1;
59668 +
59669 +               /** Channel disable */
59670 +               unsigned chdis:1;
59671 +
59672 +               /** Channel enable */
59673 +               unsigned chen:1;
59674 +       } b;
59675 +} hcchar_data_t;
59676 +
59677 +typedef union hcsplt_data {
59678 +       /** raw register data */
59679 +       uint32_t d32;
59680 +
59681 +       /** register bits */
59682 +       struct {
59683 +               /** Port Address */
59684 +               unsigned prtaddr:7;
59685 +
59686 +               /** Hub Address */
59687 +               unsigned hubaddr:7;
59688 +
59689 +               /** Transaction Position */
59690 +               unsigned xactpos:2;
59691 +#define DWC_HCSPLIT_XACTPOS_MID 0
59692 +#define DWC_HCSPLIT_XACTPOS_END 1
59693 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2
59694 +#define DWC_HCSPLIT_XACTPOS_ALL 3
59695 +
59696 +               /** Do Complete Split */
59697 +               unsigned compsplt:1;
59698 +
59699 +               /** Reserved */
59700 +               unsigned reserved:14;
59701 +
59702 +               /** Split Enble */
59703 +               unsigned spltena:1;
59704 +       } b;
59705 +} hcsplt_data_t;
59706 +
59707 +/**
59708 + * This union represents the bit fields in the Host All Interrupt
59709 + * Register.
59710 + */
59711 +typedef union hcint_data {
59712 +       /** raw register data */
59713 +       uint32_t d32;
59714 +       /** register bits */
59715 +       struct {
59716 +               /** Transfer Complete */
59717 +               unsigned xfercomp:1;
59718 +               /** Channel Halted */
59719 +               unsigned chhltd:1;
59720 +               /** AHB Error */
59721 +               unsigned ahberr:1;
59722 +               /** STALL Response Received */
59723 +               unsigned stall:1;
59724 +               /** NAK Response Received */
59725 +               unsigned nak:1;
59726 +               /** ACK Response Received */
59727 +               unsigned ack:1;
59728 +               /** NYET Response Received */
59729 +               unsigned nyet:1;
59730 +               /** Transaction Err */
59731 +               unsigned xacterr:1;
59732 +               /** Babble Error */
59733 +               unsigned bblerr:1;
59734 +               /** Frame Overrun */
59735 +               unsigned frmovrun:1;
59736 +               /** Data Toggle Error */
59737 +               unsigned datatglerr:1;
59738 +               /** Buffer Not Available (only for DDMA mode) */
59739 +               unsigned bna:1;
59740 +               /** Exessive transaction error (only for DDMA mode) */
59741 +               unsigned xcs_xact:1;
59742 +               /** Frame List Rollover interrupt */
59743 +               unsigned frm_list_roll:1;
59744 +               /** Reserved */
59745 +               unsigned reserved14_31:18;
59746 +       } b;
59747 +} hcint_data_t;
59748 +
59749 +/**
59750 + * This union represents the bit fields in the Host Channel Interrupt Mask
59751 + * Register. Read the register into the <i>d32</i> member then set/clear the
59752 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
59753 + * hcintmsk register.
59754 + */
59755 +typedef union hcintmsk_data {
59756 +       /** raw register data */
59757 +       uint32_t d32;
59758 +
59759 +       /** register bits */
59760 +       struct {
59761 +               unsigned xfercompl:1;
59762 +               unsigned chhltd:1;
59763 +               unsigned ahberr:1;
59764 +               unsigned stall:1;
59765 +               unsigned nak:1;
59766 +               unsigned ack:1;
59767 +               unsigned nyet:1;
59768 +               unsigned xacterr:1;
59769 +               unsigned bblerr:1;
59770 +               unsigned frmovrun:1;
59771 +               unsigned datatglerr:1;
59772 +               unsigned bna:1;
59773 +               unsigned xcs_xact:1;
59774 +               unsigned frm_list_roll:1;
59775 +               unsigned reserved14_31:18;
59776 +       } b;
59777 +} hcintmsk_data_t;
59778 +
59779 +/**
59780 + * This union represents the bit fields in the Host Channel Transfer Size
59781 + * Register. Read the register into the <i>d32</i> member then set/clear the
59782 + * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the
59783 + * hcchar register.
59784 + */
59785 +
59786 +typedef union hctsiz_data {
59787 +       /** raw register data */
59788 +       uint32_t d32;
59789 +
59790 +       /** register bits */
59791 +       struct {
59792 +               /** Total transfer size in bytes */
59793 +               unsigned xfersize:19;
59794 +
59795 +               /** Data packets to transfer */
59796 +               unsigned pktcnt:10;
59797 +
59798 +               /**
59799 +                * Packet ID for next data packet
59800 +                * 0: DATA0
59801 +                * 1: DATA2
59802 +                * 2: DATA1
59803 +                * 3: MDATA (non-Control), SETUP (Control)
59804 +                */
59805 +               unsigned pid:2;
59806 +#define DWC_HCTSIZ_DATA0 0
59807 +#define DWC_HCTSIZ_DATA1 2
59808 +#define DWC_HCTSIZ_DATA2 1
59809 +#define DWC_HCTSIZ_MDATA 3
59810 +#define DWC_HCTSIZ_SETUP 3
59811 +
59812 +               /** Do PING protocol when 1 */
59813 +               unsigned dopng:1;
59814 +       } b;
59815 +
59816 +       /** register bits */
59817 +       struct {
59818 +               /** Scheduling information */
59819 +               unsigned schinfo:8;
59820 +
59821 +               /** Number of transfer descriptors.
59822 +                * Max value:
59823 +                * 64 in general,
59824 +                * 256 only for HS isochronous endpoint.
59825 +                */
59826 +               unsigned ntd:8;
59827 +
59828 +               /** Data packets to transfer */
59829 +               unsigned reserved16_28:13;
59830 +
59831 +               /**
59832 +                * Packet ID for next data packet
59833 +                * 0: DATA0
59834 +                * 1: DATA2
59835 +                * 2: DATA1
59836 +                * 3: MDATA (non-Control)
59837 +                */
59838 +               unsigned pid:2;
59839 +
59840 +               /** Do PING protocol when 1 */
59841 +               unsigned dopng:1;
59842 +       } b_ddma;
59843 +} hctsiz_data_t;
59844 +
59845 +/**
59846 + * This union represents the bit fields in the Host DMA Address
59847 + * Register used in Descriptor DMA mode.
59848 + */
59849 +typedef union hcdma_data {
59850 +       /** raw register data */
59851 +       uint32_t d32;
59852 +       /** register bits */
59853 +       struct {
59854 +               unsigned reserved0_2:3;
59855 +               /** Current Transfer Descriptor. Not used for ISOC */
59856 +               unsigned ctd:8;
59857 +               /** Start Address of Descriptor List */
59858 +               unsigned dma_addr:21;
59859 +       } b;
59860 +} hcdma_data_t;
59861 +
59862 +/**
59863 + * This union represents the bit fields in the DMA Descriptor
59864 + * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then
59865 + * set/clear the bits using the <i>b</i>it elements.
59866 + */
59867 +typedef union host_dma_desc_sts {
59868 +       /** raw register data */
59869 +       uint32_t d32;
59870 +       /** quadlet bits */
59871 +
59872 +       /* for non-isochronous  */
59873 +       struct {
59874 +               /** Number of bytes */
59875 +               unsigned n_bytes:17;
59876 +               /** QTD offset to jump when Short Packet received - only for IN EPs */
59877 +               unsigned qtd_offset:6;
59878 +               /**
59879 +                * Set to request the core to jump to alternate QTD if
59880 +                * Short Packet received - only for IN EPs
59881 +                */
59882 +               unsigned a_qtd:1;
59883 +                /**
59884 +                 * Setup Packet bit. When set indicates that buffer contains
59885 +                 * setup packet.
59886 +                 */
59887 +               unsigned sup:1;
59888 +               /** Interrupt On Complete */
59889 +               unsigned ioc:1;
59890 +               /** End of List */
59891 +               unsigned eol:1;
59892 +               unsigned reserved27:1;
59893 +               /** Rx/Tx Status */
59894 +               unsigned sts:2;
59895 +#define DMA_DESC_STS_PKTERR    1
59896 +               unsigned reserved30:1;
59897 +               /** Active Bit */
59898 +               unsigned a:1;
59899 +       } b;
59900 +       /* for isochronous */
59901 +       struct {
59902 +               /** Number of bytes */
59903 +               unsigned n_bytes:12;
59904 +               unsigned reserved12_24:13;
59905 +               /** Interrupt On Complete */
59906 +               unsigned ioc:1;
59907 +               unsigned reserved26_27:2;
59908 +               /** Rx/Tx Status */
59909 +               unsigned sts:2;
59910 +               unsigned reserved30:1;
59911 +               /** Active Bit */
59912 +               unsigned a:1;
59913 +       } b_isoc;
59914 +} host_dma_desc_sts_t;
59915 +
59916 +#define        MAX_DMA_DESC_SIZE               131071
59917 +#define MAX_DMA_DESC_NUM_GENERIC       64
59918 +#define MAX_DMA_DESC_NUM_HS_ISOC       256
59919 +#define MAX_FRLIST_EN_NUM              64
59920 +/**
59921 + * Host-mode DMA Descriptor structure
59922 + *
59923 + * DMA Descriptor structure contains two quadlets:
59924 + * Status quadlet and Data buffer pointer.
59925 + */
59926 +typedef struct dwc_otg_host_dma_desc {
59927 +       /** DMA Descriptor status quadlet */
59928 +       host_dma_desc_sts_t status;
59929 +       /** DMA Descriptor data buffer pointer */
59930 +       uint32_t buf;
59931 +} dwc_otg_host_dma_desc_t;
59932 +
59933 +/** OTG Host Interface Structure.
59934 + *
59935 + * The OTG Host Interface Structure structure contains information
59936 + * needed to manage the DWC_otg controller acting in host mode. It
59937 + * represents the programming view of the host-specific aspects of the
59938 + * controller.
59939 + */
59940 +typedef struct dwc_otg_host_if {
59941 +       /** Host Global Registers starting at offset 400h.*/
59942 +       dwc_otg_host_global_regs_t *host_global_regs;
59943 +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
59944 +
59945 +       /** Host Port 0 Control and Status Register */
59946 +       volatile uint32_t *hprt0;
59947 +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
59948 +
59949 +       /** Host Channel Specific Registers at offsets 500h-5FCh. */
59950 +       dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
59951 +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
59952 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20
59953 +
59954 +       /* Host configuration information */
59955 +       /** Number of Host Channels (range: 1-16) */
59956 +       uint8_t num_host_channels;
59957 +       /** Periodic EPs supported (0: no, 1: yes) */
59958 +       uint8_t perio_eps_supported;
59959 +       /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */
59960 +       uint16_t perio_tx_fifo_size;
59961 +
59962 +} dwc_otg_host_if_t;
59963 +
59964 +/**
59965 + * This union represents the bit fields in the Power and Clock Gating Control
59966 + * Register. Read the register into the <i>d32</i> member then set/clear the
59967 + * bits using the <i>b</i>it elements.
59968 + */
59969 +typedef union pcgcctl_data {
59970 +       /** raw register data */
59971 +       uint32_t d32;
59972 +
59973 +       /** register bits */
59974 +       struct {
59975 +               /** Stop Pclk */
59976 +               unsigned stoppclk:1;
59977 +               /** Gate Hclk */
59978 +               unsigned gatehclk:1;
59979 +               /** Power Clamp */
59980 +               unsigned pwrclmp:1;
59981 +               /** Reset Power Down Modules */
59982 +               unsigned rstpdwnmodule:1;
59983 +               /** Reserved */
59984 +               unsigned reserved:1;
59985 +               /** Enable Sleep Clock Gating (Enbl_L1Gating) */
59986 +               unsigned enbl_sleep_gating:1;
59987 +               /** PHY In Sleep (PhySleep) */
59988 +               unsigned phy_in_sleep:1;
59989 +               /** Deep Sleep*/
59990 +               unsigned deep_sleep:1;
59991 +               unsigned resetaftsusp:1;
59992 +               unsigned restoremode:1;
59993 +               unsigned enbl_extnd_hiber:1;
59994 +               unsigned extnd_hiber_pwrclmp:1;
59995 +               unsigned extnd_hiber_switch:1;
59996 +               unsigned ess_reg_restored:1;
59997 +               unsigned prt_clk_sel:2;
59998 +               unsigned port_power:1;
59999 +               unsigned max_xcvrselect:2;
60000 +               unsigned max_termsel:1;
60001 +               unsigned mac_dev_addr:7;
60002 +               unsigned p2hd_dev_enum_spd:2;
60003 +               unsigned p2hd_prt_spd:2;
60004 +               unsigned if_dev_mode:1;
60005 +       } b;
60006 +} pcgcctl_data_t;
60007 +
60008 +/**
60009 + * This union represents the bit fields in the Global Data FIFO Software
60010 + * Configuration Register. Read the register into the <i>d32</i> member then
60011 + * set/clear the bits using the <i>b</i>it elements.
60012 + */
60013 +typedef union gdfifocfg_data {
60014 +       /* raw register data */
60015 +       uint32_t d32;
60016 +       /** register bits */
60017 +       struct {
60018 +               /** OTG Data FIFO depth */
60019 +               unsigned gdfifocfg:16;
60020 +               /** Start address of EP info controller */
60021 +               unsigned epinfobase:16;
60022 +       } b;
60023 +} gdfifocfg_data_t;
60024 +
60025 +/**
60026 + * This union represents the bit fields in the Global Power Down Register
60027 + * Register. Read the register into the <i>d32</i> member then set/clear the
60028 + * bits using the <i>b</i>it elements.
60029 + */
60030 +typedef union gpwrdn_data {
60031 +       /* raw register data */
60032 +       uint32_t d32;
60033 +
60034 +       /** register bits */
60035 +       struct {
60036 +               /** PMU Interrupt Select */
60037 +               unsigned pmuintsel:1;
60038 +               /** PMU Active */
60039 +               unsigned pmuactv:1;
60040 +               /** Restore */
60041 +               unsigned restore:1;
60042 +               /** Power Down Clamp */
60043 +               unsigned pwrdnclmp:1;
60044 +               /** Power Down Reset */
60045 +               unsigned pwrdnrstn:1;
60046 +               /** Power Down Switch */
60047 +               unsigned pwrdnswtch:1;
60048 +               /** Disable VBUS */
60049 +               unsigned dis_vbus:1;
60050 +               /** Line State Change */
60051 +               unsigned lnstschng:1;
60052 +               /** Line state change mask */
60053 +               unsigned lnstchng_msk:1;
60054 +               /** Reset Detected */
60055 +               unsigned rst_det:1;
60056 +               /** Reset Detect mask */
60057 +               unsigned rst_det_msk:1;
60058 +               /** Disconnect Detected */
60059 +               unsigned disconn_det:1;
60060 +               /** Disconnect Detect mask */
60061 +               unsigned disconn_det_msk:1;
60062 +               /** Connect Detected*/
60063 +               unsigned connect_det:1;
60064 +               /** Connect Detected Mask*/
60065 +               unsigned connect_det_msk:1;
60066 +               /** SRP Detected */
60067 +               unsigned srp_det:1;
60068 +               /** SRP Detect mask */
60069 +               unsigned srp_det_msk:1;
60070 +               /** Status Change Interrupt */
60071 +               unsigned sts_chngint:1;
60072 +               /** Status Change Interrupt Mask */
60073 +               unsigned sts_chngint_msk:1;
60074 +               /** Line State */
60075 +               unsigned linestate:2;
60076 +               /** Indicates current mode(status of IDDIG signal) */
60077 +               unsigned idsts:1;
60078 +               /** B Session Valid signal status*/
60079 +               unsigned bsessvld:1;
60080 +               /** ADP Event Detected */
60081 +               unsigned adp_int:1;
60082 +               /** Multi Valued ID pin */
60083 +               unsigned mult_val_id_bc:5;
60084 +               /** Reserved 24_31 */
60085 +               unsigned reserved29_31:3;
60086 +       } b;
60087 +} gpwrdn_data_t;
60088 +
60089 +#endif
60090 --- /dev/null
60091 +++ b/drivers/usb/host/dwc_otg/test/Makefile
60092 @@ -0,0 +1,16 @@
60093 +
60094 +PERL=/usr/bin/perl
60095 +PL_TESTS=test_sysfs.pl test_mod_param.pl
60096 +
60097 +.PHONY : test
60098 +test : perl_tests
60099 +
60100 +perl_tests :
60101 +       @echo
60102 +       @echo Running perl tests
60103 +       @for test in $(PL_TESTS); do \
60104 +         if $(PERL) ./$$test ; then \
60105 +           echo "=======> $$test, PASSED" ; \
60106 +         else echo "=======> $$test, FAILED" ; \
60107 +         fi \
60108 +       done
60109 --- /dev/null
60110 +++ b/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm
60111 @@ -0,0 +1,337 @@
60112 +package dwc_otg_test;
60113 +
60114 +use strict;
60115 +use Exporter ();
60116 +
60117 +use vars qw(@ISA @EXPORT
60118 +$sysfsdir $paramdir $errors $params
60119 +);
60120 +
60121 +@ISA = qw(Exporter);
60122 +
60123 +#
60124 +# Globals
60125 +#
60126 +$sysfsdir = "/sys/devices/lm0";
60127 +$paramdir = "/sys/module/dwc_otg";
60128 +$errors = 0;
60129 +
60130 +$params = [
60131 +          {
60132 +           NAME => "otg_cap",
60133 +           DEFAULT => 0,
60134 +           ENUM => [],
60135 +           LOW => 0,
60136 +           HIGH => 2
60137 +          },
60138 +          {
60139 +           NAME => "dma_enable",
60140 +           DEFAULT => 0,
60141 +           ENUM => [],
60142 +           LOW => 0,
60143 +           HIGH => 1
60144 +          },
60145 +          {
60146 +           NAME => "dma_burst_size",
60147 +           DEFAULT => 32,
60148 +           ENUM => [1, 4, 8, 16, 32, 64, 128, 256],
60149 +           LOW => 1,
60150 +           HIGH => 256
60151 +          },
60152 +          {
60153 +           NAME => "host_speed",
60154 +           DEFAULT => 0,
60155 +           ENUM => [],
60156 +           LOW => 0,
60157 +           HIGH => 1
60158 +          },
60159 +          {
60160 +           NAME => "host_support_fs_ls_low_power",
60161 +           DEFAULT => 0,
60162 +           ENUM => [],
60163 +           LOW => 0,
60164 +           HIGH => 1
60165 +          },
60166 +          {
60167 +           NAME => "host_ls_low_power_phy_clk",
60168 +           DEFAULT => 0,
60169 +           ENUM => [],
60170 +           LOW => 0,
60171 +           HIGH => 1
60172 +          },
60173 +          {
60174 +           NAME => "dev_speed",
60175 +           DEFAULT => 0,
60176 +           ENUM => [],
60177 +           LOW => 0,
60178 +           HIGH => 1
60179 +          },
60180 +          {
60181 +           NAME => "enable_dynamic_fifo",
60182 +           DEFAULT => 1,
60183 +           ENUM => [],
60184 +           LOW => 0,
60185 +           HIGH => 1
60186 +          },
60187 +          {
60188 +           NAME => "data_fifo_size",
60189 +           DEFAULT => 8192,
60190 +           ENUM => [],
60191 +           LOW => 32,
60192 +           HIGH => 32768
60193 +          },
60194 +          {
60195 +           NAME => "dev_rx_fifo_size",
60196 +           DEFAULT => 1064,
60197 +           ENUM => [],
60198 +           LOW => 16,
60199 +           HIGH => 32768
60200 +          },
60201 +          {
60202 +           NAME => "dev_nperio_tx_fifo_size",
60203 +           DEFAULT => 1024,
60204 +           ENUM => [],
60205 +           LOW => 16,
60206 +           HIGH => 32768
60207 +          },
60208 +          {
60209 +           NAME => "dev_perio_tx_fifo_size_1",
60210 +           DEFAULT => 256,
60211 +           ENUM => [],
60212 +           LOW => 4,
60213 +           HIGH => 768
60214 +          },
60215 +          {
60216 +           NAME => "dev_perio_tx_fifo_size_2",
60217 +           DEFAULT => 256,
60218 +           ENUM => [],
60219 +           LOW => 4,
60220 +           HIGH => 768
60221 +          },
60222 +          {
60223 +           NAME => "dev_perio_tx_fifo_size_3",
60224 +           DEFAULT => 256,
60225 +           ENUM => [],
60226 +           LOW => 4,
60227 +           HIGH => 768
60228 +          },
60229 +          {
60230 +           NAME => "dev_perio_tx_fifo_size_4",
60231 +           DEFAULT => 256,
60232 +           ENUM => [],
60233 +           LOW => 4,
60234 +           HIGH => 768
60235 +          },
60236 +          {
60237 +           NAME => "dev_perio_tx_fifo_size_5",
60238 +           DEFAULT => 256,
60239 +           ENUM => [],
60240 +           LOW => 4,
60241 +           HIGH => 768
60242 +          },
60243 +          {
60244 +           NAME => "dev_perio_tx_fifo_size_6",
60245 +           DEFAULT => 256,
60246 +           ENUM => [],
60247 +           LOW => 4,
60248 +           HIGH => 768
60249 +          },
60250 +          {
60251 +           NAME => "dev_perio_tx_fifo_size_7",
60252 +           DEFAULT => 256,
60253 +           ENUM => [],
60254 +           LOW => 4,
60255 +           HIGH => 768
60256 +          },
60257 +          {
60258 +           NAME => "dev_perio_tx_fifo_size_8",
60259 +           DEFAULT => 256,
60260 +           ENUM => [],
60261 +           LOW => 4,
60262 +           HIGH => 768
60263 +          },
60264 +          {
60265 +           NAME => "dev_perio_tx_fifo_size_9",
60266 +           DEFAULT => 256,
60267 +           ENUM => [],
60268 +           LOW => 4,
60269 +           HIGH => 768
60270 +          },
60271 +          {
60272 +           NAME => "dev_perio_tx_fifo_size_10",
60273 +           DEFAULT => 256,
60274 +           ENUM => [],
60275 +           LOW => 4,
60276 +           HIGH => 768
60277 +          },
60278 +          {
60279 +           NAME => "dev_perio_tx_fifo_size_11",
60280 +           DEFAULT => 256,
60281 +           ENUM => [],
60282 +           LOW => 4,
60283 +           HIGH => 768
60284 +          },
60285 +          {
60286 +           NAME => "dev_perio_tx_fifo_size_12",
60287 +           DEFAULT => 256,
60288 +           ENUM => [],
60289 +           LOW => 4,
60290 +           HIGH => 768
60291 +          },
60292 +          {
60293 +           NAME => "dev_perio_tx_fifo_size_13",
60294 +           DEFAULT => 256,
60295 +           ENUM => [],
60296 +           LOW => 4,
60297 +           HIGH => 768
60298 +          },
60299 +          {
60300 +           NAME => "dev_perio_tx_fifo_size_14",
60301 +           DEFAULT => 256,
60302 +           ENUM => [],
60303 +           LOW => 4,
60304 +           HIGH => 768
60305 +          },
60306 +          {
60307 +           NAME => "dev_perio_tx_fifo_size_15",
60308 +           DEFAULT => 256,
60309 +           ENUM => [],
60310 +           LOW => 4,
60311 +           HIGH => 768
60312 +          },
60313 +          {
60314 +           NAME => "host_rx_fifo_size",
60315 +           DEFAULT => 1024,
60316 +           ENUM => [],
60317 +           LOW => 16,
60318 +           HIGH => 32768
60319 +          },
60320 +          {
60321 +           NAME => "host_nperio_tx_fifo_size",
60322 +           DEFAULT => 1024,
60323 +           ENUM => [],
60324 +           LOW => 16,
60325 +           HIGH => 32768
60326 +          },
60327 +          {
60328 +           NAME => "host_perio_tx_fifo_size",
60329 +           DEFAULT => 1024,
60330 +           ENUM => [],
60331 +           LOW => 16,
60332 +           HIGH => 32768
60333 +          },
60334 +          {
60335 +           NAME => "max_transfer_size",
60336 +           DEFAULT => 65535,
60337 +           ENUM => [],
60338 +           LOW => 2047,
60339 +           HIGH => 65535
60340 +          },
60341 +          {
60342 +           NAME => "max_packet_count",
60343 +           DEFAULT => 511,
60344 +           ENUM => [],
60345 +           LOW => 15,
60346 +           HIGH => 511
60347 +          },
60348 +          {
60349 +           NAME => "host_channels",
60350 +           DEFAULT => 12,
60351 +           ENUM => [],
60352 +           LOW => 1,
60353 +           HIGH => 16
60354 +          },
60355 +          {
60356 +           NAME => "dev_endpoints",
60357 +           DEFAULT => 6,
60358 +           ENUM => [],
60359 +           LOW => 1,
60360 +           HIGH => 15
60361 +          },
60362 +          {
60363 +           NAME => "phy_type",
60364 +           DEFAULT => 1,
60365 +           ENUM => [],
60366 +           LOW => 0,
60367 +           HIGH => 2
60368 +          },
60369 +          {
60370 +           NAME => "phy_utmi_width",
60371 +           DEFAULT => 16,
60372 +           ENUM => [8, 16],
60373 +           LOW => 8,
60374 +           HIGH => 16
60375 +          },
60376 +          {
60377 +           NAME => "phy_ulpi_ddr",
60378 +           DEFAULT => 0,
60379 +           ENUM => [],
60380 +           LOW => 0,
60381 +           HIGH => 1
60382 +          },
60383 +         ];
60384 +
60385 +
60386 +#
60387 +#
60388 +sub check_arch {
60389 +  $_ = `uname -m`;
60390 +  chomp;
60391 +  unless (m/armv4tl/) {
60392 +    warn "# \n# Can't execute on $_.  Run on integrator platform.\n# \n";
60393 +    return 0;
60394 +  }
60395 +  return 1;
60396 +}
60397 +
60398 +#
60399 +#
60400 +sub load_module {
60401 +  my $params = shift;
60402 +  print "\nRemoving Module\n";
60403 +  system "rmmod dwc_otg";
60404 +  print "Loading Module\n";
60405 +  if ($params ne "") {
60406 +    print "Module Parameters: $params\n";
60407 +  }
60408 +  if (system("modprobe dwc_otg $params")) {
60409 +    warn "Unable to load module\n";
60410 +    return 0;
60411 +  }
60412 +  return 1;
60413 +}
60414 +
60415 +#
60416 +#
60417 +sub test_status {
60418 +  my $arg = shift;
60419 +
60420 +  print "\n";
60421 +
60422 +  if (defined $arg) {
60423 +    warn "WARNING: $arg\n";
60424 +  }
60425 +
60426 +  if ($errors > 0) {
60427 +    warn "TEST FAILED with $errors errors\n";
60428 +    return 0;
60429 +  } else {
60430 +    print "TEST PASSED\n";
60431 +    return 0 if (defined $arg);
60432 +  }
60433 +  return 1;
60434 +}
60435 +
60436 +#
60437 +#
60438 +@EXPORT = qw(
60439 +$sysfsdir
60440 +$paramdir
60441 +$params
60442 +$errors
60443 +check_arch
60444 +load_module
60445 +test_status
60446 +);
60447 +
60448 +1;
60449 --- /dev/null
60450 +++ b/drivers/usb/host/dwc_otg/test/test_mod_param.pl
60451 @@ -0,0 +1,133 @@
60452 +#!/usr/bin/perl -w
60453 +#
60454 +# Run this program on the integrator.
60455 +#
60456 +# - Tests module parameter default values.
60457 +# - Tests setting of valid module parameter values via modprobe.
60458 +# - Tests invalid module parameter values.
60459 +# -----------------------------------------------------------------------------
60460 +use strict;
60461 +use dwc_otg_test;
60462 +
60463 +check_arch() or die;
60464 +
60465 +#
60466 +#
60467 +sub test {
60468 +  my ($param,$expected) = @_;
60469 +  my $value = get($param);
60470 +
60471 +  if ($value == $expected) {
60472 +    print "$param = $value, okay\n";
60473 +  }
60474 +
60475 +  else {
60476 +    warn "ERROR: value of $param != $expected, $value\n";
60477 +    $errors ++;
60478 +  }
60479 +}
60480 +
60481 +#
60482 +#
60483 +sub get {
60484 +  my $param = shift;
60485 +  my $tmp = `cat $paramdir/$param`;
60486 +  chomp $tmp;
60487 +  return $tmp;
60488 +}
60489 +
60490 +#
60491 +#
60492 +sub test_main {
60493 +
60494 +  print "\nTesting Module Parameters\n";
60495 +
60496 +  load_module("") or die;
60497 +
60498 +  # Test initial values
60499 +  print "\nTesting Default Values\n";
60500 +  foreach (@{$params}) {
60501 +    test ($_->{NAME}, $_->{DEFAULT});
60502 +  }
60503 +
60504 +  # Test low value
60505 +  print "\nTesting Low Value\n";
60506 +  my $cmd_params = "";
60507 +  foreach (@{$params}) {
60508 +    $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} ";
60509 +  }
60510 +  load_module($cmd_params) or die;
60511 +
60512 +  foreach (@{$params}) {
60513 +    test ($_->{NAME}, $_->{LOW});
60514 +  }
60515 +
60516 +  # Test high value
60517 +  print "\nTesting High Value\n";
60518 +  $cmd_params = "";
60519 +  foreach (@{$params}) {
60520 +    $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} ";
60521 +  }
60522 +  load_module($cmd_params) or die;
60523 +
60524 +  foreach (@{$params}) {
60525 +    test ($_->{NAME}, $_->{HIGH});
60526 +  }
60527 +
60528 +  # Test Enum
60529 +  print "\nTesting Enumerated\n";
60530 +  foreach (@{$params}) {
60531 +    if (defined $_->{ENUM}) {
60532 +      my $value;
60533 +      foreach $value (@{$_->{ENUM}}) {
60534 +       $cmd_params = "$_->{NAME}=$value";
60535 +       load_module($cmd_params) or die;
60536 +       test ($_->{NAME}, $value);
60537 +      }
60538 +    }
60539 +  }
60540 +
60541 +  # Test Invalid Values
60542 +  print "\nTesting Invalid Values\n";
60543 +  $cmd_params = "";
60544 +  foreach (@{$params}) {
60545 +    $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1;
60546 +  }
60547 +  load_module($cmd_params) or die;
60548 +
60549 +  foreach (@{$params}) {
60550 +    test ($_->{NAME}, $_->{DEFAULT});
60551 +  }
60552 +
60553 +  $cmd_params = "";
60554 +  foreach (@{$params}) {
60555 +    $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1;
60556 +  }
60557 +  load_module($cmd_params) or die;
60558 +
60559 +  foreach (@{$params}) {
60560 +    test ($_->{NAME}, $_->{DEFAULT});
60561 +  }
60562 +
60563 +  print "\nTesting Enumerated\n";
60564 +  foreach (@{$params}) {
60565 +    if (defined $_->{ENUM}) {
60566 +      my $value;
60567 +      foreach $value (@{$_->{ENUM}}) {
60568 +       $value = $value + 1;
60569 +       $cmd_params = "$_->{NAME}=$value";
60570 +       load_module($cmd_params) or die;
60571 +       test ($_->{NAME}, $_->{DEFAULT});
60572 +       $value = $value - 2;
60573 +       $cmd_params = "$_->{NAME}=$value";
60574 +       load_module($cmd_params) or die;
60575 +       test ($_->{NAME}, $_->{DEFAULT});
60576 +      }
60577 +    }
60578 +  }
60579 +
60580 +  test_status() or die;
60581 +}
60582 +
60583 +test_main();
60584 +0;
60585 --- /dev/null
60586 +++ b/drivers/usb/host/dwc_otg/test/test_sysfs.pl
60587 @@ -0,0 +1,193 @@
60588 +#!/usr/bin/perl -w
60589 +#
60590 +# Run this program on the integrator
60591 +# - Tests select sysfs attributes.
60592 +# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc.
60593 +# -----------------------------------------------------------------------------
60594 +use strict;
60595 +use dwc_otg_test;
60596 +
60597 +check_arch() or die;
60598 +
60599 +#
60600 +#
60601 +sub test {
60602 +  my ($attr,$expected) = @_;
60603 +  my $string = get($attr);
60604 +
60605 +  if ($string eq $expected) {
60606 +    printf("$attr = $string, okay\n");
60607 +  }
60608 +  else {
60609 +    warn "ERROR: value of $attr != $expected, $string\n";
60610 +    $errors ++;
60611 +  }
60612 +}
60613 +
60614 +#
60615 +#
60616 +sub set {
60617 +  my ($reg, $value) = @_;
60618 +  system "echo $value > $sysfsdir/$reg";
60619 +}
60620 +
60621 +#
60622 +#
60623 +sub get {
60624 +  my $attr = shift;
60625 +  my $string = `cat $sysfsdir/$attr`;
60626 +  chomp $string;
60627 +  if ($string =~ m/\s\=\s/) {
60628 +    my $tmp;
60629 +    ($tmp, $string) = split /\s=\s/, $string;
60630 +  }
60631 +  return $string;
60632 +}
60633 +
60634 +#
60635 +#
60636 +sub test_main {
60637 +  print("\nTesting Sysfs Attributes\n");
60638 +
60639 +  load_module("") or die;
60640 +
60641 +  # Test initial values of regoffset/regvalue/guid/gsnpsid
60642 +  print("\nTesting Default Values\n");
60643 +
60644 +  test("regoffset", "0xffffffff");
60645 +  test("regvalue", "invalid offset");
60646 +  test("guid", "0x12345678");  # this will fail if it has been changed
60647 +  test("gsnpsid", "0x4f54200a");
60648 +
60649 +  # Test operation of regoffset/regvalue
60650 +  print("\nTesting regoffset\n");
60651 +  set('regoffset', '5a5a5a5a');
60652 +  test("regoffset", "0xffffffff");
60653 +
60654 +  set('regoffset', '0');
60655 +  test("regoffset", "0x00000000");
60656 +
60657 +  set('regoffset', '40000');
60658 +  test("regoffset", "0x00000000");
60659 +
60660 +  set('regoffset', '3ffff');
60661 +  test("regoffset", "0x0003ffff");
60662 +
60663 +  set('regoffset', '1');
60664 +  test("regoffset", "0x00000001");
60665 +
60666 +  print("\nTesting regvalue\n");
60667 +  set('regoffset', '3c');
60668 +  test("regvalue", "0x12345678");
60669 +  set('regvalue', '5a5a5a5a');
60670 +  test("regvalue", "0x5a5a5a5a");
60671 +  set('regvalue','a5a5a5a5');
60672 +  test("regvalue", "0xa5a5a5a5");
60673 +  set('guid','12345678');
60674 +
60675 +  # Test HNP Capable
60676 +  print("\nTesting HNP Capable bit\n");
60677 +  set('hnpcapable', '1');
60678 +  test("hnpcapable", "0x1");
60679 +  set('hnpcapable','0');
60680 +  test("hnpcapable", "0x0");
60681 +
60682 +  set('regoffset','0c');
60683 +
60684 +  my $old = get('gusbcfg');
60685 +  print("setting hnpcapable\n");
60686 +  set('hnpcapable', '1');
60687 +  test("hnpcapable", "0x1");
60688 +  test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9)));
60689 +  test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9)));
60690 +
60691 +  $old = get('gusbcfg');
60692 +  print("clearing hnpcapable\n");
60693 +  set('hnpcapable', '0');
60694 +  test("hnpcapable", "0x0");
60695 +  test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9)));
60696 +  test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9)));
60697 +
60698 +  # Test SRP Capable
60699 +  print("\nTesting SRP Capable bit\n");
60700 +  set('srpcapable', '1');
60701 +  test("srpcapable", "0x1");
60702 +  set('srpcapable','0');
60703 +  test("srpcapable", "0x0");
60704 +
60705 +  set('regoffset','0c');
60706 +
60707 +  $old = get('gusbcfg');
60708 +  print("setting srpcapable\n");
60709 +  set('srpcapable', '1');
60710 +  test("srpcapable", "0x1");
60711 +  test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8)));
60712 +  test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8)));
60713 +
60714 +  $old = get('gusbcfg');
60715 +  print("clearing srpcapable\n");
60716 +  set('srpcapable', '0');
60717 +  test("srpcapable", "0x0");
60718 +  test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8)));
60719 +  test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8)));
60720 +
60721 +  # Test GGPIO
60722 +  print("\nTesting GGPIO\n");
60723 +  set('ggpio','5a5a5a5a');
60724 +  test('ggpio','0x5a5a0000');
60725 +  set('ggpio','a5a5a5a5');
60726 +  test('ggpio','0xa5a50000');
60727 +  set('ggpio','11110000');
60728 +  test('ggpio','0x11110000');
60729 +  set('ggpio','00001111');
60730 +  test('ggpio','0x00000000');
60731 +
60732 +  # Test DEVSPEED
60733 +  print("\nTesting DEVSPEED\n");
60734 +  set('regoffset','800');
60735 +  $old = get('regvalue');
60736 +  set('devspeed','0');
60737 +  test('devspeed','0x0');
60738 +  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
60739 +  set('devspeed','1');
60740 +  test('devspeed','0x1');
60741 +  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
60742 +  set('devspeed','2');
60743 +  test('devspeed','0x2');
60744 +  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2));
60745 +  set('devspeed','3');
60746 +  test('devspeed','0x3');
60747 +  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3));
60748 +  set('devspeed','4');
60749 +  test('devspeed','0x0');
60750 +  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3)));
60751 +  set('devspeed','5');
60752 +  test('devspeed','0x1');
60753 +  test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1));
60754 +
60755 +
60756 +  #  mode      Returns the current mode:0 for device mode1 for host mode       Read
60757 +  #  hnp       Initiate the Host Negotiation Protocol.  Read returns the status.       Read/Write
60758 +  #  srp       Initiate the Session Request Protocol.  Read returns the status.        Read/Write
60759 +  #  buspower  Get or Set the Power State of the bus (0 - Off or 1 - On)       Read/Write
60760 +  #  bussuspend        Suspend the USB bus.    Read/Write
60761 +  #  busconnected      Get the connection status of the bus    Read
60762 +
60763 +  #  gotgctl   Get or set the Core Control Status Register.    Read/Write
60764 +  ##  gusbcfg  Get or set the Core USB Configuration Register  Read/Write
60765 +  #  grxfsiz   Get or set the Receive FIFO Size Register       Read/Write
60766 +  #  gnptxfsiz Get or set the non-periodic Transmit Size Register      Read/Write
60767 +  #  gpvndctl  Get or set the PHY Vendor Control Register      Read/Write
60768 +  ##  ggpio    Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write
60769 +  ##  guid     Get or set the value of the User ID Register    Read/Write
60770 +  ##  gsnpsid  Get the value of the Synopsys ID Regester       Read
60771 +  ##  devspeed Get or set the device speed setting in the DCFG register        Read/Write
60772 +  #  enumspeed Gets the device enumeration Speed.      Read
60773 +  #  hptxfsiz  Get the value of the Host Periodic Transmit FIFO        Read
60774 +  #  hprt0     Get or Set the value in the Host Port Control and Status Register       Read/Write
60775 +
60776 +  test_status("TEST NYI") or die;
60777 +}
60778 +
60779 +test_main();
60780 +0;